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2024-04-26rockchip: rk3308: Move cru and grf include files to arch-rockchipJonas Karlman
Move cru_rk3308.h and grf_rk3308.h to arch-rockchip to match path used for all other Rockchip SoCs. Signed-off-by: Jonas Karlman <[email protected]> Reviewed-by: Kever Yang <[email protected]>
2024-03-15Merge tag 'u-boot-rockchip-20240315' of ↵Tom Rini
https://source.denx.de/u-boot/custodians/u-boot-rockchip into next Please pull the updates for rockchip platform: - Add board: rk3588 Generic, Cool Pi CM5, Theobroma-Systems RK3588 Jaguar SBC, Toybrick TB-RK3588X; rk3588s Cool Pi 4B; rk3566 Pine64 PineTab2; - Add saradc v2 support; - Add PMIC RK806 support; - rk3588 disable force_jtag by default; - Migrate to use IO-domain driver for all boards; - Use common bss and stack addresses for rk33xx and rk35xx boards; - Other updates for driver, config and dts;
2024-03-13ram: k3-ddrss: enable the am62ax's DDR controller for am62pxBryan Brattlof
The am62px family of SoCs uses the same DDR controller as found on the am62ax family. Enable this option when building for the am62px family Reviewed-by: Neha Malcom Francis <[email protected]> Signed-off-by: Bryan Brattlof <[email protected]>
2024-03-13rockchip: include asm/io.h directly in asm/arch-rockchip/hardware.hQuentin Schulz
The different macros use writel which is defined in asm/io.h, so let's include the header so users of hardware.h do not need to include asm/io.h as well. While at it, remove asm/io.h includes wherever asm/arch-rockchip/hardware.h is included already. Cc: Quentin Schulz <[email protected]> Reviewed-by: Kever Yang <[email protected]> Signed-off-by: Quentin Schulz <[email protected]>
2024-03-13rockchip: migrate hardware.h inclusion into appropriate filesQuentin Schulz
hardware.h is only defining macros which are "wrappers" around writel(). writel() is however not available in hardware.h, <asm/io.h> needs to be included. This means in order to use the wrappers in hardware.h, one also needs to include the <asm/io.h> header. However, this cannot be done currently because hardware.h is included in include/configs files, which are implicitly included by every code file by default, which makes the compilation of arch/arm/cpu/armv8/u-boot.lds fail because ALIGN (the ARM assembly directive) got redefined by some of the include files coming from <asm.io.h>. Because nothing in the include/configs file actually use hardware.h, let's remove the inclusion of hardware.h from the include/configs files and explicitly add it wherever it is required. This prepares for the next commit where <asm/io.h> will be included in hardware.h. Cc: Quentin Schulz <[email protected]> Reviewed-by: Kever Yang <[email protected]> Signed-off-by: Quentin Schulz <[email protected]>
2024-03-11Merge tag 'v2024.04-rc4' into nextTom Rini
Prepare v2024.04-rc4
2024-03-04arm: mach-k3: Add basic support for J784S4 SoC definitionApurva Nandan
Add J784S4 initialization files for initial SPL boot. config SYS_K3_MCU_SCRATCHPAD_BASE default value is same for J721E, J721S2, J784S4. So combined them into a single default. Signed-off-by: Hari Nagalla <[email protected]> [ add firewall configurations and change the R5 MCU scratchpad ] Signed-off-by: Manorit Chawdhry <[email protected]> Signed-off-by: Dasnavis Sabiya <[email protected]> Signed-off-by: Apurva Nandan <[email protected]> Reviewed-by: Neha Malcom Francis <[email protected]> Tested-by: Marcel Ziswiler <[email protected]> # AM69-SK
2024-03-02ARM: renesas: Rename ARCH_RMOBILE to ARCH_RENESASMarek Vasut
Rename ARCH_RMOBILE to ARCH_RENESAS because all the chips are made by Renesas, while only a subset of them is from the R-Mobile line. Use the following command to perform the rename: " $ git grep -l 'ARCH_RMOBILE' | xargs -I {} sed -i 's@ARCH_RMOBILE@ARCH_RENESAS@g' {} " Signed-off-by: Marek Vasut <[email protected]> Reviewed-by: Paul Barker <[email protected]>
2024-02-04ram: rockchip: Add rv1126 ddr4 supportTim Lunn
Add support for ddr4 on rv1126. Timing detection files are imported from downstream Rockchip BSP u-boot. Allow selecting ddr4 ram with define CONFIG_RAM_ROCKCHIP_DDR4. Signed-off-by: Tim Lunn <[email protected]> Reviewed-by: Kever Yang <[email protected]>
2023-11-10tree-wide: Replace http:// link with https:// link for ti.comNishanth Menon
Replace instances of http://www.ti.com with https://www.ti.com Signed-off-by: Nishanth Menon <[email protected]>
2023-10-22sunxi: add R528/T113-s3/D1(s) DRAM initialisation codeAndre Przywara
The Allwinner R528/T113-s/D1/D1s SoCs all share the same die, so use the same DRAM initialisation code. Make use of prior art here and lift some code from awboot[1], which carried init code based on earlier decompilation efforts, but with a GPL2 license tag. This code has been heavily reworked and cleaned up, to match previous DRAM routines for other SoCs, and also to be closer to U-Boot's coding style and support routines. The actual DRAM chip timing parameters are included in the main file, since they cover all DRAM types, and are protected by a new Kconfig CONFIG_SUNXI_DRAM_TYPE symbol, which allows the compiler to pick only the relevant settings, at build time. The relevant DRAM chips/board specific configuration parameters are delivered via Kconfig, so this code here should work for all supported SoCs and DRAM chips combinations. Signed-off-by: Andre Przywara <[email protected]> Tested-by: Sam Edwards <[email protected]>
2023-10-22Kconfig: sunxi: prepare for using drivers/ram/sunxiAndre Przywara
At the moment all Allwinner DRAM initialisation routines are stored in arch/arm/mach-sunxi, even though those "drivers" are just a giant collection of writel's, without any architectural dependency. The R528/T113-s SoC (with ARM cores) and the D1/D1s Soc (with RISC-V cores) share the same die, so should share the same DRAM init routines as well. To prepare for this, add a new sunxi directory inside drivers/ram, and add some stub entries to prepare for the addition of the share DRAM code for those SoCs. The RISC-V D1(s) SoCs will probably use SPL_DM, so for that SoC this would be the right directory anyway. Signed-off-by: Andre Przywara <[email protected]>
2023-10-13treewide: use dev_read_addr_*_ptr() where appropriateMatthias Schiffer
A follow-up to commit 842fb5de424e ("drivers: use devfdt_get_addr_size_index_ptr when cast to pointer") and commit 320a1938b6f7 ("drivers: use devfdt_get_addr_index_ptr when cast to pointer"). In addition to using the *_ptr variants of these functions where the address is cast to a pointer, this also changes devfdt_get_addr_*() to dev_read_addr_*() in a few places. Some variable and field types are changed from fdt_addr_t or phys_addr_t to void* where the cast was happening later. This patch fixes a number of compile warnings when building a 32bit U-Boot with CONFIG_PHYS_64BIT=y. In some places, it also fixes error handling where the return value of dev_read_addr() etc. was checked for NULL instead of FDT_ADDR_T_NONE. Signed-off-by: Matthias Schiffer <[email protected]> Reviewed-by: Simon Glass <[email protected]>
2023-10-04Merge tag 'u-boot-stm32-20231004' of ↵Tom Rini
https://source.denx.de/u-boot/custodians/u-boot-stm STM32 MCU: _ alignment with kernel DT v6.5 for stm32f429 and stm32f746 _ rework way of displaying ST logo for stm32f746-disco and stm32f769-disco STM32 MPU: _ alignment with kernel DT v6.6-rc1 _ add RNG support for stm32mp13 _ add USB, USB boot and stm32prog command support for stm32mp13 _ add support of USART1 clock for stm32mp1 _ only print RAM and board code with SPL_DISPLAY_PRINT flag for stm32mp1 _ rename update_sf to dh_update_sd_to_sf and add dh_update_sd_to_emmc for stm32mp15xx DHCOR [ Fix merge conflict at board/st/common/stm32mp_dfu.c ] Signed-off-by: Tom Rini <[email protected]>
2023-10-04ram: stm32mp1: Only print RAM config with CONFIG_SPL_DISPLAY_PRINTHarald Seiler
Ensure that the RAM configuration line is only printed when CONFIG_SPL_DISPLAY_PRINT is set. Signed-off-by: Harald Seiler <[email protected]> Reviewed-by: Patrice Chotard <[email protected]>
2023-09-24common: Drop linux/printk.h from common headerSimon Glass
This old patch was marked as deferred. Bring it back to life, to continue towards the removal of common.h Move this out of the common header and include it only where needed. Signed-off-by: Simon Glass <[email protected]>
2023-08-03board: mediatek: update config headersWeijie Gao
Remove unused information from include/configs/mtxxxx.h Signed-off-by: Weijie Gao <[email protected]>
2023-07-21ram: k3-ddrss: do not touch ctrl regs during trainingBryan Brattlof
During LPDDR initialization we will loop through a series of frequency changes in order to train at the various operating frequencies. During this training, accessing the DRAM_CLASS bitfield could happen during a frequency change and cause the read to hang. Store the DRAM type into the main structure to avoid multiple readings while the independent phy is training. Signed-off-by: Bryan Brattlof <[email protected]>
2023-07-12ram: starfive: Read memory size information from EEPROMYanhong Wang
StarFive VisionFive 2 has two versions, 1.2A and 1.3B, each version of DDR capacity includes 2G/4G/8G, a DT can not support multiple capacities, so the capacity size information is recorded to EEPROM, when DDR initialization required capacity size information is read from EEPROM. If there is no information in EEPROM, it is initialized with the default size defined in DT. Signed-off-by: Yanhong Wang <[email protected]> Reviewed-by: Leo Yu-Chi Liang <[email protected]>
2023-05-13board: schneider: add RZN1 board supportRalph Siemsen
Add support for Schneider Electric RZ/N1D and RZ/N1S boards, which are based on the Reneasas RZ/N1 SoC devices. The intention is to support both boards using a single defconfig, and to handle the differences at runtime. Signed-off-by: Ralph Siemsen <[email protected]> Reviewed-by: Marek Vasut <[email protected]>
2023-05-13ram: cadence: add driver for Cadence EDACRalph Siemsen
Driver for Cadence EDAC DDR controller, as found in the Renesas RZ/N1. Signed-off-by: Ralph Siemsen <[email protected]> Reviewed-by: Marek Vasut <[email protected]>
2023-05-06core: remap: fix regmap_init_mem_plat() reg size handelingJohan Jonker
The fdt_addr_t and phys_addr_t size have been decoupled. A 32bit CPU can expect 64-bit data from the device tree parser, so convert regmap_init_mem_plat() input to handel both. The syscon class driver also makes use of the regmap_init_mem_plat() function, but has no way of knowing the format of the device-specific platform data. In case of odd reg structures other then that the syscon class driver assumes the regmap must be filled in the individual syscon driver before pre-probe. Also fix the ARRAY_SIZE divider in the syscon class driver. Signed-off-by: Johan Jonker <[email protected]> Reviewed-by: Simon Glass <[email protected]>
2023-04-24arm: mach-k3: Remove empty sys_proto.h includeAndrew Davis
This header file is now empty, remove it. Signed-off-by: Andrew Davis <[email protected]> Reviewed-by: Christian Gmeiner <[email protected]>
2023-04-24arm: mach-k3: Move sdelay() and wait_on_value() declarationAndrew Davis
These probably should be in some system wide header given their use. Until then move them out of K3 sys_proto.h so we can finish cleaning that header out. Signed-off-by: Andrew Davis <[email protected]> Reviewed-by: Christian Gmeiner <[email protected]>
2023-04-23Merge tag 'u-boot-rockchip-20230421' of ↵Tom Rini
https://source.denx.de/u-boot/custodians/u-boot-rockchip - Add rk3588 evb support; - Update pinctrl for rk3568 and rk3588; - Update rk3288 dts; - Update mmc support for rk3568 and rk3588; - Add rng support for rk3588; - Add DSI support for rk3568; - Some other misc fixes in dts, config, driver;
2023-04-22Merge https://source.denx.de/u-boot/custodians/u-boot-riscvTom Rini
* Add StarFive VisionFive v2 Board support * Support CONFIG_REMAKE_ELF * Code cleanups for RISC-V architecture
2023-04-21ram: rk3399: add missing high row detectionJonathan Liu
For 2 GB LPDDR4 single-rank RAM with 16 rows, the Rockchip ddr init bin prints: "Bus Width=32 Col=10 Bank=8 Row=16 CS=1 Die Bus-Width=16 Size=2048MB" U-Boot TPL prints: "BW=32 Col=10 Bk=8 CS0 Row=16/15 CS=1 Die BW=16 Size=2048MB" Add missing high row detection so that U-Boot TPL prints Row=16, same as the Rockchip ddr init bin: "BW=32 Col=10 Bk=8 CS0 Row=16 CS=1 Die BW=16 Size=2048MB" Signed-off-by: Jonathan Liu <[email protected]> Reviewed-by: Kever Yang <[email protected]>
2023-04-20ram: starfive: add ddr driverYanhong Wang
Add driver for StarFive JH7110 to support ddr initialization in SPL. Signed-off-by: Yanhong Wang <[email protected]> Tested-by: Conor Dooley <[email protected]>
2023-04-19stm32mp: fix various array bounds checksRasmus Villemoes
In all these cases, the index on the LHS is immediately afterwards used to access the array appearing in the ARRAY_SIZE() on the RHS - so if that index is equal to the array size, we'll access one-past-the-end of the array. Signed-off-by: Rasmus Villemoes <[email protected]> Reviewed-by: Patrice Chotard <[email protected]> Reviewed-by: Patrick Delaunay <[email protected]>
2023-04-03Merge branch 'next'Tom Rini
Signed-off-by: Tom Rini <[email protected]>
2023-04-02rockchip: Fix incorrect constant name in RAM init codeDavid Sebek
A condition in the rk3399 RAM initialization code used the old CONFIG_RAM_RK3399_LPDDR4 constant name. This commit changes the condition to use the correct CONFIG_RAM_ROCKCHIP_LPDDR4 constant. Reviewed-by: Simon Glass <[email protected]>
2023-03-14Merge tag 'v2023.04-rc4' into nextTom Rini
Prepare v2023.04-rc4 Signed-off-by: Tom Rini <[email protected]>
2023-03-06ram: ast2600: Keep MPLL power onDylan Hung
According to the PLL vendor, we should keep the PLL power on, so we shouldn't toggle the power-down bit during PLL initialization. Signed-off-by: Dylan Hung <[email protected]> Reviewed-by: Joel Stanley <[email protected]>
2023-02-28ram: rockchip: Add rk3588 ddr driver supportJagan Teki
Add ddr driver for rk3588 to get the ram capacity. Co-developed-by: Jonas Karlman <[email protected]> Signed-off-by: Jonas Karlman <[email protected]> Signed-off-by: Jagan Teki <[email protected]> Reviewed-by: Kever Yang <[email protected]>
2023-01-20global: Finish CONFIG -> CFG migrationTom Rini
At this point, the remaining places where we have a symbol that is defined as CONFIG_... are in fairly odd locations. While as much dead code has been removed as possible, some of these locations are simply less obvious at first. In other cases, this code is used, but was defined in such a way as to have been missed by earlier checks. Perform a rename of all such remaining symbols to be CFG_... rather than CONFIG_... Signed-off-by: Tom Rini <[email protected]> Reviewed-by: Simon Glass <[email protected]>
2023-01-16ram: rockchip: Add rv1126 lpddr4 supportJagan Teki
Add LPDDR4 detection timings and support for RV1126. Signed-off-by: Jagan Teki <[email protected]> Reviewed-by: Kever Yang <[email protected]>
2023-01-16ram: rockchip: rv1126: Control ddr init prints via DEBUGJagan Teki
Control the ddr init print messages via RAM_ROCKCHIP_DEBUG instead of printing by default. This gives an option to configs to enable these prints or not. Signed-off-by: Jagan Teki <[email protected]> Reviewed-by: Kever Yang <[email protected]>
2023-01-16ram: rockchip: Add rv1126 ddr driver supportJagan Teki
Add DDR driver for Rockchip RV1126 SoC. Signed-off-by: YouMin Chen <[email protected]> Signed-off-by: Jagan Teki <[email protected]> Reviewed-by: Kever Yang <[email protected]>
2023-01-16ram: rockchip: Add rv1126 ddr loader paramsJagan Teki
Add DDR loader parameters for Rockchip RV1126 SoC. Signed-off-by: YouMin Chen <[email protected]> Signed-off-by: Jagan Teki <[email protected]> Reviewed-by: Kever Yang <[email protected]>
2023-01-16ram: rockchip: Add rv1126 ddr3 supportJagan Teki
Add DDR3 detection timings for Rockchip RV1126 SoC. Signed-off-by: YouMin Chen <[email protected]> Signed-off-by: Jagan Teki <[email protected]> Reviewed-by: Kever Yang <[email protected]>
2023-01-16ram: rockchip: Update ddr pctl regs for px30Jagan Teki
Add full ddr pctl registers and bit masks for px30. Signed-off-by: YouMin Chen <[email protected]> Signed-off-by: Jagan Teki <[email protected]> Reviewed-by: Kever Yang <[email protected]>
2023-01-16ram: rockchip: Compute ddr capacity based on grf splitJagan Teki
DDR chip capacity is computed based on GRF split in some Rockchip SoC's like PX30 and RV1126. Add split argument in ddr print info so-that the respective ddr driver will pass the grf split. Signed-off-by: YouMin Chen <[email protected]> Signed-off-by: Jagan Teki <[email protected]> Reviewed-by: Kever Yang <[email protected]>
2023-01-16ram: rockchip: Add common ddr type configsJagan Teki
We have common ddr types in rockchip or in general. So use the common ddr type names instead of per Rockchip SoC to avoid confusion. The respective ddr type names will use on the associated ddr SoC driver as these drivers are built per SoC at a time. Signed-off-by: Jagan Teki <[email protected]> Reviewed-by: Kever Yang <[email protected]>
2023-01-16ram: Mark ram-uclass depend on TPL_DM or SPL_DMJagan Teki
ram-uclass is building irrespective of whether TPL_DM or SPL_DM is enabled. So control the ram uclass build based on TPL/SPL_DM. Signed-off-by: Jagan Teki <[email protected]> Reviewed-by: Kever Yang <[email protected]>
2022-12-22global: Remove unused CONFIG symbolsTom Rini
This removes the following unreferenced CONFIG symbols: CONFIG_FDTADDR CONFIG_FDTFILE CONFIG_FLASH_SECTOR_SIZE CONFIG_FSL_CPLD CONFIG_HDMI_ENCODER_I2C_ADDR CONFIG_I2C_MVTWSI CONFIG_I2C_RTC_ADDR CONFIG_IRAM_END CONFIG_IRAM_SIZE CONFIG_KSNET_MDIO_PHY_CONFIG_ENABLE CONFIG_L1_INIT_RAM CONFIG_MACB_SEARCH_PHY CONFIG_MIU_2BIT_21_7_INTERLEAVED CONFIG_MTD_NAND_VERIFY_WRITE CONFIG_MVGBE_PORTS CONFIG_NETDEV CONFIG_NUM_DSP_CPUS CONFIG_PHY_BASE_ADR CONFIG_PHY_INTERFACE_MODE CONFIG_PSRAM_SCFG CONFIG_RAMBOOT_SPIFLASH CONFIG_RAMBOOT_TEXT_BASE CONFIG_RD_LVL CONFIG_ROCKCHIP_SDHCI_MAX_FREQ CONFIG_SETUP_INITRD_TAG CONFIG_SH_QSPI_BASE CONFIG_SMDK5420 CONFIG_SOCRATES CONFIG_SPI_ADDR CONFIG_SPI_FLASH_QUAD CONFIG_SPI_FLASH_SIZE CONFIG_SPI_HALF_DUPLEX CONFIG_SPI_N25Q256A_RESET CONFIG_TEGRA_SLINK_CTRLS CONFIG_TPM_TIS_BASE_ADDRESS CONFIG_UBOOT_SECTOR_COUNT CONFIG_UBOOT_SECTOR_START CONFIG_VAR_SIZE_SPL CONFIG_VERY_BIG_RAM And also: BL1_SIZE PHY_NO RESERVE_BLOCK_SIZE Signed-off-by: Tom Rini <[email protected]>
2022-12-09ram: k3-ddrss: add am62a controller supportBryan Brattlof
TI's am62a family of SoCs uses a new 32bit DDR controller that shares much of the same functionality with the existing am64 and j721e controllers. Select this controller by default when u-boot is build for the am62a Signed-off-by: Bryan Brattlof <[email protected]> Reviewed-by: Tom Rini <[email protected]>
2022-12-09ram: k3-ddrss: add auto-generated macros for am62a supportBryan Brattlof
The new 32bit DDR controller for TI's am62a family of SoCs shares much of the same functionality with the existing 16bit (am64) and 32bit (j721e) controllers, so this patch reorganizes the existing auto-generated macros for the 16bit and 32bit controllers to make room for the macros for the am62a's controller This patch consists mostly of header/macro renames and additions with a new Kconfig option (K3_AM62A_DDRSS) allowing us to select these new macros during compilation. Signed-off-by: Bryan Brattlof <[email protected]>
2022-12-05global: Move remaining CONFIG_SYS_SDRAM_* to CFG_SYS_SDRAM_*Tom Rini
The rest of the unmigrated CONFIG symbols in the CONFIG_SYS_SDRAM namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <[email protected]> Reviewed-by: Simon Glass <[email protected]>
2022-11-24ram: ast2600: Align the RL and WL settingDylan Hung
Use macro to represent the RL and WL setting to ensure the PHY and controller setting are aligned. Review-by: Ryan Chen <[email protected]> Signed-off-by: Dylan Hung <[email protected]>
2022-11-24ram: ast2600: Improve ddr4 timing and signal qualityDylan Hung
Adjust the following settings to get better timing and signal quality. 1. write DQS/DQ delay - 1e6e2304[0] - 1e6e2304[15:8] 2. read DQS/DQ delay - 0x1e6e0298[0] - 0x1e6e0298[15:8] 3. CLK/CA timing - 0x1e6e01a8[31] 4. Read and write termination - change RTT_ROM from 40 ohm to 48 ohm (MR1[10:8]) - change RTT_PARK from disable to 48 ohm (MR5[8:6]) - change RTT_WR from 120 ohm to disable (MR2[11:9]) - change PHY ODT from 40 ohm to 80 ohm (0x1e6e0130[10:8]) Note1: Both DDR-PHY and DDR controller have their own registers for DDR4 Mode Registers (MR0~MR6). This patch introduces macros to synchronize the MR value on both sides. Note2: the waveform meansurement can be found in item #21 of Aspeed AST26x0 Application note (AP note). Review-by: Ryan Chen <[email protected]> Signed-off-by: Dylan Hung <[email protected]>
generated by cgit v1.3.1 (git 2.54.0) at 2026-07-24 09:16:27 +0000