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2023-02-28ram: rockchip: Add rk3588 ddr driver supportJagan Teki
Add ddr driver for rk3588 to get the ram capacity. Co-developed-by: Jonas Karlman <[email protected]> Signed-off-by: Jonas Karlman <[email protected]> Signed-off-by: Jagan Teki <[email protected]> Reviewed-by: Kever Yang <[email protected]>
2023-01-20global: Finish CONFIG -> CFG migrationTom Rini
At this point, the remaining places where we have a symbol that is defined as CONFIG_... are in fairly odd locations. While as much dead code has been removed as possible, some of these locations are simply less obvious at first. In other cases, this code is used, but was defined in such a way as to have been missed by earlier checks. Perform a rename of all such remaining symbols to be CFG_... rather than CONFIG_... Signed-off-by: Tom Rini <[email protected]> Reviewed-by: Simon Glass <[email protected]>
2023-01-16ram: rockchip: Add rv1126 lpddr4 supportJagan Teki
Add LPDDR4 detection timings and support for RV1126. Signed-off-by: Jagan Teki <[email protected]> Reviewed-by: Kever Yang <[email protected]>
2023-01-16ram: rockchip: rv1126: Control ddr init prints via DEBUGJagan Teki
Control the ddr init print messages via RAM_ROCKCHIP_DEBUG instead of printing by default. This gives an option to configs to enable these prints or not. Signed-off-by: Jagan Teki <[email protected]> Reviewed-by: Kever Yang <[email protected]>
2023-01-16ram: rockchip: Add rv1126 ddr driver supportJagan Teki
Add DDR driver for Rockchip RV1126 SoC. Signed-off-by: YouMin Chen <[email protected]> Signed-off-by: Jagan Teki <[email protected]> Reviewed-by: Kever Yang <[email protected]>
2023-01-16ram: rockchip: Add rv1126 ddr loader paramsJagan Teki
Add DDR loader parameters for Rockchip RV1126 SoC. Signed-off-by: YouMin Chen <[email protected]> Signed-off-by: Jagan Teki <[email protected]> Reviewed-by: Kever Yang <[email protected]>
2023-01-16ram: rockchip: Add rv1126 ddr3 supportJagan Teki
Add DDR3 detection timings for Rockchip RV1126 SoC. Signed-off-by: YouMin Chen <[email protected]> Signed-off-by: Jagan Teki <[email protected]> Reviewed-by: Kever Yang <[email protected]>
2023-01-16ram: rockchip: Update ddr pctl regs for px30Jagan Teki
Add full ddr pctl registers and bit masks for px30. Signed-off-by: YouMin Chen <[email protected]> Signed-off-by: Jagan Teki <[email protected]> Reviewed-by: Kever Yang <[email protected]>
2023-01-16ram: rockchip: Compute ddr capacity based on grf splitJagan Teki
DDR chip capacity is computed based on GRF split in some Rockchip SoC's like PX30 and RV1126. Add split argument in ddr print info so-that the respective ddr driver will pass the grf split. Signed-off-by: YouMin Chen <[email protected]> Signed-off-by: Jagan Teki <[email protected]> Reviewed-by: Kever Yang <[email protected]>
2023-01-16ram: rockchip: Add common ddr type configsJagan Teki
We have common ddr types in rockchip or in general. So use the common ddr type names instead of per Rockchip SoC to avoid confusion. The respective ddr type names will use on the associated ddr SoC driver as these drivers are built per SoC at a time. Signed-off-by: Jagan Teki <[email protected]> Reviewed-by: Kever Yang <[email protected]>
2023-01-16ram: Mark ram-uclass depend on TPL_DM or SPL_DMJagan Teki
ram-uclass is building irrespective of whether TPL_DM or SPL_DM is enabled. So control the ram uclass build based on TPL/SPL_DM. Signed-off-by: Jagan Teki <[email protected]> Reviewed-by: Kever Yang <[email protected]>
2022-12-22global: Remove unused CONFIG symbolsTom Rini
This removes the following unreferenced CONFIG symbols: CONFIG_FDTADDR CONFIG_FDTFILE CONFIG_FLASH_SECTOR_SIZE CONFIG_FSL_CPLD CONFIG_HDMI_ENCODER_I2C_ADDR CONFIG_I2C_MVTWSI CONFIG_I2C_RTC_ADDR CONFIG_IRAM_END CONFIG_IRAM_SIZE CONFIG_KSNET_MDIO_PHY_CONFIG_ENABLE CONFIG_L1_INIT_RAM CONFIG_MACB_SEARCH_PHY CONFIG_MIU_2BIT_21_7_INTERLEAVED CONFIG_MTD_NAND_VERIFY_WRITE CONFIG_MVGBE_PORTS CONFIG_NETDEV CONFIG_NUM_DSP_CPUS CONFIG_PHY_BASE_ADR CONFIG_PHY_INTERFACE_MODE CONFIG_PSRAM_SCFG CONFIG_RAMBOOT_SPIFLASH CONFIG_RAMBOOT_TEXT_BASE CONFIG_RD_LVL CONFIG_ROCKCHIP_SDHCI_MAX_FREQ CONFIG_SETUP_INITRD_TAG CONFIG_SH_QSPI_BASE CONFIG_SMDK5420 CONFIG_SOCRATES CONFIG_SPI_ADDR CONFIG_SPI_FLASH_QUAD CONFIG_SPI_FLASH_SIZE CONFIG_SPI_HALF_DUPLEX CONFIG_SPI_N25Q256A_RESET CONFIG_TEGRA_SLINK_CTRLS CONFIG_TPM_TIS_BASE_ADDRESS CONFIG_UBOOT_SECTOR_COUNT CONFIG_UBOOT_SECTOR_START CONFIG_VAR_SIZE_SPL CONFIG_VERY_BIG_RAM And also: BL1_SIZE PHY_NO RESERVE_BLOCK_SIZE Signed-off-by: Tom Rini <[email protected]>
2022-12-09ram: k3-ddrss: add am62a controller supportBryan Brattlof
TI's am62a family of SoCs uses a new 32bit DDR controller that shares much of the same functionality with the existing am64 and j721e controllers. Select this controller by default when u-boot is build for the am62a Signed-off-by: Bryan Brattlof <[email protected]> Reviewed-by: Tom Rini <[email protected]>
2022-12-09ram: k3-ddrss: add auto-generated macros for am62a supportBryan Brattlof
The new 32bit DDR controller for TI's am62a family of SoCs shares much of the same functionality with the existing 16bit (am64) and 32bit (j721e) controllers, so this patch reorganizes the existing auto-generated macros for the 16bit and 32bit controllers to make room for the macros for the am62a's controller This patch consists mostly of header/macro renames and additions with a new Kconfig option (K3_AM62A_DDRSS) allowing us to select these new macros during compilation. Signed-off-by: Bryan Brattlof <[email protected]>
2022-12-05global: Move remaining CONFIG_SYS_SDRAM_* to CFG_SYS_SDRAM_*Tom Rini
The rest of the unmigrated CONFIG symbols in the CONFIG_SYS_SDRAM namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <[email protected]> Reviewed-by: Simon Glass <[email protected]>
2022-11-24ram: ast2600: Align the RL and WL settingDylan Hung
Use macro to represent the RL and WL setting to ensure the PHY and controller setting are aligned. Review-by: Ryan Chen <[email protected]> Signed-off-by: Dylan Hung <[email protected]>
2022-11-24ram: ast2600: Improve ddr4 timing and signal qualityDylan Hung
Adjust the following settings to get better timing and signal quality. 1. write DQS/DQ delay - 1e6e2304[0] - 1e6e2304[15:8] 2. read DQS/DQ delay - 0x1e6e0298[0] - 0x1e6e0298[15:8] 3. CLK/CA timing - 0x1e6e01a8[31] 4. Read and write termination - change RTT_ROM from 40 ohm to 48 ohm (MR1[10:8]) - change RTT_PARK from disable to 48 ohm (MR5[8:6]) - change RTT_WR from 120 ohm to disable (MR2[11:9]) - change PHY ODT from 40 ohm to 80 ohm (0x1e6e0130[10:8]) Note1: Both DDR-PHY and DDR controller have their own registers for DDR4 Mode Registers (MR0~MR6). This patch introduces macros to synchronize the MR value on both sides. Note2: the waveform meansurement can be found in item #21 of Aspeed AST26x0 Application note (AP note). Review-by: Ryan Chen <[email protected]> Signed-off-by: Dylan Hung <[email protected]>
2022-11-24ram: ast2600: Fix incorrect statement of the register pollingDylan Hung
The condition "~data" in the if-statement is a typo. The original intention is to poll if SDRAM_PHYCTRL0_INIT bit equals to 0. So use "data == 0" for instead. Besides, the bit[1] of "phy_status" register is hardwired to SDRAM_PHYCTRL0_INIT (with inverse logic). Since SDRAM_PHYCTRL0_INIT has already done, remove the unnecessary checking of phy_status[1]. Fixes: fde93143469f ("ram: aspeed: Add AST2600 DRAM control support") Review-by: Ryan Chen <[email protected]> Signed-off-by: Dylan Hung <[email protected]>
2022-10-19ram: rockchip: fix typo in KConfig option labelQuentin Schulz
RAM_PX30_DDR4 is for DDR4 support and not DDR3 so let's fix the typo. Fixes: 2db36c64bd5a ("ram: rockchip: px30: add a config-based ddr selection") Cc: Quentin Schulz <[email protected]> Signed-off-by: Quentin Schulz <[email protected]> Reviewed-by: Kever Yang <[email protected]>
2022-09-19Merge branch 'master' into nextTom Rini
Signed-off-by: Tom Rini <[email protected]>
2022-09-18RAM: Add changes for i.MXRT11xx seriesJesse Taube
The i.MXRT11 series has different offsets for IOCR_MUX, it also can address 64MiB of SDRAM so add a macro for that. Signed-off-by: Jesse Taube <[email protected]>
2022-09-18cyclic: Use schedule() instead of WATCHDOG_RESET()Stefan Roese
Globally replace all occurances of WATCHDOG_RESET() with schedule(), which handles the HW_WATCHDOG functionality and the cyclic infrastructure. Signed-off-by: Stefan Roese <[email protected]> Reviewed-by: Simon Glass <[email protected]> Tested-by: Tom Rini <[email protected]> [am335x_evm, mx6cuboxi, rpi_3,dra7xx_evm, pine64_plus, am65x_evm, j721e_evm]
2022-09-04ram: rk3399: Conduct memory training at 400MHzLee Jones
Currently the default initialisation frequency is 50MHz. Although this does appear to be suitable for some LPDDR4 RAM chips, training at this low frequency has been seen to cause Column errors, leading to Capacity check errors on others. Here we force RAM initialisation to happen at 400MHz before ramping up to the final value running value of 800MHz after everything has been successfully configured. Link: https://lore.kernel.org/u-boot/[email protected]/ Suggested-by: YouMin Chen <[email protected]> Signed-off-by: Lee Jones <[email protected]> Tested-by: Xavier Drudis Ferran <[email protected]> Reviewed-by: Kever Yang <[email protected]> Tested-by: Michal Suchánek <[email protected]>
2022-09-04ram: rk3399: Fix faulty frequency change reportsLee Jones
Frequency changes to 400MHz are presently reported as: lpddr4_set_rate_0: change freq to 400000000 mhz 0, 1 This is obviously wrong by 6 orders of magnitude. Ensure frequency changes are reported accurately. Signed-off-by: Lee Jones <[email protected]> Tested-by: Xavier Drudis Ferran <[email protected]> Reviewed-by: Kever Yang <[email protected]>
2022-09-04ram: rk3399: Fix .set_rate_index() error handlingLee Jones
Functions pointed to by this op pointer can return non-zero values indicating an error. Ensure any error value is propagated back up the call-chain. Signed-off-by: Lee Jones <[email protected]> Tested-by: Xavier Drudis Ferran <[email protected]> Reviewed-by: Kever Yang <[email protected]>
2022-09-04drivers: ram: rockchip: Fix dram channels calculation for rk3399Han Pengfei
Only add the dram channel when we finally setup it successfully at the last step. Signed-off-by: Han Pengfei <[email protected]> Reviewed-by: Kever Yang <[email protected]>
2022-07-25arm: mach-k3: Rename SOC_K3_AM6 to SOC_K3_AM654Andrew Davis
The first AM6x device was the AM654x, but being the first we named it just AM6, since more devices have come out with this same prefix we should switch it to the normal convention of using the full name of the first compatibility device the series. This makes what device we are talking about more clear and matches all the K3 devices added since. Signed-off-by: Andrew Davis <[email protected]> Reviewed-by: Tom Rini <[email protected]>
2022-06-28tpl: Ensure all TPL symbols in Kconfig have some TPL dependencyTom Rini
Tighten up symbol dependencies in a number of places. Ensure that a TPL specific option has at least a direct dependency on TPL. In places where it's clear that we depend on something more specific, use that dependency instead. Reported-by: Pali Rohár <[email protected]> Signed-off-by: Tom Rini <[email protected]>
2022-06-17ram: stm32mp1: add support of STM32MP13xPatrick Delaunay
Add support for new compatible "st,stm32mp13-ddr" to manage the DDR sub system (Controller and PHY) in STM32MP13x SOC: - only one AXI port - support of 16 port output (MEMC_DRAM_DATA_WIDTH = 2) The STM32MP15x SOC have 2 AXI ports and 32 bits support. Signed-off-by: Patrick Delaunay <[email protected]> Reviewed-by: Patrice Chotard <[email protected]>
2022-06-10arm: mach-k3: Introduce the basic files to support AM62Suman Anna
The AM62 SoC family is the follow on AM335x built on K3 Multicore SoC architecture platform, providing ultra-low-power modes, dual display, multi-sensor edge compute, security and other BOM-saving integration. The AM62 SoC targets broad market to enable applications such as Industrial HMI, PLC/CNC/Robot control, Medical Equipment, Building Automation, Appliances and more. Some highlights of this SoC are: * Quad-Cortex-A53s (running up to 1.4GHz) in a single cluster. Pin-to-pin compatible options for single and quad core are available. * Cortex-M4F for general-purpose or safety usage. * Dual display support, providing 24-bit RBG parallel interface and OLDI/LVDS-4 Lane x2, up to 200MHz pixel clock support for 2K display resolution. * Selectable GPUsupport, up to 8GFLOPS, providing better user experience in 3D graphic display case and Android. * PRU(Programmable Realtime Unit) support for customized programmable interfaces/IOs. * Integrated Giga-bit Ethernet switch supporting up to a total of two external ports (TSN capable). * 9xUARTs, 5xSPI, 6xI2C, 2xUSB2, 3xCAN-FD, 3x eMMC and SD, GPMC for NAND/FPGA connection, OSPI memory controller, 3xMcASP for audio, 1x CSI-RX-4L for Camera, eCAP/eQEP, ePWM, among other peripherals. * Dedicated Centralized System Controller for Security, Power, and Resource Management. * Multiple low power modes support, ex: Deep sleep,Standby, MCU-only, enabling battery powered system design. AM625 is the first device of the family. Add DT bindings for the same. More details can be found in the Technical Reference Manual: https://www.ti.com/lit/pdf/spruiv7 Signed-off-by: Suman Anna <[email protected]> Signed-off-by: Gowtham Tammana <[email protected]> Signed-off-by: Aswath Govindraju <[email protected]> Signed-off-by: Nishanth Menon <[email protected]> Signed-off-by: Vignesh Raghavendra <[email protected]> Reviewed-by: Tom Rini <[email protected]>
2022-05-10ram: stm32mp1: Conditionally enable ASRMarek Vasut
Enable DRAM ASR, auto self-refresh, conditionally, based on DT PWRCTL register bits. While ASR does save considerable amount of power at runtime automatically, it also causes LTDC underruns on large panels. Let user select whether or not ASR is required or not, generally ASR should be enabled on portable and battery operated devices. Signed-off-by: Marek Vasut <[email protected]> Cc: Patrick Delaunay <[email protected]> Cc: Patrice Chotard <[email protected]> Reviewed-by: Patrick Delaunay <[email protected]> Signed-off-by: Patrice Chotard <[email protected]>
2022-04-20ram: k3-ddrss: Allow use of dt provided initial frequencyDave Gerlach
Allow device tree to provide ti,ddr-freq0 to be used as the initial DDR frequency that is set for lpddr4 before initialization of the controller. Make this optional and continue to use PLL bypass frequency as is done currently if ti,ddr-freq0 is not provided. Signed-off-by: Dave Gerlach <[email protected]>
2022-04-20ram: k3-ddrss: Fix register name and explain its usageDominic Rath
The k3-ddrss driver wants to configure the DDRSS_V2A_CTL_REG to reflect the maximum possible SDRAM of 2 GB for AM64x (instead of the register's default that says 8 GB, which the AM64x DDR controller wouldn't support). The offset 0x20 was correct, but the register name DDRSS_V2A_R1_MAT_REG was that of the next register at offset 0x24. Signed-off-by: Dominic Rath <[email protected]>
2022-04-18rockchip: rk3066: add sdram driverPaweł Jarosz
Add rockchip rk3066 sdram driver Signed-off-by: Paweł Jarosz <[email protected]> Signed-off-by: Johan Jonker <[email protected]> Reviewed-by: Kever Yang <[email protected]>
2022-04-04ram: k3-am654: Make VTT regulator optionalChristian Gmeiner
Signed-off-by: Christian Gmeiner <[email protected]>
2022-04-04ram: k3-am654: Write all configuration valuesDominic Rath
Makes it possible to use 16-bit DDR memory. Signed-off-by: Dominic Rath <[email protected]> Signed-off-by: Christian Gmeiner <[email protected]>
2022-04-04ram: k3-ddrss: Introduce ECC Functionality for full memory spaceDave Gerlach
Introduce ECC Functionality for full memory space as implemented in the DDRSS. The following is done to accomplish this: * Introduce a memory region "ss" to allow dt to provide DDRSS region, which is not the same as "ctl" which is the controller region. * Introduce a "ti,ecc-enable" flag which allows a memorycontroller instance to enable ecc. * Introduce functionality to properly program the DDRSS registers to enable ECC for the full DDR memory space if enabled with above flag. * Expose a k3_ddrss_ddr_fdt_fixup call to allow fixup of fdt blob to account from DDR memory that must be reserved for ECC operation. Signed-off-by: Dave Gerlach <[email protected]>
2022-04-04ram: k3-ddrss: Rename ddrss_ss_regs to ddrss_ctl_regsDave Gerlach
The current address being read from dt actually represents the ddrss_ctl memory region, while ddrss_ss region is something else. Introduce ddrss_ctl_regs and use it to free up ddrss_ss_regs for its proper purpose later so that we can avoid confusion. Signed-off-by: Dave Gerlach <[email protected]>
2022-03-28Merge tag 'v2022.04-rc5' into nextTom Rini
Prepare v2022.04-rc5
2022-03-18rockchip: ram: sdram_rk3x88: replace comma by semicolonJohan Jonker
A comma at the end of a line gives sometimes strange effects in combination with some code formatters, so replace a comma by a semicolon in the sdram_rk3188.c and sdram_rk3288.c files. Signed-off-by: Johan Jonker <[email protected]> Reviewed-by: Simon Glass <[email protected]> Reviewed-by: Jagan Teki <[email protected]> Reviewed-by: Kever Yang <[email protected]>
2022-03-15ram: stm32mp1: Unconditionally enable ASRMarek Vasut
Enable DRAM ASR, auto self-refresh, unconditionally. This saves non-trivial amount of power both at runtime and in suspend (on 2x W632GU6NB-15 ~150mW). Reviewed-by: Patrice Chotard <[email protected]> Signed-off-by: Marek Vasut <[email protected]> Cc: Patrick Delaunay <[email protected]> Cc: Patrice Chotard <[email protected]>
2022-03-10ram: aspeed: Rework kconfig optionsJoel Stanley
Ensure the ASPEED related options are grouped together under the RAM option when enabling support. This also makes some minor grammar corrections and renames options so they present cleanly in menuconfig. There should be no functional change to the configuration or binary. Signed-off-by: Joel Stanley <[email protected]> Reviewed-by: Dylan Hung <[email protected]>
2022-02-08ram: k3-ddrss: Add support for J721S2 SoCDavid Huang
Add support for DDR subsystem in J721S2 SoC. Signed-off-by: David Huang <[email protected]> Signed-off-by: Aswath Govindraju <[email protected]>
2022-02-08ram: k3-ddrss: Add support for configuring MSMC subsystem in case of ↵Aswath Govindraju
Multiple DDR subsystems In Multi DDR subystems with interleaving support, the following needs to configured, - interleaving granular size and region - EMIFs to be enabled - EMIFs with ecc to be enabled - EMIF separated or interleaved - number of cycles of unsuccessful EMIF arbitration to wait before arbitrating for a different EMIF port, by default set to 3 Add support for configuring all the above by using a MSMC device Signed-off-by: Aswath Govindraju <[email protected]>
2022-02-08ram: k3-ddrss: Add support for multiple instances of DDR subsystemsAswath Govindraju
The current driver only supports single instance of DRR subsystem. Add support for probing multiple instances of DDR subsystem. Signed-off-by: Aswath Govindraju <[email protected]>
2022-02-08ram: k3-ddrss: lpddr4_structs_if.h: Add a pointer to ddr instanceAswath Govindraju
Add a pointer to ddr instance int the lpddr4_privatedata_s structure for supporting mutliple instances of DDR in the drivers. Signed-off-by: Aswath Govindraju <[email protected]>
2022-01-20drivers: octeon: get rid of Unicode in codeHeinrich Schuchardt
Placing Unicode control codes <U+0080><U+0093> in the middle of a comment does not make much sense. Let's get rid of all Unicode in drivers/ram/octeon/octeon3_lmc.c. Signed-off-by: Heinrich Schuchardt <[email protected]> Reviewed-by: Stefan Roese <[email protected]>
2021-11-30ram: stm32mp1: remove __maybe_unused on stm32mp1_ddr_setupPatrick Delaunay
Since the commit f42045b2e750 ("stm32mp15: replace CONFIG_TFABOOT when it is possible") the function stm32mp1_ddr_setup is always called so the __maybe_unused can be removed. Signed-off-by: Patrick Delaunay <[email protected]> Reviewed-by: Patrice Chotard <[email protected]>
2021-11-30ram: stm32mp1: compute DDR size from DDRCTL registersPatrick Delaunay
Compute the DDR size from DDR controller register (mstr and addrmap) in U-Boot proper as the DDR information are useful only for SPL but not for U-Boot proper, for example with TFABOOT. This patch simplify U-Boot DT when several DDR size are supported and support of next SOC in STM32MP family. Signed-off-by: Patrick Delaunay <[email protected]> Signed-off-by: Patrick Delaunay <[email protected]>
2021-11-30stm32mp1: ram: remove tuning supportPatrick Delaunay
Remove the DDR interactive command tuning, as the support of a predefined DDR PHY tuning is removed for STM32MP1 driver in SPL and in TF-A and the result of this tuning will be never used. Moreover this SW tuning procedure can failed on some hardware configuration (to many BIST errors and no convergence); it will be no more supported in the next delivery of the DDR utilities included in the CubeMX tool of STMicroelectronics. Signed-off-by: Patrick Delaunay <[email protected]> Reviewed-by: Patrice Chotard <[email protected]>
generated by cgit v1.3.1 (git 2.54.0) at 2026-06-01 13:58:27 +0000