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This commit fixes the change of below commit
"spi: fsl_qspi: Use GENMASK"
(sha1 :bad490a24212c068c5b718b9189f47ea4075d078)
Signed-off-by: Gong Qianyu <[email protected]>
Reviewed-by: Jagan Teki <[email protected]>
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When the Zynq Boot ROM code loads the payload from QSPI it uses the
LQSPI feature of the QSPI device, however it does not clean up its
configuration before handing over to the payload which leaves the device
confgured to by-pass the standard non-linear operating mode.
This ensures the Linear QSPI mode is disabled before re-enabling the
device.
Signed-off-by: Nathan Rossi <[email protected]>
Cc: Jagan Teki <[email protected]>
Cc: Siva Durga Prasad Paladugu <[email protected]>
Cc: Simon Glass <[email protected]>
Signed-off-by: Michal Simek <[email protected]>
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When reading a large blob. e.g. a linux kernel (several MiBs) a watchdog
timeout might occur meanwhile. So pet the watchdog while operating on
the flash.
Signed-off-by: Alexander Stein <[email protected]>
Reviewed-by: York Sun <[email protected]>
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Add xlnx,xps-spi-2.00.a/b which is compatible string
listed in the Linux kernel.
Remove origin one which has no real background.
Signed-off-by: Michal Simek <[email protected]>
Reviewed-by: Jagan Teki <[email protected]>
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ZynqMP is using different symbol.
Use correct one.
Reviewed-by: Jagan Teki <[email protected]>
Signed-off-by: Michal Simek <[email protected]>
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Extend compatible list table for cdns,spi-r1p6 compatible string.
Reviewed-by: Jagan Teki <[email protected]>
Signed-off-by: Michal Simek <[email protected]>
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SPI_3WIRE is spi mode not spi flags, so this patch fixed
the spi-3wire checking throgh mode instead of flags.
Cc: Mugunthan V N <[email protected]>
Acked-by: Simon Glass <[email protected]>
Signed-off-by: Jagan Teki <[email protected]>
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spi-3wire is used when SI/SO signals shared so get
the same from dts node and assign to mode on slave
plat->mode.
Acked-by: Simon Glass <[email protected]>
Signed-off-by: Jagan Teki <[email protected]>
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The console includes a global variable and several functions that are only
used by a small subset of U-Boot files. Before adding more functions, move
the definitions into their own header file.
Signed-off-by: Simon Glass <[email protected]>
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It is follow up patch based on
"dm: Add support for all targets which requires MANUAL_RELOC"
(sha1: 484fdf5ba058b07be5ca82763aa2b72063540ef3)
to update function pointers for DM.
Signed-off-by: Michal Simek <[email protected]>
Acked-by: Simon Glass <[email protected]>
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Change ioremap() to map_physmem(), as it is more used in u-boot.
Signed-off-by: Thomas Chou <[email protected]>
Reviewed-by: Marek Vasut <[email protected]>
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Add dummy readl after invalidating cmd field of QSPI_CMD_REG to ensure
bus sync. Without this device's CS is not deactivated reliably leading
to failure to enumerate flash or failure to set quad enable bit on
Macronix flash present on am437x-sk and am437x-idk evms.
Signed-off-by: Vignesh R <[email protected]>
Reviewed-by: Mugunthan V N <[email protected]>
Reviewed-by: Jagan Teki <[email protected]>
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This is the normal Tegra SPI driver modified to work with the
QSPI controller in Tegra210. It does not do 2x/4x transfers
or any other QSPI protocol.
Signed-off-by: Yen Lin <[email protected]>
Signed-off-by: Tom Warren <[email protected]>
Reviewed-by: Jagan Teki <[email protected]>
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- Remove the penultimate comma in of_match ids
Signed-off-by: Thomas Chou <[email protected]>
Reviewed-by: Jagan Teki <[email protected]>
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Ensure the intended SCLK frequency not exceeding the maximum
frequency. If that happen, SCLK will set to maximum frequency.
Signed-off-by: Chin Liang See <[email protected]>
Cc: Dinh Nguyen <[email protected]>
Cc: Dinh Nguyen <[email protected]>
Cc: Marek Vasut <[email protected]>
Cc: Stefan Roese <[email protected]>
Cc: Vikas Manocha <[email protected]>
Cc: Jagannadh Teki <[email protected]>
Cc: Pavel Machek <[email protected]>
Acked-by: Pavel Machek <[email protected]>
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Fix the fdt read for spi-max-frequency as it's contained
in the child node. Current state of code is always
returning default value.
Signed-off-by: Chin Liang See <[email protected]>
Cc: Dinh Nguyen <[email protected]>
Cc: Dinh Nguyen <[email protected]>
Cc: Marek Vasut <[email protected]>
Cc: Stefan Roese <[email protected]>
Cc: Vikas Manocha <[email protected]>
Cc: Jagannadh Teki <[email protected]>
Cc: Pavel Machek <[email protected]>
Acked-by: Marek Vasut <[email protected]>
Acked-by: Pavel Machek <[email protected]>
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Ensuring spi_calibration is run when there is a change of sclk
frequency. This will ensure the qspi flash access works for high
sclk frequency
Signed-off-by: Chin Liang See <[email protected]>
Cc: Dinh Nguyen <[email protected]>
Cc: Dinh Nguyen <[email protected]>
Cc: Marek Vasut <[email protected]>
Cc: Stefan Roese <[email protected]>
Cc: Vikas Manocha <[email protected]>
Cc: Jagannadh Teki <[email protected]>
Cc: Pavel Machek <[email protected]>
Acked-by: Marek Vasut <[email protected]>
Reviewed-by: Jagan Teki <[email protected]>
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- Moved macro definitions to top
- Give tab space to CONFIG_ALTERA_SPI_IDLE_VAL value
- Re-arrange header includes ascending order
Acked-by: Thomas Chou <[email protected]>
Signed-off-by: Jagan Teki <[email protected]>
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Replace numerical bit shift with BIT macro
in altera_spi
:%s/(1 << nr)/BIT(nr)/g
where nr = 0, 1, 2 .... 31
Cc: Marek Vasut <[email protected]>
Acked-by: Thomas Chou <[email protected]>
Reviewed-by: Tom Rini <[email protected]>
Signed-off-by: Jagan Teki <[email protected]>
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Replace numeric mask hexcodes with GENMASK macro
in xilinx_spi
Cc: Michal Simek <[email protected]>
Signed-off-by: Jagan Teki <[email protected]>
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Replace numeric mask hexcodes with GENMASK macro
in tegra*.c
Cc: Stephen Warren <[email protected]>
Cc: Tom Warren <[email protected]>
Signed-off-by: Jagan Teki <[email protected]>
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Replace numeric mask hexcodes with GENMASK macro
in omap3_spi
Cc: Nikita Kiryanov <[email protected]>
Reviewed-by: Tom Rini <[email protected]>
Signed-off-by: Jagan Teki <[email protected]>
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Replace numeric mask hexcodes with GENMASK macro
in fsl_qspi
Cc: York Sun <[email protected]>
Cc: Haikun Wang <[email protected]>
Signed-off-by: Jagan Teki <[email protected]>
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Replace numeric mask hexcodes with GENMASK macro
in designware_spi
Cc: Stefan Roese <[email protected]>
Cc: Marek Vasut <[email protected]>
Reviewed-by: Tom Rini <[email protected]>
Signed-off-by: Jagan Teki <[email protected]>
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Replace numeric mask hexcodes with GENMASK macro
in atmel_spi
Cc: Bo Shen <[email protected]>
Reviewed-by: Tom Rini <[email protected]>
Signed-off-by: Jagan Teki <[email protected]>
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Replace numerical bit shift with BIT macro
in xilinx_spi
:%s/(1 << nr)/BIT(nr)/g
where nr = 0, 1, 2 .... 31
Cc: Michal Simek <[email protected]>
Reviewed-by: Tom Rini <[email protected]>
Signed-off-by: Jagan Teki <[email protected]>
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Replace numerical bit shift with BIT macro
in ti_qspi
:%s/(1 << nr)/BIT(nr)/g
where nr = 0, 1, 2 .... 31
Reviewed-by: Vignesh R <[email protected]>
Reviewed-by: Tom Rini <[email protected]>
Signed-off-by: Jagan Teki <[email protected]>
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Replace numerical bit shift with BIT macro
in tegra*.c
:%s/(1 << nr)/BIT(nr)/g
where nr = 0, 1, 2 .... 31
Cc: Stephen Warren <[email protected]>
Cc: Tom Warren <[email protected]>
Reviewed-by: Tom Rini <[email protected]>
Signed-off-by: Jagan Teki <[email protected]>
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Replace numerical bit shift with BIT macro
in sh_qspi
:%s/(1 << nr)/BIT(nr)/g
where nr = 0, 1, 2 .... 31
Cc: Nobuhiro Iwamatsu <[email protected]>
Reviewed-by: Tom Rini <[email protected]>
Signed-off-by: Jagan Teki <[email protected]>
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Replace numerical bit shift with BIT macro
in omap3_spi
:%s/(1 << nr)/BIT(nr)/g
where nr = 0, 1, 2 .... 31
Cc: Nikita Kiryanov <[email protected]>
Reviewed-by: Tom Rini <[email protected]>
Signed-off-by: Jagan Teki <[email protected]>
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Replace numerical bit shift with BIT macro
in mpc8xxx_spi
:%s/(1 << nr)/BIT(nr)/g
where nr = 0, 1, 2 .... 31
Reviewed-by: Tom Rini <[email protected]>
Signed-off-by: Jagan Teki <[email protected]>
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Replace numerical bit shift with BIT macro
in ich
:%s/(1 << nr)/BIT(nr)/g
where nr = 0, 1, 2 .... 31
Reviewed-by: Simon Glass <[email protected]>
Reviewed-by: Tom Rini <[email protected]>
Signed-off-by: Jagan Teki <[email protected]>
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Replace numerical bit shift with BIT macro
in fsl_*spi.c
:%s/(1 << nr)/BIT(nr)/g
where nr = 0, 1, 2 .... 31
Cc: York Sun <[email protected]>
Cc: Haikun Wang <[email protected]>
Reviewed-by: Tom Rini <[email protected]>
Signed-off-by: Jagan Teki <[email protected]>
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Replace numerical bit shift with BIT macro
in designware_spi
:%s/(1 << nr)/BIT(nr)/g
where nr = 0, 1, 2 .... 31
Cc: Stefan Roese <[email protected]>
Cc: Marek Vasut <[email protected]>
Reviewed-by: Tom Rini <[email protected]>
Signed-off-by: Jagan Teki <[email protected]>
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Replace numerical bit shift with BIT macro
in cadence_qspi_apb
:%s/(1 << nr)/BIT(nr)/g
where nr = 0, 1, 2 .... 31
Cc: Stefan Roese <[email protected]>
Cc: Marek Vasut <[email protected]>
Acked-by: Vikas Manocha <[email protected]>
Reviewed-by: Tom Rini <[email protected]>
Signed-off-by: Jagan Teki <[email protected]>
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Replace numerical bit shift with BIT macro
in bfin_spi6xx
:%s/(1 << nr)/BIT(nr)/g
where nr = 0, 1, 2 .... 31
Reviewed-by: Tom Rini <[email protected]>
Signed-off-by: Jagan Teki <[email protected]>
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Replace numerical bit shift with BIT macro
in atmel_spi
:%s/(1 << nr)/BIT(nr)/g
where nr = 0, 1, 2 .... 31
Cc: Bo Shen <[email protected]>
Reviewed-by: Tom Rini <[email protected]>
Signed-off-by: Jagan Teki <[email protected]>
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GENMASK macro used on zynq_spi.c and zynq_qspi.c
GENMASK is used to create a contiguous bitmask([hi:lo]).
Ex: (0x7 << 3) => GENMASK(5, 3)
Cc: Michal Simek <[email protected]>
Acked-by: Siva Durga Prasad Paladugu <[email protected]>
Signed-off-by: Jagan Teki <[email protected]>
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Used BIT macro on zynq_spi.c and zynq_qspi.c
:%s/(1 << nr)/BIT(nr)/g
where nr = 0, 1, 2 .... 31
Cc: Michal Simek <[email protected]>
Acked-by: Siva Durga Prasad Paladugu <[email protected]>
Reviewed-by: Tom Rini <[email protected]>
Signed-off-by: Jagan Teki <[email protected]>
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- Use __func__ on debug
- Removed unnecessary comment
- Fix function name in debug as zynq_qspi_xfer instead of spi_xfer
Signed-off-by: Jagan Teki <[email protected]>
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- Removed unneeded inclusion of header files
- Add "Xilinx" on license text
Cc: Michal Simek <[email protected]>
Cc: Siva Durga Prasad Paladugu <[email protected]>
Signed-off-by: Jagan Teki <[email protected]>
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priv->mode is initialized when .set_speed triggers
with mode value, so checking mode for configuring
CPOL, CPHA using priv->mode is invalid hence use
mode from .set_speed argument, and at the end
priv->mode will initialized with mode.
This patch also replaces formatting string to use
speed instead of mode in .set_speed ops.
Signed-off-by: Jagan Teki <[email protected]>
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Store cs value into private data and use it while activating
chipselect instead of passing through function.
Signed-off-by: Jagan Teki <[email protected]>
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Rename ZYNQ_SPI_CR_BRD_MASK to ZYNQ_SPI_CR_BAUD_MASK
for more readable.
Signed-off-by: Jagan Teki <[email protected]>
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Update the numerical values for baudrate and chipselect
with config reg shift named macro's
Signed-off-by: Jagan Teki <[email protected]>
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Add Zynq QSPI controller Kconfig entry.
Signed-off-by: Jagan Teki <[email protected]>
Reviewed-by: Simon Glass <[email protected]>
Acked-by: Michal Simek <[email protected]>
Cc: Siva Durga Prasad Paladugu <[email protected]>
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Added zynq qspi controller driver for Xilinx Zynq APSOC,
this driver is driver-model driven with devicetree support.
=> sf probe
SF: Detected S25FL128S_64K with page size 256 Bytes, erase size 64 KiB, total 16 MiB
=> mw.b 0x100 0xCC 0x1000000
=> sf update 0x100 0x0 0x1000000
device 0 whole chip
16777216 bytes written, 0 bytes skipped in 59.842s, speed 289262 B/s
=> sf read 0x3000000 0x0 0x1000000
device 0 whole chip
SF: 16777216 bytes @ 0x0 Read: OK
=> cmp.b 0x3000000 0x100 0x1000000
Total of 16777216 byte(s) were the same
Signed-off-by: Jagan Teki <[email protected]>
Reviewed-by: Simon Glass <[email protected]>
Cc: Michal Simek <[email protected]>
Acked-by: Siva Durga Prasad Paladugu <[email protected]>
Tested-by: Jagan Teki <[email protected]>
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