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Add the Kconfig entry for SOFT_SPI which uses gpio to simulate the
SPI signals. We use it for accessing 74x164 on some i.MX boards.
Signed-off-by: Peng Fan <[email protected]>
Cc: Jagan Teki <[email protected]>
Cc: Stefano Babic <[email protected]>
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This patch adds a remove function to the Intel ICH SPI driver, that will
be called upon U-Boot exit, directly before the OS (Linux) is started.
This function takes care of configuring the BIOS registers in the SPI
controller (similar to what a "standard" BIOS or coreboot does), so that
the Linux MTD device driver is able to correctly read/write to the SPI
NOR chip. Without this, the chip is not detected at all.
Signed-off-by: Stefan Roese <[email protected]>
Reviewed-by: Simon Glass <[email protected]>
Cc: Bin Meng <[email protected]>
Cc: Jagan Teki <[email protected]>
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This particular quirk is not enabled in any config files today. It does
however exist and is handled correctly in device trees and via
CONFIG_DM_SPI. So we drop the symbol now and add a comment to indicate
that any (new) boards that require this quirk need to enable DM_SPI
instead.
Signed-off-by: Tom Rini <[email protected]>
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The existing Rockchip SPI (rk_spi.c) driver also matches the hardware
block found in the RK3399. This has been confirmed both with SPI NOR
flashes and general SPI transfers on the RK3399-Q7 for SPI1 and SPI5.
This change adds the 'rockchip,rk3399-spi' string to its compatible
list to allow reuse of the existing driver.
X-AffectedPlatforms: RK3399-Q7
Signed-off-by: Philipp Tomsich <[email protected]>
Tested-by: Jakob Unterwurzacher <[email protected]>
Acked-by: Simon Glass <[email protected]>
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The baudrate in rkspi was calculated by using an integer division
(which implicitly discarded any fractional result), then rounding to
an even number and finally clamping to 0xfffe using a bitwise AND
operator. This introduced two issues:
1) for very small baudrates (overflowing the 0xfffe range), the
bitwise-AND generates rather random-looking (wildly varying)
actual output bitrates
2) for higher baudrates, the calculation tends to 'err towards a
higher baudrate' with the actual error increasing as the dividers
become very small. E.g., with a 99MHz input clock, a request
for a 20MBit baudrate (99/20 = 4.95), a 24.75 MBit would be use
(which amounts to a 23.75% error)... for a 34 MBit request this
would be an actual outbout of 49.5 Mbit (i.e. a 45% error).
This change rewrites the divider selection (i.e. baudrate calculation)
by making sure that
a) for the normal case: the largest representable baudrate below the
requested rate will be chosen;
b) for the denormal case (i.e. when the divider can no longer be
represented), the lowest representable baudrate is chosen.
Even though the denormal case (b) may be of little concern in real
world applications (even with a 198MHz input clock, this will only
happen at below approx. 3kHz/3kBit), our board-verification team kept
complaining.
Signed-off-by: Philipp Tomsich <[email protected]>
Tested-by: Klaus Goger <[email protected]>
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The original clock/bitrate selection code for the rk_spi driver was a
bit limited, as it always selected a 99MHz input clock rate (which
would allow for a maximum bitrate of 49.5MBit/s), but returned -EINVAL
if a bitrate higher than 48MHz was requested.
To give us better control over the bitrate (i.e. add more operating
points, especially at "higher" bitrate---such as above 9MBit/s), we
try to choose 4x the maximum frequency (clamped to 50MBit) from the
DTS instead of 99MHz... for most use-cases this will yield a frequency
of 198MHz, but is flexible to go beyond this in future configurations.
This also rewrites the check to allow frequencies of up to half the
SPI module rate as bitrates and then clamps to whatever the DTS allows
as a maximum (board-specific) frequency and does away with the -EINVAL
when trying to select a bitrate (for cases that exceeded the hard
limit) and instead consistently clamps to the lower of the hard limit,
the soft limit for the SPI bus (from the DTS) or the soft limit for
the SPI slave device.
This replaces
"rockchip: spi: rk_spi: select 198MHz input to the SPI module for the RK3399"
"rockchip: spi: rk_spi: improve clocking code for the RK3399"
from earlier versions of this series.
Signed-off-by: Philipp Tomsich <[email protected]>
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Signed-off-by: Vikas Manocha <[email protected]>
cc: Christophe KERELLO <[email protected]>
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.probe method has been assigned twice when declaring
a driver with U_BOOT_DRIVER(). Removed one of them.
Here is the last commit which had the duplicate entry:
"spi: omap3: Convert to driver model"
(sha1: 77b8d04854f486741471ad02b93b473b5b3d72f8)
Signed-off-by: Suniel Mahesh <[email protected]>
Reviewed-by: Jagan Teki <[email protected]>
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This is not currently implemented. Add support for this so that the
Chrome OS EC can be used reliably.
Signed-off-by: Moritz Fischer <[email protected]>
Acked-by: Simon Glass <[email protected]>
Reviewed-by: Jagan Teki <[email protected]>
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Before using the cs_gpio, check if the GPIO is valid or not.
Signed-off-by: Wenyou Yang <[email protected]>
Reviewed-by: Jagan Teki <[email protected]>
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The architecture is currently unmaintained, remove.
Cc: Benjamin Matthews <[email protected]>
Cc: Chong Huang <[email protected]>
Cc: Dimitar Penev <[email protected]>
Cc: Haitao Zhang <[email protected]>
Cc: I-SYST Micromodule <[email protected]>
Cc: M.Hasewinkel (MHA) <[email protected]>
Cc: Marek Vasut <[email protected]>
Cc: Martin Strubel <[email protected]>
Cc: Peter Meerwald <[email protected]>
Cc: Sonic Zhang <[email protected]>
Cc: Valentin Yakovenkov <[email protected]>
Cc: Wojtek Skulski <[email protected]>
Cc: Wojtek Skulski <[email protected]>
Signed-off-by: Tom Rini <[email protected]>
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This patch adds the flags parameter to device_remove() and changes all
calls to this function to provide the default value of DM_REMOVE_NORMAL
for "normal" device removal.
This is in preparation for the driver specific pre-OS (e.g. DMA
cancelling) remove support.
Signed-off-by: Stefan Roese <[email protected]>
Cc: Simon Glass <[email protected]>
Acked-by: Simon Glass <[email protected]>
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SOC’s like LS1012A has only one chip select signal for QSPI flash.
Avoid scanning other flash.
Signed-off-by: Suresh Gupta <[email protected]>
Reviewed-by: York Sun <[email protected]>
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We used to get the address of the optionnal ctrl_mod_mmap register as the
third memory range of the "reg" property. the linux driver moved to use a
syscon instead. In order to keep the DTS as close as possible to that of
linux, we move to using a syscon as well.
If SYSCON is not supported, the driver reverts to the old way of getting
the address from the 3rd memory range
Signed-off-by: Jean-Jacques Hiblot <[email protected]>
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At present devices use a simple integer offset to record the device tree
node associated with the device. In preparation for supporting a live
device tree, which uses a node pointer instead, refactor existing code to
access this field through an inline function.
Signed-off-by: Simon Glass <[email protected]>
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This patch adds support for the QSPI IP found in stm32f7 devices.
Signed-off-by: Michael Kurz <[email protected]>
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Dropped becuase
- driver not used any board.
- no dm conversion.
Cc: Angelo Dureghello <[email protected]>
Cc: Richard Retanubun <[email protected]>
Signed-off-by: Jagan Teki <[email protected]>
Acked-by: Angelo Dureghello <[email protected]>
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Dropped becuase
- driver and related configs not used any board.
- no dm conversion.
Cc: Heiko Schocher <[email protected]>
Cc: Sergey Kostanbaev <[email protected]>
Signed-off-by: Jagan Teki <[email protected]>
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According to Section 11.15.4.9.1 Indirect Read Controller of K2G SoC
TRM SPRUHY8D[1], the external master is only permitted to issue 32-bit
data interface reads until the last word of an indirect transfer
So, make sure that QSPI indirect reads are 32 bit sized except for the
final read. If the rxbuf is unaligned then use bounce buffer, so that
readsl() can be used instead of readsb() to avoid non 32-bit accesses.
[1]www.ti.com/lit/ug/spruhy8d/spruhy8d.pdf
Signed-off-by: Vignesh R <[email protected]>
Reviewed-by: Marek Vasut <[email protected]>
Reviewed-by: Jagan Teki <[email protected]>
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According to Section 11.15.4.9.2 Indirect Write Controller of K2G SoC
TRM SPRUHY8D[1], the external master is only permitted to issue 32-bit
data interface writes until the last word of an indirect transfer
otherwise indirect writes is known to fails sometimes. So, make sure
that QSPI indirect writes are 32 bit sized except for the last write. If
the txbuf is unaligned then use bounce buffer to avoid data aborts.
So, now that the driver uses bounce_buffer, enable CONFIG_BOUNCE_BUFFER
for all boards that use Cadence QSPI driver.
[1]www.ti.com/lit/ug/spruhy8d/spruhy8d.pdf
Signed-off-by: Vignesh R <[email protected]>
Reviewed-by: Marek Vasut <[email protected]>
Reviewed-by: Jagan Teki <[email protected]>
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armada100_spi.c and related env is zapping becuase
of "no DM conversion".
Cc: Ajay Bhargav <[email protected]>
Signed-off-by: Jagan Teki <[email protected]>
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armada100_spi.c, related config options and related codes
are zapping becuase of "no DM conversion".
Cc: Werner Pfister <[email protected]>
Signed-off-by: Jagan Teki <[email protected]>
Reviewed-by: Tom Rini <[email protected]>
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Move the code to read the "sram-size" property into the other code
that reads properties from the node, rather than the SF subnode.
Signed-off-by: Phil Edworthy <[email protected]>
Reviewed-by: Jagan Teki <[email protected]>
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The Cadence QSPI controller has specified overheads for the various CS
times that are in addition to those programmed in to the Device Delay
register. The overheads are different for the delays.
In addition, the existing code does not handle the case when the delay
is less than a SCLK period.
This change accurately calculates the additional delays in Ref clocks.
Signed-off-by: Phil Edworthy <[email protected]>
Reviewed-by: Jagan Teki <[email protected]>
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Signed-off-by: Phil Edworthy <[email protected]>
Acked-by: Marek Vasut <[email protected]>
Reviewed-by: Jagan Teki <[email protected]>
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Instead of extracting mode settings and passing them as separate
args to another function, just pass the SPI mode as an arg.
Signed-off-by: Phil Edworthy <[email protected]>
Reviewed-by: Jagan Teki <[email protected]>
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A lot of the #defines are for single bits in a register, where the
name has _MASK on the end. Since this can be used for both a mask
and the value, remove _MASK from them.
Whilst doing so, also remove the unnecessary brackets around the
constants.
Signed-off-by: Phil Edworthy <[email protected]>
Acked-by: Marek Vasut <[email protected]>
Reviewed-by: Jagan Teki <[email protected]>
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Most of the code already uses #defines for the bit value, rather
than the shift required to get the value. This changes the remaining
code over.
Whislt at it, fix the names of the "Rd Data Capture" register defs.
Signed-off-by: Phil Edworthy <[email protected]>
Acked-by: Marek Vasut <[email protected]>
Reviewed-by: Jagan Teki <[email protected]>
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Show what the output clock rate actually is.
Signed-off-by: Phil Edworthy <[email protected]>
Acked-by: Marek Vasut <[email protected]>
Reviewed-by: Jagan Teki <[email protected]>
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With the existing code, when the requested SPI clock rate is near
to the lowest that can be achieved by the hardware (max divider
of the ref clock is 32), the generated clock rate is wrong.
For example, with a 50MHz ref clock, when asked for anything less
than a 1.5MHz SPI clock, the code sets up the divider to generate
25MHz.
This change fixes the calculation.
Signed-off-by: Phil Edworthy <[email protected]>
Reviewed-by: Jagan Teki <[email protected]>
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Or'ing together bit positions is clearly wrong.
Signed-off-by: Phil Edworthy <[email protected]>
Acked-by: Marek Vasut <[email protected]>
Reviewed-by: Jagan Teki <[email protected]>
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At present an invalid bus width prints a message but does not return an
error. This is the opposite of the correct behaviour. Adjust it to avoid
code bloat in the common case, and avoid hard-to-debug failure in the
uncommon case.
Signed-off-by: Simon Glass <[email protected]>
Reviewed-by: Jagan Teki <[email protected]>
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CONFIG_AM57XX is just an unnecessary macro that is redundant given So,
remove the same instead of spreading through out the u-boot source
code and getting in the way to maintain common code for DRA7x family.
Acked-by: Andrew F. Davis <[email protected]>
Signed-off-by: Nishanth Menon <[email protected]>
Signed-off-by: Lokesh Vutla <[email protected]>
Reviewed-by: Tom Rini <[email protected]>
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This is an uncommon error but we may as well have a debug() message when
it happens.
Signed-off-by: Simon Glass <[email protected]>
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This is not currently implemented. Add support for this so that the Chrome
OS EC can be used on jerry.
Signed-off-by: Simon Glass <[email protected]>
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Allow this driver to be used with of-platdata on rk3288.
Signed-off-by: Simon Glass <[email protected]>
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Some boards may want to use these subsystems with of-platdata in SPL. Add
support for this by avoiding any device tree access in this case.
Signed-off-by: Simon Glass <[email protected]>
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Set the appropriate bits in the interface config register based
on the SPI_ mode flags.
Reviewed-by: Stefan Roese <[email protected]>
Reviewed-by: Jagan Teki <[email protected]>
Signed-off-by: Chris Packham <[email protected]>
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Fix the divider calculation logic to choose a value so that the
resulting baudrate is either equal to or closest possible baudrate less
than the requested value. While at that, cleanup ti_spi_set_speed().
Signed-off-by: Vignesh R <[email protected]>
Reviewed-by: Jagan Teki <[email protected]>
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Add driver model support while retaining the existing legacy code.
This allows the driver to support boards that have converted to
driver model as well as those that have not.
Signed-off-by: Wenyou Yang <[email protected]>
Reviewed-by: Simon Glass <[email protected]>
Acked-by: Stephen Warren <[email protected]>
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The signature for this macro has changed. Bring in the upstream version and
adjust U-Boot's usages to suit.
Signed-off-by: Simon Glass <[email protected]>
Update to drivers/power/pmic/palmas.c:
Signed-off-by: Keerthy <[email protected]>
Change-Id: I6cc9021339bfe686f9df21d61a1095ca2b3776e8
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Signed-off-by: Tom Rini <[email protected]>
Conflicts:
include/configs/ls1021aqds.h
include/configs/ls1021atwr.h
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Fix various misspellings of:
* deprecated
* partition
* preceding,preceded
* preparation
* its versus it's
* export
* existing
* scenario
* redundant
* remaining
* value
* architecture
Signed-off-by: Robert P. J. Day <[email protected]>
Reviewed-by: Jagan Teki <[email protected]>
Reviewed-by: Stefan Roese <[email protected]>
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The endianness can be changed by RCW + PBI sequence. It may have
other than power on reset value.
Signed-off-by: York Sun <[email protected]>
CC: Yuan Yao <[email protected]>
CC: Peng Fan <[email protected]>
CC: Alison Wang <[email protected]>
Reviewed-by: Jagan Teki <[email protected]>
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The SPI IP core in the Marvell Armada 3700 is similar to the one in the
other Armada SoCs. But the differences are big enough that it makes
sense to introduce a new driver instead of cluttering the old
kirkwood driver with #ifdef's.
Signed-off-by: Stefan Roese <[email protected]>
Cc: Nadav Haklai <[email protected]>
Cc: Kostya Porotchkin <[email protected]>
Cc: Wilson Ding <[email protected]>
Cc: Victor Gu <[email protected]>
Cc: Hua Jing <[email protected]>
Cc: Terry Zhou <[email protected]>
Cc: Hanna Hawa <[email protected]>
Cc: Haim Boot <[email protected]>
Reviewed-by: Jagan Teki <[email protected]>
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Now, arch/${ARCH}/include/asm/errno.h and include/linux/errno.h have
the same content. (both just wrap <asm-generic/errno.h>)
Replace all include directives for <asm/errno.h> with <linux/errno.h>.
Signed-off-by: Masahiro Yamada <[email protected]>
[trini: Fixup include/clk.]
Signed-off-by: Tom Rini <[email protected]>
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Since FSL_QSPI driver still supporting non-dm code
better to move the Kconfig from DM undefined place.
Cc: Stefano Babic <[email protected]>
Reviewed-by: Peng Fan <[email protected]>
Signed-off-by: Jagan Teki <[email protected]>
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Current code generates warning when it is compiled for arm64:
Warnings:
In file included from drivers/spi/zynq_spi.c:14:0:
drivers/spi/zynq_spi.c: In function ‘zynq_spi_init_hw’:
drivers/spi/zynq_spi.c:95:9: warning: large integer implicitly truncated
to unsigned type [-Woverflow]
writel(~ZYNQ_SPI_ENR_SPI_EN_MASK, ®s->enr);
^
./arch/arm/include/asm/io.h:146:34: note: in definition of macro
‘writel’
#define writel(v,c) ({ u32 __v = v; __iowmb(); __arch_putl(__v,c); __v;
})
^
drivers/spi/zynq_spi.c: In function ‘zynq_spi_release_bus’:
drivers/spi/zynq_spi.c:177:9: warning: large integer implicitly
truncated to unsigned type [-Woverflow]
writel(~ZYNQ_SPI_ENR_SPI_EN_MASK, ®s->enr);
^
./arch/arm/include/asm/io.h:146:34: note: in definition of macro
‘writel’
#define writel(v,c) ({ u32 __v = v; __iowmb(); __arch_putl(__v,c); __v;
})
^
This patch is using one variable to do conversion via u32 variable.
Signed-off-by: Michal Simek <[email protected]>
Reviewed-by: Jagan Teki <[email protected]>
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Make rx mode flags as generic to spi, earlier mode_rx is
maintained separately because of some flash specific code.
Cc: Simon Glass <[email protected]>
Cc: Bin Meng <[email protected]>
Cc: Michal Simek <[email protected]>
Cc: Siva Durga Prasad Paladugu <[email protected]>
Cc: Vignesh R <[email protected]>
Cc: Mugunthan V N <[email protected]>
Signed-off-by: Jagan Teki <[email protected]>
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