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This would be useful to start moving various config options.
Signed-off-by: Masahiro Yamada <[email protected]>
Acked-by: Simon Glass <[email protected]>
Tested-by: Simon Glass <[email protected]>
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Signed-off-by: Stefan Roese <[email protected]>
Cc: Jagannadha Sutradharudu Teki <[email protected]>
Acked-by: Prafulla Wadaskar <[email protected]>
Tested-by: Luka Perkov <[email protected]>
Reviewed-by: Jagannadha Sutradharudu Teki <[email protected]>
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Signed-off-by: Stefan Roese <[email protected]>
Acked-by: Prafulla Wadaskar <[email protected]>
Tested-by: Luka Perkov <[email protected]>
Reviewed-by: Jagannadha Sutradharudu Teki <[email protected]>
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This patch introduces the clrsetbits_le32() accessor functions in the
kirkwood SPI driver. Note that it also includes a fix:
- writel(~KWSPI_CSN_ACT | KWSPI_SMEMRDY, &spireg->ctrl);
+ writel(KWSPI_SMEMRDY, &spireg->ctrl);
Here the bit KWSPI_CSN_ACT (0x1) should have been cleared. Instead
0xfffffffe is written into this control register. This is the main
reason to use the clrsetbits() functions now. As they make clearing
bits much less error prone.
Additionally KWSPI_IRQUNMASK is not used in spi_cs_activate() and
spi_cs_deactivate() any more. Its the wrong macro but has the same
value as the correct one (KWSPI_CSN_ACT).
This is in preparation for use of this driver on the Marvell Armada XP
platform as well.
Signed-off-by: Stefan Roese <[email protected]>
Acked-by: Prafulla Wadaskar <[email protected]>
Tested-by: Luka Perkov <[email protected]>
Reviewed-by: Jagannadha Sutradharudu Teki <[email protected]>
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MXC SPI driver has a feature whereas a GPIO line can be used to force CS high
across multiple transactions. This is set up by embedding the GPIO information
in the CS value:
cs = (cs | gpio << 8)
This merge of cs and gpio data into one value breaks the sf probe command:
if the use of gpio is required, invoking "sf probe <cs>" will not work, because
the CS argument doesn't have the GPIO information in it. Instead, the user must
use "sf probe <cs | gpio << 8>". For example, if bank 2 gpio 30 is used to force
cs high on cs 0, bus 0, then instead of typing "sf probe 0" the user now must
type "sf probe 15872".
This is inconsistent with the description of the sf probe command, and forces
the user to be aware of implementaiton details.
Fix this by introducing a new board function: board_spi_cs_gpio(), which will
accept a naked CS value, and provide the driver with the relevant GPIO, if one
is necessary.
Cc: Eric Nelson <[email protected]>
Cc: Eric Benard <[email protected]>
Cc: Fabio Estevam <[email protected]>
Cc: Tim Harvey <[email protected]>
Cc: Stefano Babic <[email protected]>
Cc: Tom Rini <[email protected]>
Cc: Marek Vasut <[email protected]>
Reviewed-by: Marek Vasut <[email protected]>
Signed-off-by: Nikita Kiryanov <[email protected]>
Reviewed-by: Jagannadha Sutradharudu Teki <[email protected]>
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if status register do never set MXC_CSPICTRL_TC, spi_xchg_single
endless loops. Add a timeout here to prevent endless hang.
Signed-off-by: Heiko Schocher <[email protected]>
Cc: Dirk Behme <[email protected]>
Reviewed-by: Jagannadha Sutradharudu Teki <[email protected]>
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This parameter should also be supported.
Signed-off-by: Simon Glass <[email protected]>
Tested-by: Ajay Kumar <[email protected]>
Reviewed-by: Jagannadha Sutradharudu Teki <[email protected]>
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The SPI transaction delay is supposed to be measured from the end of one
transaction to the start of the next. The code does not work that way, so
fix it.
Signed-off-by: Simon Glass <[email protected]>
Tested-by: Ajay Kumar <[email protected]>
Reviewed-by: Jagannadha Sutradharudu Teki <[email protected]>
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This patch returns back support for old ep93xx processors family
Signed-off-by: Sergey Kostanbaev <[email protected]>
Cc: [email protected]
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Conflicts:
boards.cfg
Conflict was trivial between goni maintainer change and
lager_nor removal.
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SPI recieve and transfer code in exynos_spi driver has a logical bug.
We read data in a variable which can hold an integer. Then we assign
this integer 32 bit value to another variable which has data type uchar.
Latter represents a unit of our recieve buffer. Everytime when we write
a value to our recieve buffer we step ahead by 4 units when actually we
wrote to one unit. This results in the loss of 3 bytes out of every 4
bytes recieved. This patch intends to fix this bug.
Signed-off-by: Akshay Saraswat <[email protected]>
Acked-by: Simon Glass <[email protected]>
Tested-by: Simon Glass <[email protected]>
Signed-off-by: Minkyu Kang <[email protected]>
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Fix a trivial copy-paste bug.
Signed-off-by: Axel Lin <[email protected]>
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Add Freescale QSPI driver support for VF610.
Signed-off-by: Alison Wang <[email protected]>
Signed-off-by: Chao Fu <[email protected]>
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This mirrors the conventions used in other SPI drivers (kirkwood,
davinci, atmel, et al) where the din/dout buffer can be NULL when the
received/transmitted data isn't important. This reduces the need for
allocating additional buffers when write-only/read-only functionality is
needed.
In the din == NULL case, the received data is simply not stored. In the
dout == NULL case, zeroes are transmitted.
Signed-off-by: Andrew Ruder <[email protected]>
Cc: Jean-Christophe PLAGNIOL-VILLARD <[email protected]>
Reviewed-by: Jagannadha Sutradharudu Teki <[email protected]>
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The patch populates the slave data which will be used by flash driver to
set the flash quad enable bit.
Signed-off-by: Sourav Poddar <[email protected]>
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Replace 80 mircoseconds delay with polling flag ESPI_EV_TXE.
Signed-off-by: Hou Zhiqiang <[email protected]>
Reviewed-by: York Sun <[email protected]>
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Currently davinci spi driver supports only bus 0 cs 0.
This patch allows driver to support bus 1 and bus 2 with
configurable number of chip selects. Also defaults are
selected in a way to avoid regression on other platforms
that uses davinci spi driver and has only one spi bus.
Signed-off-by: Rex Chang <[email protected]>
Signed-off-by: Murali Karicheri <[email protected]>
Reviewed-by: Jagannadha Sutradharudu Teki <[email protected]>
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Bulk erase is not happening properly on dra7 due to erase timing constraints,
add a delay so that erase timing constraints are properly met.
Signed-off-by: Sourav Poddar <[email protected]>
Tested-by: Yebio Mesfin <[email protected]>
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This renames all the Tegra20 pinmux pins and functions so they have a
prefix which matches the type name.
The entries in tegra20_pingroups[] are all updated to remove the columns
which are no longer used.
All affected code is updated to match.
Signed-off-by: Stephen Warren <[email protected]>
Acked-by: Simon Glass <[email protected]>
Signed-off-by: Tom Warren <[email protected]>
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Trivial merge conflict, needed to manually remove
local_info as per commit 41364f0f.
Conflicts:
board/samsung/common/board.c
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This function is needed when CONFIG_OF_SPI is defined.
Signed-off-by: Simon Glass <[email protected]>
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Refactor the code a bit to make it better in readability.
Remove the comments because now the intention of the code is pretty clear.
Signed-off-by: Axel Lin <[email protected]>
Reviewed-by: Jagannadha Sutradharudu Teki <[email protected]>
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The logic determining SPI "write" transfer completion was faulty. At
certain conditions (e.g. slow SPI clock freq) the transfers were
interrupted before completion. Both EOT and TXS flags of channel
status registeer shall be checked to ensure that all data was
transferred. Tested on AM3359 chip.
Signed-off-by: Vasili Galka <[email protected]>
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Signed-off-by: Sonic Zhang <[email protected]>
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Without this delay, write/read is failing.
Looks like, the WIP always remain set and hence a timeout
occurs leading to the error.
Without this patch, device does not get probed also.
Here is the log.
U-Boot#
U-Boot#
U-Boot#
U-Boot# sf probe 0
SF: Unsupported flash IDs: manuf ff, jedec ffff, ext_jedec ffff
Failed to initialize SPI flash at 0:0
U-Boot# sf probe 0
While with this patch, log is
U-Boot# sf probe 0
SF: Detected MX25L51235F with page size 256 Bytes, erase size 64 KiB, total 64 MiB, mapped at 30000000
U-Boot# sf erase 0 0x80000
SF: 524288 bytes @ 0x0 Erased: OK
U-Boot# mw 81000000 0xdededede 0x40000
U-Boot# sf write 81000000 0 0x40000
SF: 262144 bytes @ 0x0 Written: OK
U-Boot# sf read 82000000 0 0x40000
SF: 262144 bytes @ 0x0 Read: OK
U-Boot# md 0x82000000
Signed-off-by: Sourav Poddar <[email protected]>
Reviewed-by: Jagannadha Sutradharudu Teki <[email protected]>
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Add AM43xx specific changes.
Signed-off-by: Sourav Poddar <[email protected]>
Reviewed-by: Jagannadha Sutradharudu Teki <[email protected]>
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SPI_MODE_3 requires clk high when inactive. The SCLK_CTL
field of the config reg was not configured in case of CPOL.
Fix configuration so that SPI_MODE_3 which uses CPOL configures
the clk line to be high in inactive state.
Signed-off-by: Markus Niebel <[email protected]>
Reviewed-by: Jagannadha Sutradharudu Teki <[email protected]>
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Timeout calculation should be out of the data loop.
This patch increase spi bandwidth for 30%.
Signed-off-by: Michal Simek <[email protected]>
Reviewed-by: Jagannadha Sutradharudu Teki <[email protected]>
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Signed-off-by: Nobuhiro Iwamatsu <[email protected]>
Reviewed-by: Jagannadha Sutradharudu Teki <[email protected]>
Signed-off-by: Nobuhiro Iwamatsu <[email protected]>
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We have a sh_spi_clear_bit() function, there's no reason not to use it.
Signed-off-by: Axel Lin <[email protected]>
Acked-by: Nobuhiro Iwamatsu <[email protected]>
Reviewed-by: Jagannadha Sutradharudu Teki <[email protected]>
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The Faraday FTSSP010 is a multi-function controller
which supports I2S/SPI/SSP/AC97/SPDIF. However This
patch implements only the SPI mode.
NOTE:
The DMA and CS/Clock control logic has been altered
since hardware revision 1.19.0. So this patch
would first detects the revision id of the underlying
chip, and then switch to the corresponding software
control routines.
Signed-off-by: Kuo-Jung Su <[email protected]>
Signed-off-by: Jagannadha Sutradharudu Teki <[email protected]>
CC: Tom Rini <[email protected]>
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The RDY bit indicates that a transfer is complete. This needs to be
cleared by SW before every single HW transaction, rather than only
at the start of each SW transaction (those being made up of n HW
transactions).
It seems that earlier HW may have cleared this bit autonomously when
starting a new transfer, and hence this code was not needed in practice.
However, this is generally a good idea in all cases. In Tegra124, the
HW behaviour appears to have changed, and SW must explicitly clear this
bit. Otherwise, SW will believe that transfers have completed when they
have not, and may e.g. read stale data from the RX FIFO.
Signed-off-by: Yen Lin <[email protected]>
[swarren, rewrote commit description, unified duplicate RDY clearing code
and moved it right before the start of the HW transaction, unconditionally
exit loop after reading RX data, rather than checking if TX FIFO is empty,
since it is guaranteed to be]
Signed-off-by: Stephen Warren <[email protected]>
Reviewed-by: Jagannadha Sutradharudu Teki <[email protected]>
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This patch adds a driver for Renesas SoC's Quad SPI bus.
This supports with 8 bits per transfer to use with SPI flash.
Signed-off-by: Kouei Abe <[email protected]>
Signed-off-by: Nobuhiro Iwamatsu <[email protected]>
Signed-off-by: Jagannadha Sutradharudu Teki <[email protected]>
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This adds a SPI framework for people to hook up simulated SPI clients.
Signed-off-by: Mike Frysinger <[email protected]>
Signed-off-by: Simon Glass <[email protected]>
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This allows us to put the SPI flash chip inside the SPI interface node,
with U-Boot finding the correct bus and chip select automatically.
Signed-off-by: Simon Glass <[email protected]>
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For invalid bus number, current code returns NULL in the default case of
switch-case statements. In additional, pins[bus] is always not NULL because
it is the address of specific row of the two-dimensional array.
Thus this patch removes these unnecessary test.
Signed-off-by: Axel Lin <[email protected]>
Acked-by: Scott Jiang <[email protected]>
Signed-off-by: Sonic Zhang <[email protected]>
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For invalid bus number, current code returns NULL in the default case of
switch-case statements. In additional, pins[bus] is always not NULL because
it is the address of specific row of the two-dimensional array.
Thus this patch removes these unnecessary test.
Signed-off-by: Axel Lin <[email protected]>
Acked-by: Scott Jiang <[email protected]>
Signed-off-by: Sonic Zhang <[email protected]>
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Current implementation only supports 8 bit word lengths, even though
omap3 can handle anything between 4 and 32.
Update the spi interface to support changing the SPI word length,
and implement it in omap3_spi driver to support the full range of
possible word lengths.
This implementation is backwards compatible by defaulting to the old
behavior of 8 bit word lengths.
Also, it required a change to the omap3_spi non static I/O functions,
but since they are not used anywhere else, no collateral changes are required.
Cc: Tom Rini <[email protected]>
Cc: Jagannadha Sutradharudu Teki <[email protected]>
Cc: Igor Grinberg <[email protected]>
Signed-off-by: Nikita Kiryanov <[email protected]>
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Remove unnecessary semicolon from #define SPI_WAIT_TIMEOUT
Cc: Tom Rini <[email protected]>
Cc: Jagannadha Sutradharudu Teki <[email protected]>
Cc: Igor Grinberg <[email protected]>
Cc: Gerhard Sittig <[email protected]>
Signed-off-by: Nikita Kiryanov <[email protected]>
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Signed-off-by: Masahiro Yamada <[email protected]>
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If dout buffer is not 32 bit-aligned or data to transmit is not multiple
of 32 bit the read data pointer is already incremented on single byte reads.
Signed-off-by: Timo Herbrecher <[email protected]>
Signed-off-by: Jagannadha Sutradharudu Teki <[email protected]>
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Added GPL-2.0+ SPDX-License-Identifier for missed spi
source files.
Signed-off-by: Jagannadha Sutradharudu Teki <[email protected]>
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