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The Andes PLMT driver directly accesses the mtime MMIO region,
indicating its intended use in the M-mode boot stage. However,
since U-Boot proper (S-mode) also uses the PLMT driver, we need
to specifically mark the region as readable through PMPCFGx (or
S/U-mode read-only shared data region for Smepmp) in OpenSBI.
Granting permission for this case doesn't make sense. Instead,
we should use the generic RISC-V timer driver to read the mtime
through the TIME CSR. Therefore, we add the SPL_ANDES_PLMT_TIMER
config, which ensures that the PLMT driver is linked exclusively
against M-mode U-Boot or U-Boot SPL binaries.
Signed-off-by: Yu Chien Peter Lin <[email protected]>
Reviewed-by: Samuel Holland <[email protected]>
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Add timer driver in Starfive SoC. It is an timer that outside
of CPU core and inside Starfive SoC.
Signed-off-by: Kuan Lim Lee <[email protected]>
Reviewed-by: Wei Liang Lim <[email protected]>
Reviewed-by: Simon Glass <[email protected]>
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timer_get_boot_us function is required to record the boot stages as
us-based timestamp.
To get a micro-second time from a timer tick, this converts the
formula like below to avoid zero result of (tick / rate) part.
From: time(us) = (tick / rate) * 1000000
To : time(us) = (tick * 1000) / (rate / 1000)
Signed-off-by: Chanho Park <[email protected]>
Reviewed-by: Leo Yu-Chi Liang <[email protected]>
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timer_get_boot_us function is required to record the boot stages as
us-based timestamp.
To get a micro-second time from a timer tick, this converts the
formula like below to avoid zero result of (tick / rate) part.
From: time(us) = (tick / rate) * 1000000
To : time(us) = (tick * 1000) / (rate / 1000)
Signed-off-by: Chanho Park <[email protected]>
Reviewed-by: Leo Yu-Chi Liang <[email protected]>
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Signed-off-by: Tom Rini <[email protected]>
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The last user of the NEEDS_MANUAL_RELOC has been removed in commit
26af162ac8f8 ("arch: m68k: Implement relocation")
Remove now unused NEEDS_MANUAL_RELOC code.
Signed-off-by: Marek Vasut <[email protected]>
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For the architectural timer on riscv, there already is a defined
device tree binding[1]. Allow timer instances to be created from
device tree matches, but for now retain the old mechanism, which
registers the timer biggy-back with the CPU.
[1] linux/Documentation/devicetree/bindings/timer/riscv,timer.yaml
Signed-off-by: Torsten Duwe <[email protected]>
Reviewed-by: Leo Yu-Chi Liang <[email protected]>
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The TI AM654 timer is compatible with the omap-timer implementation,
so add it to the compatible id list.
Signed-off-by: Sjoerd Simons <[email protected]>
Reviewed-by: Roger Quadros <[email protected]>
Reviewed-by: Tom Rini <[email protected]>
Tested-by: Maxime Ripard <[email protected]>
Tested-by: Ravi Gunasekaran <[email protected]>
Tested-by: Mattijs Korpershoek <[email protected]>
Cc: Francesco Dolcini <[email protected]>
Cc: Wadim Egorov <[email protected]>
Signed-off-by: Nishanth Menon <[email protected]>
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As the RISC-V ACLINT specification is defined to be backward compatible
with the SiFive CLINT specification, we rename SiFive CLINT to RISC-V
ALINT in the source tree to be future-proof.
Signed-off-by: Bin Meng <[email protected]>
Reviewed-by: Rick Chen <[email protected]>
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This RISC-V ACLINT specification [1] defines a set of memory mapped
devices which provide inter-processor interrupts (IPI) and timer
functionalities for each HART on a multi-HART RISC-V platform.
The RISC-V ACLINT specification is defined to be backward compatible
with the SiFive CLINT specification, however the device tree binding
is a new one. This change updates the sifive clint timer driver to
support ACLINT mtimer device, using a per-driver data field to hold
the mtimer offset to the base address encoded in the mtimer node.
[1] https://github.com/riscv/riscv-aclint/blob/main/riscv-aclint.adoc
Signed-off-by: Bin Meng <[email protected]>
Reviewed-by: Rick Chen <[email protected]>
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The fdt_addr_t and phys_addr_t size have been decoupled.
A 32bit CPU can expect 64-bit data from the device tree parser,
so use a regs variable with uintptr_t size in the
dw-apb-timer.c file.
Signed-off-by: Johan Jonker <[email protected]>
Reviewed-by: Simon Glass <[email protected]>
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In the binding for the Rockchip timer the compatible string
consists of a SoC orientated string and a fall back string
"rockchip,rk3288-timer", so remove all unneeded ones and
fix driver name.
Signed-off-by: Johan Jonker <[email protected]>
Reviewed-by: Kever Yang <[email protected]>
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Prepare v2023.04-rc4
Signed-off-by: Tom Rini <[email protected]>
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It is not yet clear how to read the timer via EFI. The current value seems
much too high on a Framework laptop I tried. Adjust it to a lower
hard-coded value for now.
Signed-off-by: Simon Glass <[email protected]>
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The fttmr010 timer driver was deleted by
commit 29fc6f24926e ("ARM: remove a320evb board support")
The original source file was: arch/arm/cpu/arm920t/a320/timer.c
Return the driver to the codebase in a DM compatible form.
A platform using fttmr010 will be submitted later.
This hardware is described in the datasheet [1], starting from page 348.
According to the datasheet, there is a Revision Register at offset 0x3C,
which is not present in 'struct fttmr010'. Add it and debug() print
revision in probe function.
[1]
https://bitbucket.org/Kasreyn/mkrom-uc7112lx/src/master/documents/FIC8120_DS_v1.2.pdf
Signed-off-by: Sergei Antonov <[email protected]>
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Building sandbox_defconfig with CONFIG_SPL_TIMER=y results in an error
include/dm/platdata.h:63:33: error: static assertion failed:
"Cannot use U_BOOT_DRVINFO with of-platdata.
Please use devicetree instead"
Add a missing condition in the sandbox driver.
Signed-off-by: Heinrich Schuchardt <[email protected]>
Reviewed-by: Simon Glass <[email protected]>
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Tracing is typically enabled by the time driver model starts up, so there
is no point in adding a 'notrace' to the timer-init function. However,
once the driver model timer is enabled, we do need to be able to access
the timer's private data when reading the timer, so add it to the core
function needed for that.
Update the function's documentation while we are here.
Signed-off-by: Simon Glass <[email protected]>
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Add timer support for T20/T30/T114/T124 and T210 based devices.
Driver is based on DM, has device tree support and can be
used on SPL and early boot stage.
Arm64 Tegra (apart T210) according to comment in tegra-common.h use
architected timer.
Tested-by: Andreas Westman Dorcsak <[email protected]> # ASUS TF600T T30
Tested-by: Jonas Schwöbel <[email protected]> # Surface RT T30
Tested-by: Robert Eckelmann <[email protected]> # ASUS TF101 T20
Tested-by: Agneli <[email protected]> # Toshiba AC100 T20
Tested-by: Svyatoslav Ryhel <[email protected]> # LG P895 T30
Co-developed-by: Jonas Schwöbel <[email protected]>
Signed-off-by: Jonas Schwöbel <[email protected]>
Signed-off-by: Svyatoslav Ryhel <[email protected]>
Reviewed-by: Simon Glass <[email protected]>
Signed-off-by: Tom <[email protected]>
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At this point, the remaining places where we have a symbol that is
defined as CONFIG_... are in fairly odd locations. While as much dead
code has been removed as possible, some of these locations are simply
less obvious at first. In other cases, this code is used, but was
defined in such a way as to have been missed by earlier checks. Perform
a rename of all such remaining symbols to be CFG_... rather than
CONFIG_...
Signed-off-by: Tom Rini <[email protected]>
Reviewed-by: Simon Glass <[email protected]>
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It was noticed that Clearfog is currently broken with this newly
introduced early_init_done() function. Apparently the timer is enabled
here when U-Boot is run but not configured - at least not correctly.
Resulting in a hangup in the timer reading functions.
To fix this, also read the value of the reload register and check it's
value with the one written to by U-Boot. Only if this matches, the
init has already been done.
Fixes: 5387b093cb79 ("timer: orion-timer: Fix problem with early static variable")
Signed-off-by: Stefan Roese <[email protected]>
Acked-by: Pali Rohár <[email protected]>
Cc: Martin Rowe <[email protected]>
Cc: Tony Dinh <[email protected]>
Cc: Pali Rohár <[email protected]>
Cc: Michael Walle <[email protected]>
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Signed-off-by: Tom Rini <[email protected]>
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We've noticed that at least one Kirkwood board (Pogo v4) has problems
with the new orion DM timer implementation. Debugging revealed that this
issue is related with the static variable "early_init_done" which does
not work correctly before relocation in all cases.
This patch removes this static variable and replaces it's functionality
via a function that detects if the timer is already initialized.
Signed-off-by: Stefan Roese <[email protected]>
Cc: Pali Rohár <[email protected]>
Cc: Michael Walle <[email protected]>
Cc: Tony Dinh <[email protected]>
Tested-by: Tony Dinh <[email protected]>
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The rest of the unmigrated CONFIG symbols in the CONFIG_SYS namespace do
not easily transition to Kconfig. In many cases they likely should come
from the device tree instead. Move these out of CONFIG namespace and in
to CFG namespace.
Signed-off-by: Tom Rini <[email protected]>
Reviewed-by: Simon Glass <[email protected]>
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Current xilinx_timer_get_count() implementation does not take into account
the periodic 32-bit wrap arounds, as it directly returns the 32-bit counter
register value. The roll-overs cause problems in the upper timer layers, as
generic timer code expects an incrementing 64-bit value from get_count() to
work correctly.
Add the missing 64-bit up-conversion to fix random hangs/delays in
__udelay().
Fixes: a36d86720f ("microblaze: Convert axi timer to DM driver")
Signed-off-by: Ovidiu Panait <[email protected]>
Reviewed-by: Michal Simek <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Michal Simek <[email protected]>
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Relocate timer_ops pointers when CONFIG_NEEDS_MANUAL_RELOC is enabled.
The (gd->flags & GD_FLG_RELOC) check was added to make sure the reloc_done
logic works for drivers that use DM_FLAG_PRE_RELOC.
Signed-off-by: Ovidiu Panait <[email protected]>
Reviewed-by: Simon Glass <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Michal Simek <[email protected]>
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Align timer uclass with the other subsystems and provide a timer_get_ops()
convenience macro.
Using this instead of the generic device_get_ops() also prevents
-Wdiscarded-qualifiers warnings when used with non-const variables.
Signed-off-by: Ovidiu Panait <[email protected]>
Reviewed-by: Simon Glass <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Michal Simek <[email protected]>
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- Improve arm semihosting, NPCM8xx pinctrl driver, SP804 uclass timer
driver (and enable on relevant platforms), pvblock cleanup, eeprom cmd
bugfix, add RTI watchdog nodes to k3-am64-main, evb-ast2500 config
updates.
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As PLICSW is used to trigger the software interrupt, we should rename
Andes PLIC configuration and file name to reflect the usage. This patch
also updates PLMT and PLICSW compatible strings to be consistent with
OpenSBI fdt driver.
Signed-off-by: Yu Chien Peter Lin <[email protected]>
Reviewed-by: Rick Chen <[email protected]>
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The "Arm Ltd. Dual-Timer Module (SP804)" is a simple 32-bit count-down
timer IP with interrupt functionality, and is used in some SoCs from
various vendors.
Add a simple DM compliant timer driver, to allow users of the SP804 to
switch to DM_TIMER.
This relies on the input clock to be accessible via the DM clock
framework, which should be fine as we probably look at fixed-clock's
here anyway.
We re-program the control register in the probe() function, but keep
the divider in place, in case this has been set to something on purpose
before.
The TRM for the timer IP can be found here:
https://developer.arm.com/documentation/ddi0271/latest
Signed-off-by: Andre Przywara <[email protected]>
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STI timer is actually ARM Cortex A9 global timer. Convert the driver to
use generic global timer name and make it consistent with Linux kernel
global timer driver. This also allows any A9 based device to use this
driver.
Signed-off-by: William Zhang <[email protected]>
Reviewed-by: Patrice Chotard <[email protected]>
Tested-by: Patrice Chotard <[email protected]>
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Move the code making sure that the timer is initialized only once into
orion_timer_init(), which is called from timer_early_init() and from
orion_timer_probe(). This way the timer is not re-initialized.
Signed-off-by: Stefan Roese <[email protected]>
Cc: Michael Walle <[email protected]>
Cc: Pali Rohár <[email protected]>
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This patch add general-purpose timer support for MediaTek MT7981/MT7986.
These two SoCs uses a newer version of timer with its register definition
slightly changed.
Reviewed-by: Simon Glass <[email protected]>
Tested-by: Daniel Golle <[email protected]>
Signed-off-by: Weijie Gao <[email protected]>
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Add timer_get_boot_us() to support boards, that have CONFIG_BOOTSTAGE
enabled, like pogo_v4.
Signed-off-by: Stefan Roese <[email protected]>
Tested-by: Tony Dinh <[email protected]>
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This patch adds support for other Marvell Armada SoC's, supporting the
25MHz fixed clock operation, like the Armada XP etc.
Signed-off-by: Stefan Roese <[email protected]>
Tested-by: Tony Dinh <[email protected]>
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Signed-off-by: Tom Rini <[email protected]>
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While testing on some Kirkwood platforms it was noticed that the timer
did not function correctly all the time. The driver did not correctly
handle 32bit timer value wrap arounds. Using the timer_conv_64()
conversion function fixes this issue.
Fixes: e9e73d78a8fb ("timer: add orion-timer support")
Suggested-by: Stefan Herbrechtsmeier <[email protected]>
Signed-off-by: Stefan Roese <[email protected]>
Tested-by: Tony Dinh <[email protected]>
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Globally replace all occurances of WATCHDOG_RESET() with schedule(),
which handles the HW_WATCHDOG functionality and the cyclic
infrastructure.
Signed-off-by: Stefan Roese <[email protected]>
Reviewed-by: Simon Glass <[email protected]>
Tested-by: Tom Rini <[email protected]> [am335x_evm, mx6cuboxi, rpi_3,dra7xx_evm, pine64_plus, am65x_evm, j721e_evm]
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Move arm twd timer driver from zynq to generic location.
DM timer drivers are designed differently to original driver. Timer is
counting up and not down.
Information about clock rates are find out in timer_pre_probe() that's
why there is no need to get any additional information from DT in the
driver itself (only register offset).
Signed-off-by: Stefan Herbrechtsmeier <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Michal Simek <[email protected]>
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Add timer support for Kirkwood and MVEBU devices.
Cc: Pali Rohár <[email protected]>
Signed-off-by: Michael Walle <[email protected]>
Acked-by: Pali Rohár <[email protected]>
Reviewed-by: Stefan Roese <[email protected]>
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https://source.denx.de/u-boot/custodians/u-boot-microblaze into next
Xilinx changes for v2022.10
cpu:
- Add driver for microblaze cpu
net:
- Add support for DM_ETH_PHY to AXI emac and emaclite
xilinx:
- Switch platforms to DM_ETH_PHY
- DT chagnes in ZynqMP and Zynq
- Enable support for SquashFS
zynqmp:
- Add support for KR260 boards
- Move BSS from address 0
- Move platform identification from board code to soc driver
- Improve zynqmp_psu_init_minimize
versal:
- Enable loading app at EL1
serial:
- Setup default address and clock rates for DEBUG uarts
pinctrl:
- Add support for tri state and output enable properties
relocate-rela:
- Clean relocate-rela implementation for ARM64
- Add support for Microblaze
microblaze:
- Add support for runtime relocation
- Rework cache handling (wiring, Kconfig) based on cpuinfo
- Remove interrupt support
timer:
- Extract axi timer driver from Microblaze to generic location
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Add SPL_REGMAP dependency when SPL is enabled. This can avoid compilation
issues if timer is selected but SPL_REGMAP not.
Reported-by: Ovidiu Panait <[email protected]>
Signed-off-by: Michal Simek <[email protected]>
Link: https://lore.kernel.org/r/8f6c187e04cb3127bf5148ae2dbbdf55b25ea544.1655982509.git.michal.simek@amd.com
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Move axi timer driver from Microblaze to generic location.
Origin implementation was irq based with counting down timer.
CONFIG_TIMER drivers are designed differently that timer is free running up
timer with automatic reload without any interrupt.
Information about clock rates are find out in timer_pre_probe() that's why
there is no need to get any additional information from DT in the driver
itself (only register offset).
Signed-off-by: Michal Simek <[email protected]>
Tested-by: Ovidiu Panait <[email protected]>
Link: https://lore.kernel.org/r/6c12fc86bbc1f17d05c25018862e7b7b03346b36.1654684731.git.michal.simek@amd.com
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Add support for the HPE GXP SOC timer. The GXP supports several different
kinds of timers but for the purpose of this driver there is only support
for the General Timer. The timer has a 1us resolution and is 56 bits.
Signed-off-by: Nick Hawkins <[email protected]>
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This is always defined to 2, and referenced in two places. Move the
define to <asm/omap_common.h> and make sure the code that uses this
includes that file. Make <asm/arch-omap*/clock.h> not include that
file, as we don't need to be doing so.
Signed-off-by: Tom Rini <[email protected]>
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Add Nuvoton BMC NPCM7xx/NPCM8xx timer driver.
Signed-off-by: Jim Liu <[email protected]>
Signed-off-by: Stanley Chu <[email protected]>
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Add VPL versions of commonly used Kconfig options.
Signed-off-by: Simon Glass <[email protected]>
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This commit allows the ATMEL_PIT_TIMER driver to be unselected in SPL and be
selected in u-boot proper. The SPL can use a different timer.
By having a separate Kconfig for ATMEL_TCB in SPL, the size of the SPL
decreases by 0.3 KBytes.
Signed-off-by: Eugen Hristev <[email protected]>
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This commit allows the ATMEL_TCB driver to be unselected in SPL and be
selected in u-boot proper. The SPL can use a different timer.
By having a separate Kconfig for ATMEL_TCB in SPL, the size of the SPL
decreases by 1 KByte.
Signed-off-by: Eugen Hristev <[email protected]>
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As removal of nds32 has been ack'd for the Linux kernel, remove support
here as well.
Cc: Rick Chen <[email protected]>
Signed-off-by: Tom Rini <[email protected]>
Reviewed-by: Rick Chen <[email protected]>
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