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https://git.u-boot-project.org/u-boot/custodians/u-boot-rockchip into next
- Fixed possible SPI hangs when only PICO is routed (TX-only),
- Added support for ROC-RK3399-PC-PLUS (via roc-pc-rk3399_defconfig)
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Shahriyar Jalayeri <[email protected]> says:
This fixes an out-of-bounds write in the RLE8 BMP decoder and adds a
regression test.
video_display_rle8_bitmap() lets the framebuffer cursor drift below the
start of the framebuffer via repeated End-Of-Line escapes, so a crafted
image displayed from the splash-screen or PXE-menu path (loaded from
removable media or over TFTP) writes before the framebuffer. Patch 1
bounds each run and rejects such an image with -EINVAL; patch 2 adds a DM
test for it.
Link: https://lore.kernel.org/r/[email protected]
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video_display_rle8_bitmap() moves the framebuffer cursor fb up by a
full row plus a scanline on each End-Of-Line escape, with no
lower-bound check. Repeated EOL escapes desynchronise fb from the
scanline index y: after height - 1 escapes y is back in range while fb
has drifted about one framebuffer below priv->fb, and the decoder
writes pixel data before the start of the framebuffer. The DELTA
escape recomputes fb from an unchecked y as well. A crafted RLE8
image displayed from the splash-screen or PXE-menu path can therefore
write out of bounds.
Check the cursor against [priv->fb, priv->fb + fb_size) before each
run and reject the image with -EINVAL if a write would fall outside
it.
Signed-off-by: Shahriyar Jalayeri <[email protected]>
Reviewed-by: Simon Glass <[email protected]>
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The block cache keys its entries on (iftype, devnum, start, blkcnt,
blksz) but not on the block descriptor's hardware partition. Devices
that expose several independent address spaces through blk_desc->hwpart
therefore alias each other in the cache: once a block has been cached
for one hwpart, reads of the same LBA on another hwpart return the data
cached for the first one.
For MMC this is masked because switching hwpart invalidates the cache,
but a UBI block device selects the target volume purely through hwpart
and does not invalidate on switch, so scanning several UBI volumes
returns the first volume's blocks for all of them.
Add hwpart to the cache key so entries for different hardware partitions
(or UBI volumes) are kept distinct.
Fixes: e40cf34a29f1 ("drivers: block: add block device cache")
Signed-off-by: Daniel Golle <[email protected]>
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https://git.u-boot-project.org/u-boot/custodians/hs/u-boot-i2c into next
i2c updates for 2026.10-next
- i2c/clk: spacemit: k1: fix I2C bus configuration and clock handling
from Junhui
Reviewed by Yao Zi and myself.
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https://git.u-boot-project.org/u-boot/custodians/u-boot-mediatek into next
* New HDMI PHY and I2C DDC drivers, default EDID_ADDR macro
* MT8189 clock qualifier fix
* Phase-aware PSCI reset (MT8195/MT8365)
* dwc_eth_qos MT8366 support
* MediaTek TPHY v3 hardware support
* mtk_snor mt8188/mt8189 compatible-string cleanup
* MT6358/MT6366 PMIC regulator + pwrap support
* MediaTek pinctrl Kconfig cleanup (per-SoC symbols → single driver + TARGET_*)
* New MT8366 pinctrl driver + dt-bindings header
* MediaTek serial driver clock-handling fixes
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The TWSI functional clocks incorrectly include both the functional clock
enable bit and the bus clock enable bit in their gate masks. The device
tree and the full clock tree model the bus clocks separately.
Remove the bus clock enable bit from the functional clock gate masks so
that the functional and bus clocks are controlled independently.
Keep the combined gate for TWSI8 because its clock control register is
write-only and therefore cannot be safely shared by two clock
instances.
Fixes: 3aa2882a3e1a ("clk: spacemit: Add support for K1 SoC")
Reviewed-by: Yao Zi <[email protected]>
Signed-off-by: Junhui Liu <[email protected]>
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The K1 I2C controller requires both its functional clock and APB bus
clock to operate. The device tree provides them as "func" and "bus", but
the driver currently acquires and enables only the first clock.
Acquire both clocks by name and enable them during probe. Use explicit
named lookups instead of the bulk clock API to align with the K1 Linux
driver and keep the roles of the two clocks clear if functional clock
rate configuration is needed later.
Fixes: 271546fb8e54 ("i2c: k1: add I2C driver support")
Reviewed-by: Heiko Schocher <[email protected]>
Reviewed-by: Yao Zi <[email protected]>
Signed-off-by: Junhui Liu <[email protected]>
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The K1 device tree describes separate functional and bus clocks for TWSI
controllers, but the SPL clock tree currently only provides their
functional clocks.
Add the bus clocks for TWSI2 and TWSI8, which are the TWSI controllers
currently used in SPL, along with their required parent clock chain.
TWSI8 uses a fixed-factor bus clock because its write-only clock control
register requires the functional and bus gate bits to remain combined in
a single clock instance.
Reviewed-by: Yao Zi <[email protected]>
Signed-off-by: Junhui Liu <[email protected]>
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The controller bus mode should be selected according to the requested
I2C bus speed. However, the driver currently passes the functional clock
rate to k1_i2c_set_bus_speed(), so the selected mode does not reflect
the requested bus speed.
Fix this by reading the clock-frequency property from the Device Tree,
defaulting to standard speed, and drop the unused clk_rate field.
Fixes: 271546fb8e54 ("i2c: k1: add I2C driver support")
Reviewed-by: Heiko Schocher <[email protected]>
Reviewed-by: Yao Zi <[email protected]>
Signed-off-by: Junhui Liu <[email protected]>
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Drop the redundant check that clk_bus.dev is valid before enabling it.
clk_enable() already calls clk_valid() which does the same check.
Link: https://patch.msgid.link/[email protected]
Signed-off-by: David Lechner <[email protected]>
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Pass the return value from clk_get_rate() instead of changing it to
-EINVAL. These return values are either ignored or logged, so it should
make debugging easier in the cases where it is logged.
Reviewed-by: Julien Stephan <[email protected]>
Link: https://patch.msgid.link/[email protected]
Signed-off-by: David Lechner <[email protected]>
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Check that priv->clk has been populated before trying to use it in the
MediaTek serial driver.
The clock is optional and may not be populated in all cases (in which
case it is expected that there was a fixed clock rate provided.)
Note this changes behavior slightly: previously, a populated clock
whose clk_get_rate() failed silently fell back to
priv->fixed_clk_rate (which is only set from DT when
clk_get_by_index() failed, so it would have been 0 here). Now an
error is returned instead.
Fixes: 3b17f2e2c2a9 ("serial: mtk: add support for using dynamic baud clock souce")
Signed-off-by: Suhrid Subramaniam <[email protected]>
Link: https://patch.msgid.link/[email protected]
Signed-off-by: David Lechner <[email protected]>
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Use ulong for return value of clk_get_rate() in the MediaTek serial
driver.
IS_ERR_VALUE() does a signed 64-bit comparison against the range of
possible error codes. If clk_get_rate() returns an error, assigning this
to a u32 truncates the top 32 bits making the value smaller, defeating
IS_ERR_VALUE() and producing a garbage divisor that hangs the UART.
Fixes: 3b17f2e2c2a9 ("serial: mtk: add support for using dynamic baud clock souce")
Signed-off-by: Suhrid Subramaniam <[email protected]>
Reviewed-by: Julien Stephan <[email protected]>
Link: https://patch.msgid.link/[email protected]
Signed-off-by: David Lechner <[email protected]>
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Add driver containing pinctrl register maps for MT8366.
Signed-off-by: Deep Pani <[email protected]>
Signed-off-by: Macpaul Lin <[email protected]>
Co-developed-by: David Lechner <[email protected]>
Reviewed-by: Julien Stephan <[email protected]>
Link: https://patch.msgid.link/[email protected]
Signed-off-by: David Lechner <[email protected]>
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Change the MediaTek pinctrl Kconfig to just have a single option for
all targets. This will simplify adding new targets and SPL support in
the future.
There is only one MediaTek target that does not have a pinctrl driver.
All other targets enable it by default so the configs don't have to
explicitly set it in addition to just enabling PINCTRL.
In the Makefile, we can use the target config symbol to automatically
select the correct driver. And the config selector on the common file
was redundant since we already have the same in the parent Makefile,
so it is dropped. Targets are also sorted while we are touching this.
Suggested-by: Quentin Schulz <[email protected]>
Closes: https://lore.kernel.org/u-boot/[email protected]/
Acked-by: Quentin Schulz <[email protected]>
Link: https://patch.msgid.link/20260807-mtk-pinctrl-kconfig-cleanup-v2-3-509a8f833181@baylibre.com
Signed-off-by: David Lechner <[email protected]>
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Remove #if conditionals that checked if PINCONF was enabled. The Kconfig
now selects PINCONF, so it will always be enabled and we don't need the
checks anymore.
Link: https://patch.msgid.link/20260807-mtk-pinctrl-kconfig-cleanup-v2-2-509a8f833181@baylibre.com
Signed-off-by: David Lechner <[email protected]>
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All MediaTek targets include pinconf registers so we should just always
select PINCONF instead of requiring each config to explicitly enable it.
MT8518 was the only target that didn't have PINCONF already enabled in
the defconfig, so it will be enabled there by default now. (This was
likely unintentional as the MT8518 driver does define pinconf registers
for drive and pull so supports pinconf operations.)
Link: https://patch.msgid.link/20260807-mtk-pinctrl-kconfig-cleanup-v2-1-509a8f833181@baylibre.com
Signed-off-by: David Lechner <[email protected]>
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Add support for MT6358 compatible PMICs to the MediaTek PMIC wrapper
driver. This has a different register map compared to other already
supported PMICs. It will be used initially for Genio 360 EVK support.
Reviewed-by: Julien Stephan <[email protected]>
Link: https://patch.msgid.link/[email protected]
Signed-off-by: David Lechner <[email protected]>
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Remove the duplicated info for mt8188 and mt8189 platforms in the
MediaTek PMIC wrapper driver. These both have a devicetree fallback
to mt8195. There are no differences relevant to U-Boot, so we can
avoid the duplication.
Reviewed-by: Julien Stephan <[email protected]>
Link: https://patch.msgid.link/[email protected]
Signed-off-by: David Lechner <[email protected]>
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Change clock names to match the upstream devicetree bindings. There
are no known devicetrees using these wrong names.
Fixes: 219c05f3f68e ("power: pmic: mtk-pwrap: add MediaTek PMIC Wrapper driver")
Reviewed-by: Julien Stephan <[email protected]>
Link: https://patch.msgid.link/[email protected]
Signed-off-by: David Lechner <[email protected]>
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Add a new driver for MediaTek MT6366 PMIC regulators. The register
layout is compatible with MT6358, so the driver itself is called
"mt6358". Only support for MT6366 is added currently for use with
the MediaTek Genio 360 EVK.
Reviewed-by: Julien Stephan <[email protected]>
Link: https://patch.msgid.link/[email protected]
Signed-off-by: David Lechner <[email protected]>
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Replace "mediatek,mt8188-nor" and "mediatek,mt8189-nor" with
"mediatek,mt8186-nor" in the mtk_snor driver. Both of these have
"mediatek,mt8186-nor" as a fallback, so we can use that instead of
adding each new compatible when we add more similar SoCs.
Reviewed-by: Julien Stephan <[email protected]>
Link: https://patch.msgid.link/20260806-mtk-snor-fallback-compatible-v1-1-74559b491b4a@baylibre.com
Signed-off-by: David Lechner <[email protected]>
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Add a compatible string match for MT8366 targets.
Reviewed-by: Julien Stephan <[email protected]>
Link: https://patch.msgid.link/[email protected]
Signed-off-by: David Lechner <[email protected]>
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Add a compatible string match and new PERI_ETH_BASE address for MT8366
targets.
Reviewed-by: Julien Stephan <[email protected]>
Link: https://patch.msgid.link/[email protected]
Signed-off-by: David Lechner <[email protected]>
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Add infrastructure to support future MediaTek platforms that have a
different PERI_ETH_BASE address. There are at least 3 different known
base address for this.
Reviewed-by: Julien Stephan <[email protected]>
Link: https://patch.msgid.link/[email protected]
Signed-off-by: David Lechner <[email protected]>
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Add devicetree compatible and match data for "mediatek,generic-tphy-v3"
in the MediaTek TPHY driver.
According to the Linux driver implementation, the only difference
between this and v2 is that v3 doesn't need to set slew rate. There is
one register write in the U-Boot driver that gets skipped because of
this now.
Also, according to the upstream devicetree bindings, mt8195 is also
v3 TPHY, so it gets updated as well.
Reviewed-by: Julien Stephan <[email protected]>
Link: https://patch.msgid.link/[email protected]
Signed-off-by: David Lechner <[email protected]>
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part_get_info_ubi() passes the UBI volume name straight to snprintf() as
its format argument:
snprintf(info->name, PART_NAME_LEN, vol->name);
A volume name that contains a '%' is then interpreted as a printf
conversion specifier, yielding a wrong partition name or reading
unintended variadic arguments; a '%n' would be undefined behaviour.
Volume names are user-defined and boot methods select images by volume
name, so copy the name through a "%s" format instead.
Fixes: aa5b67ce2262 ("disk: support UBI partitions")
Signed-off-by: Daniel Golle <[email protected]>
Reviewed-by: Heiko Schocher <[email protected]>
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The controller has a transfer-mode field that can run transmit-only or
receive-only instead of both, which leaves the unused FIFO out of the
transfer entirely. The driver never used it for that: claim_bus always
programmed TMOD_TR, and the only other mode came from an opportunistic
switch to TMOD_RO for read-only transfers.
A device described with spi-{tx,rx}-bus-width = <0> has no wire in that
direction at all, so now that the width reaches plat->mode as
SPI_NO_TX/SPI_NO_RX, pick the transfer mode from it. A write-only
display stops clocking receive bytes nobody reads.
The transmit-only case needs one more change. The 8-bit loop paces
itself on the receive FIFO and sets toread unconditionally, so with no
receive path it would wait on a FIFO that stays empty forever. Leave
toread at zero there and let the existing wait_till_not_busy() at the
end of the chunk handle completion, which is the same thing that
already covers a transmit component today.
The restore at the end of a read-only transfer went back to a hardcoded
TMOD_TR, which would undo the device's own mode. Restore what the mode
asks for instead.
Signed-off-by: Cole Munz <[email protected]>
Tested-by: Alexey Charkov <[email protected]>
Reviewed-by: Quentin Schulz <[email protected]>
Link: https://patch.msgid.link/3cf8dc75d461caf6076c35275021bbcdc0943de1.1787309754.git.Munzzyy1@proton.me
Signed-off-by: Quentin Schulz <[email protected]>
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The spi-peripheral-props binding shipped in dts/upstream allows a bus
width of 0, meaning no RX or TX is possible on this device. The
switches in spi_slave_of_to_plat() only handle 1/2/4/8, so a width of
0 falls through to the default case and warns "spi-rx-bus-width 0 not
supported" on every boot, even though the devicetree is valid per the
binding. The fact that the wire is missing is then dropped from
plat->mode.
Map 0 to new SPI_NO_TX/SPI_NO_RX mode bits, as Linux has done since
v5.12 ("spi: Add SPI_NO_TX/RX support", mainline d962608ce218).
Bits 16 and 17 are the first free mode bits.
Mapping the bits is not enough on its own, as Quentin pointed out:
nothing would stop a caller from asking for a transfer in a direction
that has no wire, and every controller driver would need its own
guard. Validate centrally in dm_spi_xfer() instead, matching Linux's
__spi_validate(): a din on a SPI_NO_RX device or a dout on a SPI_NO_TX
device fails with -EINVAL before it reaches the driver. A new sandbox
test covers both rejections.
This comes up on devices with no MISO line at all, such as a
write-only SPI display described with spi-rx-bus-width = <0>.
Signed-off-by: Cole Munz <[email protected]>
Acked-by: Quentin Schulz <[email protected]>
Link: https://patch.msgid.link/ae6a85d6f985b63c8f5a3fe8deeab89d79757b14.1787309754.git.Munzzyy1@proton.me
Signed-off-by: Quentin Schulz <[email protected]>
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The code was synced with linux-pinctrl/for-next (future linux-7.3) branch.
Signed-off-by: Mikhail Kshevetskiy <[email protected]>
Reviewed-by: Daniel Schwierzeck <[email protected]>
Tested-by: Daniel Schwierzeck <[email protected]>
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Use device managed GPIO and reset get to automatically free
those resources up. No functional change.
Signed-off-by: Marek Vasut <[email protected]>
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Avoid repeated link attempts for these controllers. In case the
controller link is up, this is a noop since the probe() already
finished. In case the controller link is down, a repeated link
up attempt seems to require reset of both PCIe controllers, which
is not desired. It is also unlikely that a repeated link attempt
would bring the link up, as U-Boot does not support hotplug anyway.
Therefore, prevent repeated link attempts.
Signed-off-by: Marek Vasut <[email protected]>
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Use generic request_firmware_into_buf_via_script() instead of local
implementation of similar functionality. This reduces code duplication.
Signed-off-by: Marek Vasut <[email protected]>
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Currently the driver can not report core status. Determine SCP core
state via SCP_CPUWAIT_WAIT bit and use SCMI PD protocol POWER_STATE_GET
call to determine CR52 and CA720AE core state. Report the core states.
Signed-off-by: Marek Vasut <[email protected]>
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Currently the driver could only start cores. Add support for stopping
CR52 and CA720AE cores via SCMI. Note that the SCP core is controlled
via direct register IO.
Signed-off-by: Marek Vasut <[email protected]>
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Use SCP core init code, which resets the SCP core, as a SCP core stop.
Once stop is invoked, the SCP core is reset and ready to be loaded with
new software, which is practical for SCP firmware development.
Signed-off-by: Marek Vasut <[email protected]>
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Replace devfdt_get_addr_index_ptr() with dev_read_addr_index_ptr() which
supports both live device tree and flat DT backends, avoiding direct
dependency on devfdt_* helpers.
No functional changes.
Signed-off-by: Peng Fan <[email protected]>
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Update N5X clock driver to support enabling or disabling
the peripheral clocks via clock driver model APIs.
The caller will pass the clock ID to this driver and the driver
will then proceed to manipulate the desired bit in the N5X clock
manager peripheral PLL register based on the given clock ID.
N5X_L4_SYS_FREE_CLK is a free-running clock with no gate control in
hardware, therefore attempting to enable or disable it is not applicable.
Return -EOPNOTSUPP for this clock ID and treat it as a no-op in
socfpga_clk_enable() and socfpga_clk_disable().
Signed-off-by: Alif Zakuan Yuslaimi <[email protected]>
Signed-off-by: Chen Huei Lok <[email protected]>
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The schedule() call after the break statement is unreachable.
Remove the dead code as it has no functional impact.
Signed-off-by: Dinesh Maniyam <[email protected]>
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Fix the wrong API used for memory free.
Signed-off-by: Dinesh Maniyam <[email protected]>
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Remove MEMBUS_CLKSLICE_REG source synchronous mode configuration to run
as source asynchronous mode.
Switching the HPS PLL to async mode improves resistance to clock
marginality issues such as F2S clk to HPS PLL
Signed-off-by: Alif Zakuan Yuslaimi <[email protected]>
Signed-off-by: Boon Khai Ng <[email protected]>
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Add a delay of 1ms before writing the address of the data for HIP
interface into the Responder Mailbox Read Address Register.
The UIBSSM mailbox require some time to settle down while waiting
for the MBRDADATA_VALID bit to become 1 without this delay,
specifically the board will timeout while waiting for
MBRDDATA_VALID bit to 1 after setting to 1.
This 1ms delay has been tested thoroughly and no intermittent issues
with UIBSSM mailbox communication is observed.
Signed-off-by: Alif Zakuan Yuslaimi <[email protected]>
Signed-off-by: Boon Khai Ng <[email protected]>
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SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS is already added in
SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET() macro.
Remove extra SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS in mpu1 address
computation.
Signed-off-by: Alif Zakuan Yuslaimi <[email protected]>
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Enable ECC scrubbing support for Gen5 by moving sdram_init_ecc_bits() from
sdram_arria10.c to a new common file, sdram_soc32.c which is shared by both
Arria10 and Gen5 devices. This makes ECC scrubbing support no longer
exclusive only to Arria10.
Remove legacy HW watchdog check in favor of current WDT DM for
Gen5/Arria10.
New Kconfig is introduced to enable this implementation only on the default
Arria10 and CycloneV boards as this will increase the SPL size which
will exceed some Gen5 devices' SPL size limit.
Signed-off-by: Tien Fong Chee <[email protected]>
Signed-off-by: Alif Zakuan Yuslaimi <[email protected]>
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Add DRAM size checking compare between size from device tree and actual
hardware.
Trigger hang if DRAM size from device tree is greater than actual hardware.
Display warning message if DRAM size mismatch between device tree and
actual hardware.
get_ram_size() uses size from device tree. So, it has consistency with
other device families.
New Kconfig is introduced to enable this implementation only on the default
CycloneV board as this will increase the SPL size which will exceed some
Gen5 devices' SPL size limit.
Signed-off-by: Alif Zakuan Yuslaimi <[email protected]>
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Excluding Stratix10 from legacy implementation of retrieving clkmgr base
address as Stratix10's clock driver is already following clock driver model
and is supporting enable/disable APIs.
The legacy devices' clock driver will continue to be refactored to support
driver model which enables us to support enable/disable APIs for all these
devices.
Signed-off-by: Alif Zakuan Yuslaimi <[email protected]>
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Refactor Stratix10 clock manager driver to support driver model, following
Agilex clock driver.
Create a new clock driver, clk-s10.c, for Stratix10 which supports the
driver model. This allows several APIs such as enable/disable clock, and
get clock rate to be supported.
This driver will be initialized during SPL to bring up the clock as early
as possible. The clock initialization process are refactored into this new
driver from clock_manager_s10.c during clock driver probe.
Excluding Stratix10 from legacy method of obtaining clkmgr base address in
mach-socfpga/misc.c as the base address is already obtained during clock
driver probe during SPL initialization.
Signed-off-by: Alif Zakuan Yuslaimi <[email protected]>
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Setting up firewall regions based on SDRAM memory banks configuration
(up to CONFIG_NR_DRAM_BANKS banks) instead of using whole address space.
First 1 MiB (0 to 0xfffff) of SDRAM is configured as secure region,
other address spaces are non-secure regions. The ARM Trusted Firmware (ATF)
image is located in this first 1 MiB memory region. So, this can prevent
software executing at non-secure state EL0-EL2 and non-secure masters
access to secure region.
Add common function for firewall setup and reuse for all SoC64 devices.
Signed-off-by: Alif Zakuan Yuslaimi <[email protected]>
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