| Age | Commit message (Collapse) | Author |
|---|
|
Commit de1d786e (add support for Xilinx 1000BASE-X phy (GTX)) introduced the
checking for ESTATUS_1000_XHALF, but it incorrectly sets the
SUPPORTED_1000baseX_Full flag in this case.
Set the SUPPORTED_1000baseX_Half flag instead.
Acked-by: Charles Coldwell <[email protected]>
Reviewed-By: Sascha Silbe <[email protected]>
Reviewed-by: Joe Hershberger <[email protected]>
Signed-off-by: Fabio Estevam <[email protected]>
|
|
de1d786 [add support for Xilinx 1000BASE-X phy (GTX)] introduced a
check for the extended status register in order to support
1Gbps-capable PHYs that don't have the 1000BASE-T registers. Since
Extended Status only indicates what the PHY (i.e. the local side) is
capable of, this broke communication with non-1Gbps peers.
Only check the extended status if the 1000BASE-T registers are
actually missing so we don't end up setting speed to 1Gbps even though
the previous test (for the combination of local and peer support for
1Gbps) already indicated we can't do 1Gbps with the current peer.
Signed-off-by: Sascha Silbe <[email protected]>
Tested-by: Fabio Estevam <[email protected]>
Reviewed-by: Joe Hershberger <[email protected]>
|
|
|
|
Dealing with the sys ctrl register should touch only the
relevant bits and not accidently the whole register. On i.MX6,
the sys control register contains bits which shouldn't be reset to
0, e.g. SYS_CTRL[3-0] and IPP_RST_N (SYS_CTRL[23]).
Do this by read/modify/write instead of just a 32bit write.
Signed-off-by: Dirk Behme <[email protected]>
Acked-by: Stefano Babic <[email protected]>
Signed-off-by: Andy Fleming <[email protected]>
|
|
1. No contents of "asm/arch/clk.h" is used within "dw_mmc.c".
2. If arch doesn't have "asm/arch/clk.h" driver won't build.
Without mentioned inclusion dw_mmc driver could be built for arches
other than ARM. For ARM driver still builds without it.
Signed-off-by: Alexey Brodkin <[email protected]>
Cc: Mischa Jonker <[email protected]>
Cc: Andy Fleming <[email protected]>
Cc: Rajeshwari Shinde <[email protected]>
Cc: Amar <[email protected]>
Cc: Minkyu Kang <[email protected]>
Cc: Jaehoon Chung <[email protected]>
Signed-off-by: Andy Fleming <[email protected]>
|
|
Fill the right command type when using CMD12 to stop data transfer.
Signed-off-by: Haijun Zhang <[email protected]>
CC: Fleming Andrew-AFLEMING <[email protected]>
CC: Scott Wood <[email protected]>
Signed-off-by: Andy Fleming <[email protected]>
|
|
Add support for Atmel TPM devices with two wire interface.
Signed-off-by: Dirk Eibach <[email protected]>
Signed-off-by: Reinhard Pfau <[email protected]>
Reviewed-by: Simon Glass <[email protected]>
Signed-off-by: Andy Fleming <[email protected]>
|
|
if alen is 0: no longer start a write cycle before reading data.
Signed-off-by: Dirk Eibach <[email protected]>
Signed-off-by: Reinhard Pfau <[email protected]>
Acked-by: Heiko Schocher <[email protected]>
Signed-off-by: Andy Fleming <[email protected]>
|
|
|
|
The driver triggered a BUG() in nand_base.c:3214/nand_scan_tail()
because the ecc.strength was not set in NAND_ECC_HW_SYNDROME ECC
mode.
Signed-off-by: Marek Vasut <[email protected]>
Cc: Benoit Thebaudeau <[email protected]>
Cc: Fabio Estevam <[email protected]>
Cc: Scott Wood <[email protected]>
Cc: Stefano Babic <[email protected]>
|
|
Fix a trivial conflict in arch/arm/dts/exynos5250.dtsi about gpio and
serial.
Conflicts:
arch/arm/dts/exynos5250.dtsi
Signed-off-by: Tom Rini <[email protected]>
|
|
|
|
The MX28 multi-layer AHB bus can be too slow and trigger the
FEC DMA too early, before all the data hit the DRAM. This patch
ensures the data are written in the RAM before the DMA starts.
Please see the comment in the patch for full details.
This patch was produced with an amazing help from Albert Aribaud,
who pointed out it can possibly be such a bus synchronisation
issue.
Signed-off-by: Marek Vasut <[email protected]>
Cc: Albert ARIBAUD <[email protected]>
Cc: Fabio Estevam <[email protected]>
Cc: Stefano Babic <[email protected]>
Tested-by: Fabio Estevam <[email protected]>
Tested-by: Alexandre Pereira da Silva <[email protected]>
|
|
Remove incorrectly called and duplicate flush_dcache_range() call
from fec_mxc driver. The call is not needed, since the caches are
already flushed in fec_tbd_init(), moreover the second argument should
be the ending address, not size.
Signed-off-by: Marek Vasut <[email protected]>
Reported-by: Albert Aribaud <[email protected]>
Cc: Stefano Babic <[email protected]>
Cc: Tom Rini <[email protected]>
|
|
Tegra30 and Tegra114 are compatible except PLL parameters.
Tested on Tegra30 Cardhu, and Tegra114 Dalmore
platforms. All works well.
Signed-off-by: Jim Lin <[email protected]>
Signed-off-by: Tom Warren <[email protected]>
|
|
|
|
Newer gcc versions warn about unused variables. This patch corrects a few of
those warnings that popped up in a build for the palmtreo680 board.
Signed-off-by: Mike Dunn <[email protected]>
|
|
The DFU's state machine original implementation author and copyright were
missing.
Signed-off-by: Lukasz Majewski <[email protected]>
Acked-by: Stefan Schmidt <[email protected]>
|
|
|
|
This patch resolves the below mentioned compilation error of i2c driver
for non-FDT case
Compilation error:
s3c24x0_i2c.c: In function 'board_i2c_init':
s3c24x0_i2c.c:544:18: error: 'CONFIG_MAX_I2C_NUM' undeclared (first use
in this function) s3c24x0_i2c.c:544:18: note: each undeclared
identifier is reported only once for each function it appears in
s3c24x0_i2c.c:545:3: warning: implicit declaration of function
Signed-off-by: Rajeshwari Shinde <[email protected]>
Signed-off-by: Amar <[email protected]>
Signed-off-by: Minkyu Kang <[email protected]>
|
|
Code for checking "splashpos" environment variable is
duplicated in drivers, move it to the common function.
Call this function also in the bmp display command to
consider "splashpos" settings.
Signed-off-by: Anatolij Gustschin <[email protected]>
Acked-by: Otavio Salvador <[email protected]>
|
|
Add support for disabling battery charging with ctrl+C keyboard
combination pressed.
Moreover the battery update is done more frequently.
Signed-off-by: Lukasz Majewski <[email protected]>
Cc: Tom Rini <[email protected]>
Signed-off-by: Minkyu Kang <[email protected]>
|
|
For the first eMMC read of data for upload, use the "large" dfu_buf (now
configurable) instead of usb request buffer allocated at composite layer
(which is 4KiB) [*].
For eMMC the whole file is read, which usually is larger than the buffer [*]
provided with usb request.
Signed-off-by: Lukasz Majewski <[email protected]>
Cc: Tom Rini <[email protected]>
Cc: Pantelis Antoniou <[email protected]>
Cc: Marek Vasut <[email protected]>
Cc: Heiko Schocher <[email protected]>
|
|
In the following commit:
"dfu: Support larger than memory transfers."
SHA1: ea2453d56b8860dbd18a3c517531ffc8dcb5c839
The ext4{read|write} command formatting has been changed. It removed
a write mandatory [sizebytes] parameter.
It extents DFU_FS_EXT4 case at mmc_file_op to provide mandatory
parameter for DFU write.
Signed-off-by: Lukasz Majewski <[email protected]>
Cc: Tom Rini <[email protected]>
Cc: Pantelis Antoniou <[email protected]>
Cc: Marek Vasut <[email protected]>
Cc: Heiko Schocher <[email protected]>
|
|
|
|
The omap_gpio driver is used by AM33XX, OMAP3/4, OMAP54XX and DRA7XX SoCs.
These SoCs have different gpio count but currently omap_gpio driver uses hard
coded 192 which is wrong.
This patch fixes this issue by:
1. Move define of OMAP_MAX_GPIO to all arch/arm/include/asm/arch-omap*/gpio.h.
2. Update gpio bank settings and enable GPIO modules 7 & 8 clocks for OMAP5.
Thanks for Lubomir Popov to provide valuable comments to fix this issue.
Signed-off-by: Axel Lin <[email protected]>
Tested-by: Lubomir Popov <[email protected]>
Acked-by: Heiko Schocher <[email protected]>
|
|
This patch fix the omap access to the transceiver
configuration registers using the ulpi bus. As reported by
the documentation the bit31 is used only to check if the
transaction is done or still running and the reading and
writing operation have different offset and have different
values. What we need to do at the end of a transaction is
leave the bus in done state. Anyway an error using the ulpi
omap register is not recoverable so any error give out the
usage of this interface.
Tested on a custom OMAP5430 board with a TUSB1210 ULPI PHY
on USBB1.
Signed-off-by: Michael Trimarchi <[email protected]>
Acked-by: Igor Grinberg <[email protected]>
Tested-by: Lubomir Popov <[email protected]>
Cc: Stefano Babic <[email protected]>
Cc: Marek Vasut <[email protected]>
Cc: Tom Rini <[email protected]>
|
|
Create splash.c/h to put the function and any future common splash
screen code in.
Signed-off-by: Robert Winkler <[email protected]>
Acked-by: Igor Grinberg <[email protected]>
|
|
This patch change 'data_to_send' array to static to avoid
unaligned access exeption on some platforms (ex Trats2).
Signed-off-by: Piotr Wilczek <[email protected]>
Signed-off-by: Kyungmin Park <[email protected]>
CC: Minkyu Kang <[email protected]>
CC: Anatolij Gustschin <[email protected]>
|
|
|
|
This trivial patch adds the definition of the vid/pid for the Ver C1 of the
USB Ethernet adapter D-Link DUB-E100.
Signed-off-by: Pierre Aubert <[email protected]>
CC: Marek Vasut <[email protected]>
|
|
This subtle change fix problem with too small amount of allocated
memory to store DFU function pointers.
One needs to allocate extra space for sentinel NULL pointer in this array
of function pointers.
With the previous code, the NULL value overwrites malloc internal data
and afterwards free(f_dfu->function) crashes.
Signed-off-by: Lukasz Majewski <[email protected]>
Signed-off-by: Kyungmin Park <[email protected]>
Cc: Marek Vasut <[email protected]>
|
|
Signed-off-by: Heiko Schocher <[email protected]>
Cc: Marek Vasut <[email protected]>
Cc: Ilya Yanok <[email protected]>
|
|
add a weak dummy function g_dnl_fixup to add the possibility to update
the device_desc board specific. Used on the upcoming siemens board
support, where idVendor and idProduct is stored in an eeprom.
Signed-off-by: Heiko Schocher <[email protected]>
Cc: Marek Vasut <[email protected]>
Cc: Lukasz Majewski <[email protected]>
Cc: Kyungmin Park <[email protected]>
Reviewed-by: Lukasz Majewski <[email protected]>
|
|
- set in to_dfu_mode() f_dfu->dfu_state = DFU_STATE_dfuIDLE
as after every to_dfu_mode call this is done, so move
this into to_dfu_mode
- switch in dfu_bind() into dfu mode:
This fixes wrong "dfu-util -l" output, when calling
"dfu-util -l" after a board reset, without doing a
download before. See also discussion here:
http://lists.denx.de/pipermail/u-boot/2013-June/157272.html
Signed-off-by: Heiko Schocher <[email protected]>
Cc: Lukasz Majewski <[email protected]>
Cc: Pantelis Antoniou <[email protected]>
Cc: Tom Rini <[email protected]>
Cc: Kyungmin Park <[email protected]>
Cc: Marek Vasut <[email protected]>
Cc: Wolfgang Denk <[email protected]>
Cc: Samuel Egli <[email protected]>
Acked-by: Lukasz Majewski <[email protected]>
Tested-by: Lukasz Majewski <[email protected]>
|
|
This patch memcpy is used instead of an assignment to
avoid unaligned access execption on some ARM platforms.
Signed-off-by: Piotr Wilczek <[email protected]>
Signed-off-by: Kyungmin Park <[email protected]>
CC: Lukasz Majewski <[email protected]>
Tested-by: Heiko Schocher <[email protected]>
Acked-by: Heiko Schocher <[email protected]>
|
|
This patch use get|put_unaligned_le16 to access structure data
to avoid data abort on some ARM platforms.
Signed-off-by: Piotr Wilczek <[email protected]>
Signed-off-by: Kyungmin Park <[email protected]>
CC: Marek Vasut <[email protected]>
|
|
Dfu transfer uses a buffer before writing data to the
raw storage device. Make the size (in bytes) of this buffer
configurable through environment variable "dfu_bufsiz".
Defaut value is configurable through CONFIG_SYS_DFU_DATA_BUF_SIZE
Signed-off-by: Heiko Schocher <[email protected]>
Cc: Pantelis Antoniou <[email protected]>
Cc: Tom Rini <[email protected]>
Cc: Lukasz Majewski <[email protected]>
Cc: Kyungmin Park <[email protected]>
Cc: Marek Vasut <[email protected]>
Cc: Wolfgang Denk <[email protected]>
Acked-by: Tom Rini <[email protected]>
|
|
|
|
Currently we have the following on boot:
CPU: Freescale i.MX28 rev1.2 at 454 MHz
BOOT: SSP SD/MMC #0, 3V3
DRAM: 128 MiB
MMC: MXS MMC: 0
Video: MXSFB: 'videomode' variable not set!In: serial
Break the line of the warning message in order to have a better reading format.
Signed-off-by: Fabio Estevam <[email protected]>
|
|
Newer gcc versions warn about unused variables. This patch corrects a few of
those warnings that popped up in a build for the palmtreo680 board.
Signed-off-by: Mike Dunn <[email protected]>
|
|
Signed-off-by: Eric Nelson <[email protected]>
|
|
Signed-off-by: Axel Lin <[email protected]>
|
|
Signed-off-by: Axel Lin <[email protected]>
|
|
Signed-off-by: Axel Lin <[email protected]>
|
|
Signed-off-by: Axel Lin <[email protected]>
|
|
With CONFIG_SYS_64BIT_LBA, lbaint_t gets defined as a 64-bit type,
which is required to represent block numbers for storage devices that
exceed 2TiB (the block size usually is 512B), e.g. recent hard drives.
For some obscure reason, the current U-Boot code uses lbaint_t for the
number of blocks to read (a rather optimistic estimation of how RAM
sizes will evolve), but not for the starting address. Trying to access
blocks beyond the 2TiB boundary will simply wrap around and read a
block within the 0..2TiB range.
We now use lbaint_t for block start addresses, too. This required
changes to all block drivers as the signature of block_read(),
block_write() and block_erase() in block_dev_desc_t changed.
Signed-off-by: Sascha Silbe <[email protected]>
|
|
The spi clock divisor is of the form x * (2**y), or x << y, where x is
1 to 16, and y is 0 to 15. Note the similarity with floating point numbers.
Convert the desired divisor to the smallest number which is >= desired divisor,
and can be represented in this form. The previous algorithm chose a divisor
which could be almost twice as large as needed.
Signed-off-by: Troy Kisky <[email protected]>
Signed-off-by: Dirk Behme <[email protected]>
|
|
Fix two issues with the calculation of pre_div and post_div:
1. pre_div: While the calculation of pre_div looks correct, to set the
CONREG[15-12] bits pre_div needs to be decremented by 1:
The i.MX 6Dual/6Quad Applications Processor Reference Manual (IMX6DQRM
Rev. 0, 11/2012) states:
CONREG[15-12]: PRE_DIVIDER
0000 Divide by 1
0001 Divide by 2
0010 Divide by 3
...
1101 Divide by 14
1110 Divide by 15
1111 Divide by 16
I.e. if we want to divide by 2, we have to write 1 to CONREG[15-12].
2. In case the post divider becomes necessary, pre_div will be divided by
16. So set pre_div to 16, too. And not 15.
Both issues above are tested using the following examples:
clk_src = 60000000 (60MHz, default i.MX6 ECSPI clock)
a) max_hz == 23000000 (23MHz, max i.MX6 ECSPI read clock)
-> pre_div = 3 (divide by 3 => CONREG[15-12] == 2)
-> post_div = 0 (divide by 1 => CONREG[11- 8] == 0)
=> 60MHz / 3 = 20MHz SPI clock
b) max_hz == 2000000 (2MHz)
-> pre_div = 16 (divide by 16 => CONREG[15-12] == 15)
-> post_div = 1 (divide by 2 => CONREG[11- 8] == 1)
=> 60MHz / 32 = 1.875MHz SPI clock
c) max_hz == 1000000 (1MHz)
-> pre_div = 16 (divide by 16 => CONREG[15-12] == 15)
-> post_div = 2 (divide by 4 => CONREG[11- 8] == 2)
=> 60MHz / 64 = 937.5kHz SPI clock
d) max_hz == 500000 (500kHz)
-> pre_div = 16 (divide by 16 => CONREG[15-12] == 15)
-> post_div = 3 (divide by 8 => CONREG[11- 8] == 3)
=> 60MHz / 128 = 468.75kHz SPI clock
Signed-off-by: Dirk Behme <[email protected]>
|
|
This patch adds the driver for keyboard that's controlled by ChromeOS EC.
Signed-off-by: Randall Spangler <[email protected]>
Signed-off-by: Simon Glass <[email protected]>
Signed-off-by: Vincent Palatin <[email protected]>
Signed-off-by: Hung-ying Tyan <[email protected]>
Acked-by: Simon Glass <[email protected]>
|
