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MMC core expects (now) valid mmc->dev pointer.
During conversion in commit cffe5d86 not every driver was updated.
This patch fixes crash while accessing MMC on
boards using Qualcomm SDHCI controller.
Signed-off-by: Mateusz Kulikowski <[email protected]>
Acked-by: Simon Glass <[email protected]>
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Return value of rtl_send_common propogates unmodified all the way
up to eth_send and further to API consumer if CONFIG_API is enabled.
Previously rtl_send_common returned number of bytes sent on success
which was erroneouly detected as error condition by API consumers
that checked for operation success by comparing return value with 0.
Switch rtl_send_common to use common convention: return 0 on success
and negative value for failure.
Cc: Stephen Warren <[email protected]>
Cc: Joe Hershberger <[email protected]>
Signed-off-by: Oleksandr Tymoshenko <[email protected]>
Reviewed-by: Simon Glass <[email protected]>
Acked-by: Joe Hershberger <[email protected]>
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This patch adds support for aquantia AQR106/107 PHY.
Signed-off-by: Mingkai Hu <[email protected]>
Signed-off-by: Gong Qianyu <[email protected]>
Acked-by: Joe Hershberger <[email protected]>
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Commit 90b7fc924adf "net: designware: support phy reset device-tree
bindings" made DW GMAC driver dependent on DM_GPIO by unconditional
usage of purely DM_GPIO stuff like:
* dm_gpio_XXX()
* gpio_request_by_name()
But since that driver as of today might be easily used without
DM_GPIO (that's the case for Synopsys AXS10x boards) we're
shielding all DM_GPIO things by ifdefs.
Signed-off-by: Alexey Brodkin <[email protected]>
Cc: Simon Glass <[email protected]>
Cc: Beniamino Galvani <[email protected]>
Cc: Joe Hershberger <[email protected]>
Cc: Sjoerd Simons <[email protected]>
Cc: Sonic Zhang <[email protected]>
Cc: Bin Meng <[email protected]>
Cc: Marek Vasut <[email protected]>
Reviewed-by: Simon Glass <[email protected]>
Acked-by: Joe Hershberger <[email protected]>
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This seems to give the best performance, so let's use it always.
Signed-off-by: Simon Glass <[email protected]>
Acked-by: Stephen Warren <[email protected]>
Signed-off-by: Tom Warren <[email protected]>
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We have standard drivers for panels and backlights which can do most of the
work for us. Move the tegra20 LCD driver over to use those instead of custom
code.
This patch includes device tree changes for the nvidia boards. I have only
been able to test seaboard. If this patch is applied, these boards will
also need to be synced with the kernel, and updated to use display-timings:
- colibri
- medcom-wide
- paz00
- tec
Signed-off-by: Simon Glass <[email protected]>
Signed-off-by: Tom Warren <[email protected]>
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On recent SoCs, tegra_pcie_phy_enable() isn't called; but instead
tegra_pcie_enable_controller() calls tegra_xusb_phy_enable(). However,
part of tegra_pcie_phy_enable() needs to happen in all cases. Move that
code to tegra_pcie_port_enable() instead.
For reference, NVIDIA's downstream Linux kernel performs this operation
in tegra_pcie_enable_rp_features(), which is called immediately after
tegra_pcie_port_enable(). Since that function doesn't exist in the U-Boot
driver, we'll just add it to the tail of tegra_pcie_port_enable() instead.
Signed-off-by: Stephen Warren <[email protected]>
Signed-off-by: Tom Warren <[email protected]>
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The value that should be programmed into the PADS_REFCLK register varies
per SoC. Fix the Tegra PCIe driver to program the correct values. Future
SoCs will require different values in cfg0/1, so the two values are stored
separately in the per-SoC data structures.
For reference, the values are all documented in NV bug 1771116 comment 20.
The Tegra210 value doesn't match the current TRM, but I've filed a bug to
get the TRM fixed. Earlier TRMs don't document the value this register
should contain, but the ASIC team has validated all these values, except
for the Tegra20 value which is simply left unchanged in this patch.
Signed-off-by: Stephen Warren <[email protected]>
Signed-off-by: Tom Warren <[email protected]>
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Waiting 30 seconds for the hpd to go high seems a bit much, especially
on headless boots. Lowering the timeout to 300ms.
Sending as RFC because frankly i don't know what a sensible timeout is
here, but 30 seconds is clearly not it :)
Signed-off-by: Sjoerd Simons <[email protected]>
Reviewed-by: Simon Glass <[email protected]>
Dropped RFC tag:
Signed-off-by: Simon Glass <[email protected]>
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Otherwise, ocassionally see errors like this:
Flashing sparse image at offset 2078720
Flashing Sparse Image
sdhci_send_command: Timeout for status update!
mmc fail to send stop cmd
write_sparse_image: Write failed, block #2181088 [0]
This does not affect the actual writing speed, which is controlled by
the default value:
CONFIG_SDHCI_CMD_DEFAULT_TIMEOUT
It only increases the retries when reading:
SDHCI_INT_STATUS
to avoid the timeout error.
Signed-off-by: Steve Rae <[email protected]>
Reviewed-by: Stefan Roese <[email protected]>
Tested-by: Masahiro Yamada <[email protected]>
Tested-by: Jaehoon Chung <[email protected]>
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Correcting QSPI disable/unselect CS reset value.
CTRL_CORE_CONTROL_IO_2: QSPI_MEMMAPPED_CS[10:8]
This is not causing any issue, but its better
to untouch the reserved bits.
Praneeth Bajjuri <[email protected]>
Signed-off-by: Ravi Babu <[email protected]>
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Signed-off-by: Masahiro Yamada <[email protected]>
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SPL does not use all of the devices, so we can save some memory
footprint.
Signed-off-by: Masahiro Yamada <[email protected]>
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PH1-LD4 and PH1-sLD8 SoCs have pins that support pin configuration
(pin biasing, drive strength control), but not pin-muxing.
Allow to fill the mux value table with -1 for those pins; pins with
mux value -1 will be skipped in the pin-mux set function. The mux
value type should be changed from "unsigned" to "int" in order to
accommodate -1 as a special case.
[ Linux commit: 363c90e743b50a432a91a211dd8b078d9df446e9 ]
Signed-off-by: Masahiro Yamada <[email protected]>
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PH1-LD11 and PH1-LD20 have much pin controlling in common, so I
added a single driver shared between them in the initial commit.
However, the Ethernet pin-mux settings I am going to add are
different with each other, and they may diverge more as the
progress of development. Split it into two dedicated drivers.
Signed-off-by: Masahiro Yamada <[email protected]>
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Currently, the UniPhier pinctrl driver itself is a syscon, but it
turned out much more reasonable to make it a child node of a syscon
because our syscon node consists of a bunch of system configuration
registers, not only pinctrl, but also phy, and misc registers.
It is difficult to split the node. This commit allows to migrate to
the new DT structure.
Signed-off-by: Masahiro Yamada <[email protected]>
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This SoC does not support NAND CS1. This place-holder is no longer
necessary.
Signed-off-by: Masahiro Yamada <[email protected]>
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My mistake in the initial support patch.
Signed-off-by: Masahiro Yamada <[email protected]>
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These are pin group names, not function names.
Signed-off-by: Masahiro Yamada <[email protected]>
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Freescale ARMv8 SoC name ends with "A" to represent ARM SoCs.
like LS2080A, LS1043A, LS1012A.
So append "A" to SoC names.
Signed-off-by: Pratiyush Mohan Srivastava <[email protected]>
Signed-off-by: Prabhakar Kushwaha <[email protected]>
Reviewed-by: York Sun <[email protected]>
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Introudce wp_enable. To check WPSPL, wp_enable needs to be set
to 1 in board code.
Take i.MX6UL for example, for some boards, they do not use WP singal,
so they does not configure USDHC1_WP_SELECT_INPUT, and its default
value is 0(GPIO1_IO02). However GPIO1_IO02 is muxed for i2c usage and
SION bit set. So USDHC controller can always get wp signal and WPSPL
shows write protect and blocks driver continuing. This is not what
we want to see, so add wp_enable, and if set to 0, just omit the
WPSPL checking and this does not effect normal working of usdhc
controller.
If wp-gpios is provided in dts, wp_enable is set to 1, otherwise 0.
Signed-off-by: Peng Fan <[email protected]>
Cc: Pantelis Antoniou <[email protected]>
Cc: York Sun <[email protected]>
Cc: Stefano Babic <[email protected]>
Cc: Fabio Estevam <[email protected]>
Tested-by: Fabio Estevam <[email protected]>
Reviewed-by: York Sun <[email protected]>
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The USDHC moves the 4 clock bits CARD_CLK_SOFT_EN, IPG_PERCLK_SOFT_EN,
HCLK_SOFT_EN, and IPG_CLK_SOFT_EN from sysctl register to vendorspec
register. The driver uses RSTA to replace the clock gate off
operation. But this is not a good solution because:
1. when using RSTA, we should wait this bit to clear by itself. This is not
implemeneted in the code.
2. After RSTA is set, it is recommended that the Host Driver reset the
external card and reinitialize it.
So in this patch, we change to use the vendorspec registers for these bits
operation.
Signed-off-by: Ye Li <[email protected]>
Signed-off-by: Peng Fan <[email protected]>
Cc: York Sun <[email protected]>
Cc: Stefano Babic <[email protected]>
Cc: Pantelis Antoniou <[email protected]>
Cc: Fabio Estevam <[email protected]>
Tested-by: Fabio Estevam <[email protected]>
Reviewed-by: York Sun <[email protected]>
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When booting in eMMC fast boot, MMC host does not exit from
boot mode after bootrom loading image. So the first command
'CMD0' sent in uboot will pull down the CMD line to low and
cause errors.
This patch cleans the MMC boot register in "mmc_init" to put the
MMC host back to normal mode.
Also clear DLL_CTRL delay line settings at USDHC initialization
to eliminate the pre-settings from boot rom.
Signed-off-by: Peng Fan <[email protected]>
Cc: Pantelis Antoniou <[email protected]>
Cc: York Sun <[email protected]>
Cc: Stefano Babic <[email protected]>
Cc: Fabio Estevam <[email protected]>
Tested-by: Fabio Estevam <[email protected]>
Reviewed-by: York Sun <[email protected]>
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- update fastboot_okay() and fastboot_fail()
This file originally came from upstream code.
While retaining the storage abstraction feature, this is the second
set of the changes required to resync with the
cmd_flash_mmc_sparse_img()
in the file
aboot.c
from
https://us.codeaurora.org/cgit/quic/la/kernel/lk/plain/app/aboot/aboot.c?h=LE.BR.1.2.1
Signed-off-by: Steve Rae <[email protected]>
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This "session-id" alogrithm is not required, and currently corrupts
the stored image whenever more the one "session" is required.
Signed-off-by: Steve Rae <[email protected]>
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These condition checking are wrong.
Original Author's intention might be "&" instead of "&&".
It can know whether receive or transmit data request with
BIT[4]/BIT[5] of RINTSTS register.
Signed-off-by: Jaehoon Chung <[email protected]>
Signed-off-by: Minkyu Kang <[email protected]>
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The USBNC_PHYCFG2_ACAENB bit should be cleared to enable the
OTG ID detection, not set it. When the bit is set, the ACA
Resistance Detection is enabled, which disables the OTG ID
detection, because the internal pull up is off.
Signed-off-by: Ye Li <[email protected]>
Signed-off-by: Peng Fan <[email protected]>
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There is a 4 bytes hole between phy_cfg2 and phy_status, fix the
usbnc_regs structure to include the hole.
Signed-off-by: Ye Li <[email protected]>
Signed-off-by: Peng Fan <[email protected]>
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Fixes NULL terminating issue for usb controller name string by using
sizeof operator.
Signed-off-by: Rajesh Bhagat <[email protected]>
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clk->id is unsigned, so it can't be < 0. Remove the check for that.
FWIW, this issue was introduced when the clock API converted e.g.
clk_get_rate()'s clock ID parameter from an int to an unsigned long
(with a struct clk), without removing this check.
Fixes: 135aa9500264 ("clk: convert API to match reset/mailbox style")
Reported-by: Coverity Scan
Signed-off-by: Stephen Warren <[email protected]>
Acked-by: Simon Glass <[email protected]>
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This empty line should not be there. Remove it.
Signed-off-by: Andre Renaud <[email protected]>
Reviewed-by: Andreas Bießmann <[email protected]>
Signed-off-by: Simon Glass <[email protected]>
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Commit a058052c "net: phy: do not read configuration register on reset",
changes the behaviour of the phy_reset function such that the state of
the BMCR register is not preserved during reset.
Change the config function for the m88e1310 so that it does not do a
reset after configuring auto-negotiation.
Signed-off-by: Nathan Rossi <[email protected]>
Cc: Joe Hershberger <[email protected]>
Cc: Michal Simek <[email protected]>
Cc: Stefan Roese <[email protected]>
Acked-by: Michal Simek <[email protected]>
Acked-by: Joe Hershberger <[email protected]>
Reviewed-by: Stefan Roese <[email protected]>
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This patch adds a phy driver for the Micrel KSZ886x switches.
Similarly to the KSZ8895, SoC MAC is directly connected to the switch
MAC on the switch CPU port, so the link to the switch is always up.
KSZ886x switches can be used in the following configuration modes:
- Unmanaged mode with config stored in external EEPROM
- Managed mode over SPI
- Managed mode over I2C
- Managed mode over mdio/mdc (aka MIIM or SMI)
This patch supports only unmanaged and MIIM modes.
Based on Micrel KSZ886x driver from Linux kernel and
Micrel KSZ8895 driver from U-Boot.
Verified with the KSZ8863MLL.
Signed-off-by: Alexey Firago <[email protected]>
Acked-by: Joe Hershberger <[email protected]>
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The rtl8169 driver uses a global variable to store the register address
of the adapter being operated upon. This is updated to point at the
correct adapter when sending or receiving a packet, or shutting down the
adapter, but not when initializing the adapter. Consequently, switching
between different adapters within the same U-Boot runtime does not work
correctly since the driver programs the wrong registers during
rtl8169_eth_start() -> rtl8169_common_start() -> rtl8169_hw_start().
Note that since rtl8169_eth_stop() does set the global variable, the
second consecutive attempt to use the "new" adapter did work even before
this patch, because each time network usage is shut down, the network
core calls stop, which sets the variable so that the next start does
actually initialize the hardware, and the adapter works.
Equally, rtl8169_eth_probe() calls rtl_init() which sets the global, so
if using only a single device, or if picking the "right" device (based on
probe order) when multiple devices are present, ioaddr will already be set
correctly from the get-go, so the issue does not occur.
Signed-off-by: Stephen Warren <[email protected]>
Acked-by: Joe Hershberger <[email protected]>
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Signed-off-by: Stefan Wahren <[email protected]>
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Some drivers are still directly accessing the chip->mtd field. Patch
them to use nand_to_mtd() instead.
Signed-off-by: Boris Brezillon <[email protected]>
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follow parameter name change (nand to mtd) to fix compiler error.
Signed-off-by: Max Krummenacher <[email protected]>
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NAND chips are supposed to expose their capabilities through advanced
mechanisms like READID, ONFI or JEDEC parameter tables. While those
methods are appropriate for the bootloader itself, it's way to
complicated and takes too much space to fit in the SPL.
Replace those mechanisms by a dumb 'trial and error' mechanism.
With this new approach we can get rid of the fixed config list that was
used in the sunxi NAND SPL driver.
Signed-off-by: Boris Brezillon <[email protected]>
Acked-by: Hans de Goede <[email protected]>
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Split the 'load page' and 'read page' logic in 2 different functions so
we can later load the page and test different ECC configs without the
penalty of reloading the same page in the NAND cache.
We also move common setup to a dedicated function (nand_apply_config()) to
avoid rewriting the same values in NFC registers each time we read a page.
These new functions are passed a pointer to an nfc_config struct to limit
the number of parameters.
Signed-off-by: Boris Brezillon <[email protected]>
Acked-by: Hans de Goede <[email protected]>
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check_value_xxx() helpers are using a 1ms delay between each test, which
can be quite long for some operations (like a page read on an SLC NAND).
Since we don't have anything to do but to poll this register, reduce the
delay between each test to 1us.
While we're at it, rename the max_number_of_retries parameters and the
MAX_RETRIES macro into timeout_us and DEFAULT_TIMEOUT_US to reflect that
we're actually waiting a given amount of time and not only a number of
retries.
Signed-off-by: Boris Brezillon <[email protected]>
Acked-by: Hans de Goede <[email protected]>
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Use CONFIG_SYS_NAND_U_BOOT_OFFS_REDUND value instead of trying to guess
where the redundant u-boot image is based on simple (and most of the time
erroneous) heuristics.
Signed-off-by: Boris Brezillon <[email protected]>
Acked-by: Hans de Goede <[email protected]>
# Conflicts:
# drivers/mtd/nand/sunxi_nand_spl.c
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On modern NAND it's more than recommended to have a backup copy of the
u-boot binary to recover from corruption: bitflips are quite common on
MLC NANDs, and the read-disturbance will corrupt your u-boot partitition
more quickly than what you would see on an SLC NAND.
Add an extra Kconfig option to specify the offset of the redundant u-boot
image.
Signed-off-by: Boris Brezillon <[email protected]>
Acked-by: Hans de Goede <[email protected]>
[scottwood: added ifdef to fix build break]
Signed-off-by: Scott Wood <[email protected]>
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The SYS_NAND_U_BOOT_OFFS is quite generic, but the Kconfig entry is forced
to explicitly depend on platforms that are not already defining it in their
include/configs/<board>.h header.
Add the SYS_NAND_U_BOOT_LOCATIONS option, make the SYS_NAND_U_BOOT_OFFS
depends on it, remove the dependency on NAND_SUNXI and make it dependent
on SPL selection.
Signed-off-by: Boris Brezillon <[email protected]>
Acked-by: Hans de Goede <[email protected]>
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The sunxi SPL NAND controller driver supports use 'BootROM'-like configs,
that is, configs where the ECC bytes and real data are interleaved in the
page instead of putting ECC bytes in the OOB area.
Doing that has several drawbacks:
- since you're interleaving data and ECC bytes you can't use the whole page
otherwise you might override the bad block marker with non-FF bytes.
- to solve the bad block marker problem, the ROM code supports partially
using the page, but this introduces a huge penalty both in term of read
speed and NAND memory usage. While this is fine for rather small
binaries(like the SPL one which is at maximum 24KB large), it becomes
non-negligible for the bootloader image (several hundred of KB).
- auto-detection of the page size is not reliable (this is in my opinion
the biggest problem). If you get the page size wrong, you'll end up
reading data at a different offset than what was specified by the caller
and the reading may succeed (if valid data were written at this address).
For all those reasons I think it's wiser to completely remove support for
'syndrome' configs. If we ever need to support it again, then I'd recommend
specifying all the config parameters through Kconfig options.
Signed-off-by: Boris Brezillon <[email protected]>
Acked-by: Hans de Goede <[email protected]>
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