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On the A64 the clock for the first USB controller is actually the parent
of the clock for the second controller, so turning them off in that order
makes the system hang.
Fix this by only turning off *both* clocks when the *last* OHCI controller
is brought down. This covers the case when only one controller is used.
Signed-off-by: Andre Przywara <[email protected]>
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When using CONFIG_OF_BOARD on rpi to use the dtb provided by the
RaspberryPi Fundation, the compatible string isn't the same, resulting
in not-functional usb from u-boot.
Signed-off-by: Oleksandr Tymoshenko <[email protected]>
Signed-off-by: Emmanuel Vadot <[email protected]>
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Make the initialization sequence consistent with the Linux kernel
driver.
Reviewed-by: Stefan Roese <[email protected]>
Acked-by: Joe Hershberger <[email protected]>
Signed-off-by: Rabeeh Khoury <[email protected]>
Signed-off-by: Baruch Siach <[email protected]>
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This fixes sporadic timeout on initial packet Tx (usually ARP), with an
error message like:
timeout: packet not sent
Reviewed-by: Stefan Roese <[email protected]>
Tested-by: Chris Packham <[email protected]>
Acked-by: Joe Hershberger <[email protected]>
Signed-off-by: Rabeeh Khoury <[email protected]>
Signed-off-by: Baruch Siach <[email protected]>
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phyread can timeout and val will contain random value. Initialize it to
zero not to report random value in case of error.
Signed-off-by: Michal Simek <[email protected]>
Acked-by: Joe Hershberger <[email protected]>
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When using CONFIG_OF_BOARD on rpi to use the dtb provided by the
RaspberryPi Fundation, the compatible string isn't the same, resulting
in not-functional video in u-boot.
Signed-off-by: Oleksandr Tymoshenko <[email protected]>
Signed-off-by: Emmanuel Vadot <[email protected]>
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With the introduction of early timer support in the TSC driver,
the capability of getting clock rate from device tree was lost
unfortunately. Now we bring such functionality back, but with a
limitation that when TSC is used as early timer, specifying clock
rate from device tree does not work.
This fixes random boot failures seen on QEMU targets: printing "TSC
frequency is ZERO" and reset forever.
Signed-off-by: Bin Meng <[email protected]>
Reviewed-by: Simon Glass <[email protected]>
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Masking clock gate, reset register bits based on the
probed controller is proper only due to the assumption
that masking should start with 0 even thought the controller
has separate PHY or shared between OTG.
unfortunately these are fixed due to lack of separate
clock, reset drivers.
Say for example EHCI1 - EHCI3 in the datasheet (EHCI0 is for the OTG)
so we need to start reg_mask 0 - 2.
This patch calculated the mask, based on the register base
so that we can get the proper bits to set with respect to
probed controller.
We even do this masking by using PHY index specifier from dt,
but dev_read_addr_size is failing for 64-bit boards.
Signed-off-by: Jagan Teki <[email protected]>
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For ohci, the maximam supported endpoint number is 32(in and out), and
now we have used (usb_pipeendpoint(pipe) << 1) to index the specified
endpoint descritor, usb_pipeendpoint(pipe) can reach 0xf, so we need
change the NUM_EDs from 8 to 32.
Signed-off-by: Zeng Tao <[email protected]>
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ohci-hcd casts priv_data pointer to (ohci_t *), thus it must be
the first member in private data struct.
Fixes 831cc98b1 ("usb: sunxi: Simplify ccm reg base code")
Signed-off-by: Vasily Khoruzhick <[email protected]>
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The N25Q256(A) datasheet clearly states that this device does have
a Flag Status Register and does update FSR PEC bit 7 during Program
and Erase cycles to indicate the cycle is in progress. Enable the
FSR PEC bit polling on this device to prevent data corruption.
Signed-off-by: Marek Vasut <[email protected]>
Cc: Jagan Teki <[email protected]>
Cc: Tom Rini <[email protected]>
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The claim/release bus function must not reset the whole SPI core because
settings regarding wordlen, clock-frequency and so on made by
set_wordlen, set_mode, set_speed get lost with this action. Resulting in
a non-functional SPI.
Without DM the failure didn't came up since after the spi_reset within
claim bus all the setup (wordlen, mode, ...) was called, in DM they are
called by the spi uclass.
We change now the things as following for having a working SPI instance
in DM:
- move the spi_reset(...) to the probe call in DM for having a known
hardware state after probe. Without DM we don't have a probe call, so we
issue the reset as before during the claim_bus call.
- in release bus we just reset the modulctrl to the reset-value (spi-
slave)
Signed-off-by: Hannes Schmelzer <[email protected]>
Reviewed-by: Jagan Teki <[email protected]>
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This bug is the combination of dwc2 USB controller and lan78xx
USB ethernet controller, which is the combination in use on
the Raspberry Pi Model 3 B+.
When the host attempts to receive a packet, but a packet has not
arrived, the lan78xx controller responds by setting BIR
(Bulk-In Empty Response) to NAK. Unfortunately, this hangs
the USB controller and requires the USB controller to
be reset.
The fix proposed is to have the lan78xx controller respond
by setting BIR to ZLP.
Signed-off-by: Andrew Thomas <[email protected]>
Tested-by: Peter Robinson <[email protected]>
Reviewed-by: Alexander Graf <[email protected]>
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For now, the existing SPL MXS NAND driver only supports to identify
ONFi-compliant NAND chips. In order to allow identifying
non-ONFi-compliant chips add `mxs_flash_full_ident()` which uses the
`nand_get_flash_type()` functionality from `nand_base.c` to lookup
for supported NAND chips in the chip ID list.
For compatibility reason the full identification support is only
available if the config option `CONFIG_SPL_NAND_IDENT` is enabled.
The lookup was tested on a custom i.MX6ULL board with a Toshiba
TC58NVG1S3HTAI0 NAND chip.
Signed-off-by: Jörg Krause <[email protected]>
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The existing `mxs_flash_ident()` is limited to identify ONFi compliant
NAND chips only. In order to support non-ONFi NAND chips refactor the
function and rename it to `mxs_flash_onfi_ident()`.
A follow-up patch will add `mxs_flash_full_ident()` which allows to use
the chip ID list to lookup for supported NAND flashs.
Signed-off-by: Jörg Krause <[email protected]>
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Add the config option `CONFIG_SPL_NAND_IDENT` for using the NAND chip ID list
to identify the NAND flash in SPL.
Signed-off-by: Jörg Krause <[email protected]>
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`nand_get_flash_type()` allows identification of supported NAND flashs.
The function is useful in SPL (like mxs_nand_spl.c) to lookup for a NAND
flash (which does not support ONFi) instead of using nand_simple.c and
hard-coding all required NAND parameters.
Signed-off-by: Jörg Krause <[email protected]>
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The PFUZE3000 uses registers addresses up to 0xff.
The DM pfuze100 driver supports both pfuze100 and pfuze3000. Allow it
to use the device type to return the correct number of registers.
Also rename the too generic PMIC_NUM_OF_REGS enumeration value for
pfuze3000 to match the other "PFUZE3000_" prefixed enumerations and the
pfuze100 enumeration value PFUZE100_NUM_OF_REGS.
Cc: Peng Fan <[email protected]>
Cc: Jaehoon Chung <[email protected]>
Cc: Stefano Babic <[email protected]>
Cc: Fabio Estevam <[email protected]>
Signed-off-by: Trent Piepho <[email protected]>
Reviewed-by: Fabio Estevam <[email protected]>
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Add support for specified ECC strength/size using device tree
properties nand-ecc-strength/nand-ecc-step-size.
This aligns behavior with the mainline driver, such that:
- If fsl,use-minimal-ecc is requested it will use data from
data sheet/ONFI. If this is not available the driver will fail.
- If nand-ecc-strength/nand-ecc-step-size are specified those
value will be used.
- By default maximum possible ECC strength is used
Signed-off-by: Stefan Agner <[email protected]>
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Support driver data from device tree. Also support fsl,use-minimal-ecc
similar to Linux' GPMI NAND driver.
Signed-off-by: Stefan Agner <[email protected]>
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Move structs into header file so we can use a separate compile
unit for device tree support.
Signed-off-by: Stefan Agner <[email protected]>
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Add use_minimum_ecc as struct mxs_nand_info field in preparation
for device tree support.
Signed-off-by: Stefan Agner <[email protected]>
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In preparation for device tree support separate board init
from controller init similar to other raw NAND drivers.
Signed-off-by: Stefan Agner <[email protected]>
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This function initializes DMA descriptors so mxs_nand_init_dma is
more precise. It also frees up the rather generic name mxs_nand_init.
Signed-off-by: Stefan Agner <[email protected]>
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Move GPMI and BCH register structs to the driver struct mxs_nand_info
in prepartion for device tree support.
Signed-off-by: Stefan Agner <[email protected]>
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Add support for minimum ECC strength supported by the NAND chip.
This aligns with the behavior when using the fsl,use-minimum-ecc
device tree property in Linux.
Signed-off-by: Stefan Agner <[email protected]>
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Report correct ECC parameters back to the stack. Do not report
bytes as we have it not immeaditly available and the Linux version
also does not report it. It seems to have no aversive effect.
Signed-off-by: Stefan Agner <[email protected]>
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Calculate BCH geometry at start and store the information in
a structure. This avoids recalculation on every page access
and allows to calculate ECC relevant information in one place.
This patch does not change ECC layout or driver behavior in
any way.
The patch aligns the driver somewhat with the Linux GPMI NAND
driver which drives the same IP.
Signed-off-by: Stefan Agner <[email protected]>
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Add config option which allows to enable on flash bad block table
support. This has the same effect as when using the device tree
property "nand-on-flash-bbt" in Linux.
Signed-off-by: Stefan Agner <[email protected]>
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Instead of completing initialization via scan_bbt callback use
NAND self init to initialize the GPMI (MXS) NAND controller.
Suggested-by: Scott Wood <[email protected]>
Signed-off-by: Stefan Agner <[email protected]>
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In preparation to convert the driver to use NAND self init
provide a new minimal init for SPL builds. As a side effect
this also reduces size of SPL by about 4KiB.
Signed-off-by: Stefan Agner <[email protected]>
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Change sector size to 256KiB in table spi_flash_ids.
Signed-off-by: Ashish Kumar <[email protected]>
Reviewed-by: Jagan Teki <[email protected]>
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commit 84807922874e03895bbf15c4472a2dcee8fbbd03
("spi: omap3: Skip set_mode, set_speed from claim") did break SPI
support on my AM335x board.
The named commit:
- ignored the responsible arguments (speed, mode)
The set speed/mode function must use the supplied function arguments to
work properly. With this commit we take those arguments and transfer
them to the priv-data.
- used wrong udevice pointer for getting priv data
the udevice-pointer within function argument is already the spi-bus
device, so it is wrong looking here for some parent (ocp-bus in this
case) and getting priv-pointer from there.
Signed-off-by: Hannes Schmelzer <[email protected]>
Reviewed-by: Jagan Teki <[email protected]>
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Otherwise the frequency is zero and the clock divider cannot be setup by
'omap3_spi_set_speed' function.
Signed-off-by: Hannes Schmelzer <[email protected]>
Reviewed-by: Jagan Teki <[email protected]>
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CS GPIO activation low/high is determinated by the device tree
so we don't need to take in accoung in cs_activate and cs_deactivate
Signed-off-by: Michael Trimarchi <[email protected]>
Reviewed-by: Peng Fan <[email protected]>
Reviewed-by: Jagan Teki <[email protected]>
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drivers/spi/mxc_spi.c:507: undefined reference to `dev_get_addr'
linux-ld.bfd: BFD (GNU Binutils) 2.29.1 assertion fail elf32-arm.c:9509
Signed-off-by: Michael Trimarchi <[email protected]>
Reviewed-by: Fabio Estevam <[email protected]>
Reviewed-by: Peng Fan <[email protected]>
Reviewed-by: Jagan Teki <[email protected]>
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This patch replaced "return 0" with "return status" to fix the
incorrect return value error reported by the coverity.
Reviewed-by: Michal Simek <[email protected]>
Signed-off-by: Vipul Kumar <[email protected]>
[jagan: rebased on master]
Signed-off-by: Jagan Teki <[email protected]>
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In Linux, the clock rate of the UART is given by the clock driver.
If you try to follow that in U-Boot, you would end up with adding
more u-boot,dm-pre-reloc properties, and also the clock driver would
be too big for SPL, which is used for UniPhier ARMv7 platform.
The current solution is to add 'clock-frequency' property to the
UART nodes, but it does not exist in the DT files in Linux. I do
not want to let DT diverge for U-Boot.
Check the SoC compatible and set the clock rate according to it.
This will be helpful to sync DT between Linux and U-Boot.
Signed-off-by: Masahiro Yamada <[email protected]>
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Just for making it shorter.
Signed-off-by: Masahiro Yamada <[email protected]>
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Signed-off-by: Masahiro Yamada <[email protected]>
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Use the clk framework to initialize clocks from drivers that need them
instead of having hardcoded frequencies and initializations from board
code.
Signed-off-by: Beniamino Galvani <[email protected]>
Signed-off-by: Neil Armstrong <[email protected]>
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Introduce a basic clock driver for Amlogic Meson SoCs which supports
enabling/disabling clock gates and getting their frequency.
Signed-off-by: Beniamino Galvani <[email protected]>
Signed-off-by: Neil Armstrong <[email protected]>
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The SARADC driver was merged after the following commit :
commit d35812368a59 ("regmap: change regmap_init_mem() to take ofnode instead udevice")
Thus breaking build, this patch fixes the regmap_init_mem accordingly.
Signed-off-by: Neil Armstrong <[email protected]>
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