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At the very early stage when PHY ID is being auto-detected, the
PHY device is not yet instantiated and rswitch_etha .phydev is
still NULL. Add missing check for this condition and perform C22
fallback access in this PHY ID auto-detection case.
Signed-off-by: Marek Vasut <[email protected]>
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While USB DFU boot works with this patch, but the non USB boot modes like
SD Boot and flash boot fails for J784S4 EVM device.
So, Reverting this patch.
This reverts commit bfb530e06ca6c19f66c079601e568c761a001993.
Signed-off-by: Prasanth Babu Mantena <[email protected]>
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Prevent the Qualcomm watchdog from autostarting and ensure it's stopped
when the driver probed. In some cases the watchdog is left running by
a previous bootloader stage. Disable autostart so it isn't left running
when we boot into the OS, this behaviour can be changed by enabling
autostart in the board defconfig.
Reviewed-by: Stefan Roese <[email protected]>
Reviewed-by: Sumit Garg <[email protected]>
Reviewed-by: Tom Rini <[email protected]>
Link: https://patch.msgid.link/[email protected]
Signed-off-by: Casey Connolly <[email protected]>
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Just stub out non-active votes, if we return an error the caller may
propagate it and not send its active vote. Since we don't suspend
there's no risk of us entering a broken state due to missing votes.
Link: https://patch.msgid.link/20260320-casey-qcom-rpmh-serial-fixes-v1-2-b81d05832eec@linaro.org
Signed-off-by: Casey Connolly <[email protected]>
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Pre-relocation we may not have a clock but it's usually been enabled for
us already, or worst case we will enable it after relocation. Erroring
out in this case will almost always cause U-Boot to hang pre-relocation
which is undesirable and may be hard to debug.
Link: https://patch.msgid.link/20260320-casey-qcom-rpmh-serial-fixes-v1-1-b81d05832eec@linaro.org
Signed-off-by: Casey Connolly <[email protected]>
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The DM_REGULATOR_QCOM_USB_VBUS functionality can only work with DM_PMIC
enabled as well, so express this dependency in Kconfig.
Signed-off-by: Tom Rini <[email protected]>
Link: https://patch.msgid.link/[email protected]
Signed-off-by: Casey Connolly <[email protected]>
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Add support for QCS615 QUSB2 PHY by introducing platform-specific
initialization table and register layout. The implementation reuses
the IPQ6018 register layout and defines QCS615-specific tuning
parameters for proper USB PHY operation.
Taken from Linux commit 8adbf20e0502 ("phy: qcom-qusb2: Add support for QCS615")
Signed-off-by: Balaji Selvanathan <[email protected]>
Reviewed-by: Sumit Garg <[email protected]>
Reviewed-by: Neil Armstrong <[email protected]>
Link: https://patch.msgid.link/[email protected]
Signed-off-by: Casey Connolly <[email protected]>
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Add GCC_AHB2PHY_WEST_CLK gate clock definition to the QCS615
clock driver. This clock is required for proper PHY operation
and eliminates clock-related warnings during USB initialization.
Signed-off-by: Balaji Selvanathan <[email protected]>
Reviewed-by: Sumit Garg <[email protected]>
Reviewed-by: Neil Armstrong <[email protected]>
Link: https://patch.msgid.link/[email protected]
Signed-off-by: Casey Connolly <[email protected]>
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Add support for GCC_USB3_PRIM_CLKREF_CLK to the QCS615 clock driver.
This clock is referenced in the device tree USB node but was not
implemented in U-Boot, causing "Clock 152 not found" warnings during
fastboot run.
Signed-off-by: Balaji Selvanathan <[email protected]>
Reviewed-by: Sumit Garg <[email protected]>
Link: https://patch.msgid.link/[email protected]
Signed-off-by: Casey Connolly <[email protected]>
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https://source.denx.de/u-boot/custodians/u-boot-mediatek
* A fix for mt7622 infracfg and pericfg clocks that were unusable.
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The MT7622 infracfg and pericfg drivers both use
mtk_common_clk_infrasys_init() for probe, which populates struct
mtk_clk_priv and stores gate definitions in the clk_tree. However,
both drivers were incorrectly wired to mtk_clk_gate_ops which expects
struct mtk_cg_priv with separately populated gates/num_gates/gates_offs
fields from mtk_common_clk_gate_init().
Since those fields were never set, any attempt to enable an infracfg or
pericfg gate clock (e.g. CLK_INFRA_TRNG) would fail with -EINVAL.
Switch both to mtk_clk_infrasys_ops and struct mtk_clk_priv to match
the init function.
Fixes: 72ab603b201 ("clk: mediatek: add driver for MT7622")
Signed-off-by: Daniel Golle <[email protected]>
Reviewed-by: David Lechner <[email protected]>
Signed-off-by: David Lechner <[email protected]>
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BCM2711 has different pull-up/down register values compared to BCM2835
- BCM2835: NONE=0, DOWN=1, UP=2
- BCM2711: NONE=0, UP=1, DOWN=2
This patch fixes the pull state register values for BCM2711.
Fixes: 2c39d975f87c ("pinctrl: bcm283x: Add GPIO pull-up/down control for BCM2835 and BCM2711")
Signed-off-by: Cibil Pankiras <[email protected]>
Reviewed-by: Matthias Brugger <[email protected]>
Reviewed-by: Peter Robinson <[email protected]>
Tested-by: Peter Robinson <[email protected]>
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Siddharth Vadapalli <[email protected]> says:
Since Linux device-tree has switched to 64-bit Address space for the
PCIe Controllers on TI SoCs, currently, U-Boot needs to support the
same. This series adds support for 64-bit addressing for PCIe along with
enabling Root-Complex mode of operation for AM69 and J784S4 SoCs.
Series has been tested on all platforms being affected by this series.
Test Logs:
1. AM642-EVM
https://gist.github.com/Siddharth-Vadapalli-at-TI/82512389f8396a51e4f167c7ebe4c2a3
2. AM69-SK
https://gist.github.com/Siddharth-Vadapalli-at-TI/b20b2811804ffc6e6c063564330c0a35
3. J7200-EVM
https://gist.github.com/Siddharth-Vadapalli-at-TI/c545da68bd28a5e036803bb60f32d8e9
4. J722S-EVM
https://gist.github.com/Siddharth-Vadapalli-at-TI/3dde05c4c7076076aa20ac47a6e2d176
5. J784S4-EVM
https://gist.github.com/Siddharth-Vadapalli-at-TI/a93c1b2cd5d90f494e885d1831d3d23e
Link: https://lore.kernel.org/r/[email protected]
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The PCIe Controllers on the J784S4 SoC support Root-Complex mode of
operation. Hence, enable it.
Signed-off-by: Siddharth Vadapalli <[email protected]>
Fixes: 79f3e77133bd ("Subtree merge tag 'v6.16-dts' of dts repo [1] into dts/upstream")
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Drivers should extract device-tree data before probing via the
.of_to_plat hook.
Implement it for stm32_dsi driver. By doing so, it also solve a
variable shadowing in stm32_dsi_probe() where &clk was used as
peripheral clock and ref clock.
For readability some struct have been renamed such as:
* struct stm32_dsi_priv *dsi -> struct stm32_dsi_priv *priv
* struct clk clk -> struct clk pclk
Signed-off-by: Raphael Gallais-Pou <[email protected]>
Reviewed-by: Patrick Delaunay <[email protected]>
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Philip Molloy <[email protected]> says:
This series updates the maintainers for the ADI ADSP platform. It
follows Greg's series adding support for ADI ADSP SoCs.
Timesys spent years developing and maintaining Linux support for ADI
ADSP SoCs. The maintenance contract has ended and ADI has brought that
effort in-house. Additionally, Timesys was acquired by another company.
Thanks to everyone at Timesys for all of their hard work over the years!
Link: https://lore.kernel.org/r/[email protected]
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After years of developing the ADI ADSP platform, Timesys was purchased
by another company and is no longer contracted to maintain the platform.
Signed-off-by: Philip Molloy <[email protected]>
Reviewed-by: Greg Malysa <[email protected]>
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https://source.denx.de/u-boot/custodians/u-boot-ufs
A few fixes/missing changes for UFS:
- remove unused ufs_post_bind() declaration
- Disable UTP command timeout in slow mode
- Missing MediaTek UFS PHY Driver to be used with the UFS driver
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Replace then -> they so that the sentence makes sense.
Signed-off-by: Hugo Villeneuve <[email protected]>
Reviewed-by: Quentin Schulz <[email protected]>
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The ofnode_to_fdt() function may return a NULL pointer in multiple cases.
Or, this function's return value is often passed directly to functions such
as fdt_getprop() which end up dereferencing it, thus causing a NULL pointer
exception.
Don't allow ofnode_to_fdt() to return NULL, to avoid a NULL pointer
dereference.
Reviewed-by: Raphaël Gallais-Pou <[email protected]>
Signed-off-by: Romain Gantois <[email protected]>
Reviewed-by: Simon Glass <[email protected]>
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Commit 067c1b033282 ("ufs: Call ufs_scsi_bind() from uclass .post_bind")
inlined ufs_scsi_bind() into ufs_post_bind() as trivial
device_bind_driver() call.
ufs_scsi_bind() is no longer referenced anywhere in the codebase, so
drop its declaration from include/ufs.h.
Drivers used to include <ufs.h> to include prototype of ufs_scsi_bind()
function, so we can now safely remove such includes.
Fixes: 067c1b033282 ("ufs: Call ufs_scsi_bind() from uclass .post_bind")
Signed-off-by: Julien Stephan <[email protected]>
Reviewed-by: Neil Armstrong <[email protected]>
Link: https://patch.msgid.link/[email protected]
Signed-off-by: Neil Armstrong <[email protected]>
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This UFS M-PHY driver can be used on recent MediaTek SoCs as the
primary PHY for the UFS controller.
Signed-off-by: Igor Belwon <[email protected]>
Link: https://patch.msgid.link/20251011-mtk-ufs-uboot-v1-1-a05f991ee150@mentallysanemainliners.org
Signed-off-by: Neil Armstrong <[email protected]>
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When the UFS controller is operating in slow (PWM) mode,
the driver is disabled the timeout for UTP send commands.
In high-speed mode, the timeout remains enabled to
detect stalled or failed transfers. This change ensures reliable
operation in slow mode, where command completion may take longer
and timeouts are not required.
Signed-off-by: Padmarao Begari <[email protected]>
Signed-off-by: Michal Simek <[email protected]>
Reviewed-by: Neil Armstrong <[email protected]>
Link: https://patch.msgid.link/e6deb9086afab9d2bdd53db8ecbc7db93af5204d.1764169598.git.michal.simek@amd.com
Signed-off-by: Neil Armstrong <[email protected]>
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Similar to pinctrl_select_state(), add dev_has_ofnode() check before doing the
real work. Device(scmi_base.0) does not have a real device node, ofnode_null()
is assigned as the device tree node for scmi base protocol device:
'commit 7eb4eb541c14 ("firmware: scmi: install base protocol to SCMI agent")'
However with recent update in
'commit 0535e46d55d7 ("scripts/dtc: Update to upstream version v1.7.2-35-g52f07dcca47c")',
SPL panic in fdt_check_node_offset_()->fdt_next_tag(), because offset is -1
and SPL_OF_LIBFDT_ASSUME_MASK is 0xFF.
So need to validate device tree node.
Reported-by: Ye Li <[email protected]>
Closes: https://lore.kernel.org/u-boot/[email protected]/
Signed-off-by: Peng Fan <[email protected]>
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Similar to pinctrl_select_state(), add dev_has_ofnode() check before doing the
real work. Device(scmi_base.0) does not have a real device node, ofnode_null()
is assigned as the device tree node for scmi base protocol device:
'commit 7eb4eb541c14 ("firmware: scmi: install base protocol to SCMI agent")'
However with recent update in
'commit 0535e46d55d7 ("scripts/dtc: Update to upstream version v1.7.2-35-g52f07dcca47c")',
SPL panic in fdt_check_node_offset_()->fdt_next_tag(), because offset is -1
and SPL_OF_LIBFDT_ASSUME_MASK is 0xFF.
So need to validate device tree node.
Reported-by: Ye Li <[email protected]>
Closes: https://lore.kernel.org/u-boot/[email protected]/
Signed-off-by: Peng Fan <[email protected]>
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SCMI base protocol device does not have a device tree, it should use and
need to use the agent base channel.
For scmi_base.[x], there is no real device tree node for it. ofnode_null() is
assigned as the device tree node for scmi base protocol device:
commit 7eb4eb541c14 ("firmware: scmi: install base protocol to SCMI agent")
However with recent update in commit 0535e46d55d7
("scripts/dtc: Update to upstream version v1.7.2-35-g52f07dcca47c"),
SPL panic in fdt_check_node_offset_()->fdt_next_tag(), because offset is -1
and SPL_OF_LIBFDT_ASSUME_MASK is 0xFF.
So add a check in x_get_channel() to validate the protocol devices'
ofnode.
Reported-by: Ye Li <[email protected]>
Closes: https://lore.kernel.org/u-boot/[email protected]/
Signed-off-by: Peng Fan <[email protected]>
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- Assorted platform and video driver updates
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The USB PHY used by the Exynos7870 SoC has a single USB 2.0 interface.
Add its dedicated variant enum, compatible, and init/exit functions.
The PHY enable bit of Exynos7870's PHY is different in contrast to that
of Exynos850 and most Exynos PHYs. To allow this change, a simple if
condition is added in exynos_usbdrd_phy_isol() which changes the
bitmask. Since the variant enum is required, the function argument is
changed to accept the driver data itself.
Reviewed-by: Mattijs Korpershoek <[email protected]>
Signed-off-by: Kaustabh Chakraborty <[email protected]>
Signed-off-by: Minkyu Kang <[email protected]>
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The variant enum is used to uniquely identify which SoC the PHY block
belongs to. It is initially set in the match table, along with the
compatible string, it gets copied to driver data struct during probe.
SoC specific functions must only be called if the respective variant
enum is set. Add switch-case blocks wherever required.
Reviewed-by: Mattijs Korpershoek <[email protected]>
Signed-off-by: Kaustabh Chakraborty <[email protected]>
Signed-off-by: Minkyu Kang <[email protected]>
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Implement STM32MP21 reset drivers using stm32-core-reset API.
Signed-off-by: Gabriel Fernandez <[email protected]>
Signed-off-by: Patrice Chotard <[email protected]>
Reviewed-by: Patrick Delaunay <[email protected]>
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Add clock driver support for STM32MP21 SoCs.
Signed-off-by: Nicolas Le Bayon <[email protected]>
Signed-off-by: Patrice Chotard <[email protected]>
Reviewed-by: Patrick Delaunay <[email protected]>
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The hardware denies any access from the U-Boot non-secure world to the
secure-protected pins. Hence, prevent any driver to configure such a pin.
Identify the secure pins with "NO ACCESS" through the 'pinmux status -a'
command.
Use a driver data structure to identify which hardware versions support
this feature.
Signed-off-by: Fabien Dessenne <[email protected]>
Signed-off-by: Patrice Chotard <[email protected]>
Reviewed-by: Patrick Delaunay <[email protected]>
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The hardware denies any access from the U-Boot non-secure world to the
secure-protected pins. Hence, prevent any driver to request such a pin.
Signed-off-by: Fabien Dessenne <[email protected]>
Signed-off-by: Patrice Chotard <[email protected]>
Reviewed-by: Patrick Delaunay <[email protected]>
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The cdns3_bind() function is responsible for identifying the appropriate
driver to bind to the USB Controller's device-tree node. If the device-tree
node has the 'dr_mode' property set to 'otg', the existing approach fails
to bind a driver, leading to loss of functionality.
To address this, use the VBUS Valid field of the OTG Status register to
determine the role as follows:
- If VBUS Valid field is set, it indicates that a USB Host is supplying
power and the Controller should assume the Peripheral role.
- If VBUS Valid field is clear, it indicates the absence of a USB Host and
the Controller should assume the Host role.
Additionally, when 'dr_mode' happens to be 'otg' and the STRAP settings
are not specified, use VBUS Valid to determine the role in cdns3_drd_init()
and assign it to cdns->dr_mode.
Signed-off-by: Siddharth Vadapalli <[email protected]>
Reviewed-by: Marek Vasut <[email protected]>
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https://source.denx.de/u-boot/custodians/u-boot-microblaze
AMD/Xilinx/FPGA changes for v2026.04-rc3
clk:
- zynqmp clk fixes
phy:
- sync vsc8541 config
versal2:
- fix GIC configuration
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https://source.denx.de/u-boot/custodians/u-boot-dfu
u-boot-dfu-20260211
USB Gadget:
* dwc3: Support ip and version type
* dwc3: Increase controller halt timeout
* dwc3: Don't send unintended link state change
* dwc3: Improve reset sequence
* dwc2: Move dr_mode check to bind to support RK3288/RK3506 with
2 DWC2 controllers
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Set RMII reference clock output to enabled (1) by default for VSC8541
PHY in RMII mode. The RMII specification requires a 50MHz reference
clock, and many board designs expect the PHY to provide this clock to
the MAC controller.
Previously, the driver defaulted rmii_clk_out to 0 (disabled) for all
interface modes, which caused the PHY to not output the required 50MHz
clock. This resulted in MAC-PHY communication failures and prevented
network operations like DHCP from working on RMII-configured boards.
This change alligns with the hardware power-up default behavior and
aligns with both the generic PHY driver and Linux MSCC PHY driver
implementations.
Signed-off-by: Pranav Tilak <[email protected]>
Signed-off-by: Michal Simek <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
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When built without CONFIG_CMD_CLK, we get a warning about the unused
clk_names variable:
../drivers/clk/clk_zynqmp.c:153:27: warning: ‘clk_names’ defined but not used [-Wunused-const-variable=]
153 | static const char * const clk_names[clk_max] = {
So also guard it with CONFIG_CMD_CLK to get rid of that.
Signed-off-by: Peter Korsgaard <[email protected]>
Reviewed-by: Quentin Schulz <[email protected]>
Signed-off-by: Michal Simek <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
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It looks like the original zynqmp typo was copied to versal as well. Fix
both.
Signed-off-by: Peter Korsgaard <[email protected]>
Reviewed-by: Quentin Schulz <[email protected]>
Signed-off-by: Michal Simek <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
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Pull request net-20260209.
net:
- airoha: mdio support for the switch
- phy: mscc: allow RGMII with internal delay for the VSC8541
- dwc_eth_qos: Update tail pointer handling
net-legacy:
- Stop conflating return value with file size in net_loop()
net-lwip:
- wget: rework the '#' printing
- tftp: add support of tsize option to client
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https://source.denx.de/u-boot/custodians/u-boot-at91
First set of u-boot-at91 features for the 2026.04 cycle:
This small fixes set includes fixing 64 bit builds and some warnings for
the at91 serial driver, and some cleanup on the nand driver.
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i.MX95 uses System Manager(sm) API to start/stop logical machine or cpu.
There are two modes:
M7 in a dedicated logical machine, use LMM API
M7 and A55 in same logical machine, use CPU API
Extend the driver to using LMM and CPU protocol to manage the M7 core:
- Detect using LMM or CPU API in probe using API scmi_imx_lmm_info().
- Compare linux LM ID(got using scmi_imx_lmm_info) and M7 LM ID(the ID
is fixed as 1 in SM firmware if M7 is in a separate LM),
if Linux LM ID is not same as M7 LM ID(linux and M7 in same LM), use
LMM protocol to start/stop. Whether using CPU or LMM protocol to
start/stop, the M7 status detection could use CPU protocol to detect
started or not. So in imx_rproc_is_running, use scmi_imx_cpu_started to
check the status of M7.
- For above case (2), Use scmi_imx_lmm_power_boot to detect whether
the M7 LM is under control of A55 LM.
- For above case , after using SCMI_IMX_LMM_POWER_ON to check
permission, scmi_imx_lmm_shutdown API should be called to shutdown
the M7 LM.
- Add a new ops imx_rproc_ops_sm.
Signed-off-by: Peng Fan <[email protected]>
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Add a new flag ATT_ECC which indicates the memory region needs ECC
initialization. If the flag is set, clearing the whole memory region to
initialize ECC. If ECC is not initialized, remote core will crash if
directly access the area.
Signed-off-by: Peng Fan <[email protected]>
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The i.MX91 SoC reuses the ENET FEC from i.MX93. Add all required driver
checks to make it work also on the i.MX91 based platforms.
Signed-off-by: Primoz Fiser <[email protected]>
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Add the missing RGMII modes with internal delay for the VSC8541.
Fixes: a5fd13ad1913 ("net: phy: MSCC Add Support for VSC8530-VSC8531-VSC8540-VSC8541")
Signed-off-by: Charles Perry <[email protected]>
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mdio is a child node of the switch, so to get switch base address
we need to lookup for a parent node
Signed-off-by: Mikhail Kshevetskiy <[email protected]>
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Commit d2145a89bcf6 ("net: airoha: bind MDIO controller on Ethernet load")
uses "airoha,en7581-switch" dts node for finding MDIO childs. This is wrong
for EN7523 SoC. The correct node name should be used instead.
Fixes: d2145a89bcf6 ("net: airoha: bind MDIO controller on Ethernet load")
Signed-off-by: Mikhail Kshevetskiy <[email protected]>
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Commit d2145a89bcf6 ("net: airoha: bind MDIO controller on Ethernet load")
refers to non-present CONFIG_MDIO_MT7531 and non-present "mt7531-mdio"
driver. It should use CONFIG_MDIO_MT7531_MMIO and "mt7531-mdio-mmio"
instead.
Fixes: d2145a89bcf6 ("net: airoha: bind MDIO controller on Ethernet load")
Signed-off-by: Mikhail Kshevetskiy <[email protected]>
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Multicast and Broadcast Queue Enable and Promiscuous Mode Enable bits
are currently written to "unused" registers using magic values.
Define more of the "unused" MAC regs based on information in the
DesignWare Cores Ethernet Quality-of-Service databook.
Signed-off-by: Jonas Karlman <[email protected]>
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The DesignWare Cores Ethernet Quality-of-Service databook state that
receive and transmit descriptor list address and also transmit and
receive tail pointer registers should be initialized before the receive
and transmit DMAs are started.
It also state to enable the MAC receiver only after the DMA is active.
Otherwise, received frames can fill the Rx FIFO and overflow.
Move the activation of receive and transmit DMA and MAC receiver until
after tail pointer registers have been initialized.
Signed-off-by: Jonas Karlman <[email protected]>
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