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In commit 187af954cf7958c24efcf0fd62289bbdb4f1f24e there
was a typo that offset all the ecc registers by 4 bytes, fixed that.
Signed-off-by: Ben Goska <[email protected]>
Acked-by: Dirk Behme <[email protected]>
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Current code for the Monahans CPU defined OSCR_CLK_FREQ as 3.250 (MHz)
which caused floating point operations to be used. This resulted in
unresolved references to some FP related libgcc functions when using
U-Boot's private libgcc functions.
Change the code to use fixed point math only.
Signed-off-by: Wolfgang Denk <[email protected]>
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Applying two indepenent OMAP3 patches resulted in missing
GPMC_CONFIG_CS0_BASE. Patch "omap3: embedd gpmc_cs into gpmc
config struct" removes GPMC_CONFIG_CS0_BASE, independent patch
"omap3: bug fix for NOR boot support" introduces it's usage.
Re-introduce GPMC_CONFIG_CS0_BASE.
Signed-off-by: Dirk Behme <[email protected]>
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This is a port of Linux driver for SDHC host controller hardware
found on Freescale's MX2 and MX3 processors. Uses new generic MMC
framework (CONFIG_GENERIC_MMC) and it looks like there are some
problems with a framework (at least on LE cpus). Some of these
problems are addressed in the following patches.
Signed-off-by: Ilya Yanok <[email protected]>
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Signed-off-by: Alessandro Rubini <[email protected]>
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replace variable types in ctrl_structs for omap3 by those with
fixed size (u8, u16, u32).
Additional ifndef-protection is needed by examples which do not
compile when including asm/types.h
Signed-off-by: Matthias Ludwig <[email protected]>
Signed-off-by: Dirk Behme <[email protected]>
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Signed-off-by: Matthias Ludwig <[email protected]>
Signed-off-by: Dirk Behme <[email protected]>
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Embedd chip select configuration into struct for gpmc config
instead of having it completely separated as suggested by
Wolfgang Denk on
http://lists.denx.de/pipermail/u-boot/2009-May/052247.html
Signed-off-by: Matthias Ludwig <[email protected]>
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Fix a typo in the GCDR(x) macro. It's a good thing no one was using it.
Signed-off-by: David Hunter <[email protected]>
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Signed-off-by: Alessandro Rubini <[email protected]>
Acked-by: Andrea Gallo <[email protected]>
Acked-by: Jean-Christophe PLAGNIOL-VILLARD <[email protected]>
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These defines have been subplanted by the equivelent defines in
include/twl4030.h
Signed-off-by: Tom Rix <[email protected]>
Acked-by: Jean-Christophe PLAGNIOL-VILLARD <[email protected]>
Acked-by: Heiko Schocher <[email protected]>
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This problem is seen on Zoom1 and Zoom2 in the startup and
when i2c probe is used
Before :
In: serial
Out: serial
Err: serial
timed out in wait_for_bb: I2C_STAT=1000
timed out in wait_for_bb: I2C_STAT=1000
timed out in wait_for_bb: I2C_STAT=1000
timed out in wait_for_pin: I2C_STAT=1000
I2C read: I/O error
timed out in wait_for_bb: I2C_STAT=1000
timed out in wait_for_bb: I2C_STAT=1000
Die ID #327c00020000000004013ddd05026013
Hit any key to stop autoboot: 0
OMAP3 Zoom1# i2c probe
Valid chip addresses:timed out in wait_for_bb: I2C_STAT=1000
02 03 04 05 06 07 08 09 0A 0B 0C 0D <snip>
After :
In: serial
Out: serial
Err: serial
Die ID #327c00020000000004013ddd05026013
Hit any key to stop autoboot: 0
OMAP3 Zoom1# i2c probe
Valid chip addresses: 48 49 4A 4B
The addresses are for the twl4030.
The prescalar that converts the function clock to the sampling
clock is hardcoded to 0. The reference manual recommends 7
if the function clock is 96MHz.
Instead of just changing the hardcoded values, the prescalar
is calculated from the value I2C_IP_CLK.
The i2c #defines are in kHz. The speed passed into the
i2c init routine is in Hz. To be consistent, change the
defines to be in Hz.
The timing calculations are based on what is done in the
linux 2.6.30 kernel in drivers/i2c/buses/i2c_omap.c as
apposed to what is done in TRM.
The major variables in the timing caculations are
specified as #defines that can be overriden as required.
The variables and their defaults are
I2C_IP_CLK SYSTEM_CLOCK_96
I2C_INTERNAL_SAMPLING_CLK 19200000
I2C_FASTSPEED_SCLL_TRIM 6
I2C_FASTSPEED_SCLH_TRIM 6
I2C_HIGHSPEED_PHASE_ONE_SCLL_TRIM I2C_FASTSPEED_SCLL_TRIM
I2C_HIGHSPEED_PHASE_ONE_SCLH_TRIM I2C_FASTSPEED_SCLH_TRIM
I2C_HIGHSPEED_PHASE_TWO_SCLL_TRIM I2C_FASTSPEED_SCLL_TRIM
I2C_HIGHSPEED_PHASE_TWO_SCLH I2C_FASTSPEED_SCLH_TRIM
This was runtime verified on Zoom1, Zoom2, Beagle and Overo.
The 400kHz and 3.4M cases were verifed on test Zoom1,
Zoom2, Beagle and Overo configurations.
Testing for omap2 will be done in a second step as Nishanth
and Jean-Christophe commented.
Signed-off-by: Tom Rix <[email protected]>
Acked-by: Jean-Christophe PLAGNIOL-VILLARD <[email protected]>
Acked-by: Heiko Schocher <[email protected]>
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Signed-off-by: Heiko Schocher <[email protected]>
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Signed-off-by: Dieter Kiermaier <[email protected]>
Acked-by: Prafulla Wadaskar <[email protected]>
Tested-by: Heiko Schocher <[email protected]>
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Signed-off-by: Heiko Schocher <[email protected]>
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This patch adds unaligned.h for ARM (needed to build with LZO
compression). The file is taken from the linux kernel, but includes
u-boot headers instead.
Signed-off-by: Simon Kagstrom <[email protected]>
Acked-by: Stefan Roese <[email protected]>
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AT91sam9g10 is an ARM 926ej-s SOC. It is an evolution of the at91sam9261 with a
faster clock speed: 266/133MHz.
Signed-off-by: Sedji Gaouaou <[email protected]>
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AT91sam9g45 series is an ARM 926ej-s SOC family clocked at 400/133MHz.
It embeds USB high speed host and device, LCD, DDR2 RAM, and a full set of
peripherals.
The first board that embeds at91sam9g45 chip is the AT91SAM9G45-EKES.
On the board you can find 2 USART, USB high speed,
a 480*272 LG lcd, ethernet, gpio/joystick/buttons.
Signed-off-by: Sedji Gaouaou <[email protected]>
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The current defition for CKEN_B register bits is nonsense. Adding 32 to
the shifted value is equal to '| (1 << 5)', and this bit is marked
'reserved' in the PXA docs.
Signed-off-by: Daniel Mack <[email protected]>
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This clock is needed for systems using the USB2 device unit or the 2d
graphics accelerator.
Signed-off-by: Daniel Mack <[email protected]>
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Signed-off-by: Prafulla Wadaskar <[email protected]>
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This patch use blackfin errno.h implementation which
correspond Linux kernel one.
MIPS implemetation is different that's why I keep it.
I removed ppc_error_no.h from Marvell boards which
was the same too.
I have got ack from ppc40x, blackfin, arm, coldfire and avr custodians.
Acked-by: Stefan Roese <[email protected]>
Signed-off-by: Michal Simek <[email protected]>
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Update chipselect handling in davinci_nand.c so that it can
handle 2 GByte chips the same way Linux does: as one device,
even though it has two halves with independent chip selects.
For such chips the "nand info" command reports:
Device 0: 2x nand0, sector size 128 KiB
Switch to use the default chipselect function unless the board
really needs its own. The logic for the Sonata board moves out
of the driver into board-specific code. (Which doesn't affect
current build breakage if its NAND support is enabled...)
Signed-off-by: David Brownell <[email protected]>
Signed-off-by: Scott Wood <[email protected]>
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All DaVinci SOC's use a CLE mask of 0x10 and an ALE mask of 0x8
except the DM646x. This was decided by the design team driving the design.
This patch updates the CLE and ALE values for DM646x.
Updated patches for DM646x will be sent shortly.
This applies to u-boot-nand-flash git
Signed-off-by: Sandeep Paulraj <[email protected]>
Signed-off-by: Scott Wood <[email protected]>
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The ALE mask used by DaVinci SOCs is wrong. The patch changes the mask value
from '0xa' to '0x8'. This is the mask we use for all TI releases.
Signed-off-by: Sandeep Paulraj <[email protected]>
Signed-off-by: Scott Wood <[email protected]>
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Remove CONFIG_SYS_DAVINCI_BROKEN_ECC option. It's not just nasty;
it's also unused by any current boards, and doesn't even match the
main U-Boot distributions from TI (which use soft ECC, or 4-bit ECC
on newer chips that support it).
DaVinci GIT kernels since 2.6.24, and mainline Linux since 2.6.30,
match non-BROKEN code paths for 1-bit HW ECC. The BROKEN code paths
do seem to partially match what MontaVista/TI kernels (4.0/2.6.10,
and 5.0/2.6.18) do ... but only for small pages. Large page support
is really broken (and it's unclear just what software it was trying
to match!), and the ECC layout was making three more bytes available
for use by filesystem (or whatever) code.
Since this option itself seems broken, remove it. Add a comment
about the MV/TI compat issue, and the most straightforward way to
address it (should someone really need to solve it).
Signed-off-by: David Brownell <[email protected]>
Signed-off-by: Scott Wood <[email protected]>
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Minor cleanup for DaVinci NAND code:
- Use I/O addresses from nand_chip; CONFIG_SYS_NAND_BASE won't
be defined when there are multiple chipselect lines in use
(as with common 2 GByte chips).
- Cleanup handling of EMIF control registers
* Only need one pointer pointing to them
* Remove incorrect and unused struct supersetting them
- Use the standard waitfunc; we don't need a custom version
- Partial legacy cleanup:
* Don't initialize every board like it's a DM6446 EVM
* #ifdef a bit more code for BROKEN_ECC
Sanity checked with small page NAND on dm355 and dm6446 EVMs;
and large page on dm355 EVM (packaged as two devices, not one).
Signed-off-by: David Brownell <[email protected]>
Signed-off-by: Scott Wood <[email protected]>
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Signed-off-by: Wolfgang Denk <[email protected]>
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Signed-off-by: Magnus Lilja <[email protected]>
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This patch abstracts Kirkwood arch specific changes to support ehci-kirkwood driver
Signed-off-by: Prafulla Wadaskar <[email protected]>
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This sets CONFIG_SYS_HZ to 1000 as required, and completely rewrites
timer code, which is now both correct and much smaller. Unused
functions like udelay_masked() have been removed as no driver uses
them, even the ones that are not currently active for this board.
mtu.h is copied literally from the kernel sources.
Signed-off-by: Alessandro Rubini <[email protected]>
Acked-by: Andrea Gallo <[email protected]>
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <[email protected]>
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update against linux v2.6.30
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <[email protected]>
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To enable CAN init, CONFIG_CAN has to be defined in the board config file
and at91_can_hw_init() has to be called in the board specific code.
CAN is available on AT91SAM9263 and AT91CAP9 SoC.
Signed-off-by: Daniel Gorsulowski <[email protected]>
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Correct define typo (. -> ,)
Signed-off-by: Simon Kagstrom <[email protected]>
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Add support for Freescale's i.MX31 PDK board (a.k.a. 3 stack board).
This patch assumes that some other program performs the actual
NAND boot.
Signed-off-by: Magnus Lilja <[email protected]>
Acked-by: Fabio Estevam <[email protected]>
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <[email protected]>
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Signed-off-by: HeungJun, Kim <[email protected]>
CC: Dirk Behme <[email protected]>
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <[email protected]>
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Kirkwood family controllers are highly integrated SOCs
based on Feroceon-88FR131/Sheeva-88SV131/arm926ejs cpu core.
SOC versions supported:-
1) 88F6281-A0 define CONFIG_KW88F6281_A0
2) 88F6192-A0 define CONFIG_KW88F6192_A0
Other supported features:-
1) get_random_hex() fucntion
2) PCI Express port initialization
3) NS16550 driver support
Contributors:
Yotam Admon <[email protected]>
Michael Blostein <[email protected]
Reviewed-by: Ronen Shitrit <[email protected]>
Acked-by: Stefan Rose <[email protected]>
Signed-off-by: Prafulla Wadaskar <[email protected]>
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This patch is required for Kirkwood SoC support
may be used by other ARM architectures
Signed-off-by: Prafulla Wadaskar <[email protected]>
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Signed-off-by: Matthias Ludwig <[email protected]>
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This patch adds a SPI driver for the Marvell Kirkwood SoC's.
Signed-off-by: Prafulla Wadaskar <[email protected]>
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This patch adds generic code to support Freescale's i.MX27 SoCs.
Signed-off-by: Ilya Yanok <[email protected]>
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Signed-off-by: Magnus Lilja <[email protected]>
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Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <[email protected]>
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This patch adds the NAND SPL framework needed to boot i.MX31 boards
from NAND.
It has been tested on a i.MX31 PDK board with large page NAND. Small
page NANDs should work as well, but this has not been tested.
Note: The i.MX31 NFC uses a non-standard layout for large page NANDs,
whether this is compatible with a particular setup depends on how
the NAND device is programmed by the flash programmer (e.g. JTAG
debugger).
The patch is based on the work by Maxim Artamonov.
Signed-off-by: Maxim Artamonov <[email protected]>
Signed-off-by: Magnus Lilja <[email protected]>
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the lowlevel init sequence is the same so unify it
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <[email protected]>
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optimize a few the RAM init
Signed-off-by: Ilko Iliev <[email protected]>
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <[email protected]>
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Different flavours of DaVinci SOC's have differences in their EMAC IP
This patch does the following
1) Updates base addresses for DM365
2) Updates MDIO frequencies for DM365 and DM646x
3) Update EMAC wrapper registers for DM365 and DM646x
Patch applies to u-boot-net git. the EMAC driver itself
will be updated shortly to add support for DM365 and DM646x
Signed-off-by: Sandeep Paulraj <[email protected]>
Signed-off-by: Ben Warren <[email protected]>
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This patch is required for Kirkwood support
may be used by other ARM architectures
Signed-off-by: Prafulla Wadaskar <[email protected]>
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