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The versaclock doesn't have a driver yet, but there are a bunch
of device tree updates for the Beacon RZ/G2 boards that won't
compile without these. A driver is coming, so sync the bindings
for now
Signed-off-by: Adam Ford <[email protected]>
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Add pre-requisite headers for AT91 clock architecture. These
are based on already present files on Linux and will be used
by following commits for AT91 CCF clock drivers.
Signed-off-by: Claudiu Beznea <[email protected]>
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The location and license header of DT bindings header for SiFive
clock driver has changed in upstream Linux hence this patch.
Signed-off-by: Anup Patel <[email protected]>
Reviewed-by: Bin Meng <[email protected]>
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Add driver code for the SiFive FU540 PRCI IP block. This IP block
handles reset and clock control for the SiFive FU540 device and
implements SoC-level clock tree controls and dividers.
Based on code written by Wesley Terpstra <[email protected]>
found in commit 999529edf517ed75b56659d456d221b2ee56bb60 of:
https://github.com/riscv/riscv-linux
Boot and PLL rate change were tested on a SiFive HiFive Unleashed
board.
Signed-off-by: Paul Walmsley <[email protected]>
Signed-off-by: Atish Patra <[email protected]>
Signed-off-by: Anup Patel <[email protected]>
Reviewed-by: Alexander Graf <[email protected]>
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Add a clock driver for the MPC83xx architecture.
Signed-off-by: Mario Six <[email protected]>
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Sync all dra7xx based dts files with latest Linux
Signed-off-by: Lokesh Vutla <[email protected]>
Reviewed-by: Tom Rini <[email protected]>
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