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As part of various code clean-ups we have on occasion missed removing
unused header files. None of these files are referenced anywhere else
at this point.
Signed-off-by: Tom Rini <[email protected]>
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This is not used since this commit:
570c3dcfc15 arm: Remove spear600 boards and the rest of SPEAr support
Drop the driver and Kconfig option.
Signed-off-by: Simon Glass <[email protected]>
Reviewed-by: Michael Trimarchi <[email protected]>
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This is not used since this commit:
8d1e3cb1400 powerpc: mpc83xx: remove MPC8360ERDK, EMPC8360EMDS support
Drop the driver and Kconfig option.
Signed-off-by: Simon Glass <[email protected]>
Reviewed-By: Michael Trimarchi <[email protected]>
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Infineon S25FS256T is 256Mbit Quad SPI NOR flash. The key features and
differences comparing to other Spansion/Cypress flash familes are:
- 4-byte address mode by factory default
- Quad mode is enabled by factory default
- Supports mixture of 128KB and 64KB sectors by OTP configuration
(this patch supports uniform 128KB only)
Signed-off-by: Takahiro Kuwano <[email protected]>
Reviewed-by: Jagan Teki <[email protected]>
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Cypress defines two flavors of configuration registers, volatile and
non volatile, and both use the same bit fields. Rename the bitfields in
the configuration registers so that they can be used for both flavors.
Suggested-by: Tudor Ambarus <[email protected]>
Signed-off-by: Takahiro Kuwano <[email protected]>
Reviewed-by: Tudor Ambarus <[email protected]>
Reviewed-by: Dhruva Gole <[email protected]>
Reviewed-by: Jagan Teki <[email protected]>
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CFR5[6] is reserved bit and must be always 1. Set it to comply with flash
requirements. While fixing SPINOR_REG_CYPRESS_CFR5V_OCT_DTR_EN definition,
stop using magic numbers and describe the missing bit fields in CFR5
register. This is useful for both readability and future possible addition
of Octal STR mode support.
Fixes: ea9a22f7e79c ("mtd: spi-nor-core: Add support for Cypress Semper flash")
Suggested-by: Tudor Ambarus <[email protected]>
Signed-off-by: Takahiro Kuwano <[email protected]>
Reviewed-by: Tudor Ambarus <[email protected]>
Reviewed-by: Dhruva Gole <[email protected]>
Reviewed-by: Jagan Teki <[email protected]>
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Support u-boot driver model. We still retain
support legacy way of doing things if ELM_BASE
is defined in <asm/arch/hardware.h>
We could completely get rid of that if all
platforms defining ELM_BASE get rid of that definition
and enable CONFIG_SYS_NAND_SELF_INIT and are verified
to work.
Signed-off-by: Roger Quadros <[email protected]>
Signed-off-by: Michael Trimarchi <[email protected]>
Signed-off-by: Dario Binacchi <[email protected]>
Reviewed-by: Tom Rini <[email protected]>
Link: https://lore.kernel.org/all/[email protected]
Link: https://lore.kernel.org/all/CABGWkvrvKiVA_yaDnHJcHEKwc+pEuLdz=i6HQEY0oJQvohCUsw@mail.gmail.com
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This function is only used within this module, so it is no longer
necessary to use EXPORT_SYMBOL_GPL().
This patch parallels the work done in the following patch:
https://lore.kernel.org/linux-mtd/[email protected]
Signed-off-by: Dario Binacchi <[email protected]>
Reviewed-By: Michael Trimarchi <[email protected]>
Link: https://lore.kernel.org/all/[email protected]
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The GPMC is a unified memory controller dedicated for interfacing
with external memory devices like
- Asynchronous SRAM-like memories and ASICs
- Asynchronous, synchronous, and page mode burst NOR flash
- NAND flash
- Pseudo-SRAM devices
This driver will take care of setting up the GPMC based on
the settings specified in the Device tree and then
probe its children.
Signed-off-by: Roger Quadros <[email protected]>
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The nor->addr_width tracks number of address bytes used in
read/program/erase ops and eventually set to 4 for >16MB chips, regardless
of flash's internal address mode. For Infineon SEMPER flash's, we use
Read/Write Any Register commands for configuration and status check.
These commands take 3- or 4-byte address depending on flash's internal
address mode.
Signed-off-by: Takahiro Kuwano <[email protected]>
Reviewed-by: Jagan Teki <[email protected]>
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Since commit 8d38a8459b0d ("mtd: Rename free() to rfree()")
the function has been renamed to rfree(), so update the description
inside the mtd_oob_region structure as well.
Fixes: 8d38a8459b0d ("mtd: Rename free() to rfree()")
Reported-by: Mikhail Kshevetskiy <[email protected]>
Signed-off-by: Fabio Estevam <[email protected]>
Acked-by: Michael Trimarchi <[email protected]>
Reviewed-by: Dario Binacchi <[email protected]>
Signed-off-by: Dario Binacchi <[email protected]>
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This adds support for the dirmap API to the spi-nor subsystem, as
introduced in Linux commit df5c21002cf4 ("mtd: spi-nor: use
spi-mem dirmap API").
This patch is synchronize from the following patch
https://patchwork.ozlabs.org/project/uboot/patch/[email protected]/
The corresponding Linux kernel SHA1 is df5c21002cf4.
Signed-off-by: Chin-Ting Kuo <[email protected]>
Signed-off-by: Sean Anderson <[email protected]>
Acked-by: Pratyush Yadav <[email protected]>
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Upstream linux commit 7bb427990ee364.
Rename the function to match this new behavior.
NOTE: fix nand_detect/nand_get_flash_type parameters in
mxs_nand_spl. This code seems never executed by any board
as alternative for nand detect
Signed-off-by: Michael Trimarchi <[email protected]>
Reviewed-by: Dario Binacchi <[email protected]>
Signed-off-by: Dario Binacchi <[email protected]>
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Upstream linux commit 4722c0e958e636.
The returned "type" is never used in nand_scan_ident() and spl code
Make nand_get_flash_type() simply return an integer value in order
to avoid unnecessary ERR_PTR/PTR_ERR dance.
Signed-off-by: Michael Trimarchi <[email protected]>
Reviewed-by: Dario Binacchi <[email protected]>
Signed-off-by: Dario Binacchi <[email protected]>
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Upstream linux commit 8cfb9ab68f9070.
Drop the 's' at the end of nand_manufacturers since the struct is actually
describing a single manufacturer, not a manufacturer table.
Signed-off-by: Michael Trimarchi <[email protected]>
Reviewed-by: Dario Binacchi <[email protected]>
Signed-off-by: Dario Binacchi <[email protected]>
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Upstream linux commit 3b5206f4be9b65.
Move Macronix specific initialization logic into nand_macronix.c. This
is part of the "separate vendor specific code from core" cleanup
process.
Signed-off-by: Michael Trimarchi <[email protected]>
Signed-off-by: Dario Binacchi <[email protected]>
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Upstream linux commit 229204da53b31d.
Move AMD/Spansion specific initialization/detection logic into
nand_amd.c. This is part of the "separate vendor specific code from
core" cleanup process.
Signed-off-by: Michael Trimarchi <[email protected]>
Signed-off-by: Dario Binacchi <[email protected]>
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Upstream linux commit 10d4e75c36f6c1.
Move Micron specific initialization logic into nand_micron.c. This is
part of the "separate vendor specific code from core" cleanup process.
Signed-off-by: Michael Trimarchi <[email protected]>
Signed-off-by: Dario Binacchi <[email protected]>
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Upstream linux commit 9b2d61f80b060c.
Move Toshiba specific initialization and detection logic into
nand_toshiba.c. This is part of the "separate vendor specific code from
core" cleanup process.
Signed-off-by: Michael Trimarchi <[email protected]>
Signed-off-by: Dario Binacchi <[email protected]>
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Upstream linux commit 01389b6bd2f4f7.
Move Hynix specific initialization and detection logic into
nand_hynix.c. This is part of the "separate vendor specific code from
core" cleanup process.
Signed-off-by: Michael Trimarchi <[email protected]>
Signed-off-by: Dario Binacchi <[email protected]>
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Upstream linux commit c51d0ac59f2420.
Move Samsung specific initialization and detection logic into
nand_samsung.c. This is part of the "separate vendor specific code from
core" cleanup process.
Signed-off-by: Michael Trimarchi <[email protected]>
Signed-off-by: Dario Binacchi <[email protected]>
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In preparation of moving specific nand support that are not jedec
or onfi
Signed-off-by: Michael Trimarchi <[email protected]>
Signed-off-by: Dario Binacchi <[email protected]>
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chip points to mtd. Passing chip is enough to have a reference
to mtd when is necessary
Signed-off-by: Michael Trimarchi <[email protected]>
Signed-off-by: Dario Binacchi <[email protected]>
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Upstream linux commit abbe26d144ec22.
A lot of NANDs are implementing generic features in a non-generic way,
or are providing advanced auto-detection logic where the NAND ID bytes
meaning changes with the NAND generation.
Providing this vendor specific initialization step will allow us to get
rid of full-id entries in the nand_ids table or all the vendor specific
cases added over the time in the generic NAND ID decoding logic.
Signed-off-by: Michael Trimarchi <[email protected]>
Signed-off-by: Dario Binacchi <[email protected]>
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Upstream linux commit 7f501f0a72036d.
Store the NAND ID in struct nand_chip to avoid passing id_data and id_len
as function parameters.
Signed-off-by: Michael Trimarchi <[email protected]>
Signed-off-by: Dario Binacchi <[email protected]>
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There was no user of this callback after 5b66fdb29dc3 anymore, and its
semantic as now inconsistent between stm and sst26. What we need for the
upcoming new usecase is a "completely unlocked" semantic. So consolidate
over this.
Signed-off-by: Jan Kiszka <[email protected]>
Acked-by: Jagan Teki <[email protected]>
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Parse SCCR 22nd dword and check DTR Octal Mode Enable
Volatile bit for Octal DTR enable
Signed-off-by: JaimeLiao <[email protected]>
Reviewed-by: Jagan Teki <[email protected]>
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Follow patch <f6adec1af4b2f5d3012480c6cdce7743b74a6156> (Allow using Micron mt35xu512aba
in Octal DTR mode).
Enable Octal DTR mode with 20 dummy cycles to allow running at the
maximum supported frequency for adding Macronix flash in Octal DTR mode.
-https://www.mxic.com.tw/Lists/Datasheet/Attachments/7841/MX25LM51245G,%203V,%20512Mb,%20v1.1.pdf
Signed-off-by: JaimeLiao <[email protected]>
Reviewed-by: Jagan Teki <[email protected]>
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Replace reference to the correct name STMicroelectronics
Signed-off-by: Patrick Delaunay <[email protected]>
Reviewed-by: Heiko Schocher <[email protected]>
Reviewed-by: Patrice Chotard <[email protected]>
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We need to know where the typedef of 'ofnode' comes from.
Fixes: c86a4de8df61 ("mtd: Add flash_node in struct mtd_info")
Signed-off-by: Tom Rini <[email protected]>
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Currently, add_mtd_partitions_of() can be used only if dev field of
mtd_info struct is populated. It's the case, for example, for a spi nor
flash, which has a DT compatible "jedec,spi-nor" and an associated
device. mtd->dev is populated in spi_nor_scan().
But in case of a raw nand node, mtd_info's dev field can't be populated
as flash node has no compatible, so no associated device.
add_mtd_partitions_of() can't be used to parse "partitions" subnode.
To remove this constraint, add an ofnode field in mtd_info struct
which reference the DT flash node. This new field is populated by
nand_scan_tail(). This new field will be used by add_mtd_partitions_of()
to parse the flash node for "partitions" defined in DT.
Signed-off-by: Patrice Chotard <[email protected]>
Cc: Farhan Ali <[email protected]>
Cc: Heinrich Schuchardt <[email protected]>
Cc: Jagan Teki <[email protected]>
Cc: Marek Behun <[email protected]>
Cc: Miquel Raynal <[email protected]>
Cc: Simon Glass <[email protected]>
Cc: Wolfgang Denk <[email protected]>
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The original purpose of mtd_erase_callback() in Linux at the time it was
imported to U-Boot, was to inform the caller that erasing is done (since
it was an asynchronous operation).
All supplied callback methods in U-Boot do nothing, but the
mtd_erase_callback() function was (until previous patch) grossly abused
in U-Boot's mtdpart implementation for completely different purpose.
Since we got rid of the abusement, remove the mtd_erase_callback()
function and the .callback member from struct erase_info entirely, in
order to avoid such problems in the future.
Signed-off-by: Marek Behún <[email protected]>
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This converts the following to Kconfig:
CONFIG_SYS_NAND_MAX_CHIPS
Signed-off-by: Tom Rini <[email protected]>
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https://source.denx.de/u-boot/custodians/u-boot-microblaze into next
Xilinx changes for v2022.01-rc1
zynq:
- Enable capsule update for qspi and mmc
- Update zed DT qspi compatible string
zynqmp:
- Add missing modeboot for EMMC
- Add missing nand DT properties
- List all eeproms for SC on vck190
- Add vck190 SC psu_init
clk:
- Handle only GATE type clock for Versal
watchdog:
- Update versal driver to handle system reset
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Signed-off-by: Wolfgang Denk <[email protected]>
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Signed-off-by: Wolfgang Denk <[email protected]>
Reviewed-by: Simon Glass <[email protected]>
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Signed-off-by: Wolfgang Denk <[email protected]>
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nand_dt_init() is still using fdtdec_xx() interface.
If OF_LIVE flag is enabled, dt property can't be get anymore.
Updating all fdtdec_xx() interface to ofnode_xx() to solve this issue.
For doing this, node parameter type must be ofnode.
First idea was to convert "node" parameter to ofnode type inside
nand_dt_init() using offset_to_ofnode(node). But offset_to_ofnode()
is not bijective, in case OF_LIVE flag is enabled, it performs an assert().
So, this leads to update nand_chip struct flash_node field from int to
ofnode and to update all nand_dt_init() callers.
Signed-off-by: Patrice Chotard <[email protected]>
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Force the mtd name of spi-nor to "nor" + the driver sequence number:
"nor0", "nor1"... beginning after the existing nor devices.
This patch is coherent with existing "nand" and "spi-nand"
mtd device names.
When CFI MTD NOR device are supported, the spi-nor index is chosen after
the last CFI device defined by CONFIG_SYS_MAX_FLASH_BANKS.
When CONFIG_SYS_MAX_FLASH_BANKS_DETECT is activated, this config
is replaced by to cfi_flash_num_flash_banks in the include file
mtd/cfi_flash.h.
This generic name "nor%d" can be use to identify the mtd spi-nor device
without knowing the real device name or the DT path of the device,
used with API get_mtd_device_nm() and is used in mtdparts command.
This patch also avoids issue when the same NOR device is present 2 times,
for example on STM32MP15F-EV1:
STM32MP> mtd list
SF: Detected mx66l51235l with page size 256 Bytes, erase size 64 KiB, \
total 64 MiB
List of MTD devices:
* nand0
- type: NAND flash
- block size: 0x40000 bytes
- min I/O: 0x1000 bytes
- OOB size: 224 bytes
- OOB available: 118 bytes
- ECC strength: 8 bits
- ECC step size: 512 bytes
- bitflip threshold: 6 bits
- 0x000000000000-0x000040000000 : "nand0"
* mx66l51235l
- device: mx66l51235l@0
- parent: spi@58003000
- driver: jedec_spi_nor
- path: /soc/spi@58003000/mx66l51235l@0
- type: NOR flash
- block size: 0x10000 bytes
- min I/O: 0x1 bytes
- 0x000000000000-0x000004000000 : "mx66l51235l"
* mx66l51235l
- device: mx66l51235l@1
- parent: spi@58003000
- driver: jedec_spi_nor
- path: /soc/spi@58003000/mx66l51235l@1
- type: NOR flash
- block size: 0x10000 bytes
- min I/O: 0x1 bytes
- 0x000000000000-0x000004000000 : "mx66l51235l"
The same mtd name "mx66l51235l" identify the 2 instances
mx66l51235l@0 and mx66l51235l@1.
This patch fixes a ST32CubeProgrammer / stm32prog command issue
with nor0 target on STM32MP157C-EV1 board introduced by
commit b7f060565e31 ("mtd: spi-nor: allow registering multiple MTDs when
DM is enabled").
Fixes: b7f060565e31 ("mtd: spi-nor: allow registering multiple MTDs when DM is enabled")
Signed-off-by: Patrick Delaunay <[email protected]>
[trini: Add <dm/device.h> to <mtd.h> for DM_MAX_SEQ_STR]
Signed-off-by: Tom Rini <[email protected]>
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nand_dt_init() is still using fdtdec_xx() interface.
If OF_LIVE flag is enabled, dt property can't be get anymore.
Updating all fdtdec_xx() interface to ofnode_xx() to solve this issue.
For doing this, node parameter type must be ofnode.
First idea was to convert "node" parameter to ofnode type inside
nand_dt_init() using offset_to_ofnode(node). But offset_to_ofnode()
is not bijective, in case OF_LIVE flag is enabled, it performs an assert().
So, this leads to update nand_chip struct flash_node field from int to
ofnode and to update all nand_dt_init() callers.
Signed-off-by: Patrice Chotard <[email protected]>
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Remove the driver st_smic.c used in SPEAr products and the associated
config CONFIG_ST_SMI; this driver is no more used in U-Boot after the
commit 570c3dcfc153 ("arm: Remove spear600 boards and the rest of SPEAr
support").
Fixes: 570c3dcfc153 ("arm: Remove spear600 boards and the rest of SPEAr support")
Signed-off-by: Patrick Delaunay <[email protected]>
Reviewed-by: Stefan Roese <[email protected]>
Reviewed-by: Tom Rini <[email protected]>
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The nor->ready() and spansion_sr_ready() introduced earlier in this
series are used for multi-die package parts.
The nor->quad_enable() sets the volatile QE bit on each die.
The nor->erase() is hooked if the device is not configured to uniform
sectors, assuming it has 32 x 4KB sectors overlaid on bottom address.
Other configurations, top and split, are not supported at this point.
Will submit additional patches to support it as needed.
The post_bfpt/sfdp() fixes the params wrongly advertised in SFDP.
Signed-off-by: Takahiro Kuwano <[email protected]>
Reviewed-by: Jagan Teki <[email protected]>
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Cypress chips support SPINOR_OP_EN4B(B7h) to enable 4-byte addressing mode.
Cypress chips support B8h to disable 4-byte addressing mode instead of
SPINOR_OP_EX4B(E9h).
This patch defines new opcode and updates set_4byte() to support
enable/disable 4-byte addressing mode for Cypress chips.
Signed-off-by: Takahiro Kuwano <[email protected]>
Reviewed-by: Jagan Teki <[email protected]>
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The spansion_sr_ready() reads status register 1 by Read Any Register
commnad. This function is called from Flash specific hook with die address
and dummy cycles to support multi-die package parts from Spansion/Cypress.
Signed-off-by: Takahiro Kuwano <[email protected]>
Reviewed-by: Pratyush Yadav <[email protected]>
Reviewed-by: Jagan Teki <[email protected]>
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For dual/quad die package devices from Spansion/Cypress, the device's
status needs to be checked by reading status registers in all dies, by
using Read Any Register command. To support this, a Flash specific hook
that can overwrite the legacy status check is needed.
Signed-off-by: Takahiro Kuwano <[email protected]>
Reviewed-by: Pratyush Yadav <[email protected]>
Reviewed-by: Jagan Teki <[email protected]>
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Some of Spansion/Cypress chips support volatile version of configuration
registers and it is recommended to update volatile registers in the field
application due to a risk of the non-volatile registers corruption by
power interrupt. This patch adds a function to set Quad Enable bit in CFR1
volatile.
Signed-off-by: Takahiro Kuwano <[email protected]>
Reviewed-by: Jagan Teki <[email protected]>
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Some of Spansion/Cypress chips support Read/Write Any Register commands.
These commands are mainly used to write volatile registers and access to
the registers in second and subsequent die for multi-die package parts.
The Read Any Register instruction (65h) is followed by register address
and dummy cycles, then the selected register byte is returned.
The Write Any Register instruction (71h) is followed by register address
and register byte to write.
Signed-off-by: Takahiro Kuwano <[email protected]>
Reviewed-by: Pratyush Yadav <[email protected]>
Reviewed-by: Jagan Teki <[email protected]>
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This patch adds Cypress manufacturer ID (34h) definition.
Signed-off-by: Takahiro Kuwano <[email protected]>
Reviewed-by: Pratyush Yadav <[email protected]>
Reviewed-by: Jagan Teki <[email protected]>
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Since this flash doesn't have a Profile 1.0 table, the Octal DTR
capabilities are enabled in the post SFDP fixup, along with the 8D-8D-8D
fast read settings.
Enable Octal DTR mode with 20 dummy cycles to allow running at the
maximum supported frequency of 200Mhz.
Signed-off-by: Pratyush Yadav <[email protected]>
Reviewed-by: Jagan Teki <[email protected]>
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The Cypress Semper flash is an xSPI compliant octal DTR flash. Add
support for using it in octal DTR mode.
The flash by default boots in a hybrid sector mode. Switch to uniform
sector mode on boot. Use the default 20 dummy cycles for a read fast
command.
The SFDP programming on some older versions of the flash was incorrect.
Fixes for that are included in the fixup hooks.
Signed-off-by: Pratyush Yadav <[email protected]>
Reviewed-by: Jagan Teki <[email protected]>
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