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This driver can control up to 32 clocks.
Signed-off-by: Álvaro Fernández Rojas <[email protected]>
Reviewed-by: Simon Glass <[email protected]>
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This driver can control up to 32 clocks.
Signed-off-by: Álvaro Fernández Rojas <[email protected]>
Reviewed-by: Simon Glass <[email protected]>
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This driver can control up to 32 resets.
Signed-off-by: Álvaro Fernández Rojas <[email protected]>
Reviewed-by: Simon Glass <[email protected]>
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This driver can control up to 32 clocks.
Signed-off-by: Álvaro Fernández Rojas <[email protected]>
Reviewed-by: Simon Glass <[email protected]>
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This driver can control up to 32 clocks.
Signed-off-by: Álvaro Fernández Rojas <[email protected]>
Reviewed-by: Simon Glass <[email protected]>
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This driver can control up to 32 clocks.
Signed-off-by: Álvaro Fernández Rojas <[email protected]>
Reviewed-by: Simon Glass <[email protected]>
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This serves as an example for bcm6358-leds.
Signed-off-by: Álvaro Fernández Rojas <[email protected]>
Reviewed-by: Simon Glass <[email protected]>
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Signed-off-by: Álvaro Fernández Rojas <[email protected]>
Reviewed-by: Simon Glass <[email protected]>
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Signed-off-by: Álvaro Fernández Rojas <[email protected]>
Reviewed-by: Simon Glass <[email protected]>
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Signed-off-by: Álvaro Fernández Rojas <[email protected]>
Reviewed-by: Simon Glass <[email protected]>
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Signed-off-by: Álvaro Fernández Rojas <[email protected]>
Reviewed-by: Simon Glass <[email protected]>
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Signed-off-by: Álvaro Fernández Rojas <[email protected]>
Reviewed-by: Simon Glass <[email protected]>
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Signed-off-by: Álvaro Fernández Rojas <[email protected]>
Reviewed-by: Simon Glass <[email protected]>
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CFE checks CPU Thread in a different way (using register $22):
mfc0 t1, C0_BCM_CONFIG, 3 # $22
li t2, CP0_CMT_TPID # (1 << 31)
and t1, t2
bnez t1, 2f # if we are running on thread 1, skip init
nop
Signed-off-by: Álvaro Fernández Rojas <[email protected]>
Reviewed-by: Simon Glass <[email protected]>
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The PHY framework provides a set of APIs to control a PHY. This API is
derived from the linux version of the generic PHY framework.
Currently the API supports init(), deinit(), power_on, power_off() and
reset(). The framework provides a way to get a reference to a phy from the
device-tree.
Signed-off-by: Jean-Jacques Hiblot <[email protected]>
Reviewed-by: Simon Glass <[email protected]>
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Update the configuration files to support the device tree and driver
model. The device clock and pins configuration are handled by the
clock and the pinctrl drivers respectively.
Signed-off-by: Wenyou Yang <[email protected]>
Reviewed-by: Simon Glass <[email protected]>
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Update the configuration files to support the device tree and driver
model. The device clock and pins configuration are handled by the
clock and the pinctrl drivers respectively.
Signed-off-by: Wenyou Yang <[email protected]>
Reviewed-by: Simon Glass <[email protected]>
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Update the configuration files to support the device tree and driver
model. The device clock and pins configuration are handled by the
clock and the pinctrl drivers respectively.
Signed-off-by: Wenyou Yang <[email protected]>
Reviewed-by: Simon Glass <[email protected]>
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Update the configuration files to support the device tree and driver
model. The device clock and pins configuration are handled by the
clock and the pinctrl drivers respectively.
Because the limitation of internal SRAM size, the SPL with driver
model can't be supported, disable the SPL option.
Signed-off-by: Wenyou Yang <[email protected]>
Reviewed-by: Simon Glass <[email protected]>
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Update the configuration files to support the device tree and driver
model. The device clock and pins configuration are handled by the
clock and the pinctrl drivers respectively.
Because the limitation of internal SRAM size, the SPL with driver
model can't be supported, disable the SPL option.
Signed-off-by: Wenyou Yang <[email protected]>
Reviewed-by: Simon Glass <[email protected]>
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Update the configuration files to support the device tree and driver
model. The device clock and pins configuration are handled by the
clock and the pinctrl drivers respectively.
Because the limitation of internal SRAM size, the SPL with driver
model can't be supported, disable the SPL option.
Signed-off-by: Wenyou Yang <[email protected]>
Reviewed-by: Simon Glass <[email protected]>
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Enable config options to support the SPL, increase the malloc
memory size for the SPL and board_init_f stage and increase
the memory space for the SPL binary.
Signed-off-by: Wenyou Yang <[email protected]>
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Enable CONFIG_DM_ETH to make MACB to support driver model.
Because the USB Ether doesn't support driver model so far,
remove this feature.
Signed-off-by: Wenyou Yang <[email protected]>
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Move existing configuration from header file to defconfig or dts as
appropriate.
Signed-off-by: Chris Packham <[email protected]>
Reviewed-by: Simon Glass <[email protected]>
Reviewed-by: Stefan Roese <[email protected]>
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This patch adds the option to configure a comphy to 5G XFI mode.
In order to configure the comphy to 5G XFI, update
the comphy node in the device-tree:
phy2 {
phy-type = <PHY_TYPE_SFI>;
phy-speed = <PHY_SPEED_5_15625G>;
};
Signed-off-by: Igal Liberman <[email protected]>
Signed-off-by: Stefan Roese <[email protected]>
Reviewed-by: Stefan Roese <[email protected]>
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This type tells u-boot to preserve the COMPHY settings as is
it is usefull in situations where the COMPHY was initialized by
earlier firmware.
Note that IGNORE is different from UNCONNECTED since setting
UNCONNECTED type will disconnect the COMPHY in the COMPHY MUX
which is a desired behaviour
Signed-off-by: Yehuda Yitschak <[email protected]>
Signed-off-by: Stefan Roese <[email protected]>
Signed-off-by: Igal Liberman <[email protected]>
Reviewed-by: Stefan Roese <[email protected]>
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UTMI_PHY_TO_USB_HOST was used in USB3 UTMI dts node only, but there will
be USB2 UTMI dts node for some SoCs that have got USB2 controller, so rename
TO_USB_HOST to TO_USB3_HOST to distinguish TO_USB2_HOST in later on patches.
Signed-off-by: zachary <[email protected]>
Signed-off-by: Stefan Roese <[email protected]>
Signed-off-by: Igal Liberman <[email protected]>
Reviewed-by: Stefan Roese <[email protected]>
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Use correct naming as done in the latest Marvell U-Boot version as well.
Signed-off-by: Stefan Roese <[email protected]>
Signed-off-by: Igal Liberman <[email protected]>
Reviewed-by: Stefan Roese <[email protected]>
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Add NAND configuration parameters to A8K shared config file.
Add defconfig for db-88f7040 board with boot from NAND setup.
Signed-off-by: Konstantin Porotchkin <[email protected]>
Cc: Stefan Roese <[email protected]>
Cc: Igal Liberman <[email protected]>
Cc: Nadav Haklai <[email protected]>
Reviewed-by: Stefan Roese <[email protected]>
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One some keystone2 platforms like K2G ICE, there is an option
to switch between 24MHz or 25MHz as sysclk. But the existing
driver assumes it is always 24MHz. Add support for getting
all reference clocks dynamically by reading boot pins.
Signed-off-by: Lokesh Vutla <[email protected]>
Reviewed-by: Tom Rini <[email protected]>
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Add support for clocks needed by MACs to ast2500 clock driver.
The clocks are D2-PLL, which is used by both MACs and PCLK_MAC1 and
PCLK_MAC2 for MAC1 and MAC2 respectively.
The rate of D2-PLL is hardcoded to 250MHz -- the value used in Aspeed
SDK. It is not entirely clear from the datasheet how this clock is used
by MACs, so not clear if the rate would ever need to be different. So,
for now, hardcoding it is probably safer.
The rate of PCLK_MAC{1,2} is chosen based on MAC speed selected through
hardware strapping.
So, the network driver would only need to enable these clocks, no need
to configure the rate.
Signed-off-by: Maxim Sloyko <[email protected]>
Reviewed-by: Simon Glass <[email protected]>
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Add Reset Driver configuration to ast2500 SoC Device Tree and bindings
for various reset signals
Signed-off-by: Maxim Sloyko <[email protected]>
Reviewed-by: Simon Glass <[email protected]>
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This is a simple uclass for Watchdog Timers. It has four operations:
start, restart, reset, stop. Drivers must implement start, restart and
stop operations, while implementing reset is optional: It's default
implementation expires watchdog timer in one clock tick.
Signed-off-by: Maxim Sloyko <[email protected]>
Reviewed-by: Simon Glass <[email protected]>
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netboot allows to boot an external image using TFTP and NFS protocols
Signed-off-by: Pau Pajuelo <[email protected]>
Signed-off-by: Ladislav Michl <[email protected]>
Tested-by: Pau Pajuelo <[email protected]>
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The IGEP SMARC AM335x is an industrial processor module with
following highlights:
o AM3352 TI processor (Up to AM3359)
o Cortex-A8 ARM CPU
o SMARC form factor module
o Up to 512 MB DDR3 SDRAM / 512 MB FLASH
o WiFi a/b/g/n and Bluetooth v4.0 on-board
o Ethernet 10/100/1000 Mbps and 10/100 Mbps controller on-board
o JTAG debug connector available
o Designed for industrial range purposes
Signed-off-by: Pau Pajuelo <[email protected]>
Signed-off-by: Ladislav Michl <[email protected]>
Tested-by: Pau Pajuelo <[email protected]>
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Convert IGEP board to use UBI volumes for U-Boot, its environment and
kernel. With exception of first four sectors read by SoC BootROM whole
NAND is UBI managed.
Signed-off-by: Ladislav Michl <[email protected]>
Reviewed-by: Heiko Schocher<[email protected]>
Tested-by: Pau Pajuelo <[email protected]>
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Rename igep0033 to igep003x as IGEP SMARC AM335x module (igep0034)
can use the same source files.
Signed-off-by: Ladislav Michl <[email protected]>
Tested-by: Pau Pajuelo <[email protected]>
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This patch removes:
- CONFIG_CMD_MEM: enabled by default
- CONFIG_DESIGNWARE_ETH : not being used anywhere.
Signed-off-by: Vikas Manocha <[email protected]>
cc: Christophe KERELLO <[email protected]>
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Actually the sdram memory on stm32f746 discovery board is micron part
MT48LC_4M32_B2B5_6A. This patch does the modification required in the
device tree node & driver for the same.
Also we are passing here all the timing parameters in terms of clock
cycles, so no need to convert time(ns or ms) to cycles.
Signed-off-by: Vikas Manocha <[email protected]>
cc: Christophe KERELLO <[email protected]>
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Signed-off-by: Vikas Manocha <[email protected]>
cc: Christophe KERELLO <[email protected]>
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Signed-off-by: Vikas Manocha <[email protected]>
cc: Christophe KERELLO <[email protected]>
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All discovery boards have one user button & one user LED. Here we are
just reading the button status & switching ON the user LED.
Signed-off-by: Vikas Manocha <[email protected]>
cc: Christophe KERELLO <[email protected]>
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With this gpio driver supporting DM, there is no need to enable clocks
for different gpios (for pin muxing) in the board specific code.
Need to increase the allocatable area required before relocation from 0x400 to
0xC00 becuase of 10 new gpio devices(& new gpio class) added in device tree.
Signed-off-by: Vikas Manocha <[email protected]>
cc: Christophe KERELLO <[email protected]>
Reviewed-by: Simon Glass <[email protected]>
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Signed-off-by: Vikas Manocha <[email protected]>
cc: Christophe KERELLO <[email protected]>
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At present fdt blob or argument address being passed to kernel is fixed at
compile time using macro CONFIG_SYS_SPL_ARGS_ADDR. FDT blob from
different media like nand, nor flash are copied to the address pointed
by the macro.
The problem is, it makes args/fdt blob compulsory to copy which is not required
in cases like for NOR Flash. This patch removes this limitation.
Signed-off-by: Vikas Manocha <[email protected]>
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USB bus scan attempt:
----------------------------------cut----------------------------------
=> usb start
starting USB...
USB0: Register 2000140 NbrPorts 2
Starting the controller
USB XHCI 1.00
scanning bus 0 for devices... data abort
pc : [<fff6240e>] lr : [<fff623b3>]
reloc pc : [<8081b40e>] lr : [<8081b3b3>]
sp : fdf42930 ip : fdf42960 fp : 00000000
r10: 00000001 r9 : fdf42ef0 r8 : 48890020
r7 : 00000002 r6 : fffa5840 r5 : fff8b140 r4 : fdf429c0
r3 : 00000000 r2 : 00000004 r1 : 00000000 r0 : 00000000
Flags: nZcv IRQs off FIQs off Mode SVC_32
Resetting CPU ...
resetting ...
----------------------------------cut----------------------------------
Fix by enabling USB configuration in the SPL.
Signed-off-by: Uri Mashiach <[email protected]>
Reviewed-by: Tom Rini <[email protected]>
Reviewed-by: Igor Grinberg <[email protected]>
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Modify the determination of the base address of xHCI registers of DRA7XX
targets.
Before the commit: by the target.
After the commit: by the USB port index.
Cc: Lokesh Vutla <[email protected]>
Cc: Marek Vasut <[email protected]>
Cc: Roger Quadros <[email protected]>
Signed-off-by: Uri Mashiach <[email protected]>
Reviewed-by: Marek Vasut <[email protected]>
Reviewed-by: Tom Rini <[email protected]>
Reviewed-by: Roger Quadros <[email protected]>
Acked-by: Marek Vasut <[email protected]>
Acked-by: Marek Vasut <[email protected]>
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The symbol CONFIG_DRA7XX is needed for Kconfig conditions.
Cc: Lokesh Vutla <[email protected]>
Signed-off-by: Uri Mashiach <[email protected]>
Reviewed-by: Tom Rini <[email protected]>
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