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LAN8720 PHY is used on Freescale C2X0QDS board.
Signed-off-by: Mingkai Hu <[email protected]>
Signed-off-by: Andy Fleming <[email protected]>
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Starting from QMan3.0, the QMan clock cycle needs be exposed so that the kernel
driver can use it to calculate the shaper prescaler and rate.
Signed-off-by: Haiying Wang <[email protected]>
Signed-off-by: Andy Fleming <[email protected]>
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The T4240QDS is a high-performance computing evaluation, development and
test platform supporting the T4240 QorIQ Power Architecture™ processor.
SERDES Connections
32 lanes grouped into four 8-lane banks
Two “front side” banks dedicated to Ethernet
Two “back side” banks dedicated to other protocols
DDR Controllers
Three independant 64-bit DDR3 controllers
Supports rates up to 2133 MHz data-rate
Supports two DDR3/DDR3LP UDIMM/RDIMMs per controller
QIXIS System Logic FPGA
Each DDR controller has two DIMM slots. The first slot of each controller
has up to 4 chip selects to support single-, dual- and quad-rank DIMMs.
The second slot has only 2 chip selects to support single- and dual-rank
DIMMs. At any given time, up to total 4 chip selects can be used.
Detail information can be found in doc/README.t4qds
Signed-off-by: York Sun <[email protected]>
Signed-off-by: Andy Fleming <[email protected]>
Signed-off-by: Kumar Gala <[email protected]>
Signed-off-by: Prabhakar Kushwaha <[email protected]>
Signed-off-by: Shengzhou Liu <[email protected]>
Signed-off-by: Roy Zang <[email protected]>
Signed-off-by: Andy Fleming <[email protected]>
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The multirate ethernet media access controller (mEMAC) interfaces to
10Gbps and below Ethernet/IEEE 802.3 networks via either RGMII/RMII
interfaces or XAUI/XFI/SGMII/QSGMII using the high-speed SerDes interface.
Signed-off-by: Sandeep Singh <[email protected]>
Signed-off-by: Poonam Aggrwal <[email protected]>
Signed-off-by: Roy Zang <[email protected]>
Signed-off-by: Andy Fleming <[email protected]>
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Add support for Freescale T4240 SoC. Feature of T4240 are
(incomplete list):
12 dual-threaded e6500 cores built on Power Architecture® technology
Arranged as clusters of four cores sharing a 2 MB L2 cache.
Up to 1.8 GHz at 1.0 V with 64-bit ISA support (Power Architecture
v2.06-compliant)
Three levels of instruction: user, supervisor, and hypervisor
1.5 MB CoreNet Platform Cache (CPC)
Hierarchical interconnect fabric
CoreNet fabric supporting coherent and non-coherent transactions with
prioritization and bandwidth allocation amongst CoreNet end-points
1.6 Tbps coherent read bandwidth
Queue Manager (QMan) fabric supporting packet-level queue management and
quality of service scheduling
Three 64-bit DDR3/3L SDRAM memory controllers with ECC and interleaving
support
Memory prefetch engine (PMan)
Data Path Acceleration Architecture (DPAA) incorporating acceleration for
the following functions:
Packet parsing, classification, and distribution (Frame Manager 1.1)
Queue management for scheduling, packet sequencing, and congestion
management (Queue Manager 1.1)
Hardware buffer management for buffer allocation and de-allocation
(BMan 1.1)
Cryptography acceleration (SEC 5.0) at up to 40 Gbps
RegEx Pattern Matching Acceleration (PME 2.1) at up to 10 Gbps
Decompression/Compression Acceleration (DCE 1.0) at up to 20 Gbps
DPAA chip-to-chip interconnect via RapidIO Message Manager (RMAN 1.0)
32 SerDes lanes at up to 10.3125 GHz
Ethernet interfaces
Up to four 10 Gbps Ethernet MACs
Up to sixteen 1 Gbps Ethernet MACs
Maximum configuration of 4 x 10 GE + 8 x 1 GE
High-speed peripheral interfaces
Four PCI Express 2.0/3.0 controllers
Two Serial RapidIO 2.0 controllers/ports running at up to 5 GHz with
Type 11 messaging and Type 9 data streaming support
Interlaken look-aside interface for serial TCAM connection
Additional peripheral interfaces
Two serial ATA (SATA 2.0) controllers
Two high-speed USB 2.0 controllers with integrated PHY
Enhanced secure digital host controller (SD/MMC/eMMC)
Enhanced serial peripheral interface (eSPI)
Four I2C controllers
Four 2-pin or two 4-pin UARTs
Integrated Flash controller supporting NAND and NOR flash
Two eight-channel DMA engines
Support for hardware virtualization and partitioning enforcement
QorIQ Platform's Trust Architecture 1.1
Signed-off-by: York Sun <[email protected]>
Signed-off-by: Kumar Gala <[email protected]>
Signed-off-by: Andy Fleming <[email protected]>
Signed-off-by: Roy Zang <[email protected]>
Signed-off-by: Prabhakar Kushwaha <[email protected]>
Signed-off-by: Shengzhou Liu <[email protected]>
Signed-off-by: Andy Fleming <[email protected]>
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The P5040 does not have SRIO, so don't put the SRIO definitions in
corenet_ds.h. They belong in the board-specific header files.
Signed-off-by: Timur Tabi <[email protected]>
Signed-off-by: Andy Fleming <[email protected]>
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Enable Coreboot and EXT4 Filesystems on the coreboot board.
Signed-off-by: Simon Glass <[email protected]>
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This change adds CBFS support and some commands to use it to u-boot. These
commands are:
cbfsinit - Initialize CBFS support and pull all metadata into RAM. The end of
the ROM is an optional parameter which defaults to the standard 0xffffffff and
can be used to support multiple CBFSes in a system. The last one set up with
cbfsinit is the one that will be used.
cbfsinfo - Print information from the CBFS header.
cbfsls - Print out the size, type, and name of all the files in the current
CBFS. Recognized types are translated into symbolic names.
cbfsload - Load a file from CBFS into memory. Like the similar command for fat
filesystems, you can optionally provide a maximum size.
Support for CBFS is compiled in when the CONFIG_CMD_CBFS option is specified.
The CBFS driver can also be used programmatically from within u-boot.
If u-boot needs something out of CBFS very early before the heap is
configured, it won't be able to use the normal CBFS support which caches some
information in memory it allocates from the heap. The
cbfs_file_find_uncached function searches a CBFS instance without touching
the heap.
Signed-off-by: Gabe Black <[email protected]>
Signed-off-by: Stefan Reinauer <[email protected]>
Signed-off-by: Simon Glass <[email protected]>
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The size of an LBA type changes depending on this option. We need to
use a different printf() string in each case, so create a define for
this.
Signed-off-by: Gabe Black <[email protected]>
Signed-off-by: Simon Glass <[email protected]>
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The command declaration now uses the new LG-array method to generate
list of commands. Thus the __u_boot_cmd section is now superseded and
redundant and therefore can be removed. Also, remove externed symbols
associated with this section from include/command.h .
Signed-off-by: Marek Vasut <[email protected]>
Cc: Joe Hershberger <[email protected]>
Cc: Mike Frysinger <[email protected]>
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This patch converts the old method of creating a list of command
onto the new LG-arrays code. The old u_boot_cmd section is converted
to new u_boot_list_cmd subsection and LG-array macros used as needed.
Minor adjustments had to be made to the common code to work with the
LG-array macros, mostly the fixup_cmdtable() calls are now passed the
ll_entry_start and ll_entry_count instead of linker-generated symbols.
The command.c had to be adjusted as well so it would use the newly
introduced LG-array API instead of directly using linker-generated
symbols.
Signed-off-by: Marek Vasut <[email protected]>
Cc: Joe Hershberger <[email protected]>
Cc: Mike Frysinger <[email protected]>
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This patch adds support for linker-generated array. These arrays
are a generalization of the U-Boot command declaration approach.
Basically, the idea is to generate an array, where elements of the
array are statically initialized at compile time and each element
is declared separatelly at different place. Such array is assembled
together into continuous piece of memory by linker and a pointer to
it's first entry can then be retrieved via accessor.
The actual implementation relies on placing any variable that is to
represent an element of LG-array into particular subsection of the
.u_boot_list linker section . The subsection is determined by user
options. Once compiled, it is possible to dump all symbols placed
in .u_boot_list section and the subsections in which they should be
and generate appropriate bounds for each requested subsection of the
.u_boot_list section. Each such subsection thus contains __start and
__end entries at the begining and end respecitively.
This allows for simple run-time traversing of the array, since the
symbols are properly defined.
Signed-off-by: Marek Vasut <[email protected]>
Cc: Joe Hershberger <[email protected]>
Cc: Mike Frysinger <[email protected]>
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Support the DesginWare MMC Controller.
Signed-off-by: Jaehoon Chung <[email protected]>
Signed-off-by: Kyungmin Park <[email protected]>
Signed-off-by: Rajeshawari Shinde <[email protected]>
Signed-off-by: Andy Fleming <[email protected]>
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Some of the boards still used the old PXA_MMC driver instead of the
new generic one. Use the new one instead so the old can be removed
and the generic MMC framework can be properly used.
Signed-off-by: Marek Vasut <[email protected]>
Cc: Andy Fleming <[email protected]>
Signed-off-by: Andy Fleming <[email protected]>
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MMC host controller requires a delay between every sdhci_send_cmd()
execution. In s5p_mmc driver (s5p_sdhci replaces this driver), a delay
of 1000us was provided after every mmc_send_cmd() call. Adding a quirk
in current sdhci driver to replicate the behaviour.
Without this delay, MMC initialization on Origen board fails with
following error messages.
Timeout for status update!
mmc fail to send stop cmd
Signed-off-by: Tushar Behera <[email protected]>
Signed-off-by: Jaehoon Chung <[email protected]>
Signed-off-by: Andy Fleming <[email protected]>
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Flip the boards to use the generic bounce buffer instead of the
MMC one.
Signed-off-by: Marek Vasut <[email protected]>
Cc: Andy Fleming <[email protected]>
Cc: Fabio Estevam <[email protected]>
Signed-off-by: Andy Fleming <[email protected]>
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Implement common bounce buffer to be used on a less capable hardware.
That includes hardware that can not do DMA from any address or such.
Signed-off-by: Marek Vasut <[email protected]>
Cc: Fabio Estevam <[email protected]>
Cc: Andy Fleming <[email protected]>
Signed-off-by: Andy Fleming <[email protected]>
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Data cache and CONFIG_MMC_BOUNCE_BUFFER can be safely enabled now.
Signed-off-by: Fabio Estevam <[email protected]>
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Data cache and CONFIG_MMC_BOUNCE_BUFFER can be safely enabled now.
Signed-off-by: Fabio Estevam <[email protected]>
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Use internal RAM for stack pointer as it is done in other i.MX boards.
Signed-off-by: Fabio Estevam <[email protected]>
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Conflicts:
drivers/serial/serial_lh7a40x.c
Signed-off-by: Tom Rini <[email protected]>
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To support Non-ASCII keys (ex, Fn, PgUp/Dn, arrow keys, ...), we need to
translate key code into escape sequence.
(Updated by [email protected] to move away from a function to store
keycodes, so we can easily record how many were sent. We now need to
return this from input_send_keycodes() so we know whether keys were
generated.)
Signed-off-by: Hung-Te Lin <[email protected]>
Signed-off-by: Simon Glass <[email protected]>
Signed-off-by: Tom Rini <[email protected]>
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The BIOS leaves the keyboard enabled during boot time so that any
keystroke would interfere kernel driver initialization.
Add a way to disable the keyboard to make sure no scancode will be
generated during the boot time. Note that the keyboard will be
re-enabled again after the kernel driver is up.
This code can be called from the board functions.
Signed-off-by: Louis Yung-Chieh Lo <[email protected]>
Signed-off-by: Louis Yung-Chieh Lo <[email protected]>
Signed-off-by: Simon Glass <[email protected]>
Signed-off-by: Tom Rini <[email protected]>
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empty
On x86, the i8042 keyboard controller driver frequently waits for the keyboard
input buffer to be empty to make sure the controller has had a chance to
process the data it was given. The way the delay loop was structured, if the
controller hadn't cleared the corresponding status bit immediately, it would
wait 1ms before checking again. If the keyboard responded quickly but not
instantly, the driver would still wait a full 1ms when perhaps 1us would have
been sufficient. Because udelay is a busy wait anyway, this change decreases
the delay between checks to 1us.
Also, this change gets rid of a hardcoded 250ms delay.
On Stumpy, this saves 100-150ms during boot.
Signed-off-by: Gabe Black <[email protected]>
Signed-off-by: Simon Glass <[email protected]>
Signed-off-by: Tom Rini <[email protected]>
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There used to be a huge structure duplicated 3 times in the source.
Signed-off-by: Joe Hershberger <[email protected]>
Signed-off-by: Tom Rini <[email protected]>
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This patch provides a support to use buffered writes on flash
for versatile and vexpress boards.
This will certainly increase the flash writes.
Signed-off-by: Jagannadha Sutradharudu Teki <[email protected]>
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Signed-off-by: Marek Vasut <[email protected]>
Cc: David Müller <[email protected]>
Cc: Minkyu Kang <[email protected]>
Cc: Wolfgang Denk <[email protected]>
Cc: Albert Aribaud <[email protected]>
Cc: U-Boot DM <[email protected]>
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Signed-off-by: Marek Vasut <[email protected]>
Cc: Oliver Brown <[email protected]>
Cc: Wolfgang Denk <[email protected]>
Cc: Albert Aribaud <[email protected]>
Cc: U-Boot DM <[email protected]>
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The sbc8548/60 (both similar, just variations in UART hardware)
support has been removed from the linux kernel as of v3.6-rc1~132
so lets also now remove it from the u-boot tree as well.
Signed-off-by: Paul Gortmaker <[email protected]>
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The recent U-Boot version 2012.07 has improved drivers
(e.g. MMC and network/FEC) regarding DCache handling.
So it should be safe to use the DCache on the i.MX6, now.
Signed-off-by: Dirk Behme <[email protected]>
Acked-by: Stefano Babic <[email protected]>
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mx53evk has only one Ethernet port, so remove CONFIG_HAS_ETH1 option.
Signed-off-by: Fabio Estevam <[email protected]>
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mx51evk has only one Ethernet port, so remove CONFIG_HAS_ETH1 option.
Signed-off-by: Fabio Estevam <[email protected]>
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mx53loco has only one Ethernet port, so remove CONFIG_HAS_ETH1 option.
Signed-off-by: Fabio Estevam <[email protected]>
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Since PLL2 now has changed, it is necessary to adapt the CONFIG_IPUV3_CLK
accordingly.
Signed-off-by: Fabio Estevam <[email protected]>
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This changes input_data() and friends from static function to global symbols
under weak alias, to enable board specific overrides (and therefore get rid of
board-specific code in cmd_ide.c)
Also declare ide_bus_offset in the header file, so other files can use
ATA_CURR_BASE as well.
Signed-off-by: Pavel Herrmann <[email protected]>
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move most of mpc8xx hooks from cmd_ide.c into ide_preinit() and newly created
ide_init_postreset() (invoked after calling ide_reset after ide_preinit),
some cleanup to make checkpatch happy, enable IDE init hooks in configs of
affected boards.
confusingly, these hooks are used by more than just mpc8xx-based boards, and
therefore are placed in arch/ppc/lib/
note: checkpatch still emits warnings about using volatile
Signed-off-by: Pavel Herrmann <[email protected]>
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U-Boot contains a lot of duplicit implementations of serial_puts()
call which just pipes single characters into the port in loop. Implement
function that does this behavior into common code, so others can make
easy use of it.
This function is called default_serial_puts() and it's sole purpose
is to call putc() in loop on the whole string passed to it.
Signed-off-by: Marek Vasut <[email protected]>
Cc: Marek Vasut <[email protected]>
Cc: Tom Rini <[email protected]>
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As the board seems to be unmaintained for some time, lets remove
the support in mainline completely.
Signed-off-by: Stefan Roese <[email protected]>
Cc: Marek Vasut <[email protected]>
Cc: James F. Dougherty <[email protected]>
Cc: Wolfgang Denk <[email protected]>
Acked-by: Marek Vasut <[email protected]>
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Signed-off-by: Josh Wu <[email protected]>
Signed-off-by: Andreas Bießmann <[email protected]>
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Since the at91sam9263, the mmc hardware support multi blocks read/write. So this driver enable it.
Signed-off-by: Josh Wu <[email protected]>
Signed-off-by: Andreas Bießmann <[email protected]>
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Since commit 957731ed (ARM: remove broken "lpd7a40x" boards),
lh7a40x cpu and serial driver have become unused. Remove them.
Signed-off-by: Albert ARIBAUD <[email protected]>
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Signed-off-by: Daniel Schwierzeck <[email protected]>
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Both big-endian and little-endian are tested with below commands:
Rom version: (Default, Now we config it as rom version)
qemu-system-mips64el -M mips -bios u-boot.bin -cpu MIPS64R2-generic -nographic
qemu-system-mips64 -M mips -bios u-boot.bin -cpu MIPS64R2-generic -nographic
Ram version:
qemu-system-mips64el -M mips -cpu MIPS64R2-generic -kernel u-boot -nographic
qemu-system-mips64 -M mips -cpu MIPS64R2-generic -kernel u-boot -nographic
Signed-off-by: Zhizhou Zhang <[email protected]>
Signed-off-by: Daniel Schwierzeck <[email protected]>
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We define CONFIG_SYS_TEXT_BASE in board's specified header file.
So config.mk is useless, then remove it.
Signed-off-by: Zhizhou Zhang <[email protected]>
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Adds support for HDMI, two LVDS panels and one RGB panel to
the SABRE-Lite board.
Displays supported:
HDMI - 1024 x 768 for maximum compatibility
Hannstar-XGA - 1024 x 768 LVDS (Freescale part number MCIMX-LVDS1)
wsvga-lvds - 1024 x 600 LVDS (Boundary p/n Nit6X_1024x600)
wvga-rgb - 800 x 480 RGB (Boundary p/n Nit6X_800x480)
Since the ipuv3_fb display driver currently supports only a single display,
this code auto-detects panel by probing the HDMI Phy for Hot Plug Detect
or the I2C touch controller of the LVDS and RGB displays in the priority
listed above.
Setting 'panel' environment variable to one of the names above will
override auto-detection.
Signed-off-by: Eric Nelson <[email protected]>
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Signed-off-by: Eric Nelson <[email protected]>
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The mmcroot setting vary between mx6qsabreauto and mx6qsabresd so we
move this to the board configuration file.
Signed-off-by: Otavio Salvador <[email protected]>
Acked-by: Fabio Estevam <[email protected]>
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On mxc, each SDHC instance has a dedicated clock, so gd->sdhc_clk is not
suitable for the multi-instance use case (initialization made directly with
fsl_esdhc_initialize()).
This patch fixes this issue by adding a configuration field for the SDHC input
clock frequency.
Signed-off-by: Benoît Thébaudeau <[email protected]>
Cc: Stefano Babic <[email protected]>
Cc: Eric Bénard <[email protected]>
Cc: Otavio Salvador <[email protected]>
Cc: Fabio Estevam <[email protected]>
Cc: Jason Liu <[email protected]>
Cc: Matt Sealey <[email protected]>
Cc: Andy Fleming <[email protected]>
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