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This patch adds SPI support for carrying out the cros_ec protocol.
Signed-off-by: Hung-ying Tyan <[email protected]>
Signed-off-by: Randall Spangler <[email protected]>
Signed-off-by: Simon Glass <[email protected]>
Acked-by: Simon Glass <[email protected]>
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This patch adds the cros_ec driver that implements the protocol for
communicating with Google's ChromeOS embedded controller.
Signed-off-by: Bernie Thompson <[email protected]>
Signed-off-by: Bill Richardson <[email protected]>
Signed-off-by: Che-Liang Chiou <[email protected]>
Signed-off-by: Doug Anderson <[email protected]>
Signed-off-by: Gabe Black <[email protected]>
Signed-off-by: Hung-ying Tyan <[email protected]>
Signed-off-by: Louis Yung-Chieh Lo <[email protected]>
Signed-off-by: Randall Spangler <[email protected]>
Signed-off-by: Sean Paul <[email protected]>
Signed-off-by: Simon Glass <[email protected]>
Signed-off-by: Vincent Palatin <[email protected]>
Acked-by: Simon Glass <[email protected]>
Tested-by: Simon Glass <[email protected]>
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Faraday FTMAC110 10/100Mbps supports half-word data transfer for Linux.
However it has a weird DMA alignment issue:
(1) Tx DMA Buffer Address:
1 bytes aligned: Invalid
2 bytes aligned: O.K
4 bytes aligned: O.K
(2) Rx DMA Buffer Address:
1 bytes aligned: Invalid
2 bytes aligned: O.K
4 bytes aligned: Invalid!!!
Signed-off-by: Kuo-Jung Su <[email protected]>
Cc: Joe Hershberger <[email protected]>
Cc: Tom Rini <[email protected]>
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Add function ksz9031_phy_extended_write and ksz9031_phy_extended_read
Signed-off-by: Leo Sartre <[email protected]>
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add network support with ksz8851_16mll on at91sam9n12ek board
Signed-off-by: Bo Shen <[email protected]>
Acked-by: Andreas Bießmann <[email protected]>
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The device interface is 16 bits wide.
All the available packets are read from the incoming fifo.
Signed-off-by: Roberto Cerati <[email protected]>
Signed-off-by: Raffaele Recalcati <[email protected]>
[[email protected]: address comments from review results]
[[email protected]: clean up for submit]
Signed-off-by: Bo Shen <[email protected]>
Tested-by: Raffaele Recalcati <[email protected]>
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commit 39695029bc15041c809df3db4ba19bd729c447fa
Author: Charles Coldwell <[email protected]>
Date: Tue Feb 19 08:27:33 2013 -0500
Changes to support the Xilinx 1000BASE-X phy (GTX/MGT)
Signed-off-by: Charles Coldwell <[email protected]>
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for use with sparse.
Signed-off-by: Kim Phillips <[email protected]>
Cc: Joe Hershberger <[email protected]>
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Make do_bootz available for other functions like do_bootm is.
Signed-off-by: Rob Herring <[email protected]>
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Signed-off-by: Yegor Yefremov <[email protected]>
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This patch adds support for the WEMAC, the ethernet controller included
in the Allwinner A10 SoC. It will get used in the upcoming A10 board
support.
From: Stefan Roese <[email protected]>
Signed-off-by: Stefan Roese <[email protected]>
Signed-off-by: Henrik Nordstrom <[email protected]>
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before writing the received buffer to nand, erase the nand
sectors. If not doing this, nand write fails. See for
more info here:
http://lists.denx.de/pipermail/u-boot/2013-June/156361.html
Using the nand erase option "spread", maybe overwrite
blocks on, for example another mtd partition, if the
erasing range contains bad blocks.
So a limit option is added to nand_erase_opts()
Signed-off-by: Heiko Schocher <[email protected]>
Cc: Scott Wood <[email protected]>
Cc: Pantelis Antoniou <[email protected]>
Cc: Lukasz Majewski <[email protected]>
Cc: Kyungmin Park <[email protected]>
Cc: Marek Vasut <[email protected]>
Cc: Tom Rini <[email protected]>
Signed-off-by: Scott Wood <[email protected]>
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- remove the builtin 'rootpath' spec (according to U-Boot project
policy) and require user provided environments to contain these
- rephrase the evaluation of the 'muster_nr' approach which allows to
quickly switch among several network boot setups (make the setting
transparent when empty, resulting in default DULG behaviour)
- reduce the ARP timeout for faster network boot
Signed-off-by: Gerhard Sittig <[email protected]>
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remove remaining "k6" code names, switch to the official 'ac14xx' name
Signed-off-by: Gerhard Sittig <[email protected]>
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- use the default baudrate table for serial communication
- remove hostname/boofile/rootpath defines which were not referenced elsewhere
Signed-off-by: Gerhard Sittig <[email protected]>
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fix typos, minor rephrasing, remove obsolete notes and TODO items
Signed-off-by: Gerhard Sittig <[email protected]>
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This patch enables CONFIG_SILENT_CONSOLE for EXYNOS5.
This patch also removes the hardcoding of UART port from
exynos5250 config.
Signed-off-by: Rajeshwari Shinde <[email protected]>
Signed-off-by: Minkyu Kang <[email protected]>
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Add required compatible information for s5p serial driver
Signed-off-by: Abhilash Kesavan <[email protected]>
Signed-off-by: Rajeshwari Shinde <[email protected]>
Signed-off-by: Minkyu Kang <[email protected]>
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Some Exynos5250 silicon may require 1.05v on the MIF to be stable, so to be
safe we can default to 1.05v instead of 1.00v. This can be set optimally later
in the boot process by the kernel.
The 0x6 value for 1.05v comes from the MAX77686 datasheet.
Signed-off-by: Bernie Thompson <[email protected]>
Acked-by: Simon Glass <[email protected]>
Signed-off-by: Minkyu Kang <[email protected]>
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Flag status register polling is required for micron 512Mb flash
devices onwards, for performing erase/program operations.
Like polling for WIP(Write-In-Progress) bit in read status register,
spi_flash_cmd_wait_ready will poll for PEC(Program-Erase-Control)
bit in flag status register.
Signed-off-by: Jagannadha Sutradharudu Teki <[email protected]>
Reviewed-by: Simon Glass <[email protected]>
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Defined bank addr code on CONFIG_SPI_FLASH_BAR macro, to reduce the
size for existing boards which has < 16Mbytes SPI flashes.
It's upto user which has provision to use the bank addr code for
flashes which has > 16Mbytes.
Signed-off-by: Jagannadha Sutradharudu Teki <[email protected]>
Reviewed-by: Simon Glass <[email protected]>
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Read the flash bank addr register to get the state of bank in
a perticular flash. and also bank write happens only when there is
a change in bank selection from user.
bank read only valid for flashes which has > 16Mbytes those are
opearted in 3-byte addr mode, each bank occupies 16Mytes.
Suppose if the flash has 64Mbytes size consists of 4 banks like
bank0, bank1, bank2 and bank3.
Signed-off-by: Jagannadha Sutradharudu Teki <[email protected]>
Reviewed-by: Simon Glass <[email protected]>
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Bank/Extended addr commands are specific to particular
flash vendor so discover them based on the idocode0.
Assign the discovered bank commands to spi_flash members
so-that the bank read/write will use their specific operations.
Signed-off-by: Jagannadha Sutradharudu Teki <[email protected]>
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This patch adds support for the Palm Treo 680 smartphone. A quick overview of
u-boot implementation on the treo 680...
The treo 680 has a Diskonchip G4 nand flash chip. This device has a 2k region
that maps to the system bus at the reset vector in a NOR-like fashion so that it
can be used as the boot device. The phone is shipped with this 2k region
configured as write-protected (can't be modified) and programmed with an initial
program loader (IPL). At power-up, this IPL loads the contents of two flash
blocks to SDRAM and jumps to it. The capacity of the two blocks is not large
enough to hold all of u-boot, so a u-boot SPL is used. To conserve flash space,
these two blocks and the necessary number of subsequent blocks are programmed
with a concatenated spl + u-boot image. That way, the IPL will also load a
portion of u-boot proper, and when the spl runs, it relocates the portion of
u-boot that the IPL has already loaded, and then resumes loading the remaining
part of u-boot before jumping to it.
The default_environment is used (CONFIG_ENV_IS_NOWHERE) because I didn't think
that having a writable environment was worth the cost of a flash block, although
adding it would be straightforward. I abuse the CONFIG_EXTRA_ENV_SETTINGS
option to specify the usbtty for the console (CONFIG_SYS_CONSOLE_IS_IN_ENV).
Support for the LCD is included, but currently it is only useful for displaying
the u-boot splash screen. But if u-boot is built without the usbtty console, it
does display the auto-boot progress nicely.
Signed-off-by: Mike Dunn <[email protected]>
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Discard all .dynsym sections from linker scripts
Remove all __dynsym_start definitions from linker scripts
Remove all __dynsym_start references from the codebase
Note: this touches include/asm-generic/sections.h, which
is not ARM-specific, but actual uses of __dynsym_start
are only in ARM, so this patch can safely go through
the ARM repository.
Signed-off-by: Albert ARIBAUD <[email protected]>
Tested-by: Lubomir Popov <[email protected]>
Tested-by: Jeroen Hofstee <[email protected]>
Reviewed-by: Benoît Thébaudeau <[email protected]>
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P1023RDB Specification:
-----------------------
Memory subsystem:
512MB DDR3 (Fixed DDR on board)
64MB NOR flash
128MB NAND flash
Ethernet:
eTSEC1: Connected to Atheros AR8035 GETH PHY
eTSEC2: Connected to Atheros AR8035 GETH PHY
PCIe:
Three mini-PCIe slots
USB:
Two USB2.0 Type A ports
I2C:
AT24C08 8K Board EEPROM (8 bit address)
Signed-off-by: Chunhe Lan <[email protected]>
Cc: Scott Wood <[email protected]>
Signed-off-by: Andy Fleming <[email protected]>
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There will need the environment in SPL for reasons other than network
support (in particular, hwconfig contains info for how to set up DDR).
Add a new symbol CONFIG_SPL_ENV_SUPPORT to replace CONFIG_SPL_NET_SUPPORT
for environment in common/Makefile.
Signed-off-by: Ying Zhang <[email protected]>
Reviewed-by: Tom Rini <[email protected]>
Signed-off-by: Andy Fleming <[email protected]>
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Relax parameters to give address latching more time to setup.
Signed-off-by: Prabhakar Kushwaha <[email protected]>
Signed-off-by: Andy Fleming <[email protected]>
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When a T4 board boots from SRIO or PCIE, it needs to finish these processes:
1. Set all the cores in holdoff status.
2. Set the boot location to one PCIE or SRIO interface by RCW.
3. Set a specific TLB entry for the boot process.
4. Set a LAW entry with the TargetID of one PCIE or SRIO for the boot.
5. Set a specific TLB entry in order to fetch ucode and ENV from
master.
6. Set a LAW entry with the TargetID one of the PCIE ports for
ucode and ENV.
7. Slave's u-boot image should be generated specifically by
make xxxx_SRIO_PCIE_BOOT_config.
This will set SYS_TEXT_BASE=0xFFF80000 and other configurations.
For more information about the feature of Boot from SRIO/PCIE, please
refer to the document doc/README.srio-pcie-boot-corenet.
Signed-off-by: Liu Gang <[email protected]>
Signed-off-by: Andy Fleming <[email protected]>
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T4 can support the feature of Boot from SRIO/PCIE, and the macro
"CONFIG_SRIO_PCIE_BOOT_MASTER" will enable the master module of this feature
when building the u-boot image.
You can get some description about this macro in README file, and for more
information about the feature of Boot from SRIO/PCIE, please refer to the
document doc/README.srio-pcie-boot-corenet.
Signed-off-by: Liu Gang <[email protected]>
Signed-off-by: Andy Fleming <[email protected]>
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When a b4860qds board boots from SRIO or PCIE, it needs to finish these
processes:
1. Set all the cores in holdoff status.
2. Set the boot location to one PCIE or SRIO interface by RCW.
3. Set a specific TLB entry for the boot process.
4. Set a LAW entry with the TargetID of one PCIE or SRIO for the boot.
5. Set a specific TLB entry in order to fetch ucode and ENV from
master.
6. Set a LAW entry with the TargetID one of the PCIE ports for
ucode and ENV.
7. Slave's u-boot image should be generated specifically by
make xxxx_SRIO_PCIE_BOOT_config.
This will set SYS_TEXT_BASE=0xFFF80000 and other configurations.
For more information about the feature of Boot from SRIO/PCIE, please
refer to the document doc/README.srio-pcie-boot-corenet.
Signed-off-by: Liu Gang <[email protected]>
Signed-off-by: Andy Fleming <[email protected]>
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B4860QDS can support the feature of Boot from SRIO/PCIE, and the macro
"CONFIG_SRIO_PCIE_BOOT_MASTER" will enable the master module of this feature
when building the u-boot image.
You can get some description about this macro in README file, and for more
information about the feature of Boot from SRIO/PCIE, please refer to the
document doc/README.srio-pcie-boot-corenet.
Signed-off-by: Liu Gang <[email protected]>
Signed-off-by: Andy Fleming <[email protected]>
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Currently, the macro "CONFIG_SYS_FSL_SRIO_PCIE_BOOT_MASTER" can enable
the master module of Boot from SRIO and PCIE on a platform. But this
is not a silicon feature, it's just a specific booting mode based on
the SRIO and PCIE interfaces. So it's inappropriate to put the macro
into the file arch/powerpc/include/asm/config_mpc85xx.h.
Change the macro "CONFIG_SYS_FSL_SRIO_PCIE_BOOT_MASTER" to
"CONFIG_SRIO_PCIE_BOOT_MASTER", remove them from
arch/powerpc/include/asm/config_mpc85xx.h file, and add those macros
in configuration header file of each board which can support the
master module of Boot from SRIO and PCIE.
Signed-off-by: Liu Gang <[email protected]>
Signed-off-by: Andy Fleming <[email protected]>
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BSC9131RDB has 1GB DDR.
Out of this, only 880MB is passed on to Linux via bootm_size.
Remaining
-16MB is reserved for PowerPC-DSP shared control area
-128MB is reserved for DSP private area.
Also 256MB, out of this 880MB is required for data communication between
PowerPC and DSP core.
For this bootargs are modified to pass parameter to create 1 hugetlb
page of 256MB via default_hugepagesz, hugepagesz and hugepages
Signed-off-by: Priyanka Jain <[email protected]>
Signed-off-by: Andy Fleming <[email protected]>
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BSC9131RDB is a Freescale Reference Design Board for
BSC9131 SoC which is a integrated device that contains
one powerpc e500v2 core and one DSP starcore.
To support DSP starcore
-Creating LAW and TLB for DSP-CCSR space.
-Creating LAW for DSP-core subsystem M2 memory
Signed-off-by: Priyanka Jain <[email protected]>
Signed-off-by: Poonam Aggrwal <[email protected]>
Signed-off-by: Prabhakar Kushwaha <[email protected]>
Signed-off-by: Andy Fleming <[email protected]>
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BSC9131RDB supports Sysclk
-66MHz if jumper J16 is close (default state)
-100MHz if jumper J16 is open
Add targets
-BSC9131RDB_NAND_SYSCLK100 : for NAND boot at Sysclk 100MHz
-BSC9131RDB_SPIFLASH_SYSCLK100: for SPI boot at Sysclk 100MHz
Signed-off-by: Ramneek Mehresh <[email protected]>
Signed-off-by: Priyanka Jain <[email protected]>
Signed-off-by: Andy Fleming <[email protected]>
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- Add NAND boot target
- defines constants
- Add spl_minimal.c to initialise DDR
- update TLB, LAW entries as per NAND boot
Signed-off-by: Prabhakar Kushwaha <[email protected]>
Signed-off-by: Andy Fleming <[email protected]>
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- Add NAND boot target
- defines constants
- Add spl_minimal.c to initialise DDR
- update TLB entries as per NAND boot
Signed-off-by: Prabhakar Kushwaha <[email protected]>
Signed-off-by: Andy Fleming <[email protected]>
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- defines constants
- Add spl_minimal.c to initialise DDR
- update TLB entries as per NAND boot
- remove nand_spl support for P1010RDB
Signed-off-by: Prabhakar Kushwaha <[email protected]>
Signed-off-by: Andy Fleming <[email protected]>
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IFC errata A003399 is valid for IFC NOR boot i.e.if no on-board NOR flash or
no NOR boot, do not compile its workaround.
Signed-off-by: Prabhakar Kushwaha <[email protected]>
Signed-off-by: Andy Fleming <[email protected]>
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This patch ensures minimal cooling for the net2big_v2 by automatically
starting the I2C fan (GMT G762) at low speed (2800 RPM).
Signed-off-by: Simon Guinot <[email protected]>
Acked-by: Prafulla Wadaskar <[email protected]>
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Conflicts:
spl/Makefile
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Detect if we are running on a panda revision A1-A6,
or an ES panda board. This can be done by reading
the level of GPIOs and checking the processor revisions.
This should result in:
Panda 4430:
GPIO171, GPIO101, GPIO182: 0 1 1 => A1-A5
GPIO171, GPIO101, GPIO182: 1 0 1 => A6
Panda ES:
GPIO2, GPIO3, GPIO171, GPIO48, GPIO182: 0 0 0 1 1 => B1/B2
GPIO2, GPIO3, GPIO171, GPIO48, GPIO182: 0 0 1 1 1 => B3
Set the board name appropriately for the board revision that
is detected.
Update the findfdt macro to load the a4 device tree binary.
Signed-off-by: Dan Murphy <[email protected]>
[trini: %s/CONTROL_PADCONF_CORE/(*ctrl)->control_padconf_core_base/ and
formatting for that]
Signed-off-by: Tom Rini <[email protected]>
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Update the EXTRA_ENV_SETTING for the dra7xx.
The console needs to be set to ttyO0 and the
findfdt needs to be updated to load the
dra7xx-evm.dtb file.
Signed-off-by: Dan Murphy <[email protected]>
Reviewed-by: Tom Rini <[email protected]>
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Correct the console sys prompt to display the correct processor
and the corrent board
Signed-off-by: Dan Murphy <[email protected]>
Reported-by: Lubomir Popov <[email protected]>
Reviewed-by: Tom Rini <[email protected]>
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