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Remove duplicated code in P2020DS board and utilize the common
fsl_pcie_init_board(). We also now dynamically setup the LAWs for PCI
controllers based on which PCIe controllers are enabled.
Signed-off-by: Li Yang <[email protected]>
Signed-off-by: Kumar Gala <[email protected]>
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Remove duplicated code in MPC8572DS board and utilize the common
fsl_pcie_init_board(). We also now dynamically setup the LAWs for PCI
controllers based on which PCIe controllers are enabled.
Signed-off-by: Chenhui Zhao <[email protected]>
Signed-off-by: Kumar Gala <[email protected]>
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Previously we passed in a specifically named struct pci_controller to
determine if we had setup the particular PCI bus. Now we can search for
the struct so we dont have to depend on the name or the struct being
statically allocated.
Introduced new find_hose_by_cfg_addr() to get back a pci_controller struct
back by searching for it means we can do things like dynamically allocate
them or not have to expose the static structures to all users.
Signed-off-by: Kumar Gala <[email protected]>
Acked-by: Wolfgang Denk <[email protected]>
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This config option is for an erratum workaround; rename it to be more
clear. Also, drop it from config files don't need it and were
undefining it.
Signed-off-by: Becky Bruce <[email protected]>
Signed-off-by: Kumar Gala <[email protected]>
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Correct initdram to use phys_size_t to represent the size of
dram; instead of changing this all over the place, and correcting
all the other random errors I've noticed, create a
common initdram that is used by all non-corenet 85xx parts. Most
of the initdram() functions were identical, with 2 common differences:
1) DDR tlbs for the fixed_sdram case were set up in initdram() on
some boards, and were part of the tlb_table on others. I have
changed them all over to the initdram() method - we shouldn't
be accessing dram before this point so they don't need to be
done sooner, and this seems cleaner.
2) Parts that require the DDR11 erratum workaround had different
implementations - I have adopted the version from the Freescale
errata document. It also looks like some of the versions were
buggy, and, depending on timing, could have resulted in the
DDR controller being disabled. This seems bad.
The xpedite boards had a common/fsl_8xxx_ddr.c; with this
change only the 517 board uses this so I have moved the ddr code
into that board's directory in xpedite517x.c
Signed-off-by: Becky Bruce <[email protected]>
Tested-by: Paul Gortmaker <[email protected]>
Signed-off-by: Kumar Gala <[email protected]>
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Some new platform's esdhc pins don't share with other function.
The eSDHC shouldn't be disabled, even if "esdhc" isn't defined
in hwconfig env variable.
Use CONFIG_FSL_ESDHC_PIN_MUX to fix this problem.
Signed-off-by: Chenhui Zhao <[email protected]>
Signed-off-by: Li Yang <[email protected]>
Signed-off-by: Kumar Gala <[email protected]>
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Instead of a #define use a null weak function for fsl_serdes_init
Signed-off-by: Kumar Gala <[email protected]>
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Mimic support that exists on MPC8536DS on the MPC8572DS to allow booting
from NAND.
Signed-off-by: Jin Qing <[email protected]>
Signed-off-by: Kumar Gala <[email protected]>
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Neither of these parts should have the erratum this is meant to
work around. Delete it.
Signed-off-by: Becky Bruce <[email protected]>
Signed-off-by: Kumar Gala <[email protected]>
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This isn't used - delete it.
Signed-off-by: Becky Bruce <[email protected]>
Signed-off-by: Kumar Gala <[email protected]>
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The PM854/PM856 boards are no longer maintained and thus we are removing
support for them.
Signed-off-by: Kumar Gala <[email protected]>
Acked-by: Wolfgang Denk <[email protected]>
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The MPC8540EVAL board is no longer maintained and thus we are removing
support for it.
Signed-off-by: Kumar Gala <[email protected]>
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The ATUM8548 board is no longer maintained and thus we are removing
support for it.
Signed-off-by: Kumar Gala <[email protected]>
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This patch sync with David's patch on Linux for handling nand_scan_ident.
commit 5e81e88a4c140586d9212999cea683bcd66a15c6
Author: David Woodhouse <[email protected]>
Date: Fri Feb 26 18:32:56 2010 +0000
mtd: nand: Allow caller to pass alternative ID table to nand_scan_ident()
Signed-off-by: David Woodhouse <[email protected]>
Signed-off-by: Lei Wen <[email protected]>
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This patch add addition suffix to nand write to give the uboot
the power to directly burn the yaffs image to nand.
Signed-off-by: Lei Wen <[email protected]>
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PCI is not used at all on lwmon5. So lets remove it. It saves space and
reduces boot time a bit (approx. 50ms).
Signed-off-by: Stefan Roese <[email protected]>
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Patch "Replace CONFIG_SYS_GBL_DATA_SIZE by auto-generated value"
(sha1: 25ddd1fb0a2281b182529afbc8fda5de2dc16d96)
introduce GENERATED_GBL_DATA_SIZE which is sizeof aligned gd_t
(currently 0x40).
Microblaze configs used 0x40(128) because this place also contained
board info structure which lies on the top of ram.
U-Boot is placed to the top of the ram (for example 0xd7ffffff)
and bd structure was moved out of ram.
This patch is fixing this scheme with GENERATED_BD_INFO_SIZE
which swap global data and board info structures.
For example:
Current: gd 0xd7ffffc0, bd 0xd8000000
Fixed: gd 0xd7ffffc0, bd 0xd7ffff90
Signed-off-by: Michal Simek <[email protected]>
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Add Faraday's ftgmac100 (gigabit ethernet)
MAC controller's driver.
Signed-off-by: Macpaul Lin <[email protected]>
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The include/miiphy.h header duplicates a lot of things from linux/mii.h.
So punt all the things that overlap to keep the API simple and to make
merging between U-Boot and Linux simpler.
Signed-off-by: Mike Frysinger <[email protected]>
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We have config_defaults.h which are random configuration settings that
everyone gets by default. We also have config_cmd_default.h which is a
recommended list of defaults but boards have to opt into. Now we have
config_cmd_defaults.h which is a list of defaults that everyone gets
and has to actively opt out of.
For now, we populate it with the bootm command which previously was
unable to be disabled.
Signed-off-by: Mike Frysinger <[email protected]>
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Currently, only basic completion is supported (no globs), but this is
what we had previously.
Signed-off-by: Mike Frysinger <[email protected]>
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This patch supports T-SH7706LSR board.
This is constitution almost same as shmin (T-SH7706LAN).
Therefore, most functions work by a change of the setting of config.
http://web.kyoto-inet.or.jp/people/takagaki/T-SH7706/T-SH7706LSR.htm
Signed-off-by: Nobuhiro Iwamatsu <[email protected]>
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Signed-off-by: Nobuhiro Iwamatsu <[email protected]>
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Signed-off-by: Nobuhiro Iwamatsu <[email protected]>
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This adds support for the SHMIN SH7706 board(T-SH7706LAN).
The CPU of this board is SH7706.
There are SDRAM of 32M byte, Flash memory of 512K byte, Serial,
10Base Ether and MMC.
http://web.kyoto-inet.or.jp/people/takagaki/T-SH7706/T-SH7706.htm
Signed-off-by: Nobuhiro Iwamatsu <[email protected]>
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After booting the u-boot, and first using some SD card (such as Sandisk 2G SD
card), because the field 'clock' of struct mmc is zero, this will cause
the read transfer is always active and SDHC DATA line is always active,
therefore, driver can't handle the next command.
Therefore, we use mmc_set_clock to setup both the data structure and HW
to the initial clock speed of 400000Hz.
Signed-off-by: Jerry Huang <[email protected]>
Tested-by: Stefano Babic <[email protected]>
Signed-off-by: Kumar Gala <[email protected]>
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Add reginfo as a default command for p1022ds boards
Signed-off-by: Matthew McClintock <[email protected]>
Signed-off-by: Kumar Gala <[email protected]>
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This command is used to read the device ONFI parameters page.
Signed-off-by: Florian Fainelli <[email protected]>
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These id tables need not be writable.
Signed-off-by: Mike Frysinger <[email protected]>
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The non-reentrant versions of the hashtable functions operate on a single
shared hashtable. So if two different people try using these funcs for
two different purposes, they'll cause problems for the other.
Avoid this by converting all existing hashtable consumers over to the
reentrant versions and then punting the non-reentrant ones.
Signed-off-by: Mike Frysinger <[email protected]>
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New default partitions on nor flash:
640k (firmware)
1408k (kernel)
2m (initrd)
4m (small-fs)
24320k (big-fs)
256k (dts)
Signed-off-by: Heiko Schocher <[email protected]>
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Signed-off-by: Heiko Schocher <[email protected]>
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Signed-off-by: Wolfgang Denk <[email protected]>
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Add ARM Relocation Support
Signed-off-by: Sandeep Paulraj <[email protected]>
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Add ARM Relocation Support
Signed-off-by: Sandeep Paulraj <[email protected]>
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Add ARM Relocation Support
Signed-off-by: Sandeep Paulraj <[email protected]>
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Add ARM Relocation Support
Signed-off-by: Sandeep Paulraj <[email protected]>
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Some DaVinci boards are using flags that are no longer valid
So remove them.
Signed-off-by: Sandeep Paulraj <[email protected]>
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This patch adds the possibility to (optinally) write to the
flash configuration register. The Intel style CFI chips support
such a register that can be used to configure the operation
mode to a non-default value.
This method will be used by the t3corp board, which needs to
configure the DS617 Xilinx flash for async read mode.
Signed-off-by: Stefan Roese <[email protected]>
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Use common ppc4xx linker script for xilinx ppc440 and ppc405 related boards.
Signed-off-by: Ricardo Ribalda Delgado <[email protected]>
Signed-off-by: Stefan Roese <[email protected]>
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This patch includes the following changes for the lwmon5 board support:
- Enable cache in SDRAM
- Use common EHCI driver instead of the PPC4xx specific OHCI driver
This can be done since only high-speed devices are connected.
- Remove cached TLB entry again after ECC setup
- Use correct define for cache enabling
(CONFIG_4xx_DCACHE instead of CONFIG_SYS_ENABLE_SDRAM_CACHE)
- Enable FIT image support
Signed-off-by: Stefan Roese <[email protected]>
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The t3corp board has an Xilinx DS617 flash chip connected to the
onboard FPGA. This patch adds support for these chips. Board
specific flash accessor functions are needed, since the chips
can only be read correctly in 16bit mode.
Additionally the FPGA chip-selects are configured for device-paced
transfers (ready is enabled).
Signed-off-by: Stefan Roese <[email protected]>
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