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This patch provides support for AFEB9260 board, a product of
OpenSource hardware and software. Some commertial projects
are made with this design. A board is basically AT91SAM9260-EK
with some modifications and different peripherals and different
parts used. Main purpose of this project is to gain experience in
hardware design.
More info: http://groups.google.com/group/arm9fpga-evolution-board
(In Russian only, sorry).
Subversion repository: svn://194.85.238.22/home/users/george/svn/arm9eb
Signed-off-by: Sergey Lapin <[email protected]>
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We put the bootpg for the secondary cpus into memory and use
BPTR to get to it. This is a step towards converting to the
ePAPR boot methodology. Also, the code is written to
deal properly with more than 4GB of RAM.
Signed-off-by: Becky Bruce <[email protected]>
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There are several items in the config file that were hardcoded
but that should really be based on other config options, since
the regions are contiguous and depend on being so. This cleans
that up a bit. Also, add BR_PHYS_ADDR() macro to convert
addresses into the proper format for BR registers.
Signed-off-by: Becky Bruce <[email protected]>
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Currently, the CCSR gets relocated while translation is
enabled, meaning we need 2 BAT translations to get to both the
old location and the new location. Also, the DEFAULT
CCSR location has a dependency on the BAT that maps the
FLASH region. Moving the relocation removes this unnecessary
dependency. This makes it easier and more intutive to
modify the board's memory map.
Swap BATs 3 and 4 on 8610 so that all 86xx boards use the same
BAT for CCSR space.
Signed-off-by: Becky Bruce <[email protected]>
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You can't actually have both, and with some coming changes to
change the memory map for the board and support 36-bit physical,
we need the extra BAT that is being consumed by having both.
I also make non-PCI configs build cleanly, for the sake of sanity.
Signed-off-by: Becky Bruce <[email protected]>
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We don't actually ever do this, remove the code so we
can stop maintaining it.
Signed-off-by: Becky Bruce <[email protected]>
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Signed-off-by: TsiChung Liew <[email protected]>
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Add serial boot support
Signed-off-by: TsiChung Liew <[email protected]>
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Signed-off-by: TsiChung Liew <[email protected]>
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Place FEC pin assignments in cpu_init.c from platform's
mii.c
Signed-off-by: TsiChung Liew <[email protected]>
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Consolidate ATA, ePORT, QSPI, FlexCan, PWM, RNG,
MDHA, SKHA, INTC, and FlexBus structures and
definitions in immap_5xxx.h to more unify modules
header files. Append DSPI support for m547x_8x.
SSI cleanup. Remove USB Host structure from immap_539.h.
Apply changes to use FlexBus structures in mcf52x2's
cpu_init.c and platform configuration files.
Signed-off-by: TsiChung Liew <[email protected]>
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Signed-off-by: Wolfgang Denk <[email protected]>
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There were several, now there is one (two if you count the lower-case
versions).
Signed-off-by: Andy Fleming <[email protected]>
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Signed-off-by: Heiko Schocher <[email protected]>
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Signed-off-by: Wolfgang Denk <[email protected]>
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This removes in nand.h code that is verbatim duplicated from bbm.h,
including directly bbm.h in nand.h. The previous state of affairs
prevented compiling code for a board hosting both NAND and OneNAND chips.
Reported-by: Scott Wood <[email protected]>
Signed-off-by: Alessandro Rubini <[email protected]>
Signed-off-by: Scott Wood <[email protected]>
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This patch defines 1M TLB&LAW size for NAND on MPC8536DS, assigns 0xffa00000
for CONFIG_SYS_NAND_BASE and adds other NAND supports in config file.
It also moves environment(CONFIG_ENV_ADDR) outside of u-boot image.
Singed-off-by: Jason Jin <[email protected]>
Signed-off-by: Haiying Wang <[email protected]>
Signed-off-by: Kumar Gala <[email protected]>
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CONFIG_ENV_ADDR should be (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE).
Signed-off-by: Haiying Wang <[email protected]>
Signed-off-by: Kumar Gala <[email protected]>
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Signed-off-by: Matthias Fuchs <[email protected]>
Signed-off-by: Stefan Roese <[email protected]>
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Xilinx ppc440 and ppc405 have many similarities. This patch merge the
config files of both infrastuctures
Signed-off-by: Ricardo Ribalda Delgado <[email protected]>
Signed-off-by: Stefan Roese <[email protected]>
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Arches doesn't use PerCS3 but GPIO43, so let's configure the GPIO
pin multiplexing correctly
Signed-off-by: Stefan Roese <[email protected]>
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Signed-off-by: Dave Liu <[email protected]>
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This patch defines 1M TLB&LAW size for NAND on MPC8572DS, assigns
0xffa00000 for CONFIG_SYS_NAND_BASE and adds other NAND supports in
config file.
It also moves environment(CONFIG_ENV_ADDR) outside of u-boot image, to
make room for the increased code size with NAND enabled.
Signed-off-by: Jason Jin <[email protected]>
Signed-off-by: Haiying Wang <[email protected]>
Signed-off-by: Scott Wood <[email protected]>
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- Rename lbus83xx_t to fsl_lbus_t and move it to asm/fsl_lbc.h so that it
can be shared by both 83xx and 85xx
- Remove lbus83xx_t and replace it with fsl_lbus_t in all 83xx boards
files which use lbus83xx_t.
- Move FMR, FIR, FCR, FPAR, LTESR from mpc83xx.h to asm/fsl_lbc.h so that
85xx can share them.
Signed-off-by: Jason Jin <[email protected]>
Signed-off-by: Haiying Wang <[email protected]>
Signed-off-by: Scott Wood <[email protected]>
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This brings the core NAND code up to date with the Linux kernel.
Since there were several drivers in Linux as of the last update that are
not in u-boot, I'm not bringing over new drivers that have been added
since in the absence of an interested party.
I did not update OneNAND since it was recently synced by Kyungmin Park,
and I'm not sure exactly what the common ancestor is.
Signed-off-by: Scott Wood <[email protected]>
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Add the ability to break the steps of the bootm command into several
subcommands: start, loados, ramdisk, fdt, bdt, cmdline, prep, go.
This allows us to do things like manipulate device trees before
they are passed to a booting kernel or setup memory for a secondary
core in multicore situations.
Not all OS types support all subcommands (currently only start, loados,
ramdisk, fdt, and go are supported).
Signed-off-by: Kumar Gala <[email protected]>
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The MPC8572 has a 4-bit wide PORDEVSR IO_SEL field. Other MPC85xx
processors have a 3-bit wide IO_SEL field but have the most
significant bit is wired to 0 so this change should not affect
them.
Signed-off-by: Peter Tyser <[email protected]>
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The information displayed when CONFIG_LCD_INFO is set is inherently
board-specific, so it should be done by the board code. The current code
dealing with this only handles two cases, and is already a horrible mess
of #ifdeffery.
Yes, this duplicates some code, but it also allows boards to print more
board-specific information; this used to be very difficult.
Signed-off-by: Haavard Skinnemoen <[email protected]>
Signed-off-by: Anatolij Gustschin <[email protected]>
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atmel_lcdfb doesn't actually need anything from asm/arch/hardware.h. It
includes a file that does, asm/arch/gpio.h, but this file doesn't
include <asm/arch/hardware.h> like it's supposed to.
Add the missing include to asm/arch/gpio.h and remove the workaround
from the atmel_lcdfb driver. This makes the driver compile on avr32.
Signed-off-by: Haavard Skinnemoen <[email protected]>
Signed-off-by: Anatolij Gustschin <[email protected]>
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Converted MPC8610HCPD, MPC8641HPCN, and SBC8641D to use
fsl_pci_setup_inbound_windows() and ft_fsl_pci_setup().
With these changes the board code is a bit smaller and we get dma-ranges
set in the device tree for these boards.
Signed-off-by: Kumar Gala <[email protected]>
Signed-off-by: Andrew Fleming-AFLEMING <[email protected]>
Acked-by: Jon Loeliger <[email protected]>
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Converted ATUM8548, MPC8536DS, MPC8544DS, MPC8548CDS, MPC8568MDS,
MPC8572DS, TQM85xx, and SBC8548 to use fsl_pci_setup_inbound_windows()
and ft_fsl_pci_setup().
With these changes the board code is a bit smaller and we get dma-ranges
set in the device tree for these boards.
Signed-off-by: Kumar Gala <[email protected]>
Signed-off-by: Andrew Fleming-AFLEMING <[email protected]>
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Added fdt_pci_dma_ranges() that parses the pci_region info from the
struct pci_controller and populates the dma-ranges based on it.
The max # of windws/dma-ranges we support is 3 since on embedded
PowerPC based systems this is the max number of windows.
Signed-off-by: Kumar Gala <[email protected]>
Signed-off-by: Andrew Fleming-AFLEMING <[email protected]>
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Add helper functions to return find a node and return it's property
or a default value.
Signed-off-by: Kumar Gala <[email protected]>
Signed-off-by: Andrew Fleming-AFLEMING <[email protected]>
Acked-by: Gerald Van Baren <[email protected]>
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Signed-off-by: Kumar Gala <[email protected]>
Signed-off-by: Andrew Fleming-AFLEMING <[email protected]>
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Signed-off-by: Kumar Gala <[email protected]>
Signed-off-by: Andrew Fleming-AFLEMING <[email protected]>
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PCI bus is inherently 64-bit. While not all system require access to
the full 64-bit PCI address range some do. This allows those systems
to enable the full PCI address width via CONFIG_SYS_PCI_64BIT.
Signed-off-by: Kumar Gala <[email protected]>
Signed-off-by: Andrew Fleming-AFLEMING <[email protected]>
Acked-by: Wolfgang Denk <[email protected]>
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Signed-off-by: Dave Liu <[email protected]>
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Introduce CONFIG_E500MC to deal with the minor differences between
e500v2 and e500mc.
* Certain fields of HID0/1 don't exist anymore on e500mc
* Cache line size is 64-bytes on e500mc
* reset value of PIR is different
Signed-off-by: Kumar Gala <[email protected]>
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This patch adds support for the avnet fx12 minimodul.
It needs the "ppc4xx: Generic architecture for xilinx ppc405"
patch from Ricardo.
Signed-off-by: Georg Schardt <[email protected]>
Signed-off-by: Ricardo Ribalda Delgado <[email protected]>
Signed-off-by: Stefan Roese <[email protected]>
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As "ppc44x: Unification of virtex5 pp440 boards" did for the xilinx
ppc440 boards, this patch presents a common architecture for all the
xilinx ppc405 boards.
Any custom xilinx ppc405 board can be added very easily with no code
duplicity.
This patch also adds a simple generic board, that can be used on almost
any design with xilinx ppc405 replacing the file ppc405-generic/xparameters.h
This patch is prepared to work with the latest version of EDK (10.1)
Signed-off-by: Ricardo Ribalda Delgado <[email protected]>
Signed-off-by: Stefan Roese <[email protected]>
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Since the new autocalibration still has some problems on some Kilauea
boards with 200MHz DDR2 frequency we disable the autocalibration and
use the hardcoded values as done before. This seems to work reliably
on all known DDR2 frequencies.
After the autocalibration issue is fixed we will enable it again.
Signed-off-by: Stefan Roese <[email protected]>
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The SWRST register is a 16bit, not 32bit, register.
Signed-off-by: Mike Frysinger <[email protected]>
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Signed-off-by: Mike Frysinger <[email protected]>
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