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The Hammerhead platform is built around a AVR32 32-bit microcontroller
from Atmel. It offers versatile peripherals, such as ethernet, usb
device, usb host etc.
The board also incooperates a power supply and is a Power over Ethernet
(PoE) Powered Device (PD).
Additonally, a Cyclone III FPGA from Altera is integrated on the board.
The FPGA is mapped into the 32-bit AVR memory bus. The FPGA offers two
DDR2 SDRAM interfaces, which will cover even the most exceptional need
of memory bandwidth. Together with the onboard video decoder the board
is ready for video processing.
For more information see: http:///www.miromico.com/hammerhead
Signed-off-by: Julien May <[email protected]>
[[email protected]: various small fixes and adaptions]
Signed-off-by: Haavard Skinnemoen <[email protected]>
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Due to increased space usage, U-Boot can no longer be stored in three sectors.
The current U-Boot use just over three flash sectors (197k), and U-Boot will
become corrupt after saving environment variables. This patch adds another 64k
to CFG_MONITOR_LEN.
Signed-off-by: Frank E. Svendsbøe <[email protected]>
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Signed-off-by: Rafal Czubak <[email protected]>
Acked-by: Rafal Jaworowski <[email protected]>
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Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <[email protected]>
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Because the cmd_tbl_s structure depends on the configuration file, it
must be assured that config.h is included before the structure is
evaluated by the compiler. If this is not certain, it could happen
that the compiler generates structures of different size, depending
on the fact if the source file includes <config.h> before or after
<command.h>.
The effect is that u-boot crashes when tries to relocate the command
table (for ppc) or try to access to the command table for other
architectures.
The problem can happen on board-depending commands. All general
commands under /common are unaffected, because they include already
config.h before command.h.
Signed-off-by: Stefano Babic <[email protected]>
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Support for the adsvix was originally provided by Applied Data
Systems (ADS), inc., now EuroTech, Inc.
The board never shipped aside from some sample boards.
Signed-off-by: Adrian Filipi <[email protected]>
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Signed-off-by: Haavard Skinnemoen <[email protected]>
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map_physmem() takes a phys_addr_t as parameter. This type is defined in
asm/types.h, so we need to include that file.
Signed-off-by: Haavard Skinnemoen <[email protected]>
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Signed-off-by: Detlev Zundel <[email protected]>
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This patch defines CFG_64BIT_VSPRINTF and CFG_64BIT_STRTOUL for all
440/460 platforms. This may be needed since those platforms support
36bit physical address space.
Signed-off-by: Stefan Roese <[email protected]>
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Signed-off-by: Stefan Roese <[email protected]>
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The Xilinx ML507 Board is a Virtex 5 prototyping board that includes,
among others:
-Virtex 5 FX FPGA (With a ppc440x5 in it)
-256MB of SDRAM2
-32MB of Flash
-I2C Eeprom
-System ACE chip
-Serial ATA connectors
-RS232 Level Conversors
-Ethernet Transceiver
This patch gives support to a standard design produced by EDK for this
board: ppc440, uartlite, xilinx_int and flash
- Includes Changes propossed by Stefan Roese and Michal Simek
Signed-off-by: Ricardo Ribalda Delgado <[email protected]>
Acked-by: Stefan Roese <[email protected]>
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-This patchs gives support for the embbedded ppc440
on the Virtex5 FPGAs
-interrupts.c divided in uic.c and interrupts.c
-xilinx_irq.c for xilinx interrupt controller
-Include modifications propossed by Stefan Roese
Signed-off-by: Ricardo Ribalda Delgado <[email protected]>
Acked-by: Stefan Roese <[email protected]>
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Freescale ships MPC8315E-RDB boards either with TSEC1 and USB UTMI
support, or without TSEC1 but with USB ULPI PHY support in addition.
With this patch user can specify desired USB PHY.
Also, it seems that we can't distinguish the two boards in software, so
user have to set `mpc8315erdb' environment variable to either 'tsec1'
(TSEC1 enabled) or `ulpi' (board with ULPI PHY, TSEC1 disabled), so that
Linux will not probe for TSEC1.
Signed-off-by: Anton Vorontsov <[email protected]>
Signed-off-by: Kim Phillips <[email protected]>
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The MVBC_P is a MPC5200B based camera system with Intel Gigabit ethernet
controller (using e1000) and custom Altera Cyclone-II FPGA on PCI.
Signed-off-by: Andre Schwarz <[email protected]>
Signed-off-by: Grant Likely <[email protected]>
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Update the sys_eeprom.c file to handle both NXID and CCID EEPROM formats. The
NXID format replaces the older CCID format, but it's important to support both
since most boards out there still use the CCID format. This change is in
preparation for using one file to handle both formats. This will also unify
EEPROM support for all Freescale 85xx and 86xx boards.
Also update the 86xx board header files to use the standard CFG_I2C_EEPROM_ADDR
instead of ID_EEPROM_ADDR.
Signed-off-by: Timur Tabi <[email protected]>
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The L2_INIT_RAM option was unused, and recent changes to the TLB code
meant that the INIT_RAM TLBs weren't being cleared out. In order to reduce
the amount of mapped space attached to nothing, we change things so the TLBs
get cleared.
Signed-off-by: Andy Fleming <[email protected]>
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The fake flash bank was generating errors for anyone who didn't have a
PromJET hooked up to the board. As that constitutes the vast majority of
users, we remove it.
Signed-off-by: Andy Fleming <[email protected]>
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Add support for using a PCIe ATI Video card on PCIe2.
Signed-off-by: Kumar Gala <[email protected]>
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Add new L1/L2 SPRs related to e500mc cache config and control.
Signed-off-by: Kumar Gala <[email protected]>
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Make the default build for the sbc8560 board be powerpc
capable with libfdt support.
Signed-off-by: Paul Gortmaker <[email protected]>
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This was proposed by Paul Gortmaker in response to Wolfgang's comments on
similar #defines in sbc8560.h.
Signed-off-by: Andy Fleming <[email protected]>
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Add in the default fdt settings and the typical EXTRA_ENV
settings as borrowed from the mpc8560ads. Fix a couple
of stale references to the mpc8560ads dating back to the
original clone/fork.
Signed-off-by: Paul Gortmaker <[email protected]>
Signed-off-by: Andy Fleming <[email protected]>
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The existing config doesn't define CONFIG_HAS_ETH0, and so the
fdt support doesn't update the zeros in the dtb local-mac with
real data from the u-boot env. Since the existing config is
tailored to just two interfaces, get rid of the ETH2 definitions
at the same time.
Also don't include any end user specific data into the environment
by default -- things like MAC address, network parameters etc. need
to come from the end user.
Signed-off-by: Paul Gortmaker <[email protected]>
Signed-off-by: Andy Fleming <[email protected]>
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The definitions for the TSEC have become out of date. There is no
longer any such options like "CONFIG_MPC85xx_TSEC1" or similar.
Update to match those of other boards, like the MPC8560ADS.
Signed-off-by: Paul Gortmaker <[email protected]>
Acked-by: Ben Warren <[email protected]>
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Delete the crypto node if not on an E-processor. If on 8360 or 834x family,
check rev and up-rev crypto node (to SEC rev. 2.4 property values)
if on an 'EA' processor, e.g. MPC8349EA.
Signed-off-by: Kim Phillips <[email protected]>
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The 8544 DS doesn't have any cacheable Local Bus memories set up. By mapping
space for some anyway, we were allowing speculative loads into unmapped space,
which would cause an exception (annoying, even if ultimately harmless).
Removing LBC_CACHE_BASE, and using LBC_NONCACHE_BASE for the LBC LAW solves the
problem.
Signed-off-by: Andy Fleming <[email protected]>
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Signed-off-by: Wolfgang Denk <[email protected]>
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Signed-off-by: Michal Simek <[email protected]>
Acked-by: Stefan Roese <[email protected]>
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Clean Makefile
Move device specific values to driver for better reading
Signed-off-by: Michal Simek <[email protected]>
Acked-by: Stefan Roese <[email protected]>
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Signed-off-by: Michal Simek <[email protected]>
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Redesign uartlite driver to in_be32 and out_be32 macros
Fix missing header in io.h
Signed-off-by: Michal Simek <[email protected]>
Acked-by: Grant Likely <[email protected]>
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caused by missing dcache status/enable/disable functions.
Signed-off-by: Hugo Villeneuve <[email protected]>
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Add #define CONFIG_MCFTMR in EB+MCF-EV123.h configuration file
Signed-off-by: TsiChung Liew <[email protected]>
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The timer was assigned to wrong timer memory mapped which
caused udelay() and timer() not working properly.
Signed-off-by: TsiChung Liew <[email protected]>
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Signed-off-by: Kurt Mahan <[email protected]>
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Signed-off-by: Stefan Roese <[email protected]>
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Only the really needed ones are added (cascading and EMAC/MAL).
Signed-off-by: Stefan Roese <[email protected]>
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This patch continues the ppc440.h cleanup by removing some of the unused
defines.
Signed-off-by: Stefan Roese <[email protected]>
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This patch cleans up the 440SPe PCIe register usage. Now only defines
from the include/asm-ppc/4xx_pcie.h are used.
Signed-off-by: Stefan Roese <[email protected]>
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This patch reworks the 440GX interrupt handling so that the common 4xx
code can be used. The 440GX is an exception to all other 4xx variants
by having the cascading interrupt vectors not on UIC0 but on a special
UIC named UICB0 (UIC Base 0). With this patch now, U-Boot references
the 440GX UICB0 when UIC0 is selected. And the common 4xx interrupt
handling is simpler without any 440GX special cases.
Also some additional cleanup to cpu/ppc4xx/interrupt.c is done.
Signed-off-by: Stefan Roese <[email protected]>
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This 2nd patch now removes all UIC mask bit definition. They should be
generated from the vectors by using the UIC_MASK() macro from now on.
This way only the vectors need to get defined for new PPC's.
Also only the really used interrupt vectors are now defined. This makes
definitions for new PPC versions easier and less error prone.
Another part of this patch is that the 4xx emac driver got a little
cleanup, since now the usage of the interrupts is clearer.
Signed-off-by: Stefan Roese <[email protected]>
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