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When I set up Tegra's config files to put the environment into eMMC, I
assumed that CONFIG_ENV_OFFSET was a linearized address relative to the
start of the eMMC device, and spanning HW partitions boot0, boot1,
general* and the user area in order. However, it turns out that the
offset is actually relative to the beginning of the user area. Hence,
the environment block ended up in a different location to expected and
documented.
Set CONFIG_SYS_MMC_ENV_PART=2 (boot1) to solve this, and adjust
CONFIG_ENV_OFFSET to be relative to the start of boot1, not the entire
eMMC.
Signed-off-by: Stephen Warren <[email protected]>
Signed-off-by: Tom Warren <[email protected]>
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Some eMMC devices contain boot partitions, but do not set the PART_SUPPORT
bit in EXT_CSD_PARTITIONING_SUPPORT. Allow partition selection on such
devices, by enabling partition switching when EXT_CSD_BOOT_MULT is set.
Note that the Linux kernel enables access to boot partitions solely based
on the value of EXT_CSD_BOOT_MULT; EXT_CSD_PARTITIONING_SUPPORT only
influences access to "general" partitions.
eMMC devices affected by this issue exist on various NVIDIA Tegra
platforms (and presumably many others too), such as Harmony (plug-in eMMC),
Seaboard, Springbank, and Whistler (plug-in eMMC).
Signed-off-by: Stephen Warren <[email protected]>
Signed-off-by: Tom Warren <[email protected]>
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This commit enables NAND support on the Tamonten Evaluation Carrier and
adds the corresponding device tree nodes. Furthermore, the U-Boot
environment can now be stored in NAND.
Signed-off-by: Thierry Reding <[email protected]>
Signed-off-by: Tom Warren <[email protected]>
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Signed-off-by: Stephen Warren <[email protected]>
Signed-off-by: Tom Warren <[email protected]>
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This enables NAND support for the Seaboard.
Signed-off-by: Simon Glass <[email protected]>
Signed-off-by: Tom Warren <[email protected]>
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A device tree is used to configure the NAND, including memory
timings and block/pages sizes.
If this node is not present or is disabled, then NAND will not
be initialized.
Signed-off-by: Jim Lin <[email protected]>
Signed-off-by: Simon Glass <[email protected]>
Signed-off-by: Tom Warren <[email protected]>
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The NAND layer needs to use cache-aligned buffers by default. Towards this
goal. align the default buffers and their members according to the minimum
DMA alignment defined for the architecture.
Signed-off-by: Simon Glass <[email protected]>
Signed-off-by: Tom Warren <[email protected]>
Acked-by: Scott Wood <[email protected]>
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Signed-off-by: Stefano Babic <[email protected]>
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Signed-off-by: Stefano Babic <[email protected]>
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The manufacturer delivers the TAM3517 SOM with 4 MAC address.
They are stored on the EEPROM of the SOM. The patch adds a
function to get their values and set the ethaddr variables.
Signed-off-by: Stefano Babic <[email protected]>
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In order to use the serial interface on the PortuxG20 we need to enable the
level converter first by setting the PC9 pin to high. The level converter needs
some time to settle so we have to use the mdelay() function to wait for some
time. Unfortunately we have no timers available at board_early_init_f() so we
enable the serial output early within board_postclk_init().
Now the U-Boot output looks fine:
| U-Boot 2012.07-00132-gaf1a3b0-dirty (Aug 16 2012 - 18:21:32)
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| CPU: AT91SAM9G20
| Crystal frequency: 18.432 MHz
| CPU clock : 396.288 MHz
| Master clock : 132.096 MHz
| DRAM: 64 MiB
| WARNING: Caches not enabled
| NAND: 128 MiB
| In: serial
| Out: serial
| Err: serial
| Net: macb0
| Hit any key to stop autoboot: 0
Signed-off-by: Markus Hubig <[email protected]>
Signed-off-by: Andreas Bießmann <[email protected]>
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* add ram target for EB+CPUx9k2 board (eb_cpux9k2_ram_config)
Signed-off-by: Jens Scharsig <[email protected]>
Signed-off-by: Jens Scharsig (BuS Elektronik) <[email protected]>
Signed-off-by: Andreas Bießmann <[email protected]>
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The configuration that is common for all Integrator boards may
just as well be stored in a common include file as per pattern
from other boards. This eases maintenance quite a bit.
Signed-off-by: Linus Walleij <[email protected]>
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For some reasons we had an own implementaion of dram_init and
dram_init_banksize. This is not needed anymore, use the standard
kirkwood functions instead.
Signed-off-by: Holger Brunck <[email protected]>
cc: Prafulla Wadaskar <[email protected]>
cc: Valentin Longchamp <[email protected]>
cc: Gerlando Falauto <[email protected]>
Acked-By: Prafulla Wadaskar <[email protected]>
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According to our last HW measures, this could be raised while still
compatible with the potential delays on the lines.
Signed-off-by: Valentin Longchamp <[email protected]>
cc: Holger Brunck <[email protected]>
Acked-By: Prafulla Wadaskar <[email protected]>
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These parameters are used by the the sf probe command that are used by
our update script and they therefore need to be set for all of our
boards.
The timing is the same as for the ENV SPI NOR Flash (since it's the
same physical device) and takes the boco2 delay on the bus into account.
Signed-off-by: Valentin Longchamp <[email protected]>
cc: Holger Brunck <[email protected]>
Acked-by: Prafulla Wadaskar <[email protected]>
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Orion5x did not actually write GPIO output values
or input polarities, and ED Mini V2 had bad or
missing values for GPIO settings.
Signed-off-by: Albert ARIBAUD <[email protected]>
Acked-By: Prafulla Wadaskar <[email protected]>
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Signed-off-by: Josh Wu <[email protected]>
Signed-off-by: Andreas Bießmann <[email protected]>
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atmel_hw_nand_init_param().
This patch
1. extract the hwecc initialization code into one function. It is a preparation for adding atmel PMECC support.
2. enable CONFIG_SYS_NAND_SELF_INIT. Which make us can configurate the ecc parameters between nand_scan_ident() and nand_scan_tail().
Signed-off-by: Josh Wu <[email protected]>
[fix empty newline at EOF error and move return value check into ifdef]
Signed-off-by: Andreas Bießmann <[email protected]>
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Add at91sam9x5 series spi flash boot support
Using at91sam9x5ek_spiflash to configure, then it can boot from at25df321
serial flash
SPI mater work in 30Mhz speed, while not 1Mhz speed. This will base on
atmel_spi patch, or else, it will occur receive overrun
Signed-off-by: Bo Shen <[email protected]>
Signed-off-by: Andreas Bießmann <[email protected]>
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Remove CONFIG_ARCH_CPU_INIT for at91sam9g10ek and at91sam9m10g45ek
Signed-off-by: Bo Shen <[email protected]>
[rebase on TOT]
Signed-off-by: Andreas Bießmann <[email protected]>
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The old update script uses 'load_addr' which is never set. Use 'fileaddr'
instead which is automagically set by e.g. dhcp.
Signed-off-by: Andreas Bießmann <[email protected]>
cc: Stelian Pop <[email protected]>
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Remove CONFIG_ARCH_CPU_INIT, no need it anymore
Signed-off-by: Bo Shen <[email protected]>
Signed-off-by: Andreas Bießmann <[email protected]>
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The cache snooping feature of Freescale's eSDHC IP is not available on i.MX, so
disable it globally for this architecture. This avoids setting no_snoop for all
i.MX boards, and it prevents setting a reserved bit of a reserved register if
fsl_esdhc_mmc_init() is used on i.MX, like in
arch/arm/cpu/armv7/imx-common/cpu.c/cpu_mmc_init().
Since no_snoop was only used on i.MX, get rid of it BTW.
Signed-off-by: Benoît Thébaudeau <[email protected]>
Cc: Andy Fleming <[email protected]>
Cc: Stefano Babic <[email protected]>
Cc: Kim Phillips <[email protected]>
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for new boards
* Move Efika MX Smarttop and Smartbook boards into a "genesi" vendor directory
* Rename efikamx -> mx51_efikamx since there is an mx53_efikamx and mx6_efikamx to come
Signed-off-by: Matt Sealey <[email protected]>
Acked-by: Stefano Babic <[email protected]>
Acked-by: Stefano Babic <[email protected]>
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Signed-off-by: Marek Vasut <[email protected]>
Cc: Fabio Estevam <[email protected]>
Cc: Otavio Salvador <[email protected]>
Cc: Stefano Babic <[email protected]>
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Align the SSP clock speed with oscilator to achieve
higher transfer stability.
Signed-off-by: Marek Vasut <[email protected]>
Cc: Fabio Estevam <[email protected]>
Cc: Otavio Salvador <[email protected]>
Cc: Stefano Babic <[email protected]>
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Signed-off-by: Philippe Reynes <[email protected]>
Acked-by: Stefano Babic <[email protected]>
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Each i.MX has its own gpio.h, defining the same structure.
The internal GPIO controller has the same layout
(at least for the register used by u-boot) and can be shared.
Signed-off-by: Stefano Babic <[email protected]>
Tested-by: Matt Sealey <[email protected]>
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There is no need to undef an option that is not enabled by default.
Signed-off-by: Fabio Estevam <[email protected]>
Acked-by: Marek Vasut <[email protected]>
Acked-by: Stefano Babic <[email protected]>
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For i.MX233 addition the base registers need to be change so the SoC
definition needs to be known before the header include.
The following boards has been changed:
* apx4devkit
* m28evk
* mx28evk
* sc_sps_1
Signed-off-by: Otavio Salvador <[email protected]>
Acked-by: Stefano Babic <[email protected]>
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This allows a watchdog reset to start the ROM's
usb/serial downloader, or boot from an sdcard.
Signed-off-by: Troy Kisky <[email protected]>
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This allows a watchdog reset to start the ROM's
usb downloader, or boot from an sdcard.
Signed-off-by: Troy Kisky <[email protected]>
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Turn on data and instruction caches.
Signed-off-by: Fabio Estevam <[email protected]>
include/configs/apx4devkit.h | 2 --
1 files changed, 0 insertions(+), 2 deletions(-)
Acked-by: Veli-Pekka Peltola <[email protected]>
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Turn on data and instruction caches.
Signed-off-by: Fabio Estevam <[email protected]>
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Enable the PL310 L2 cache controller at TRATS Samsung board.
Signed-off-by: Lukasz Majewski <[email protected]>
Signed-off-by: Kyungmin Park <[email protected]>
Signed-off-by: Minkyu Kang <[email protected]>
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To support display port in exynos fb driver, added dp_enabled variable
in vidinfo structure that set in board file.
Signed-off-by: Donghwa Lee <[email protected]>
Signed-off-by: Kyungmin Park <[email protected]>
Signed-off-by: Minkyu Kang <[email protected]>
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Signed-off-by: Lukasz Majewski <[email protected]>
Signed-off-by: Kyungmin Park <[email protected]>
Signed-off-by: Minkyu Kang <[email protected]>
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This patch sets UART3 and MMC channle 0 for Exynos5250 Rev 1.0
Signed-off-by: Rajeshwari Shinde <[email protected]>
Signed-off-by: Minkyu Kang <[email protected]>
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Default spl/u-boot-spl.lds created by spl/Makefile resolves
the spl text load addr to 0x0. As 0x0 belongs to iROM addr so
Global variables can not be used.
Adding specific smdk5250-uboot-spl.lds makes possible to use Global Variables
in spl.
Signed-off-by: Alim Akhtar <[email protected]>
Signed-off-by: Rajeshwari Shinde <[email protected]>
Signed-off-by: Minkyu Kang <[email protected]>
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CONFIG_STACKSIZE is not referenced anywhere except on AVR32, but present
in most ARM board config files.
IRQs are only enabled for 1 config, so remove the unused config options
for IRQ and FIQ stack size as well.
Cc: Albert ARIBAUD <[email protected]>
Signed-off-by: Rob Herring <[email protected]>
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Add SPL options to tegra20 config files and enable SPL build for
tegra20 boards. Also remove redundant code from u-boot that is not
contained in SPL.
Signed-off-by: Allen Martin <[email protected]>
Acked-by: Stephen Warren <[email protected]>
Tested-by: Thierry Reding <[email protected]>
Signed-off-by: Tom Warren <[email protected]>
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Add tegra20-common-post.h to be consistent with other tegra20 boards.
Signed-off-by: Allen Martin <[email protected]>
Acked-by: Thierry Reding <[email protected]>
Acked-by: Stephen Warren <[email protected]>
Tested-by: Thierry Reding <[email protected]>
Signed-off-by: Tom Warren <[email protected]>
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Rename CONFIG_MACH_TEGRA_GENERIC to the less confusing CONFIG_TEGRA.
The meaning of the config options is now:
CONFIG_TEGRA - Any tegra chip
CONFIG_TEGRA20 - A tegra20 family chip
CONFIG_TEGRA30 - A tegra30 family chip (not added yet)
Signed-off-by: Allen Martin <[email protected]>
Acked-by: Stephen Warren <[email protected]>
Tested-by: Thierry Reding <[email protected]>
Signed-off-by: Tom Warren <[email protected]>
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This is make naming consistent with the kernel and devicetree and in
preparation of pulling out the common tegra20 code.
Signed-off-by: Allen Martin <[email protected]>
Acked-by: Stephen Warren <[email protected]>
Tested-by: Thierry Reding <[email protected]>
Signed-off-by: Tom Warren <[email protected]>
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The Raspberry Pi model B uses the BCM2835 SoC, has 256MB of RAM,
contains an SMSC 9512 USB LAN/Hub chip, and various IO connectors.
For more details, see http://www.raspberrypi.org/.
Various portions (cache enable, MACH_TYPE setup, RAM size limit, stack
relocation to top of RAM) extracted from work by:
Oleksandr Tymoshenko <[email protected]>.
GPIO driver enablement by Vikram Narayanan <[email protected]>.
Signed-off-by: Stephen Warren <[email protected]>
Acked-by: Tom Rini <[email protected]>
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Configuration in vexpress and u8500.v1 is different from what
is needed in u8500.v2. As such, card configuration specifics need
to reside in the board file rather than the driver.
Signed-off-by: John Rigby <[email protected]>
Signed-off-by: Mathieu Poirier <[email protected]>
Signed-off-by: Tom Rini <[email protected]>
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LAN and GBF need to be powered explicitely, doing so with
interface to AB8500 companion chip.
Signed-off-by: Mathieu Poirier <[email protected]>
Signed-off-by: John Rigby <[email protected]>
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