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Add mvsata_ide and cmd_ide configuration in edminiv2 config
Signed-off-by: Albert Aribaud <[email protected]>
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CONFIG_IDE_SWAP_IO
This configuration option replaces a complex conditional
in cmd_ide.c with an explicit define to be added to SoC or
board configs.
Signed-off-by: Albert Aribaud <[email protected]>
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Specify vram on command line, remove erroneous call to nandboot
in the boot script, add CONFIG_BOOTDELAY
Signed-off-by: Steve Sakoman <[email protected]>
Acked-by: Nishanth Menon <[email protected]>
Signed-off-by: Sandeep Paulraj <[email protected]>
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Signed-off-by: Steve Sakoman <[email protected]>
Signed-off-by: Sandeep Paulraj <[email protected]>
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Signed-off-by: Steve Sakoman <[email protected]>
Signed-off-by: Sandeep Paulraj <[email protected]>
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This patch add the basic infrastructure for the TWL6030 driver and enables
support in the two existing OMAP4 boards, Panda and OMAP4430 SDP
Signed-off-by: Steve Sakoman <[email protected]>
Signed-off-by: Sandeep Paulraj <[email protected]>
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The OMAP4 x-load code sets gptimer1 clock source to 32Khz. This isn't
acceptable for udelay. This patch changes from gptimer1 to gptimer2,
which uses sys_clk at 38.4 Mhz.
Signed-off-by: Steve Sakoman <[email protected]>
Signed-off-by: Sandeep Paulraj <[email protected]>
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Add functional multiplexing support for OMAP4 pads.
Configure all the pads for the OMAP4430 SDP
and OMAP4 Panda boards
Signed-off-by: Steve Sakoman <[email protected]>
Signed-off-by: Aneesh V <[email protected]>
Signed-off-by: Sandeep Paulraj <[email protected]>
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While running from flash, i. e. before relocation, we have only a
limited C runtime environment without writable data segment. In this
phase, some configurations (for example with environment in EEPROM)
must not use the normal getenv(), but a special function. This
function had been called getenv_r(), with the idea that the "_r"
suffix would mean the same as in the _r_eentrant versions of some of
the C library functions (for example getdate vs. getdate_r, getgrent
vs. getgrent_r, etc.).
Unfortunately this was a misleading name, as in U-Boot the "_r"
generally means "running from RAM", i. e. _after_ relocation.
To avoid confusion, rename into getenv_f() [as "running from flash"]
Signed-off-by: Wolfgang Denk <[email protected]>
Acked-by: Detlev Zundel <[email protected]>
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Adds the board_mmc_init function and enable the mmc command
Signed-off-by: Minkyu Kang <[email protected]>
Signed-off-by: Jaehoon Chung <[email protected]>
Signed-off-by: Kyungmin Park <[email protected]>
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because it's convenient.
Signed-off-by: Kim Phillips <[email protected]>
Signed-off-by: Kumar Gala <[email protected]>
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Add support for the P4080DS board, with the following features:
* 36-bit only
* Boots from NOR flash
* FMAN drivers NOT supported
* SPD DDR initialization
Signed-off-by: Ed Swarthout <[email protected]>
Signed-off-by: Emil Medve <[email protected]>
Signed-off-by: Becky Bruce <[email protected]>
Signed-off-by: Ashish Kalra <[email protected]>
Signed-off-by: Stuart Yoder <[email protected]>
Signed-off-by: Dave Liu <[email protected]>
Signed-off-by: Lan Chunhe-B25806 <[email protected]>
Signed-off-by: Scott Wood <[email protected]>
Signed-off-by: Kim Phillips <[email protected]>
Signed-off-by: Roy Zang <[email protected]>
Signed-off-by: Timur Tabi <[email protected]>
Signed-off-by: Andy Fleming <[email protected]>
Signed-off-by: York Sun <[email protected]>
Signed-off-by: Kumar Gala <[email protected]>
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Enabled SPD
Enabled DDR2
Enabled hwconfig
Signed-off-by: York Sun <[email protected]>
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Enabled registered DIMMs using data from SPD. RDIMMs have registers
which need to be configured before using. The register configuration
words are stored in SPD byte 60~116 (JEDEC standard No.21-C). Software
should read those RCWs and put into DDR controller before initialization.
Signed-off-by: York Sun <[email protected]>
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Verified on MPC8641HPCN with four DDR2 dimms. Each dimm has dual
rank with 512MB each rank.
Also check dimm size and rank size for memory controller interleaving
Signed-off-by: York Sun <[email protected]>
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If we are creating reference (handles) to nodes in a device tree we need
to first create a new phandle in node and this needs a new phandle
value. So we search through the whole dtb to find the max phandle value
and return the next greater value for a new phandle allocation.
Signed-off-by: Kumar Gala <[email protected]>
Acked-by: Gerald Van Baren <[email protected]>
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If 36-bit is enabled, move INIT_RAM_ADDR physical address higher
to free lowest 4GB address space.
Signed-off-by: York Sun <[email protected]>
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Use the new common gpio framework to simplify and unify the soft i2c
configuration settings.
Signed-off-by: Mike Frysinger <[email protected]>
Acked-by: Heiko Schocher <[email protected]>
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- reformat
- throw out macros like FAT_DPRINT and FAT_DPRINT
- remove dead code
Signed-off-by: Wolfgang Denk <[email protected]>
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Signed-off-by: Stefan Roese <[email protected]>
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Signed-off-by: Stefan Roese <[email protected]>
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This patch fixes some problems for the T3CORP board. Here the list
of the changes:
- Add 600-67 and 677 CPU frequency setting to chip_config
command
- Define CONFIG_DDR_RFDC_FIXED on t3corp:
While using the "normal" auto calibration code, sometimes values for
RFDC were picked (>= T3) that resulted in a non-working U-Boot (hang
upon relocation, while running from SDRAM). With this optimized RFDC
value we can force this register and use the auto-calibration code to
setup the remaining calibration registers.
- Increase sizes of FPGA chips selects
- EBC timing updated OEN=3 for 66 MHz EBC speed
- Change ext. IRQ2 setup to level-low active
- Enable CONFIG_SYS_CFI_FLASH_STATUS_POLL
By defining CONFIG_SYS_CFI_FLASH_STATUS_POLL, DQ7 is polled to detect the
chip busy status. This is now used instead of the data toggle method which
is used historically by default in the common CFI driver. With this change
a problem with not written data is solved on this board, where a 32 byte
block of data is still erased instead of filled with the correct content
after these commands:
=> erase 0xfc100000 +0x1000000
....................................................................
done
Erased 128 sectors
=> cp.b 0x100000 0xfc100000 0x1000000
Copy to Flash... done
=> cmp.b 0x100000 0xfc100000 0x1000000
byte at 0x00d0d6c0 (0x00) != byte at 0xfcd0d6c0 (0xff)
Total of 12637888 bytes were the same
Signed-off-by: Stefan Roese <[email protected]>
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Functions added to support board callbacks for USB init. This
isolates USB manipulations such that it is only touched if USB is
used by U-Boot.
Signed-off-by: Dave Mitchell <[email protected]>
Signed-off-by: Rupjyoti Sarmah <[email protected]>
Signed-off-by: Stefan Roese <[email protected]>
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Move serdes init until after we are in ram so we can keep track of a
global static protocal map for the particular serdes config we are in.
This makes is_serdes_configured() much simplier and not constantly
reading registers to determine if a given device is enabled based on the
protocol.
Signed-off-by: Kumar Gala <[email protected]>
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Move serdes init until after we are in ram so we can keep track of a
global static protocal map for the particular serdes config we are in.
This makes is_serdes_configured() much simplier and not constantly
reading registers to determine if a given device is enabled based on the
protocol.
Signed-off-by: Kumar Gala <[email protected]>
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Given a compatible string and physical address try and find a node that
matches. This is useful when we want to find a specific device node to
update (for example if we have multiple PCI nodes we can use the
physical address to distinguish them when trying to update the device
tree).
Signed-off-by: Kumar Gala <[email protected]>
Acked-by: Gerald Van Baren <[email protected]>
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This code is extracted out of the Linux Kernel code from
arch/powerpc/kernel/prom_parse.c.
We maintain some of the same structure to support multiple bus types even
though we only have one in the current code. In the future we might want
to translate across a PCI bus and thus it will be easier to add that
functionality back in.
Signed-off-by: Kumar Gala <[email protected]>
Acked-by: Gerald Van Baren <[email protected]>
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The MPC8641 boards actually only have PCIE not PCI. Rename so we are
uniform with regards to names so we can replace this code with templated
code.
Signed-off-by: Kumar Gala <[email protected]>
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Remove dupliacted setting of PCI/PCIe address and offsets in board
config.h. Renamed CONFIG_SYS_PCI1/2_ADDR to CONFIG_SYS_PCI1/2ADDR on
MPC8641 boards since its really PCIE controllers and not PCI.
Signed-off-by: Kumar Gala <[email protected]>
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Remove dupliacted setting of PCI/PCIe address and offsets in board
config.h.
Signed-off-by: Kumar Gala <[email protected]>
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The board maintainer states:
The GTH board is obsolete and has not been manufactured for
several years.
To my knowledge, no recent U-Boot build has been tested on that
card.
So drop support for this board.
Signed-off-by: Wolfgang Denk <[email protected]>
Cc: Thomas Lange <[email protected]>
Acked-by: Thomas Lange<[email protected]>
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Signed-off-by: Anatolij Gustschin <[email protected]>
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Signed-off-by: Kumar Gala <[email protected]>
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Signed-off-by: Kumar Gala <[email protected]>
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Add 'errata' command to report what errata we workaround. Report
workaround for erratum SATA-A001 on P1022/P1013.
Also sorted the CONFIG_CMD_* list.
Signed-off-by: Kumar Gala <[email protected]>
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Specifics:
1) 36-bit only
2) Booting from NOR flash only
3) Environment stored in NOR flash only
4) No SPI support
5) No DIU support
Signed-off-by: Timur Tabi <[email protected]>
Signed-off-by: Kumar Gala <[email protected]>
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Enables the Intel Pro/1000 PT Gb Ethernet PCI-E Network Adapter
configuration support for P1/P2 RDB.
Signed-off-by: Poonam Aggrwal <[email protected]>
Signed-off-by: Kumar Gala <[email protected]>
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The new command dumps the TLBCAM, the LAWs, and the BR/OR regs.
Add CONFIG_CMD_REGINFO to the config for all MPC85xx parts.
Signed-off-by: Becky Bruce <[email protected]>
Signed-off-by: Kumar Gala <[email protected]>
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Currently, 83xx, 86xx, and 85xx have a lot of duplicated code
dedicated to defining and manipulating the LBC registers. Merge
this into a single spot.
To do this, we have to decide on a common name for the data structure
that holds the lbc registers - it will now be known as fsl_lbc_t, and we
adopt a common name for the immap layouts that include the lbc - this was
previously known as either im_lbc or lbus; use the former.
In addition, create accessors for the BR/OR regs that use in/out_be32
and use those instead of the mismash of access methods currently in play.
I have done a successful ppc build all and tested a board or two from
each processor family.
Signed-off-by: Becky Bruce <[email protected]>
Acked-by: Kim Phillips <[email protected]>
Signed-off-by: Kumar Gala <[email protected]>
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Some parts that have an Enhanced Local Bus Controller weren't
setting CONFIG_FSL_ELBC. Fix this so we can use this define
properly going forward (currently it's only used if PHYS_64BIT is
set, which meant not all platforms needed to have it set correctly).
Signed-off-by: Becky Bruce <[email protected]>
Acked-by: Kim Phillips <[email protected]>
Signed-off-by: Kumar Gala <[email protected]>
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Signed-off-by: Vivek Mahajan <[email protected]>
Signed-off-by: Kumar Gala <[email protected]>
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We have several boards that use the same ICS307 CLK chip to drive the
System clock and DDR clock. Move the code into a common location so we
share it.
Convert the P2020DS board as the first to use the new common ICS307
code.
Signed-off-by: Kumar Gala <[email protected]>
Acked-by: Timur Tabi <[email protected]>
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CONFIG_SYS_FSL_SEC_COMPAT is set to 2 for the SEC 2.x and SEC 3.x.
Parts with newer SEC h/w versions will increment the number to
accomodate incompatible code changes.
Signed-off-by: Kim Phillips <[email protected]>
Signed-off-by: Kumar Gala <[email protected]>
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