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The code is now fixed to the point where we can safely enable
the L1 data cache. Enable the D-Cache and set it as write-alloc.
Signed-off-by: Marek Vasut <[email protected]>
Cc: Chin Liang See <[email protected]>
Cc: Dinh Nguyen <[email protected]>
Cc: Albert Aribaud <[email protected]>
Cc: Tom Rini <[email protected]>
Cc: Wolfgang Denk <[email protected]>
Cc: Pavel Machek <[email protected]>
Acked-by: Pavel Machek <[email protected]>
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The Cortex-A9 has 32-byte long L1 cachelines. Define this value.
Signed-off-by: Marek Vasut <[email protected]>
Cc: Chin Liang See <[email protected]>
Cc: Dinh Nguyen <[email protected]>
Cc: Albert Aribaud <[email protected]>
Cc: Tom Rini <[email protected]>
Cc: Wolfgang Denk <[email protected]>
Cc: Pavel Machek <[email protected]>
Acked-by: Pavel Machek <[email protected]>
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Add code necessary to program the FPGA part of SoCFPGA from U-Boot
with an RBF blob. This patch also integrates the code into the
FPGA driver framework in U-Boot so it can be used via the 'fpga'
command.
Signed-off-by: Pavel Machek <[email protected]>
Signed-off-by: Marek Vasut <[email protected]>
Cc: Chin Liang See <[email protected]>
Cc: Dinh Nguyen <[email protected]>
Cc: Albert Aribaud <[email protected]>
Cc: Tom Rini <[email protected]>
Cc: Wolfgang Denk <[email protected]>
Cc: Pavel Machek <[email protected]>
V2: Move the not-CPU specific stuff into drivers/fpga/ and base
this on the cleaned up altera FPGA support.
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The timer reload value is a property of the timer hardware and there
is no reason for this to be configurable. Place this into the timer
driver just like on the other hardware.
Signed-off-by: Marek Vasut <[email protected]>
Cc: Chin Liang See <[email protected]>
Cc: Dinh Nguyen <[email protected]>
Cc: Albert Aribaud <[email protected]>
Cc: Tom Rini <[email protected]>
Cc: Wolfgang Denk <[email protected]>
Cc: Pavel Machek <[email protected]>
Acked-by: Dinh Nguyen <[email protected]>
Acked-by: Pavel Machek <[email protected]>
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Add the entire bulk of code to read out clock configuration from the SoCFPGA
CPU registers. This is important for MMC, QSPI and UART drivers as otherwise
they cannot determine the frequency of their upstream clock.
Signed-off-by: Pavel Machek <[email protected]>
Signed-off-by: Marek Vasut <[email protected]>
Cc: Chin Liang See <[email protected]>
Cc: Dinh Nguyen <[email protected]>
Cc: Albert Aribaud <[email protected]>
Cc: Tom Rini <[email protected]>
Cc: Wolfgang Denk <[email protected]>
Cc: Pavel Machek <[email protected]>
V2: Fixed the L4 MP clock divider and synced the clock code with latest
rocketboards codebase (thanks Dinh for pointing this out)
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'topic/drivers/net-20141006', 'topic/tools/mkimage-20141006' and 'topic/arm/cache-20141006' into HEAD
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Like many platforms, the Altera socfpga platform requires that the
preloader be "signed" in a certain way or the built-in boot ROM will
not boot the code.
This change automatically creates an appropriately signed preloader
from an SPL image.
The signed image includes a CRC which must, of course, be generated
with a CRC generator that the SoCFPGA boot ROM agrees with otherwise
the boot ROM will reject the image.
Unfortunately the CRC used in this boot ROM is not the same as the
Adler CRC in lib/crc32.c. Indeed the Adler code is not technically a
CRC but is more correctly described as a checksum.
Thus, the appropriate CRC generator is added to lib/ as crc32_alt.c.
Signed-off-by: Charles Manning <[email protected]>
Signed-off-by: Marek Vasut <[email protected]>
Cc: Chin Liang See <[email protected]>
Cc: Dinh Nguyen <[email protected]>
Cc: Albert Aribaud <[email protected]>
Cc: Tom Rini <[email protected]>
Cc: Wolfgang Denk <[email protected]>
Cc: Pavel Machek <[email protected]>
Acked-by: Pavel Machek <[email protected]>
V2: - Zap unused constant
- Explicitly print an error message in case of error
- Rework the hdr_checksum() function to take the *header directly
instead of a plan buffer pointer
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Remove this symbol from configs, since it's unused.
Signed-off-by: Pavel Machek <[email protected]>
Signed-off-by: Marek Vasut <[email protected]>
Cc: Chin Liang See <[email protected]>
Cc: Dinh Nguyen <[email protected]>
Cc: Albert Aribaud <[email protected]>
Cc: Tom Rini <[email protected]>
Cc: Wolfgang Denk <[email protected]>
Cc: Pavel Machek <[email protected]>
Cc: Joe Hershberger <[email protected]>
Acked-by: Chin Liang See <[email protected]>
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The DMA descriptors used by the DW MMC block must be aligned to cacheline
size, otherwise we are unable to properly flush/inval cache over them and
we get data corruption.
The reason I chose this approach of expanding the structure is because
the driver allocates the descriptors in bulk. This approach does waste
space by inserting slop inbetween the descriptors, but it makes access
to the descriptors easy as the compiler does know the real size of the
structure. It also makes cache operations easy, since the size of the
structure is cache aligned and the structure start address is as well.
Signed-off-by: Marek Vasut <[email protected]>
Cc: Chin Liang See <[email protected]>
Cc: Dinh Nguyen <[email protected]>
Cc: Albert Aribaud <[email protected]>
Cc: Tom Rini <[email protected]>
Cc: Wolfgang Denk <[email protected]>
Cc: Pavel Machek <[email protected]>
Cc: Pantelis Antoniou <[email protected]>
Acked-by: Pavel Machek <[email protected]>
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Get rid of the line-over-80 problems and zap the typedef that
went alongside those enums.
Signed-off-by: Marek Vasut <[email protected]>
Cc: Chin Liang See <[email protected]>
Cc: Dinh Nguyen <[email protected]>
Cc: Albert Aribaud <[email protected]>
Cc: Tom Rini <[email protected]>
Cc: Wolfgang Denk <[email protected]>
Cc: Pavel Machek <[email protected]>
Acked-by: Pavel Machek <[email protected]>
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This patch adds support for the OT1200 series of devices.
Following components are used in u-boot:
+ ethernet
+ i2c
+ emmc
+ gpio
For more details see README.
Changes v1 > v2
- make use of enable_cspi_clock(..)
- fix usage of OUTPUT_40OHM define
- added README
Changes v2 > v3
- improve spelling in README
- added own copy of mx6q_4x_mt41j128.cfg
Signed-off-by: Christian Gmeiner <[email protected]>
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Remove this tab from env, since it's useless, just use spaces.
Signed-off-by: Marek Vasut <[email protected]>
Cc: Stefano Babic <[email protected]>
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Remove this tab from env, since it's useless, just use spaces.
Signed-off-by: Marek Vasut <[email protected]>
Cc: Stefano Babic <[email protected]>
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PERST_GPIO and POWER_GPIO are currently swapped.
Fix the GPIO assignments as per the board schematics.
Signed-off-by: Fabio Estevam <[email protected]>
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Besides converting the LS-XHL and LS-CHLv2 to generic board, fix a typo
which accidentally reverted the bootsource to 'hdd' although the default
bootsource should be 'legacy'.
Cc: Tom Rini <[email protected]>
Cc: Prafulla Wadaskar <[email protected]>
Signed-off-by: Michael Walle <[email protected]>
Signed-off-by: Prafulla Wadaskar <[email protected]>
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Siemens boards are now using DFU in fullspeed only. For
this CONFIG_USB_GADGET_DUALSPEED is undefined.
Signed-off-by: Heiko Schocher <[email protected]>
Cc: Tom Rini <[email protected]>
Cc: Lukasz Majewski <[email protected]>
Cc: Marek Vasut <[email protected]>
Cc: Liu Bin <[email protected]>
Cc: Lukas Stockmann <[email protected]>
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Use the new force parameter to make the stdio_deregister succeed, replacing
stdin with a nulldev, and assume that the usb keyboard will come back after
the reset.
Signed-off-by: Hans de Goede <[email protected]>
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In some cases we really want to move forward with a deregister, add a force
parameter to allow this, and replace the dev with a nulldev in this case.
Signed-off-by: Hans de Goede <[email protected]>
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These are used by Panasonic UniPhier SoC family.
Signed-off-by: Masahiro Yamada <[email protected]>
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This patch add HUSH command parser
Signed-off-by: Gerald Kerma <[email protected]>
Changes in v1:
- add HUSH command parser
Signed-off-by: Prafulla Wadaskar <[email protected]>
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This patch redefine MTDPARTS
Signed-off-by: Gerald Kerma <[email protected]>
Changes in v1:
- redefine MTDPARTS
Signed-off-by: Prafulla Wadaskar <[email protected]>
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This patch add MTDIDS and MTDPARTS defaults settings to sheevaplug
Signed-off-by: Gerald Kerma <[email protected]>
Changes in v1:
- add MTDIDS and MTDPARTS default to sheevaplug
Signed-off-by: Prafulla Wadaskar <[email protected]>
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This patch add MVSATA driver to sheevaplug
Signed-off-by: Gerald Kerma <[email protected]>
Changes in v1:
- add MVSATA driver to sheevaplug
- enable ext4 FS support
Signed-off-by: Prafulla Wadaskar <[email protected]>
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This patch move the environment offset in sheevaplug.
The size of the u-boot binary is become too big.
Fix saving environments was result of corrupting the u-boot.
Signed-off-by: Gerald Kerma <[email protected]>
Changes in v2:
- patch description
Changes in v1:
- fix sheevaplug environment offset
Signed-off-by: Prafulla Wadaskar <[email protected]>
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Select CONFIG_CMD_FUSE so that the fuse API commands can be used.
Signed-off-by: Fabio Estevam <[email protected]>
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Update the ddr scripts for LPDDR2 and add two build configs for LPDDR2
arm2 board. Since the LPDDR2 arm2 board has different DDR size, use
CONFIG_DDR_MB in defconfig to replace the PHYS_SDRAM_SIZE.
Signed-off-by: Ye.Li <[email protected]>
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This patch adds the i.MX6DL arm2 board support. The i.MX6DL ARM2
shared the same board with i.MX6Q ARM2 board since the i.MX6DL is
pin-pin compatible with i.MX6Q.
The patch also support the DDR 32-BIT mode option. Please define
CONFIG_DDR_32BIT in the board configure file to enable DDR 32-BIT
mode.But due to the board design, it's 64bit DDR buswidth physically,
so, if you CONFIG_DDR_32BIT, the DDR memory size will be half of it.
Signed-off-by: Ye.Li <[email protected]>
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Enable the CONFIG_CMD_FS_GENERIC on m53evk to avoid per-fs specific commands
and tweak the environment to cater for this new option.
Signed-off-by: Marek Vasut <[email protected]>
Cc: Stefano Babic <[email protected]>
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Enable the CONFIG_CMD_FS_GENERIC on m28evk to avoid per-fs specific commands
and tweak the environment to cater for this new option.
Signed-off-by: Marek Vasut <[email protected]>
Cc: Stefano Babic <[email protected]>
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Make sure the boot.scr exists on the card before loading it
from the card to avoid annoying message on the console.
Signed-off-by: Marek Vasut <[email protected]>
Cc: Stefano Babic <[email protected]>
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Make sure the boot.scr exists on the card before loading it
from the card to avoid annoying message on the console.
Signed-off-by: Marek Vasut <[email protected]>
Cc: Stefano Babic <[email protected]>
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1. Set the image load partition to the first FAT partition.
2. Set the kernel rootfs partition to the second partition.
Signed-off-by: Ye.Li <[email protected]>
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To support loading FDT file for kernel, add the fdt address,
file and loading script to arm2 board default environment.
Signed-off-by: Ye.Li <[email protected]>
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Some of the #defines in spi.h are not bracketed. To avoid future mistakes
add brackets. Also add an explanatory comment for SPI_CONN_DUAL_...
Signed-off-by: Simon Glass <[email protected]>
Reviewed-by: Jagannadha Sutradharudu Teki <[email protected]>
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Sandbox may as well support everything. This increases the amount of code
that is built/tested by sandbox, and also provides access to all the
supported SPI flash devices.
Signed-off-by: Simon Glass <[email protected]>
Reviewed-by: Jagannadha Sutradharudu Teki <[email protected]>
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LS1021AQDS has a variant with DDR4 slot. This patch adds a new defconfig
for this variant to enable DDR4 support. RAW timing parameters are not
added for DDR4. The board timing parameters are only tuned for single-
rank 1600 and 1800MT/s with Micron DIMM 9ASF51272AZ-2G1A1 due to DIMM
availability.
Signed-off-by: York Sun <[email protected]>
CC: Alison Wang <[email protected]>
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When booting with SP, RCW resides at the beginning of IFC NOR flash.
Signed-off-by: York Sun <[email protected]>
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Spin table is at the very beginning of boot code. Each core has an individual
release address within the spin table, the ft_cpu_setup fn updates the
"cpu-release-addr" property of each cpu node with the corresponding release
address.
Also fix CPU_RELEASE_ADDR to point to secondary_boot_func.
Signed-off-by: York Sun <[email protected]>
Signed-off-by: Arnab Basu <[email protected]>
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of_bus_default_count_cells can be used to get the #address-cells
and #size-cells defined by the current node's parent node. This
is required when using of_read_number to read from FDT nodes that
can be 32 or 64 bytes depending on values defined by the parent.
Signed-off-by: Arnab Basu <[email protected]>
CC: Scott Wood <[email protected]>
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This is being done so that it can be used outside 'fdt_support.c'. Making
life more convenient when reading device node properties that can be 32
or 64 bits long.
Signed-off-by: Arnab Basu <[email protected]>
Cc: Scott Wood <[email protected]>
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The driver was written using old DDR3 spec which only covers low speeds.
The value would be suboptimal for higher speeds. Fix both timing according
to latest DDR3 spec, remove tCKE as an config option.
Signed-off-by: York Sun <[email protected]>
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DP-DDR is used for DPAA, separated from main memory pool for general
use. It has 32-bit bus width and use a standard DDR4 DIMM (64-bit).
Signed-off-by: York Sun <[email protected]>
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U-boot has been initializing DDR for the main memory. The presumption
is the memory stays as a big continuous block, either linear or
interleaved. This change is to support putting some DDR controllers
to separated space without counting into main memory. The standalone
memory controller could use different number of DIMM slots.
Signed-off-by: York Sun <[email protected]>
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Add support of NOR and NAND flash for simulator target.
Here
IFC - CS0: NOR flash
IFC - CS1: NAND flash
Signed-off-by: Prabhakar Kushwaha <[email protected]>
Reviewed-by: York Sun <[email protected]>
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This option specifies the default Device Tree used for the run-time
configuration of U-Boot.
Signed-off-by: Masahiro Yamada <[email protected]>
Cc: Simon Glass <[email protected]>
Cc: Stephen Warren <[email protected]>
Cc: Minkyu Kang <[email protected]>
Cc: Michal Simek <[email protected]>
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This commit moves:
CONFIG_OF_CONTROL
CONFIG_OF_SEPARATE
CONFIG_OF_EMBED
CONFIG_OF_HOSTFILE
Because these options are currently not supported for SPL,
the "Device Tree Control" menu does not appear in the SPL
configuration.
Note:
zynq-common.h should be adjusted so as not to change the
default value of CONFIG_SPL_FAT_LOAD_PAYLOAD_NAME.
Signed-off-by: Masahiro Yamada <[email protected]>
Acked-by: Simon Glass <[email protected]>
Cc: Stephen Warren <[email protected]>
Cc: Minkyu Kang <[email protected]>
Acked-by: Michal Simek <[email protected]>
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The libc headers on FreeBSD and likely related projects as well contain an
header file, cdefs.h which provides similiar functionality as linux/compiler.h.
It provides compiler independent defines like __weak __packed, to allow
compiling with multiple compilers which might have a different syntax for such
extension.
Since that header file is included in multiple standard headers, like stddef.h
and stdarg.h, multiple definitions of those defines will be present if both are
included. When compiling u-boot the compiler will warn about it hundreds of
times since e.g. common.h will include both files indirectly.
commit 7ea50d52849fe8ffa5b5b74c979b60b1045d6fc9 "compiler_gcc: do not redefine
__gnu_attributes" prevented such redefinitions, but this was undone by commit
fb8ffd7cfc68b3dc44e182356a207d784cb30b34 "compiler*.h: sync
include/linux/compiler*.h with Linux 3.16".
Add the checks back where necessary to prevent such warnings.
As the original patch this checkpatch warning is ignored:
"WARNING: Adding new packed members is to be done with care"
Cc: Masahiro Yamada <[email protected]>
Cc: Tom Rini <[email protected]>
Signed-off-by: Jeroen Hofstee <[email protected]>
Acked-by: Masahiro Yamada <[email protected]>
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