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The on-board number of available usdhc devices is something board
specific. The patch moves CONFIG_SYS_FSL_USDHC_NUM out of
mx6qsabre_common.h and adds usdhc2 and usdhc4 support for mx6qsabresd
board.
To keep the default mmc device for environment same as before (usdhc3),
it moves CONFIG_SYS_MMC_ENV_DEV out of mx6qsabre_common.h and changes
it to 1 for mx6qsabresd.
Signed-off-by: Shawn Guo <[email protected]>
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Adjust the NAND partitioning layout so that there is a separate partition
for the ramdisk and fdt blob on the NAND.
Signed-off-by: Marek Vasut <[email protected]>
Cc: Detlev Zundel <[email protected]>
Cc: Stefano Babic <[email protected]>
Cc: Wolfgang Denk <[email protected]>
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Since commit c733681 (pmic: Extend PMIC framework to support multiple instances
of PMIC devices) mx53loco fails to allocate the memory for PMIC:
U-Boot 2013.01-rc2-dirty (Dec 20 2012 - 15:55:01)
Board: MX53 LOCO
I2C: ready
DRAM: 1 GiB
pmic_alloc: No available memory for allocation!
pmic_init: POWER allocation error!
CPU: Freescale i.MX53 family rev2.0 at 800 MHz
Reset cause: POR
MMC: FSL_SDHC: 0, FSL_SDHC: 1
Calling the PMIC related functions at a later stage, ie, from board_late_init()
fixes the issue.
Reported-by: Robert Nelson <[email protected]>
Signed-off-by: Fabio Estevam <[email protected]>
Tested-by: Stefano Babic <[email protected]>
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This allow use of mainline and Freescale BSP Linux kernel with same
environment.
Signed-off-by: Otavio Salvador <[email protected]>
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This allow use of mainline and Freescale BSP Linux kernel with same
environment.
Signed-off-by: Otavio Salvador <[email protected]>
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This allow use of mainline and Freescale BSP Linux kernel with same
environment.
Signed-off-by: Otavio Salvador <[email protected]>
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For a generic environment, we shouldn't have a fixed rootfs filesystem
so we drop it from env.
Signed-off-by: Otavio Salvador <[email protected]>
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Select CONFIG_OF_LIBFDT, so that a dt kernel can be launched.
Signed-off-by: Fabio Estevam <[email protected]>
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Select CONFIG_OF_LIBFDT so that a device tree kernel can be launched.
Signed-off-by: Fabio Estevam <[email protected]>
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Make the necessary adaptions for the new PMIC framework, so that mx25pdk can
be built again.
Signed-off-by: Fabio Estevam <[email protected]>
Acked-by: Stefano Babic <[email protected]>
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Conflicts:
drivers/power/power_fsl.c
include/configs/mx35pdk.h
include/configs/mx53loco.h
include/configs/woodburn_common.h
board/woodburn/woodburn.c
These boards still use the old old PMIC framework, so they
do not merge properly after the power framework was merged into
mainline.
Fix all conflicts and update woodburn to use Power Framework.
Signed-off-by: Stefano Babic <[email protected]>
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Change e-mail address of Luka Perkov.
Signed-off-by: Luka Perkov <[email protected]>
CC: Luka Perkov <[email protected]>
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The config is current broken. It compiles but does not boot because IDE is
enabled. Remove all IDE options, and enable SCSI instead.
Also add a working boot command and Linux bootargs, and enable command
line editing to make it easier to work with.
Signed-off-by: Simon Glass <[email protected]>
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This allows u-boot to figure out the partitions of a chrome-os install.
Signed-off-by: Gabe Black <[email protected]>
Signed-off-by: Simon Glass <[email protected]>
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Enable the display on coreboot, using CFB.
Signed-off-by: Simon Glass <[email protected]>
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This helps us monitor boot progress and determine where U-Boot dies if
there are any problems.
Signed-off-by: Stefan Reinauer <[email protected]>
Signed-off-by: Simon Glass <[email protected]>
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The default implementation of this function is just memset, but other
implementations will be needed when physical memory isn't accessible by
U-Boot using normal addressing mechanisms.
Signed-off-by: Gabe Black <[email protected]>
Signed-off-by: Che-Liang Chiou <[email protected]>
Signed-off-by: Simon Glass <[email protected]>
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Enable this option to support booting a zImage.
Signed-off-by: Simon Glass <[email protected]>
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Coreboot uses this controller to implement GPIO access.
Signed-off-by: Simon Glass <[email protected]>
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Implement <asm-generic/gpio.h> functions for Intel ICH6 and later.
Only GPIOs 0-31 are handled by this code.
Signed-off-by: Bill Richardson <[email protected]>
Signed-off-by: Simon Glass <[email protected]>
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This adds a docbook template for fs, and makes CBFS use it.
Signed-off-by: Simon Glass <[email protected]>
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As requested by Wolfgang, remove references to CREDITS in the CBFS
files.
Signed-off-by: Simon Glass <[email protected]>
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This patch fixes an issue with overlapping PCI regions
on boards with more than 64MB RAM.
Signed-off-by: Matthias Fuchs <[email protected]>
Signed-off-by: Stefan Roese <[email protected]>
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This patch adds support for the a3m071 board based on the
MPC5200.
Signed-off-by: Stefan Roese <[email protected]>
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This option protects the printf() functions from overflow.
Signed-off-by: Simon Glass <[email protected]>
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We want to support VGA, serial, USB keyboard and the Coreboot memory
console buffer.
Signed-off-by: Simon Glass <[email protected]>
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This patch builds upon the recently introduced CBMEM console
feature of coreboot.
CBMEM console uses a memry area allocated by coreboot to store
the console output. The memory area has a certain structure,
which allows to determine where the buffer is, the buffer size
and the location of the pointer in the buffer. This allows
different phases of the firmware (rom based coreboot, ram based
coreboot, u-boot after relocation with this change) to keep
adding text to the same buffer.
Note that this patch introduces a new console driver and adds the
driver to the list of drivers to be used for console output, i.e.
it engages only after u-boot relocates. Usiong CBMEM console for
capturing the pre-relocation console output will be done under a
separate change.
>From Linux, run the cbmem.py utility (which is a part of the coreboot
package) to see the output, e.g.:
vvvvvvvvvvvvvvvvv
SCSI: AHCI 0001.0300 32 slots 6 ports ? Gbps 0xf impl SATA mode
flags: 64bit ilck stag led pmp pio
...
Magic signature found
Kernel command line: "cros_secure quiet loglevel=1 console=tty2...
^^^^^^^^^^^^^^^^^
Note that the entire u-boot output fits into the buffer only if
the coreboot log level is reduced from the most verbose. Ether
the buffer size will have to be increased, or the coreboot
verbosity permanently reduced.
Signed-off-by: Vadim Bendebury <[email protected]>
Signed-off-by: Simon Glass <[email protected]>
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When __BYTEORDER_HAS_U64__ is not defined, we got warning following:
-----
/tmp/include/linux/byteorder/little_endian.h: In function ‘__cpu_to_be64p’:
/tmp/include/linux/byteorder/little_endian.h:71:2: warning: implicit declaration of function ‘__swab64p’
[-Wimplicit-function-declaration]
-----
Usually, __arch__swab64* required for __fswab64, __swab64p and __swab64s
is defined. Therefore, __BYTEORDER_HAS_U64__ is unnecessary.
This removes __BYTEORDER_HAS_U64__.
Signed-off-by: Nobuhiro Iwamatsu <[email protected]>
CC: Kim Phillips <[email protected]>
Reviewed-by: Kim Phillips <[email protected]>
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Coreboot boards have an LPC TPM connected, so enable this.
Signed-off-by: Simon Glass <[email protected]>
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Now that coreboot doesn't need the start16 code, remove it. We need
to remove the CONFIG_SYS_X86_RESET_VECTOR option from coreboot.h also.
Signed-off-by: Simon Glass <[email protected]>
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Putting global data on the stack simplifies the init process (and makes it
slightly quicker). During the 'flash' stage of the init sequence, global
data is in the CAR stack. After SDRAM is initialised, global data is copied
from CAR to the SDRAM stack
Signed-off-by: Graeme Russ <[email protected]>
Signed-off-by: Simon Glass <[email protected]>
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board configuration file is included before asm/config_mpc85xx.h.
however, CONFIG_FSL_SATA_V2 is defined in asm/config_mpc85xx.h.
it will never take effective in the board configuration file for
this kind of code :
#ifdef CONFIG_FSL_SATA_V2
...
#endif
To solve this problem, move CONFIG_FSL_SATA_V2 to board
configuration header file.
This patch reverts Timur's
commit:3e0529f742e893653848494ffb9f7cd0d91304bf
Signed-off-by: Roy Zang <[email protected]>
Signed-off-by: Andy Fleming <[email protected]>
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P2041RDB uses common corenet TLB and LAW. However it doesn't have promjet
connector. It is necessary to use the same base address for correct LAW
address. An offset is added for NOR flash.
Signed-off-by: York Sun <[email protected]>
Signed-off-by: Andy Fleming <[email protected]>
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The P5040DS reference board (a.k.a "Superhydra") is an enhanced version of
P3041DS/P5020DS ("Hydra") reference board.
Signed-off-by: Timur Tabi <[email protected]>
Signed-off-by: Shaohui Xie <[email protected]>
Signed-off-by: Andy Fleming <[email protected]>
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Move FMAN microcude from 0xEF000000 to 0xEFF40000 to free up the beginning
of this virtual bank so that this bank can store RCW or be used together
with other banks to store large images.
Signed-off-by: York Sun <[email protected]>
Signed-off-by: Andy Fleming <[email protected]>
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Tegra's MMC driver does DMA, and hence needs cache-aligned buffers. In
some cases (e.g. user load commands) this cannot be guaranteed by callers
of the MMC APIs. To solve this, modify the Tegra MMC driver to use the
new bounce_buffer_*() APIs.
Note: Ideally, all U-Boot code will always provide address- and size-
aligned buffers, so a bounce buffer will only ever be needed for user-
supplied buffers (e.g. load commands). Ensuring this removes the need
for performance-sucking bounce buffer cache management and memcpy()s.
The one known exception at present is the SCR buffer in sd_change_freq(),
which is only 8 bytes long. Solving this requires enhancing struct
mmc_data to know the difference between buffer size and transferred data
size, or forcing all callers of mmc_send_cmd() to have allocated buffers
using ALLOC_CACHE_ALIGN_BUFFER(), which while true in this case, is not
enforced in any way at present, and so cannot be assumed by the core MMC
code.
Signed-off-by: Stephen Warren <[email protected]>
Acked-by: Simon Glass <[email protected]>
Tested-by: Simon Glass <[email protected]>
Signed-off-by: Andy Fleming <[email protected]>
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The current bouncebuf API requires all parameters to be passed to both
bounce_buffer_start() and bounce_buffer_stop(). Modify the bouncebuf
start function to accept a state structure as a parameter, and only
require that state struct to be passed to the stop function. This
simplifies usage of the bounce buffer by clients.
Don't modify the data pointer, but rather store the temporary buffer in
this state struct. The bouncebuf code ensures that client code can
always use a single buffer pointer in the state structure, irrespective
of whether a bounce buffer actually had to be allocated.
Move cache management logic into the bounce buffer code, so that each
client doesn't have to duplicate this. I believe there's no need to
invalidate the buffer before a DMA operation, since flushing the cache
should prevent any write-backs.
Update the MXS MMC driver for this change.
Signed-off-by: Stephen Warren <[email protected]>
Acked-by: Simon Glass <[email protected]>
Tested-by: Simon Glass <[email protected]>
Signed-off-by: Andy Fleming <[email protected]>
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If any driver ever needs to use the bounce buffer API, it always needs
to use it. As such, providing a dummy implementation of those APIs when
CONFIG_BOUNCE_BUFFER isn't defined does not make sense. Remove the dummy
implementation.
Signed-off-by: Stephen Warren <[email protected]>
Acked-by: Simon Glass <[email protected]>
Tested-by: Simon Glass <[email protected]>
Signed-off-by: Andy Fleming <[email protected]>
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Commits 6dc71c8 "MMC: MXS: Toggle the generic bounce buffer on the
boards" and 49a627f "MMC: Remove the MMC bounce buffer" replaced
CONFIG_MMC_BOUNCE_BUFFER with CONFIG_BOUNCE_BUFFER, but missed
converting a few boards over to the new option. Fix this.
Signed-off-by: Stephen Warren <[email protected]>
Acked-by: Simon Glass <[email protected]>
Tested-by: Simon Glass <[email protected]>
Signed-off-by: Andy Fleming <[email protected]>
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Bring in the code from Linux kernel.
Added to Linux kernel by:
commit e08c1694d9e2138204f2b79b73f0f159074ce2f5
Author: Andres Salomon <[email protected]>
Date: Fri Jul 4 10:00:03 2008 -0700
Some HW balks when writing both voltage setting and power up at the same
time to SDHCI_POWER_CONTROL register.
Signed-off-by: Rommel G Custodio <[email protected]>
CC: Andy Fleming <[email protected]>
v2: fix attribution and SOB
Signed-off-by: Andy Fleming <[email protected]>
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Signed-off-by: Josh Wu <[email protected]>
Acked-by: Andreas Bießmann <[email protected]>
Signed-off-by: Andy Fleming <[email protected]>
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usbdescriptors.h conflicts with linux/usb/ch9.h
Remove it.
Signed-off-by: Pantelis Antoniou <[email protected]>
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This patch adds a NAND Flash torture feature, which is useful as a block stress
test to determine if a block is still good and reliable (or should be marked as
bad), e.g. after a write error.
This code is ported from mtd-utils' lib/libmtd.c.
Signed-off-by: Benoît Thébaudeau <[email protected]>
Cc: Scott Wood <[email protected]>
[[email protected]: removed unnec. ifdef and unwrapped error strings]
Signed-off-by: Scott Wood <[email protected]>
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Use a flag instead of a hard-coded macro so that sub-page reads can be
enabled in other cases (such as on-die ecc).
This is the same as a5ff4f102937a3492bca4a9ff0c341d78813414c in Linux
Signed-off-by: Joe Hershberger <[email protected]>
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This allows DDR configuration to be deferred to the final U-Boot image,
which is able to make use of SPD data. The SPL itself cannot use SPD due
to code size constraints. It previously used fixed register values for
DDR configuration, and those values did not work on the p2020rdb-pca
board I tested with. It's possible that different revisions of the board
require different settings. Using SPD eliminates that problem.
Signed-off-by: Scott Wood <[email protected]>
Cc: Andy Fleming <[email protected]>
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