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Commit 1eb0c03c2198a7ec9de456b83dacdc4831b96cbf added
SPL_SYS_MALLOC_SIMPLE Kconfig option and changed the way it is
evaluated.
Thus, the definitions of CONFIG_SYS_MALLOC_SIMPLE in rk3***_common.h
board configs are now incorrect because CONFIG_SPL_BUILD is enabled so
CONFIG_IS_ENABLED(SYS_MALLOC_SIMPLE) will look for SPL_SYS_MALLOC_SIMPLE
instead of SYS_MALLOC_SIMPLE.
This commit fix this enabling SPL_SYS_MALLOC_SIMPLE with the new Kconfig
option by default in rockchip-mach.
Signed-off-by: Ariel D'Alessandro <[email protected]>
Acked-by: Simon Glass <[email protected]>
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This add some basic files required to allow the board to dispaly
serial message and can run command(mmc info etc)
Signed-off-by: Lin Huang <[email protected]>
Acked-by: Simon Glass <[email protected]>
Moved board Kconfig fragment from previous patch into this one to fix
build error:
Signed-off-by: Simon Glass <[email protected]>
Series-changes: 8
- moved board Kconfig fragment from previous patch into this one
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rk3036 only 4K size SRAM for SPL, so only support
timer, uart, sdram driver in SPL stage, when finish
initial sdram, back to bootrom.And in rk3036 sdmmc and
debug uart use same iomux, so if you want to boot from
sdmmc, you must disable debug uart.
Signed-off-by: Lin Huang <[email protected]>
Acked-by: Simon Glass <[email protected]>
Fixed build error for chromebook_jerry, firefly-rk3288:
Signed-off-by: Simon Glass <[email protected]>
Series-changes: 8
- Fix build error for chromebook_jerry, firefly-rk3288
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some soc(rk3036 etc) use dw_mmc but do not have internal dma,
so we implement fifo mode to read and write data.
Signed-off-by: Lin Huang <[email protected]>
Acked-by: Simon Glass <[email protected]>
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Since rk3036 device tree file still in reviewing, bring it from
https://patchwork.kernel.org/patch/7203371/ and add some aliases
we need in uboot
Signed-off-by: Lin Huang <[email protected]>
Acked-by: Simon Glass <[email protected]>
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some rockchips soc will not use uclass in SPL stage,
so define config to decide whether to build common.c
Signed-off-by: Lin Huang <[email protected]>
Acked-by: Simon Glass <[email protected]>
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some rockchip soc will not include lib/timer.c in SPL stage,
so implement timer driver for some soc can use us delay function in SPL.
Signed-off-by: Lin Huang <[email protected]>
Acked-by: Simon Glass <[email protected]>
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Save the environment on the SD card for Firefly in the empty space
between the SPL and the u-boot image.
Signed-off-by: Sjoerd Simons <[email protected]>
Acked-by: Simon Glass <[email protected]>
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Similar to load an fdt, when loading an initrd about the 512Mb mark
things seem to break. For now force loading below 512Mb until the reason
why this fails has been determined/solved.
Signed-off-by: Sjoerd Simons <[email protected]>
Acked-by: Simon Glass <[email protected]>
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We eventually need to drop the compatibility functions for driver model. As
a first step, create a configuration option to enable them and hide them
when the option is disabled.
Signed-off-by: Simon Glass <[email protected]>
Reviewed-by: Bin Meng <[email protected]>
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Adjust this command to use the correct PCI functions, instead of the
compatibility layer.
Signed-off-by: Simon Glass <[email protected]>
Reviewed-by: Bin Meng <[email protected]>
Tested-by: Bin Meng <[email protected]>
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With driver mode, struct pci_controller is stored as uclass-private data.
Add a comment to that effect.
Signed-off-by: Simon Glass <[email protected]>
Reviewed-by: Bin Meng <[email protected]>
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Adjust the Tegra PCI driver to support driver model and move all boards over
at the same time. This can make use of some generic driver model code, such
as the range-decoding logic.
Signed-off-by: Simon Glass <[email protected]>
Tested-by: Stephen Warren <[email protected]>
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This function looks up the controller and returns a pointer to each region
type.
Signed-off-by: Simon Glass <[email protected]>
Acked-by: Stephen Warren <[email protected]>
Tested-by: Stephen Warren <[email protected]>
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A PCI bus may be a bridge device where the controller is the bridge's
parent. Add a function to return the controller device, given a PCI device.
Signed-off-by: Simon Glass <[email protected]>
Acked-by: Stephen Warren <[email protected]>
Tested-by: Stephen Warren <[email protected]>
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Provide a few functions to support using 32-bit access to emulate 8- and
16-bit access.
Signed-off-by: Simon Glass <[email protected]>
Reviewed-by: Stephen Warren <[email protected]>
Tested-by: Stephen Warren <[email protected]>
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This is not supported with driver model, so print a message instead of
generating a build error. Rescanning PCI is not yet implemented.
This function will be implemented later once some additional PCI driver
model improvements are merged. It was confirmed on the mailing list
that no one on the tegra side will miss this feature, so it is disabled
for tegra.
Signed-off-by: Simon Glass <[email protected]>
Tested-by: Stephen Warren <[email protected]>
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Move this option to Kconfig and fix up all users.
Signed-off-by: Simon Glass <[email protected]>
Tested-by: Stephen Warren <[email protected]>
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To group all dm timer drivers together, move tsc timer to
drivers/timer directory.
Signed-off-by: Bin Meng <[email protected]>
Acked-by: Simon Glass <[email protected]>
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There are timers with a 64-bit counter value but current timer
uclass driver assumes a 32-bit one. Modify timer_get_count()
to ask timer driver to always return a 64-bit counter value,
and provide an inline helper function timer_conv_64() to handle
the 32-bit/64-bit conversion automatically.
Signed-off-by: Bin Meng <[email protected]>
Acked-by: Simon Glass <[email protected]>
Signed-off-by: Simon Glass <[email protected]>
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This changes 'Timer' to 'timer' at several places.
Signed-off-by: Bin Meng <[email protected]>
Acked-by: Thomas Chou <[email protected]>
Reviewed-by: Simon Glass <[email protected]>
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The board supports following features:
- Boot media support: SD card/e.MMC/SPI flash,
- Support LCD display (optional, disabled by default),
- Support ethernet,
- Support USB mass storage.
Signed-off-by: Wenyou Yang <[email protected]>
[fix checkpatch warnings]
Signed-off-by: Andreas Bießmann <[email protected]>
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As the environment variables "serial#" and "ethaddr" need to be
overwriten by the users, CONFIG_ENV_OVERWRITE is defined to disable
the write protection. Anybody can change or delete these parameters.
Signed-off-by: Alison Wang <[email protected]>
Reviewed-by: York Sun <[email protected]>
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As 3G/1G user/kernel memory split is used on LS1021A, the Linux kernel
fails to access the device tree blob on boot. The reason is that u-boot
relocates the device tree blob into high memory when booting the kernel
and the kernel is unable to access the blob.
To avoid this issue, fdt_high is set to the value of 0xffffffff. The
device tree blob will not get relocated and is still in low memory to
make it accessible to the kernel.
For the same reason, initrd_high is set to the value of 0xffffffff too.
This patch is to update fdt_high and initrd_high for LS1021AQDS board.
Signed-off-by: Alison Wang <[email protected]>
Reviewed-by: York Sun <[email protected]>
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Freescale LSCH3 platforms use two DDR controlers interleaving mode out of
reset. It can be configured to disable one controller. To support this
operation, the driver needs to detect and skip the disabled controller.
Signed-off-by: York Sun <[email protected]>
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Add support for the third USB controller for LS1043A.
Signed-off-by: Gong Qianyu <[email protected]>
Reviewed-by: York Sun <[email protected]>
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Use the U-Boot Driver Model. Just enable Freescale DSPI driver
and set DSPI related parameters in dts file.
Signed-off-by: Gong Qianyu <[email protected]>
Reviewed-by: York Sun <[email protected]>
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LS1043AQDS Specification:
-------------------------
Memory subsystem:
* 2GByte DDR4 DIMM
* 128 Mbyte NOR flash single-chip memory
* 512 Mbyte NAND flash
* 16 Mbyte high-speed SPI flash
* SD connector to interface with the SD memory card
Ethernet:
* Two RGMII ports
* XFI 10G port
* SGMII
* QSGMII with 4x 1G ports
PCIe: supports Gen 1 and Gen 2
SATA 3.0: one SATA 3.0 port
USB 3.0: two micro AB connector and one type A connector
UART: supports two UARTs up to 115200 bps for console
Signed-off-by: Shaohui Xie <[email protected]>
Signed-off-by: Mingkai Hu <[email protected]>
Signed-off-by: Hou Zhiqiang <[email protected]>
Signed-off-by: Gong Qianyu <[email protected]>
[York Sun: Add CONFIG_SYS_NS16550=y in defconfig]
Reviewed-by: York Sun <[email protected]>
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Freescale's LS2085A is a another personality of LS2080A SoC with
support of AIOP and DP-DDR.
This Patch adds support of LS2085A Personality.
Signed-off-by: Pratiyush Mohan Srivastava <[email protected]>
Signed-off-by: Prabhakar Kushwaha <[email protected]>
[York Sun: Updated MAINTAINERS files
Dropped #ifdef in cpu.h
Add CONFIG_SYS_NS16550=y in defconfig]
Reviewed-by: York Sun <[email protected]>
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LS2080A is a prime personality of Freescale’s LS2085A. It is a non-AIOP
personality without support of DP-DDR, L2 switch, 1588, PCIe endpoint etc.
So renaming existing LS2085A code base to reflect LS2080A (Prime personality)
Signed-off-by: Pratiyush Mohan Srivastava <[email protected]>
Signed-off-by: Prabhakar Kushwaha <[email protected]>
[York Sun: Dropped #ifdef in cpu.c for cpu_type_list]
Reviewed-by: York Sun <[email protected]>
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As per current implementation of DPAA2 ethernet driver DPNI is used as
net device. DPNI is tangible objects can be multiple connected to same physical lane.
Use DPMAC as net device where it represents physical lane.
Below modification done in driver
- Use global DPNI object
- Connect DPMAC to DPNI
- Create and destroy DPMAC
Signed-off-by: Prabhakar Kushwaha <[email protected]>
Reviewed-by: York Sun <[email protected]>
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Freescale's DPAA2 ethernet driver depends upon the static DPL for the
DPRC, DPNI, DPBP, DPIO objects.
Instead of static objects, Create DPNI, DPBP, DPIO objects at run-time.
Signed-off-by: Prabhakar Kushwaha <[email protected]>
Reviewed-by: York Sun <[email protected]>
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Management complex Firmware, DPL and DPC are depolyed during u-boot boot
sequence.
Add new DPAA2 commands to manage Management Complex (MC) i.e. start mc, aiop
and apply DPL from u-boot command prompt.
Signed-off-by: Prabhakar Kushwaha <[email protected]>
Reviewed-by: York Sun <[email protected]>
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DPMAC represents physical line on the board. This physical
line eventually asscociate with on-board PHY.
So Add an api to return linked PHY ID of DPMAC object.
Signed-off-by: Prabhakar Kushwaha <[email protected]>
Reviewed-by: York Sun <[email protected]>
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DPMAC object of Management complex controls Physical MAC and MDIO controller.
It provides APIs for MDIO and link state updates. It also provides APIs for
PHY/link configuration.
Signed-off-by: Prabhakar Kushwaha <[email protected]>
Reviewed-by: York Sun <[email protected]>
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Current Management Complex Flibs does not support APIs for adding and
destroying the objects.
Add APIs to create and destroy objects for DPBP, DPIO, DPNI and DPRC.
Signed-off-by: Prabhakar Kushwaha <[email protected]>
Reviewed-by: York Sun <[email protected]>
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Remove fsloadcmd / ext2load as we are using load command
which use the corresponding latest file system command.
Signed-off-by: Chin Liang See <[email protected]>
Cc: Dinh Nguyen <[email protected]>
Cc: Dinh Nguyen <[email protected]>
Cc: Pavel Machek <[email protected]>
Cc: Marek Vasut <[email protected]>
Cc: Stefan Roese <[email protected]>
Reviewed-by: Stefan Roese <[email protected]>
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socfpga_dw_mmc driver will obtain the drvsel and
smplsel value from device tree instead of definition
in config header file.
Signed-off-by: Chin Liang See <[email protected]>
Cc: Dinh Nguyen <[email protected]>
Cc: Dinh Nguyen <[email protected]>
Cc: Pavel Machek <[email protected]>
Cc: Marek Vasut <[email protected]>
Cc: Stefan Roese <[email protected]>
Cc: Pantelis Antoniou <[email protected]>
Cc: Simon Glass <[email protected]>
Cc: Jaehoon Chung <[email protected]>
Acked-by: Marek Vasut <[email protected]>
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This board was constantly parasiting on the CV SoCDK, so split it
into it's own separate directory. Moreover, the board config was
missing important bits, like simple-bus support in SPL, the DRAM
configuration was incorrect and the DTS was also missing the pre
reloc bits.
Signed-off-by: Marek Vasut <[email protected]>
Cc: Stefan Roese <[email protected]>
Cc: Dinh Nguyen <[email protected]>
Cc: Dinh Nguyen <[email protected]>
Cc: Jan Viktorin <[email protected]>
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When adding support for the Arria10 platform, we're going to name the file
base_addr_a10.h, so to be systematic about it, rename the socfpga_base_addr.h
to be base_addr_ac5.h for the Arria5 and Cyclone5 platform.
Suggested-by: Marek Vasut <[email protected]>
Signed-off-by: Dinh Nguyen <[email protected]>
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Give default CONFIG_SYS_MAX_FLASH_SECT in flash.h, so that
the header can be included regardless of the present of flash.
The value 512 is the most used.
Signed-off-by: Thomas Chou <[email protected]>
Signed-off-by: Stefan Roese <[email protected]>
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This patch add ZyXEL NSA310S 1-Bay Media Server
The ZyXEL NSA310S device is a Kirkwood based NAS:
- SoC: Marvell 88F6702 1000Mhz
- SDRAM memory: 256MB DDR2 400Mhz
- Gigabit ethernet: PHY Marvell 88E1318
- Flash memory: 128MB
- 1 Power button
- 1 Power LED (blue)
- 4 Status LED (green)
- 1 Copy/Sync button
- 1 Reset button
- 1 SATA II port
- 2 USB 2.0 ports (front and back)
- Smart fan
Signed-off-by: Gerald Kerma <[email protected]>
Signed-off-by: Tony Dinh <[email protected]>
Signed-off-by: Luka Perkov <[email protected]>
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Use the correct function name in the function description.
Signed-off-by: Stefan Roese <[email protected]>
Reviewed-by: Simon Glass <[email protected]>
Cc: Heiko Schocher <[email protected]>
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There are already Kconfig options for SPI flash drivers, but we
have not moved them from config.h to defconfig files. This commit
does this in a batch.
Signed-off-by: Bin Meng <[email protected]>
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There are already Kconfig options for SPI drivers, but we
have not moved them from config.h to defconfig files. This
commit does this in a batch.
Signed-off-by: Bin Meng <[email protected]>
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