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Commit 12cc54376768461533b55ada1b0b6d4979f40579 'omap3: overo: Select
fdtfile for expansion board' wrongly missed the operator in the fdtfile
test. Update the test to only overwrite an empty fdtfile environment
variable.
Signed-off-by: Stefan Herbrechtsmeier <[email protected]>
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SCIF of koelsch use external clock mode.
This enables external clock mode on koelsch board.
Signed-off-by: Nobuhiro Iwamatsu <[email protected]>
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SCIF of lager use external clock mode.
This enables external clock mode on lager board.
Signed-off-by: Nobuhiro Iwamatsu <[email protected]>
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The clock of SCIF (serial port) of lager is supplied from External
Clock. And value of clock is 14.7456MHz.
Signed-off-by: Nobuhiro Iwamatsu <[email protected]>
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The single file conflict below is actually trivial.
Conflicts:
board/boundary/nitrogen6x/nitrogen6x.c
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Enable this feature to support driver model before relocation.
Signed-off-by: Simon Glass <[email protected]>
Signed-off-by: Minkyu Kang <[email protected]>
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Change this board to add a device tree.
Signed-off-by: Simon Glass <[email protected]>
Signed-off-by: Minkyu Kang <[email protected]>
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Change this board to add a device tree.
This also adds a pinmux header file although it is not used as yet.
Signed-off-by: Simon Glass <[email protected]>
Signed-off-by: Minkyu Kang <[email protected]>
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Most of the smdkv310 features are common with other exynos4 boards. To
permit easier addition of driver model support, use the common file and
add a device tree file.
Signed-off-by: Simon Glass <[email protected]>
Signed-off-by: Minkyu Kang <[email protected]>
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Most of the arndale features are common with other exynos5250 boards. To
permit easier addition of driver model support, use the common file.
Signed-off-by: Simon Glass <[email protected]>
Signed-off-by: Minkyu Kang <[email protected]>
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These boards do not in fact have a Chrome OS EC, nor a TPS565090 PMIC, so
move the settings into a separate common file to be used by those that need
it.
Signed-off-by: Simon Glass <[email protected]>
Signed-off-by: Minkyu Kang <[email protected]>
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A few things are common but are not in the common file. Fix this and
rename the file to fit with the other exynos*-common files.
Signed-off-by: Simon Glass <[email protected]>
Signed-off-by: Minkyu Kang <[email protected]>
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Since exynos4 and exyno5 share many settings, we should move these into
a common file to avoid duplication.
In effect the changes are that all exynos boards now have EXT4 and FAT
write support. This affects exynos5250 and exynos5420 which previously
did not. This also disables the ext2 commands which are equivalent to
ext4 anyway.
Signed-off-by: Simon Glass <[email protected]>
Signed-off-by: Minkyu Kang <[email protected]>
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We want exynos5250-dt.h to be a board which can support any exynos5250
device. This matches the naming used by Linux. As a first step, rename
the existing -dt files to -common to make it clear they are common files,
and not specific boards.
Signed-off-by: Simon Glass <[email protected]>
Signed-off-by: Minkyu Kang <[email protected]>
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With the driver model conversion we are going to be using driver model for
SPI and not for I2C. This works OK so long as a board doesn't need both
dm and non-dm versions of the cros_ec driver. Since pit uses SPI and snow
uses I2C we need to split the configs so that only one driver is compiled
for each platform.
We can fix this later when driver model supports I2C.
Signed-off-by: Simon Glass <[email protected]>
Signed-off-by: Minkyu Kang <[email protected]>
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Exynos 5250 boards (snow, spring) use the I2C driver but Exynos 5420 boards
cannot due to a hardware design decision. Select the correct driver to use
in each case.
Signed-off-by: Simon Glass <[email protected]>
Tested-by: Ajay Kumar <[email protected]>
Signed-off-by: Minkyu Kang <[email protected]>
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Things run faster when the data cache is enabled, so turn it on along with
the 'dcache' command.
Signed-off-by: Simon Glass <[email protected]>
Tested-by: Ajay Kumar <[email protected]>
Signed-off-by: Minkyu Kang <[email protected]>
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Support reading/writing ext4 partitions.
Signed-off-by: Kevin Mihelich <[email protected]>
Signed-off-by: Eric Nelson <[email protected]>
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Enable 'fastboot' command.
This is currently enabled but not yet functional. Including it in the
configuration will ease further testing and development as discussed
on the mailing list.
Signed-off-by: Eric Nelson <[email protected]>
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Enable the 'gpio' command to allow reading and toggling of GPIO
pins.
Signed-off-by: Eric Nelson <[email protected]>
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Some users (QNX and Windows CE users in particular) have asked
to disable the Penguin shown on the display at boot time.
Signed-off-by: Eric Nelson <[email protected]>
Acked-by: Stefano Babic <[email protected]>
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Increase the maximum number of arguments allowed by the Hush parser.
This prevents errors when users or scripts aren't quoting parameters
when setting the "bootargs" variable et al.
Signed-off-by: Troy Kisky <[email protected]>
Signed-off-by: Eric Nelson <[email protected]>
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Enable the "i2c edid" command to query data from an attached
HDMI monitor.
Usage is typically this:
U-Boot > i2c dev 1
U-Boot > i2c edid 0x50
...
Signed-off-by: Eric Nelson <[email protected]>
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Enable the 'mtest' command on Nitrogen6x and SABRE Lite boards.
Signed-off-by: Eric Nelson <[email protected]>
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Enable the use of USB keyboards on SABRE Lite and Nitrogen6x boards.
Signed-off-by: Eric Nelson <[email protected]>
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If no boot script was found, expose internal storage over the
USB mass storage gadget to allow easy programming.
This is especially useful when SD cards are inaccessible or when
loading SATA drives.
More details are available in this blog post:
http://boundarydevices.com/u-boot-usb-mass-storage-gadget/
Signed-off-by: Eric Nelson <[email protected]>
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Support RAM disks by setting initrd_high. See commit 7e9603e
Signed-off-by: Eric Nelson <[email protected]>
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Remove the individual attempts to load using ext2 and fat, replace with the
generic load command supporting available filesystem types.
Signed-off-by: Kevin Mihelich <[email protected]>
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This patch enables boot to USB storage devices by expanding on the list
of boot devices.
Because the USB startup currently takes a long time, it places USB at
the end of the list of supported devices.
You can over-ride the boot order using the bootdevs environment variable.
For instance, this will make USB the first (highest priority) device:
U-Boot > setenv bootdevs usb mmc sata
U-Boot > saveenv
Signed-off-by: Diego Rondini <[email protected]>
Signed-off-by: Eric Nelson <[email protected]>
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Add support for the USB mass storage to enable access to on-board
storage (especially eMMC and SATA).
Details at:
http://boundarydevices.com/u-boot-usb-mass-storage-gadget/
Signed-off-by: Eric Nelson <[email protected]>
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Enable and use the CONFIG_CMD_FS_GENERIC to avoid hard-coding the
filesystem type into the environment.
Signed-off-by: Marek Vasut <[email protected]>
Cc: Chin Liang See <[email protected]>
Cc: Dinh Nguyen <[email protected]>
Cc: Albert Aribaud <[email protected]>
Cc: Tom Rini <[email protected]>
Cc: Wolfgang Denk <[email protected]>
Cc: Pavel Machek <[email protected]>
Acked-by: Pavel Machek <[email protected]>
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Split the SoCFPGA configuration into SoC-specific part which is
common for all boards (socfpga_cyclone5_common.h) and a board
specific part. There is currently only one board, which is the
generic SoCFPGA board (socfpga_cyclone5.h), but there are more
to come.
This is necessary due to various features of the boards, which
unfortunatelly cannot be autodetected.
Signed-off-by: Marek Vasut <[email protected]>
Cc: Chin Liang See <[email protected]>
Cc: Dinh Nguyen <[email protected]>
Cc: Albert Aribaud <[email protected]>
Cc: Tom Rini <[email protected]>
Cc: Wolfgang Denk <[email protected]>
Cc: Pavel Machek <[email protected]>
Acked-by: Pavel Machek <[email protected]>
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Reorganize and cleanup the configuration file for SoCFPGA. There
is no functional change after this cleanup. This was necessary,
since the file was a wild mess and it was impossible to make sense
of it's content, let alone change something without breaking some
other thing. This patch puts the contents on par with regular U-Boot
standards.
Also remove unused preprocessor symbols CONFIG_SINGLE_BOOTOADER
and CONFIG_USE_IRQ, which is undefined by default. Finally, do
logical reordering of the defines in the file so it's much more
readable. The reordering was also necessary for the splitting
as the initial one was messy.
Signed-off-by: Marek Vasut <[email protected]>
Cc: Chin Liang See <[email protected]>
Cc: Dinh Nguyen <[email protected]>
Cc: Albert Aribaud <[email protected]>
Cc: Tom Rini <[email protected]>
Cc: Wolfgang Denk <[email protected]>
Cc: Pavel Machek <[email protected]>
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Enable the SDMMC boot as default boot for SOCFPGA U-Boot dev kit.
Enable the bootz command as zImage is used instead uImage.
Signed-off-by: Chin Liang See <[email protected]>
Signed-off-by: Marek Vasut <[email protected]>
Cc: Dinh Nguyen <[email protected]>
Cc: Pavel Machek <[email protected]>
Cc: Marek Vasut <[email protected]>
Cc: Tom Rini <[email protected]>
Cc: Albert Aribaud <[email protected]>
Cc: Wolfgang Denk <[email protected]>
Acked-by: Pavel Machek <[email protected]>
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Enable the DesignWare MMC controller driver support
for SOCFPGA Cyclone5 dev kit
Signed-off-by: Chin Liang See <[email protected]>
Signed-off-by: Marek Vasut <[email protected]>
Cc: Dinh Nguyen <[email protected]>
Cc: Pavel Machek <[email protected]>
Cc: Marek Vasut <[email protected]>
Cc: Tom Rini <[email protected]>
Cc: Albert Aribaud <[email protected]>
Cc: Wolfgang Denk <[email protected]>
Acked-by: Pavel Machek <[email protected]>
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Enable the PL310 L2 cache controller support for the SoCFPGA.
With the cache related issues resolved, this is safe to be done.
Signed-off-by: Marek Vasut <[email protected]>
Cc: Chin Liang See <[email protected]>
Cc: Dinh Nguyen <[email protected]>
Cc: Albert Aribaud <[email protected]>
Cc: Tom Rini <[email protected]>
Cc: Wolfgang Denk <[email protected]>
Cc: Pavel Machek <[email protected]>
Acked-by: Pavel Machek <[email protected]>
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The code is now fixed to the point where we can safely enable
the L1 data cache. Enable the D-Cache and set it as write-alloc.
Signed-off-by: Marek Vasut <[email protected]>
Cc: Chin Liang See <[email protected]>
Cc: Dinh Nguyen <[email protected]>
Cc: Albert Aribaud <[email protected]>
Cc: Tom Rini <[email protected]>
Cc: Wolfgang Denk <[email protected]>
Cc: Pavel Machek <[email protected]>
Acked-by: Pavel Machek <[email protected]>
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The Cortex-A9 has 32-byte long L1 cachelines. Define this value.
Signed-off-by: Marek Vasut <[email protected]>
Cc: Chin Liang See <[email protected]>
Cc: Dinh Nguyen <[email protected]>
Cc: Albert Aribaud <[email protected]>
Cc: Tom Rini <[email protected]>
Cc: Wolfgang Denk <[email protected]>
Cc: Pavel Machek <[email protected]>
Acked-by: Pavel Machek <[email protected]>
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Add code necessary to program the FPGA part of SoCFPGA from U-Boot
with an RBF blob. This patch also integrates the code into the
FPGA driver framework in U-Boot so it can be used via the 'fpga'
command.
Signed-off-by: Pavel Machek <[email protected]>
Signed-off-by: Marek Vasut <[email protected]>
Cc: Chin Liang See <[email protected]>
Cc: Dinh Nguyen <[email protected]>
Cc: Albert Aribaud <[email protected]>
Cc: Tom Rini <[email protected]>
Cc: Wolfgang Denk <[email protected]>
Cc: Pavel Machek <[email protected]>
V2: Move the not-CPU specific stuff into drivers/fpga/ and base
this on the cleaned up altera FPGA support.
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The timer reload value is a property of the timer hardware and there
is no reason for this to be configurable. Place this into the timer
driver just like on the other hardware.
Signed-off-by: Marek Vasut <[email protected]>
Cc: Chin Liang See <[email protected]>
Cc: Dinh Nguyen <[email protected]>
Cc: Albert Aribaud <[email protected]>
Cc: Tom Rini <[email protected]>
Cc: Wolfgang Denk <[email protected]>
Cc: Pavel Machek <[email protected]>
Acked-by: Dinh Nguyen <[email protected]>
Acked-by: Pavel Machek <[email protected]>
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Add the entire bulk of code to read out clock configuration from the SoCFPGA
CPU registers. This is important for MMC, QSPI and UART drivers as otherwise
they cannot determine the frequency of their upstream clock.
Signed-off-by: Pavel Machek <[email protected]>
Signed-off-by: Marek Vasut <[email protected]>
Cc: Chin Liang See <[email protected]>
Cc: Dinh Nguyen <[email protected]>
Cc: Albert Aribaud <[email protected]>
Cc: Tom Rini <[email protected]>
Cc: Wolfgang Denk <[email protected]>
Cc: Pavel Machek <[email protected]>
V2: Fixed the L4 MP clock divider and synced the clock code with latest
rocketboards codebase (thanks Dinh for pointing this out)
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'topic/drivers/net-20141006', 'topic/tools/mkimage-20141006' and 'topic/arm/cache-20141006' into HEAD
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Like many platforms, the Altera socfpga platform requires that the
preloader be "signed" in a certain way or the built-in boot ROM will
not boot the code.
This change automatically creates an appropriately signed preloader
from an SPL image.
The signed image includes a CRC which must, of course, be generated
with a CRC generator that the SoCFPGA boot ROM agrees with otherwise
the boot ROM will reject the image.
Unfortunately the CRC used in this boot ROM is not the same as the
Adler CRC in lib/crc32.c. Indeed the Adler code is not technically a
CRC but is more correctly described as a checksum.
Thus, the appropriate CRC generator is added to lib/ as crc32_alt.c.
Signed-off-by: Charles Manning <[email protected]>
Signed-off-by: Marek Vasut <[email protected]>
Cc: Chin Liang See <[email protected]>
Cc: Dinh Nguyen <[email protected]>
Cc: Albert Aribaud <[email protected]>
Cc: Tom Rini <[email protected]>
Cc: Wolfgang Denk <[email protected]>
Cc: Pavel Machek <[email protected]>
Acked-by: Pavel Machek <[email protected]>
V2: - Zap unused constant
- Explicitly print an error message in case of error
- Rework the hdr_checksum() function to take the *header directly
instead of a plan buffer pointer
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Remove this symbol from configs, since it's unused.
Signed-off-by: Pavel Machek <[email protected]>
Signed-off-by: Marek Vasut <[email protected]>
Cc: Chin Liang See <[email protected]>
Cc: Dinh Nguyen <[email protected]>
Cc: Albert Aribaud <[email protected]>
Cc: Tom Rini <[email protected]>
Cc: Wolfgang Denk <[email protected]>
Cc: Pavel Machek <[email protected]>
Cc: Joe Hershberger <[email protected]>
Acked-by: Chin Liang See <[email protected]>
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The DMA descriptors used by the DW MMC block must be aligned to cacheline
size, otherwise we are unable to properly flush/inval cache over them and
we get data corruption.
The reason I chose this approach of expanding the structure is because
the driver allocates the descriptors in bulk. This approach does waste
space by inserting slop inbetween the descriptors, but it makes access
to the descriptors easy as the compiler does know the real size of the
structure. It also makes cache operations easy, since the size of the
structure is cache aligned and the structure start address is as well.
Signed-off-by: Marek Vasut <[email protected]>
Cc: Chin Liang See <[email protected]>
Cc: Dinh Nguyen <[email protected]>
Cc: Albert Aribaud <[email protected]>
Cc: Tom Rini <[email protected]>
Cc: Wolfgang Denk <[email protected]>
Cc: Pavel Machek <[email protected]>
Cc: Pantelis Antoniou <[email protected]>
Acked-by: Pavel Machek <[email protected]>
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Get rid of the line-over-80 problems and zap the typedef that
went alongside those enums.
Signed-off-by: Marek Vasut <[email protected]>
Cc: Chin Liang See <[email protected]>
Cc: Dinh Nguyen <[email protected]>
Cc: Albert Aribaud <[email protected]>
Cc: Tom Rini <[email protected]>
Cc: Wolfgang Denk <[email protected]>
Cc: Pavel Machek <[email protected]>
Acked-by: Pavel Machek <[email protected]>
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