From 14bb9c27b7c65a5804e0f2c0d92723b6af500d47 Mon Sep 17 00:00:00 2001 From: Eugen Hristev Date: Tue, 25 Apr 2023 16:06:59 +0300 Subject: configs: rock5b-rk3588: add rtl8169 driver Add the rtl8169 driver, which supports the rtl8125b device, which is connected on the pciE bus on this board. Enable also CONFIG_SYS_HAS_NONCACHED_MEMORY to have the descriptors stored. Signed-off-by: Eugen Hristev Reviewed-by: Kever Yang --- configs/rock5b-rk3588_defconfig | 2 ++ 1 file changed, 2 insertions(+) diff --git a/configs/rock5b-rk3588_defconfig b/configs/rock5b-rk3588_defconfig index 17205a56cd9..85cb70bd091 100644 --- a/configs/rock5b-rk3588_defconfig +++ b/configs/rock5b-rk3588_defconfig @@ -1,5 +1,6 @@ CONFIG_ARM=y CONFIG_SKIP_LOWLEVEL_INIT=y +CONFIG_SYS_HAS_NONCACHED_MEMORY=y CONFIG_COUNTER_FREQUENCY=24000000 CONFIG_ARCH_ROCKCHIP=y CONFIG_TEXT_BASE=0x00a00000 @@ -71,6 +72,7 @@ CONFIG_MMC_SDHCI_ROCKCHIP=y CONFIG_SPI_FLASH_MACRONIX=y CONFIG_SPI_FLASH_XTX=y CONFIG_ETH_DESIGNWARE=y +CONFIG_RTL8169=y CONFIG_GMAC_ROCKCHIP=y CONFIG_PCIE_DW_ROCKCHIP=y CONFIG_PHY_ROCKCHIP_INNO_USB2=y -- cgit v1.3.1 From 3c057b4c6c38aa60fcb1fceb46bcc441a8065116 Mon Sep 17 00:00:00 2001 From: Chris Morgan Date: Wed, 10 May 2023 10:55:50 -0500 Subject: rockchip: board: Update Odroid Go2 to Support Additional Revisions Update the board.c file for the Odroid Go Advance to support the Black Edition and the Odroid Go Super. The Odroid Go Advance Black Edition differs from the original model with the addition of 2 extra buttons and an ESP8266 WiFi module. The Odroid Go Super adds an additional 2 buttons compared to the Black Edition, along with a larger panel and larger battery. This change uses the value of ADC0 to determine which of these 3 models it is, and then changes the ${fdtfile} environment variable to match the proper devicetree name in mainline Linux. Tested on an Odroid Go Advance (first revision) and an Odroid Go Super. The correct ${fdtfile} variable was set for each device. Signed-off-by: Chris Morgan Reviewed-by: Kever Yang --- board/hardkernel/odroid_go2/go2.c | 103 ++++++++++++++++++++++++++++++++++++++ configs/odroid-go2_defconfig | 1 + 2 files changed, 104 insertions(+) diff --git a/board/hardkernel/odroid_go2/go2.c b/board/hardkernel/odroid_go2/go2.c index 29464ae63ec..a0338ead3b5 100644 --- a/board/hardkernel/odroid_go2/go2.c +++ b/board/hardkernel/odroid_go2/go2.c @@ -2,3 +2,106 @@ /* * (C) Copyright 2019 Rockchip Electronics Co., Ltd */ + +#include +#include +#include +#include +#include +#include + +#define DTB_DIR "rockchip/" + +struct oga_model { + const u16 adc_value; + const char *board; + const char *board_name; + const char *fdtfile; +}; + +enum oga_device_id { + OGA, + OGA_V11, + OGS, +}; + +/* + * All ADC values from schematic of Odroid Go Advance Black Edition. + * Value for OGS is inferred based on schematic and observed values. + */ +static const struct oga_model oga_model_details[] = { + [OGA] = { + 856, + "rk3326-odroid-go2", + "ODROID-GO Advance", + DTB_DIR "rk3326-odroid-go2.dtb", + }, + [OGA_V11] = { + 677, + "rk3326-odroid-go2-v11", + "ODROID-GO Advance Black Edition", + DTB_DIR "rk3326-odroid-go2-v11.dtb", + }, + [OGS] = { + 85, + "rk3326-odroid-go3", + "ODROID-GO Super", + DTB_DIR "rk3326-odroid-go3.dtb", + }, +}; + +/* Detect which Odroid Go Advance device we are using so as to load the + * correct devicetree for Linux. Set an environment variable once + * found. The detection depends on the value of ADC channel 0. + */ +int oga_detect_device(void) +{ + u32 adc_info; + int ret, i; + int board_id = -ENXIO; + + ret = adc_channel_single_shot("saradc@ff288000", 0, &adc_info); + if (ret) { + printf("Read SARADC failed with error %d\n", ret); + return ret; + } + + /* + * Get the correct device from the table. The ADC value is + * determined by a resistor on ADC channel 0. The manufacturer + * accounted for this with a 5% tolerance, so assume a +- value + * of 50 should be enough. + */ + for (i = 0; i < ARRAY_SIZE(oga_model_details); i++) { + u32 adc_min = oga_model_details[i].adc_value - 50; + u32 adc_max = oga_model_details[i].adc_value + 50; + + if (adc_min < adc_info && adc_max > adc_info) { + board_id = i; + break; + } + } + + if (board_id < 0) + return board_id; + + env_set("board", oga_model_details[board_id].board); + env_set("board_name", + oga_model_details[board_id].board_name); + env_set("fdtfile", oga_model_details[board_id].fdtfile); + + return 0; +} + +int rk_board_late_init(void) +{ + int ret; + + ret = oga_detect_device(); + if (ret) { + printf("Unable to detect device type: %d\n", ret); + return ret; + } + + return 0; +} diff --git a/configs/odroid-go2_defconfig b/configs/odroid-go2_defconfig index 459ae3d59c6..bdc2288af66 100644 --- a/configs/odroid-go2_defconfig +++ b/configs/odroid-go2_defconfig @@ -35,6 +35,7 @@ CONFIG_DEFAULT_FDT_FILE="rockchip/rk3326-odroid-go2.dtb" # CONFIG_CONSOLE_MUX is not set # CONFIG_DISPLAY_CPUINFO is not set CONFIG_DISPLAY_BOARDINFO_LATE=y +CONFIG_BOARD_LATE_INIT=y CONFIG_MISC_INIT_R=y CONFIG_SPL_MAX_SIZE=0x20000 CONFIG_SPL_PAD_TO=0x7f8000 -- cgit v1.3.1 From 0825522eeaa91685dd2491deb6a12893f9859d09 Mon Sep 17 00:00:00 2001 From: Ondrej Jirman Date: Thu, 25 May 2023 14:29:03 +0200 Subject: video: rockchip: Add support for RK3399 to dw-mipi-dsi bridge This just needs some extra clocks enabled, and different registers configured. Copied from Linux, just like the original submitter of this driver did for rk3568. Tested on Pinephone Pro. Signed-off-by: Ondrej Jirman Cc: Anatolij Gustschin Cc: Simon Glass Cc: Philipp Tomsich Cc: Kever Yang Cc: Chris Morgan Reviewed-by: Kever Yang --- drivers/video/rockchip/dw_mipi_dsi_rockchip.c | 99 +++++++++++++++++++++++++++ 1 file changed, 99 insertions(+) diff --git a/drivers/video/rockchip/dw_mipi_dsi_rockchip.c b/drivers/video/rockchip/dw_mipi_dsi_rockchip.c index 117c3db21ac..0852b53ebed 100644 --- a/drivers/video/rockchip/dw_mipi_dsi_rockchip.c +++ b/drivers/video/rockchip/dw_mipi_dsi_rockchip.c @@ -134,6 +134,32 @@ #define HS_RX_CONTROL_OF_LANE_2 0x84 #define HS_RX_CONTROL_OF_LANE_3 0x94 +#define DW_MIPI_NEEDS_PHY_CFG_CLK BIT(0) +#define DW_MIPI_NEEDS_GRF_CLK BIT(1) + +#define RK3399_GRF_SOC_CON20 0x6250 +#define RK3399_DSI0_LCDC_SEL BIT(0) +#define RK3399_DSI1_LCDC_SEL BIT(4) + +#define RK3399_GRF_SOC_CON22 0x6258 +#define RK3399_DSI0_TURNREQUEST (0xf << 12) +#define RK3399_DSI0_TURNDISABLE (0xf << 8) +#define RK3399_DSI0_FORCETXSTOPMODE (0xf << 4) +#define RK3399_DSI0_FORCERXMODE (0xf << 0) + +#define RK3399_GRF_SOC_CON23 0x625c +#define RK3399_DSI1_TURNDISABLE (0xf << 12) +#define RK3399_DSI1_FORCETXSTOPMODE (0xf << 8) +#define RK3399_DSI1_FORCERXMODE (0xf << 4) +#define RK3399_DSI1_ENABLE (0xf << 0) + +#define RK3399_GRF_SOC_CON24 0x6260 +#define RK3399_TXRX_MASTERSLAVEZ BIT(7) +#define RK3399_TXRX_ENABLECLK BIT(6) +#define RK3399_TXRX_BASEDIR BIT(5) +#define RK3399_TXRX_SRC_SEL_ISP0 BIT(4) +#define RK3399_TXRX_TURNREQUEST GENMASK(3, 0) + #define RK3568_GRF_VO_CON2 0x0368 #define RK3568_DSI0_SKEWCALHS (0x1f << 11) #define RK3568_DSI0_FORCETXSTOPMODE (0xf << 4) @@ -209,6 +235,8 @@ struct dw_rockchip_dsi_priv { struct clk *pclk; struct clk *ref; + struct clk *grf_clk; + struct clk *phy_cfg_clk; struct reset_ctl *rst; unsigned int lane_mbps; /* per lane */ u16 input_div; @@ -844,6 +872,28 @@ static int dw_mipi_dsi_rockchip_probe(struct udevice *dev) } } + if (cdata->flags & DW_MIPI_NEEDS_PHY_CFG_CLK) { + priv->phy_cfg_clk = devm_clk_get(dev, "phy_cfg"); + if (IS_ERR(priv->phy_cfg_clk)) { + ret = PTR_ERR(priv->phy_cfg_clk); + dev_err(dev, "phy_cfg_clk clock get error %d\n", ret); + return ret; + } + + clk_enable(priv->phy_cfg_clk); + } + + if (cdata->flags & DW_MIPI_NEEDS_GRF_CLK) { + priv->grf_clk = devm_clk_get(dev, "grf"); + if (IS_ERR(priv->grf_clk)) { + ret = PTR_ERR(priv->grf_clk); + dev_err(dev, "grf_clk clock get error %d\n", ret); + return ret; + } + + clk_enable(priv->grf_clk); + } + priv->rst = devm_reset_control_get_by_index(device->dev, 0); if (IS_ERR(priv->rst)) { ret = PTR_ERR(priv->rst); @@ -864,6 +914,52 @@ struct video_bridge_ops dw_mipi_dsi_rockchip_ops = { .set_backlight = dw_mipi_dsi_rockchip_set_bl, }; +static const struct rockchip_dw_dsi_chip_data rk3399_chip_data[] = { + { + .reg = 0xff960000, + .lcdsel_grf_reg = RK3399_GRF_SOC_CON20, + .lcdsel_big = HIWORD_UPDATE(0, RK3399_DSI0_LCDC_SEL), + .lcdsel_lit = HIWORD_UPDATE(RK3399_DSI0_LCDC_SEL, + RK3399_DSI0_LCDC_SEL), + + .lanecfg1_grf_reg = RK3399_GRF_SOC_CON22, + .lanecfg1 = HIWORD_UPDATE(0, RK3399_DSI0_TURNREQUEST | + RK3399_DSI0_TURNDISABLE | + RK3399_DSI0_FORCETXSTOPMODE | + RK3399_DSI0_FORCERXMODE), + + .flags = DW_MIPI_NEEDS_PHY_CFG_CLK | DW_MIPI_NEEDS_GRF_CLK, + .max_data_lanes = 4, + }, + { + .reg = 0xff968000, + .lcdsel_grf_reg = RK3399_GRF_SOC_CON20, + .lcdsel_big = HIWORD_UPDATE(0, RK3399_DSI1_LCDC_SEL), + .lcdsel_lit = HIWORD_UPDATE(RK3399_DSI1_LCDC_SEL, + RK3399_DSI1_LCDC_SEL), + + .lanecfg1_grf_reg = RK3399_GRF_SOC_CON23, + .lanecfg1 = HIWORD_UPDATE(0, RK3399_DSI1_TURNDISABLE | + RK3399_DSI1_FORCETXSTOPMODE | + RK3399_DSI1_FORCERXMODE | + RK3399_DSI1_ENABLE), + + .lanecfg2_grf_reg = RK3399_GRF_SOC_CON24, + .lanecfg2 = HIWORD_UPDATE(RK3399_TXRX_MASTERSLAVEZ | + RK3399_TXRX_ENABLECLK, + RK3399_TXRX_MASTERSLAVEZ | + RK3399_TXRX_ENABLECLK | + RK3399_TXRX_BASEDIR), + + .enable_grf_reg = RK3399_GRF_SOC_CON23, + .enable = HIWORD_UPDATE(RK3399_DSI1_ENABLE, RK3399_DSI1_ENABLE), + + .flags = DW_MIPI_NEEDS_PHY_CFG_CLK | DW_MIPI_NEEDS_GRF_CLK, + .max_data_lanes = 4, + }, + { /* sentinel */ } +}; + static const struct rockchip_dw_dsi_chip_data rk3568_chip_data[] = { { .reg = 0xfe060000, @@ -887,6 +983,9 @@ static const struct rockchip_dw_dsi_chip_data rk3568_chip_data[] = { }; static const struct udevice_id dw_mipi_dsi_rockchip_dt_ids[] = { + { .compatible = "rockchip,rk3399-mipi-dsi", + .data = (long)&rk3399_chip_data, + }, { .compatible = "rockchip,rk3568-mipi-dsi", .data = (long)&rk3568_chip_data, }, -- cgit v1.3.1 From 22a5a9724b892cd344da01c37434566170e33da5 Mon Sep 17 00:00:00 2001 From: Eugen Hristev Date: Mon, 29 May 2023 10:34:23 +0300 Subject: ARM: dts: rockchip: rk3588: sync with Linux Sync the devicetree with linux-next tag: next-20230525 Signed-off-by: Eugen Hristev Reviewed-by: Kever Yang --- arch/arm/dts/rk3588-rock-5b.dts | 152 +++++++++++++++++++++++++ arch/arm/dts/rk3588.dtsi | 68 ++++++++++++ arch/arm/dts/rk3588s-u-boot.dtsi | 12 -- arch/arm/dts/rk3588s.dtsi | 234 ++++++++++++++++++++++++++++++++++++++- 4 files changed, 449 insertions(+), 17 deletions(-) diff --git a/arch/arm/dts/rk3588-rock-5b.dts b/arch/arm/dts/rk3588-rock-5b.dts index 95805cb0adf..3e4aee8f70c 100644 --- a/arch/arm/dts/rk3588-rock-5b.dts +++ b/arch/arm/dts/rk3588-rock-5b.dts @@ -2,6 +2,7 @@ /dts-v1/; +#include #include "rk3588.dtsi" / { @@ -17,6 +18,31 @@ stdout-path = "serial2:1500000n8"; }; + fan: pwm-fan { + compatible = "pwm-fan"; + cooling-levels = <0 95 145 195 255>; + fan-supply = <&vcc5v0_sys>; + pwms = <&pwm1 0 50000 0>; + #cooling-cells = <2>; + }; + + sound { + compatible = "audio-graph-card"; + label = "Analog"; + + widgets = "Microphone", "Mic Jack", + "Headphone", "Headphones"; + + routing = "MIC2", "Mic Jack", + "Headphones", "HPOL", + "Headphones", "HPOR"; + + dais = <&i2s0_8ch_p0>; + hp-det-gpio = <&gpio1 RK_PD5 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&hp_detect>; + }; + vcc5v0_sys: vcc5v0-sys-regulator { compatible = "regulator-fixed"; regulator-name = "vcc5v0_sys"; @@ -27,6 +53,132 @@ }; }; +&cpu_b0 { + cpu-supply = <&vdd_cpu_big0_s0>; +}; + +&cpu_b1 { + cpu-supply = <&vdd_cpu_big0_s0>; +}; + +&cpu_b2 { + cpu-supply = <&vdd_cpu_big1_s0>; +}; + +&cpu_b3 { + cpu-supply = <&vdd_cpu_big1_s0>; +}; + +&i2c0 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c0m2_xfer>; + status = "okay"; + + vdd_cpu_big0_s0: regulator@42 { + compatible = "rockchip,rk8602"; + reg = <0x42>; + fcs,suspend-voltage-selector = <1>; + regulator-name = "vdd_cpu_big0_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <1050000>; + regulator-ramp-delay = <2300>; + vin-supply = <&vcc5v0_sys>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_cpu_big1_s0: regulator@43 { + compatible = "rockchip,rk8603", "rockchip,rk8602"; + reg = <0x43>; + fcs,suspend-voltage-selector = <1>; + regulator-name = "vdd_cpu_big1_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <1050000>; + regulator-ramp-delay = <2300>; + vin-supply = <&vcc5v0_sys>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; +}; + +&i2c6 { + status = "okay"; + + hym8563: rtc@51 { + compatible = "haoyu,hym8563"; + reg = <0x51>; + #clock-cells = <0>; + clock-output-names = "hym8563"; + pinctrl-names = "default"; + pinctrl-0 = <&hym8563_int>; + interrupt-parent = <&gpio0>; + interrupts = ; + wakeup-source; + }; +}; + +&i2c7 { + status = "okay"; + + es8316: audio-codec@11 { + compatible = "everest,es8316"; + reg = <0x11>; + clocks = <&cru I2S0_8CH_MCLKOUT>; + clock-names = "mclk"; + #sound-dai-cells = <0>; + + port { + es8316_p0_0: endpoint { + remote-endpoint = <&i2s0_8ch_p0_0>; + }; + }; + }; +}; + +&i2s0_8ch { + pinctrl-names = "default"; + pinctrl-0 = <&i2s0_lrck + &i2s0_mclk + &i2s0_sclk + &i2s0_sdi0 + &i2s0_sdo0>; + status = "okay"; + + i2s0_8ch_p0: port { + i2s0_8ch_p0_0: endpoint { + dai-format = "i2s"; + mclk-fs = <256>; + remote-endpoint = <&es8316_p0_0>; + }; + }; +}; + +&pinctrl { + hym8563 { + hym8563_int: hym8563-int { + rockchip,pins = <0 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + sound { + hp_detect: hp-detect { + rockchip,pins = <1 RK_PD5 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +}; + +&pwm1 { + status = "okay"; +}; + &sdhci { bus-width = <8>; no-sdio; diff --git a/arch/arm/dts/rk3588.dtsi b/arch/arm/dts/rk3588.dtsi index d085e57fbc4..8be75556af8 100644 --- a/arch/arm/dts/rk3588.dtsi +++ b/arch/arm/dts/rk3588.dtsi @@ -7,6 +7,74 @@ #include "rk3588-pinctrl.dtsi" / { + i2s8_8ch: i2s@fddc8000 { + compatible = "rockchip,rk3588-i2s-tdm"; + reg = <0x0 0xfddc8000 0x0 0x1000>; + interrupts = ; + clocks = <&cru MCLK_I2S8_8CH_TX>, <&cru MCLK_I2S8_8CH_TX>, <&cru HCLK_I2S8_8CH>; + clock-names = "mclk_tx", "mclk_rx", "hclk"; + assigned-clocks = <&cru CLK_I2S8_8CH_TX_SRC>; + assigned-clock-parents = <&cru PLL_AUPLL>; + dmas = <&dmac2 22>; + dma-names = "tx"; + power-domains = <&power RK3588_PD_VO0>; + resets = <&cru SRST_M_I2S8_8CH_TX>; + reset-names = "tx-m"; + #sound-dai-cells = <0>; + status = "disabled"; + }; + + i2s6_8ch: i2s@fddf4000 { + compatible = "rockchip,rk3588-i2s-tdm"; + reg = <0x0 0xfddf4000 0x0 0x1000>; + interrupts = ; + clocks = <&cru MCLK_I2S6_8CH_TX>, <&cru MCLK_I2S6_8CH_TX>, <&cru HCLK_I2S6_8CH>; + clock-names = "mclk_tx", "mclk_rx", "hclk"; + assigned-clocks = <&cru CLK_I2S6_8CH_TX_SRC>; + assigned-clock-parents = <&cru PLL_AUPLL>; + dmas = <&dmac2 4>; + dma-names = "tx"; + power-domains = <&power RK3588_PD_VO1>; + resets = <&cru SRST_M_I2S6_8CH_TX>; + reset-names = "tx-m"; + #sound-dai-cells = <0>; + status = "disabled"; + }; + + i2s7_8ch: i2s@fddf8000 { + compatible = "rockchip,rk3588-i2s-tdm"; + reg = <0x0 0xfddf8000 0x0 0x1000>; + interrupts = ; + clocks = <&cru MCLK_I2S7_8CH_RX>, <&cru MCLK_I2S7_8CH_RX>, <&cru HCLK_I2S7_8CH>; + clock-names = "mclk_tx", "mclk_rx", "hclk"; + assigned-clocks = <&cru CLK_I2S7_8CH_RX_SRC>; + assigned-clock-parents = <&cru PLL_AUPLL>; + dmas = <&dmac2 21>; + dma-names = "rx"; + power-domains = <&power RK3588_PD_VO1>; + resets = <&cru SRST_M_I2S7_8CH_RX>; + reset-names = "rx-m"; + #sound-dai-cells = <0>; + status = "disabled"; + }; + + i2s10_8ch: i2s@fde00000 { + compatible = "rockchip,rk3588-i2s-tdm"; + reg = <0x0 0xfde00000 0x0 0x1000>; + interrupts = ; + clocks = <&cru MCLK_I2S10_8CH_RX>, <&cru MCLK_I2S10_8CH_RX>, <&cru HCLK_I2S10_8CH>; + clock-names = "mclk_tx", "mclk_rx", "hclk"; + assigned-clocks = <&cru CLK_I2S10_8CH_RX_SRC>; + assigned-clock-parents = <&cru PLL_AUPLL>; + dmas = <&dmac2 24>; + dma-names = "rx"; + power-domains = <&power RK3588_PD_VO1>; + resets = <&cru SRST_M_I2S10_8CH_RX>; + reset-names = "rx-m"; + #sound-dai-cells = <0>; + status = "disabled"; + }; + gmac0: ethernet@fe1b0000 { compatible = "rockchip,rk3588-gmac", "snps,dwmac-4.20a"; reg = <0x0 0xfe1b0000 0x0 0x10000>; diff --git a/arch/arm/dts/rk3588s-u-boot.dtsi b/arch/arm/dts/rk3588s-u-boot.dtsi index c703e41802b..1bb3c6a9d95 100644 --- a/arch/arm/dts/rk3588s-u-boot.dtsi +++ b/arch/arm/dts/rk3588s-u-boot.dtsi @@ -174,18 +174,6 @@ status = "disabled"; }; - otp: nvmem@fecc0000 { - compatible = "rockchip,rk3588-otp"; - reg = <0x0 0xfecc0000 0x0 0x400>; - #address-cells = <1>; - #size-cells = <1>; - status = "okay"; - - cpu_id: id@7 { - reg = <0x07 0x10>; - }; - }; - rng: rng@fe378000 { compatible = "rockchip,trngv1"; reg = <0x0 0xfe378000 0x0 0x200>; diff --git a/arch/arm/dts/rk3588s.dtsi b/arch/arm/dts/rk3588s.dtsi index fca8503aed8..7dbac9ae2e1 100644 --- a/arch/arm/dts/rk3588s.dtsi +++ b/arch/arm/dts/rk3588s.dtsi @@ -60,6 +60,8 @@ enable-method = "psci"; capacity-dmips-mhz = <530>; clocks = <&scmi_clk SCMI_CLK_CPUL>; + assigned-clocks = <&scmi_clk SCMI_CLK_CPUL>; + assigned-clock-rates = <816000000>; cpu-idle-states = <&CPU_SLEEP>; i-cache-size = <32768>; i-cache-line-size = <64>; @@ -136,6 +138,8 @@ enable-method = "psci"; capacity-dmips-mhz = <1024>; clocks = <&scmi_clk SCMI_CLK_CPUB01>; + assigned-clocks = <&scmi_clk SCMI_CLK_CPUB01>; + assigned-clock-rates = <816000000>; cpu-idle-states = <&CPU_SLEEP>; i-cache-size = <65536>; i-cache-line-size = <64>; @@ -174,6 +178,8 @@ enable-method = "psci"; capacity-dmips-mhz = <1024>; clocks = <&scmi_clk SCMI_CLK_CPUB23>; + assigned-clocks = <&scmi_clk SCMI_CLK_CPUB23>; + assigned-clock-rates = <816000000>; cpu-idle-states = <&CPU_SLEEP>; i-cache-size = <65536>; i-cache-line-size = <64>; @@ -222,6 +228,8 @@ cache-size = <131072>; cache-line-size = <64>; cache-sets = <512>; + cache-level = <2>; + cache-unified; next-level-cache = <&l3_cache>; }; @@ -230,6 +238,8 @@ cache-size = <131072>; cache-line-size = <64>; cache-sets = <512>; + cache-level = <2>; + cache-unified; next-level-cache = <&l3_cache>; }; @@ -238,6 +248,8 @@ cache-size = <131072>; cache-line-size = <64>; cache-sets = <512>; + cache-level = <2>; + cache-unified; next-level-cache = <&l3_cache>; }; @@ -246,6 +258,8 @@ cache-size = <131072>; cache-line-size = <64>; cache-sets = <512>; + cache-level = <2>; + cache-unified; next-level-cache = <&l3_cache>; }; @@ -254,6 +268,8 @@ cache-size = <524288>; cache-line-size = <64>; cache-sets = <1024>; + cache-level = <2>; + cache-unified; next-level-cache = <&l3_cache>; }; @@ -262,6 +278,8 @@ cache-size = <524288>; cache-line-size = <64>; cache-sets = <1024>; + cache-level = <2>; + cache-unified; next-level-cache = <&l3_cache>; }; @@ -270,6 +288,8 @@ cache-size = <524288>; cache-line-size = <64>; cache-sets = <1024>; + cache-level = <2>; + cache-unified; next-level-cache = <&l3_cache>; }; @@ -278,6 +298,8 @@ cache-size = <524288>; cache-line-size = <64>; cache-sets = <1024>; + cache-level = <2>; + cache-unified; next-level-cache = <&l3_cache>; }; @@ -286,6 +308,8 @@ cache-size = <3145728>; cache-line-size = <64>; cache-sets = <4096>; + cache-level = <3>; + cache-unified; }; }; @@ -304,10 +328,6 @@ scmi_clk: protocol@14 { reg = <0x14>; - assigned-clocks = <&scmi_clk SCMI_CLK_CPUB01>, - <&scmi_clk SCMI_CLK_CPUB23>; - assigned-clock-rates = <1200000000>, - <1200000000>; #clock-cells = <1>; }; @@ -414,7 +434,7 @@ <&cru ACLK_BUS_ROOT>, <&cru CLK_150M_SRC>, <&cru CLK_GPU>; assigned-clock-rates = - <100000000>, <786432000>, + <1100000000>, <786432000>, <850000000>, <1188000000>, <702000000>, <400000000>, <500000000>, @@ -1132,6 +1152,103 @@ status = "disabled"; }; + i2s0_8ch: i2s@fe470000 { + compatible = "rockchip,rk3588-i2s-tdm"; + reg = <0x0 0xfe470000 0x0 0x1000>; + interrupts = ; + clocks = <&cru MCLK_I2S0_8CH_TX>, <&cru MCLK_I2S0_8CH_RX>, <&cru HCLK_I2S0_8CH>; + clock-names = "mclk_tx", "mclk_rx", "hclk"; + assigned-clocks = <&cru CLK_I2S0_8CH_TX_SRC>, <&cru CLK_I2S0_8CH_RX_SRC>; + assigned-clock-parents = <&cru PLL_AUPLL>, <&cru PLL_AUPLL>; + dmas = <&dmac0 0>, <&dmac0 1>; + dma-names = "tx", "rx"; + power-domains = <&power RK3588_PD_AUDIO>; + resets = <&cru SRST_M_I2S0_8CH_TX>, <&cru SRST_M_I2S0_8CH_RX>; + reset-names = "tx-m", "rx-m"; + rockchip,trcm-sync-tx-only; + pinctrl-names = "default"; + pinctrl-0 = <&i2s0_lrck + &i2s0_sclk + &i2s0_sdi0 + &i2s0_sdi1 + &i2s0_sdi2 + &i2s0_sdi3 + &i2s0_sdo0 + &i2s0_sdo1 + &i2s0_sdo2 + &i2s0_sdo3>; + #sound-dai-cells = <0>; + status = "disabled"; + }; + + i2s1_8ch: i2s@fe480000 { + compatible = "rockchip,rk3588-i2s-tdm"; + reg = <0x0 0xfe480000 0x0 0x1000>; + interrupts = ; + clocks = <&cru MCLK_I2S1_8CH_TX>, <&cru MCLK_I2S1_8CH_RX>, <&cru HCLK_I2S1_8CH>; + clock-names = "mclk_tx", "mclk_rx", "hclk"; + dmas = <&dmac0 2>, <&dmac0 3>; + dma-names = "tx", "rx"; + resets = <&cru SRST_M_I2S1_8CH_TX>, <&cru SRST_M_I2S1_8CH_RX>; + reset-names = "tx-m", "rx-m"; + rockchip,trcm-sync-tx-only; + pinctrl-names = "default"; + pinctrl-0 = <&i2s1m0_lrck + &i2s1m0_sclk + &i2s1m0_sdi0 + &i2s1m0_sdi1 + &i2s1m0_sdi2 + &i2s1m0_sdi3 + &i2s1m0_sdo0 + &i2s1m0_sdo1 + &i2s1m0_sdo2 + &i2s1m0_sdo3>; + #sound-dai-cells = <0>; + status = "disabled"; + }; + + i2s2_2ch: i2s@fe490000 { + compatible = "rockchip,rk3588-i2s", "rockchip,rk3066-i2s"; + reg = <0x0 0xfe490000 0x0 0x1000>; + interrupts = ; + clocks = <&cru MCLK_I2S2_2CH>, <&cru HCLK_I2S2_2CH>; + clock-names = "i2s_clk", "i2s_hclk"; + assigned-clocks = <&cru CLK_I2S2_2CH_SRC>; + assigned-clock-parents = <&cru PLL_AUPLL>; + dmas = <&dmac1 0>, <&dmac1 1>; + dma-names = "tx", "rx"; + power-domains = <&power RK3588_PD_AUDIO>; + rockchip,trcm-sync-tx-only; + pinctrl-names = "default"; + pinctrl-0 = <&i2s2m1_lrck + &i2s2m1_sclk + &i2s2m1_sdi + &i2s2m1_sdo>; + #sound-dai-cells = <0>; + status = "disabled"; + }; + + i2s3_2ch: i2s@fe4a0000 { + compatible = "rockchip,rk3588-i2s", "rockchip,rk3066-i2s"; + reg = <0x0 0xfe4a0000 0x0 0x1000>; + interrupts = ; + clocks = <&cru MCLK_I2S3_2CH>, <&cru HCLK_I2S3_2CH>; + clock-names = "i2s_clk", "i2s_hclk"; + assigned-clocks = <&cru CLK_I2S3_2CH_SRC>; + assigned-clock-parents = <&cru PLL_AUPLL>; + dmas = <&dmac1 2>, <&dmac1 3>; + dma-names = "tx", "rx"; + power-domains = <&power RK3588_PD_AUDIO>; + rockchip,trcm-sync-tx-only; + pinctrl-names = "default"; + pinctrl-0 = <&i2s3_lrck + &i2s3_sclk + &i2s3_sdi + &i2s3_sdo>; + #sound-dai-cells = <0>; + status = "disabled"; + }; + gic: interrupt-controller@fe600000 { compatible = "arm,gic-v3"; reg = <0x0 0xfe600000 0 0x10000>, /* GICD */ @@ -1141,7 +1258,24 @@ mbi-alias = <0x0 0xfe610000>; mbi-ranges = <424 56>; msi-controller; + ranges; + #address-cells = <2>; #interrupt-cells = <4>; + #size-cells = <2>; + + its0: msi-controller@fe640000 { + compatible = "arm,gic-v3-its"; + reg = <0x0 0xfe640000 0x0 0x20000>; + msi-controller; + #msi-cells = <1>; + }; + + its1: msi-controller@fe660000 { + compatible = "arm,gic-v3-its"; + reg = <0x0 0xfe660000 0x0 0x20000>; + msi-controller; + #msi-cells = <1>; + }; ppi-partitions { ppi_partition0: interrupt-partition-0 { @@ -1241,6 +1375,22 @@ status = "disabled"; }; + timer0: timer@feae0000 { + compatible = "rockchip,rk3588-timer", "rockchip,rk3288-timer"; + reg = <0x0 0xfeae0000 0x0 0x20>; + interrupts = ; + clocks = <&cru PCLK_BUSTIMER0>, <&cru CLK_BUSTIMER0>; + clock-names = "pclk", "timer"; + }; + + wdt: watchdog@feaf0000 { + compatible = "rockchip,rk3588-wdt", "snps,dw-wdt"; + reg = <0x0 0xfeaf0000 0x0 0x100>; + clocks = <&cru TCLK_WDT0>, <&cru PCLK_WDT0>; + clock-names = "tclk", "pclk"; + interrupts = ; + }; + spi0: spi@feb00000 { compatible = "rockchip,rk3588-spi", "rockchip,rk3066-spi"; reg = <0x0 0xfeb00000 0x0 0x1000>; @@ -1572,6 +1722,26 @@ status = "disabled"; }; + tsadc: tsadc@fec00000 { + compatible = "rockchip,rk3588-tsadc"; + reg = <0x0 0xfec00000 0x0 0x400>; + interrupts = ; + clocks = <&cru CLK_TSADC>, <&cru PCLK_TSADC>; + clock-names = "tsadc", "apb_pclk"; + assigned-clocks = <&cru CLK_TSADC>; + assigned-clock-rates = <2000000>; + resets = <&cru SRST_P_TSADC>, <&cru SRST_TSADC>; + reset-names = "tsadc-apb", "tsadc"; + rockchip,hw-tshut-temp = <120000>; + rockchip,hw-tshut-mode = <0>; /* tshut mode 0:CRU 1:GPIO */ + rockchip,hw-tshut-polarity = <0>; /* tshut polarity 0:LOW 1:HIGH */ + pinctrl-0 = <&tsadc_gpio_func>; + pinctrl-1 = <&tsadc_shut>; + pinctrl-names = "gpio", "otpout"; + #thermal-sensor-cells = <1>; + status = "disabled"; + }; + i2c6: i2c@fec80000 { compatible = "rockchip,rk3588-i2c", "rockchip,rk3399-i2c"; reg = <0x0 0xfec80000 0x0 0x1000>; @@ -1627,6 +1797,60 @@ status = "disabled"; }; + otp: efuse@fecc0000 { + compatible = "rockchip,rk3588-otp"; + reg = <0x0 0xfecc0000 0x0 0x400>; + clocks = <&cru CLK_OTPC_NS>, <&cru PCLK_OTPC_NS>, + <&cru CLK_OTP_PHY_G>, <&cru CLK_OTPC_ARB>; + clock-names = "otp", "apb_pclk", "phy", "arb"; + resets = <&cru SRST_OTPC_NS>, <&cru SRST_P_OTPC_NS>, + <&cru SRST_OTPC_ARB>; + reset-names = "otp", "apb", "arb"; + #address-cells = <1>; + #size-cells = <1>; + + cpu_code: cpu-code@2 { + reg = <0x02 0x2>; + }; + + otp_id: id@7 { + reg = <0x07 0x10>; + }; + + cpub0_leakage: cpu-leakage@17 { + reg = <0x17 0x1>; + }; + + cpub1_leakage: cpu-leakage@18 { + reg = <0x18 0x1>; + }; + + cpul_leakage: cpu-leakage@19 { + reg = <0x19 0x1>; + }; + + log_leakage: log-leakage@1a { + reg = <0x1a 0x1>; + }; + + gpu_leakage: gpu-leakage@1b { + reg = <0x1b 0x1>; + }; + + otp_cpu_version: cpu-version@1c { + reg = <0x1c 0x1>; + bits = <3 3>; + }; + + npu_leakage: npu-leakage@28 { + reg = <0x28 0x1>; + }; + + codec_leakage: codec-leakage@29 { + reg = <0x29 0x1>; + }; + }; + dmac2: dma-controller@fed10000 { compatible = "arm,pl330", "arm,primecell"; reg = <0x0 0xfed10000 0x0 0x4000>; -- cgit v1.3.1 From 7b57ca18f8a3a88216b69cd295e1eed2b0c6c1be Mon Sep 17 00:00:00 2001 From: Frank Wang Date: Mon, 29 May 2023 13:01:33 +0300 Subject: phy: rockchip: add usbdp combo phy driver This adds a new USBDP combo PHY with Samsung IP block driver. The PHY is a combo between USB 3.0 and DisplayPort alt mode. Signed-off-by: Frank Wang [eugen.hristev@collabora.com: ported to 2023.07, clean-up] Signed-off-by: Eugen Hristev Reviewed-by: Kever Yang --- drivers/phy/rockchip/Kconfig | 7 + drivers/phy/rockchip/Makefile | 1 + drivers/phy/rockchip/phy-rockchip-usbdp.c | 880 ++++++++++++++++++++++++++++++ include/linux/usb/phy-rockchip-usbdp.h | 70 +++ 4 files changed, 958 insertions(+) create mode 100644 drivers/phy/rockchip/phy-rockchip-usbdp.c create mode 100644 include/linux/usb/phy-rockchip-usbdp.h diff --git a/drivers/phy/rockchip/Kconfig b/drivers/phy/rockchip/Kconfig index f87ca8c3106..0247d93ab40 100644 --- a/drivers/phy/rockchip/Kconfig +++ b/drivers/phy/rockchip/Kconfig @@ -41,6 +41,13 @@ config PHY_ROCKCHIP_SNPS_PCIE3 It could support PCIe Gen3 single root complex, and could also be able splited into multiple combinations of lanes. +config PHY_ROCKCHIP_USBDP + tristate "Rockchip USBDP COMBO PHY Driver" + depends on ARCH_ROCKCHIP + select PHY + help + Enable this to support the Rockchip USB3.0/DP + combo PHY with Samsung IP block. config PHY_ROCKCHIP_TYPEC bool "Rockchip TYPEC PHY Driver" diff --git a/drivers/phy/rockchip/Makefile b/drivers/phy/rockchip/Makefile index 25a803a8a86..7fdbd107976 100644 --- a/drivers/phy/rockchip/Makefile +++ b/drivers/phy/rockchip/Makefile @@ -9,3 +9,4 @@ obj-$(CONFIG_PHY_ROCKCHIP_PCIE) += phy-rockchip-pcie.o obj-$(CONFIG_PHY_ROCKCHIP_SNPS_PCIE3) += phy-rockchip-snps-pcie3.o obj-$(CONFIG_PHY_ROCKCHIP_TYPEC) += phy-rockchip-typec.o obj-$(CONFIG_PHY_ROCKCHIP_INNO_DSIDPHY) += phy-rockchip-inno-dsidphy.o +obj-$(CONFIG_PHY_ROCKCHIP_USBDP) += phy-rockchip-usbdp.o diff --git a/drivers/phy/rockchip/phy-rockchip-usbdp.c b/drivers/phy/rockchip/phy-rockchip-usbdp.c new file mode 100644 index 00000000000..baf92529348 --- /dev/null +++ b/drivers/phy/rockchip/phy-rockchip-usbdp.c @@ -0,0 +1,880 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Rockchip USBDP Combo PHY with Samsung IP block driver + * + * Copyright (C) 2021 Rockchip Electronics Co., Ltd + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include + +#define BIT_WRITEABLE_SHIFT 16 + +enum { + UDPHY_MODE_NONE = 0, + UDPHY_MODE_USB = BIT(0), + UDPHY_MODE_DP = BIT(1), + UDPHY_MODE_DP_USB = BIT(1) | BIT(0), +}; + +struct udphy_grf_reg { + unsigned int offset; + unsigned int bitend; + unsigned int bitstart; + unsigned int disable; + unsigned int enable; +}; + +/** + * struct reg_sequence - An individual write from a sequence of writes. + * + * @reg: Register address. + * @def: Register value. + * @delay_us: Delay to be applied after the register write in microseconds + * + * Register/value pairs for sequences of writes with an optional delay in + * microseconds to be applied after each write. + */ +struct reg_sequence { + unsigned int reg; + unsigned int def; + unsigned int delay_us; +}; + +struct udphy_grf_cfg { + /* u2phy-grf */ + struct udphy_grf_reg bvalid_phy_con; + struct udphy_grf_reg bvalid_grf_con; + + /* usb-grf */ + struct udphy_grf_reg usb3otg0_cfg; + struct udphy_grf_reg usb3otg1_cfg; + + /* usbdpphy-grf */ + struct udphy_grf_reg low_pwrn; + struct udphy_grf_reg rx_lfps; +}; + +struct rockchip_udphy; + +struct rockchip_udphy_cfg { + /* resets to be requested */ + const char * const *rst_list; + int num_rsts; + + struct udphy_grf_cfg grfcfg; + int (*combophy_init)(struct rockchip_udphy *udphy); +}; + +struct rockchip_udphy { + struct udevice *dev; + struct regmap *pma_regmap; + struct regmap *u2phygrf; + struct regmap *udphygrf; + struct regmap *usbgrf; + struct regmap *vogrf; + + /* clocks and rests */ + struct reset_ctl *rsts; + + /* PHY status management */ + bool flip; + bool mode_change; + u8 mode; + u8 status; + + /* utilized for USB */ + bool hs; /* flag for high-speed */ + + /* utilized for DP */ + struct gpio_desc *sbu1_dc_gpio; + struct gpio_desc *sbu2_dc_gpio; + u32 lane_mux_sel[4]; + u32 dp_lane_sel[4]; + u32 dp_aux_dout_sel; + u32 dp_aux_din_sel; + int id; + + /* PHY const config */ + const struct rockchip_udphy_cfg *cfgs; +}; + +static const struct reg_sequence rk3588_udphy_24m_refclk_cfg[] = { + {0x0090, 0x68}, {0x0094, 0x68}, + {0x0128, 0x24}, {0x012c, 0x44}, + {0x0130, 0x3f}, {0x0134, 0x44}, + {0x015c, 0xa9}, {0x0160, 0x71}, + {0x0164, 0x71}, {0x0168, 0xa9}, + {0x0174, 0xa9}, {0x0178, 0x71}, + {0x017c, 0x71}, {0x0180, 0xa9}, + {0x018c, 0x41}, {0x0190, 0x00}, + {0x0194, 0x05}, {0x01ac, 0x2a}, + {0x01b0, 0x17}, {0x01b4, 0x17}, + {0x01b8, 0x2a}, {0x01c8, 0x04}, + {0x01cc, 0x08}, {0x01d0, 0x08}, + {0x01d4, 0x04}, {0x01d8, 0x20}, + {0x01dc, 0x01}, {0x01e0, 0x09}, + {0x01e4, 0x03}, {0x01f0, 0x29}, + {0x01f4, 0x02}, {0x01f8, 0x02}, + {0x01fc, 0x29}, {0x0208, 0x2a}, + {0x020c, 0x17}, {0x0210, 0x17}, + {0x0214, 0x2a}, {0x0224, 0x20}, + {0x03f0, 0x0d}, {0x03f4, 0x09}, + {0x03f8, 0x09}, {0x03fc, 0x0d}, + {0x0404, 0x0e}, {0x0408, 0x14}, + {0x040c, 0x14}, {0x0410, 0x3b}, + {0x0ce0, 0x68}, {0x0ce8, 0xd0}, + {0x0cf0, 0x87}, {0x0cf8, 0x70}, + {0x0d00, 0x70}, {0x0d08, 0xa9}, + {0x1ce0, 0x68}, {0x1ce8, 0xd0}, + {0x1cf0, 0x87}, {0x1cf8, 0x70}, + {0x1d00, 0x70}, {0x1d08, 0xa9}, + {0x0a3c, 0xd0}, {0x0a44, 0xd0}, + {0x0a48, 0x01}, {0x0a4c, 0x0d}, + {0x0a54, 0xe0}, {0x0a5c, 0xe0}, + {0x0a64, 0xa8}, {0x1a3c, 0xd0}, + {0x1a44, 0xd0}, {0x1a48, 0x01}, + {0x1a4c, 0x0d}, {0x1a54, 0xe0}, + {0x1a5c, 0xe0}, {0x1a64, 0xa8} +}; + +static const struct reg_sequence rk3588_udphy_init_sequence[] = { + {0x0104, 0x44}, {0x0234, 0xE8}, + {0x0248, 0x44}, {0x028C, 0x18}, + {0x081C, 0xE5}, {0x0878, 0x00}, + {0x0994, 0x1C}, {0x0AF0, 0x00}, + {0x181C, 0xE5}, {0x1878, 0x00}, + {0x1994, 0x1C}, {0x1AF0, 0x00}, + {0x0428, 0x60}, {0x0D58, 0x33}, + {0x1D58, 0x33}, {0x0990, 0x74}, + {0x0D64, 0x17}, {0x08C8, 0x13}, + {0x1990, 0x74}, {0x1D64, 0x17}, + {0x18C8, 0x13}, {0x0D90, 0x40}, + {0x0DA8, 0x40}, {0x0DC0, 0x40}, + {0x0DD8, 0x40}, {0x1D90, 0x40}, + {0x1DA8, 0x40}, {0x1DC0, 0x40}, + {0x1DD8, 0x40}, {0x03C0, 0x30}, + {0x03C4, 0x06}, {0x0E10, 0x00}, + {0x1E10, 0x00}, {0x043C, 0x0F}, + {0x0D2C, 0xFF}, {0x1D2C, 0xFF}, + {0x0D34, 0x0F}, {0x1D34, 0x0F}, + {0x08FC, 0x2A}, {0x0914, 0x28}, + {0x0A30, 0x03}, {0x0E38, 0x05}, + {0x0ECC, 0x27}, {0x0ED0, 0x22}, + {0x0ED4, 0x26}, {0x18FC, 0x2A}, + {0x1914, 0x28}, {0x1A30, 0x03}, + {0x1E38, 0x05}, {0x1ECC, 0x27}, + {0x1ED0, 0x22}, {0x1ED4, 0x26}, + {0x0048, 0x0F}, {0x0060, 0x3C}, + {0x0064, 0xF7}, {0x006C, 0x20}, + {0x0070, 0x7D}, {0x0074, 0x68}, + {0x0AF4, 0x1A}, {0x1AF4, 0x1A}, + {0x0440, 0x3F}, {0x10D4, 0x08}, + {0x20D4, 0x08}, {0x00D4, 0x30}, + {0x0024, 0x6e}, +}; + +static inline int grfreg_write(struct regmap *base, + const struct udphy_grf_reg *reg, bool en) +{ + u32 val, mask, tmp; + + tmp = en ? reg->enable : reg->disable; + mask = GENMASK(reg->bitend, reg->bitstart); + val = (tmp << reg->bitstart) | (mask << BIT_WRITEABLE_SHIFT); + + return regmap_write(base, reg->offset, val); +} + +static int __regmap_multi_reg_write(struct regmap *map, + const struct reg_sequence *regs, + int num_regs) +{ + int i, ret = 0; + + for (i = 0; i < num_regs; i++) { + ret = regmap_write(map, regs[i].reg, regs[i].def); + + if (regs[i].delay_us) + udelay(regs[i].delay_us); + } + + return ret; +} + +static int udphy_clk_init(struct rockchip_udphy *udphy, struct udevice *dev) +{ + return 0; +} + +static int udphy_reset_init(struct rockchip_udphy *udphy, struct udevice *dev) +{ + const struct rockchip_udphy_cfg *cfg = udphy->cfgs; + int idx; + int ret; + + udphy->rsts = devm_kcalloc(dev, cfg->num_rsts, + sizeof(*udphy->rsts), GFP_KERNEL); + if (!udphy->rsts) + return -ENOMEM; + + for (idx = 0; idx < cfg->num_rsts; idx++) { + const char *name = cfg->rst_list[idx]; + + ret = reset_get_by_name(dev, name, &udphy->rsts[idx]); + if (ret) { + dev_err(dev, "failed to get %s reset\n", name); + goto err; + } + + reset_assert(&udphy->rsts[idx]); + } + + return 0; + +err: + devm_kfree(dev, udphy->rsts); + return ret; +} + +static int udphy_get_rst_idx(const char * const *list, int num, char *name) +{ + int idx; + + for (idx = 0; idx < num; idx++) { + if (!strcmp(list[idx], name)) + return idx; + } + + return -EINVAL; +} + +static int udphy_reset_assert(struct rockchip_udphy *udphy, char *name) +{ + const struct rockchip_udphy_cfg *cfg = udphy->cfgs; + int idx; + + idx = udphy_get_rst_idx(cfg->rst_list, cfg->num_rsts, name); + if (idx < 0) + return idx; + + return reset_assert(&udphy->rsts[idx]); +} + +static int udphy_reset_deassert(struct rockchip_udphy *udphy, char *name) +{ + const struct rockchip_udphy_cfg *cfg = udphy->cfgs; + int idx; + + idx = udphy_get_rst_idx(cfg->rst_list, cfg->num_rsts, name); + if (idx < 0) + return idx; + + return reset_deassert(&udphy->rsts[idx]); +} + +static void udphy_u3_port_disable(struct rockchip_udphy *udphy, u8 disable) +{ + const struct rockchip_udphy_cfg *cfg = udphy->cfgs; + const struct udphy_grf_reg *preg; + + preg = udphy->id ? &cfg->grfcfg.usb3otg1_cfg : &cfg->grfcfg.usb3otg0_cfg; + grfreg_write(udphy->usbgrf, preg, disable); +} + +__maybe_unused +static void udphy_usb_bvalid_enable(struct rockchip_udphy *udphy, u8 enable) +{ + const struct rockchip_udphy_cfg *cfg = udphy->cfgs; + + grfreg_write(udphy->u2phygrf, &cfg->grfcfg.bvalid_phy_con, enable); + grfreg_write(udphy->u2phygrf, &cfg->grfcfg.bvalid_grf_con, enable); +} + +/* + * In usb/dp combo phy driver, here are 2 ways to mapping lanes. + * + * 1 Type-C Mapping table (DP_Alt_Mode V1.0b remove ABF pin mapping) + * --------------------------------------------------------------------------- + * Type-C Pin B11-B10 A2-A3 A11-A10 B2-B3 + * PHY Pad ln0(tx/rx) ln1(tx) ln2(tx/rx) ln3(tx) + * C/E(Normal) dpln3 dpln2 dpln0 dpln1 + * C/E(Flip ) dpln0 dpln1 dpln3 dpln2 + * D/F(Normal) usbrx usbtx dpln0 dpln1 + * D/F(Flip ) dpln0 dpln1 usbrx usbtx + * A(Normal ) dpln3 dpln1 dpln2 dpln0 + * A(Flip ) dpln2 dpln0 dpln3 dpln1 + * B(Normal ) usbrx usbtx dpln1 dpln0 + * B(Flip ) dpln1 dpln0 usbrx usbtx + * --------------------------------------------------------------------------- + * + * 2 Mapping the lanes in dtsi + * if all 4 lane assignment for dp function, define rockchip,dp-lane-mux = ; + * sample as follow: + * --------------------------------------------------------------------------- + * B11-B10 A2-A3 A11-A10 B2-B3 + * rockchip,dp-lane-mux ln0(tx/rx) ln1(tx) ln2(tx/rx) ln3(tx) + * <0 1 2 3> dpln0 dpln1 dpln2 dpln3 + * <2 3 0 1> dpln2 dpln3 dpln0 dpln1 + * --------------------------------------------------------------------------- + * if 2 lane for dp function, 2 lane for usb function, define rockchip,dp-lane-mux = ; + * sample as follow: + * --------------------------------------------------------------------------- + * B11-B10 A2-A3 A11-A10 B2-B3 + * rockchip,dp-lane-mux ln0(tx/rx) ln1(tx) ln2(tx/rx) ln3(tx) + * <0 1> dpln0 dpln1 usbrx usbtx + * <2 3> usbrx usbtx dpln0 dpln1 + * --------------------------------------------------------------------------- + */ + +__maybe_unused +static int upphy_set_typec_default_mapping(struct rockchip_udphy *udphy) +{ + if (udphy->flip) { + udphy->dp_lane_sel[0] = 0; + udphy->dp_lane_sel[1] = 1; + udphy->dp_lane_sel[2] = 3; + udphy->dp_lane_sel[3] = 2; + udphy->lane_mux_sel[0] = PHY_LANE_MUX_DP; + udphy->lane_mux_sel[1] = PHY_LANE_MUX_DP; + udphy->lane_mux_sel[2] = PHY_LANE_MUX_USB; + udphy->lane_mux_sel[3] = PHY_LANE_MUX_USB; + udphy->dp_aux_dout_sel = PHY_AUX_DP_DATA_POL_INVERT; + udphy->dp_aux_din_sel = PHY_AUX_DP_DATA_POL_INVERT; + } else { + udphy->dp_lane_sel[0] = 2; + udphy->dp_lane_sel[1] = 3; + udphy->dp_lane_sel[2] = 1; + udphy->dp_lane_sel[3] = 0; + udphy->lane_mux_sel[0] = PHY_LANE_MUX_USB; + udphy->lane_mux_sel[1] = PHY_LANE_MUX_USB; + udphy->lane_mux_sel[2] = PHY_LANE_MUX_DP; + udphy->lane_mux_sel[3] = PHY_LANE_MUX_DP; + udphy->dp_aux_dout_sel = PHY_AUX_DP_DATA_POL_NORMAL; + udphy->dp_aux_din_sel = PHY_AUX_DP_DATA_POL_NORMAL; + } + + udphy->mode = UDPHY_MODE_DP_USB; + + return 0; +} + +static int udphy_setup(struct rockchip_udphy *udphy) +{ + const struct rockchip_udphy_cfg *cfg = udphy->cfgs; + int ret = 0; + + if (cfg->combophy_init) { + ret = cfg->combophy_init(udphy); + if (ret) + dev_err(udphy->dev, "failed to init usbdp combophy\n"); + } + + return ret; +} + +static int udphy_disable(struct rockchip_udphy *udphy) +{ + const struct rockchip_udphy_cfg *cfg = udphy->cfgs; + int i; + + for (i = 0; i < cfg->num_rsts; i++) + reset_assert(&udphy->rsts[i]); + + return 0; +} + +static int udphy_parse_lane_mux_data(struct rockchip_udphy *udphy, + const struct device_node *np) +{ + struct property *prop; + int ret, i, len, num_lanes; + + prop = of_find_property(np, "rockchip,dp-lane-mux", &len); + if (!prop) { + dev_dbg(udphy->dev, + "failed to find dp lane mux, following dp alt mode\n"); + udphy->mode = UDPHY_MODE_USB; + return 0; + } + + num_lanes = len / sizeof(u32); + + if (num_lanes != 2 && num_lanes != 4) { + dev_err(udphy->dev, "invalid number of lane mux\n"); + return -EINVAL; + } + + ret = of_read_u32_array(np, "rockchip,dp-lane-mux", udphy->dp_lane_sel, + num_lanes); + if (ret) { + dev_err(udphy->dev, "get dp lane mux failed\n"); + return -EINVAL; + } + + for (i = 0; i < num_lanes; i++) { + int j; + + if (udphy->dp_lane_sel[i] > 3) { + dev_err(udphy->dev, + "lane mux between 0 and 3, exceeding the range\n"); + return -EINVAL; + } + + udphy->lane_mux_sel[udphy->dp_lane_sel[i]] = PHY_LANE_MUX_DP; + + for (j = i + 1; j < num_lanes; j++) { + if (udphy->dp_lane_sel[i] == udphy->dp_lane_sel[j]) { + dev_err(udphy->dev, + "set repeat lane mux value\n"); + return -EINVAL; + } + } + } + + udphy->mode = UDPHY_MODE_DP; + if (num_lanes == 2) + udphy->mode |= UDPHY_MODE_USB; + + return 0; +} + +static int udphy_parse_dt(struct rockchip_udphy *udphy, struct udevice *dev) +{ + const struct device_node *np = ofnode_to_np(dev_ofnode(dev)); + enum usb_device_speed maximum_speed; + int ret; + + udphy->u2phygrf = syscon_regmap_lookup_by_phandle(dev, + "rockchip,u2phy-grf"); + if (IS_ERR(udphy->u2phygrf)) { + if (PTR_ERR(udphy->u2phygrf) == -ENODEV) { + dev_warn(dev, "missing u2phy-grf dt node\n"); + udphy->u2phygrf = NULL; + } else { + return PTR_ERR(udphy->u2phygrf); + } + } + + udphy->udphygrf = syscon_regmap_lookup_by_phandle(dev, + "rockchip,usbdpphy-grf"); + if (IS_ERR(udphy->udphygrf)) { + if (PTR_ERR(udphy->udphygrf) == -ENODEV) { + dev_warn(dev, "missing usbdpphy-grf dt node\n"); + udphy->udphygrf = NULL; + } else { + return PTR_ERR(udphy->udphygrf); + } + } + + udphy->usbgrf = syscon_regmap_lookup_by_phandle(dev, + "rockchip,usb-grf"); + if (IS_ERR(udphy->usbgrf)) { + if (PTR_ERR(udphy->usbgrf) == -ENODEV) { + dev_warn(dev, "missing usb-grf dt node\n"); + udphy->usbgrf = NULL; + } else { + return PTR_ERR(udphy->usbgrf); + } + } + + udphy->vogrf = syscon_regmap_lookup_by_phandle(dev, "rockchip,vo-grf"); + if (IS_ERR(udphy->vogrf)) { + if (PTR_ERR(udphy->vogrf) == -ENODEV) { + dev_warn(dev, "missing vo-grf dt node\n"); + udphy->vogrf = NULL; + } else { + return PTR_ERR(udphy->vogrf); + } + } + + ret = udphy_parse_lane_mux_data(udphy, np); + if (ret) + return ret; + + if (dev_read_prop(dev, "maximum-speed", NULL)) { + maximum_speed = usb_get_maximum_speed(dev_ofnode(dev)); + udphy->hs = maximum_speed <= USB_SPEED_HIGH ? true : false; + } + + ret = udphy_clk_init(udphy, dev); + if (ret) + return ret; + + ret = udphy_reset_init(udphy, dev); + if (ret) + return ret; + + return 0; +} + +static int udphy_power_on(struct rockchip_udphy *udphy, u8 mode) +{ + int ret; + + if (!(udphy->mode & mode)) { + dev_info(udphy->dev, "mode 0x%02x is not support\n", mode); + return 0; + } + + if (udphy->status == UDPHY_MODE_NONE) { + udphy->mode_change = false; + ret = udphy_setup(udphy); + if (ret) + return ret; + + if (udphy->mode & UDPHY_MODE_USB) + udphy_u3_port_disable(udphy, false); + } else if (udphy->mode_change) { + udphy->mode_change = false; + udphy->status = UDPHY_MODE_NONE; + if (udphy->mode == UDPHY_MODE_DP) + udphy_u3_port_disable(udphy, true); + + ret = udphy_disable(udphy); + if (ret) + return ret; + ret = udphy_setup(udphy); + if (ret) + return ret; + } + + udphy->status |= mode; + + return 0; +} + +static int udphy_power_off(struct rockchip_udphy *udphy, u8 mode) +{ + int ret; + + if (!(udphy->mode & mode)) { + dev_info(udphy->dev, "mode 0x%02x is not supported\n", mode); + return 0; + } + + if (!udphy->status) + return 0; + + udphy->status &= ~mode; + + if (udphy->status == UDPHY_MODE_NONE) { + ret = udphy_disable(udphy); + if (ret) + return ret; + } + + return 0; +} + +static int rockchip_u3phy_init(struct phy *phy) +{ + struct udevice *parent = phy->dev->parent; + struct rockchip_udphy *udphy = dev_get_priv(parent); + + /* DP only or high-speed, disable U3 port */ + if (!(udphy->mode & UDPHY_MODE_USB) || udphy->hs) { + udphy_u3_port_disable(udphy, true); + return 0; + } + + return udphy_power_on(udphy, UDPHY_MODE_USB); +} + +static int rockchip_u3phy_exit(struct phy *phy) +{ + struct udevice *parent = phy->dev->parent; + struct rockchip_udphy *udphy = dev_get_priv(parent); + + /* DP only or high-speed */ + if (!(udphy->mode & UDPHY_MODE_USB) || udphy->hs) + return 0; + + return udphy_power_off(udphy, UDPHY_MODE_USB); +} + +static const struct phy_ops rockchip_u3phy_ops = { + .init = rockchip_u3phy_init, + .exit = rockchip_u3phy_exit, +}; + +int rockchip_u3phy_uboot_init(void) +{ + struct udevice *udev; + struct rockchip_udphy *udphy; + int ret; + + ret = uclass_get_device_by_driver(UCLASS_PHY, + DM_DRIVER_GET(rockchip_udphy_u3_port), + &udev); + if (ret) { + pr_err("%s: get u3-port failed: %d\n", __func__, ret); + return ret; + } + + /* DP only or high-speed, disable U3 port */ + udphy = dev_get_priv(udev->parent); + if (!(udphy->mode & UDPHY_MODE_USB) || udphy->hs) { + udphy_u3_port_disable(udphy, true); + return 0; + } + + return udphy_power_on(udphy, UDPHY_MODE_USB); +} + +static int rockchip_udphy_probe(struct udevice *dev) +{ + const struct device_node *np = ofnode_to_np(dev_ofnode(dev)); + struct rockchip_udphy *udphy = dev_get_priv(dev); + const struct rockchip_udphy_cfg *phy_cfgs; + int id, ret; + + udphy->dev = dev; + + id = of_alias_get_id(np, "usbdp"); + if (id < 0) + id = 0; + udphy->id = id; + + phy_cfgs = (const struct rockchip_udphy_cfg *)dev_get_driver_data(dev); + if (!phy_cfgs) { + dev_err(dev, "unable to get phy_cfgs\n"); + return -EINVAL; + } + udphy->cfgs = phy_cfgs; + + ret = regmap_init_mem(dev_ofnode(dev), &udphy->pma_regmap); + if (ret) + return ret; + udphy->pma_regmap->ranges[0].start += UDPHY_PMA; + + ret = udphy_parse_dt(udphy, dev); + if (ret) + return ret; + + return 0; +} + +static int rockchip_udphy_bind(struct udevice *parent) +{ + struct udevice *child; + ofnode subnode; + const char *node_name; + int ret; + + dev_for_each_subnode(subnode, parent) { + if (!ofnode_valid(subnode)) { + printf("%s: no subnode for %s", __func__, parent->name); + return -ENXIO; + } + + node_name = ofnode_get_name(subnode); + debug("%s: subnode %s\n", __func__, node_name); + + /* if there is no match, continue */ + if (strcasecmp(node_name, "usb3-port")) + continue; + + /* node name is usb3-port */ + ret = device_bind_driver_to_node(parent, + "rockchip_udphy_u3_port", + node_name, subnode, &child); + if (ret) { + printf("%s: '%s' cannot bind its driver\n", + __func__, node_name); + return ret; + } + } + + return 0; +} + +static int rk3588_udphy_refclk_set(struct rockchip_udphy *udphy) +{ + /* configure phy reference clock */ + return __regmap_multi_reg_write(udphy->pma_regmap, + rk3588_udphy_24m_refclk_cfg, + ARRAY_SIZE(rk3588_udphy_24m_refclk_cfg)); +} + +static int rk3588_udphy_status_check(struct rockchip_udphy *udphy) +{ + unsigned int val; + int ret; + + if (!(udphy->mode & UDPHY_MODE_USB)) + return 0; + + /* LCPLL check */ + ret = regmap_read_poll_timeout(udphy->pma_regmap, + CMN_ANA_LCPLL_DONE_OFFSET, + val, (val & CMN_ANA_LCPLL_AFC_DONE) && + (val & CMN_ANA_LCPLL_LOCK_DONE), + 200, 100); + if (ret) { + dev_err(udphy->dev, "cmn ana lcpll lock timeout\n"); + return ret; + } + + if (!udphy->flip) { + ret = regmap_read_poll_timeout(udphy->pma_regmap, + TRSV_LN0_MON_RX_CDR_DONE_OFFSET, + val, + val & TRSV_LN0_MON_RX_CDR_LOCK_DONE, + 200, 100); + if (ret) + dev_err(udphy->dev, "trsv ln0 mon rx cdr lock timeout\n"); + } else { + ret = regmap_read_poll_timeout(udphy->pma_regmap, + TRSV_LN2_MON_RX_CDR_DONE_OFFSET, + val, + val & TRSV_LN2_MON_RX_CDR_LOCK_DONE, + 200, 100); + if (ret) + dev_err(udphy->dev, "trsv ln2 mon rx cdr lock timeout\n"); + } + + return 0; +} + +static int rk3588_udphy_init(struct rockchip_udphy *udphy) +{ + const struct rockchip_udphy_cfg *cfg = udphy->cfgs; + int ret; + + /* enable rx lfps for usb */ + if (udphy->mode & UDPHY_MODE_USB) + grfreg_write(udphy->udphygrf, &cfg->grfcfg.rx_lfps, true); + + /* Step 1: power on pma and deassert apb rstn */ + grfreg_write(udphy->udphygrf, &cfg->grfcfg.low_pwrn, true); + + udphy_reset_deassert(udphy, "pma_apb"); + udphy_reset_deassert(udphy, "pcs_apb"); + + /* Step 2: set init sequence and phy refclk */ + ret = __regmap_multi_reg_write(udphy->pma_regmap, + rk3588_udphy_init_sequence, + ARRAY_SIZE(rk3588_udphy_init_sequence)); + if (ret) { + dev_err(udphy->dev, "init sequence set error %d\n", ret); + goto assert_apb; + } + + ret = rk3588_udphy_refclk_set(udphy); + if (ret) { + dev_err(udphy->dev, "refclk set error %d\n", ret); + goto assert_apb; + } + + /* Step 3: configure lane mux */ + regmap_update_bits(udphy->pma_regmap, CMN_LANE_MUX_AND_EN_OFFSET, + CMN_DP_LANE_MUX_ALL | CMN_DP_LANE_EN_ALL, + FIELD_PREP(CMN_DP_LANE_MUX_N(3), + udphy->lane_mux_sel[3]) | + FIELD_PREP(CMN_DP_LANE_MUX_N(2), + udphy->lane_mux_sel[2]) | + FIELD_PREP(CMN_DP_LANE_MUX_N(1), + udphy->lane_mux_sel[1]) | + FIELD_PREP(CMN_DP_LANE_MUX_N(0), + udphy->lane_mux_sel[0]) | + FIELD_PREP(CMN_DP_LANE_EN_ALL, 0)); + + /* Step 4: deassert init rstn and wait for 200ns from datasheet */ + if (udphy->mode & UDPHY_MODE_USB) + udphy_reset_deassert(udphy, "init"); + + if (udphy->mode & UDPHY_MODE_DP) { + regmap_update_bits(udphy->pma_regmap, CMN_DP_RSTN_OFFSET, + CMN_DP_INIT_RSTN, + FIELD_PREP(CMN_DP_INIT_RSTN, 0x1)); + } + + udelay(1); + + /* Step 5: deassert cmn/lane rstn */ + if (udphy->mode & UDPHY_MODE_USB) { + udphy_reset_deassert(udphy, "cmn"); + udphy_reset_deassert(udphy, "lane"); + } + + /* Step 6: wait for lock done of pll */ + ret = rk3588_udphy_status_check(udphy); + if (ret) + goto assert_phy; + + return 0; + +assert_phy: + udphy_reset_assert(udphy, "init"); + udphy_reset_assert(udphy, "cmn"); + udphy_reset_assert(udphy, "lane"); + +assert_apb: + udphy_reset_assert(udphy, "pma_apb"); + udphy_reset_assert(udphy, "pcs_apb"); + + return ret; +} + +static const char * const rk3588_udphy_rst_l[] = { + "init", "cmn", "lane", "pcs_apb", "pma_apb" +}; + +static const struct rockchip_udphy_cfg rk3588_udphy_cfgs = { + .num_rsts = ARRAY_SIZE(rk3588_udphy_rst_l), + .rst_list = rk3588_udphy_rst_l, + .grfcfg = { + /* u2phy-grf */ + .bvalid_phy_con = { 0x0008, 1, 0, 0x2, 0x3 }, + .bvalid_grf_con = { 0x0010, 3, 2, 0x2, 0x3 }, + + /* usb-grf */ + .usb3otg0_cfg = { 0x001c, 15, 0, 0x1100, 0x0188 }, + .usb3otg1_cfg = { 0x0034, 15, 0, 0x1100, 0x0188 }, + + /* usbdpphy-grf */ + .low_pwrn = { 0x0004, 13, 13, 0, 1 }, + .rx_lfps = { 0x0004, 14, 14, 0, 1 }, + }, + .combophy_init = rk3588_udphy_init, +}; + +static const struct udevice_id rockchip_udphy_dt_match[] = { + { + .compatible = "rockchip,rk3588-usbdp-phy", + .data = (ulong)&rk3588_udphy_cfgs + }, + { /* sentinel */ } +}; + +U_BOOT_DRIVER(rockchip_udphy_u3_port) = { + .name = "rockchip_udphy_u3_port", + .id = UCLASS_PHY, + .ops = &rockchip_u3phy_ops, +}; + +U_BOOT_DRIVER(rockchip_udphy) = { + .name = "rockchip_udphy", + .id = UCLASS_PHY, + .of_match = rockchip_udphy_dt_match, + .probe = rockchip_udphy_probe, + .bind = rockchip_udphy_bind, + .priv_auto = sizeof(struct rockchip_udphy), +}; diff --git a/include/linux/usb/phy-rockchip-usbdp.h b/include/linux/usb/phy-rockchip-usbdp.h new file mode 100644 index 00000000000..8acfa6ddf5a --- /dev/null +++ b/include/linux/usb/phy-rockchip-usbdp.h @@ -0,0 +1,70 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Rockchip USBDP Combo PHY with Samsung IP block driver + * + * Copyright (C) 2021 Rockchip Electronics Co., Ltd + */ + +#ifndef __PHY_ROCKCHIP_USBDP_H_ +#define __PHY_ROCKCHIP_USBDP_H_ + +#include + +/* RK3588 USBDP PHY Register Definitions */ + +#define UDPHY_PCS 0x4000 +#define UDPHY_PMA 0x8000 + +/* VO0 GRF Registers */ +#define RK3588_GRF_VO0_CON0 0x0000 +#define RK3588_GRF_VO0_CON2 0x0008 +#define DP_SINK_HPD_CFG BIT(11) +#define DP_SINK_HPD_SEL BIT(10) +#define DP_AUX_DIN_SEL BIT(9) +#define DP_AUX_DOUT_SEL BIT(8) +#define DP_LANE_SEL_N(n) GENMASK(2 * (n) + 1, 2 * (n)) +#define DP_LANE_SEL_ALL GENMASK(7, 0) +#define PHY_AUX_DP_DATA_POL_NORMAL 0 +#define PHY_AUX_DP_DATA_POL_INVERT 1 + +/* PMA CMN Registers */ +#define CMN_LANE_MUX_AND_EN_OFFSET 0x0288 /* cmn_reg00A2 */ +#define CMN_DP_LANE_MUX_N(n) BIT((n) + 4) +#define CMN_DP_LANE_EN_N(n) BIT(n) +#define CMN_DP_LANE_MUX_ALL GENMASK(7, 4) +#define CMN_DP_LANE_EN_ALL GENMASK(3, 0) +#define PHY_LANE_MUX_USB 0 +#define PHY_LANE_MUX_DP 1 + +#define CMN_DP_LINK_OFFSET 0x28c /*cmn_reg00A3 */ +#define CMN_DP_TX_LINK_BW GENMASK(6, 5) +#define CMN_DP_TX_LANE_SWAP_EN BIT(2) + +#define CMN_SSC_EN_OFFSET 0x2d0 /* cmn_reg00B4 */ +#define CMN_ROPLL_SSC_EN BIT(1) +#define CMN_LCPLL_SSC_EN BIT(0) + +#define CMN_ANA_LCPLL_DONE_OFFSET 0x0350 /* cmn_reg00D4 */ +#define CMN_ANA_LCPLL_LOCK_DONE BIT(7) +#define CMN_ANA_LCPLL_AFC_DONE BIT(6) + +#define CMN_ANA_ROPLL_DONE_OFFSET 0x0354 /* cmn_reg00D5 */ +#define CMN_ANA_ROPLL_LOCK_DONE BIT(1) +#define CMN_ANA_ROPLL_AFC_DONE BIT(0) + +#define CMN_DP_RSTN_OFFSET 0x038c /* cmn_reg00E3 */ +#define CMN_DP_INIT_RSTN BIT(3) +#define CMN_DP_CMN_RSTN BIT(2) +#define CMN_CDR_WTCHDG_EN BIT(1) +#define CMN_CDR_WTCHDG_MSK_CDR_EN BIT(0) + +#define TRSV_ANA_TX_CLK_OFFSET_N(n) (0x854 + (n) * 0x800) /* trsv_reg0215 */ +#define LN_ANA_TX_SER_TXCLK_INV BIT(1) + +#define TRSV_LN0_MON_RX_CDR_DONE_OFFSET 0x0b84 /* trsv_reg02E1 */ +#define TRSV_LN0_MON_RX_CDR_LOCK_DONE BIT(0) + +#define TRSV_LN2_MON_RX_CDR_DONE_OFFSET 0x1b84 /* trsv_reg06E1 */ +#define TRSV_LN2_MON_RX_CDR_LOCK_DONE BIT(0) + +#endif -- cgit v1.3.1 From b8bae824cc2352731e41b7f5235ad09ff9a0f202 Mon Sep 17 00:00:00 2001 From: Joseph Chen Date: Mon, 29 May 2023 13:01:34 +0300 Subject: ARM: dts: rockchip: rk3588: add support for USB 3.0 devices Add support for the USB 3.0 devices in rk3588: - USB DRD(dual role device) 3.0 #0 as usbdrd3_0 which is available in rk3588s - USB DRD(dual role device) 3.0 #1 as usbdrd3_1 which is available in rk3588 only - USB DP PHY (combo USB3.0 and DisplayPort Alt Mode ) #0 phy interface as usbdp_phy0 - USB DP PHY (combo USB3.0 and DisplayPort Alt Mode ) #1 phy interface as usbdp_phy1 - USB 2.0 phy #2 , the USB 3.0 device can work with this phy in USB 2.0 mode - associated GRFs (general register files) for the devices. Signed-off-by: Joseph Chen [eugen.hristev@collabora.com: move nodes to right place, adapt from latest linux kernel] Signed-off-by: Eugen Hristev Reviewed-by: Kever Yang --- arch/arm/dts/rk3588-u-boot.dtsi | 93 ++++++++++++++++++++++++++++++++++ arch/arm/dts/rk3588s-u-boot.dtsi | 105 +++++++++++++++++++++++++++++++++++++++ 2 files changed, 198 insertions(+) diff --git a/arch/arm/dts/rk3588-u-boot.dtsi b/arch/arm/dts/rk3588-u-boot.dtsi index 4c8ac804d61..68b419f3abd 100644 --- a/arch/arm/dts/rk3588-u-boot.dtsi +++ b/arch/arm/dts/rk3588-u-boot.dtsi @@ -5,3 +5,96 @@ #include "rockchip-u-boot.dtsi" #include "rk3588s-u-boot.dtsi" + +/ { + usbdrd3_1: usbdrd3_1 { + compatible = "rockchip,rk3588-dwc3", "rockchip,rk3399-dwc3"; + clocks = <&cru REF_CLK_USB3OTG1>, <&cru SUSPEND_CLK_USB3OTG1>, + <&cru ACLK_USB3OTG1>; + clock-names = "ref", "suspend", "bus"; + #address-cells = <2>; + #size-cells = <2>; + ranges; + status = "disabled"; + + usbdrd_dwc3_1: usb@fc400000 { + compatible = "snps,dwc3"; + reg = <0x0 0xfc400000 0x0 0x400000>; + interrupts = ; + power-domains = <&power RK3588_PD_USB>; + resets = <&cru SRST_A_USB3OTG1>; + reset-names = "usb3-otg"; + dr_mode = "host"; + phys = <&u2phy1_otg>, <&usbdp_phy1_u3>; + phy-names = "usb2-phy", "usb3-phy"; + phy_type = "utmi_wide"; + snps,dis_enblslpm_quirk; + snps,dis-u2-freeclk-exists-quirk; + snps,dis-del-phy-power-chg-quirk; + snps,dis-tx-ipgap-linecheck-quirk; + }; + }; + + usbdpphy1_grf: syscon@fd5cc000 { + compatible = "rockchip,rk3588-usbdpphy-grf", "syscon"; + reg = <0x0 0xfd5cc000 0x0 0x4000>; + }; + + usb2phy1_grf: syscon@fd5d4000 { + compatible = "rockchip,rk3588-usb2phy-grf", "syscon", + "simple-mfd"; + reg = <0x0 0xfd5d4000 0x0 0x4000>; + #address-cells = <1>; + #size-cells = <1>; + + u2phy1: usb2-phy@4000 { + compatible = "rockchip,rk3588-usb2phy"; + reg = <0x4000 0x10>; + interrupts = ; + resets = <&cru SRST_OTGPHY_U3_1>, <&cru SRST_P_USB2PHY_U3_1_GRF0>; + reset-names = "phy", "apb"; + clocks = <&cru CLK_USB2PHY_HDPTXRXPHY_REF>; + clock-names = "phyclk"; + clock-output-names = "usb480m_phy1"; + #clock-cells = <0>; + rockchip,usbctrl-grf = <&usb_grf>; + status = "disabled"; + + u2phy1_otg: otg-port { + #phy-cells = <0>; + status = "disabled"; + }; + }; + }; + + usbdp_phy1: phy@fed90000 { + compatible = "rockchip,rk3588-usbdp-phy"; + reg = <0x0 0xfed90000 0x0 0x10000>; + rockchip,u2phy-grf = <&usb2phy1_grf>; + rockchip,usb-grf = <&usb_grf>; + rockchip,usbdpphy-grf = <&usbdpphy1_grf>; + rockchip,vo-grf = <&vo0_grf>; + clocks = <&cru CLK_USBDPPHY_MIPIDCPPHY_REF>, + <&cru CLK_USBDP_PHY1_IMMORTAL>, + <&cru PCLK_USBDPPHY1>, + <&u2phy1>; + clock-names = "refclk", "immortal", "pclk", "utmi"; + resets = <&cru SRST_USBDP_COMBO_PHY1_INIT>, + <&cru SRST_USBDP_COMBO_PHY1_CMN>, + <&cru SRST_USBDP_COMBO_PHY1_LANE>, + <&cru SRST_USBDP_COMBO_PHY1_PCS>, + <&cru SRST_P_USBDPPHY1>; + reset-names = "init", "cmn", "lane", "pcs_apb", "pma_apb"; + status = "disabled"; + + usbdp_phy1_dp: dp-port { + #phy-cells = <0>; + status = "disabled"; + }; + + usbdp_phy1_u3: usb3-port { + #phy-cells = <0>; + status = "disabled"; + }; + }; +}; diff --git a/arch/arm/dts/rk3588s-u-boot.dtsi b/arch/arm/dts/rk3588s-u-boot.dtsi index 1bb3c6a9d95..acb1cfe2006 100644 --- a/arch/arm/dts/rk3588s-u-boot.dtsi +++ b/arch/arm/dts/rk3588s-u-boot.dtsi @@ -13,6 +13,37 @@ status = "okay"; }; + usbdrd3_0: usbdrd3_0 { + compatible = "rockchip,rk3588-dwc3", "rockchip,rk3399-dwc3"; + clocks = <&cru REF_CLK_USB3OTG0>, <&cru SUSPEND_CLK_USB3OTG0>, + <&cru ACLK_USB3OTG0>; + clock-names = "ref", "suspend", "bus"; + #address-cells = <2>; + #size-cells = <2>; + ranges; + status = "disabled"; + + usbdrd_dwc3_0: usb@fc000000 { + compatible = "snps,dwc3"; + reg = <0x0 0xfc000000 0x0 0x400000>; + interrupts = ; + power-domains = <&power RK3588_PD_USB>; + resets = <&cru SRST_A_USB3OTG0>; + reset-names = "usb3-otg"; + dr_mode = "otg"; + phys = <&u2phy0_otg>, <&usbdp_phy0_u3>; + phy-names = "usb2-phy", "usb3-phy"; + phy_type = "utmi_wide"; + snps,dis_enblslpm_quirk; + snps,dis-u1-entry-quirk; + snps,dis-u2-entry-quirk; + snps,dis-u2-freeclk-exists-quirk; + snps,dis-del-phy-power-chg-quirk; + snps,dis-tx-ipgap-linecheck-quirk; + quirk-skip-phy-init; + }; + }; + usb_host0_ehci: usb@fc800000 { compatible = "generic-ehci"; reg = <0x0 0xfc800000 0x0 0x40000>; @@ -64,6 +95,33 @@ reg = <0x0 0xfd5bc000 0x0 0x100>; }; + usb2phy0_grf: syscon@fd5d0000 { + compatible = "rockchip,rk3588-usb2phy-grf", "syscon", + "simple-mfd"; + reg = <0x0 0xfd5d0000 0x0 0x4000>; + #address-cells = <1>; + #size-cells = <1>; + + u2phy0: usb2-phy@0 { + compatible = "rockchip,rk3588-usb2phy"; + reg = <0x0 0x10>; + interrupts = ; + resets = <&cru SRST_OTGPHY_U3_0>, <&cru SRST_P_USB2PHY_U3_0_GRF0>; + reset-names = "phy", "apb"; + clocks = <&cru CLK_USB2PHY_HDPTXRXPHY_REF>; + clock-names = "phyclk"; + clock-output-names = "usb480m_phy0"; + #clock-cells = <0>; + rockchip,usbctrl-grf = <&usb_grf>; + status = "disabled"; + + u2phy0_otg: otg-port { + #phy-cells = <0>; + status = "disabled"; + }; + }; + }; + usb2phy2_grf: syscon@fd5d8000 { compatible = "rockchip,rk3588-usb2phy-grf", "syscon", "simple-mfd"; @@ -87,6 +145,17 @@ }; }; + vo0_grf: syscon@fd5a6000 { + compatible = "rockchip,rk3588-vo-grf", "syscon"; + reg = <0x0 0xfd5a6000 0x0 0x2000>; + clocks = <&cru PCLK_VO0GRF>; + }; + + usb_grf: syscon@fd5ac000 { + compatible = "rockchip,rk3588-usb-grf", "syscon"; + reg = <0x0 0xfd5ac000 0x0 0x4000>; + }; + usb2phy3_grf: syscon@fd5dc000 { compatible = "rockchip,rk3588-usb2phy-grf", "syscon", "simple-mfd"; @@ -110,6 +179,11 @@ }; }; + usbdpphy0_grf: syscon@fd5c8000 { + compatible = "rockchip,rk3588-usbdpphy-grf", "syscon"; + reg = <0x0 0xfd5c8000 0x0 0x4000>; + }; + pcie2x1l2: pcie@fe190000 { compatible = "rockchip,rk3588-pcie", "snps,dw-pcie"; #address-cells = <3>; @@ -180,6 +254,37 @@ status = "disabled"; }; + usbdp_phy0: phy@fed80000 { + compatible = "rockchip,rk3588-usbdp-phy"; + reg = <0x0 0xfed80000 0x0 0x10000>; + rockchip,u2phy-grf = <&usb2phy0_grf>; + rockchip,usb-grf = <&usb_grf>; + rockchip,usbdpphy-grf = <&usbdpphy0_grf>; + rockchip,vo-grf = <&vo0_grf>; + clocks = <&cru CLK_USBDPPHY_MIPIDCPPHY_REF>, + <&cru CLK_USBDP_PHY0_IMMORTAL>, + <&cru PCLK_USBDPPHY0>, + <&u2phy0>; + clock-names = "refclk", "immortal", "pclk", "utmi"; + resets = <&cru SRST_USBDP_COMBO_PHY0_INIT>, + <&cru SRST_USBDP_COMBO_PHY0_CMN>, + <&cru SRST_USBDP_COMBO_PHY0_LANE>, + <&cru SRST_USBDP_COMBO_PHY0_PCS>, + <&cru SRST_P_USBDPPHY0>; + reset-names = "init", "cmn", "lane", "pcs_apb", "pma_apb"; + status = "disabled"; + + usbdp_phy0_dp: dp-port { + #phy-cells = <0>; + status = "disabled"; + }; + + usbdp_phy0_u3: usb3-port { + #phy-cells = <0>; + status = "disabled"; + }; + }; + combphy0_ps: phy@fee00000 { compatible = "rockchip,rk3588-naneng-combphy"; reg = <0x0 0xfee00000 0x0 0x100>; -- cgit v1.3.1 From 32961c09af6e4145abf18056d98fe52667e88235 Mon Sep 17 00:00:00 2001 From: Eugen Hristev Date: Mon, 29 May 2023 13:01:35 +0300 Subject: ARM: dts: rockchip: rk3588-rock-5b-u-boot: add USB3 support Enable the USB3.0 host node, and gadget node. The gadget is available through the USB type C connector on the board. The connector is tied to a Fairchild fusb302b device, which currently does not have a driver in U-boot, but the node is here for correct description of the board + Linux future compatibility. It will be easier to move the node as-is when it will be available in the DT from Linux Signed-off-by: Eugen Hristev Reviewed-by: Kever Yang --- arch/arm/dts/rk3588-rock-5b-u-boot.dtsi | 197 ++++++++++++++++++++++++++++++++ 1 file changed, 197 insertions(+) diff --git a/arch/arm/dts/rk3588-rock-5b-u-boot.dtsi b/arch/arm/dts/rk3588-rock-5b-u-boot.dtsi index 1cd8a57a6fa..5a329269964 100644 --- a/arch/arm/dts/rk3588-rock-5b-u-boot.dtsi +++ b/arch/arm/dts/rk3588-rock-5b-u-boot.dtsi @@ -7,6 +7,7 @@ #include #include #include +#include / { aliases { @@ -18,6 +19,25 @@ u-boot,spl-boot-order = "same-as-spl", &sdmmc, &sdhci; }; + vcc12v_dcin: vcc12v-dcin-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc12v_dcin"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <12000000>; + regulator-max-microvolt = <12000000>; + }; + + vcc5v0_usbdcin: vcc5v0-usbdcin { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_usbdcin"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&vcc12v_dcin>; + }; + vcc5v0_host: vcc5v0-host-regulator { compatible = "regulator-fixed"; regulator-name = "vcc5v0_host"; @@ -29,6 +49,28 @@ pinctrl-0 = <&vcc5v0_host_en>; vin-supply = <&vcc5v0_sys>; }; + + vcc5v0_usb: vcc5v0-usb { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_usb"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&vcc5v0_usbdcin>; + }; + + vbus5v0_typec: vbus5v0-typec { + compatible = "regulator-fixed"; + regulator-name = "vbus5v0_typec"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + enable-active-high; + gpio = <&gpio2 RK_PB6 GPIO_ACTIVE_HIGH>; + vin-supply = <&vcc5v0_usb>; + pinctrl-names = "default"; + pinctrl-0 = <&typec5v_pwren>; + }; }; &combphy0_ps { @@ -85,6 +127,16 @@ rockchip,pins = <4 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>; }; }; + + usb-typec { + usbc0_int: usbc0-int { + rockchip,pins = <3 RK_PB4 RK_FUNC_GPIO &pcfg_pull_up>; + }; + + typec5v_pwren: typec5v-pwren { + rockchip,pins = <2 RK_PB6 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; }; &pcfg_pull_none { @@ -168,6 +220,15 @@ status = "okay"; }; +&u2phy0 { + status = "okay"; +}; + +&u2phy0_otg { + rockchip,typec-vbus-det; + status = "okay"; +}; + &u2phy2 { resets = <&cru SRST_OTGPHY_U2_0>, <&cru SRST_P_USB2PHY_U2_0_GRF0>; reset-names = "phy", "apb"; @@ -209,3 +270,139 @@ status = "okay"; }; +&usbdp_phy0 { + orientation-switch; + svid = <0xff01>; + sbu1-dc-gpios = <&gpio4 RK_PA6 GPIO_ACTIVE_HIGH>; + sbu2-dc-gpios = <&gpio4 RK_PA7 GPIO_ACTIVE_HIGH>; + status = "okay"; + + port { + #address-cells = <1>; + #size-cells = <0>; + usbdp_phy0_orientation_switch: endpoint@0 { + reg = <0>; + remote-endpoint = <&usbc0_orien_sw>; + }; + + usbdp_phy0_dp_altmode_mux: endpoint@1 { + reg = <1>; + remote-endpoint = <&dp_altmode_mux>; + }; + }; +}; + +&usbdp_phy0_u3 { + status = "okay"; +}; + +&usbdrd3_0 { + status = "okay"; +}; + +&usbdrd_dwc3_0 { + dr_mode = "otg"; + usb-role-switch; + + port { + #address-cells = <1>; + #size-cells = <0>; + dwc3_0_role_switch: endpoint@0 { + reg = <0>; + remote-endpoint = <&usbc0_role_sw>; + }; + }; +}; + +&usbdp_phy1 { + rockchip,dp-lane-mux = <2 3>; + status = "okay"; +}; + +&usbdp_phy1_u3 { + status = "okay"; +}; + +&usbdrd3_1 { + status = "okay"; +}; + +&u2phy1 { + status = "okay"; +}; + +&u2phy1_otg { + status = "okay"; +}; + +&i2c4 { + pinctrl-0 = <&i2c4m1_xfer>; + status = "okay"; + + usbc0: fusb302@22 { + compatible = "fcs,fusb302"; + reg = <0x22>; + interrupt-parent = <&gpio3>; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&usbc0_int>; + vbus-supply = <&vbus5v0_typec>; + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + usbc0_role_sw: endpoint@0 { + remote-endpoint = <&dwc3_0_role_switch>; + }; + }; + }; + + usb_con: connector { + compatible = "usb-c-connector"; + label = "USB-C"; + data-role = "dual"; + power-role = "dual"; + try-power-role = "sink"; + op-sink-microwatt = <1000000>; + sink-pdos = + ; + source-pdos = + ; + + altmodes { + #address-cells = <1>; + #size-cells = <0>; + + altmode@0 { + reg = <0>; + svid = <0xff01>; + vdo = <0xffffffff>; + }; + }; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + usbc0_orien_sw: endpoint { + remote-endpoint = <&usbdp_phy0_orientation_switch>; + }; + }; + + port@1 { + reg = <1>; + dp_altmode_mux: endpoint { + remote-endpoint = <&usbdp_phy0_dp_altmode_mux>; + }; + }; + }; + }; + }; +}; + -- cgit v1.3.1 From a6bd5bc9884eb679ba955bf043a325446f985178 Mon Sep 17 00:00:00 2001 From: Eugen Hristev Date: Mon, 29 May 2023 13:01:36 +0300 Subject: configs: rock5b-rk3588: enable USB 3.0 controller, command, gadget Enable configuration for USB 3.0 controller, the commands required, and the gadget drivers. Signed-off-by: Eugen Hristev Reviewed-by: Kever Yang --- configs/rock5b-rk3588_defconfig | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/configs/rock5b-rk3588_defconfig b/configs/rock5b-rk3588_defconfig index 85cb70bd091..7618258ac5b 100644 --- a/configs/rock5b-rk3588_defconfig +++ b/configs/rock5b-rk3588_defconfig @@ -48,9 +48,11 @@ CONFIG_SYS_SPI_U_BOOT_OFFS=0x60000 CONFIG_SPL_ATF=y CONFIG_CMD_GPIO=y CONFIG_CMD_GPT=y +CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y CONFIG_CMD_PCI=y CONFIG_CMD_USB=y +CONFIG_CMD_ROCKUSB=y # CONFIG_CMD_SETEXPR is not set CONFIG_CMD_REGULATOR=y # CONFIG_SPL_DOS_PARTITION is not set @@ -60,6 +62,7 @@ CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigne CONFIG_SPL_REGMAP=y CONFIG_SPL_SYSCON=y CONFIG_SPL_CLK=y +# CONFIG_USB_FUNCTION_FASTBOOT is not set CONFIG_ROCKCHIP_GPIO=y CONFIG_SYS_I2C_ROCKCHIP=y CONFIG_MISC=y @@ -77,6 +80,7 @@ CONFIG_GMAC_ROCKCHIP=y CONFIG_PCIE_DW_ROCKCHIP=y CONFIG_PHY_ROCKCHIP_INNO_USB2=y CONFIG_PHY_ROCKCHIP_NANENG_COMBOPHY=y +CONFIG_PHY_ROCKCHIP_USBDP=y CONFIG_SPL_PINCTRL=y CONFIG_REGULATOR_PWM=y CONFIG_PWM_ROCKCHIP=y @@ -87,10 +91,16 @@ CONFIG_SYS_NS16550_MEM32=y CONFIG_ROCKCHIP_SFC=y CONFIG_SYSRESET=y CONFIG_USB=y +CONFIG_DM_USB_GADGET=y +CONFIG_USB_XHCI_HCD=y +# CONFIG_USB_XHCI_DWC3_OF_SIMPLE is not set CONFIG_USB_EHCI_HCD=y CONFIG_USB_EHCI_GENERIC=y CONFIG_USB_OHCI_HCD=y CONFIG_USB_OHCI_GENERIC=y +CONFIG_USB_DWC3=y +CONFIG_USB_DWC3_GENERIC=y +CONFIG_SPL_USB_DWC3_GENERIC=y CONFIG_USB_HOST_ETHER=y CONFIG_USB_ETHER_ASIX=y CONFIG_USB_ETHER_ASIX88179=y @@ -99,4 +109,8 @@ CONFIG_USB_ETHER_LAN78XX=y CONFIG_USB_ETHER_MCS7830=y CONFIG_USB_ETHER_RTL8152=y CONFIG_USB_ETHER_SMSC95XX=y +CONFIG_USB_GADGET=y +CONFIG_USB_GADGET_PRODUCT_NUM=0x350b +CONFIG_USB_GADGET_DOWNLOAD=y +CONFIG_USB_FUNCTION_ROCKUSB=y CONFIG_ERRNO_STR=y -- cgit v1.3.1 From 59c255ae5f3000f9bf7f3d703415f81f721afc88 Mon Sep 17 00:00:00 2001 From: Chris Morgan Date: Mon, 15 May 2023 11:00:27 -0500 Subject: board: rockchip: Correct i2c2 pinctrl for RGxx3 The pinctrl on the Anbernic RGxx3 for the i2c2 bus does not use the default value, so explicitly define it. Fixes: 6cf6fe25370c ("board: rockchip: add Anbernic RGXX3 Series Devices") Signed-off-by: Chris Morgan Reviewed-by: Kever Yang --- arch/arm/dts/rk3566-anbernic-rgxx3-u-boot.dtsi | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm/dts/rk3566-anbernic-rgxx3-u-boot.dtsi b/arch/arm/dts/rk3566-anbernic-rgxx3-u-boot.dtsi index a18e5d1cf75..62e75223af3 100644 --- a/arch/arm/dts/rk3566-anbernic-rgxx3-u-boot.dtsi +++ b/arch/arm/dts/rk3566-anbernic-rgxx3-u-boot.dtsi @@ -47,6 +47,8 @@ }; &i2c2 { + pinctrl-0 = <&i2c2m1_xfer>; + pinctrl-names = "default"; status = "okay"; }; -- cgit v1.3.1 From 9c879516637292830b19251564547ec1f464b5bd Mon Sep 17 00:00:00 2001 From: Chris Morgan Date: Mon, 15 May 2023 11:00:28 -0500 Subject: board: rockchip: add DSI and DSI-DPHY for Anbernic RGxx3 Add support for the DSI and DSI-DPHY to U-Boot for the RGxx3. These are needed so we can send a panel ID request to determine which panel is being used. Signed-off-by: Chris Morgan Reviewed-by: Kever Yang --- arch/arm/dts/rk3566-anbernic-rgxx3-u-boot.dtsi | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/arm/dts/rk3566-anbernic-rgxx3-u-boot.dtsi b/arch/arm/dts/rk3566-anbernic-rgxx3-u-boot.dtsi index 62e75223af3..f986e1941e7 100644 --- a/arch/arm/dts/rk3566-anbernic-rgxx3-u-boot.dtsi +++ b/arch/arm/dts/rk3566-anbernic-rgxx3-u-boot.dtsi @@ -46,6 +46,14 @@ <&pmucru CLK_RTC32K_FRAC>; }; +&dsi_dphy0 { + status = "okay"; +}; + +&dsi0 { + status = "okay"; +}; + &i2c2 { pinctrl-0 = <&i2c2m1_xfer>; pinctrl-names = "default"; -- cgit v1.3.1 From b190381418c4850c5f0fb0cc43f3843f9d864ae0 Mon Sep 17 00:00:00 2001 From: Chris Morgan Date: Mon, 15 May 2023 11:00:29 -0500 Subject: board: rockchip: Add support for RG353PS to RGxx3 Add support for the RG353PS to the Anbernic RGxx3. This device is a slightly pared down version of the RG353P with no eMMC, no touchscreen, and only 1GB of RAM. Refactor board logic so that all supported devices are defined with ADC values and that future boards can be added by just defining the board values in the device array. Signed-off-by: Chris Morgan Reviewed-by: Kever Yang --- board/anbernic/rgxx3_rk3566/rgxx3-rk3566.c | 126 ++++++++++++++++++++--------- 1 file changed, 86 insertions(+), 40 deletions(-) diff --git a/board/anbernic/rgxx3_rk3566/rgxx3-rk3566.c b/board/anbernic/rgxx3_rk3566/rgxx3-rk3566.c index decc46db78e..4d3c724b9c2 100644 --- a/board/anbernic/rgxx3_rk3566/rgxx3-rk3566.c +++ b/board/anbernic/rgxx3_rk3566/rgxx3-rk3566.c @@ -7,24 +7,30 @@ #include #include #include +#include +#include +#include #include +#include #include #include #include -#include -#include #define GPIO0_BASE 0xfdd60000 +#define GPIO_SWPORT_DR_L 0x0000 #define GPIO_SWPORT_DR_H 0x0004 +#define GPIO_SWPORT_DDR_L 0x0008 #define GPIO_SWPORT_DDR_H 0x000c -#define GPIO_A5 BIT(5) -#define GPIO_A6 BIT(6) +#define GPIO_C5 BIT(5) +#define GPIO_C6 BIT(6) +#define GPIO_C7 BIT(7) #define GPIO_WRITEMASK(bits) ((bits) << 16) #define DTB_DIR "rockchip/" struct rg3xx_model { + const u16 adc_value; const char *board; const char *board_name; const char *fdtfile; @@ -34,49 +40,64 @@ enum rgxx3_device_id { RG353M, RG353P, RG353V, - RG353VS, RG503, + /* Devices with duplicate ADC value */ + RG353PS, + RG353VS, }; static const struct rg3xx_model rg3xx_model_details[] = { [RG353M] = { + 517, /* Observed average from device */ "rk3566-anbernic-rg353m", "RG353M", - DTB_DIR "rk3566-anbernic-rg353m.dtb", + DTB_DIR "rk3566-anbernic-rg353p.dtb", /* Identical devices */ }, [RG353P] = { + 860, /* Documented value of 860 */ "rk3566-anbernic-rg353p", "RG353P", DTB_DIR "rk3566-anbernic-rg353p.dtb", }, [RG353V] = { + 695, /* Observed average from device */ "rk3566-anbernic-rg353v", "RG353V", DTB_DIR "rk3566-anbernic-rg353v.dtb", }, - [RG353VS] = { - "rk3566-anbernic-rg353vs", - "RG353VS", - DTB_DIR "rk3566-anbernic-rg353vs.dtb", - }, [RG503] = { + 1023, /* Observed average from device */ "rk3566-anbernic-rg503", "RG503", DTB_DIR "rk3566-anbernic-rg503.dtb", }, + /* Devices with duplicate ADC value */ + [RG353PS] = { + 860, /* Observed average from device */ + "rk3566-anbernic-rg353ps", + "RG353PS", + DTB_DIR "rk3566-anbernic-rg353ps.dtb", + }, + [RG353VS] = { + 695, /* Gathered from second hand information */ + "rk3566-anbernic-rg353vs", + "RG353VS", + DTB_DIR "rk3566-anbernic-rg353vs.dtb", + }, }; /* * Start LED very early so user knows device is on. Set color - * to amber. + * to red. */ void spl_board_init(void) { - /* Set GPIO0_A5 and GPIO0_A6 to output. */ - writel(GPIO_WRITEMASK(GPIO_A6 | GPIO_A5) | (GPIO_A6 | GPIO_A5), + /* Set GPIO0_C5, GPIO0_C6, and GPIO0_C7 to output. */ + writel(GPIO_WRITEMASK(GPIO_C7 | GPIO_C6 | GPIO_C5) | \ + (GPIO_C7 | GPIO_C6 | GPIO_C5), (GPIO0_BASE + GPIO_SWPORT_DDR_H)); - /* Set GPIO0_A5 to 0 and GPIO0_A6 to 1. */ - writel(GPIO_WRITEMASK(GPIO_A6 | GPIO_A5) | GPIO_A6, + /* Set GPIO0_C5 and GPIO_C6 to 0 and GPIO0_C7 to 1. */ + writel(GPIO_WRITEMASK(GPIO_C7 | GPIO_C6 | GPIO_C5) | GPIO_C7, (GPIO0_BASE + GPIO_SWPORT_DR_H)); } @@ -129,12 +150,12 @@ void __maybe_unused startup_buzz(void) /* Detect which Anbernic RGXX3 device we are using so as to load the * correct devicetree for Linux. Set an environment variable once * found. The detection depends on the value of ADC channel 1, the - * presence of an eMMC on mmc0, and querying the DSI panel (TODO). + * presence of an eMMC on mmc0, and querying the DSI panel. */ int rgxx3_detect_device(void) { u32 adc_info; - int ret; + int ret, i; int board_id = -ENXIO; struct mmc *mmc; @@ -144,30 +165,37 @@ int rgxx3_detect_device(void) return ret; } - /* Observed value 517. */ - if (adc_info > 505 && adc_info < 530) - board_id = RG353M; - /* Observed value 695. */ - if (adc_info > 680 && adc_info < 710) - board_id = RG353V; - /* Documented value 860. */ - if (adc_info > 850 && adc_info < 870) - board_id = RG353P; - /* Observed value 1023. */ - if (adc_info > 1010) - board_id = RG503; + /* + * Get the correct device from the table. The ADC value is + * determined by a resistor on ADC channel 0. The hardware + * design calls for no more than a 1% variance on the + * resistor, so assume a +- value of 15 should be enough. + */ + for (i = 0; i < ARRAY_SIZE(rg3xx_model_details); i++) { + u32 adc_min = rg3xx_model_details[i].adc_value - 15; + u32 adc_max = rg3xx_model_details[i].adc_value + 15; + + if (adc_min < adc_info && adc_max > adc_info) { + board_id = i; + break; + } + } /* - * Try to access the eMMC on an RG353V. If it's missing, it's - * an RG353VS. Note we could also check for a touchscreen at - * 0x1a on i2c2. + * Try to access the eMMC on an RG353V or RG353P. If it's + * missing, it's an RG353VS or RG353PS. Note we could also + * check for a touchscreen at 0x1a on i2c2. */ - if (board_id == RG353V) { + if (board_id == RG353V || board_id == RG353P) { mmc = find_mmc_device(0); if (mmc) { ret = mmc_init(mmc); - if (ret) - board_id = RG353VS; + if (ret) { + if (board_id == RG353V) + board_id = RG353VS; + else + board_id = RG353PS; + } } } @@ -186,18 +214,36 @@ int rk_board_late_init(void) { int ret; - /* Turn off orange LED and turn on green LED. */ - writel(GPIO_WRITEMASK(GPIO_A6 | GPIO_A5) | GPIO_A5, - (GPIO0_BASE + GPIO_SWPORT_DR_H)); - ret = rgxx3_detect_device(); if (ret) { printf("Unable to detect device type: %d\n", ret); return ret; } + /* Turn off red LED and turn on orange LED. */ + writel(GPIO_WRITEMASK(GPIO_C7 | GPIO_C6 | GPIO_C5) | GPIO_C6, + (GPIO0_BASE + GPIO_SWPORT_DR_H)); + if (IS_ENABLED(CONFIG_DM_PWM)) startup_buzz(); return 0; } + +int ft_board_setup(void *blob, struct bd_info *bd) +{ + char *env; + + /* No fixups necessary for the RG503 */ + env = env_get("board_name"); + if (env && (!strcmp(env, rg3xx_model_details[RG503].board_name))) + return 0; + + /* Change the model name of the RG353M */ + if (env && (!strcmp(env, rg3xx_model_details[RG353M].board_name))) + fdt_setprop(blob, 0, "model", + rg3xx_model_details[RG353M].board_name, + sizeof(rg3xx_model_details[RG353M].board_name)); + + return 0; +} -- cgit v1.3.1 From ff27afedff95f25bcd3c3ce90a4f35ea16b37e55 Mon Sep 17 00:00:00 2001 From: Chris Morgan Date: Mon, 15 May 2023 11:00:30 -0500 Subject: board: rockchip: Add panel auto-detection for Anbernic RGxx3 Add support to automatically detect the panel for the Anbernic RGxx3. This is done by creating a "pseudo driver" that provides only the bare minimum to start the DSI controller and DSI DPHY. Once started, we then can query the panel for its panel ID and compare it to a table of known values. The panel compatible string (which corresponds to the upstream Linux driver) is then defined as an environment variable "panel". The panel compatible string is also changed automatically via an ft_board_setup() call if what is detected differs from what is in the loaded tree. This way, end users can use the same bootloader without having to worry about which panel they have (as there is no obvious way of knowing). Signed-off-by: Chris Morgan Reviewed-by: Kever Yang --- board/anbernic/rgxx3_rk3566/rgxx3-rk3566.c | 196 +++++++++++++++++++++++++++++ 1 file changed, 196 insertions(+) diff --git a/board/anbernic/rgxx3_rk3566/rgxx3-rk3566.c b/board/anbernic/rgxx3_rk3566/rgxx3-rk3566.c index 4d3c724b9c2..3f1a42d1844 100644 --- a/board/anbernic/rgxx3_rk3566/rgxx3-rk3566.c +++ b/board/anbernic/rgxx3_rk3566/rgxx3-rk3566.c @@ -6,21 +6,27 @@ #include #include #include +#include #include #include #include #include #include +#include #include +#include #include #include #include +#include #define GPIO0_BASE 0xfdd60000 +#define GPIO4_BASE 0xfe770000 #define GPIO_SWPORT_DR_L 0x0000 #define GPIO_SWPORT_DR_H 0x0004 #define GPIO_SWPORT_DDR_L 0x0008 #define GPIO_SWPORT_DDR_H 0x000c +#define GPIO_A0 BIT(0) #define GPIO_C5 BIT(5) #define GPIO_C6 BIT(6) #define GPIO_C7 BIT(7) @@ -86,6 +92,16 @@ static const struct rg3xx_model rg3xx_model_details[] = { }, }; +struct rg353_panel { + const u16 id; + const char *panel_compat; +}; + +static const struct rg353_panel rg353_panel_details[] = { + { .id = 0x3052, .panel_compat = "newvision,nv3051d"}, + { .id = 0x3821, .panel_compat = "anbernic,rg353v-panel-v2"}, +}; + /* * Start LED very early so user knows device is on. Set color * to red. @@ -147,6 +163,150 @@ void __maybe_unused startup_buzz(void) pwm_set_enable(dev, 0, 0); } +/* + * Provide the bare minimum to identify the panel for the RG353 + * series. Since we don't have a working framebuffer device, no + * need to init the panel; just identify it and provide the + * clocks so we know what to set the different clock values to. + */ + +static const struct display_timing rg353_default_timing = { + .pixelclock.typ = 24150000, + .hactive.typ = 640, + .hfront_porch.typ = 40, + .hback_porch.typ = 80, + .hsync_len.typ = 2, + .vactive.typ = 480, + .vfront_porch.typ = 18, + .vback_porch.typ = 28, + .vsync_len.typ = 2, + .flags = DISPLAY_FLAGS_HSYNC_HIGH | + DISPLAY_FLAGS_VSYNC_HIGH, +}; + +static int anbernic_rg353_panel_get_timing(struct udevice *dev, + struct display_timing *timings) +{ + memcpy(timings, &rg353_default_timing, sizeof(*timings)); + + return 0; +} + +static int anbernic_rg353_panel_probe(struct udevice *dev) +{ + struct mipi_dsi_panel_plat *plat = dev_get_plat(dev); + + plat->lanes = 4; + plat->format = MIPI_DSI_FMT_RGB888; + plat->mode_flags = MIPI_DSI_MODE_VIDEO | + MIPI_DSI_MODE_VIDEO_BURST | + MIPI_DSI_MODE_EOT_PACKET | + MIPI_DSI_MODE_LPM; + + return 0; +} + +static const struct panel_ops anbernic_rg353_panel_ops = { + .get_display_timing = anbernic_rg353_panel_get_timing, +}; + +U_BOOT_DRIVER(anbernic_rg353_panel) = { + .name = "anbernic_rg353_panel", + .id = UCLASS_PANEL, + .ops = &anbernic_rg353_panel_ops, + .probe = anbernic_rg353_panel_probe, + .plat_auto = sizeof(struct mipi_dsi_panel_plat), +}; + +int rgxx3_detect_display(void) +{ + struct udevice *dev; + struct mipi_dsi_device *dsi; + struct mipi_dsi_panel_plat *mplat; + const struct rg353_panel *panel; + int ret = 0; + int i; + u8 panel_id[2]; + + /* + * Take panel out of reset status. + * Set GPIO4_A0 to output. + */ + writel(GPIO_WRITEMASK(GPIO_A0) | GPIO_A0, + (GPIO4_BASE + GPIO_SWPORT_DDR_L)); + /* Set GPIO4_A0 to 1. */ + writel(GPIO_WRITEMASK(GPIO_A0) | GPIO_A0, + (GPIO4_BASE + GPIO_SWPORT_DR_L)); + + /* Probe the DSI controller. */ + ret = uclass_get_device_by_name(UCLASS_VIDEO_BRIDGE, + "dsi@fe060000", &dev); + if (ret) { + printf("DSI host not probed: %d\n", ret); + return ret; + } + + /* Probe the DSI panel. */ + ret = device_bind_driver_to_node(dev, "anbernic_rg353_panel", + "anbernic_rg353_panel", + dev_ofnode(dev), NULL); + if (ret) { + printf("Failed to probe RG353 panel: %d\n", ret); + return ret; + } + + /* + * Attach the DSI controller which will also probe and attach + * the DSIDPHY. + */ + ret = video_bridge_attach(dev); + if (ret) { + printf("Failed to attach DSI controller: %d\n", ret); + return ret; + } + + /* + * Get the panel which should have already been probed by the + * video_bridge_attach() function. + */ + ret = uclass_first_device_err(UCLASS_PANEL, &dev); + if (ret) { + printf("Panel device error: %d\n", ret); + return ret; + } + + /* Now call the panel via DSI commands to get the panel ID. */ + mplat = dev_get_plat(dev); + dsi = mplat->device; + mipi_dsi_set_maximum_return_packet_size(dsi, sizeof(panel_id)); + ret = mipi_dsi_dcs_read(dsi, MIPI_DCS_GET_DISPLAY_ID, &panel_id, + sizeof(panel_id)); + if (ret < 0) { + printf("Unable to read panel ID: %d\n", ret); + return ret; + } + + /* Get the correct panel compatible from the table. */ + for (i = 0; i < ARRAY_SIZE(rg353_panel_details); i++) { + if (rg353_panel_details[i].id == ((panel_id[0] << 8) | + panel_id[1])) { + panel = &rg353_panel_details[i]; + break; + } + } + + if (!panel) { + printf("Unable to identify panel_id %x\n", + (panel_id[0] << 8) | panel_id[1]); + env_set("panel", "unknown"); + return -EINVAL; + } + + env_set("panel", panel->panel_compat); + + return 0; +} + /* Detect which Anbernic RGXX3 device we are using so as to load the * correct devicetree for Linux. Set an environment variable once * found. The detection depends on the value of ADC channel 1, the @@ -207,6 +367,14 @@ int rgxx3_detect_device(void) rg3xx_model_details[board_id].board_name); env_set("fdtfile", rg3xx_model_details[board_id].fdtfile); + /* Detect the panel type for any device that isn't a 503. */ + if (board_id == RG503) + return 0; + + ret = rgxx3_detect_display(); + if (ret) + return ret; + return 0; } @@ -232,6 +400,7 @@ int rk_board_late_init(void) int ft_board_setup(void *blob, struct bd_info *bd) { + int node, ret; char *env; /* No fixups necessary for the RG503 */ @@ -245,5 +414,32 @@ int ft_board_setup(void *blob, struct bd_info *bd) rg3xx_model_details[RG353M].board_name, sizeof(rg3xx_model_details[RG353M].board_name)); + /* + * Check if the environment variable doesn't equal the panel. + * If it doesn't, update the devicetree to the correct panel. + */ + node = fdt_path_offset(blob, "/dsi@fe060000/panel@0"); + if (!(node > 0)) { + printf("Can't find the DSI node\n"); + return -ENODEV; + } + + env = env_get("panel"); + if (!env) { + printf("Can't get panel env\n"); + return -ENODEV; + } + + ret = fdt_node_check_compatible(blob, node, env); + if (ret < 0) + return -ENODEV; + + /* Panels match, return 0. */ + if (!ret) + return 0; + + do_fixup_by_path_string(blob, "/dsi@fe060000/panel@0", + "compatible", env); + return 0; } -- cgit v1.3.1 From 12b715bd4f7847358b2d3f6d454e0f8136c9be12 Mon Sep 17 00:00:00 2001 From: Chris Morgan Date: Mon, 15 May 2023 11:00:31 -0500 Subject: configs: Update anbernic-rgxx3_defconfig for panel detection Update the anbernic-rgxx3_defconfig file to support panel autodetection and automatically updating the compatible string in the devicetree. Signed-off-by: Chris Morgan Reviewed-by: Kever Yang --- configs/anbernic-rgxx3_defconfig | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/configs/anbernic-rgxx3_defconfig b/configs/anbernic-rgxx3_defconfig index b17e9179148..ed6643d9d4f 100644 --- a/configs/anbernic-rgxx3_defconfig +++ b/configs/anbernic-rgxx3_defconfig @@ -12,6 +12,7 @@ CONFIG_DEFAULT_DEVICE_TREE="rk3566-anbernic-rgxx3" CONFIG_ROCKCHIP_RK3568=y CONFIG_SPL_ROCKCHIP_BACK_TO_BROM=y CONFIG_SPL_ROCKCHIP_COMMON_BOARD=y +CONFIG_ROCKCHIP_RK8XX_DISABLE_BOOT_ON_POWERON=y CONFIG_SPL_MMC=y CONFIG_SPL_SERIAL=y CONFIG_SPL_STACK_R_ADDR=0x600000 @@ -24,9 +25,13 @@ CONFIG_DEBUG_UART=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_SPL_LOAD_FIT=y +CONFIG_OF_BOARD_SETUP=y +CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_DEFAULT_FDT_FILE="rockchip/rk3566-anbernic-rgxx3.dtb" +# CONFIG_CONSOLE_MUX is not set # CONFIG_DISPLAY_CPUINFO is not set CONFIG_DISPLAY_BOARDINFO_LATE=y +CONFIG_BOARD_RNG_SEED=y CONFIG_SPL_MAX_SIZE=0x20000 CONFIG_SPL_PAD_TO=0x7f8000 CONFIG_SPL_HAS_BSS_LINKER_SECTION=y @@ -41,6 +46,7 @@ CONFIG_CMD_PWM=y CONFIG_CMD_GPT=y CONFIG_CMD_MMC=y # CONFIG_CMD_SETEXPR is not set +# CONFIG_CMD_CLS is not set # CONFIG_SPL_DOS_PARTITION is not set CONFIG_SPL_OF_CONTROL=y CONFIG_OF_LIVE=y @@ -60,6 +66,7 @@ CONFIG_MMC_DW_ROCKCHIP=y CONFIG_MMC_SDHCI=y CONFIG_MMC_SDHCI_SDMA=y CONFIG_MMC_SDHCI_ROCKCHIP=y +CONFIG_PHY_ROCKCHIP_INNO_DSIDPHY=y CONFIG_DM_PMIC=y CONFIG_DM_PMIC_FAN53555=y CONFIG_PMIC_RK8XX=y @@ -69,10 +76,18 @@ CONFIG_REGULATOR_RK8XX=y CONFIG_DM_REGULATOR_SCMI=y CONFIG_PWM_ROCKCHIP=y CONFIG_SPL_RAM=y +# CONFIG_RAM_ROCKCHIP_DEBUG is not set +CONFIG_DM_RNG=y +CONFIG_RNG_ROCKCHIP=y +# CONFIG_RNG_SMCCC_TRNG is not set CONFIG_BAUDRATE=1500000 CONFIG_DEBUG_UART_SHIFT=2 CONFIG_SYS_NS16550_MEM32=y CONFIG_SYSRESET=y +CONFIG_VIDEO=y +CONFIG_VIDEO_ROCKCHIP=y +CONFIG_DISPLAY_ROCKCHIP_DW_MIPI=y +CONFIG_VIDEO_BRIDGE=y CONFIG_REGEX=y CONFIG_ERRNO_STR=y # CONFIG_EFI_LOADER is not set -- cgit v1.3.1 From 182d0ba6d6fe2155571babcc7b09f7a838e00e92 Mon Sep 17 00:00:00 2001 From: Chris Morgan Date: Mon, 15 May 2023 11:00:32 -0500 Subject: doc: anbernic: Update RGxx3 Docs for panel detection Update the Anbernic RGxx3 documentation to note that panel detection has been added and how it works. Signed-off-by: Chris Morgan Reviewed-by: Kever Yang --- doc/board/anbernic/rgxx3.rst | 31 ++++++++++++++++++++----------- 1 file changed, 20 insertions(+), 11 deletions(-) diff --git a/doc/board/anbernic/rgxx3.rst b/doc/board/anbernic/rgxx3.rst index afa7538282f..7d1beb423ce 100644 --- a/doc/board/anbernic/rgxx3.rst +++ b/doc/board/anbernic/rgxx3.rst @@ -7,27 +7,36 @@ This allows U-Boot to boot the following Anbernic devices: - Anbernic RG353M - Anbernic RG353P + - Anbernic RG353PS - Anbernic RG353V - Anbernic RG353VS - Anbernic RG503 The correct device is detected automatically by comparing ADC values -from ADC channel 1. In the event of an RG353V, an attempt is then made -to probe for an eMMC and if it fails the device is assumed to be an -RG353VS. Based on the detected device, the environment variables -"board", "board_name", and "fdtfile" are set to the correct values -corresponding to the board which can be read by a boot script to boot -with the correct device tree. - -Please note that there are some versions of the RG353 devices with -different panels. Panel auto-detection is planned for a later date. +from ADC channel 1. In the event of an RG353V or RG353P, an attempt +is then made to probe for an eMMC and if it fails the device is assumed +to be an RG353VS or RG353PS. Based on the detected device, the +environment variables "board", "board_name", and "fdtfile" are set to +the correct values corresponding to the board which can be read by a +boot script to boot with the correct device tree. If the board detected +is not of type RG503 (which currently has only 1 panel revision) a +panel detect is then performed by probing a "dummy" display on the DSI +bus and then querying the display ID. The display ID is then compared +to a table to get the known compatible string for use in Linux, and +this string is saved as an environment variable of "panel". + +FDT fixups are performed in the event of an RG353M to change the device +name, or in the event the panel detected does not match the devicetree. +This allows Linux to load the correct panel driver without having to +know exactly which panel is used (as there is no user distingushable +way to tell). Building U-Boot --------------- .. code-block:: bash - $ export CROSS_COMPILE=aarch64-none-elf- + $ export CROSS_COMPILE=aarch64-linux-gnu- $ export BL31=../rkbin/bin/rk35/rk3568_bl31_v1.34.elf $ export ROCKCHIP_TPL=../rkbin/bin/rk35/rk3568_ddr_1056MHz_v1.13.bin $ make anbernic-rgxx3_defconfig @@ -40,7 +49,7 @@ Image installation ------------------ Write the ``u-boot-rockchip.bin`` to an SD card offset 32kb from the -start. +start. Please note that eMMC booting has not been tested at this time. .. code-block:: bash -- cgit v1.3.1 From 69e16c7b1cdd03907b86bb31abee24f5d4836400 Mon Sep 17 00:00:00 2001 From: Tianling Shen Date: Sat, 20 May 2023 19:20:49 +0800 Subject: rockchip: rk3328: Add support for Orange Pi R1 Plus Orange Pi R1 Plus is a Rockchip RK3328 based SBC by Xunlong. This device is similar to the NanoPi R2S, and has a 16MB SPI NOR (mx25l12805d). The reset button is changed to directly reset the power supply, another detail is that both network ports have independent MAC addresses. The device tree and description are taken from kernel v6.3-rc1. Reviewed-by: Kever Yang Signed-off-by: Tianling Shen --- arch/arm/dts/Makefile | 1 + arch/arm/dts/rk3328-orangepi-r1-plus-u-boot.dtsi | 46 +++ arch/arm/dts/rk3328-orangepi-r1-plus.dts | 373 +++++++++++++++++++++++ board/rockchip/evb_rk3328/MAINTAINERS | 6 + configs/orangepi-r1-plus-rk3328_defconfig | 114 +++++++ 5 files changed, 540 insertions(+) create mode 100644 arch/arm/dts/rk3328-orangepi-r1-plus-u-boot.dtsi create mode 100644 arch/arm/dts/rk3328-orangepi-r1-plus.dts create mode 100644 configs/orangepi-r1-plus-rk3328_defconfig diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index b7780de776b..0cd2c86fdb5 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -125,6 +125,7 @@ dtb-$(CONFIG_ROCKCHIP_RK3328) += \ rk3328-evb.dtb \ rk3328-nanopi-r2c.dtb \ rk3328-nanopi-r2s.dtb \ + rk3328-orangepi-r1-plus.dtb \ rk3328-roc-cc.dtb \ rk3328-rock64.dtb \ rk3328-rock-pi-e.dtb diff --git a/arch/arm/dts/rk3328-orangepi-r1-plus-u-boot.dtsi b/arch/arm/dts/rk3328-orangepi-r1-plus-u-boot.dtsi new file mode 100644 index 00000000000..637c70adf19 --- /dev/null +++ b/arch/arm/dts/rk3328-orangepi-r1-plus-u-boot.dtsi @@ -0,0 +1,46 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * (C) Copyright 2018-2019 Rockchip Electronics Co., Ltd + * (C) Copyright 2020 David Bauer + */ + +#include "rk3328-u-boot.dtsi" +#include "rk3328-sdram-ddr4-666.dtsi" +/ { + chosen { + u-boot,spl-boot-order = "same-as-spl", &sdmmc, &emmc; + }; +}; + +&gpio0 { + bootph-pre-ram; +}; + +&pinctrl { + bootph-pre-ram; +}; + +&sdmmc0m1_pin { + bootph-pre-ram; +}; + +&pcfg_pull_up_4ma { + bootph-pre-ram; +}; + +/* Need this and all the pinctrl/gpio stuff above to set pinmux */ +&vcc_sd { + bootph-pre-ram; +}; + +&gmac2io { + snps,reset-gpio = <&gpio1 RK_PC2 GPIO_ACTIVE_LOW>; + snps,reset-active-low; + snps,reset-delays-us = <0 10000 50000>; +}; + +&spi0 { + spi_flash: spiflash@0 { + bootph-all; + }; +}; diff --git a/arch/arm/dts/rk3328-orangepi-r1-plus.dts b/arch/arm/dts/rk3328-orangepi-r1-plus.dts new file mode 100644 index 00000000000..dc83d74045a --- /dev/null +++ b/arch/arm/dts/rk3328-orangepi-r1-plus.dts @@ -0,0 +1,373 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Based on rk3328-nanopi-r2s.dts, which is: + * Copyright (c) 2020 David Bauer + */ + +/dts-v1/; + +#include +#include +#include "rk3328.dtsi" + +/ { + model = "Xunlong Orange Pi R1 Plus"; + compatible = "xunlong,orangepi-r1-plus", "rockchip,rk3328"; + + aliases { + ethernet1 = &rtl8153; + mmc0 = &sdmmc; + }; + + chosen { + stdout-path = "serial2:1500000n8"; + }; + + gmac_clk: gmac-clock { + compatible = "fixed-clock"; + clock-frequency = <125000000>; + clock-output-names = "gmac_clkin"; + #clock-cells = <0>; + }; + + leds { + compatible = "gpio-leds"; + pinctrl-0 = <&lan_led_pin>, <&sys_led_pin>, <&wan_led_pin>; + pinctrl-names = "default"; + + led-0 { + function = LED_FUNCTION_LAN; + color = ; + gpios = <&gpio2 RK_PB7 GPIO_ACTIVE_HIGH>; + }; + + led-1 { + function = LED_FUNCTION_STATUS; + color = ; + gpios = <&gpio3 RK_PC5 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "heartbeat"; + }; + + led-2 { + function = LED_FUNCTION_WAN; + color = ; + gpios = <&gpio2 RK_PC2 GPIO_ACTIVE_HIGH>; + }; + }; + + vcc_sd: sdmmc-regulator { + compatible = "regulator-fixed"; + gpio = <&gpio0 RK_PD6 GPIO_ACTIVE_LOW>; + pinctrl-0 = <&sdmmc0m1_pin>; + pinctrl-names = "default"; + regulator-name = "vcc_sd"; + regulator-boot-on; + vin-supply = <&vcc_io>; + }; + + vcc_sys: vcc-sys-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + }; + + vdd_5v_lan: vdd-5v-lan-regulator { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio2 RK_PC6 GPIO_ACTIVE_HIGH>; + pinctrl-0 = <&lan_vdd_pin>; + pinctrl-names = "default"; + regulator-name = "vdd_5v_lan"; + regulator-always-on; + regulator-boot-on; + vin-supply = <&vcc_sys>; + }; +}; + +&cpu0 { + cpu-supply = <&vdd_arm>; +}; + +&cpu1 { + cpu-supply = <&vdd_arm>; +}; + +&cpu2 { + cpu-supply = <&vdd_arm>; +}; + +&cpu3 { + cpu-supply = <&vdd_arm>; +}; + +&display_subsystem { + status = "disabled"; +}; + +&gmac2io { + assigned-clocks = <&cru SCLK_MAC2IO>, <&cru SCLK_MAC2IO_EXT>; + assigned-clock-parents = <&gmac_clk>, <&gmac_clk>; + clock_in_out = "input"; + phy-handle = <&rtl8211e>; + phy-mode = "rgmii"; + phy-supply = <&vcc_io>; + pinctrl-0 = <&rgmiim1_pins>; + pinctrl-names = "default"; + snps,aal; + rx_delay = <0x18>; + tx_delay = <0x24>; + status = "okay"; + + mdio { + compatible = "snps,dwmac-mdio"; + #address-cells = <1>; + #size-cells = <0>; + + rtl8211e: ethernet-phy@1 { + reg = <1>; + pinctrl-0 = <ð_phy_reset_pin>; + pinctrl-names = "default"; + reset-assert-us = <10000>; + reset-deassert-us = <50000>; + reset-gpios = <&gpio1 RK_PC2 GPIO_ACTIVE_LOW>; + }; + }; +}; + +&i2c1 { + status = "okay"; + + rk805: pmic@18 { + compatible = "rockchip,rk805"; + reg = <0x18>; + interrupt-parent = <&gpio1>; + interrupts = <24 IRQ_TYPE_LEVEL_LOW>; + #clock-cells = <1>; + clock-output-names = "xin32k", "rk805-clkout2"; + gpio-controller; + #gpio-cells = <2>; + pinctrl-0 = <&pmic_int_l>; + pinctrl-names = "default"; + rockchip,system-power-controller; + wakeup-source; + + vcc1-supply = <&vcc_sys>; + vcc2-supply = <&vcc_sys>; + vcc3-supply = <&vcc_sys>; + vcc4-supply = <&vcc_sys>; + vcc5-supply = <&vcc_io>; + vcc6-supply = <&vcc_sys>; + + regulators { + vdd_log: DCDC_REG1 { + regulator-name = "vdd_log"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <712500>; + regulator-max-microvolt = <1450000>; + regulator-ramp-delay = <12500>; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1000000>; + }; + }; + + vdd_arm: DCDC_REG2 { + regulator-name = "vdd_arm"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <712500>; + regulator-max-microvolt = <1450000>; + regulator-ramp-delay = <12500>; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <950000>; + }; + }; + + vcc_ddr: DCDC_REG3 { + regulator-name = "vcc_ddr"; + regulator-always-on; + regulator-boot-on; + + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + vcc_io: DCDC_REG4 { + regulator-name = "vcc_io"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3300000>; + }; + }; + + vcc_18: LDO_REG1 { + regulator-name = "vcc_18"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vcc18_emmc: LDO_REG2 { + regulator-name = "vcc18_emmc"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vdd_10: LDO_REG3 { + regulator-name = "vdd_10"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1000000>; + }; + }; + }; + }; +}; + +&io_domains { + pmuio-supply = <&vcc_io>; + vccio1-supply = <&vcc_io>; + vccio2-supply = <&vcc18_emmc>; + vccio3-supply = <&vcc_io>; + vccio4-supply = <&vcc_io>; + vccio5-supply = <&vcc_io>; + vccio6-supply = <&vcc_io>; + status = "okay"; +}; + +&pinctrl { + gmac2io { + eth_phy_reset_pin: eth-phy-reset-pin { + rockchip,pins = <1 RK_PC2 RK_FUNC_GPIO &pcfg_pull_down>; + }; + }; + + leds { + lan_led_pin: lan-led-pin { + rockchip,pins = <2 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + sys_led_pin: sys-led-pin { + rockchip,pins = <3 RK_PC5 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + wan_led_pin: wan-led-pin { + rockchip,pins = <2 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + lan { + lan_vdd_pin: lan-vdd-pin { + rockchip,pins = <2 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + pmic { + pmic_int_l: pmic-int-l { + rockchip,pins = <1 RK_PD0 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; +}; + +&pwm2 { + status = "okay"; +}; + +&sdmmc { + bus-width = <4>; + cap-sd-highspeed; + disable-wp; + pinctrl-0 = <&sdmmc0_clk>, <&sdmmc0_cmd>, <&sdmmc0_dectn>, <&sdmmc0_bus4>; + pinctrl-names = "default"; + vmmc-supply = <&vcc_sd>; + status = "okay"; +}; + +&spi0 { + status = "okay"; + + flash@0 { + compatible = "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <50000000>; + }; +}; + +&tsadc { + rockchip,hw-tshut-mode = <0>; + rockchip,hw-tshut-polarity = <0>; + status = "okay"; +}; + +&u2phy { + status = "okay"; +}; + +&u2phy_host { + status = "okay"; +}; + +&u2phy_otg { + status = "okay"; +}; + +&uart2 { + status = "okay"; +}; + +&usb20_otg { + dr_mode = "host"; + status = "okay"; +}; + +&usbdrd3 { + dr_mode = "host"; + status = "okay"; + #address-cells = <1>; + #size-cells = <0>; + + /* Second port is for USB 3.0 */ + rtl8153: device@2 { + compatible = "usbbda,8153"; + reg = <2>; + }; +}; + +&usb_host0_ehci { + status = "okay"; +}; + +&usb_host0_ohci { + status = "okay"; +}; diff --git a/board/rockchip/evb_rk3328/MAINTAINERS b/board/rockchip/evb_rk3328/MAINTAINERS index 3c46613ab58..91dc6b58cf0 100644 --- a/board/rockchip/evb_rk3328/MAINTAINERS +++ b/board/rockchip/evb_rk3328/MAINTAINERS @@ -18,6 +18,12 @@ F: configs/nanopi-r2s-rk3328_defconfig F: arch/arm/dts/rk3328-nanopi-r2s-u-boot.dtsi F: arch/arm/dts/rk3328-nanopi-r2s.dts +ORANGEPI-R1-PLUS-RK3328 +M: Tianling Shen +S: Maintained +F: configs/orangepi-r1-plus-rk3328_defconfig +F: arch/arm/dts/rk3328-orangepi-r1-plus-u-boot.dtsi + ROC-RK3328-CC M: Loic Devulder M: Chen-Yu Tsai diff --git a/configs/orangepi-r1-plus-rk3328_defconfig b/configs/orangepi-r1-plus-rk3328_defconfig new file mode 100644 index 00000000000..3f62f0588d7 --- /dev/null +++ b/configs/orangepi-r1-plus-rk3328_defconfig @@ -0,0 +1,114 @@ +CONFIG_ARM=y +CONFIG_SKIP_LOWLEVEL_INIT=y +CONFIG_COUNTER_FREQUENCY=24000000 +CONFIG_ARCH_ROCKCHIP=y +CONFIG_TEXT_BASE=0x00200000 +CONFIG_SPL_GPIO=y +CONFIG_NR_DRAM_BANKS=1 +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x300000 +CONFIG_ENV_OFFSET=0x3F8000 +CONFIG_DEFAULT_DEVICE_TREE="rk3328-orangepi-r1-plus" +CONFIG_DM_RESET=y +CONFIG_ROCKCHIP_RK3328=y +CONFIG_TPL_ROCKCHIP_COMMON_BOARD=y +CONFIG_TPL_LIBCOMMON_SUPPORT=y +CONFIG_TPL_LIBGENERIC_SUPPORT=y +CONFIG_SPL_DRIVERS_MISC=y +CONFIG_SPL_STACK_R_ADDR=0x600000 +CONFIG_SPL_STACK=0x400000 +CONFIG_TPL_SYS_MALLOC_F_LEN=0x800 +CONFIG_DEBUG_UART_BASE=0xFF130000 +CONFIG_DEBUG_UART_CLOCK=24000000 +CONFIG_SYS_LOAD_ADDR=0x800800 +CONFIG_DEBUG_UART=y +# CONFIG_ANDROID_BOOT_IMAGE is not set +CONFIG_FIT=y +CONFIG_FIT_VERBOSE=y +CONFIG_SPL_LOAD_FIT=y +CONFIG_DEFAULT_FDT_FILE="rockchip/rk3328-orangepi-r1-plus.dtb" +# CONFIG_DISPLAY_CPUINFO is not set +CONFIG_DISPLAY_BOARDINFO_LATE=y +CONFIG_MISC_INIT_R=y +CONFIG_SPL_MAX_SIZE=0x40000 +CONFIG_SPL_PAD_TO=0x7f8000 +CONFIG_SPL_HAS_BSS_LINKER_SECTION=y +CONFIG_SPL_BSS_START_ADDR=0x2000000 +CONFIG_SPL_BSS_MAX_SIZE=0x2000 +# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set +# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set +CONFIG_SPL_STACK_R=y +CONFIG_SPL_I2C=y +CONFIG_SPL_POWER=y +CONFIG_SPL_ATF=y +CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y +CONFIG_TPL_SYS_MALLOC_SIMPLE=y +CONFIG_CMD_BOOTZ=y +CONFIG_CMD_GPT=y +CONFIG_CMD_MMC=y +CONFIG_CMD_USB=y +# CONFIG_CMD_SETEXPR is not set +CONFIG_CMD_TIME=y +CONFIG_SPL_OF_CONTROL=y +CONFIG_TPL_OF_CONTROL=y +CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" +CONFIG_TPL_OF_PLATDATA=y +CONFIG_ENV_IS_IN_MMC=y +CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_SYS_MMC_ENV_DEV=1 +CONFIG_NET_RANDOM_ETHADDR=y +CONFIG_TPL_DM=y +CONFIG_REGMAP=y +CONFIG_SPL_REGMAP=y +CONFIG_TPL_REGMAP=y +CONFIG_SYSCON=y +CONFIG_SPL_SYSCON=y +CONFIG_TPL_SYSCON=y +CONFIG_CLK=y +CONFIG_SPL_CLK=y +CONFIG_FASTBOOT_BUF_ADDR=0x800800 +CONFIG_FASTBOOT_CMD_OEM_FORMAT=y +CONFIG_ROCKCHIP_GPIO=y +CONFIG_SYS_I2C_ROCKCHIP=y +CONFIG_MMC_DW=y +CONFIG_MMC_DW_ROCKCHIP=y +CONFIG_SF_DEFAULT_SPEED=20000000 +CONFIG_SPI_FLASH_GIGADEVICE=y +CONFIG_ETH_DESIGNWARE=y +CONFIG_GMAC_ROCKCHIP=y +CONFIG_PINCTRL=y +CONFIG_SPL_PINCTRL=y +CONFIG_DM_PMIC=y +CONFIG_PMIC_RK8XX=y +CONFIG_SPL_PMIC_RK8XX=y +CONFIG_SPL_DM_REGULATOR=y +CONFIG_REGULATOR_PWM=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_SPL_DM_REGULATOR_FIXED=y +CONFIG_REGULATOR_RK8XX=y +CONFIG_PWM_ROCKCHIP=y +CONFIG_RAM=y +CONFIG_SPL_RAM=y +CONFIG_TPL_RAM=y +CONFIG_BAUDRATE=1500000 +CONFIG_DEBUG_UART_SHIFT=2 +CONFIG_SYS_NS16550_MEM32=y +CONFIG_ROCKCHIP_SPI=y +CONFIG_SYSINFO=y +CONFIG_SYSRESET=y +# CONFIG_TPL_SYSRESET is not set +CONFIG_USB=y +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_XHCI_DWC3=y +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_EHCI_GENERIC=y +CONFIG_USB_OHCI_HCD=y +CONFIG_USB_OHCI_GENERIC=y +CONFIG_USB_DWC2=y +CONFIG_USB_DWC3=y +# CONFIG_USB_DWC3_GADGET is not set +CONFIG_USB_GADGET=y +CONFIG_USB_GADGET_DWC2_OTG=y +CONFIG_SPL_TINY_MEMSET=y +CONFIG_TPL_TINY_MEMSET=y +CONFIG_ERRNO_STR=y -- cgit v1.3.1 From 9bd954ab8a8513913bf74be06ba80a79754c7820 Mon Sep 17 00:00:00 2001 From: Tianling Shen Date: Sat, 20 May 2023 19:20:50 +0800 Subject: rockchip: rk3328: Add support for Orange Pi R1 Plus LTS The OrangePi R1 Plus LTS is a minor variant of OrangePi R1 Plus with the on-board NIC chip changed from rtl8211e to yt8531c, and RAM type changed from DDR4 to LPDDR3. The device tree is taken from kernel v6.4-rc1. Signed-off-by: Tianling Shen Reviewed-by: Kever Yang --- arch/arm/dts/Makefile | 1 + .../dts/rk3328-orangepi-r1-plus-lts-u-boot.dtsi | 46 +++++++++ arch/arm/dts/rk3328-orangepi-r1-plus-lts.dts | 40 ++++++++ board/rockchip/evb_rk3328/MAINTAINERS | 6 ++ configs/orangepi-r1-plus-lts-rk3328_defconfig | 114 +++++++++++++++++++++ 5 files changed, 207 insertions(+) create mode 100644 arch/arm/dts/rk3328-orangepi-r1-plus-lts-u-boot.dtsi create mode 100644 arch/arm/dts/rk3328-orangepi-r1-plus-lts.dts create mode 100644 configs/orangepi-r1-plus-lts-rk3328_defconfig diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index 0cd2c86fdb5..abb700e8a20 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -126,6 +126,7 @@ dtb-$(CONFIG_ROCKCHIP_RK3328) += \ rk3328-nanopi-r2c.dtb \ rk3328-nanopi-r2s.dtb \ rk3328-orangepi-r1-plus.dtb \ + rk3328-orangepi-r1-plus-lts.dtb \ rk3328-roc-cc.dtb \ rk3328-rock64.dtb \ rk3328-rock-pi-e.dtb diff --git a/arch/arm/dts/rk3328-orangepi-r1-plus-lts-u-boot.dtsi b/arch/arm/dts/rk3328-orangepi-r1-plus-lts-u-boot.dtsi new file mode 100644 index 00000000000..ebe33e48cb9 --- /dev/null +++ b/arch/arm/dts/rk3328-orangepi-r1-plus-lts-u-boot.dtsi @@ -0,0 +1,46 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * (C) Copyright 2018-2019 Rockchip Electronics Co., Ltd + * (C) Copyright 2020 David Bauer + */ + +#include "rk3328-u-boot.dtsi" +#include "rk3328-sdram-lpddr3-666.dtsi" +/ { + chosen { + u-boot,spl-boot-order = "same-as-spl", &sdmmc, &emmc; + }; +}; + +&gpio0 { + bootph-pre-ram; +}; + +&pinctrl { + bootph-pre-ram; +}; + +&sdmmc0m1_pin { + bootph-pre-ram; +}; + +&pcfg_pull_up_4ma { + bootph-pre-ram; +}; + +/* Need this and all the pinctrl/gpio stuff above to set pinmux */ +&vcc_sd { + bootph-pre-ram; +}; + +&gmac2io { + snps,reset-gpio = <&gpio1 RK_PC2 GPIO_ACTIVE_LOW>; + snps,reset-active-low; + snps,reset-delays-us = <0 10000 50000>; +}; + +&spi0 { + spi_flash: spiflash@0 { + bootph-all; + }; +}; diff --git a/arch/arm/dts/rk3328-orangepi-r1-plus-lts.dts b/arch/arm/dts/rk3328-orangepi-r1-plus-lts.dts new file mode 100644 index 00000000000..5d7d567283e --- /dev/null +++ b/arch/arm/dts/rk3328-orangepi-r1-plus-lts.dts @@ -0,0 +1,40 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Copyright (c) 2016 Xunlong Software. Co., Ltd. + * (http://www.orangepi.org) + * + * Copyright (c) 2021-2023 Tianling Shen + */ + +/dts-v1/; +#include "rk3328-orangepi-r1-plus.dts" + +/ { + model = "Xunlong Orange Pi R1 Plus LTS"; + compatible = "xunlong,orangepi-r1-plus-lts", "rockchip,rk3328"; +}; + +&gmac2io { + phy-handle = <&yt8531c>; + tx_delay = <0x19>; + rx_delay = <0x05>; + + mdio { + /delete-node/ ethernet-phy@1; + + yt8531c: ethernet-phy@0 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0>; + + motorcomm,clk-out-frequency-hz = <125000000>; + motorcomm,keep-pll-enabled; + motorcomm,auto-sleep-disabled; + + pinctrl-0 = <ð_phy_reset_pin>; + pinctrl-names = "default"; + reset-assert-us = <15000>; + reset-deassert-us = <50000>; + reset-gpios = <&gpio1 RK_PC2 GPIO_ACTIVE_LOW>; + }; + }; +}; diff --git a/board/rockchip/evb_rk3328/MAINTAINERS b/board/rockchip/evb_rk3328/MAINTAINERS index 91dc6b58cf0..8a19eb373d0 100644 --- a/board/rockchip/evb_rk3328/MAINTAINERS +++ b/board/rockchip/evb_rk3328/MAINTAINERS @@ -24,6 +24,12 @@ S: Maintained F: configs/orangepi-r1-plus-rk3328_defconfig F: arch/arm/dts/rk3328-orangepi-r1-plus-u-boot.dtsi +ORANGEPI-R1-PLUS-LTS-RK3328 +M: Tianling Shen +S: Maintained +F: configs/orangepi-r1-plus-lts-rk3328_defconfig +F: arch/arm/dts/rk3328-orangepi-r1-plus-lts-u-boot.dtsi + ROC-RK3328-CC M: Loic Devulder M: Chen-Yu Tsai diff --git a/configs/orangepi-r1-plus-lts-rk3328_defconfig b/configs/orangepi-r1-plus-lts-rk3328_defconfig new file mode 100644 index 00000000000..59a28e5209c --- /dev/null +++ b/configs/orangepi-r1-plus-lts-rk3328_defconfig @@ -0,0 +1,114 @@ +CONFIG_ARM=y +CONFIG_SKIP_LOWLEVEL_INIT=y +CONFIG_COUNTER_FREQUENCY=24000000 +CONFIG_ARCH_ROCKCHIP=y +CONFIG_TEXT_BASE=0x00200000 +CONFIG_SPL_GPIO=y +CONFIG_NR_DRAM_BANKS=1 +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x300000 +CONFIG_ENV_OFFSET=0x3F8000 +CONFIG_DEFAULT_DEVICE_TREE="rk3328-orangepi-r1-plus-lts" +CONFIG_DM_RESET=y +CONFIG_ROCKCHIP_RK3328=y +CONFIG_TPL_ROCKCHIP_COMMON_BOARD=y +CONFIG_TPL_LIBCOMMON_SUPPORT=y +CONFIG_TPL_LIBGENERIC_SUPPORT=y +CONFIG_SPL_DRIVERS_MISC=y +CONFIG_SPL_STACK_R_ADDR=0x600000 +CONFIG_SPL_STACK=0x400000 +CONFIG_TPL_SYS_MALLOC_F_LEN=0x800 +CONFIG_DEBUG_UART_BASE=0xFF130000 +CONFIG_DEBUG_UART_CLOCK=24000000 +CONFIG_SYS_LOAD_ADDR=0x800800 +CONFIG_DEBUG_UART=y +# CONFIG_ANDROID_BOOT_IMAGE is not set +CONFIG_FIT=y +CONFIG_FIT_VERBOSE=y +CONFIG_SPL_LOAD_FIT=y +CONFIG_DEFAULT_FDT_FILE="rockchip/rk3328-orangepi-r1-plus-lts.dtb" +# CONFIG_DISPLAY_CPUINFO is not set +CONFIG_DISPLAY_BOARDINFO_LATE=y +CONFIG_MISC_INIT_R=y +CONFIG_SPL_MAX_SIZE=0x40000 +CONFIG_SPL_PAD_TO=0x7f8000 +CONFIG_SPL_HAS_BSS_LINKER_SECTION=y +CONFIG_SPL_BSS_START_ADDR=0x2000000 +CONFIG_SPL_BSS_MAX_SIZE=0x2000 +# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set +# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set +CONFIG_SPL_STACK_R=y +CONFIG_SPL_I2C=y +CONFIG_SPL_POWER=y +CONFIG_SPL_ATF=y +CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y +CONFIG_TPL_SYS_MALLOC_SIMPLE=y +CONFIG_CMD_BOOTZ=y +CONFIG_CMD_GPT=y +CONFIG_CMD_MMC=y +CONFIG_CMD_USB=y +# CONFIG_CMD_SETEXPR is not set +CONFIG_CMD_TIME=y +CONFIG_SPL_OF_CONTROL=y +CONFIG_TPL_OF_CONTROL=y +CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" +CONFIG_TPL_OF_PLATDATA=y +CONFIG_ENV_IS_IN_MMC=y +CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_SYS_MMC_ENV_DEV=1 +CONFIG_NET_RANDOM_ETHADDR=y +CONFIG_TPL_DM=y +CONFIG_REGMAP=y +CONFIG_SPL_REGMAP=y +CONFIG_TPL_REGMAP=y +CONFIG_SYSCON=y +CONFIG_SPL_SYSCON=y +CONFIG_TPL_SYSCON=y +CONFIG_CLK=y +CONFIG_SPL_CLK=y +CONFIG_FASTBOOT_BUF_ADDR=0x800800 +CONFIG_FASTBOOT_CMD_OEM_FORMAT=y +CONFIG_ROCKCHIP_GPIO=y +CONFIG_SYS_I2C_ROCKCHIP=y +CONFIG_MMC_DW=y +CONFIG_MMC_DW_ROCKCHIP=y +CONFIG_SF_DEFAULT_SPEED=20000000 +CONFIG_SPI_FLASH_GIGADEVICE=y +CONFIG_ETH_DESIGNWARE=y +CONFIG_GMAC_ROCKCHIP=y +CONFIG_PINCTRL=y +CONFIG_SPL_PINCTRL=y +CONFIG_DM_PMIC=y +CONFIG_PMIC_RK8XX=y +CONFIG_SPL_PMIC_RK8XX=y +CONFIG_SPL_DM_REGULATOR=y +CONFIG_REGULATOR_PWM=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_SPL_DM_REGULATOR_FIXED=y +CONFIG_REGULATOR_RK8XX=y +CONFIG_PWM_ROCKCHIP=y +CONFIG_RAM=y +CONFIG_SPL_RAM=y +CONFIG_TPL_RAM=y +CONFIG_BAUDRATE=1500000 +CONFIG_DEBUG_UART_SHIFT=2 +CONFIG_SYS_NS16550_MEM32=y +CONFIG_ROCKCHIP_SPI=y +CONFIG_SYSINFO=y +CONFIG_SYSRESET=y +# CONFIG_TPL_SYSRESET is not set +CONFIG_USB=y +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_XHCI_DWC3=y +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_EHCI_GENERIC=y +CONFIG_USB_OHCI_HCD=y +CONFIG_USB_OHCI_GENERIC=y +CONFIG_USB_DWC2=y +CONFIG_USB_DWC3=y +# CONFIG_USB_DWC3_GADGET is not set +CONFIG_USB_GADGET=y +CONFIG_USB_GADGET_DWC2_OTG=y +CONFIG_SPL_TINY_MEMSET=y +CONFIG_TPL_TINY_MEMSET=y +CONFIG_ERRNO_STR=y -- cgit v1.3.1 From 0ef326b5e92ee7c0f3cd27385510eb5c211b10fb Mon Sep 17 00:00:00 2001 From: Tianling Shen Date: Tue, 30 May 2023 15:11:21 +0800 Subject: rockchip: rk3568: Add support for FriendlyARM NanoPi R5S FriendlyARM NanoPi R5S is an open-sourced mini IoT gateway device. Board Specifications - Rockchip RK3568 - 2 or 4GB LPDDR4X - 8GB or 16GB eMMC, SD card slot - GbE LAN (Native) - 2x 2.5G LAN (PCIe) - M.2 Connector - HDMI 2.0, MIPI DSI/CSI - 2xUSB 3.0 Host - USB Type C PD, 5V/9V/12V - GPIO: 12-pin 0.5mm FPC connector The device tree is taken from kernel v6.4-rc1. Reviewed-by: Kever Yang Signed-off-by: Tianling Shen --- arch/arm/dts/Makefile | 1 + arch/arm/dts/rk3568-nanopi-r5s-u-boot.dtsi | 31 ++ arch/arm/dts/rk3568-nanopi-r5s.dts | 136 +++++++ arch/arm/dts/rk3568-nanopi-r5s.dtsi | 590 +++++++++++++++++++++++++++++ board/rockchip/evb_rk3568/MAINTAINERS | 8 + configs/nanopi-r5s-rk3568_defconfig | 85 +++++ 6 files changed, 851 insertions(+) create mode 100644 arch/arm/dts/rk3568-nanopi-r5s-u-boot.dtsi create mode 100644 arch/arm/dts/rk3568-nanopi-r5s.dts create mode 100644 arch/arm/dts/rk3568-nanopi-r5s.dtsi create mode 100644 configs/nanopi-r5s-rk3568_defconfig diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index abb700e8a20..c8d580b0c66 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -171,6 +171,7 @@ dtb-$(CONFIG_ROCKCHIP_RK3568) += \ rk3566-anbernic-rgxx3.dtb \ rk3566-radxa-cm3-io.dtb \ rk3568-evb.dtb \ + rk3568-nanopi-r5s.dtb \ rk3568-rock-3a.dtb dtb-$(CONFIG_ROCKCHIP_RK3588) += \ diff --git a/arch/arm/dts/rk3568-nanopi-r5s-u-boot.dtsi b/arch/arm/dts/rk3568-nanopi-r5s-u-boot.dtsi new file mode 100644 index 00000000000..0ecca85b206 --- /dev/null +++ b/arch/arm/dts/rk3568-nanopi-r5s-u-boot.dtsi @@ -0,0 +1,31 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Copyright (c) 2022 FriendlyElec Computer Tech. Co., Ltd. + * (http://www.friendlyelec.com) + * + * Copyright (c) 2023 Tianling Shen + */ + +#include "rk356x-u-boot.dtsi" + +/ { + chosen { + stdout-path = &uart2; + u-boot,spl-boot-order = "same-as-spl", &sdmmc0, &sdhci; + }; +}; + +&sdhci { + cap-mmc-highspeed; + mmc-ddr-1_8v; + mmc-hs200-1_8v; + mmc-hs400-1_8v; + mmc-hs400-enhanced-strobe; + pinctrl-0 = <&emmc_bus8 &emmc_clk &emmc_cmd &emmc_datastrobe>; +}; + +&uart2 { + clock-frequency = <24000000>; + bootph-all; + status = "okay"; +}; diff --git a/arch/arm/dts/rk3568-nanopi-r5s.dts b/arch/arm/dts/rk3568-nanopi-r5s.dts new file mode 100644 index 00000000000..b6ad8328c7e --- /dev/null +++ b/arch/arm/dts/rk3568-nanopi-r5s.dts @@ -0,0 +1,136 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Copyright (c) 2022 FriendlyElec Computer Tech. Co., Ltd. + * (http://www.friendlyelec.com) + * + * Copyright (c) 2023 Tianling Shen + */ + +/dts-v1/; +#include "rk3568-nanopi-r5s.dtsi" + +/ { + model = "FriendlyElec NanoPi R5S"; + compatible = "friendlyarm,nanopi-r5s", "rockchip,rk3568"; + + aliases { + ethernet0 = &gmac0; + }; + + gpio-leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&lan1_led_pin>, <&lan2_led_pin>, <&power_led_pin>, <&wan_led_pin>; + + led-lan1 { + color = ; + function = LED_FUNCTION_LAN; + function-enumerator = <1>; + gpios = <&gpio3 RK_PD6 GPIO_ACTIVE_HIGH>; + }; + + led-lan2 { + color = ; + function = LED_FUNCTION_LAN; + function-enumerator = <2>; + gpios = <&gpio3 RK_PD7 GPIO_ACTIVE_HIGH>; + }; + + power_led: led-power { + color = ; + function = LED_FUNCTION_POWER; + linux,default-trigger = "heartbeat"; + gpios = <&gpio4 RK_PD2 GPIO_ACTIVE_HIGH>; + }; + + led-wan { + color = ; + function = LED_FUNCTION_WAN; + gpios = <&gpio2 RK_PC1 GPIO_ACTIVE_HIGH>; + }; + }; +}; + +&gmac0 { + assigned-clocks = <&cru SCLK_GMAC0_RX_TX>, <&cru SCLK_GMAC0>; + assigned-clock-parents = <&cru SCLK_GMAC0_RGMII_SPEED>, <&cru CLK_MAC0_2TOP>; + assigned-clock-rates = <0>, <125000000>; + clock_in_out = "output"; + phy-handle = <&rgmii_phy0>; + phy-mode = "rgmii"; + pinctrl-names = "default"; + pinctrl-0 = <&gmac0_miim + &gmac0_tx_bus2 + &gmac0_rx_bus2 + &gmac0_rgmii_clk + &gmac0_rgmii_bus>; + snps,reset-gpio = <&gpio0 RK_PC5 GPIO_ACTIVE_LOW>; + snps,reset-active-low; + /* Reset time is 15ms, 50ms for rtl8211f */ + snps,reset-delays-us = <0 15000 50000>; + tx_delay = <0x3c>; + rx_delay = <0x2f>; + status = "okay"; +}; + +&mdio0 { + rgmii_phy0: ethernet-phy@1 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <1>; + pinctrl-0 = <ð_phy0_reset_pin>; + pinctrl-names = "default"; + }; +}; + +&pcie2x1 { + num-lanes = <1>; + reset-gpios = <&gpio0 RK_PB6 GPIO_ACTIVE_HIGH>; + status = "okay"; +}; + +&pcie30phy { + data-lanes = <1 2>; + status = "okay"; +}; + +&pcie3x1 { + num-lanes = <1>; + reset-gpios = <&gpio0 RK_PA0 GPIO_ACTIVE_HIGH>; + vpcie3v3-supply = <&vcc3v3_pcie>; + status = "okay"; +}; + +&pcie3x2 { + num-lanes = <1>; + num-ib-windows = <8>; + num-ob-windows = <8>; + reset-gpios = <&gpio2 RK_PD6 GPIO_ACTIVE_HIGH>; + vpcie3v3-supply = <&vcc3v3_pcie>; + status = "okay"; +}; + +&pinctrl { + gmac0 { + eth_phy0_reset_pin: eth-phy0-reset-pin { + rockchip,pins = <0 RK_PC4 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + gpio-leds { + lan1_led_pin: lan1-led-pin { + rockchip,pins = <3 RK_PD6 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + lan2_led_pin: lan2-led-pin { + rockchip,pins = <3 RK_PD7 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + power_led_pin: power-led-pin { + rockchip,pins = <4 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + wan_led_pin: wan-led-pin { + rockchip,pins = <2 RK_PC1 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +}; diff --git a/arch/arm/dts/rk3568-nanopi-r5s.dtsi b/arch/arm/dts/rk3568-nanopi-r5s.dtsi new file mode 100644 index 00000000000..58ba328ea78 --- /dev/null +++ b/arch/arm/dts/rk3568-nanopi-r5s.dtsi @@ -0,0 +1,590 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Copyright (c) 2022 FriendlyElec Computer Tech. Co., Ltd. + * (http://www.friendlyelec.com) + * + * Copyright (c) 2023 Tianling Shen + */ + +/dts-v1/; +#include +#include +#include +#include +#include +#include "rk3568.dtsi" + +/ { + aliases { + mmc0 = &sdmmc0; + mmc1 = &sdhci; + }; + + chosen: chosen { + stdout-path = "serial2:1500000n8"; + }; + + hdmi-con { + compatible = "hdmi-connector"; + type = "a"; + + port { + hdmi_con_in: endpoint { + remote-endpoint = <&hdmi_out_con>; + }; + }; + }; + + vdd_usbc: vdd-usbc-regulator { + compatible = "regulator-fixed"; + regulator-name = "vdd_usbc"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + }; + + vcc3v3_sys: vcc3v3-sys-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&vdd_usbc>; + }; + + vcc5v0_sys: vcc5v0-sys-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&vdd_usbc>; + }; + + vcc3v3_pcie: vcc3v3-pcie-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3_pcie"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + enable-active-high; + gpios = <&gpio0 RK_PD4 GPIO_ACTIVE_HIGH>; + startup-delay-us = <200000>; + vin-supply = <&vcc5v0_sys>; + }; + + vcc5v0_usb: vcc5v0-usb-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_usb"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&vdd_usbc>; + }; + + vcc5v0_usb_host: vcc5v0-usb-host-regulator { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio0 RK_PA6 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&vcc5v0_usb_host_en>; + regulator-name = "vcc5v0_usb_host"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&vcc5v0_usb>; + }; + + vcc5v0_usb_otg: vcc5v0-usb-otg-regulator { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio0 RK_PA5 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&vcc5v0_usb_otg_en>; + regulator-name = "vcc5v0_usb_otg"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&vcc5v0_usb>; + }; + + pcie30_avdd0v9: pcie30-avdd0v9-regulator { + compatible = "regulator-fixed"; + regulator-name = "pcie30_avdd0v9"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <900000>; + vin-supply = <&vcc3v3_sys>; + }; + + pcie30_avdd1v8: pcie30-avdd1v8-regulator { + compatible = "regulator-fixed"; + regulator-name = "pcie30_avdd1v8"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + vin-supply = <&vcc3v3_sys>; + }; +}; + +&combphy0 { + status = "okay"; +}; + +&combphy1 { + status = "okay"; +}; + +&combphy2 { + status = "okay"; +}; + +&cpu0 { + cpu-supply = <&vdd_cpu>; +}; + +&cpu1 { + cpu-supply = <&vdd_cpu>; +}; + +&cpu2 { + cpu-supply = <&vdd_cpu>; +}; + +&cpu3 { + cpu-supply = <&vdd_cpu>; +}; + +&gpu { + mali-supply = <&vdd_gpu>; + status = "okay"; +}; + +&hdmi { + avdd-0v9-supply = <&vdda0v9_image>; + avdd-1v8-supply = <&vcca1v8_image>; + status = "okay"; +}; + +&hdmi_in { + hdmi_in_vp0: endpoint { + remote-endpoint = <&vp0_out_hdmi>; + }; +}; + +&hdmi_out { + hdmi_out_con: endpoint { + remote-endpoint = <&hdmi_con_in>; + }; +}; + +&hdmi_sound { + status = "okay"; +}; + +&i2c0 { + status = "okay"; + + vdd_cpu: regulator@1c { + compatible = "tcs,tcs4525"; + reg = <0x1c>; + fcs,suspend-voltage-selector = <1>; + regulator-name = "vdd_cpu"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1150000>; + regulator-ramp-delay = <2300>; + vin-supply = <&vcc5v0_sys>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + rk809: pmic@20 { + compatible = "rockchip,rk809"; + reg = <0x20>; + interrupt-parent = <&gpio0>; + interrupts = ; + #clock-cells = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&pmic_int>; + rockchip,system-power-controller; + vcc1-supply = <&vcc3v3_sys>; + vcc2-supply = <&vcc3v3_sys>; + vcc3-supply = <&vcc3v3_sys>; + vcc4-supply = <&vcc3v3_sys>; + vcc5-supply = <&vcc3v3_sys>; + vcc6-supply = <&vcc3v3_sys>; + vcc7-supply = <&vcc3v3_sys>; + vcc8-supply = <&vcc3v3_sys>; + vcc9-supply = <&vcc3v3_sys>; + wakeup-source; + + regulators { + vdd_logic: DCDC_REG1 { + regulator-name = "vdd_logic"; + regulator-always-on; + regulator-boot-on; + regulator-init-microvolt = <900000>; + regulator-initial-mode = <0x2>; + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <1350000>; + regulator-ramp-delay = <6001>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_gpu: DCDC_REG2 { + regulator-name = "vdd_gpu"; + regulator-always-on; + regulator-init-microvolt = <900000>; + regulator-initial-mode = <0x2>; + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <1350000>; + regulator-ramp-delay = <6001>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_ddr: DCDC_REG3 { + regulator-name = "vcc_ddr"; + regulator-always-on; + regulator-boot-on; + regulator-initial-mode = <0x2>; + + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + vdd_npu: DCDC_REG4 { + regulator-name = "vdd_npu"; + regulator-init-microvolt = <900000>; + regulator-initial-mode = <0x2>; + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <1350000>; + regulator-ramp-delay = <6001>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_1v8: DCDC_REG5 { + regulator-name = "vcc_1v8"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdda0v9_image: LDO_REG1 { + regulator-name = "vdda0v9_image"; + regulator-min-microvolt = <950000>; + regulator-max-microvolt = <950000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdda_0v9: LDO_REG2 { + regulator-name = "vdda_0v9"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <900000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdda0v9_pmu: LDO_REG3 { + regulator-name = "vdda0v9_pmu"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <900000>; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <900000>; + }; + }; + + vccio_acodec: LDO_REG4 { + regulator-name = "vccio_acodec"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vccio_sd: LDO_REG5 { + regulator-name = "vccio_sd"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc3v3_pmu: LDO_REG6 { + regulator-name = "vcc3v3_pmu"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3300000>; + }; + }; + + vcca_1v8: LDO_REG7 { + regulator-name = "vcca_1v8"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcca1v8_pmu: LDO_REG8 { + regulator-name = "vcca1v8_pmu"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vcca1v8_image: LDO_REG9 { + regulator-name = "vcca1v8_image"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_3v3: SWITCH_REG1 { + regulator-name = "vcc_3v3"; + regulator-always-on; + regulator-boot-on; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc3v3_sd: SWITCH_REG2 { + regulator-name = "vcc3v3_sd"; + regulator-always-on; + regulator-boot-on; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + }; + + }; +}; + +&i2c5 { + status = "okay"; + + hym8563: rtc@51 { + compatible = "haoyu,hym8563"; + reg = <0x51>; + interrupt-parent = <&gpio0>; + interrupts = ; + #clock-cells = <0>; + clock-output-names = "rtcic_32kout"; + pinctrl-names = "default"; + pinctrl-0 = <&hym8563_int>; + wakeup-source; + }; +}; + +&i2s0_8ch { + status = "okay"; +}; + +&pcie30phy { + data-lanes = <1 2>; + status = "okay"; +}; + +&pinctrl { + hym8563 { + hym8563_int: hym8563-int { + rockchip,pins = <0 RK_PD3 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + pmic { + pmic_int: pmic-int { + rockchip,pins = <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + usb { + vcc5v0_usb_host_en: vcc5v0-usb-host-en { + rockchip,pins = <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + vcc5v0_usb_otg_en: vcc5v0-usb-otg-en { + rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +}; + +&pmu_io_domains { + pmuio1-supply = <&vcc3v3_pmu>; + pmuio2-supply = <&vcc3v3_pmu>; + vccio1-supply = <&vccio_acodec>; + vccio3-supply = <&vccio_sd>; + vccio4-supply = <&vcc_1v8>; + vccio5-supply = <&vcc_3v3>; + vccio6-supply = <&vcc_1v8>; + vccio7-supply = <&vcc_3v3>; + status = "okay"; +}; + +&saradc { + vref-supply = <&vcca_1v8>; + status = "okay"; +}; + +&sdhci { + bus-width = <8>; + max-frequency = <200000000>; + non-removable; + pinctrl-names = "default"; + pinctrl-0 = <&emmc_bus8 &emmc_clk &emmc_cmd>; + status = "okay"; +}; + +&sdmmc0 { + max-frequency = <150000000>; + no-sdio; + no-mmc; + bus-width = <4>; + cap-mmc-highspeed; + cap-sd-highspeed; + disable-wp; + vmmc-supply = <&vcc3v3_sd>; + vqmmc-supply = <&vccio_sd>; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc0_bus4 &sdmmc0_clk &sdmmc0_cmd &sdmmc0_det>; + status = "okay"; +}; + +&tsadc { + rockchip,hw-tshut-mode = <1>; + rockchip,hw-tshut-polarity = <0>; + status = "okay"; +}; + +&uart2 { + status = "okay"; +}; + +&usb_host0_ehci { + status = "okay"; +}; + +&usb_host0_ohci { + status = "okay"; +}; + +&usb_host0_xhci { + extcon = <&usb2phy0>; + dr_mode = "host"; + status = "okay"; +}; + +&usb_host1_ehci { + status = "okay"; +}; + +&usb_host1_ohci { + status = "okay"; +}; + +&usb_host1_xhci { + status = "okay"; +}; + +&usb2phy0 { + status = "okay"; +}; + +&usb2phy0_host { + phy-supply = <&vcc5v0_usb_host>; + status = "okay"; +}; + +&usb2phy0_otg { + status = "okay"; +}; + +&usb2phy1 { + status = "okay"; +}; + +&usb2phy1_host { + phy-supply = <&vcc5v0_usb_otg>; + status = "okay"; +}; + +&usb2phy1_otg { + status = "okay"; +}; + +&vop { + assigned-clocks = <&cru DCLK_VOP0>, <&cru DCLK_VOP1>; + assigned-clock-parents = <&pmucru PLL_HPLL>, <&cru PLL_VPLL>; + status = "okay"; +}; + +&vop_mmu { + status = "okay"; +}; + +&vp0 { + vp0_out_hdmi: endpoint@ROCKCHIP_VOP2_EP_HDMI0 { + reg = ; + remote-endpoint = <&hdmi_in_vp0>; + }; +}; diff --git a/board/rockchip/evb_rk3568/MAINTAINERS b/board/rockchip/evb_rk3568/MAINTAINERS index 6b2e7c7575d..92226824614 100644 --- a/board/rockchip/evb_rk3568/MAINTAINERS +++ b/board/rockchip/evb_rk3568/MAINTAINERS @@ -7,6 +7,14 @@ F: configs/evb-rk3568_defconfig F: arch/arm/dts/rk3568-evb-boot.dtsi F: arch/arm/dts/rk3568-evb.dts +NANOPI-R5S +M: Tianling Shen +S: Maintained +F: configs/nanopi-r5s-rk3568_defconfig +F: arch/arm/dts/rk3568-nanopi-r5s.dts +F: arch/arm/dts/rk3568-nanopi-r5s.dtsi +F: arch/arm/dts/rk3568-nanopi-r5s-u-boot.dtsi + RADXA-CM3 M: Jagan Teki S: Maintained diff --git a/configs/nanopi-r5s-rk3568_defconfig b/configs/nanopi-r5s-rk3568_defconfig new file mode 100644 index 00000000000..0a298c65a76 --- /dev/null +++ b/configs/nanopi-r5s-rk3568_defconfig @@ -0,0 +1,85 @@ +CONFIG_ARM=y +CONFIG_SKIP_LOWLEVEL_INIT=y +CONFIG_COUNTER_FREQUENCY=24000000 +CONFIG_ARCH_ROCKCHIP=y +CONFIG_TEXT_BASE=0x00a00000 +CONFIG_SPL_LIBCOMMON_SUPPORT=y +CONFIG_SPL_LIBGENERIC_SUPPORT=y +CONFIG_NR_DRAM_BANKS=2 +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xc00000 +CONFIG_DEFAULT_DEVICE_TREE="rk3568-nanopi-r5s" +CONFIG_ROCKCHIP_RK3568=y +CONFIG_SPL_ROCKCHIP_COMMON_BOARD=y +CONFIG_SPL_SERIAL=y +CONFIG_SPL_STACK_R_ADDR=0x600000 +CONFIG_TARGET_EVB_RK3568=y +CONFIG_SPL_STACK=0x400000 +CONFIG_DEBUG_UART_BASE=0xFE660000 +CONFIG_DEBUG_UART_CLOCK=24000000 +CONFIG_SYS_LOAD_ADDR=0xc00800 +CONFIG_DEBUG_UART=y +CONFIG_FIT=y +CONFIG_FIT_VERBOSE=y +CONFIG_SPL_LOAD_FIT=y +CONFIG_DEFAULT_FDT_FILE="rockchip/rk3568-nanopi-r5s.dtb" +# CONFIG_DISPLAY_CPUINFO is not set +CONFIG_DISPLAY_BOARDINFO_LATE=y +CONFIG_SPL_MAX_SIZE=0x40000 +CONFIG_SPL_PAD_TO=0x7f8000 +CONFIG_SPL_HAS_BSS_LINKER_SECTION=y +CONFIG_SPL_BSS_START_ADDR=0x4000000 +CONFIG_SPL_BSS_MAX_SIZE=0x4000 +# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set +# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set +CONFIG_SPL_STACK_R=y +CONFIG_SPL_ATF=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_GPT=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_USB=y +CONFIG_CMD_PMIC=y +CONFIG_CMD_REGULATOR=y +# CONFIG_SPL_DOS_PARTITION is not set +CONFIG_SPL_OF_CONTROL=y +CONFIG_OF_LIVE=y +CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" +CONFIG_SPL_DM_WARN=y +CONFIG_SPL_REGMAP=y +CONFIG_SPL_SYSCON=y +CONFIG_SPL_CLK=y +CONFIG_ROCKCHIP_GPIO=y +CONFIG_SYS_I2C_ROCKCHIP=y +CONFIG_MISC=y +CONFIG_SUPPORT_EMMC_RPMB=y +CONFIG_MMC_DW=y +CONFIG_MMC_DW_ROCKCHIP=y +CONFIG_MMC_SDHCI=y +CONFIG_MMC_SDHCI_SDMA=y +CONFIG_MMC_SDHCI_ROCKCHIP=y +CONFIG_ETH_DESIGNWARE=y +CONFIG_GMAC_ROCKCHIP=y +CONFIG_PHY_ROCKCHIP_INNO_USB2=y +CONFIG_PHY_ROCKCHIP_NANENG_COMBOPHY=y +CONFIG_POWER_DOMAIN=y +CONFIG_DM_PMIC=y +CONFIG_PMIC_RK8XX=y +CONFIG_SPL_DM_REGULATOR_FIXED=y +CONFIG_REGULATOR_RK8XX=y +CONFIG_PWM_ROCKCHIP=y +CONFIG_SPL_RAM=y +CONFIG_BAUDRATE=1500000 +CONFIG_DEBUG_UART_SHIFT=2 +CONFIG_SYS_NS16550_MEM32=y +CONFIG_SYSRESET=y +CONFIG_SYSRESET_PSCI=y +CONFIG_USB=y +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_XHCI_DWC3=y +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_EHCI_GENERIC=y +CONFIG_USB_OHCI_HCD=y +CONFIG_USB_OHCI_GENERIC=y +CONFIG_USB_DWC3=y +CONFIG_ERRNO_STR=y -- cgit v1.3.1 From 6a73211d4bb12d62ce82b33cee7d75d215a3d452 Mon Sep 17 00:00:00 2001 From: Tianling Shen Date: Tue, 30 May 2023 15:11:22 +0800 Subject: rockchip: rk3568: Add support for FriendlyARM NanoPi R5C FriendlyARM NanoPi R5C is an open-sourced mini IoT gateway device. Specification: - Rockchip RK3568 - 1/4GB LPDDR4X RAM - 8/32GB eMMC - SD card slot - M.2 Connector - 2x USB 3.0 Port - 2x 2500 Base-T (PCIe, r8125) - HDMI 2.0 - MIPI DSI/CSI - USB Type C 5V The device tree is taken from kernel v6.4-rc1. Reviewed-by: Kever Yang Signed-off-by: Tianling Shen --- arch/arm/dts/Makefile | 1 + arch/arm/dts/rk3568-nanopi-r5c-u-boot.dtsi | 3 + arch/arm/dts/rk3568-nanopi-r5c.dts | 112 +++++++++++++++++++++++++++++ board/rockchip/evb_rk3568/MAINTAINERS | 7 ++ configs/nanopi-r5c-rk3568_defconfig | 85 ++++++++++++++++++++++ 5 files changed, 208 insertions(+) create mode 100644 arch/arm/dts/rk3568-nanopi-r5c-u-boot.dtsi create mode 100644 arch/arm/dts/rk3568-nanopi-r5c.dts create mode 100644 configs/nanopi-r5c-rk3568_defconfig diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index c8d580b0c66..a5eb9298ead 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -171,6 +171,7 @@ dtb-$(CONFIG_ROCKCHIP_RK3568) += \ rk3566-anbernic-rgxx3.dtb \ rk3566-radxa-cm3-io.dtb \ rk3568-evb.dtb \ + rk3568-nanopi-r5c.dtb \ rk3568-nanopi-r5s.dtb \ rk3568-rock-3a.dtb diff --git a/arch/arm/dts/rk3568-nanopi-r5c-u-boot.dtsi b/arch/arm/dts/rk3568-nanopi-r5c-u-boot.dtsi new file mode 100644 index 00000000000..fe5bc6af476 --- /dev/null +++ b/arch/arm/dts/rk3568-nanopi-r5c-u-boot.dtsi @@ -0,0 +1,3 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT + +#include "rk3568-nanopi-r5s-u-boot.dtsi" diff --git a/arch/arm/dts/rk3568-nanopi-r5c.dts b/arch/arm/dts/rk3568-nanopi-r5c.dts new file mode 100644 index 00000000000..f70ca9f0470 --- /dev/null +++ b/arch/arm/dts/rk3568-nanopi-r5c.dts @@ -0,0 +1,112 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Copyright (c) 2022 FriendlyElec Computer Tech. Co., Ltd. + * (http://www.friendlyelec.com) + * + * Copyright (c) 2023 Tianling Shen + */ + +/dts-v1/; +#include "rk3568-nanopi-r5s.dtsi" + +/ { + model = "FriendlyElec NanoPi R5C"; + compatible = "friendlyarm,nanopi-r5c", "rockchip,rk3568"; + + gpio-keys { + compatible = "gpio-keys"; + pinctrl-names = "default"; + pinctrl-0 = <&reset_button_pin>; + + button-reset { + debounce-interval = <50>; + gpios = <&gpio0 RK_PB7 GPIO_ACTIVE_LOW>; + label = "reset"; + linux,code = ; + }; + }; + + gpio-leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&lan_led_pin>, <&power_led_pin>, <&wan_led_pin>, <&wlan_led_pin>; + + led-lan { + color = ; + function = LED_FUNCTION_LAN; + gpios = <&gpio3 RK_PA3 GPIO_ACTIVE_HIGH>; + }; + + power_led: led-power { + color = ; + function = LED_FUNCTION_POWER; + linux,default-trigger = "heartbeat"; + gpios = <&gpio3 RK_PA2 GPIO_ACTIVE_HIGH>; + }; + + led-wan { + color = ; + function = LED_FUNCTION_WAN; + gpios = <&gpio3 RK_PA4 GPIO_ACTIVE_HIGH>; + }; + + led-wlan { + color = ; + function = LED_FUNCTION_WLAN; + gpios = <&gpio3 RK_PA5 GPIO_ACTIVE_HIGH>; + }; + }; +}; + +&pcie2x1 { + pinctrl-names = "default"; + pinctrl-0 = <&pcie20_reset_pin>; + reset-gpios = <&gpio3 RK_PC1 GPIO_ACTIVE_HIGH>; + status = "okay"; +}; + +&pcie3x1 { + num-lanes = <1>; + reset-gpios = <&gpio0 RK_PA0 GPIO_ACTIVE_HIGH>; + vpcie3v3-supply = <&vcc3v3_pcie>; + status = "okay"; +}; + +&pcie3x2 { + num-lanes = <1>; + reset-gpios = <&gpio0 RK_PB6 GPIO_ACTIVE_HIGH>; + vpcie3v3-supply = <&vcc3v3_pcie>; + status = "okay"; +}; + +&pinctrl { + gpio-leds { + lan_led_pin: lan-led-pin { + rockchip,pins = <3 RK_PA3 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + power_led_pin: power-led-pin { + rockchip,pins = <3 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + wan_led_pin: wan-led-pin { + rockchip,pins = <3 RK_PA4 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + wlan_led_pin: wlan-led-pin { + rockchip,pins = <3 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + pcie { + pcie20_reset_pin: pcie20-reset-pin { + rockchip,pins = <2 RK_PD2 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + rockchip-key { + reset_button_pin: reset-button-pin { + rockchip,pins = <4 RK_PA0 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; +}; diff --git a/board/rockchip/evb_rk3568/MAINTAINERS b/board/rockchip/evb_rk3568/MAINTAINERS index 92226824614..a8ed2508a16 100644 --- a/board/rockchip/evb_rk3568/MAINTAINERS +++ b/board/rockchip/evb_rk3568/MAINTAINERS @@ -7,6 +7,13 @@ F: configs/evb-rk3568_defconfig F: arch/arm/dts/rk3568-evb-boot.dtsi F: arch/arm/dts/rk3568-evb.dts +NANOPI-R5C +M: Tianling Shen +S: Maintained +F: configs/nanopi-r5c-rk3568_defconfig +F: arch/arm/dts/rk3568-nanopi-r5c.dts +F: arch/arm/dts/rk3568-nanopi-r5c-u-boot.dtsi + NANOPI-R5S M: Tianling Shen S: Maintained diff --git a/configs/nanopi-r5c-rk3568_defconfig b/configs/nanopi-r5c-rk3568_defconfig new file mode 100644 index 00000000000..b913ad4494c --- /dev/null +++ b/configs/nanopi-r5c-rk3568_defconfig @@ -0,0 +1,85 @@ +CONFIG_ARM=y +CONFIG_SKIP_LOWLEVEL_INIT=y +CONFIG_COUNTER_FREQUENCY=24000000 +CONFIG_ARCH_ROCKCHIP=y +CONFIG_TEXT_BASE=0x00a00000 +CONFIG_SPL_LIBCOMMON_SUPPORT=y +CONFIG_SPL_LIBGENERIC_SUPPORT=y +CONFIG_NR_DRAM_BANKS=2 +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xc00000 +CONFIG_DEFAULT_DEVICE_TREE="rk3568-nanopi-r5c" +CONFIG_ROCKCHIP_RK3568=y +CONFIG_SPL_ROCKCHIP_COMMON_BOARD=y +CONFIG_SPL_SERIAL=y +CONFIG_SPL_STACK_R_ADDR=0x600000 +CONFIG_TARGET_EVB_RK3568=y +CONFIG_SPL_STACK=0x400000 +CONFIG_DEBUG_UART_BASE=0xFE660000 +CONFIG_DEBUG_UART_CLOCK=24000000 +CONFIG_SYS_LOAD_ADDR=0xc00800 +CONFIG_DEBUG_UART=y +CONFIG_FIT=y +CONFIG_FIT_VERBOSE=y +CONFIG_SPL_LOAD_FIT=y +CONFIG_DEFAULT_FDT_FILE="rockchip/rk3568-nanopi-r5c.dtb" +# CONFIG_DISPLAY_CPUINFO is not set +CONFIG_DISPLAY_BOARDINFO_LATE=y +CONFIG_SPL_MAX_SIZE=0x40000 +CONFIG_SPL_PAD_TO=0x7f8000 +CONFIG_SPL_HAS_BSS_LINKER_SECTION=y +CONFIG_SPL_BSS_START_ADDR=0x4000000 +CONFIG_SPL_BSS_MAX_SIZE=0x4000 +# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set +# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set +CONFIG_SPL_STACK_R=y +CONFIG_SPL_ATF=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_GPT=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_USB=y +CONFIG_CMD_PMIC=y +CONFIG_CMD_REGULATOR=y +# CONFIG_SPL_DOS_PARTITION is not set +CONFIG_SPL_OF_CONTROL=y +CONFIG_OF_LIVE=y +CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" +CONFIG_SPL_DM_WARN=y +CONFIG_SPL_REGMAP=y +CONFIG_SPL_SYSCON=y +CONFIG_SPL_CLK=y +CONFIG_ROCKCHIP_GPIO=y +CONFIG_SYS_I2C_ROCKCHIP=y +CONFIG_MISC=y +CONFIG_SUPPORT_EMMC_RPMB=y +CONFIG_MMC_DW=y +CONFIG_MMC_DW_ROCKCHIP=y +CONFIG_MMC_SDHCI=y +CONFIG_MMC_SDHCI_SDMA=y +CONFIG_MMC_SDHCI_ROCKCHIP=y +CONFIG_ETH_DESIGNWARE=y +CONFIG_GMAC_ROCKCHIP=y +CONFIG_PHY_ROCKCHIP_INNO_USB2=y +CONFIG_PHY_ROCKCHIP_NANENG_COMBOPHY=y +CONFIG_POWER_DOMAIN=y +CONFIG_DM_PMIC=y +CONFIG_PMIC_RK8XX=y +CONFIG_SPL_DM_REGULATOR_FIXED=y +CONFIG_REGULATOR_RK8XX=y +CONFIG_PWM_ROCKCHIP=y +CONFIG_SPL_RAM=y +CONFIG_BAUDRATE=1500000 +CONFIG_DEBUG_UART_SHIFT=2 +CONFIG_SYS_NS16550_MEM32=y +CONFIG_SYSRESET=y +CONFIG_SYSRESET_PSCI=y +CONFIG_USB=y +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_XHCI_DWC3=y +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_EHCI_GENERIC=y +CONFIG_USB_OHCI_HCD=y +CONFIG_USB_OHCI_GENERIC=y +CONFIG_USB_DWC3=y +CONFIG_ERRNO_STR=y -- cgit v1.3.1 From 6b9fc19eac613d0dbb7ac8d0a4c7aa70e4e35622 Mon Sep 17 00:00:00 2001 From: Jagan Teki Date: Sun, 11 Jun 2023 12:27:09 +0530 Subject: arch: rockchip: rk3588: Fix missing suffix 'A' for Edgeble Neu6A Add missing suffix 'A' for Edgeble Neu6A SoM and IO boards. Fixes: <15b2d1fb727> ("board: rockchip: Add Edgeble Neural Compute Module 6") Signed-off-by: Jagan Teki Reviewed-by: Kever Yang --- arch/arm/mach-rockchip/rk3588/Kconfig | 10 +++++----- doc/board/rockchip/rockchip.rst | 2 +- 2 files changed, 6 insertions(+), 6 deletions(-) diff --git a/arch/arm/mach-rockchip/rk3588/Kconfig b/arch/arm/mach-rockchip/rk3588/Kconfig index b7d5f13bebb..0255f651bd7 100644 --- a/arch/arm/mach-rockchip/rk3588/Kconfig +++ b/arch/arm/mach-rockchip/rk3588/Kconfig @@ -10,14 +10,14 @@ config TARGET_RK3588_NEU6 bool "Edgeble Neural Compute Module 6(Neu6) SoM" select BOARD_LATE_INIT help - Neu6: - Neural Compute Module 6A(Neu6a) is a 96boards SoM-CB compute module + Neu6A: + Neural Compute Module 6A(Neu6A) is a 96boards SoM-CB compute module based on Rockchip RK3588 from Edgeble AI. - Neu6-IO: - Neural Compute Module 6(Neu6) IO board is an industrial form factor + Neu6A-IO: + Neural Compute Module 6A(Neu6A) IO board is an industrial form factor IO board and Neu6a needs to mount on top of this IO board in order to - create complete Edgeble Neural Compute Module 6(Neu6) IO platform. + create complete Edgeble Neural Compute Module 6A(Neu6A) IO platform. config TARGET_ROCK5B_RK3588 bool "Radxa ROCK5B RK3588 board" diff --git a/doc/board/rockchip/rockchip.rst b/doc/board/rockchip/rockchip.rst index 4c555e1c9c1..315ad41defe 100644 --- a/doc/board/rockchip/rockchip.rst +++ b/doc/board/rockchip/rockchip.rst @@ -98,7 +98,7 @@ List of mainline supported Rockchip boards: * rk3588 - Rockchip EVB (evb-rk3588) - - Edgeble Neural Compute Module 6 SoM - Neu6a (neu6a-io-rk3588) + - Edgeble Neural Compute Module 6A SoM - Neu6a (neu6a-io-rk3588) - Radxa ROCK 5B (rock5b-rk3588) * rv1108 -- cgit v1.3.1 From 0a086cb6eb87e8da102759d97af5e5b152217a83 Mon Sep 17 00:00:00 2001 From: Jagan Teki Date: Sun, 11 Jun 2023 12:27:10 +0530 Subject: arm64: dts: rockchip: Add Rockchip RK3588J MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Rockchip RK3588J is the industrial-grade version of RK3588 SoC and is operated with -40 °C to +85 °C temparature. Add rk3588j specific dtsi for adding rk3588j specific operating points and other changes to be add in future. Kernel commit: commit <8274a04ff1dc> ("arm64: dts: rockchip: Add Rockchip RK3588J") Signed-off-by: Jagan Teki Reviewed-by: Kever Yang --- arch/arm/dts/rk3588j.dtsi | 7 +++++++ 1 file changed, 7 insertions(+) create mode 100644 arch/arm/dts/rk3588j.dtsi diff --git a/arch/arm/dts/rk3588j.dtsi b/arch/arm/dts/rk3588j.dtsi new file mode 100644 index 00000000000..38b9dbf38a2 --- /dev/null +++ b/arch/arm/dts/rk3588j.dtsi @@ -0,0 +1,7 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2022 Rockchip Electronics Co., Ltd. + * + */ + +#include "rk3588.dtsi" -- cgit v1.3.1 From 51c82dda777f5f608b1f200965af664b9f8d01eb Mon Sep 17 00:00:00 2001 From: Jagan Teki Date: Sun, 11 Jun 2023 12:27:11 +0530 Subject: ARM: dts: rockchip: Add rk3588j-u-boot.dtsi Add rk3588j-u-boot.dtsi for adding U-Boot specific nodes and properties for Rockchip RK3588J SoC. Signed-off-by: Jagan Teki Reviewed-by: Kever Yang --- arch/arm/dts/rk3588j-u-boot.dtsi | 6 ++++++ 1 file changed, 6 insertions(+) create mode 100644 arch/arm/dts/rk3588j-u-boot.dtsi diff --git a/arch/arm/dts/rk3588j-u-boot.dtsi b/arch/arm/dts/rk3588j-u-boot.dtsi new file mode 100644 index 00000000000..f5c9e329a50 --- /dev/null +++ b/arch/arm/dts/rk3588j-u-boot.dtsi @@ -0,0 +1,6 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2022 Edgeble AI Technologies Pvt. Ltd. + */ + +#include "rk3588-u-boot.dtsi" -- cgit v1.3.1 From fcf5a3c900196dce839edaf155ccb91be94985ca Mon Sep 17 00:00:00 2001 From: Jagan Teki Date: Sun, 11 Jun 2023 12:27:12 +0530 Subject: arm64: dts: rockchip: Add rk3588 Edgeble Neu6B Neural Compute Module 6B(Neu6B) is a 96boards SoM-CB compute module based on Rockchip RK3588J from Edgeble AI. General features: - Rockchip RK3588J - up to 32GB LPDDR4x - up to 128GB eMMC - 2x MIPI CSI2 FPC - On module WiFi6/BT Neural Compute Module 6B(Neu6B) IO board is an industrial form factor ready-to-use IO board from Edgeble AI. General features: - microSD slot - 1x HDMI Out - 1x HDMI In - 2x DP - 1x eDP - 2x MIPI DSI connector - 4x MIPI CSI2 connector - 2x USB Host - 2x USB 3.0 OTG/Host - 1x SATA - 1x 2.5Gbps Ethernet - 1x M.2 B-Key for 4G/5G cards - 1x M.2 M-Key slot - 1x Onboard PoE - 1x RS485, RS232, CAN - 1x Audio, MIC port - RTC battery slot - 40-pin GPIO expansion Neu6B needs to mount on top of this IO board in order to create a complete Edgeble Neural Compute Module 6B(Neu6B) IO platform. Kernel commits: commit <5f06c3f508f7> ("arm64: dts: rockchip: Add rk3588 Edgeble Neu6 Model B SoM") commit <3a9181a43b94> ("arm64: dts: rockchip: Add rk3588 Edgeble Neu6 Model B IO") Signed-off-by: Jagan Teki Reviewed-by: Kever Yang --- arch/arm/dts/Makefile | 1 + arch/arm/dts/rk3588-edgeble-neu6b-io.dts | 27 +++++++++++++++++++++++++++ arch/arm/dts/rk3588-edgeble-neu6b.dtsi | 32 ++++++++++++++++++++++++++++++++ 3 files changed, 60 insertions(+) create mode 100644 arch/arm/dts/rk3588-edgeble-neu6b-io.dts create mode 100644 arch/arm/dts/rk3588-edgeble-neu6b.dtsi diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index a5eb9298ead..d1ac8acce5c 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -177,6 +177,7 @@ dtb-$(CONFIG_ROCKCHIP_RK3568) += \ dtb-$(CONFIG_ROCKCHIP_RK3588) += \ rk3588-edgeble-neu6a-io.dtb \ + rk3588-edgeble-neu6b-io.dtb \ rk3588-evb1-v10.dtb \ rk3588-rock-5b.dtb diff --git a/arch/arm/dts/rk3588-edgeble-neu6b-io.dts b/arch/arm/dts/rk3588-edgeble-neu6b-io.dts new file mode 100644 index 00000000000..e9d5a8bab58 --- /dev/null +++ b/arch/arm/dts/rk3588-edgeble-neu6b-io.dts @@ -0,0 +1,27 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2023 Edgeble AI Technologies Pvt. Ltd. + */ + +/dts-v1/; +#include "rk3588j.dtsi" +#include "rk3588-edgeble-neu6b.dtsi" + +/ { + model = "Edgeble Neu6B IO Board"; + compatible = "edgeble,neural-compute-module-6b-io", + "edgeble,neural-compute-module-6b", "rockchip,rk3588"; + + aliases { + serial2 = &uart2; + }; + + chosen { + stdout-path = "serial2:1500000n8"; + }; +}; + +&uart2 { + pinctrl-0 = <&uart2m0_xfer>; + status = "okay"; +}; diff --git a/arch/arm/dts/rk3588-edgeble-neu6b.dtsi b/arch/arm/dts/rk3588-edgeble-neu6b.dtsi new file mode 100644 index 00000000000..1c5bcf1280b --- /dev/null +++ b/arch/arm/dts/rk3588-edgeble-neu6b.dtsi @@ -0,0 +1,32 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2023 Edgeble AI Technologies Pvt. Ltd. + */ + +/ { + compatible = "edgeble,neural-compute-module-6b", "rockchip,rk3588"; + + aliases { + mmc0 = &sdhci; + }; + + vcc12v_dcin: vcc12v-dcin-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc12v_dcin"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <12000000>; + regulator-max-microvolt = <12000000>; + }; +}; + +&sdhci { + bus-width = <8>; + no-sdio; + no-sd; + non-removable; + max-frequency = <200000000>; + mmc-hs400-1_8v; + mmc-hs400-enhanced-strobe; + status = "okay"; +}; -- cgit v1.3.1 From 0a3a5746c3854f45603063f803ac36e4a361930c Mon Sep 17 00:00:00 2001 From: Jagan Teki Date: Sun, 11 Jun 2023 12:27:13 +0530 Subject: board: rockchip: Add Edgeble Neural Compute Module 6B Neural Compute Module 6B(Neu6B) is a 96boards SoM-CB compute module based on Rockchip RK3588J from Edgeble AI. Add support for this SoM and IO board. Signed-off-by: Jagan Teki Reviewed-by: Kever Yang --- arch/arm/dts/rk3588-edgeble-neu6b-io-u-boot.dtsi | 22 ++++++++ arch/arm/mach-rockchip/rk3588/Kconfig | 10 ++++ board/edgeble/neural-compute-module-6/MAINTAINERS | 1 + configs/neu6b-io-rk3588_defconfig | 64 +++++++++++++++++++++++ doc/board/rockchip/rockchip.rst | 1 + 5 files changed, 98 insertions(+) create mode 100644 arch/arm/dts/rk3588-edgeble-neu6b-io-u-boot.dtsi create mode 100644 configs/neu6b-io-rk3588_defconfig diff --git a/arch/arm/dts/rk3588-edgeble-neu6b-io-u-boot.dtsi b/arch/arm/dts/rk3588-edgeble-neu6b-io-u-boot.dtsi new file mode 100644 index 00000000000..cd7626b24b6 --- /dev/null +++ b/arch/arm/dts/rk3588-edgeble-neu6b-io-u-boot.dtsi @@ -0,0 +1,22 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2022 Edgeble AI Technologies Pvt. Ltd. + */ + +#include "rk3588j-u-boot.dtsi" + +/ { + aliases { + mmc0 = &sdmmc; + }; + + chosen { + stdout-path = &uart2; + u-boot,spl-boot-order = &sdmmc; + }; +}; + +&sdmmc { + bus-width = <4>; + status = "okay"; +}; diff --git a/arch/arm/mach-rockchip/rk3588/Kconfig b/arch/arm/mach-rockchip/rk3588/Kconfig index 0255f651bd7..d72ef92f2ef 100644 --- a/arch/arm/mach-rockchip/rk3588/Kconfig +++ b/arch/arm/mach-rockchip/rk3588/Kconfig @@ -19,6 +19,16 @@ config TARGET_RK3588_NEU6 IO board and Neu6a needs to mount on top of this IO board in order to create complete Edgeble Neural Compute Module 6A(Neu6A) IO platform. + Neu6B: + Neural Compute Module 6B(Neu6B) is a 96boards SoM-CB compute module + based on Rockchip RK3588J from Edgeble AI. + + Neu6A-IO: + Neural Compute Module 6B(Neu6B) IO board is an industrial form factor + IO board and Neu6a needs to mount on top of this IO board in order to + create complete Edgeble Neural Compute Module 6B(Neu6B) IO platform. + +config TARGET_ROCK5B_RK3588 config TARGET_ROCK5B_RK3588 bool "Radxa ROCK5B RK3588 board" select BOARD_LATE_INIT diff --git a/board/edgeble/neural-compute-module-6/MAINTAINERS b/board/edgeble/neural-compute-module-6/MAINTAINERS index 249df957f1d..bc7f9b0e680 100644 --- a/board/edgeble/neural-compute-module-6/MAINTAINERS +++ b/board/edgeble/neural-compute-module-6/MAINTAINERS @@ -4,3 +4,4 @@ S: Maintained F: board/edgeble/neural-compute-module-6 F: include/configs/neural-compute-module-6.h F: configs/neu6a-io-rk3588_defconfig +F: configs/neu6b-io-rk3588_defconfig diff --git a/configs/neu6b-io-rk3588_defconfig b/configs/neu6b-io-rk3588_defconfig new file mode 100644 index 00000000000..c7bc3b1965f --- /dev/null +++ b/configs/neu6b-io-rk3588_defconfig @@ -0,0 +1,64 @@ +CONFIG_ARM=y +CONFIG_SKIP_LOWLEVEL_INIT=y +CONFIG_COUNTER_FREQUENCY=24000000 +CONFIG_ARCH_ROCKCHIP=y +CONFIG_TEXT_BASE=0x00a00000 +CONFIG_SPL_LIBCOMMON_SUPPORT=y +CONFIG_SPL_LIBGENERIC_SUPPORT=y +CONFIG_NR_DRAM_BANKS=2 +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xc00000 +CONFIG_DEFAULT_DEVICE_TREE="rk3588-edgeble-neu6b-io" +CONFIG_ROCKCHIP_RK3588=y +CONFIG_SPL_ROCKCHIP_COMMON_BOARD=y +CONFIG_SPL_SERIAL=y +CONFIG_SPL_STACK_R_ADDR=0x600000 +CONFIG_TARGET_RK3588_NEU6=y +CONFIG_SPL_STACK=0x400000 +CONFIG_DEBUG_UART_BASE=0xFEB50000 +CONFIG_DEBUG_UART_CLOCK=24000000 +CONFIG_SYS_LOAD_ADDR=0xc00800 +CONFIG_DEBUG_UART=y +CONFIG_FIT=y +CONFIG_FIT_VERBOSE=y +CONFIG_SPL_LOAD_FIT=y +CONFIG_DEFAULT_FDT_FILE="rockchip/rk3588-edgeble-neu6b-io.dtb" +# CONFIG_DISPLAY_CPUINFO is not set +CONFIG_DISPLAY_BOARDINFO_LATE=y +CONFIG_SPL_MAX_SIZE=0x20000 +CONFIG_SPL_PAD_TO=0x7f8000 +CONFIG_SPL_HAS_BSS_LINKER_SECTION=y +CONFIG_SPL_BSS_START_ADDR=0x4000000 +CONFIG_SPL_BSS_MAX_SIZE=0x4000 +# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set +# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set +CONFIG_SPL_STACK_R=y +CONFIG_SPL_ATF=y +CONFIG_CMD_GPT=y +CONFIG_CMD_MMC=y +# CONFIG_CMD_SETEXPR is not set +# CONFIG_SPL_DOS_PARTITION is not set +CONFIG_SPL_OF_CONTROL=y +CONFIG_OF_LIVE=y +CONFIG_NET_RANDOM_ETHADDR=y +CONFIG_SPL_REGMAP=y +CONFIG_SPL_SYSCON=y +CONFIG_SPL_CLK=y +CONFIG_ROCKCHIP_GPIO=y +CONFIG_SYS_I2C_ROCKCHIP=y +CONFIG_MISC=y +CONFIG_SUPPORT_EMMC_RPMB=y +CONFIG_MMC_DW=y +CONFIG_MMC_DW_ROCKCHIP=y +CONFIG_MMC_SDHCI=y +CONFIG_MMC_SDHCI_SDMA=y +CONFIG_MMC_SDHCI_ROCKCHIP=y +CONFIG_ETH_DESIGNWARE=y +CONFIG_GMAC_ROCKCHIP=y +CONFIG_REGULATOR_PWM=y +CONFIG_PWM_ROCKCHIP=y +CONFIG_SPL_RAM=y +CONFIG_BAUDRATE=1500000 +CONFIG_DEBUG_UART_SHIFT=2 +CONFIG_SYSRESET=y +CONFIG_ERRNO_STR=y diff --git a/doc/board/rockchip/rockchip.rst b/doc/board/rockchip/rockchip.rst index 315ad41defe..d3022021e4c 100644 --- a/doc/board/rockchip/rockchip.rst +++ b/doc/board/rockchip/rockchip.rst @@ -99,6 +99,7 @@ List of mainline supported Rockchip boards: * rk3588 - Rockchip EVB (evb-rk3588) - Edgeble Neural Compute Module 6A SoM - Neu6a (neu6a-io-rk3588) + - Edgeble Neural Compute Module 6B SoM - Neu6b (neu6b-io-rk3588) - Radxa ROCK 5B (rock5b-rk3588) * rv1108 -- cgit v1.3.1 From e6fa0dcc6f3fc44b1bc08fd5d921c5ad95163a69 Mon Sep 17 00:00:00 2001 From: Quentin Schulz Date: Wed, 21 Jun 2023 18:02:52 +0200 Subject: rockchip: rk3399: pass platform parameter to TF-A by default for new RK3399 boards Long are gone the times TF-A couldn't handle the FDT passed by U-Boot. Specifically, since commit e7b586987c0a ("rockchip: don't crash if we get an FDT we can't parse") in TF-A, failure to parse the FDT will use the fallback mechanism. This patch was merged in TF-A v2.4-rc0 from two years ago. New boards should likely have this option disabled or explicitly enable it in their respective defconfig. Because existing boards might depend on a TF-A version that predates v2.4, let's just enable this option in all RK3399 defconfigs. Maintainers of each board can decide for themselves if they would prefer to disable this option and allow U-Boot to pass the DT to TF-A. Cc: Quentin Schulz Signed-off-by: Quentin Schulz Reviewed-by: Kever Yang --- arch/arm/mach-rockchip/Kconfig | 1 - configs/chromebook_bob_defconfig | 1 + configs/chromebook_kevin_defconfig | 1 + configs/eaidk-610-rk3399_defconfig | 1 + configs/evb-rk3399_defconfig | 1 + configs/ficus-rk3399_defconfig | 1 + configs/firefly-rk3399_defconfig | 1 + configs/khadas-edge-captain-rk3399_defconfig | 1 + configs/khadas-edge-rk3399_defconfig | 1 + configs/khadas-edge-v-rk3399_defconfig | 1 + configs/leez-rk3399_defconfig | 1 + configs/nanopc-t4-rk3399_defconfig | 1 + configs/nanopi-m4-2gb-rk3399_defconfig | 1 + configs/nanopi-m4-rk3399_defconfig | 1 + configs/nanopi-m4b-rk3399_defconfig | 1 + configs/nanopi-neo4-rk3399_defconfig | 1 + configs/nanopi-r4s-rk3399_defconfig | 1 + configs/orangepi-rk3399_defconfig | 1 + configs/pinebook-pro-rk3399_defconfig | 1 + configs/pinephone-pro-rk3399_defconfig | 1 + configs/puma-rk3399_defconfig | 1 + configs/roc-pc-mezzanine-rk3399_defconfig | 1 + configs/roc-pc-rk3399_defconfig | 1 + configs/rock-4c-plus-rk3399_defconfig | 1 + configs/rock-pi-4-rk3399_defconfig | 1 + configs/rock-pi-4c-rk3399_defconfig | 1 + configs/rock-pi-n10-rk3399pro_defconfig | 1 + configs/rock960-rk3399_defconfig | 1 + configs/rockpro64-rk3399_defconfig | 1 + 29 files changed, 28 insertions(+), 1 deletion(-) diff --git a/arch/arm/mach-rockchip/Kconfig b/arch/arm/mach-rockchip/Kconfig index 9d6d20bf8ed..edc413d12a0 100644 --- a/arch/arm/mach-rockchip/Kconfig +++ b/arch/arm/mach-rockchip/Kconfig @@ -250,7 +250,6 @@ config ROCKCHIP_RK3399 imply PRE_CONSOLE_BUFFER imply ROCKCHIP_COMMON_BOARD imply ROCKCHIP_SDRAM_COMMON - imply SPL_ATF_NO_PLATFORM_PARAM if SPL_ATF imply SPL_ROCKCHIP_COMMON_BOARD imply TPL_SERIAL imply TPL_LIBCOMMON_SUPPORT diff --git a/configs/chromebook_bob_defconfig b/configs/chromebook_bob_defconfig index dd6d4069a60..1807e838223 100644 --- a/configs/chromebook_bob_defconfig +++ b/configs/chromebook_bob_defconfig @@ -43,6 +43,7 @@ CONFIG_SPL_STACK_R=y CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x4000 CONFIG_SPL_SPI_LOAD=y CONFIG_SYS_SPI_U_BOOT_OFFS=0x40000 +CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y CONFIG_CMD_BOOTZ=y CONFIG_CMD_GPIO=y CONFIG_CMD_GPT=y diff --git a/configs/chromebook_kevin_defconfig b/configs/chromebook_kevin_defconfig index 3d2642f0d07..638beee2c6d 100644 --- a/configs/chromebook_kevin_defconfig +++ b/configs/chromebook_kevin_defconfig @@ -44,6 +44,7 @@ CONFIG_SPL_STACK_R=y CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x4000 CONFIG_SPL_SPI_LOAD=y CONFIG_SYS_SPI_U_BOOT_OFFS=0x40000 +CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y CONFIG_CMD_BOOTZ=y CONFIG_CMD_GPIO=y CONFIG_CMD_GPT=y diff --git a/configs/eaidk-610-rk3399_defconfig b/configs/eaidk-610-rk3399_defconfig index b4112a14712..77edbdbf959 100644 --- a/configs/eaidk-610-rk3399_defconfig +++ b/configs/eaidk-610-rk3399_defconfig @@ -26,6 +26,7 @@ CONFIG_SPL_BSS_MAX_SIZE=0x2000 # CONFIG_SPL_SHARES_INIT_SP_ADDR is not set CONFIG_SPL_STACK_R=y CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x10000 +CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y CONFIG_TPL=y CONFIG_CMD_BOOTZ=y CONFIG_CMD_GPT=y diff --git a/configs/evb-rk3399_defconfig b/configs/evb-rk3399_defconfig index f594f15b3f8..5740ffc38f6 100644 --- a/configs/evb-rk3399_defconfig +++ b/configs/evb-rk3399_defconfig @@ -28,6 +28,7 @@ CONFIG_SPL_BSS_MAX_SIZE=0x2000 # CONFIG_SPL_SHARES_INIT_SP_ADDR is not set CONFIG_SPL_STACK_R=y CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x10000 +CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y CONFIG_TPL=y CONFIG_CMD_BOOTZ=y CONFIG_CMD_GPT=y diff --git a/configs/ficus-rk3399_defconfig b/configs/ficus-rk3399_defconfig index 94b8f88a965..90b07d847cc 100644 --- a/configs/ficus-rk3399_defconfig +++ b/configs/ficus-rk3399_defconfig @@ -27,6 +27,7 @@ CONFIG_SPL_BSS_MAX_SIZE=0x10000 # CONFIG_SPL_SHARES_INIT_SP_ADDR is not set CONFIG_SPL_STACK_R=y CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x4000 +CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y CONFIG_CMD_BOOTZ=y CONFIG_CMD_GPT=y CONFIG_CMD_MMC=y diff --git a/configs/firefly-rk3399_defconfig b/configs/firefly-rk3399_defconfig index 0ece93b71d6..b4660a051df 100644 --- a/configs/firefly-rk3399_defconfig +++ b/configs/firefly-rk3399_defconfig @@ -30,6 +30,7 @@ CONFIG_SPL_BSS_MAX_SIZE=0x2000 # CONFIG_SPL_SHARES_INIT_SP_ADDR is not set CONFIG_SPL_STACK_R=y CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x10000 +CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y CONFIG_TPL=y CONFIG_CMD_BOOTZ=y CONFIG_CMD_GPT=y diff --git a/configs/khadas-edge-captain-rk3399_defconfig b/configs/khadas-edge-captain-rk3399_defconfig index 0651b982f59..2800c47361d 100644 --- a/configs/khadas-edge-captain-rk3399_defconfig +++ b/configs/khadas-edge-captain-rk3399_defconfig @@ -27,6 +27,7 @@ CONFIG_SPL_BSS_MAX_SIZE=0x2000 # CONFIG_SPL_SHARES_INIT_SP_ADDR is not set CONFIG_SPL_STACK_R=y CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x10000 +CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y CONFIG_TPL=y CONFIG_SYS_PBSIZE=1048 CONFIG_CMD_BOOTZ=y diff --git a/configs/khadas-edge-rk3399_defconfig b/configs/khadas-edge-rk3399_defconfig index 85e18aaa1a2..33b2afd869d 100644 --- a/configs/khadas-edge-rk3399_defconfig +++ b/configs/khadas-edge-rk3399_defconfig @@ -27,6 +27,7 @@ CONFIG_SPL_BSS_MAX_SIZE=0x2000 # CONFIG_SPL_SHARES_INIT_SP_ADDR is not set CONFIG_SPL_STACK_R=y CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x10000 +CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y CONFIG_TPL=y CONFIG_SYS_PBSIZE=1048 CONFIG_CMD_BOOTZ=y diff --git a/configs/khadas-edge-v-rk3399_defconfig b/configs/khadas-edge-v-rk3399_defconfig index 7fe559b49ea..f7a6445b3c1 100644 --- a/configs/khadas-edge-v-rk3399_defconfig +++ b/configs/khadas-edge-v-rk3399_defconfig @@ -27,6 +27,7 @@ CONFIG_SPL_BSS_MAX_SIZE=0x2000 # CONFIG_SPL_SHARES_INIT_SP_ADDR is not set CONFIG_SPL_STACK_R=y CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x10000 +CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y CONFIG_TPL=y CONFIG_SYS_PBSIZE=1048 CONFIG_CMD_BOOTZ=y diff --git a/configs/leez-rk3399_defconfig b/configs/leez-rk3399_defconfig index c1184596889..fa936609e9b 100644 --- a/configs/leez-rk3399_defconfig +++ b/configs/leez-rk3399_defconfig @@ -25,6 +25,7 @@ CONFIG_SPL_BSS_MAX_SIZE=0x2000 # CONFIG_SPL_SHARES_INIT_SP_ADDR is not set CONFIG_SPL_STACK_R=y CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x10000 +CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y CONFIG_TPL=y CONFIG_CMD_BOOTZ=y CONFIG_CMD_GPT=y diff --git a/configs/nanopc-t4-rk3399_defconfig b/configs/nanopc-t4-rk3399_defconfig index 75589bb519a..82e86ca0702 100644 --- a/configs/nanopc-t4-rk3399_defconfig +++ b/configs/nanopc-t4-rk3399_defconfig @@ -28,6 +28,7 @@ CONFIG_SPL_BSS_MAX_SIZE=0x2000 # CONFIG_SPL_SHARES_INIT_SP_ADDR is not set CONFIG_SPL_STACK_R=y CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x10000 +CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y CONFIG_TPL=y CONFIG_CMD_BOOTZ=y CONFIG_CMD_GPT=y diff --git a/configs/nanopi-m4-2gb-rk3399_defconfig b/configs/nanopi-m4-2gb-rk3399_defconfig index 04ce5438f4f..dd715517d5a 100644 --- a/configs/nanopi-m4-2gb-rk3399_defconfig +++ b/configs/nanopi-m4-2gb-rk3399_defconfig @@ -26,6 +26,7 @@ CONFIG_SPL_BSS_MAX_SIZE=0x2000 # CONFIG_SPL_SHARES_INIT_SP_ADDR is not set CONFIG_SPL_STACK_R=y CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x10000 +CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y CONFIG_TPL=y CONFIG_CMD_BOOTZ=y CONFIG_CMD_GPT=y diff --git a/configs/nanopi-m4-rk3399_defconfig b/configs/nanopi-m4-rk3399_defconfig index 6745934d988..3da93db06da 100644 --- a/configs/nanopi-m4-rk3399_defconfig +++ b/configs/nanopi-m4-rk3399_defconfig @@ -26,6 +26,7 @@ CONFIG_SPL_BSS_MAX_SIZE=0x2000 # CONFIG_SPL_SHARES_INIT_SP_ADDR is not set CONFIG_SPL_STACK_R=y CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x10000 +CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y CONFIG_TPL=y CONFIG_CMD_BOOTZ=y CONFIG_CMD_GPT=y diff --git a/configs/nanopi-m4b-rk3399_defconfig b/configs/nanopi-m4b-rk3399_defconfig index 1a9839b4d15..701dde15f3e 100644 --- a/configs/nanopi-m4b-rk3399_defconfig +++ b/configs/nanopi-m4b-rk3399_defconfig @@ -26,6 +26,7 @@ CONFIG_SPL_BSS_MAX_SIZE=0x2000 # CONFIG_SPL_SHARES_INIT_SP_ADDR is not set CONFIG_SPL_STACK_R=y CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x10000 +CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y CONFIG_TPL=y CONFIG_CMD_BOOTZ=y CONFIG_CMD_GPT=y diff --git a/configs/nanopi-neo4-rk3399_defconfig b/configs/nanopi-neo4-rk3399_defconfig index ad0627fe655..3f9d0340c81 100644 --- a/configs/nanopi-neo4-rk3399_defconfig +++ b/configs/nanopi-neo4-rk3399_defconfig @@ -26,6 +26,7 @@ CONFIG_SPL_BSS_MAX_SIZE=0x2000 # CONFIG_SPL_SHARES_INIT_SP_ADDR is not set CONFIG_SPL_STACK_R=y CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x10000 +CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y CONFIG_TPL=y CONFIG_CMD_BOOTZ=y CONFIG_CMD_GPT=y diff --git a/configs/nanopi-r4s-rk3399_defconfig b/configs/nanopi-r4s-rk3399_defconfig index a41e774b0c4..4f4363cb0f9 100644 --- a/configs/nanopi-r4s-rk3399_defconfig +++ b/configs/nanopi-r4s-rk3399_defconfig @@ -27,6 +27,7 @@ CONFIG_SPL_BSS_MAX_SIZE=0x2000 # CONFIG_SPL_SHARES_INIT_SP_ADDR is not set CONFIG_SPL_STACK_R=y CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x10000 +CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y CONFIG_TPL=y CONFIG_CMD_BOOTZ=y CONFIG_CMD_GPT=y diff --git a/configs/orangepi-rk3399_defconfig b/configs/orangepi-rk3399_defconfig index 0f814b1b289..ba6d91e877d 100644 --- a/configs/orangepi-rk3399_defconfig +++ b/configs/orangepi-rk3399_defconfig @@ -26,6 +26,7 @@ CONFIG_SPL_BSS_MAX_SIZE=0x2000 # CONFIG_SPL_SHARES_INIT_SP_ADDR is not set CONFIG_SPL_STACK_R=y CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x10000 +CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y CONFIG_TPL=y CONFIG_CMD_BOOTZ=y CONFIG_CMD_GPT=y diff --git a/configs/pinebook-pro-rk3399_defconfig b/configs/pinebook-pro-rk3399_defconfig index 58a8b91aa60..5d493c910ee 100644 --- a/configs/pinebook-pro-rk3399_defconfig +++ b/configs/pinebook-pro-rk3399_defconfig @@ -36,6 +36,7 @@ CONFIG_SPL_BSS_MAX_SIZE=0x2000 CONFIG_SPL_STACK_R=y CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x10000 CONFIG_SPL_SPI_LOAD=y +CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y CONFIG_TPL=y CONFIG_CMD_BOOTZ=y CONFIG_CMD_GPIO=y diff --git a/configs/pinephone-pro-rk3399_defconfig b/configs/pinephone-pro-rk3399_defconfig index e4a8beeb1ab..f97a4003bba 100644 --- a/configs/pinephone-pro-rk3399_defconfig +++ b/configs/pinephone-pro-rk3399_defconfig @@ -35,6 +35,7 @@ CONFIG_SPL_BSS_MAX_SIZE=0x2000 CONFIG_SPL_STACK_R=y CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x10000 CONFIG_SPL_SPI_LOAD=y +CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y CONFIG_TPL=y CONFIG_CMD_BOOTZ=y CONFIG_CMD_GPIO=y diff --git a/configs/puma-rk3399_defconfig b/configs/puma-rk3399_defconfig index b632fa3dcf3..697f5eccef5 100644 --- a/configs/puma-rk3399_defconfig +++ b/configs/puma-rk3399_defconfig @@ -39,6 +39,7 @@ CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x200 CONFIG_SPL_I2C=y CONFIG_SPL_POWER=y CONFIG_SPL_SPI_LOAD=y +CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y CONFIG_TPL=y CONFIG_CMD_BOOTZ=y CONFIG_CMD_GPT=y diff --git a/configs/roc-pc-mezzanine-rk3399_defconfig b/configs/roc-pc-mezzanine-rk3399_defconfig index 9321292ca52..0d113c764f6 100644 --- a/configs/roc-pc-mezzanine-rk3399_defconfig +++ b/configs/roc-pc-mezzanine-rk3399_defconfig @@ -37,6 +37,7 @@ CONFIG_SPL_STACK_R=y CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x20000 CONFIG_SPL_ENV_SUPPORT=y CONFIG_SPL_SPI_LOAD=y +CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y CONFIG_TPL=y CONFIG_CMD_BOOTZ=y CONFIG_CMD_GPT=y diff --git a/configs/roc-pc-rk3399_defconfig b/configs/roc-pc-rk3399_defconfig index 824b4041c20..7e5db741951 100644 --- a/configs/roc-pc-rk3399_defconfig +++ b/configs/roc-pc-rk3399_defconfig @@ -38,6 +38,7 @@ CONFIG_SPL_STACK_R=y CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x20000 CONFIG_SPL_ENV_SUPPORT=y CONFIG_SPL_SPI_LOAD=y +CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y CONFIG_TPL=y CONFIG_CMD_BOOTZ=y CONFIG_CMD_GPT=y diff --git a/configs/rock-4c-plus-rk3399_defconfig b/configs/rock-4c-plus-rk3399_defconfig index 3c79d2ac3d3..3028a86705c 100644 --- a/configs/rock-4c-plus-rk3399_defconfig +++ b/configs/rock-4c-plus-rk3399_defconfig @@ -31,6 +31,7 @@ CONFIG_SPL_BSS_MAX_SIZE=0x2000 # CONFIG_SPL_SHARES_INIT_SP_ADDR is not set CONFIG_SPL_STACK_R=y CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x10000 +CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y CONFIG_TPL=y CONFIG_CMD_BOOTZ=y CONFIG_CMD_NVEDIT_EFI=y diff --git a/configs/rock-pi-4-rk3399_defconfig b/configs/rock-pi-4-rk3399_defconfig index 466868d80b0..84e0dcf0282 100644 --- a/configs/rock-pi-4-rk3399_defconfig +++ b/configs/rock-pi-4-rk3399_defconfig @@ -33,6 +33,7 @@ CONFIG_SPL_BSS_MAX_SIZE=0x2000 # CONFIG_SPL_SHARES_INIT_SP_ADDR is not set CONFIG_SPL_STACK_R=y CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x10000 +CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y CONFIG_TPL=y CONFIG_CMD_BOOTZ=y CONFIG_CMD_NVEDIT_EFI=y diff --git a/configs/rock-pi-4c-rk3399_defconfig b/configs/rock-pi-4c-rk3399_defconfig index 1c7648c1f0c..5c9fb14787d 100644 --- a/configs/rock-pi-4c-rk3399_defconfig +++ b/configs/rock-pi-4c-rk3399_defconfig @@ -31,6 +31,7 @@ CONFIG_SPL_BSS_MAX_SIZE=0x2000 # CONFIG_SPL_SHARES_INIT_SP_ADDR is not set CONFIG_SPL_STACK_R=y CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x10000 +CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y CONFIG_TPL=y CONFIG_CMD_BOOTZ=y CONFIG_CMD_NVEDIT_EFI=y diff --git a/configs/rock-pi-n10-rk3399pro_defconfig b/configs/rock-pi-n10-rk3399pro_defconfig index 8eb17d8feca..1978fd525b8 100644 --- a/configs/rock-pi-n10-rk3399pro_defconfig +++ b/configs/rock-pi-n10-rk3399pro_defconfig @@ -32,6 +32,7 @@ CONFIG_SPL_BSS_MAX_SIZE=0x2000 # CONFIG_SPL_SHARES_INIT_SP_ADDR is not set CONFIG_SPL_STACK_R=y CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x10000 +CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y CONFIG_TPL=y CONFIG_CMD_BOOTZ=y CONFIG_CMD_GPT=y diff --git a/configs/rock960-rk3399_defconfig b/configs/rock960-rk3399_defconfig index 3d6aeaa5efc..4e048b6ba18 100644 --- a/configs/rock960-rk3399_defconfig +++ b/configs/rock960-rk3399_defconfig @@ -30,6 +30,7 @@ CONFIG_SPL_BSS_MAX_SIZE=0x2000 # CONFIG_SPL_SHARES_INIT_SP_ADDR is not set CONFIG_SPL_STACK_R=y CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x10000 +CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y CONFIG_TPL=y CONFIG_SYS_PBSIZE=1052 CONFIG_CMD_BOOTZ=y diff --git a/configs/rockpro64-rk3399_defconfig b/configs/rockpro64-rk3399_defconfig index dc4392c7451..62daad27a6f 100644 --- a/configs/rockpro64-rk3399_defconfig +++ b/configs/rockpro64-rk3399_defconfig @@ -41,6 +41,7 @@ CONFIG_SPL_STACK_R=y CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x10000 CONFIG_SPL_SPI_LOAD=y CONFIG_SYS_SPI_U_BOOT_OFFS=0x60000 +CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y CONFIG_TPL=y CONFIG_CMD_BOOTZ=y CONFIG_CMD_GPT=y -- cgit v1.3.1 From 9010c43b038f81d5282e51c723a673a25a0fb6b3 Mon Sep 17 00:00:00 2001 From: Quentin Schulz Date: Wed, 21 Jun 2023 18:02:53 +0200 Subject: rockchip: puma: pass platform parameter to TF-A Puma supports upstream TF-A and is configured to output serial on UART0 instead of the default UART2. Since U-Boot is properly configured to output on UART0, let's pass the DT to TF-A so there is no need for a custom TF-A to make the latter output to UART0 too. Cc: Quentin Schulz Signed-off-by: Quentin Schulz Reviewed-by: Kever Yang --- configs/puma-rk3399_defconfig | 1 - 1 file changed, 1 deletion(-) diff --git a/configs/puma-rk3399_defconfig b/configs/puma-rk3399_defconfig index 697f5eccef5..b632fa3dcf3 100644 --- a/configs/puma-rk3399_defconfig +++ b/configs/puma-rk3399_defconfig @@ -39,7 +39,6 @@ CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x200 CONFIG_SPL_I2C=y CONFIG_SPL_POWER=y CONFIG_SPL_SPI_LOAD=y -CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y CONFIG_TPL=y CONFIG_CMD_BOOTZ=y CONFIG_CMD_GPT=y -- cgit v1.3.1 From 3d17ee453348f49a975ea9a0c399258c01a160ed Mon Sep 17 00:00:00 2001 From: Johan Jonker Date: Thu, 22 Jun 2023 15:59:24 +0200 Subject: mtd: nand: raw: rockchip_nfc: copy hwecc PA data to oob_poi buffer Rockchip boot blocks are written per 4 x 512 byte sectors per page. Each page must have a page address (PA) pointer in OOB to the next page. Pages are written in a pattern depending on the NAND chip ID. This logic used to build a page pattern table is not fully disclosed and is not easy to fit in the MTD framework. The formula in rk_nfc_write_page_hwecc() function is not correct. Make hwecc and raw behavior identical. Generate boot block page address and pattern for hwecc in user space and copy PA data to/from the already reserved last 4 bytes before EEC in the chip->oob_poi data layout. Signed-off-by: Johan Jonker Reviewed-by: Kever Yang --- drivers/mtd/nand/raw/rockchip_nfc.c | 34 +++++++++++++++++++++------------- 1 file changed, 21 insertions(+), 13 deletions(-) diff --git a/drivers/mtd/nand/raw/rockchip_nfc.c b/drivers/mtd/nand/raw/rockchip_nfc.c index 5fcf6a6bfc3..274489ecbc6 100644 --- a/drivers/mtd/nand/raw/rockchip_nfc.c +++ b/drivers/mtd/nand/raw/rockchip_nfc.c @@ -525,7 +525,7 @@ static int rk_nfc_write_page_hwecc(struct mtd_info *mtd, int pages_per_blk = mtd->erasesize / mtd->writesize; int ret = 0, i, boot_rom_mode = 0; dma_addr_t dma_data, dma_oob; - u32 reg; + u32 tmp; u8 *oob; nand_prog_page_begin_op(chip, page, 0, NULL, 0); @@ -552,6 +552,13 @@ static int rk_nfc_write_page_hwecc(struct mtd_info *mtd, * * 0xFF 0xFF 0xFF 0xFF | BBM OOB1 OOB2 OOB3 | ... * + * The code here just swaps the first 4 bytes with the last + * 4 bytes without losing any data. + * + * The chip->oob_poi data layout: + * + * BBM OOB1 OOB2 OOB3 |......| PA0 PA1 PA2 PA3 + * * Configure the ECC algorithm supported by the boot ROM. */ if (page < (pages_per_blk * rknand->boot_blks)) { @@ -561,21 +568,17 @@ static int rk_nfc_write_page_hwecc(struct mtd_info *mtd, } for (i = 0; i < ecc->steps; i++) { - if (!i) { - reg = 0xFFFFFFFF; - } else { + if (!i) + oob = chip->oob_poi + (ecc->steps - 1) * NFC_SYS_DATA_SIZE; + else oob = chip->oob_poi + (i - 1) * NFC_SYS_DATA_SIZE; - reg = oob[0] | oob[1] << 8 | oob[2] << 16 | - oob[3] << 24; - } - if (!i && boot_rom_mode) - reg = (page & (pages_per_blk - 1)) * 4; + tmp = oob[0] | oob[1] << 8 | oob[2] << 16 | oob[3] << 24; if (nfc->cfg->type == NFC_V9) - nfc->oob_buf[i] = reg; + nfc->oob_buf[i] = tmp; else - nfc->oob_buf[i * (oob_step / 4)] = reg; + nfc->oob_buf[i * (oob_step / 4)] = tmp; } dma_data = dma_map_single((void *)nfc->page_buf, @@ -720,12 +723,17 @@ static int rk_nfc_read_page_hwecc(struct mtd_info *mtd, goto timeout_err; } - for (i = 1; i < ecc->steps; i++) { - oob = chip->oob_poi + (i - 1) * NFC_SYS_DATA_SIZE; + for (i = 0; i < ecc->steps; i++) { + if (!i) + oob = chip->oob_poi + (ecc->steps - 1) * NFC_SYS_DATA_SIZE; + else + oob = chip->oob_poi + (i - 1) * NFC_SYS_DATA_SIZE; + if (nfc->cfg->type == NFC_V9) tmp = nfc->oob_buf[i]; else tmp = nfc->oob_buf[i * (oob_step / 4)]; + *oob++ = (u8)tmp; *oob++ = (u8)(tmp >> 8); *oob++ = (u8)(tmp >> 16); -- cgit v1.3.1 From 52472504e9c48cc1b34e0942c0075cd111ea85f0 Mon Sep 17 00:00:00 2001 From: Jonas Karlman Date: Sun, 2 Jul 2023 10:43:57 +0000 Subject: rockchip: rk3568: Fix alloc space exhausted in SPL Current SYS_MALLOC_F_LEN of 0x2000 (8 KB) used in SPL is too small for some RK3568 boards. SPL will print following during boot: alloc space exhausted Increase the default SYS_MALLOC_F_LEN to 0x20000 (128 KB) to mitigate. Fixes: 2a950e3ba506 ("rockchip: Add rk3568 architecture core") Signed-off-by: Jonas Karlman Reviewed-by: Kever Yang --- arch/arm/mach-rockchip/rk3568/Kconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/mach-rockchip/rk3568/Kconfig b/arch/arm/mach-rockchip/rk3568/Kconfig index 94e04b79e7d..4424a3c47be 100644 --- a/arch/arm/mach-rockchip/rk3568/Kconfig +++ b/arch/arm/mach-rockchip/rk3568/Kconfig @@ -29,7 +29,7 @@ config SYS_SOC default "rk3568" config SYS_MALLOC_F_LEN - default 0x2000 + default 0x20000 source "board/rockchip/evb_rk3568/Kconfig" source "board/anbernic/rgxx3_rk3566/Kconfig" -- cgit v1.3.1 From 5b269ed404dc1ddaa8e1a100e466312d580769d7 Mon Sep 17 00:00:00 2001 From: Christopher Obbard Date: Mon, 3 Jul 2023 11:41:20 +0100 Subject: configs: rockchip: rock5b-rk3588: Enable CONFIG_PCI_INIT_R Enable CONFIG_PCI_INIT_R for rock5b pci enumeration during boot in order to autodetect the PCI ethernet NIC during the boot process. Signed-off-by: Christopher Obbard Reviewed-by: Kever Yang --- configs/rock5b-rk3588_defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/configs/rock5b-rk3588_defconfig b/configs/rock5b-rk3588_defconfig index 7618258ac5b..3976a6c0f05 100644 --- a/configs/rock5b-rk3588_defconfig +++ b/configs/rock5b-rk3588_defconfig @@ -35,6 +35,7 @@ CONFIG_OF_BOARD_SETUP=y CONFIG_DEFAULT_FDT_FILE="rockchip/rk3588-rock-5b.dtb" # CONFIG_DISPLAY_CPUINFO is not set CONFIG_DISPLAY_BOARDINFO_LATE=y +CONFIG_PCI_INIT_R=y CONFIG_SPL_MAX_SIZE=0x40000 CONFIG_SPL_PAD_TO=0x7f8000 CONFIG_SPL_HAS_BSS_LINKER_SECTION=y -- cgit v1.3.1 From fff7f5e97852e8a366c637505063b99485edab66 Mon Sep 17 00:00:00 2001 From: Alex Bee Date: Tue, 18 Jul 2023 16:57:11 +0200 Subject: rockchip: Support OP-TEE for ARM in FIT images created by binman CONFIG_SPL_OPTEE_IMAGE option is used during DRAM size detection for Rockchip ARM platform to indicate that an OP-TEE binary was already loaded and a Trusted Execution Environment (TEE) is available in order to block/reserve a memory-region for it. This adds a bunch of new `#if's` to u-boot-rockchip.dtsi to include the OP-TEE binary in the FIT image for ARM SOCs if CONFIG_SPL_OPTEE_IMAGE is selected. That makes it a little harder to read, but I opted for that, because all the duplicates in an extra ARM-OP-TEE-specfic .dtsi would be the greater evil, IMHO. Besides it's more likley being "forgotten" to sync when changes in u-boot-rockchip.dtsi are made. The no longer required rockchip-optee.dtsi and it's inclusions are dropped. The hardcoded load address is common across all OP-TEE implemenations for Rockchip (vendor and upstream). The OP-TEE-binary is non-optional if CONFIG_SPL_OPTEE_IMAGE is selected and there will be an error if the file does not exist and/or `TEE=` build option is missing. Signed-off-by: Alex Bee Reviewed-by: Kever Yang --- arch/arm/dts/rk3288-u-boot.dtsi | 1 - arch/arm/dts/rockchip-optee.dtsi | 64 --------------------------------------- arch/arm/dts/rockchip-u-boot.dtsi | 38 +++++++++++++++++++++-- 3 files changed, 35 insertions(+), 68 deletions(-) delete mode 100644 arch/arm/dts/rockchip-optee.dtsi diff --git a/arch/arm/dts/rk3288-u-boot.dtsi b/arch/arm/dts/rk3288-u-boot.dtsi index 19206988845..c4c5a2d225c 100644 --- a/arch/arm/dts/rk3288-u-boot.dtsi +++ b/arch/arm/dts/rk3288-u-boot.dtsi @@ -4,7 +4,6 @@ */ #include "rockchip-u-boot.dtsi" -#include "rockchip-optee.dtsi" / { aliases { diff --git a/arch/arm/dts/rockchip-optee.dtsi b/arch/arm/dts/rockchip-optee.dtsi deleted file mode 100644 index d84c10cf436..00000000000 --- a/arch/arm/dts/rockchip-optee.dtsi +++ /dev/null @@ -1,64 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright 2020 Google LLC - */ - -#include - -#if defined(CONFIG_HAS_ROM) && defined(CONFIG_FIT) -&binman { - itb { - filename = "u-boot.itb"; - fit { - fit,external-offset = ; - description = "FIT image with OP-TEE support"; - #address-cells = <1>; - - images { - uboot { - description = "U-Boot"; - type = "standalone"; - os = "U-Boot"; - arch = "arm"; - compression = "none"; - load = ; - - u-boot-nodtb { - }; - }; - optee { - description = "OP-TEE"; - type = "firmware"; - arch = "arm"; - os = "tee"; - compression = "none"; - load = <(CFG_SYS_SDRAM_BASE + 0x8400000)>; - entry = <(CFG_SYS_SDRAM_BASE + 0x8400000)>; - - blob-ext { - filename = "tee.bin"; - }; - }; - fdt { - description = CONFIG_SYS_BOARD; - type = "flat_dt"; - compression = "none"; - - u-boot-dtb { - }; - }; - }; - - configurations { - default = "conf"; - conf { - description = CONFIG_SYS_BOARD; - firmware = "optee"; - loadables = "uboot"; - fdt = "fdt"; - }; - }; - }; - }; -}; -#endif diff --git a/arch/arm/dts/rockchip-u-boot.dtsi b/arch/arm/dts/rockchip-u-boot.dtsi index 2878b80926c..be2658e8ef1 100644 --- a/arch/arm/dts/rockchip-u-boot.dtsi +++ b/arch/arm/dts/rockchip-u-boot.dtsi @@ -33,9 +33,13 @@ }; }; -#if defined(CONFIG_SPL_FIT) && defined(CONFIG_ARM64) +#if defined(CONFIG_SPL_FIT) && (defined(CONFIG_ARM64) || defined(CONFIG_SPL_OPTEE_IMAGE)) fit: fit { +#ifdef CONFIG_ARM64 description = "FIT image for U-Boot with bl31 (TF-A)"; +#else + description = "FIT image with OP-TEE"; +#endif #address-cells = <1>; fit,fdt-list = "of-list"; filename = "u-boot.itb"; @@ -44,10 +48,14 @@ offset = ; images { u-boot { - description = "U-Boot (64-bit)"; + description = "U-Boot"; type = "standalone"; os = "U-Boot"; +#ifdef CONFIG_ARM64 arch = "arm64"; +#else + arch = "arm"; +#endif compression = "none"; load = ; entry = ; @@ -60,6 +68,7 @@ #endif }; +#ifdef CONFIG_ARM64 @atf-SEQ { fit,operation = "split-elf"; description = "ARM Trusted Firmware"; @@ -99,6 +108,25 @@ }; #endif }; +#else + op-tee { + description = "OP-TEE"; + type = "tee"; + arch = "arm"; + os = "tee"; + compression = "none"; + load = <(CFG_SYS_SDRAM_BASE + 0x8400000)>; + entry = <(CFG_SYS_SDRAM_BASE + 0x8400000)>; + + tee-os { + }; +#ifdef CONFIG_SPL_FIT_SIGNATURE + hash { + algo = "sha256"; + }; +#endif + }; +#endif @fdt-SEQ { description = "fdt-NAME"; @@ -117,7 +145,11 @@ @config-SEQ { description = "NAME.dtb"; fdt = "fdt-SEQ"; +#ifdef CONFIG_ARM64 fit,firmware = "atf-1", "u-boot"; +#else + fit,firmware = "op-tee", "u-boot"; +#endif fit,loadables; }; }; @@ -150,7 +182,7 @@ }; }; -#ifdef CONFIG_ARM64 +#if defined(CONFIG_ARM64) || defined(CONFIG_SPL_OPTEE_IMAGE) fit { type = "blob"; filename = "u-boot.itb"; -- cgit v1.3.1 From fa86c3ee7472409858a12645a86675725458c1f3 Mon Sep 17 00:00:00 2001 From: Alex Bee Date: Tue, 18 Jul 2023 16:57:12 +0200 Subject: configs: evb-rk3229: Increase SPL_STACK_R_MALLOC_SIMPLE_LEN An OP-TEE FIT image will fail to extract in SPL because the malloc stack size is currently limited to 0x2000 for evb-rk3229 board. In SPL we do not have to care about size limitations, since we are no longer bound to SRAM limits after DRAM initialization has been done in TPL. Use the default value for CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN in order successfully unpack the FIT image. Signed-off-by: Alex Bee Reviewed-by: Kever Yang --- configs/evb-rk3229_defconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/configs/evb-rk3229_defconfig b/configs/evb-rk3229_defconfig index cf73afeded8..73015f098c2 100644 --- a/configs/evb-rk3229_defconfig +++ b/configs/evb-rk3229_defconfig @@ -31,7 +31,7 @@ CONFIG_SPL_PAD_TO=0x7f8000 CONFIG_SPL_NO_BSS_LIMIT=y # CONFIG_SPL_RAW_IMAGE_SUPPORT is not set CONFIG_SPL_STACK_R=y -CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x2000 +CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x100000 CONFIG_SPL_OPTEE_IMAGE=y CONFIG_SYS_BOOTM_LEN=0x4000000 CONFIG_CMD_GPT=y -- cgit v1.3.1 From 1d4b1078aa27ae4b8635cf1278474b0670ab8b31 Mon Sep 17 00:00:00 2001 From: Alex Bee Date: Tue, 18 Jul 2023 16:57:13 +0200 Subject: rockchip: RK322x: Select SPL_OPTEE_IMAGE For RK322x series ARM SoCs the OP-TEE is non-optional, as besides the TEE it also provides the PSCI implementation, which is expected to be available by upstream linux. Select CONFIG_SPL_OPTEE_IMAGE if an FIT image is built. Signed-off-by: Alex Bee Reviewed-by: Kever Yang --- arch/arm/mach-rockchip/Kconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/mach-rockchip/Kconfig b/arch/arm/mach-rockchip/Kconfig index edc413d12a0..07b5595dac8 100644 --- a/arch/arm/mach-rockchip/Kconfig +++ b/arch/arm/mach-rockchip/Kconfig @@ -106,6 +106,7 @@ config ROCKCHIP_RK322X imply ROCKCHIP_COMMON_BOARD imply SPL_SERIAL imply SPL_ROCKCHIP_COMMON_BOARD + select SPL_OPTEE_IMAGE if SPL_FIT imply TPL_SERIAL imply TPL_ROCKCHIP_COMMON_BOARD select TPL_LIBCOMMON_SUPPORT -- cgit v1.3.1 From f83e0a2cd8ac02c7828f771cdbae260261c0b69c Mon Sep 17 00:00:00 2001 From: Alex Bee Date: Tue, 18 Jul 2023 16:57:14 +0200 Subject: rockchip: evb_rk3229: Update/fix README This updates the evb_rk3229's README on howto create / use the FIT image created by binman. Also fix some wrong paths and update filenames which have changed in recent upstream optee-os versions. Signed-off-by: Alex Bee Reviewed-by: Kever Yang --- board/rockchip/evb_rk3229/README | 72 ++++++++++++++++++++++++++-------------- 1 file changed, 48 insertions(+), 24 deletions(-) diff --git a/board/rockchip/evb_rk3229/README b/board/rockchip/evb_rk3229/README index 9068225e272..a8dcc40f09b 100644 --- a/board/rockchip/evb_rk3229/README +++ b/board/rockchip/evb_rk3229/README @@ -13,25 +13,23 @@ Compile the OP-TEE > cd optee_os > make clean - > make CROSS_COMPILE_ta_arm32=arm-none-eabi- PLATFORM=rockchip-rk322x - Get tee.bin in this step, copy it to U-Boot root dir: - > cp out/arm-plat-rockchip/core/tee-pager.bin ../u-boot/tee.bin + > make CROSS_COMPILE=arm-none-eabi- PLATFORM=rockchip-rk322x + Get tee-raw.bin in this step, copy it to U-Boot root dir: + > cp out/arm-plat-rockchip/core/tee-raw.bin ../u-boot/tee.bin Compile the U-Boot ================== > cd ../u-boot - > export CROSS_COMPILE=arm-linux-gnueabihf- > make evb-rk3229_defconfig - > make - > make u-boot.itb + > TEE=tee.bin CROSS_COMPILE=arm-linux-gnueabihf- make - Get tpl/u-boot-tpl.bin, spl/u-boot-spl.bin and u-boot.itb in this step. + Get u-boot-rockchip.bin in this step. Compile the rkdeveloptool ======================= Follow instructions in latest README - > cd ../rkflashtool + > cd ../rkdeveloptool > autoreconf -i > ./configure > make @@ -42,30 +40,56 @@ Compile the rkdeveloptool Both origin binaries and Tool are ready now, choose either option 1 or option 2 to deploy U-Boot. -Package the image -================= - - > cd ../u-boot - > tools/mkimage -n rk322x -T rksd -d tpl/u-boot-spl.bin idbloader.img - > cat spl/u-boot-spl.bin >> idbloader.img - - Get idbloader.img in this step. - Flash the image to eMMC ======================= Power on(or reset with RESET KEY) with MASKROM KEY preesed, and then: > cd .. - > rkdeveloptool db rkbin/rk32/rk322x_loader_v1.04.232.bin - > rkdeveloptool wl 64 u-boot/idbloader.img - > rkdeveloptool wl 0x4000 u-boot/u-boot.itb - > rkdeveloptool rd + > rkdeveloptool/rkdeveloptool db rkbin/rk32/rk322x_loader_v1.04.232.bin + > rkdeveloptool/rkdeveloptool wl 64 u-boot/u-boot-rockchip.bin + > rkdeveloptool/rkdeveloptool rd Flash the image to SD card ========================== - > dd if=u-boot/idbloader.img of=/dev/sdb seek=64 - > dd if=u-boot/u-boot.itb of=/dev/sdb seek=16384 + > dd if=u-boot/u-boot-rockchip.bin of=/dev/sdb seek=64 + +You should be able to get U-Boot log message with OP-TEE boot info: + +U-Boot TPL 2023.07-00524-gf5346eba55-dirty (Jul 15 2023 - 14:22:51) +Trying to boot from BOOTROM +Returning to boot ROM... + +U-Boot SPL 2023.07-00524-gf5346eba55-dirty (Jul 15 2023 - 14:22:51 +0200) +Trying to boot from MMC1 +I/TC: +I/TC: Non-secure external DT found +I/TC: Switching console to device: /serial@11030000 +I/TC: OP-TEE version: 3.22.0-27-g893a762d1 (gcc version 10.3.1 20210621 (release) (15:10.3-2021.07-4)) #1 Sat Jul 15 12:14:36 UTC 2023 arm +I/TC: WARNING: This OP-TEE configuration might be insecure! +I/TC: WARNING: Please check https://optee.readthedocs.io/en/latest/architecture/porting_guidelines.html +I/TC: Primary CPU initializing +M/TC: Not protecting region 1: 0x68400000-0x68600000 +I/TC: Primary CPU switching to normal world boot + + +U-Boot 2023.07-00524-gf5346eba55-dirty (Jul 15 2023 - 14:22:51 +0200) + +Model: Rockchip RK3229 Evaluation board +DRAM: 1 GiB (effective 992 MiB) +Core: 113 devices, 16 uclasses, devicetree: separate +MMC: mmc@30000000: 1, mmc@30020000: 0 +Loading Environment from MMC... Card did not respond to voltage select! : -110 +*** Warning - No block device, using default environment + +In: serial@11030000 +Out: serial@11030000 +Err: serial@11030000 +Model: Rockchip RK3229 Evaluation board +Net: +Warning: ethernet@30200000 (eth0) using random MAC address - 72:65:2b:f1:c5:0a +eth0: ethernet@30200000 +Hit any key to stop autoboot: 0 +=> -You should be able to get U-Boot log message with OP-TEE boot info. For more detail, please reference to: http://opensource.rock-chips.com/wiki_Boot_option -- cgit v1.3.1 From 1379c7cfc901a04cfa552c702211191133fcc16a Mon Sep 17 00:00:00 2001 From: Christopher Obbard Date: Wed, 19 Jul 2023 17:33:56 +0100 Subject: arm: rockchip: sync ROCK Pi 4 SoCs from Linux To prepare for ROCK 4 SE support, changes are needed to the common ROCK Pi 4 devicetree to move the OPP from the common devicetree to individual board devicetrees. Sync the Rockchip RK3399 ROCK Pi 4-related DTs from Linux to gain from these changes. Kernel tag: next-20230719 Kernel commits: cfa12c32b96f ("arm64: dts: rockchip: correct wifi interrupt flag in Rock \ Pi 4B") cee572756aa2 ("arm64: dts: rockchip: Disable HS400 for eMMC on ROCK Pi 4") 2bd1d2dd808c ("arm64: dts: rockchip: Disable HS400 for eMMC on ROCK 4C+") fd2762a62646 ("arm64: dts: rockchip: Move OPP table from ROCK Pi 4 dtsi") Signed-off-by: Christopher Obbard Reviewed-by: Kever Yang --- arch/arm/dts/rk3399-rock-4c-plus.dts | 3 +-- arch/arm/dts/rk3399-rock-pi-4.dtsi | 5 ++--- arch/arm/dts/rk3399-rock-pi-4a.dts | 1 + arch/arm/dts/rk3399-rock-pi-4c.dts | 1 + 4 files changed, 5 insertions(+), 5 deletions(-) diff --git a/arch/arm/dts/rk3399-rock-4c-plus.dts b/arch/arm/dts/rk3399-rock-4c-plus.dts index 028eb508ae3..8bfd5f88d1e 100644 --- a/arch/arm/dts/rk3399-rock-4c-plus.dts +++ b/arch/arm/dts/rk3399-rock-4c-plus.dts @@ -548,9 +548,8 @@ &sdhci { max-frequency = <150000000>; bus-width = <8>; - mmc-hs400-1_8v; + mmc-hs200-1_8v; non-removable; - mmc-hs400-enhanced-strobe; status = "okay"; }; diff --git a/arch/arm/dts/rk3399-rock-pi-4.dtsi b/arch/arm/dts/rk3399-rock-pi-4.dtsi index 907071d4fe8..b1b7f4ffb1d 100644 --- a/arch/arm/dts/rk3399-rock-pi-4.dtsi +++ b/arch/arm/dts/rk3399-rock-pi-4.dtsi @@ -9,7 +9,6 @@ #include #include #include "rk3399.dtsi" -#include "rk3399-opp.dtsi" / { aliases { @@ -645,9 +644,9 @@ }; &sdhci { + max-frequency = <150000000>; bus-width = <8>; - mmc-hs400-1_8v; - mmc-hs400-enhanced-strobe; + mmc-hs200-1_8v; non-removable; status = "okay"; }; diff --git a/arch/arm/dts/rk3399-rock-pi-4a.dts b/arch/arm/dts/rk3399-rock-pi-4a.dts index 89f2af5e111..931334aa3d6 100644 --- a/arch/arm/dts/rk3399-rock-pi-4a.dts +++ b/arch/arm/dts/rk3399-rock-pi-4a.dts @@ -6,6 +6,7 @@ /dts-v1/; #include "rk3399-rock-pi-4.dtsi" +#include "rk3399-opp.dtsi" / { model = "Radxa ROCK Pi 4A"; diff --git a/arch/arm/dts/rk3399-rock-pi-4c.dts b/arch/arm/dts/rk3399-rock-pi-4c.dts index 4053ba72618..d32efab74e9 100644 --- a/arch/arm/dts/rk3399-rock-pi-4c.dts +++ b/arch/arm/dts/rk3399-rock-pi-4c.dts @@ -7,6 +7,7 @@ /dts-v1/; #include "rk3399-rock-pi-4.dtsi" +#include "rk3399-opp.dtsi" / { model = "Radxa ROCK Pi 4C"; -- cgit v1.3.1 From 0022461ba651d28b35301f0d3bb37af6cd6df431 Mon Sep 17 00:00:00 2001 From: Christopher Obbard Date: Wed, 19 Jul 2023 17:33:57 +0100 Subject: arm: rockchip: Add Radxa ROCK 4SE Add board-specific devicetree/config for the RK3399T-based Radxa ROCK 4SE board. This board offers similar peripherals in a similar form-factor to the existing ROCK Pi 4B but uses the cost-optimised RK3399T processor (which has different OPP table than the RK3399) and other minimal hardware changes. Kernel tag: next-20230719 Kernel commits: - 86a0e14a82ea ("arm64: dts: rockchip: Add Radxa ROCK 4SE") Signed-off-by: Christopher Obbard Reviewed-by: Kever Yang --- arch/arm/dts/Makefile | 1 + arch/arm/dts/rk3399-rock-4se-u-boot.dtsi | 6 ++ arch/arm/dts/rk3399-rock-4se.dts | 65 ++++++++++++++++++++ board/rockchip/evb_rk3399/MAINTAINERS | 6 ++ configs/rock-4se-rk3399_defconfig | 100 +++++++++++++++++++++++++++++++ doc/board/rockchip/rockchip.rst | 2 +- 6 files changed, 179 insertions(+), 1 deletion(-) create mode 100644 arch/arm/dts/rk3399-rock-4se-u-boot.dtsi create mode 100644 arch/arm/dts/rk3399-rock-4se.dts create mode 100644 configs/rock-4se-rk3399_defconfig diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index d1ac8acce5c..f758ced7b71 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -161,6 +161,7 @@ dtb-$(CONFIG_ROCKCHIP_RK3399) += \ rk3399-roc-pc.dtb \ rk3399-roc-pc-mezzanine.dtb \ rk3399-rock-4c-plus.dtb \ + rk3399-rock-4se.dtb \ rk3399-rock-pi-4a.dtb \ rk3399-rock-pi-4c.dtb \ rk3399-rock960.dtb \ diff --git a/arch/arm/dts/rk3399-rock-4se-u-boot.dtsi b/arch/arm/dts/rk3399-rock-4se-u-boot.dtsi new file mode 100644 index 00000000000..85ee5770add --- /dev/null +++ b/arch/arm/dts/rk3399-rock-4se-u-boot.dtsi @@ -0,0 +1,6 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2019 Jagan Teki + */ + +#include "rk3399-rock-pi-4-u-boot.dtsi" diff --git a/arch/arm/dts/rk3399-rock-4se.dts b/arch/arm/dts/rk3399-rock-4se.dts new file mode 100644 index 00000000000..7cfc198bbae --- /dev/null +++ b/arch/arm/dts/rk3399-rock-4se.dts @@ -0,0 +1,65 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2019 Akash Gajjar + * Copyright (c) 2019 Pragnesh Patel + */ + +/dts-v1/; +#include "rk3399-rock-pi-4.dtsi" +#include "rk3399-t-opp.dtsi" + +/ { + model = "Radxa ROCK 4SE"; + compatible = "radxa,rock-4se", "rockchip,rk3399"; + + aliases { + mmc2 = &sdio0; + }; +}; + +&pinctrl { + usb2 { + vcc5v0_host_en: vcc5v0-host-en { + rockchip,pins = <4 RK_PD1 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +}; + +&sdio0 { + status = "okay"; + + brcmf: wifi@1 { + compatible = "brcm,bcm4329-fmac"; + reg = <1>; + interrupt-parent = <&gpio0>; + interrupts = ; + interrupt-names = "host-wake"; + pinctrl-names = "default"; + pinctrl-0 = <&wifi_host_wake_l>; + }; +}; + +&uart0 { + status = "okay"; + + bluetooth { + compatible = "brcm,bcm4345c5"; + clocks = <&rk808 1>; + clock-names = "lpo"; + device-wakeup-gpios = <&gpio2 RK_PD3 GPIO_ACTIVE_HIGH>; + host-wakeup-gpios = <&gpio0 RK_PA4 GPIO_ACTIVE_HIGH>; + shutdown-gpios = <&gpio0 RK_PB1 GPIO_ACTIVE_HIGH>; + max-speed = <1500000>; + pinctrl-names = "default"; + pinctrl-0 = <&bt_host_wake_l &bt_wake_l &bt_enable_h>; + vbat-supply = <&vcc3v3_sys>; + vddio-supply = <&vcc_1v8>; + }; +}; + +&vcc5v0_host { + enable-active-high; + gpio = <&gpio4 RK_PD1 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&vcc5v0_host_en>; +}; diff --git a/board/rockchip/evb_rk3399/MAINTAINERS b/board/rockchip/evb_rk3399/MAINTAINERS index de1dc64a962..cb44bc9fda4 100644 --- a/board/rockchip/evb_rk3399/MAINTAINERS +++ b/board/rockchip/evb_rk3399/MAINTAINERS @@ -86,6 +86,12 @@ S: Maintained F: configs/rock-4c-plus-rk3399_defconfig F: arch/arm/dts/rk3399-rock-4c-plus.dts +ROCK-4SE +M: Christopher Obbard +S: Maintained +F: configs/rock-4se-rk3399_defconfig +F: arch/arm/dts/rk3399-rock-4se-u-boot.dtsi + ROCK-PI-4 M: Akash Gajjar M: Jagan Teki diff --git a/configs/rock-4se-rk3399_defconfig b/configs/rock-4se-rk3399_defconfig new file mode 100644 index 00000000000..9abe8bf8535 --- /dev/null +++ b/configs/rock-4se-rk3399_defconfig @@ -0,0 +1,100 @@ +CONFIG_ARM=y +CONFIG_SKIP_LOWLEVEL_INIT=y +CONFIG_COUNTER_FREQUENCY=24000000 +CONFIG_ARCH_ROCKCHIP=y +CONFIG_TEXT_BASE=0x00200000 +CONFIG_NR_DRAM_BANKS=1 +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x300000 +CONFIG_ENV_OFFSET=0x3F8000 +CONFIG_DEFAULT_DEVICE_TREE="rk3399-rock-4se" +CONFIG_OF_LIBFDT_OVERLAY=y +CONFIG_DM_RESET=y +CONFIG_ROCKCHIP_RK3399=y +CONFIG_TARGET_EVB_RK3399=y +CONFIG_SPL_STACK=0x400000 +CONFIG_DEBUG_UART_BASE=0xFF1A0000 +CONFIG_DEBUG_UART_CLOCK=24000000 +CONFIG_SYS_LOAD_ADDR=0x800800 +CONFIG_PCI=y +CONFIG_DEBUG_UART=y +# CONFIG_ANDROID_BOOT_IMAGE is not set +CONFIG_SPL_FIT_SIGNATURE=y +CONFIG_LEGACY_IMAGE_FORMAT=y +CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-rock-4se.dtb" +CONFIG_DISPLAY_BOARDINFO_LATE=y +CONFIG_MISC_INIT_R=y +CONFIG_SPL_MAX_SIZE=0x2e000 +CONFIG_SPL_PAD_TO=0x7f8000 +CONFIG_SPL_HAS_BSS_LINKER_SECTION=y +CONFIG_SPL_BSS_START_ADDR=0x400000 +CONFIG_SPL_BSS_MAX_SIZE=0x2000 +# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set +# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set +CONFIG_SPL_STACK_R=y +CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x10000 +CONFIG_TPL=y +CONFIG_CMD_BOOTZ=y +CONFIG_CMD_NVEDIT_EFI=y +CONFIG_CMD_DFU=y +CONFIG_CMD_GPT=y +CONFIG_CMD_MMC=y +CONFIG_CMD_PCI=y +CONFIG_CMD_USB=y +CONFIG_CMD_ROCKUSB=y +CONFIG_CMD_USB_MASS_STORAGE=y +# CONFIG_CMD_SETEXPR is not set +CONFIG_CMD_EFIDEBUG=y +CONFIG_CMD_TIME=y +CONFIG_SPL_OF_CONTROL=y +CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" +CONFIG_ENV_IS_IN_MMC=y +CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_DFU_MMC=y +CONFIG_ROCKCHIP_GPIO=y +CONFIG_SYS_I2C_ROCKCHIP=y +CONFIG_MISC=y +CONFIG_ROCKCHIP_EFUSE=y +CONFIG_MMC_DW=y +CONFIG_MMC_DW_ROCKCHIP=y +CONFIG_MMC_SDHCI=y +CONFIG_MMC_SDHCI_SDMA=y +CONFIG_MMC_SDHCI_ROCKCHIP=y +CONFIG_ETH_DESIGNWARE=y +CONFIG_GMAC_ROCKCHIP=y +CONFIG_NVME_PCI=y +CONFIG_PHY_ROCKCHIP_INNO_USB2=y +CONFIG_PHY_ROCKCHIP_TYPEC=y +CONFIG_PMIC_RK8XX=y +CONFIG_REGULATOR_PWM=y +CONFIG_REGULATOR_RK8XX=y +CONFIG_PWM_ROCKCHIP=y +CONFIG_RAM_ROCKCHIP_LPDDR4=y +CONFIG_BAUDRATE=1500000 +CONFIG_DEBUG_UART_SHIFT=2 +CONFIG_SYS_NS16550_MEM32=y +CONFIG_SYSRESET=y +CONFIG_USB=y +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_XHCI_DWC3=y +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_EHCI_GENERIC=y +CONFIG_USB_DWC3=y +CONFIG_USB_DWC3_GENERIC=y +CONFIG_USB_KEYBOARD=y +CONFIG_USB_HOST_ETHER=y +CONFIG_USB_ETHER_ASIX=y +CONFIG_USB_ETHER_ASIX88179=y +CONFIG_USB_ETHER_MCS7830=y +CONFIG_USB_ETHER_RTL8152=y +CONFIG_USB_ETHER_SMSC95XX=y +CONFIG_USB_GADGET=y +CONFIG_USB_FUNCTION_ROCKUSB=y +CONFIG_VIDEO=y +CONFIG_DISPLAY=y +CONFIG_VIDEO_ROCKCHIP=y +CONFIG_DISPLAY_ROCKCHIP_HDMI=y +CONFIG_SPL_TINY_MEMSET=y +CONFIG_ERRNO_STR=y +CONFIG_EFI_CAPSULE_ON_DISK=y +CONFIG_EFI_CAPSULE_FIRMWARE_RAW=y diff --git a/doc/board/rockchip/rockchip.rst b/doc/board/rockchip/rockchip.rst index d3022021e4c..78afd49e387 100644 --- a/doc/board/rockchip/rockchip.rst +++ b/doc/board/rockchip/rockchip.rst @@ -84,7 +84,7 @@ List of mainline supported Rockchip boards: - Orange Pi RK3399 (orangepi-rk3399) - Pine64 RockPro64 (rockpro64-rk3399) - Radxa ROCK 4C+ (rock-4c-plus-rk3399) - - Radxa ROCK 4SE (rock-pi-4-rk3399) + - Radxa ROCK 4SE (rock-4se-rk3399) - Radxa ROCK Pi 4A/B/A+/B+ (rock-pi-4-rk3399) - Radxa ROCK Pi 4C (rock-pi-4c-rk3399) - Rockchip Evb-RK3399 (evb_rk3399) -- cgit v1.3.1 From e5b33200f8fcc79c8555dd0b852827912abc0b04 Mon Sep 17 00:00:00 2001 From: Alper Nebi Yasak Date: Fri, 21 Jul 2023 11:46:00 +0300 Subject: rockchip: veyron: Enable Winbond SPI flash Some veyron boards seem to have Winbond SPI flash chips instead of GigaDevice ones. At the very least, coreboot builds for veyron boards have them enabled [1]. Enable support for them here as well. [1] https://review.coreboot.org/c/coreboot/+/9719 Signed-off-by: Alper Nebi Yasak Reviewed-by: Simon Glass Reviewed-by: Kever Yang --- configs/chromebit_mickey_defconfig | 1 + configs/chromebook_jerry_defconfig | 1 + configs/chromebook_minnie_defconfig | 1 + configs/chromebook_speedy_defconfig | 1 + 4 files changed, 4 insertions(+) diff --git a/configs/chromebit_mickey_defconfig b/configs/chromebit_mickey_defconfig index d4302353c5d..253ef99f993 100644 --- a/configs/chromebit_mickey_defconfig +++ b/configs/chromebit_mickey_defconfig @@ -81,6 +81,7 @@ CONFIG_MMC_DW_ROCKCHIP=y CONFIG_MTD=y CONFIG_SF_DEFAULT_BUS=2 CONFIG_SPI_FLASH_GIGADEVICE=y +CONFIG_SPI_FLASH_WINBOND=y CONFIG_PINCTRL=y CONFIG_PINCONF=y CONFIG_SPL_PINCTRL=y diff --git a/configs/chromebook_jerry_defconfig b/configs/chromebook_jerry_defconfig index 1a54986d089..3172f04a264 100644 --- a/configs/chromebook_jerry_defconfig +++ b/configs/chromebook_jerry_defconfig @@ -84,6 +84,7 @@ CONFIG_MMC_DW_ROCKCHIP=y CONFIG_MTD=y CONFIG_SF_DEFAULT_BUS=2 CONFIG_SPI_FLASH_GIGADEVICE=y +CONFIG_SPI_FLASH_WINBOND=y CONFIG_PINCTRL=y CONFIG_PINCONF=y CONFIG_SPL_PINCTRL=y diff --git a/configs/chromebook_minnie_defconfig b/configs/chromebook_minnie_defconfig index 73ab2f62af5..25a56f45fe6 100644 --- a/configs/chromebook_minnie_defconfig +++ b/configs/chromebook_minnie_defconfig @@ -83,6 +83,7 @@ CONFIG_MMC_DW_ROCKCHIP=y CONFIG_MTD=y CONFIG_SF_DEFAULT_BUS=2 CONFIG_SPI_FLASH_GIGADEVICE=y +CONFIG_SPI_FLASH_WINBOND=y CONFIG_PINCTRL=y CONFIG_PINCONF=y CONFIG_SPL_PINCTRL=y diff --git a/configs/chromebook_speedy_defconfig b/configs/chromebook_speedy_defconfig index 06437aae18d..ff2a12b25c3 100644 --- a/configs/chromebook_speedy_defconfig +++ b/configs/chromebook_speedy_defconfig @@ -82,6 +82,7 @@ CONFIG_MMC_DW_ROCKCHIP=y CONFIG_MTD=y CONFIG_SF_DEFAULT_BUS=2 CONFIG_SPI_FLASH_GIGADEVICE=y +CONFIG_SPI_FLASH_WINBOND=y CONFIG_PINCTRL=y CONFIG_PINCONF=y CONFIG_SPL_PINCTRL=y -- cgit v1.3.1 From 5e030632d49367944879e17a6d73828be22edd55 Mon Sep 17 00:00:00 2001 From: Jonas Karlman Date: Sat, 22 Jul 2023 13:30:15 +0000 Subject: core: read: add dev_read_addr_size_index_ptr function Add dev_read_addr_size_index_ptr function with the same functionality as dev_read_addr_size_index, but instead a return pointer is given. Use map_sysmem() function as cast for the return. Signed-off-by: Jonas Karlman Reviewed-by: Kever Yang --- drivers/core/read.c | 11 +++++++++++ include/dm/read.h | 21 +++++++++++++++++++++ 2 files changed, 32 insertions(+) diff --git a/drivers/core/read.c b/drivers/core/read.c index 5749473a6ca..49066b59cda 100644 --- a/drivers/core/read.c +++ b/drivers/core/read.c @@ -150,6 +150,17 @@ fdt_addr_t dev_read_addr_size_index(const struct udevice *dev, int index, return devfdt_get_addr_size_index(dev, index, size); } +void *dev_read_addr_size_index_ptr(const struct udevice *dev, int index, + fdt_size_t *size) +{ + fdt_addr_t addr = dev_read_addr_size_index(dev, index, size); + + if (addr == FDT_ADDR_T_NONE) + return NULL; + + return map_sysmem(addr, 0); +} + void *dev_remap_addr_index(const struct udevice *dev, int index) { fdt_addr_t addr = dev_read_addr_index(dev, index); diff --git a/include/dm/read.h b/include/dm/read.h index 137f2a52a29..c2615f72f40 100644 --- a/include/dm/read.h +++ b/include/dm/read.h @@ -246,6 +246,20 @@ void *dev_read_addr_index_ptr(const struct udevice *dev, int index); fdt_addr_t dev_read_addr_size_index(const struct udevice *dev, int index, fdt_size_t *size); +/** + * dev_read_addr_size_index_ptr() - Get the indexed reg property of a device + * as a pointer + * + * @dev: Device to read from + * @index: the 'reg' property can hold a list of pairs + * and @index is used to select which one is required + * @size: place to put size value (on success) + * + * Return: pointer or NULL if not found + */ +void *dev_read_addr_size_index_ptr(const struct udevice *dev, int index, + fdt_size_t *size); + /** * dev_remap_addr_index() - Get the indexed reg property of a device * as a memory-mapped I/O pointer @@ -952,6 +966,13 @@ static inline fdt_addr_t dev_read_addr_size_index(const struct udevice *dev, return devfdt_get_addr_size_index(dev, index, size); } +static inline void *dev_read_addr_size_index_ptr(const struct udevice *dev, + int index, + fdt_size_t *size) +{ + return devfdt_get_addr_size_index_ptr(dev, index, size); +} + static inline fdt_addr_t dev_read_addr_name(const struct udevice *dev, const char *name) { -- cgit v1.3.1 From bed7b2f00b1346f712f849d53c72fa8642601115 Mon Sep 17 00:00:00 2001 From: Jonas Karlman Date: Sat, 22 Jul 2023 13:30:16 +0000 Subject: pci: pcie_dw_rockchip: Get config region from reg prop Get the config region to use from the reg prop. Also update the referenced region index used in comment. Signed-off-by: Jonas Karlman Reviewed-by: Kever Yang --- drivers/pci/pcie_dw_common.c | 10 ++++++---- drivers/pci/pcie_dw_rockchip.c | 7 +++++++ 2 files changed, 13 insertions(+), 4 deletions(-) diff --git a/drivers/pci/pcie_dw_common.c b/drivers/pci/pcie_dw_common.c index 9f8b016d114..74fb6df412c 100644 --- a/drivers/pci/pcie_dw_common.c +++ b/drivers/pci/pcie_dw_common.c @@ -141,9 +141,9 @@ static uintptr_t set_cfg_address(struct pcie_dw *pcie, /* * Not accessing root port configuration space? - * Region #0 is used for Outbound CFG space access. + * Region #1 is used for Outbound CFG space access. * Direction = Outbound - * Region Index = 0 + * Region Index = 1 */ d = PCI_MASK_BUS(d); d = PCI_ADD_BUS(bus, d); @@ -328,8 +328,10 @@ void pcie_dw_setup_host(struct pcie_dw *pci) pci->prefetch.bus_start = hose->regions[ret].bus_start; /* PREFETCH_bus_addr */ pci->prefetch.size = hose->regions[ret].size; /* PREFETCH size */ } else if (hose->regions[ret].flags == PCI_REGION_SYS_MEMORY) { - pci->cfg_base = (void *)(pci->io.phys_start - pci->io.size); - pci->cfg_size = pci->io.size; + if (!pci->cfg_base) { + pci->cfg_base = (void *)(pci->io.phys_start - pci->io.size); + pci->cfg_size = pci->io.size; + } } else { dev_err(pci->dev, "invalid flags type!\n"); } diff --git a/drivers/pci/pcie_dw_rockchip.c b/drivers/pci/pcie_dw_rockchip.c index 6da618055cb..83737e62bc6 100644 --- a/drivers/pci/pcie_dw_rockchip.c +++ b/drivers/pci/pcie_dw_rockchip.c @@ -366,6 +366,13 @@ static int rockchip_pcie_parse_dt(struct udevice *dev) dev_dbg(dev, "APB address is 0x%p\n", priv->apb_base); + priv->dw.cfg_base = dev_read_addr_size_index_ptr(dev, 2, + &priv->dw.cfg_size); + if (!priv->dw.cfg_base) + return -EINVAL; + + dev_dbg(dev, "CFG address is 0x%p\n", priv->dw.cfg_base); + ret = gpio_request_by_name(dev, "reset-gpios", 0, &priv->rst_gpio, GPIOD_IS_OUT); if (ret) { -- cgit v1.3.1 From 8b001ee59a9d4a6246098c8bc5bb894a752e7c0b Mon Sep 17 00:00:00 2001 From: Jonas Karlman Date: Sat, 22 Jul 2023 13:30:18 +0000 Subject: pci: pcie_dw_rockchip: Use regulator_set_enable_if_allowed The vpcie3v3 regulator is typically a fixed regulator controlled using gpio. Change to use enable and disable calls on the regulator instead of trying to set a voltage value. Also remove the delay to match linux driver, for a fixed regulator the startup-delay-us prop can be used in case a startup delay is needed. Limited testing on ROCK 3A, ROCK 5B, Quartz64, Odroid-M1 has shown that this delay was not needed. Signed-off-by: Jonas Karlman Reviewed-by: Kever Yang --- drivers/pci/pcie_dw_rockchip.c | 17 +++++++---------- 1 file changed, 7 insertions(+), 10 deletions(-) diff --git a/drivers/pci/pcie_dw_rockchip.c b/drivers/pci/pcie_dw_rockchip.c index 83737e62bc6..1b8a1409f6d 100644 --- a/drivers/pci/pcie_dw_rockchip.c +++ b/drivers/pci/pcie_dw_rockchip.c @@ -288,21 +288,16 @@ static int rockchip_pcie_init_port(struct udevice *dev) struct rk_pcie *priv = dev_get_priv(dev); /* Set power and maybe external ref clk input */ - if (priv->vpcie3v3) { - ret = regulator_set_value(priv->vpcie3v3, 3300000); - if (ret) { - dev_err(priv->dw.dev, "failed to enable vpcie3v3 (ret=%d)\n", - ret); - return ret; - } + ret = regulator_set_enable_if_allowed(priv->vpcie3v3, true); + if (ret && ret != -ENOSYS) { + dev_err(dev, "failed to enable vpcie3v3 (ret=%d)\n", ret); + return ret; } - udelay(MACRO_US * 1000); - ret = generic_phy_init(&priv->phy); if (ret) { dev_err(dev, "failed to init phy (ret=%d)\n", ret); - return ret; + goto err_disable_regulator; } ret = generic_phy_power_on(&priv->phy); @@ -345,6 +340,8 @@ err_power_off_phy: generic_phy_power_off(&priv->phy); err_exit_phy: generic_phy_exit(&priv->phy); +err_disable_regulator: + regulator_set_enable_if_allowed(priv->vpcie3v3, false); return ret; } -- cgit v1.3.1 From 7ce186ada2ce1ece344dacc20244fb91866e435b Mon Sep 17 00:00:00 2001 From: Jonas Karlman Date: Sat, 22 Jul 2023 13:30:19 +0000 Subject: pci: pcie_dw_rockchip: Speed up link probe Use a similar pattern and delay values as the linux mainline driver to speed up failing when nothing is connected. Reduce fail speed from around 5+ seconds down to around one second on a Radxa ROCK 3 Model A, where pcie2x1 is probed before pcie3x2 M2 slot. Signed-off-by: Jonas Karlman Reviewed-by: Kever Yang --- drivers/pci/pcie_dw_rockchip.c | 68 +++++++++++++++++++++++------------------- 1 file changed, 37 insertions(+), 31 deletions(-) diff --git a/drivers/pci/pcie_dw_rockchip.c b/drivers/pci/pcie_dw_rockchip.c index 1b8a1409f6d..82a8b9c96e2 100644 --- a/drivers/pci/pcie_dw_rockchip.c +++ b/drivers/pci/pcie_dw_rockchip.c @@ -61,9 +61,6 @@ struct rk_pcie { #define PCIE_CLIENT_DBG_TRANSITION_DATA 0xffff0000 #define PCIE_CLIENT_DBF_EN 0xffff0003 -/* Parameters for the waiting for #perst signal */ -#define MACRO_US 1000 - static int rk_pcie_read(void __iomem *addr, int size, u32 *val) { if ((uintptr_t)addr & (size - 1)) { @@ -242,43 +239,46 @@ static int rk_pcie_link_up(struct rk_pcie *priv, u32 cap_speed) /* DW pre link configurations */ rk_pcie_configure(priv, cap_speed); - /* Rest the device */ - if (dm_gpio_is_valid(&priv->rst_gpio)) { - dm_gpio_set_value(&priv->rst_gpio, 0); - /* - * Minimal is 100ms from spec but we see - * some wired devices need much more, such as 600ms. - * Add a enough delay to cover all cases. - */ - udelay(MACRO_US * 1000); - dm_gpio_set_value(&priv->rst_gpio, 1); - } - rk_pcie_disable_ltssm(priv); rk_pcie_link_status_clear(priv); rk_pcie_enable_debug(priv); + /* Reset the device */ + if (dm_gpio_is_valid(&priv->rst_gpio)) + dm_gpio_set_value(&priv->rst_gpio, 0); + /* Enable LTSSM */ rk_pcie_enable_ltssm(priv); - for (retries = 0; retries < 5; retries++) { - if (is_link_up(priv)) { - dev_info(priv->dw.dev, "PCIe Link up, LTSSM is 0x%x\n", - rk_pcie_readl_apb(priv, PCIE_CLIENT_LTSSM_STATUS)); - rk_pcie_debug_dump(priv); - return 0; - } - - dev_info(priv->dw.dev, "PCIe Linking... LTSSM is 0x%x\n", - rk_pcie_readl_apb(priv, PCIE_CLIENT_LTSSM_STATUS)); - rk_pcie_debug_dump(priv); - udelay(MACRO_US * 1000); + /* + * PCIe requires the refclk to be stable for 100ms prior to releasing + * PERST. See table 2-4 in section 2.6.2 AC Specifications of the PCI + * Express Card Electromechanical Specification, 1.1. However, we don't + * know if the refclk is coming from RC's PHY or external OSC. If it's + * from RC, so enabling LTSSM is the just right place to release #PERST. + */ + mdelay(100); + if (dm_gpio_is_valid(&priv->rst_gpio)) + dm_gpio_set_value(&priv->rst_gpio, 1); + + /* Check if the link is up or not */ + for (retries = 0; retries < 10; retries++) { + if (is_link_up(priv)) + break; + + mdelay(100); + } + + if (retries >= 10) { + dev_err(priv->dw.dev, "PCIe-%d Link Fail\n", + dev_seq(priv->dw.dev)); + return -EIO; } - dev_err(priv->dw.dev, "PCIe-%d Link Fail\n", dev_seq(priv->dw.dev)); - /* Link maybe in Gen switch recovery but we need to wait more 1s */ - udelay(MACRO_US * 1000); - return -EIO; + dev_info(priv->dw.dev, "PCIe Link up, LTSSM is 0x%x\n", + rk_pcie_readl_apb(priv, PCIE_CLIENT_LTSSM_STATUS)); + rk_pcie_debug_dump(priv); + return 0; } static int rockchip_pcie_init_port(struct udevice *dev) @@ -287,6 +287,12 @@ static int rockchip_pcie_init_port(struct udevice *dev) u32 val; struct rk_pcie *priv = dev_get_priv(dev); + ret = reset_assert_bulk(&priv->rsts); + if (ret) { + dev_err(dev, "failed to assert resets (ret=%d)\n", ret); + return ret; + } + /* Set power and maybe external ref clk input */ ret = regulator_set_enable_if_allowed(priv->vpcie3v3, true); if (ret && ret != -ENOSYS) { -- cgit v1.3.1 From bc6b94b5788677c3633e0331203578ffa706ff4b Mon Sep 17 00:00:00 2001 From: Jon Lin Date: Sat, 22 Jul 2023 13:30:20 +0000 Subject: pci: pcie_dw_rockchip: Disable unused BARs of the root complex The Root Complex BARs default to claim the full 1 GiB memory region on RK3568, leaving no space for any attached device. Fix this by disable the unused BAR 0 and BAR 1 of the RC. Signed-off-by: Jon Lin [jonas@kwiboo.se: Move to rk_pcie_configure and use PCI_BASE_ADDRESS_0/1 const] Signed-off-by: Jonas Karlman Reviewed-by: Kever Yang --- drivers/pci/pcie_dw_rockchip.c | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/drivers/pci/pcie_dw_rockchip.c b/drivers/pci/pcie_dw_rockchip.c index 82a8b9c96e2..1a35fae5c3a 100644 --- a/drivers/pci/pcie_dw_rockchip.c +++ b/drivers/pci/pcie_dw_rockchip.c @@ -61,6 +61,8 @@ struct rk_pcie { #define PCIE_CLIENT_DBG_TRANSITION_DATA 0xffff0000 #define PCIE_CLIENT_DBF_EN 0xffff0003 +#define PCIE_TYPE0_HDR_DBI2_OFFSET 0x100000 + static int rk_pcie_read(void __iomem *addr, int size, u32 *val) { if ((uintptr_t)addr & (size - 1)) { @@ -158,6 +160,12 @@ static void rk_pcie_configure(struct rk_pcie *pci, u32 cap_speed) { dw_pcie_dbi_write_enable(&pci->dw, true); + /* Disable BAR 0 and BAR 1 */ + writel(0, pci->dw.dbi_base + PCIE_TYPE0_HDR_DBI2_OFFSET + + PCI_BASE_ADDRESS_0); + writel(0, pci->dw.dbi_base + PCIE_TYPE0_HDR_DBI2_OFFSET + + PCI_BASE_ADDRESS_1); + clrsetbits_le32(pci->dw.dbi_base + PCIE_LINK_CAPABILITY, TARGET_LINK_SPEED_MASK, cap_speed); -- cgit v1.3.1 From f7b8a84a29833b6e6ddac67920d688330b299fa8 Mon Sep 17 00:00:00 2001 From: Jonas Karlman Date: Sat, 22 Jul 2023 13:30:21 +0000 Subject: regulator: fixed: Add support for gpios prop The commit 12df2c182ccb ("regulator: dt-bindings: fixed-regulator: allow gpios property") in linux v6.3-rc1 added support for use of either a gpios or gpio prop with a fixed-regulator. This adds support for the new gpios prop to the fixed-regulator driver. gpios prop is used by vcc3v3-pcie-regulator on Radxa ROCK 3 Model A. Signed-off-by: Jonas Karlman Reviewed-by: Kever Yang --- drivers/power/regulator/fixed.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/drivers/power/regulator/fixed.c b/drivers/power/regulator/fixed.c index ad3b4b98d66..f7ddba8b45e 100644 --- a/drivers/power/regulator/fixed.c +++ b/drivers/power/regulator/fixed.c @@ -25,6 +25,7 @@ static int fixed_regulator_of_to_plat(struct udevice *dev) { struct dm_regulator_uclass_plat *uc_pdata; struct regulator_common_plat *plat; + bool gpios; plat = dev_get_plat(dev); uc_pdata = dev_get_uclass_plat(dev); @@ -33,7 +34,8 @@ static int fixed_regulator_of_to_plat(struct udevice *dev) uc_pdata->type = REGULATOR_TYPE_FIXED; - return regulator_common_of_to_plat(dev, plat, "gpio"); + gpios = dev_read_bool(dev, "gpios"); + return regulator_common_of_to_plat(dev, plat, gpios ? "gpios" : "gpio"); } static int fixed_regulator_get_value(struct udevice *dev) -- cgit v1.3.1 From 583a82d5e2702f2c8aadcd75d416d6e45dd5188a Mon Sep 17 00:00:00 2001 From: Jonas Karlman Date: Sat, 22 Jul 2023 13:30:22 +0000 Subject: rockchip: clk: clk_rk3568: Add CLK_PCIEPHY2_REF support Add dummy support for the CLK_PCIEPHY2_REF clock. Signed-off-by: Jonas Karlman Reviewed-by: Kever Yang --- drivers/clk/rockchip/clk_rk3568.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/clk/rockchip/clk_rk3568.c b/drivers/clk/rockchip/clk_rk3568.c index 6bdd96f35b5..0df82f59715 100644 --- a/drivers/clk/rockchip/clk_rk3568.c +++ b/drivers/clk/rockchip/clk_rk3568.c @@ -427,6 +427,7 @@ static ulong rk3568_pmuclk_set_rate(struct clk *clk, ulong rate) break; case CLK_PCIEPHY0_REF: case CLK_PCIEPHY1_REF: + case CLK_PCIEPHY2_REF: return 0; default: return -ENOENT; -- cgit v1.3.1 From a76aa6ffa6cd25eed282147f6e31b9c09272f930 Mon Sep 17 00:00:00 2001 From: Jonas Karlman Date: Sat, 22 Jul 2023 13:30:23 +0000 Subject: rockchip: rk3568-rock-3a: Enable PCIe and NVMe support Add missing pinctrl and defconfig options to enable PCIe and NVMe support on Radxa ROCK 3 Model A. Use of pcie20m1_pins and pcie30x2m1_pins ensure IO mux selection M1. The following pcie_reset_h and pcie3x2_reset_h ensure GPIO func is restored to the perstn pin, a workaround to avoid having to define a new rockchip,pins. Signed-off-by: Jonas Karlman Reviewed-by: Kever Yang --- arch/arm/dts/rk3568-rock-3a-u-boot.dtsi | 14 ++++++++++++++ configs/rock-3a-rk3568_defconfig | 9 +++++++++ 2 files changed, 23 insertions(+) diff --git a/arch/arm/dts/rk3568-rock-3a-u-boot.dtsi b/arch/arm/dts/rk3568-rock-3a-u-boot.dtsi index bbf54f888fa..9ee7b494ee2 100644 --- a/arch/arm/dts/rk3568-rock-3a-u-boot.dtsi +++ b/arch/arm/dts/rk3568-rock-3a-u-boot.dtsi @@ -36,8 +36,22 @@ bootph-all; }; +&pcie2x1 { + pinctrl-0 = <&pcie20m1_pins &pcie_reset_h>; +}; + +&pcie3x2 { + pinctrl-0 = <&pcie30x2m1_pins &pcie3x2_reset_h>; +}; + &pinctrl { bootph-all; + + pcie { + pcie3x2_reset_h: pcie3x2-reset-h { + rockchip,pins = <2 RK_PD6 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; }; &pcfg_pull_none { diff --git a/configs/rock-3a-rk3568_defconfig b/configs/rock-3a-rk3568_defconfig index 753d03914d9..8e3fe0a25e1 100644 --- a/configs/rock-3a-rk3568_defconfig +++ b/configs/rock-3a-rk3568_defconfig @@ -22,7 +22,9 @@ CONFIG_DEBUG_UART_CLOCK=24000000 CONFIG_SPL_SPI_FLASH_SUPPORT=y CONFIG_SPL_SPI=y CONFIG_SYS_LOAD_ADDR=0xc00800 +CONFIG_PCI=y CONFIG_DEBUG_UART=y +CONFIG_AHCI=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_SPL_FIT_SIGNATURE=y @@ -46,6 +48,7 @@ CONFIG_CMD_GPIO=y CONFIG_CMD_GPT=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y +CONFIG_CMD_PCI=y CONFIG_CMD_USB=y # CONFIG_CMD_SETEXPR is not set CONFIG_CMD_PMIC=y @@ -56,6 +59,8 @@ CONFIG_OF_LIVE=y CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" CONFIG_SPL_REGMAP=y CONFIG_SPL_SYSCON=y +CONFIG_SCSI_AHCI=y +CONFIG_AHCI_PCI=y CONFIG_SPL_CLK=y CONFIG_ROCKCHIP_GPIO=y CONFIG_SYS_I2C_ROCKCHIP=y @@ -70,6 +75,8 @@ CONFIG_SPI_FLASH_MACRONIX=y CONFIG_SPI_FLASH_XTX=y CONFIG_ETH_DESIGNWARE=y CONFIG_GMAC_ROCKCHIP=y +CONFIG_NVME_PCI=y +CONFIG_PCIE_DW_ROCKCHIP=y CONFIG_PHY_ROCKCHIP_INNO_USB2=y CONFIG_PHY_ROCKCHIP_NANENG_COMBOPHY=y CONFIG_SPL_PINCTRL=y @@ -78,6 +85,8 @@ CONFIG_PMIC_RK8XX=y CONFIG_REGULATOR_RK8XX=y CONFIG_PWM_ROCKCHIP=y CONFIG_SPL_RAM=y +CONFIG_SCSI=y +CONFIG_DM_SCSI=y CONFIG_BAUDRATE=1500000 CONFIG_DEBUG_UART_SHIFT=2 CONFIG_SYS_NS16550_MEM32=y -- cgit v1.3.1 From 062b712999869bdd7d6283ab8eed50e5999ac88a Mon Sep 17 00:00:00 2001 From: Jonas Karlman Date: Sat, 22 Jul 2023 13:30:24 +0000 Subject: rockchip: rk356x: Update PCIe config, IO and memory regions Update config, IO and memory regions used based on [1] with pcie3x2 config reg address and reg size corrected. Before this change: PCI Autoconfig: Bus Memory region: [0-3eefffff], PCI Autoconfig: Bus I/O region: [3ef00000-3effffff], After this change: PCI Autoconfig: Bus Memory region: [40000000-7fffffff], PCI Autoconfig: Bus I/O region: [f0100000-f01fffff], [1] https://lore.kernel.org/lkml/20221112114125.1637543-2-aholmes@omnom.net/ Signed-off-by: Jonas Karlman Reviewed-by: Kever Yang --- arch/arm/dts/rk3568.dtsi | 14 ++++++++------ arch/arm/dts/rk356x.dtsi | 7 ++++--- 2 files changed, 12 insertions(+), 9 deletions(-) diff --git a/arch/arm/dts/rk3568.dtsi b/arch/arm/dts/rk3568.dtsi index ba67b58f05b..f1be76a54ce 100644 --- a/arch/arm/dts/rk3568.dtsi +++ b/arch/arm/dts/rk3568.dtsi @@ -94,9 +94,10 @@ power-domains = <&power RK3568_PD_PIPE>; reg = <0x3 0xc0400000 0x0 0x00400000>, <0x0 0xfe270000 0x0 0x00010000>, - <0x3 0x7f000000 0x0 0x01000000>; - ranges = <0x01000000 0x0 0x3ef00000 0x3 0x7ef00000 0x0 0x00100000>, - <0x02000000 0x0 0x00000000 0x3 0x40000000 0x0 0x3ef00000>; + <0x0 0xf2000000 0x0 0x00100000>; + ranges = <0x01000000 0x0 0xf2100000 0x0 0xf2100000 0x0 0x00100000>, + <0x02000000 0x0 0xf2200000 0x0 0xf2200000 0x0 0x01e00000>, + <0x03000000 0x0 0x40000000 0x3 0x40000000 0x0 0x40000000>; reg-names = "dbi", "apb", "config"; resets = <&cru SRST_PCIE30X1_POWERUP>; reset-names = "pipe"; @@ -146,9 +147,10 @@ power-domains = <&power RK3568_PD_PIPE>; reg = <0x3 0xc0800000 0x0 0x00400000>, <0x0 0xfe280000 0x0 0x00010000>, - <0x3 0xbf000000 0x0 0x01000000>; - ranges = <0x01000000 0x0 0x3ef00000 0x3 0xbef00000 0x0 0x00100000>, - <0x02000000 0x0 0x00000000 0x3 0x80000000 0x0 0x3ef00000>; + <0x0 0xf0000000 0x0 0x00100000>; + ranges = <0x01000000 0x0 0xf0100000 0x0 0xf0100000 0x0 0x00100000>, + <0x02000000 0x0 0xf0200000 0x0 0xf0200000 0x0 0x01e00000>, + <0x03000000 0x0 0x40000000 0x3 0x80000000 0x0 0x40000000>; reg-names = "dbi", "apb", "config"; resets = <&cru SRST_PCIE30X2_POWERUP>; reset-names = "pipe"; diff --git a/arch/arm/dts/rk356x.dtsi b/arch/arm/dts/rk356x.dtsi index 6492ace0de6..e0591c194be 100644 --- a/arch/arm/dts/rk356x.dtsi +++ b/arch/arm/dts/rk356x.dtsi @@ -951,7 +951,7 @@ compatible = "rockchip,rk3568-pcie"; reg = <0x3 0xc0000000 0x0 0x00400000>, <0x0 0xfe260000 0x0 0x00010000>, - <0x3 0x3f000000 0x0 0x01000000>; + <0x0 0xf4000000 0x0 0x00100000>; reg-names = "dbi", "apb", "config"; interrupts = , , @@ -980,8 +980,9 @@ phys = <&combphy2 PHY_TYPE_PCIE>; phy-names = "pcie-phy"; power-domains = <&power RK3568_PD_PIPE>; - ranges = <0x01000000 0x0 0x3ef00000 0x3 0x3ef00000 0x0 0x00100000 - 0x02000000 0x0 0x00000000 0x3 0x00000000 0x0 0x3ef00000>; + ranges = <0x01000000 0x0 0xf4100000 0x0 0xf4100000 0x0 0x00100000>, + <0x02000000 0x0 0xf4200000 0x0 0xf4200000 0x0 0x01e00000>, + <0x03000000 0x0 0x40000000 0x3 0x00000000 0x0 0x40000000>; resets = <&cru SRST_PCIE20_POWERUP>; reset-names = "pipe"; #address-cells = <3>; -- cgit v1.3.1 From 96bdc655b09f248f1dbb0d10436437f1b45a47ec Mon Sep 17 00:00:00 2001 From: Paul Kocialkowski Date: Tue, 25 Jul 2023 14:58:35 +0200 Subject: rockchip: px30: Define variables for compressed image support The standard boot path expects the kernel_comp_addr_r and kernel_comp_size variables for booting compressed kernel images. Define them using the previous kernel_addr_c value (likely initially meant for this purpose) and usual size. This was tested on the PX30 EVB to successfully boot compressed Linux kernel images. Signed-off-by: Paul Kocialkowski Reviewed-by: Kever Yang --- include/configs/px30_common.h | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/include/configs/px30_common.h b/include/configs/px30_common.h index 6fbd2679f09..13ed9011764 100644 --- a/include/configs/px30_common.h +++ b/include/configs/px30_common.h @@ -21,8 +21,9 @@ "pxefile_addr_r=0x00600000\0" \ "fdt_addr_r=0x08300000\0" \ "kernel_addr_r=0x00280000\0" \ - "kernel_addr_c=0x03e80000\0" \ - "ramdisk_addr_r=0x0a200000\0" + "ramdisk_addr_r=0x0a200000\0" \ + "kernel_comp_addr_r=0x03e80000\0" \ + "kernel_comp_size=0x2000000\0" #define CFG_EXTRA_ENV_SETTINGS \ ENV_MEM_LAYOUT_SETTINGS \ -- cgit v1.3.1 From 7af6616c961d213b4bf2cc88003cbd868ea11ffa Mon Sep 17 00:00:00 2001 From: Jonas Karlman Date: Sat, 22 Jul 2023 14:02:12 +0000 Subject: ata: dwc_ahci: Fix support for other platforms The dwc_ahci driver use platform specific defines, place the platform specific code behind a ifdef CONFIG_ARCH_OMAP2PLUS to allow build and use of the driver on Rockchip platform. Fixes: 02a4b4297901 ("drivers: block: dwc_ahci: Implement a driver for Synopsys DWC sata device") Signed-off-by: Jonas Karlman --- drivers/ata/dwc_ahci.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/drivers/ata/dwc_ahci.c b/drivers/ata/dwc_ahci.c index 826fea71cc5..1dc91e7fce7 100644 --- a/drivers/ata/dwc_ahci.c +++ b/drivers/ata/dwc_ahci.c @@ -13,7 +13,9 @@ #include #include #include +#ifdef CONFIG_ARCH_OMAP2PLUS #include +#endif #include #include @@ -72,12 +74,14 @@ static int dwc_ahci_probe(struct udevice *dev) return ret; } +#ifdef CONFIG_ARCH_OMAP2PLUS if (priv->wrapper_base) { u32 val = TI_SATA_IDLE_NO | TI_SATA_STANDBY_NO; /* Enable SATA module, No Idle, No Standby */ writel(val, priv->wrapper_base + TI_SATA_SYSCONFIG); } +#endif return ahci_probe_scsi(dev, (ulong)priv->base); } -- cgit v1.3.1 From 8c1bb04b5699ce74ad727d4513e1a40a58c9c628 Mon Sep 17 00:00:00 2001 From: Jonas Karlman Date: Sat, 22 Jul 2023 14:02:13 +0000 Subject: cmd: ini: Fix build warning Building U-Boot with CMD_INI=y result in following build warning: cmd/ini.c: In function 'memgets': include/linux/kernel.h:184:24: warning: comparison of distinct pointer types lacks a cast 184 | (void) (&_min1 == &_min2); \ | ^~ cmd/ini.c:92:15: note: in expansion of macro 'min' 92 | len = min((end - *mem) + newline, num); | ^~~ Fix this by adding an int cast to the pointer arithmetic result. Signed-off-by: Jonas Karlman Reviewed-by: Kever Yang --- cmd/ini.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/cmd/ini.c b/cmd/ini.c index 81dfc4c4e83..35de2373e60 100644 --- a/cmd/ini.c +++ b/cmd/ini.c @@ -89,7 +89,7 @@ static char *memgets(char *str, int num, char **mem, size_t *memsize) end = *mem + *memsize; newline = 0; } - len = min((end - *mem) + newline, num); + len = min((int)(end - *mem) + newline, num); memcpy(str, *mem, len); if (len < num) str[len] = '\0'; -- cgit v1.3.1 From 94da929b933668c4b9ece7d56a2a2bb5543198c9 Mon Sep 17 00:00:00 2001 From: Jonas Karlman Date: Sat, 22 Jul 2023 14:02:15 +0000 Subject: board: rockchip: Add Hardkernel ODROID-M1 Hardkernel ODROID-M1 is a single board computer with a RK3568B2 SoC, a slightly modified version of the RK3568 SoC. Features tested on a ODROID-M1 8GB v1.0 2022-06-13: - SD-card boot - eMMC boot - SPI Flash boot - PCIe/NVMe/AHCI - SATA port - USB host Device tree is imported from linux v6.4. Signed-off-by: Jonas Karlman Reviewed-by: Stefan Agner Tested-by: Stefan Agner Reviewed-by: Kever Yang --- arch/arm/dts/Makefile | 1 + arch/arm/dts/rk3568-odroid-m1-u-boot.dtsi | 37 ++ arch/arm/dts/rk3568-odroid-m1.dts | 744 ++++++++++++++++++++++++++++++ arch/arm/mach-rockchip/rk3568/Kconfig | 6 + board/hardkernel/odroid_m1/Kconfig | 15 + board/hardkernel/odroid_m1/MAINTAINERS | 8 + board/hardkernel/odroid_m1/Makefile | 3 + board/hardkernel/odroid_m1/odroid_m1.c | 1 + configs/odroid-m1-rk3568_defconfig | 111 +++++ doc/board/rockchip/rockchip.rst | 1 + include/configs/odroid_m1.h | 11 + 11 files changed, 938 insertions(+) create mode 100644 arch/arm/dts/rk3568-odroid-m1-u-boot.dtsi create mode 100644 arch/arm/dts/rk3568-odroid-m1.dts create mode 100644 board/hardkernel/odroid_m1/Kconfig create mode 100644 board/hardkernel/odroid_m1/MAINTAINERS create mode 100644 board/hardkernel/odroid_m1/Makefile create mode 100644 board/hardkernel/odroid_m1/odroid_m1.c create mode 100644 configs/odroid-m1-rk3568_defconfig create mode 100644 include/configs/odroid_m1.h diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index f758ced7b71..bd5887bf750 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -174,6 +174,7 @@ dtb-$(CONFIG_ROCKCHIP_RK3568) += \ rk3568-evb.dtb \ rk3568-nanopi-r5c.dtb \ rk3568-nanopi-r5s.dtb \ + rk3568-odroid-m1.dtb \ rk3568-rock-3a.dtb dtb-$(CONFIG_ROCKCHIP_RK3588) += \ diff --git a/arch/arm/dts/rk3568-odroid-m1-u-boot.dtsi b/arch/arm/dts/rk3568-odroid-m1-u-boot.dtsi new file mode 100644 index 00000000000..0fc360b06df --- /dev/null +++ b/arch/arm/dts/rk3568-odroid-m1-u-boot.dtsi @@ -0,0 +1,37 @@ +// SPDX-License-Identifier: GPL-2.0+ + +#include "rk356x-u-boot.dtsi" + +/ { + chosen { + stdout-path = &uart2; + }; +}; + +&fspi_dual_io_pins { + bootph-all; +}; + +&sdhci { + cap-mmc-highspeed; + mmc-ddr-1_8v; + mmc-hs200-1_8v; + mmc-hs400-1_8v; + mmc-hs400-enhanced-strobe; + pinctrl-0 = <&emmc_bus8 &emmc_clk &emmc_cmd &emmc_datastrobe>; +}; + +&sfc { + bootph-pre-ram; + u-boot,spl-sfc-no-dma; + + flash@0 { + bootph-pre-ram; + }; +}; + +&uart2 { + bootph-all; + clock-frequency = <24000000>; + status = "okay"; +}; diff --git a/arch/arm/dts/rk3568-odroid-m1.dts b/arch/arm/dts/rk3568-odroid-m1.dts new file mode 100644 index 00000000000..59ecf868dbd --- /dev/null +++ b/arch/arm/dts/rk3568-odroid-m1.dts @@ -0,0 +1,744 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2022 Hardkernel Co., Ltd. + * + */ + +/dts-v1/; +#include +#include +#include +#include +#include "rk3568.dtsi" + +/ { + model = "Hardkernel ODROID-M1"; + compatible = "rockchip,rk3568-odroid-m1", "rockchip,rk3568"; + + aliases { + ethernet0 = &gmac0; + i2c0 = &i2c3; + i2c3 = &i2c0; + mmc0 = &sdhci; + mmc1 = &sdmmc0; + serial0 = &uart1; + serial1 = &uart0; + }; + + chosen { + stdout-path = "serial2:1500000n8"; + }; + + dc_12v: dc-12v-regulator { + compatible = "regulator-fixed"; + regulator-name = "dc_12v"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <12000000>; + regulator-max-microvolt = <12000000>; + }; + + hdmi-con { + compatible = "hdmi-connector"; + type = "a"; + + port { + hdmi_con_in: endpoint { + remote-endpoint = <&hdmi_out_con>; + }; + }; + }; + + ir-receiver { + compatible = "gpio-ir-receiver"; + gpios = <&gpio0 RK_PC2 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&ir_receiver_pin>; + }; + + leds { + compatible = "gpio-leds"; + + led_power: led-0 { + gpios = <&gpio0 RK_PC6 GPIO_ACTIVE_HIGH>; + function = LED_FUNCTION_POWER; + color = ; + default-state = "keep"; + linux,default-trigger = "default-on"; + pinctrl-names = "default"; + pinctrl-0 = <&led_power_pin>; + }; + led_work: led-1 { + gpios = <&gpio0 RK_PB7 GPIO_ACTIVE_HIGH>; + function = LED_FUNCTION_HEARTBEAT; + color = ; + linux,default-trigger = "heartbeat"; + pinctrl-names = "default"; + pinctrl-0 = <&led_work_pin>; + }; + }; + + rk809-sound { + compatible = "simple-audio-card"; + pinctrl-names = "default"; + pinctrl-0 = <&hp_det_pin>; + simple-audio-card,name = "Analog RK817"; + simple-audio-card,format = "i2s"; + simple-audio-card,hp-det-gpio = <&gpio0 RK_PB0 GPIO_ACTIVE_HIGH>; + simple-audio-card,mclk-fs = <256>; + simple-audio-card,widgets = + "Headphone", "Headphones", + "Speaker", "Speaker"; + simple-audio-card,routing = + "Headphones", "HPOL", + "Headphones", "HPOR", + "Speaker", "SPKO"; + + simple-audio-card,cpu { + sound-dai = <&i2s1_8ch>; + }; + + simple-audio-card,codec { + sound-dai = <&rk809>; + }; + }; + + vcc3v3_pcie: vcc3v3-pcie-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3_pcie"; + enable-active-high; + gpio = <&gpio4 RK_PA7 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&vcc3v3_pcie_en_pin>; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + startup-delay-us = <5000>; + vin-supply = <&vcc3v3_sys>; + }; + + vcc3v3_sys: vcc3v3-sys-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&dc_12v>; + }; + + vcc5v0_sys: vcc5v0-sys-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&dc_12v>; + }; + + vcc5v0_usb_host: vcc5v0-usb-host-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_usb_host"; + enable-active-high; + gpio = <&gpio0 RK_PA6 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&vcc5v0_usb_host_en_pin>; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&vcc5v0_sys>; + }; + + vcc5v0_usb_otg: vcc5v0-usb-otg-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_usb_otg"; + enable-active-high; + gpio = <&gpio0 RK_PA5 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&vcc5v0_usb_otg_en_pin>; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&vcc5v0_sys>; + }; +}; + +&combphy0 { + /* Used for USB3 */ + phy-supply = <&vcc5v0_usb_host>; + status = "okay"; +}; + +&combphy1 { + /* Used for USB3 */ + phy-supply = <&vcc5v0_usb_otg>; + status = "okay"; +}; + +&combphy2 { + /* used for SATA */ + status = "okay"; +}; + +&cpu0 { + cpu-supply = <&vdd_cpu>; +}; + +&cpu1 { + cpu-supply = <&vdd_cpu>; +}; + +&cpu2 { + cpu-supply = <&vdd_cpu>; +}; + +&cpu3 { + cpu-supply = <&vdd_cpu>; +}; + +&gmac0 { + assigned-clocks = <&cru SCLK_GMAC0_RX_TX>, <&cru SCLK_GMAC0>; + assigned-clock-parents = <&cru SCLK_GMAC0_RGMII_SPEED>; + assigned-clock-rates = <0>, <125000000>; + clock_in_out = "output"; + phy-handle = <&rgmii_phy0>; + phy-mode = "rgmii"; + phy-supply = <&vcc3v3_sys>; + pinctrl-names = "default"; + pinctrl-0 = <&gmac0_miim + &gmac0_tx_bus2 + &gmac0_rx_bus2 + &gmac0_rgmii_clk + &gmac0_rgmii_bus>; + status = "okay"; + + tx_delay = <0x4f>; + rx_delay = <0x2d>; +}; + +&gpu { + mali-supply = <&vdd_gpu>; + status = "okay"; +}; + +&hdmi { + avdd-0v9-supply = <&vdda0v9_image>; + avdd-1v8-supply = <&vcca1v8_image>; + status = "okay"; +}; + +&hdmi_in { + hdmi_in_vp0: endpoint { + remote-endpoint = <&vp0_out_hdmi>; + }; +}; + +&hdmi_out { + hdmi_out_con: endpoint { + remote-endpoint = <&hdmi_con_in>; + }; +}; + +&hdmi_sound { + status = "okay"; +}; + +&i2c0 { + status = "okay"; + + vdd_cpu: regulator@1c { + compatible = "tcs,tcs4525"; + reg = <0x1c>; + fcs,suspend-voltage-selector = <1>; + regulator-name = "vdd_cpu"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1150000>; + regulator-ramp-delay = <2300>; + vin-supply = <&vcc3v3_sys>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + rk809: pmic@20 { + compatible = "rockchip,rk809"; + reg = <0x20>; + interrupt-parent = <&gpio0>; + interrupts = ; + assigned-clocks = <&cru I2S1_MCLKOUT_TX>; + assigned-clock-parents = <&cru CLK_I2S1_8CH_TX>; + #clock-cells = <1>; + clock-names = "mclk"; + clocks = <&cru I2S1_MCLKOUT_TX>; + pinctrl-names = "default"; + pinctrl-0 = <&pmic_int_l>, <&i2s1m0_mclk>; + rockchip,system-power-controller; + #sound-dai-cells = <0>; + vcc1-supply = <&vcc3v3_sys>; + vcc2-supply = <&vcc3v3_sys>; + vcc3-supply = <&vcc3v3_sys>; + vcc4-supply = <&vcc3v3_sys>; + vcc5-supply = <&vcc3v3_sys>; + vcc6-supply = <&vcc3v3_sys>; + vcc7-supply = <&vcc3v3_sys>; + vcc8-supply = <&vcc3v3_sys>; + vcc9-supply = <&vcc3v3_sys>; + wakeup-source; + + regulators { + vdd_logic: DCDC_REG1 { + regulator-name = "vdd_logic"; + regulator-always-on; + regulator-boot-on; + regulator-init-microvolt = <900000>; + regulator-initial-mode = <0x2>; + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <1350000>; + regulator-ramp-delay = <6001>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_gpu: DCDC_REG2 { + regulator-name = "vdd_gpu"; + regulator-always-on; + regulator-init-microvolt = <900000>; + regulator-initial-mode = <0x2>; + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <1350000>; + regulator-ramp-delay = <6001>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_ddr: DCDC_REG3 { + regulator-name = "vcc_ddr"; + regulator-always-on; + regulator-boot-on; + regulator-initial-mode = <0x2>; + + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + vdd_npu: DCDC_REG4 { + regulator-name = "vdd_npu"; + regulator-init-microvolt = <900000>; + regulator-initial-mode = <0x2>; + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <1350000>; + regulator-ramp-delay = <6001>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_1v8: DCDC_REG5 { + regulator-name = "vcc_1v8"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdda0v9_image: LDO_REG1 { + regulator-name = "vdda0v9_image"; + regulator-always-on; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <900000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdda_0v9: LDO_REG2 { + regulator-name = "vdda_0v9"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <900000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdda0v9_pmu: LDO_REG3 { + regulator-name = "vdda0v9_pmu"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <900000>; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <900000>; + }; + }; + + vccio_acodec: LDO_REG4 { + regulator-name = "vccio_acodec"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vccio_sd: LDO_REG5 { + regulator-name = "vccio_sd"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc3v3_pmu: LDO_REG6 { + regulator-name = "vcc3v3_pmu"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3300000>; + }; + }; + + vcca_1v8: LDO_REG7 { + regulator-name = "vcca_1v8"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcca1v8_pmu: LDO_REG8 { + regulator-name = "vcca1v8_pmu"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vcca1v8_image: LDO_REG9 { + regulator-name = "vcca1v8_image"; + regulator-always-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_3v3: SWITCH_REG1 { + regulator-name = "vcc_3v3"; + regulator-always-on; + regulator-boot-on; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc3v3_sd: SWITCH_REG2 { + regulator-name = "vcc3v3_sd"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + }; + }; +}; + +&i2s0_8ch { + status = "okay"; +}; + +&i2s1_8ch { + rockchip,trcm-sync-tx-only; + status = "okay"; +}; + +&mdio0 { + rgmii_phy0: ethernet-phy@0 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0x0>; + reset-assert-us = <20000>; + reset-deassert-us = <100000>; + reset-gpios = <&gpio3 RK_PB7 GPIO_ACTIVE_LOW>; + }; +}; + +&pcie30phy { + status = "okay"; +}; + +&pcie3x2 { + pinctrl-names = "default"; + pinctrl-0 = <&pcie_reset_pin>; + reset-gpios = <&gpio2 RK_PD6 GPIO_ACTIVE_HIGH>; + vpcie3v3-supply = <&vcc3v3_pcie>; + status = "okay"; +}; + +&pinctrl { + fspi { + fspi_dual_io_pins: fspi-dual-io-pins { + rockchip,pins = + /* fspi_clk */ + <1 RK_PD0 1 &pcfg_pull_none>, + /* fspi_cs0n */ + <1 RK_PD3 1 &pcfg_pull_none>, + /* fspi_d0 */ + <1 RK_PD1 1 &pcfg_pull_none>, + /* fspi_d1 */ + <1 RK_PD2 1 &pcfg_pull_none>; + }; + }; + + ir-receiver { + ir_receiver_pin: ir-receiver-pin { + /* external pullup to VCC3V3_SYS */ + rockchip,pins = <0 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + leds { + led_power_pin: led-power-pin { + rockchip,pins = <0 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>; + }; + led_work_pin: led-work-pin { + rockchip,pins = <0 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + pcie { + pcie_reset_pin: pcie-reset-pin { + rockchip,pins = <2 RK_PD6 RK_FUNC_GPIO &pcfg_pull_none>; + }; + vcc3v3_pcie_en_pin: vcc3v3-pcie-en-pin { + rockchip,pins = <4 RK_PA7 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + pmic { + pmic_int_l: pmic-int-l { + rockchip,pins = <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + rk809 { + hp_det_pin: hp-det-pin { + rockchip,pins = <0 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + usb { + vcc5v0_usb_host_en_pin: vcc5v0-usb-host-en-pin { + rockchip,pins = <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>; + }; + vcc5v0_usb_otg_en_pin: vcc5v0-usb-dr-en-pin { + rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +}; + +&pmu_io_domains { + pmuio1-supply = <&vcc3v3_pmu>; + pmuio2-supply = <&vcc3v3_pmu>; + vccio1-supply = <&vccio_acodec>; + vccio2-supply = <&vcc_1v8>; + vccio3-supply = <&vccio_sd>; + vccio4-supply = <&vcc_1v8>; + vccio5-supply = <&vcc_3v3>; + vccio6-supply = <&vcc_3v3>; + vccio7-supply = <&vcc_3v3>; + status = "okay"; +}; + +&saradc { + vref-supply = <&vcca_1v8>; + status = "okay"; +}; + +&sata2 { + status = "okay"; +}; + +&sdhci { + bus-width = <8>; + max-frequency = <200000000>; + non-removable; + pinctrl-names = "default"; + pinctrl-0 = <&emmc_bus8 &emmc_clk &emmc_cmd &emmc_datastrobe &emmc_rstnout>; + vmmc-supply = <&vcc_3v3>; + vqmmc-supply = <&vcc_1v8>; + status = "okay"; +}; + +&sdmmc0 { + bus-width = <4>; + cap-sd-highspeed; + cd-gpios = <&gpio0 RK_PA4 GPIO_ACTIVE_LOW>; + disable-wp; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc0_bus4 &sdmmc0_clk &sdmmc0_cmd &sdmmc0_det>; + sd-uhs-sdr50; + vmmc-supply = <&vcc3v3_sd>; + vqmmc-supply = <&vccio_sd>; + status = "okay"; +}; + +&sfc { + /* Dual I/O mode as the D2 pin conflicts with the eMMC */ + pinctrl-0 = <&fspi_dual_io_pins>; + pinctrl-names = "default"; + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + flash@0 { + compatible = "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <100000000>; + spi-rx-bus-width = <2>; + spi-tx-bus-width = <1>; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "SPL"; + reg = <0x0 0xe0000>; + }; + partition@e0000 { + label = "U-Boot Env"; + reg = <0xe0000 0x20000>; + }; + partition@100000 { + label = "U-Boot"; + reg = <0x100000 0x200000>; + }; + partition@300000 { + label = "splash"; + reg = <0x300000 0x100000>; + }; + partition@400000 { + label = "Filesystem"; + reg = <0x400000 0xc00000>; + }; + }; + }; +}; + +&tsadc { + rockchip,hw-tshut-mode = <1>; + rockchip,hw-tshut-polarity = <0>; + status = "okay"; +}; + +&uart2 { + status = "okay"; +}; + +&usb_host0_ehci { + status = "okay"; +}; + +&usb_host0_ohci { + status = "okay"; +}; + +&usb_host0_xhci { + dr_mode = "host"; + status = "okay"; +}; + +&usb_host1_ehci { + status = "okay"; +}; + +&usb_host1_ohci { + status = "okay"; +}; + +&usb_host1_xhci { + status = "okay"; +}; + +&usb2phy0 { + status = "okay"; +}; + +&usb2phy0_host { + phy-supply = <&vcc5v0_usb_host>; + status = "okay"; +}; + +&usb2phy0_otg { + phy-supply = <&vcc5v0_usb_otg>; + status = "okay"; +}; + +&usb2phy1 { + status = "okay"; +}; + +&usb2phy1_host { + phy-supply = <&vcc5v0_usb_host>; + status = "okay"; +}; + +&usb2phy1_otg { + phy-supply = <&vcc5v0_usb_host>; + status = "okay"; +}; + +&vop { + assigned-clocks = <&cru DCLK_VOP0>, <&cru DCLK_VOP1>; + assigned-clock-parents = <&pmucru PLL_HPLL>, <&cru PLL_VPLL>; + status = "okay"; +}; + +&vop_mmu { + status = "okay"; +}; + +&vp0 { + vp0_out_hdmi: endpoint@ROCKCHIP_VOP2_EP_HDMI0 { + reg = ; + remote-endpoint = <&hdmi_in_vp0>; + }; +}; diff --git a/arch/arm/mach-rockchip/rk3568/Kconfig b/arch/arm/mach-rockchip/rk3568/Kconfig index 4424a3c47be..f46be3d081f 100644 --- a/arch/arm/mach-rockchip/rk3568/Kconfig +++ b/arch/arm/mach-rockchip/rk3568/Kconfig @@ -17,6 +17,11 @@ config TARGET_ANBERNIC_RGXX3_RK3566 and RG503. The correct device tree name will automatically be selected by the bootloader. +config TARGET_ODROID_M1_RK3568 + bool "ODROID-M1" + help + Hardkernel ODROID-M1 single board computer with a RK3568B2 SoC. + endchoice config ROCKCHIP_BOOT_MODE_REG @@ -33,5 +38,6 @@ config SYS_MALLOC_F_LEN source "board/rockchip/evb_rk3568/Kconfig" source "board/anbernic/rgxx3_rk3566/Kconfig" +source "board/hardkernel/odroid_m1/Kconfig" endif diff --git a/board/hardkernel/odroid_m1/Kconfig b/board/hardkernel/odroid_m1/Kconfig new file mode 100644 index 00000000000..999c4944a83 --- /dev/null +++ b/board/hardkernel/odroid_m1/Kconfig @@ -0,0 +1,15 @@ +if TARGET_ODROID_M1_RK3568 + +config SYS_BOARD + default "odroid_m1" + +config SYS_VENDOR + default "hardkernel" + +config SYS_CONFIG_NAME + default "odroid_m1" + +config BOARD_SPECIFIC_OPTIONS # dummy + def_bool y + +endif diff --git a/board/hardkernel/odroid_m1/MAINTAINERS b/board/hardkernel/odroid_m1/MAINTAINERS new file mode 100644 index 00000000000..165d2d96741 --- /dev/null +++ b/board/hardkernel/odroid_m1/MAINTAINERS @@ -0,0 +1,8 @@ +ODROID-M1 +M: Jonas Karlman +S: Maintained +F: board/hardkernel/odroid_m1/ +F: include/configs/odroid_m1.h +F: configs/odroid-m1-rk3568_defconfig +F: arch/arm/dts/rk3568-odroid-m1.dts +F: arch/arm/dts/rk3568-odroid-m1-u-boot.dtsi diff --git a/board/hardkernel/odroid_m1/Makefile b/board/hardkernel/odroid_m1/Makefile new file mode 100644 index 00000000000..ae8ea3d9781 --- /dev/null +++ b/board/hardkernel/odroid_m1/Makefile @@ -0,0 +1,3 @@ +# SPDX-License-Identifier: GPL-2.0+ + +obj-y += odroid_m1.o diff --git a/board/hardkernel/odroid_m1/odroid_m1.c b/board/hardkernel/odroid_m1/odroid_m1.c new file mode 100644 index 00000000000..4c027f2a7af --- /dev/null +++ b/board/hardkernel/odroid_m1/odroid_m1.c @@ -0,0 +1 @@ +// SPDX-License-Identifier: GPL-2.0+ diff --git a/configs/odroid-m1-rk3568_defconfig b/configs/odroid-m1-rk3568_defconfig new file mode 100644 index 00000000000..3dda5c1f917 --- /dev/null +++ b/configs/odroid-m1-rk3568_defconfig @@ -0,0 +1,111 @@ +CONFIG_ARM=y +CONFIG_SKIP_LOWLEVEL_INIT=y +CONFIG_COUNTER_FREQUENCY=24000000 +CONFIG_ARCH_ROCKCHIP=y +CONFIG_TEXT_BASE=0x00a00000 +CONFIG_SPL_LIBCOMMON_SUPPORT=y +CONFIG_SPL_LIBGENERIC_SUPPORT=y +CONFIG_NR_DRAM_BANKS=2 +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xc00000 +CONFIG_SF_DEFAULT_SPEED=24000000 +CONFIG_SF_DEFAULT_MODE=0x1000 +CONFIG_DEFAULT_DEVICE_TREE="rk3568-odroid-m1" +CONFIG_ROCKCHIP_RK3568=y +CONFIG_SPL_ROCKCHIP_COMMON_BOARD=y +CONFIG_ROCKCHIP_SPI_IMAGE=y +CONFIG_SPL_SERIAL=y +CONFIG_SPL_STACK_R_ADDR=0x600000 +CONFIG_TARGET_ODROID_M1_RK3568=y +CONFIG_SPL_STACK=0x400000 +CONFIG_DEBUG_UART_BASE=0xFE660000 +CONFIG_DEBUG_UART_CLOCK=24000000 +CONFIG_SPL_SPI_FLASH_SUPPORT=y +CONFIG_SPL_SPI=y +CONFIG_SYS_LOAD_ADDR=0xc00800 +CONFIG_PCI=y +CONFIG_DEBUG_UART=y +CONFIG_AHCI=y +CONFIG_FIT=y +CONFIG_FIT_VERBOSE=y +CONFIG_SPL_FIT_SIGNATURE=y +CONFIG_SPL_LOAD_FIT=y +CONFIG_LEGACY_IMAGE_FORMAT=y +CONFIG_DEFAULT_FDT_FILE="rockchip/rk3568-odroid-m1.dtb" +# CONFIG_DISPLAY_CPUINFO is not set +CONFIG_DISPLAY_BOARDINFO_LATE=y +CONFIG_SPL_MAX_SIZE=0x40000 +CONFIG_SPL_PAD_TO=0x7f8000 +CONFIG_SPL_HAS_BSS_LINKER_SECTION=y +CONFIG_SPL_BSS_START_ADDR=0x4000000 +CONFIG_SPL_BSS_MAX_SIZE=0x4000 +# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set +# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set +CONFIG_SPL_STACK_R=y +CONFIG_SPL_SPI_LOAD=y +CONFIG_SYS_SPI_U_BOOT_OFFS=0x100000 +CONFIG_SPL_ATF=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_GPT=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_MTD=y +CONFIG_CMD_PCI=y +CONFIG_CMD_USB=y +# CONFIG_CMD_SETEXPR is not set +CONFIG_CMD_INI=y +CONFIG_CMD_PMIC=y +CONFIG_CMD_REGULATOR=y +CONFIG_CMD_CRAMFS=y +CONFIG_MTDPARTS_DEFAULT="nor0:0x100000(reserved),0x200000(uboot),0x100000(splash),0xc00000(Firmware)" +# CONFIG_SPL_DOS_PARTITION is not set +CONFIG_SPL_OF_CONTROL=y +CONFIG_OF_LIVE=y +CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" +CONFIG_SPL_DM_SEQ_ALIAS=y +CONFIG_SPL_REGMAP=y +CONFIG_SPL_SYSCON=y +CONFIG_AHCI_PCI=y +CONFIG_DWC_AHCI=y +CONFIG_SPL_CLK=y +CONFIG_ROCKCHIP_GPIO=y +CONFIG_SYS_I2C_ROCKCHIP=y +CONFIG_MISC=y +CONFIG_SUPPORT_EMMC_RPMB=y +CONFIG_MMC_DW=y +CONFIG_MMC_DW_ROCKCHIP=y +CONFIG_MMC_SDHCI=y +CONFIG_MMC_SDHCI_SDMA=y +CONFIG_MMC_SDHCI_ROCKCHIP=y +CONFIG_MTD=y +CONFIG_SF_DEFAULT_BUS=4 +CONFIG_SPI_FLASH_SFDP_SUPPORT=y +CONFIG_SPI_FLASH_MACRONIX=y +CONFIG_SPI_FLASH_MTD=y +CONFIG_NVME_PCI=y +CONFIG_PCIE_DW_ROCKCHIP=y +CONFIG_PHY_ROCKCHIP_INNO_USB2=y +CONFIG_PHY_ROCKCHIP_NANENG_COMBOPHY=y +CONFIG_SPL_PINCTRL=y +CONFIG_DM_PMIC=y +CONFIG_PMIC_RK8XX=y +CONFIG_REGULATOR_RK8XX=y +CONFIG_PWM_ROCKCHIP=y +CONFIG_SPL_RAM=y +CONFIG_SCSI=y +CONFIG_DM_SCSI=y +CONFIG_BAUDRATE=1500000 +CONFIG_DEBUG_UART_SHIFT=2 +CONFIG_SYS_NS16550_MEM32=y +CONFIG_ROCKCHIP_SFC=y +CONFIG_SYSRESET=y +CONFIG_USB=y +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_EHCI_GENERIC=y +CONFIG_USB_OHCI_HCD=y +CONFIG_USB_OHCI_GENERIC=y +CONFIG_USB_DWC3=y +CONFIG_USB_DWC3_GENERIC=y +CONFIG_FS_CRAMFS=y +CONFIG_ERRNO_STR=y diff --git a/doc/board/rockchip/rockchip.rst b/doc/board/rockchip/rockchip.rst index 78afd49e387..dfbc27a86d6 100644 --- a/doc/board/rockchip/rockchip.rst +++ b/doc/board/rockchip/rockchip.rst @@ -95,6 +95,7 @@ List of mainline supported Rockchip boards: * rk3568 - Rockchip Evb-RK3568 (evb-rk3568) + - Hardkernel ODROID-M1 (odroid-m1-rk3568) * rk3588 - Rockchip EVB (evb-rk3588) diff --git a/include/configs/odroid_m1.h b/include/configs/odroid_m1.h new file mode 100644 index 00000000000..0d2e9fd94bf --- /dev/null +++ b/include/configs/odroid_m1.h @@ -0,0 +1,11 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ + +#ifndef __ODROID_M1_H +#define __ODROID_M1_H + +#define ROCKCHIP_DEVICE_SETTINGS \ + "cramfsaddr=0x0c000000\0" + +#include + +#endif -- cgit v1.3.1