From c4f40d092590a7b4649d354c810114d5041f8cca Mon Sep 17 00:00:00 2001 From: Balaji Selvanathan Date: Fri, 13 Feb 2026 14:31:18 +0530 Subject: clk: qcom: qcs615: Add GCC_USB3_PRIM_CLKREF_CLK support Add support for GCC_USB3_PRIM_CLKREF_CLK to the QCS615 clock driver. This clock is referenced in the device tree USB node but was not implemented in U-Boot, causing "Clock 152 not found" warnings during fastboot run. Signed-off-by: Balaji Selvanathan Reviewed-by: Sumit Garg Link: https://patch.msgid.link/20260213-talos_usb-v1-1-4c4355d61437@oss.qualcomm.com Signed-off-by: Casey Connolly --- drivers/clk/qcom/clock-qcs615.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/clk/qcom/clock-qcs615.c b/drivers/clk/qcom/clock-qcs615.c index 4700baba8c9..65b8db04020 100644 --- a/drivers/clk/qcom/clock-qcs615.c +++ b/drivers/clk/qcom/clock-qcs615.c @@ -66,6 +66,7 @@ static const struct gate_clk qcs615_clks[] = { GATE_CLK(GCC_USB3_PRIM_PHY_AUX_CLK, 0xf050, BIT(0)), GATE_CLK(GCC_USB3_PRIM_PHY_COM_AUX_CLK, 0xf054, BIT(0)), GATE_CLK(GCC_USB3_PRIM_PHY_PIPE_CLK, 0xf058, BIT(0)), + GATE_CLK(GCC_USB3_PRIM_CLKREF_CLK, 0x8c014, BIT(0)), GATE_CLK(GCC_QUPV3_WRAP0_S0_CLK, 0x5200c, GCC_QUPV3_WRAP0_S0_CLK_ENA_BIT), GATE_CLK(GCC_QUPV3_WRAP0_S1_CLK, 0x5200c, GCC_QUPV3_WRAP0_S1_CLK_ENA_BIT), GATE_CLK(GCC_QUPV3_WRAP0_S2_CLK, 0x5200c, GCC_QUPV3_WRAP0_S2_CLK_ENA_BIT), -- cgit v1.2.3 From c4169dfa1dcc2dc4876b10e1b1dc3de6b96ffd80 Mon Sep 17 00:00:00 2001 From: Balaji Selvanathan Date: Fri, 13 Feb 2026 14:31:19 +0530 Subject: clk: qcom: qcs615: Add GCC_AHB2PHY_WEST_CLK clock support Add GCC_AHB2PHY_WEST_CLK gate clock definition to the QCS615 clock driver. This clock is required for proper PHY operation and eliminates clock-related warnings during USB initialization. Signed-off-by: Balaji Selvanathan Reviewed-by: Sumit Garg Reviewed-by: Neil Armstrong Link: https://patch.msgid.link/20260213-talos_usb-v1-2-4c4355d61437@oss.qualcomm.com Signed-off-by: Casey Connolly --- drivers/clk/qcom/clock-qcs615.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/clk/qcom/clock-qcs615.c b/drivers/clk/qcom/clock-qcs615.c index 65b8db04020..2087fc38f63 100644 --- a/drivers/clk/qcom/clock-qcs615.c +++ b/drivers/clk/qcom/clock-qcs615.c @@ -67,6 +67,7 @@ static const struct gate_clk qcs615_clks[] = { GATE_CLK(GCC_USB3_PRIM_PHY_COM_AUX_CLK, 0xf054, BIT(0)), GATE_CLK(GCC_USB3_PRIM_PHY_PIPE_CLK, 0xf058, BIT(0)), GATE_CLK(GCC_USB3_PRIM_CLKREF_CLK, 0x8c014, BIT(0)), + GATE_CLK(GCC_AHB2PHY_WEST_CLK, 0x6a004, BIT(0)), GATE_CLK(GCC_QUPV3_WRAP0_S0_CLK, 0x5200c, GCC_QUPV3_WRAP0_S0_CLK_ENA_BIT), GATE_CLK(GCC_QUPV3_WRAP0_S1_CLK, 0x5200c, GCC_QUPV3_WRAP0_S1_CLK_ENA_BIT), GATE_CLK(GCC_QUPV3_WRAP0_S2_CLK, 0x5200c, GCC_QUPV3_WRAP0_S2_CLK_ENA_BIT), -- cgit v1.2.3 From 0f265c20a56f301dd44eb3e2067fe11fb9889030 Mon Sep 17 00:00:00 2001 From: Balaji Selvanathan Date: Fri, 13 Feb 2026 14:31:20 +0530 Subject: phy: qcom: qusb2: Add QCS615 QUSB2 PHY support Add support for QCS615 QUSB2 PHY by introducing platform-specific initialization table and register layout. The implementation reuses the IPQ6018 register layout and defines QCS615-specific tuning parameters for proper USB PHY operation. Taken from Linux commit 8adbf20e0502 ("phy: qcom-qusb2: Add support for QCS615") Signed-off-by: Balaji Selvanathan Reviewed-by: Sumit Garg Reviewed-by: Neil Armstrong Link: https://patch.msgid.link/20260213-talos_usb-v1-3-4c4355d61437@oss.qualcomm.com Signed-off-by: Casey Connolly --- drivers/phy/qcom/phy-qcom-qusb2.c | 38 ++++++++++++++++++++++++++++++++++++++ 1 file changed, 38 insertions(+) diff --git a/drivers/phy/qcom/phy-qcom-qusb2.c b/drivers/phy/qcom/phy-qcom-qusb2.c index 9e821365c15..6278171b100 100644 --- a/drivers/phy/qcom/phy-qcom-qusb2.c +++ b/drivers/phy/qcom/phy-qcom-qusb2.c @@ -176,6 +176,19 @@ static const unsigned int sm6115_regs_layout[] = { [QUSB2PHY_PORT_POWERDOWN] = 0xb4, [QUSB2PHY_INTR_CTRL] = 0xbc, }; +static const unsigned int ipq6018_regs_layout[] = { + [QUSB2PHY_PLL_STATUS] = 0x38, + [QUSB2PHY_PORT_TUNE1] = 0x80, + [QUSB2PHY_PORT_TUNE2] = 0x84, + [QUSB2PHY_PORT_TUNE3] = 0x88, + [QUSB2PHY_PORT_TUNE4] = 0x8C, + [QUSB2PHY_PORT_TUNE5] = 0x90, + [QUSB2PHY_PORT_TEST1] = 0x98, + [QUSB2PHY_PORT_TEST2] = 0x9C, + [QUSB2PHY_PORT_POWERDOWN] = 0xB4, + [QUSB2PHY_INTR_CTRL] = 0xBC, +}; + static const struct qusb2_phy_init_tbl msm8996_init_tbl[] = { QUSB2_PHY_INIT_CFG_L(QUSB2PHY_PORT_TUNE1, 0xf8), QUSB2_PHY_INIT_CFG_L(QUSB2PHY_PORT_TUNE2, 0xb3), @@ -189,6 +202,19 @@ static const struct qusb2_phy_init_tbl msm8996_init_tbl[] = { QUSB2_PHY_INIT_CFG(QUSB2PHY_PLL_PWR_CTRL, 0x00), }; +static const struct qusb2_phy_init_tbl qcs615_init_tbl[] = { + QUSB2_PHY_INIT_CFG_L(QUSB2PHY_PORT_TUNE1, 0xc8), + QUSB2_PHY_INIT_CFG_L(QUSB2PHY_PORT_TUNE2, 0xb3), + QUSB2_PHY_INIT_CFG_L(QUSB2PHY_PORT_TUNE3, 0x83), + QUSB2_PHY_INIT_CFG_L(QUSB2PHY_PORT_TUNE4, 0xc0), + QUSB2_PHY_INIT_CFG(QUSB2PHY_PLL_TUNE, 0x30), + QUSB2_PHY_INIT_CFG(QUSB2PHY_PLL_USER_CTL1, 0x79), + QUSB2_PHY_INIT_CFG(QUSB2PHY_PLL_USER_CTL2, 0x21), + QUSB2_PHY_INIT_CFG_L(QUSB2PHY_PORT_TEST2, 0x14), + QUSB2_PHY_INIT_CFG(QUSB2PHY_PLL_AUTOPGM_CTL1, 0x9f), + QUSB2_PHY_INIT_CFG(QUSB2PHY_PLL_PWR_CTRL, 0x00), +}; + static const struct qusb2_phy_init_tbl qusb2_v2_init_tbl[] = { QUSB2_PHY_INIT_CFG(QUSB2PHY_PLL_ANALOG_CONTROLS_TWO, 0x03), QUSB2_PHY_INIT_CFG(QUSB2PHY_PLL_CLOCK_INVERTERS, 0x7c), @@ -260,6 +286,16 @@ static const struct qusb2_phy_cfg sdm660_phy_cfg = { .autoresume_en = BIT(3), }; +static const struct qusb2_phy_cfg qcs615_phy_cfg = { + .tbl = qcs615_init_tbl, + .tbl_num = ARRAY_SIZE(qcs615_init_tbl), + .regs = ipq6018_regs_layout, + + .disable_ctrl = (CLAMP_N_EN | FREEZIO_N | POWER_DOWN), + .mask_core_ready = PLL_LOCKED, + .autoresume_en = BIT(0), +}; + static const struct qusb2_phy_cfg qusb2_v2_phy_cfg = { .tbl = qusb2_v2_init_tbl, .tbl_num = ARRAY_SIZE(qusb2_v2_init_tbl), @@ -467,6 +503,8 @@ static const struct udevice_id qusb2phy_ids[] = { { .compatible = "qcom,qusb2-phy" }, { .compatible = "qcom,qcm2290-qusb2-phy", .data = (ulong)&sm6115_phy_cfg }, + { .compatible = "qcom,qcs615-qusb2-phy", + .data = (ulong)&qcs615_phy_cfg }, { .compatible = "qcom,sdm660-qusb2-phy", .data = (ulong)&sdm660_phy_cfg }, { .compatible = "qcom,sm6115-qusb2-phy", -- cgit v1.2.3 From bb5012fb66cae854d05334c3f8787b093f0c7b92 Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Mon, 23 Mar 2026 13:53:02 -0600 Subject: power: regulator: qcom: Correct dependenecies for DM_REGULATOR_QCOM_USB_VBUS The DM_REGULATOR_QCOM_USB_VBUS functionality can only work with DM_PMIC enabled as well, so express this dependency in Kconfig. Signed-off-by: Tom Rini Link: https://patch.msgid.link/20260323195302.2363577-1-trini@konsulko.com Signed-off-by: Casey Connolly --- drivers/power/regulator/Kconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/power/regulator/Kconfig b/drivers/power/regulator/Kconfig index bd9ccd26981..d8b3e0f62e6 100644 --- a/drivers/power/regulator/Kconfig +++ b/drivers/power/regulator/Kconfig @@ -236,7 +236,7 @@ config DM_REGULATOR_QCOM_RPMH config DM_REGULATOR_QCOM_USB_VBUS bool "Enable driver model for Qualcomm USB vbus regulator" - depends on DM_REGULATOR + depends on DM_REGULATOR && DM_PMIC ---help--- Enable support for the Qualcomm USB Vbus regulator. The driver implements get/set api for the regulator to be used by u-boot. -- cgit v1.2.3 From 7f09aff39924c9bce4ac12379c5f624ce7004d43 Mon Sep 17 00:00:00 2001 From: Casey Connolly Date: Fri, 20 Mar 2026 16:45:40 +0100 Subject: serial: msm-geni: allow invalid clock Pre-relocation we may not have a clock but it's usually been enabled for us already, or worst case we will enable it after relocation. Erroring out in this case will almost always cause U-Boot to hang pre-relocation which is undesirable and may be hard to debug. Link: https://patch.msgid.link/20260320-casey-qcom-rpmh-serial-fixes-v1-1-b81d05832eec@linaro.org Signed-off-by: Casey Connolly --- drivers/serial/serial_msm_geni.c | 15 ++++++--------- 1 file changed, 6 insertions(+), 9 deletions(-) diff --git a/drivers/serial/serial_msm_geni.c b/drivers/serial/serial_msm_geni.c index bb5a2cb4d2c..3dca581f68f 100644 --- a/drivers/serial/serial_msm_geni.c +++ b/drivers/serial/serial_msm_geni.c @@ -212,7 +212,7 @@ static int msm_serial_setbrg(struct udevice *dev, int baud) ret = clk_set_rate(priv->se, clk_rate); if (ret < 0) { pr_err("%s: Couldn't set clock rate: %d\n", __func__, ret); - return ret; + return 0; } geni_serial_baud(priv->base, clk_div, baud); @@ -517,13 +517,14 @@ static int msm_serial_probe(struct udevice *dev) u32 proto; struct clk *clk; - clk = devm_clk_get(dev, NULL); + clk = devm_clk_get_optional(dev, NULL); if (IS_ERR(clk)) - return PTR_ERR(clk); - priv->se = clk; + dev_dbg(dev, "Couldn't find UART clock: %ld", PTR_ERR(clk)); + else + priv->se = clk; /* Try enable clock */ - ret = clk_enable(clk); + clk_enable(clk); /* Check if firmware loading is needed (BT UART) */ proto = readl(priv->base + GENI_FW_REVISION_RO); @@ -547,10 +548,6 @@ static int msm_serial_probe(struct udevice *dev) if (ofnode_device_is_compatible(dev_ofnode(dev), "qcom,geni-uart")) return -ENOENT; - /* Now handle clock enable return value */ - if (ret) - return ret; - ret = geni_set_oversampling(dev); if (ret < 0) return ret; -- cgit v1.2.3 From 4577a672eceaf7494cc42f9df05401e7beeab0b1 Mon Sep 17 00:00:00 2001 From: Casey Connolly Date: Fri, 20 Mar 2026 16:45:41 +0100 Subject: qcom: rpmh: don't error for SLEEP requests Just stub out non-active votes, if we return an error the caller may propagate it and not send its active vote. Since we don't suspend there's no risk of us entering a broken state due to missing votes. Link: https://patch.msgid.link/20260320-casey-qcom-rpmh-serial-fixes-v1-2-b81d05832eec@linaro.org Signed-off-by: Casey Connolly --- drivers/soc/qcom/rpmh-rsc.c | 8 ++++---- drivers/soc/qcom/rpmh.c | 4 ++-- 2 files changed, 6 insertions(+), 6 deletions(-) diff --git a/drivers/soc/qcom/rpmh-rsc.c b/drivers/soc/qcom/rpmh-rsc.c index dce61f26229..0b821cc6f9d 100644 --- a/drivers/soc/qcom/rpmh-rsc.c +++ b/drivers/soc/qcom/rpmh-rsc.c @@ -261,8 +261,8 @@ static struct tcs_group *get_tcs_for_msg(struct rsc_drv *drv, * just always used the first active TCS. */ if (msg->state != RPMH_ACTIVE_ONLY_STATE) { - log_err("WARN: only ACTIVE_ONLY state supported\n"); - return ERR_PTR(-EINVAL); + log_debug("WARN: only ACTIVE_ONLY state supported\n"); + return NULL; } return &drv->tcs[ACTIVE_TCS]; @@ -390,8 +390,8 @@ int rpmh_rsc_send_data(struct rsc_drv *drv, const struct tcs_request *msg) u32 val; tcs = get_tcs_for_msg(drv, msg); - if (IS_ERR(tcs)) - return PTR_ERR(tcs); + if (IS_ERR_OR_NULL(tcs)) + return 0; /* U-Boot is single-threaded, always use the first TCS as we'll never conflict */ tcs_id = tcs->offset; diff --git a/drivers/soc/qcom/rpmh.c b/drivers/soc/qcom/rpmh.c index 8c222324c66..b55e23c4417 100644 --- a/drivers/soc/qcom/rpmh.c +++ b/drivers/soc/qcom/rpmh.c @@ -60,8 +60,8 @@ static int __rpmh_write(const struct udevice *dev, enum rpmh_state state, struct rpmh_ctrlr *ctrlr = get_rpmh_ctrlr(dev); if (state != RPMH_ACTIVE_ONLY_STATE) { - log_err("only ACTIVE_ONLY state supported\n"); - return -EINVAL; + log_debug("WARN: Only ACTIVE_ONLY state supported\n"); + return 0; } return rpmh_rsc_send_data(ctrlr_to_drv(ctrlr), &rpm_msg->msg); -- cgit v1.2.3 From 1cf505e51b49438271f4b36a648b93b618f13a8e Mon Sep 17 00:00:00 2001 From: Casey Connolly Date: Wed, 21 Jan 2026 01:36:51 +0100 Subject: watchdog: qcom: stop watchdog by default Prevent the Qualcomm watchdog from autostarting and ensure it's stopped when the driver probed. In some cases the watchdog is left running by a previous bootloader stage. Disable autostart so it isn't left running when we boot into the OS, this behaviour can be changed by enabling autostart in the board defconfig. Reviewed-by: Stefan Roese Reviewed-by: Sumit Garg Reviewed-by: Tom Rini Link: https://patch.msgid.link/20260121003659.69305-1-casey.connolly@linaro.org Signed-off-by: Casey Connolly --- drivers/watchdog/Kconfig | 1 + drivers/watchdog/qcom-wdt.c | 2 +- 2 files changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/watchdog/Kconfig b/drivers/watchdog/Kconfig index 35ae7d106b1..416d29d256a 100644 --- a/drivers/watchdog/Kconfig +++ b/drivers/watchdog/Kconfig @@ -16,6 +16,7 @@ config WATCHDOG_AUTOSTART depends on WDT default n if ARCH_SUNXI default n if ARCH_STM32MP + default n if ARCH_SNAPDRAGON default y help Automatically start watchdog timer and start servicing it during diff --git a/drivers/watchdog/qcom-wdt.c b/drivers/watchdog/qcom-wdt.c index e4ebb1f31d4..a8d7e7a7950 100644 --- a/drivers/watchdog/qcom-wdt.c +++ b/drivers/watchdog/qcom-wdt.c @@ -129,7 +129,7 @@ static int qcom_wdt_probe(struct udevice *dev) wdt->clk_rate = (ulong)rate; - return 0; + return qcom_wdt_stop(dev); } static const struct wdt_ops qcom_wdt_ops = { -- cgit v1.2.3