From 4eee55bf2c282fd89f3cc27557ceb52533ee3431 Mon Sep 17 00:00:00 2001 From: Jim Liu Date: Tue, 13 Jun 2023 15:45:53 +0800 Subject: ARM: config: Enable config to decompress the FIT image Enable FIT and SHA config to decompress the kernel image Signed-off-by: Jim Liu --- configs/poleg_evb_defconfig | 3 +++ 1 file changed, 3 insertions(+) diff --git a/configs/poleg_evb_defconfig b/configs/poleg_evb_defconfig index b00fb48a5a7..cab589d7aa0 100644 --- a/configs/poleg_evb_defconfig +++ b/configs/poleg_evb_defconfig @@ -102,3 +102,6 @@ CONFIG_USB_GADGET_DOWNLOAD=y CONFIG_WDT_NPCM=y CONFIG_LIB_HW_RAND=y CONFIG_SHA_HW_ACCEL=y +CONFIG_FIT=y +CONFIG_SHA256=y +CONFIG_SHA512=y -- cgit v1.3.1 From 178284a9cf63095f55830f2c10983169796e7de6 Mon Sep 17 00:00:00 2001 From: Jim Liu Date: Tue, 13 Jun 2023 15:45:54 +0800 Subject: board: nuvoton: add env setting for boot to linux add console and mem env to boot to linux kernel Signed-off-by: Jim Liu --- board/nuvoton/poleg_evb/poleg_evb.c | 7 +++++++ include/configs/poleg.h | 2 ++ 2 files changed, 9 insertions(+) diff --git a/board/nuvoton/poleg_evb/poleg_evb.c b/board/nuvoton/poleg_evb/poleg_evb.c index aef142a881c..2052af6649a 100644 --- a/board/nuvoton/poleg_evb/poleg_evb.c +++ b/board/nuvoton/poleg_evb/poleg_evb.c @@ -6,6 +6,7 @@ #include #include +#include #include #include #include @@ -19,6 +20,7 @@ int board_init(void) int dram_init(void) { + char value[32]; struct npcm_gcr *gcr = (struct npcm_gcr *)NPCM_GCR_BA; int ramsize = (readl(&gcr->intcr3) >> 8) & 0x7; @@ -44,5 +46,10 @@ int dram_init(void) break; } + if (gd->ram_size > 0) { + sprintf(value, "%ldM", (gd->ram_size / 0x100000)); + env_set("mem", value); + } + return 0; } diff --git a/include/configs/poleg.h b/include/configs/poleg.h index c3f1d3393cb..1e96e838be4 100644 --- a/include/configs/poleg.h +++ b/include/configs/poleg.h @@ -27,6 +27,8 @@ "eth1addr=00:00:F7:A0:00:FD\0" \ "eth2addr=00:00:F7:A0:00:FE\0" \ "eth3addr=00:00:F7:A0:00:FF\0" \ + "console=ttyS0,115200n8\0" \ + "earlycon=uart8250,mmio32,0xf0000000\0" \ "common_bootargs=setenv bootargs earlycon=${earlycon} root=/dev/ram " \ "console=${console} mem=${mem} ramdisk_size=48000 basemac=${ethaddr}\0" \ "sd_prog=fatload mmc 0 10000000 image-bmc; cp.b 10000000 80000000 ${filesize}\0" \ -- cgit v1.3.1 From f4e086cdf1cc7e1e8c69e5d73eec2bda151ec9a1 Mon Sep 17 00:00:00 2001 From: Jim Liu Date: Tue, 13 Jun 2023 15:45:55 +0800 Subject: ARM: dts: npcm8xx: fix dts node error The SHA and OTP should under the ahb node Signed-off-by: Jim Liu --- arch/arm/dts/nuvoton-npcm8xx-u-boot.dtsi | 33 ++++++++++++++++---------------- 1 file changed, 17 insertions(+), 16 deletions(-) diff --git a/arch/arm/dts/nuvoton-npcm8xx-u-boot.dtsi b/arch/arm/dts/nuvoton-npcm8xx-u-boot.dtsi index be2ad0cf6cd..e49e564b790 100644 --- a/arch/arm/dts/nuvoton-npcm8xx-u-boot.dtsi +++ b/arch/arm/dts/nuvoton-npcm8xx-u-boot.dtsi @@ -289,6 +289,23 @@ status = "disable"; }; + aes: aes@f0858000 { + compatible = "nuvoton,npcm845-aes"; + reg = <0x0 0xf0858000 0x0 0x1000>, + <0x0 0xf0851000 0x0 0x1000>; + status = "disabled"; + clocks = <&clk NPCM8XX_CLK_AHB>; + clock-names = "clk_ahb"; + }; + + sha:sha@f085a000 { + compatible = "nuvoton,npcm845-sha"; + reg = <0x0 0xf085a000 0x0 0x1000>; + status = "disabled"; + clocks = <&clk NPCM8XX_CLK_AHB>; + clock-names = "clk_ahb"; + }; + apb { serial0: serial@0 { compatible = "nuvoton,npcm845-uart"; @@ -417,22 +434,6 @@ status = "disabled"; }; - aes: aes@f0858000 { - compatible = "nuvoton,npcm845-aes"; - reg = <0x0 0xf0858000 0x0 0x1000>, - <0x0 0xf0851000 0x0 0x1000>; - status = "disabled"; - clocks = <&clk NPCM8XX_CLK_AHB>; - clock-names = "clk_ahb"; - }; - - sha:sha@f085a000 { - compatible = "nuvoton,npcm845-sha"; - reg = <0x0 0xf085a000 0x0 0x1000>; - status = "disabled"; - clocks = <&clk NPCM8XX_CLK_AHB>; - clock-names = "clk_ahb"; - }; }; }; pinctrl: pinctrl@f0800000 { -- cgit v1.3.1 From 923edd666feb6321587f259953a6c5bea40d1dfe Mon Sep 17 00:00:00 2001 From: Jim Liu Date: Tue, 13 Jun 2023 15:45:56 +0800 Subject: misc: nuvoton: fix type error Signed-off-by: Jim Liu --- drivers/misc/npcm_otp.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/misc/npcm_otp.c b/drivers/misc/npcm_otp.c index 304910888bb..08029724c04 100644 --- a/drivers/misc/npcm_otp.c +++ b/drivers/misc/npcm_otp.c @@ -33,7 +33,7 @@ static int npcm_otp_check_inputs(u32 arr, u32 word) if (arr >= NPCM_NUM_OF_SA) { if (IS_ENABLED(CONFIG_ARCH_NPCM8XX)) printf("\nError: npcm8XX otp includs only one bank: 0\n"); - if (IS_ENABLED(CONFIG_ARCH_NPCM7XX)) + if (IS_ENABLED(CONFIG_ARCH_NPCM7xx)) printf("\nError: npcm7XX otp includs only two banks: 0 and 1\n"); return -1; } -- cgit v1.3.1 From 68f107a42b2b0f26c46afe92804485ea68951d6f Mon Sep 17 00:00:00 2001 From: Jim Liu Date: Tue, 4 Jul 2023 16:00:11 +0800 Subject: board: nuvoton: arbel: change uboot load address use new memory layout and change uboot load address. open tpm, tee and more config feature No need to reserve top memory because the reserved space is moved to the bottom area of memory. Signed-off-by: Jim Liu --- board/nuvoton/arbel_evb/Kconfig | 4 ++-- configs/arbel_evb_defconfig | 15 ++++++++++++++- include/configs/arbel.h | 5 +++-- 3 files changed, 19 insertions(+), 5 deletions(-) diff --git a/board/nuvoton/arbel_evb/Kconfig b/board/nuvoton/arbel_evb/Kconfig index efe85974a29..33c589f1fb3 100644 --- a/board/nuvoton/arbel_evb/Kconfig +++ b/board/nuvoton/arbel_evb/Kconfig @@ -11,8 +11,8 @@ config SYS_CONFIG_NAME config SYS_MEM_TOP_HIDE hex "Reserved TOP memory" - default 0xB000000 + default 0x0 help - Reserve memory for ECC/GFX/VCD/ECE. + Reserve memory for ECC/GFX/OPTEE/TIP/CP. endif diff --git a/configs/arbel_evb_defconfig b/configs/arbel_evb_defconfig index 29c4c187b58..c27a7cdd3a2 100644 --- a/configs/arbel_evb_defconfig +++ b/configs/arbel_evb_defconfig @@ -2,7 +2,8 @@ CONFIG_ARM=y CONFIG_ARCH_NPCM=y CONFIG_SYS_MALLOC_LEN=0x240000 CONFIG_SYS_MALLOC_F_LEN=0x1000 -CONFIG_NR_DRAM_BANKS=1 +CONFIG_TEXT_BASE=0x06208000 +CONFIG_NR_DRAM_BANKS=2 CONFIG_ENV_SIZE=0x40000 CONFIG_ENV_OFFSET=0x3C0000 CONFIG_ENV_SECT_SIZE=0x1000 @@ -22,6 +23,8 @@ CONFIG_BOOTCOMMAND="run common_bootargs; run romboot" CONFIG_HUSH_PARSER=y CONFIG_SYS_MAXARGS=32 CONFIG_SYS_BOOTM_LEN=0x1400000 +CONFIG_SYS_LOAD_ADDR=0x06208000 +CONFIG_SYS_INIT_SP_ADDR=0x06208000 CONFIG_CMD_FUSE=y CONFIG_CMD_GPIO=y CONFIG_CMD_I2C=y @@ -86,3 +89,13 @@ CONFIG_USB_STORAGE=y CONFIG_LIB_HW_RAND=y CONFIG_SHA_HW_ACCEL=y # CONFIG_EFI_LOADER is not set +CONFIG_TEE=y +CONFIG_OPTEE=y +CONFIG_TPM=y +CONFIG_TPM_V2=y +CONFIG_TPM2_FTPM_TEE=y +CONFIG_CMD_TPM=y +CONFIG_SUPPORT_EMMC_RPMB=y +CONFIG_CMD_GPT=y +CONFIG_CMD_FS_GENERIC=y +CONFIG_CMD_PART=y diff --git a/include/configs/arbel.h b/include/configs/arbel.h index 8e27fb52a1c..891257bc93a 100644 --- a/include/configs/arbel.h +++ b/include/configs/arbel.h @@ -7,12 +7,13 @@ #define __CONFIG_ARBEL_H #define CFG_SYS_SDRAM_BASE 0x0 -#define CFG_SYS_BOOTMAPSZ (20 << 20) +#define CFG_SYS_BOOTMAPSZ (30 << 20) +#define CFG_SYS_BOOTM_LEN (20 << 20) #define CFG_SYS_INIT_RAM_ADDR CFG_SYS_SDRAM_BASE #define CFG_SYS_INIT_RAM_SIZE 0x8000 /* Default environemnt variables */ -#define CFG_EXTRA_ENV_SETTINGS "uimage_flash_addr=80200000\0" \ +#define CFG_EXTRA_ENV_SETTINGS "uimage_flash_addr=80400000\0" \ "stdin=serial\0" \ "stdout=serial\0" \ "stderr=serial\0" \ -- cgit v1.3.1 From 0adbb8fbb1b64ae45b76cd6b1a639856d3a82de4 Mon Sep 17 00:00:00 2001 From: Jim Liu Date: Tue, 4 Jul 2023 16:00:12 +0800 Subject: pinctrl: nuvoton: fix reset reason error for poweron In non tip mode, BMC first power on with PORST+CORST. the gpio status will error. Signed-off-by: Jim Liu --- drivers/pinctrl/nuvoton/pinctrl-npcm8xx.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/pinctrl/nuvoton/pinctrl-npcm8xx.c b/drivers/pinctrl/nuvoton/pinctrl-npcm8xx.c index f18be08518e..7976e3b3ed5 100644 --- a/drivers/pinctrl/nuvoton/pinctrl-npcm8xx.c +++ b/drivers/pinctrl/nuvoton/pinctrl-npcm8xx.c @@ -808,6 +808,9 @@ static bool is_gpio_persist(struct udevice *dev, uint bank) status = npcm_get_reset_status(); dev_dbg(dev, "reset status: 0x%x\n", status); + if (status & PORST) + return false; + if (status & CORST) regmap_read(priv->rst_regmap, CORSTC, &val); else if (status & WD0RST) -- cgit v1.3.1 From fc3dab4fbe0075de0f7d6407c870069f1680a509 Mon Sep 17 00:00:00 2001 From: Jim Liu Date: Tue, 4 Jul 2023 16:00:13 +0800 Subject: misc: npcm_host_intf: change initialization sequence configuration should be done before release host wait Signed-off-by: Jim Liu --- drivers/misc/npcm_host_intf.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/misc/npcm_host_intf.c b/drivers/misc/npcm_host_intf.c index 0244e404570..79f57f57d89 100644 --- a/drivers/misc/npcm_host_intf.c +++ b/drivers/misc/npcm_host_intf.c @@ -50,9 +50,6 @@ static int npcm_host_intf_bind(struct udevice *dev) const char *type; int ret; - /* Release host wait */ - setbits_8(SMC_CTL_REG_ADDR, SMC_CTL_HOSTWAIT); - syscon = syscon_regmap_lookup_by_phandle(dev, "syscon"); if (IS_ERR(syscon)) { dev_err(dev, "%s: unable to get syscon, dev %s\n", __func__, dev->name); @@ -93,6 +90,9 @@ static int npcm_host_intf_bind(struct udevice *dev) regmap_update_bits(syscon, MFSEL1, MFSEL1_LPCSEL, MFSEL1_LPCSEL); } + /* Release host wait */ + setbits_8(SMC_CTL_REG_ADDR, SMC_CTL_HOSTWAIT); + return 0; } -- cgit v1.3.1 From 4b7f29ff146648f98b15148d28f7942651ac8450 Mon Sep 17 00:00:00 2001 From: Jim Liu Date: Tue, 4 Jul 2023 16:00:14 +0800 Subject: arch: arm: npcm8xx: add cpu version and 4G ram support Add npcm8xx A2 cpu version check and add 4G RAM support Signed-off-by: Jim Liu --- arch/arm/include/asm/arch-npcm8xx/gcr.h | 1 + arch/arm/mach-npcm/npcm8xx/cpu.c | 12 +++++- board/nuvoton/arbel_evb/arbel_evb.c | 70 +++++++++++++++++++++++++++++++-- 3 files changed, 79 insertions(+), 4 deletions(-) diff --git a/arch/arm/include/asm/arch-npcm8xx/gcr.h b/arch/arm/include/asm/arch-npcm8xx/gcr.h index ee6677a0e54..20230d64e6b 100644 --- a/arch/arm/include/asm/arch-npcm8xx/gcr.h +++ b/arch/arm/include/asm/arch-npcm8xx/gcr.h @@ -12,6 +12,7 @@ /* On-Chip ARBEL NPCM8XX VERSIONS */ #define ARBEL_Z1 0x00A35850 #define ARBEL_A1 0x04a35850 +#define ARBEL_A2 0x08a35850 #define ARBEL_NPCM845 0x00000000 #define ARBEL_NPCM830 0x00300395 #define ARBEL_NPCM810 0x00000220 diff --git a/arch/arm/mach-npcm/npcm8xx/cpu.c b/arch/arm/mach-npcm/npcm8xx/cpu.c index 2d839cfae95..af594526094 100644 --- a/arch/arm/mach-npcm/npcm8xx/cpu.c +++ b/arch/arm/mach-npcm/npcm8xx/cpu.c @@ -68,6 +68,9 @@ int print_cpuinfo(void) case ARBEL_A1: printf("A1 @ "); break; + case ARBEL_A2: + printf("A2 @ "); + break; default: printf("Unknown\n"); break; @@ -92,7 +95,7 @@ int arch_cpu_init(void) return 0; } -static struct mm_region npcm_mem_map[1 + CONFIG_NR_DRAM_BANKS + 1] = { +static struct mm_region npcm_mem_map[] = { { /* DRAM */ .phys = 0x0UL, @@ -109,6 +112,13 @@ static struct mm_region npcm_mem_map[1 + CONFIG_NR_DRAM_BANKS + 1] = { PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN }, + { + .phys = 0x100000000UL, + .virt = 0x100000000UL, + .size = 0x80000000UL, + .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | + PTE_BLOCK_INNER_SHARE + }, { /* List terminator */ 0, diff --git a/board/nuvoton/arbel_evb/arbel_evb.c b/board/nuvoton/arbel_evb/arbel_evb.c index cd12ce38345..e52e0a59abc 100644 --- a/board/nuvoton/arbel_evb/arbel_evb.c +++ b/board/nuvoton/arbel_evb/arbel_evb.c @@ -8,6 +8,17 @@ #include #include +#define SR_MII_CTRL_SWR_BIT15 15 + +#define DRAM_512MB_ECC_SIZE 0x1C000000ULL +#define DRAM_512MB_SIZE 0x20000000ULL +#define DRAM_1GB_ECC_SIZE 0x38000000ULL +#define DRAM_1GB_SIZE 0x40000000ULL +#define DRAM_2GB_ECC_SIZE 0x70000000ULL +#define DRAM_2GB_SIZE 0x80000000ULL +#define DRAM_4GB_ECC_SIZE 0xE00000000ULL +#define DRAM_4GB_SIZE 0x100000000ULL + DECLARE_GLOBAL_DATA_PTR; int board_init(void) @@ -18,12 +29,65 @@ int board_init(void) int dram_init(void) { struct npcm_gcr *gcr = (struct npcm_gcr *)NPCM_GCR_BA; + uint64_t delta = 0ULL; /* - * Get dram size from bootblock. - * The value is stored in scrpad_02 register. + * get dram active size value from bootblock. + * Value sent using scrpad_03 register. + * feature available in bootblock 0.0.6 and above. */ - gd->ram_size = readl(&gcr->scrpad_b); + + gd->ram_size = readl(&gcr->scrpad_c); + debug("%s: scrpad_c: %llx ", __func__, gd->ram_size); + + if (gd->ram_size == 0) { + gd->ram_size = readl(&gcr->scrpad_b); + debug("%s: scrpad_b: %llx ", __func__, gd->ram_size); + } else { + gd->ram_size *= 0x100000ULL; + } + + gd->bd->bi_dram[0].start = 0; + debug("ram_size: %llx ", gd->ram_size); + + switch (gd->ram_size) { + case DRAM_512MB_ECC_SIZE: + case DRAM_512MB_SIZE: + case DRAM_1GB_ECC_SIZE: + case DRAM_1GB_SIZE: + case DRAM_2GB_ECC_SIZE: + case DRAM_2GB_SIZE: + gd->bd->bi_dram[0].size = gd->ram_size; + gd->bd->bi_dram[1].start = 0; + gd->bd->bi_dram[1].size = 0; + break; + case DRAM_4GB_ECC_SIZE: + gd->bd->bi_dram[0].size = DRAM_2GB_ECC_SIZE; + gd->bd->bi_dram[1].start = DRAM_4GB_SIZE; + gd->bd->bi_dram[1].size = DRAM_2GB_SIZE; + delta = DRAM_4GB_SIZE - DRAM_2GB_ECC_SIZE; + break; + case DRAM_4GB_SIZE: + gd->bd->bi_dram[0].size = DRAM_2GB_SIZE; + gd->bd->bi_dram[1].start = DRAM_4GB_SIZE; + gd->bd->bi_dram[1].size = DRAM_2GB_SIZE; + delta = DRAM_4GB_SIZE - DRAM_2GB_SIZE; + break; + default: + gd->bd->bi_dram[0].size = DRAM_1GB_SIZE; + gd->bd->bi_dram[1].start = 0; + gd->bd->bi_dram[1].size = 0; + break; + } + + gd->ram_size -= delta; + + return 0; +} + +int dram_init_banksize(void) +{ + dram_init(); return 0; } -- cgit v1.3.1