From 0c5eab2bf8633d0e57e79a7b672bc5992ff36dfa Mon Sep 17 00:00:00 2001 From: Alif Zakuan Yuslaimi Date: Wed, 25 Feb 2026 17:44:53 +0800 Subject: clk: altera: agilex: Update sync to async mode config in clk pll Remove MEMBUS_CLKSLICE_REG source synchronous mode configuration to run as source asynchronous mode. Switching the HPS PLL to async mode improves resistance to clock marginality issues such as F2S clk to HPS PLL Signed-off-by: Alif Zakuan Yuslaimi Signed-off-by: Boon Khai Ng --- drivers/clk/altera/clk-agilex.c | 9 --------- 1 file changed, 9 deletions(-) diff --git a/drivers/clk/altera/clk-agilex.c b/drivers/clk/altera/clk-agilex.c index b793dbf6a42..426f400159c 100644 --- a/drivers/clk/altera/clk-agilex.c +++ b/drivers/clk/altera/clk-agilex.c @@ -74,15 +74,6 @@ static const struct { u32 val; u32 mask; } membus_pll[] = { - { - MEMBUS_CLKSLICE_REG, - /* - * BIT[7:7] - * Enable source synchronous mode - */ - BIT(7), - BIT(7) - }, { MEMBUS_SYNTHCALFOSC_INIT_CENTERFREQ_REG, /* -- cgit v1.3.1