From b17c594ac499c8cfb91093d62ff83d90a547ecf1 Mon Sep 17 00:00:00 2001 From: Wadim Egorov Date: Wed, 30 Jul 2025 17:42:11 +0200 Subject: arch: arm: dts: k3-am625-phyboard-lyra: Disable unused watchdogs in U-Boot The watchdog driver probes all available watchdog devices. This causes SMP boot errors when bringing up secondary CPUs. In our setup, only a single watchdog is needed to monitor the boot process until userspace or the OS takes over. Disable all unnecessary watchdog devices in U-Boot to avoid conflicts during CPU bring-up. Signed-off-by: Wadim Egorov --- arch/arm/dts/k3-am625-phyboard-lyra-rdk-u-boot.dtsi | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/arch/arm/dts/k3-am625-phyboard-lyra-rdk-u-boot.dtsi b/arch/arm/dts/k3-am625-phyboard-lyra-rdk-u-boot.dtsi index ee273563e83..3a1a8b06dc6 100644 --- a/arch/arm/dts/k3-am625-phyboard-lyra-rdk-u-boot.dtsi +++ b/arch/arm/dts/k3-am625-phyboard-lyra-rdk-u-boot.dtsi @@ -95,6 +95,22 @@ bootph-all; }; +&main_rti1 { + status = "disabled"; +}; + +&main_rti2 { + status = "disabled"; +}; + +&main_rti3 { + status = "disabled"; +}; + +&main_rti15 { + status = "disabled"; +}; + &main_uart0 { bootph-all; }; -- cgit v1.2.3 From dfd185939d9e4dc89e4365b142a14ffd7e775854 Mon Sep 17 00:00:00 2001 From: Wadim Egorov Date: Wed, 30 Jul 2025 17:42:12 +0200 Subject: arch: arm: dts: k3-am62a7-phyboard-lyra: Disable unused watchdogs in U-Boot The watchdog driver probes all available watchdog devices. This causes SMP boot errors when bringing up secondary CPUs. In our setup, only a single watchdog is needed to monitor the boot process until userspace or the OS takes over. Disable all unnecessary watchdog devices in U-Boot to avoid conflicts during CPU bring-up. Signed-off-by: Wadim Egorov --- arch/arm/dts/k3-am62a7-phyboard-lyra-rdk-u-boot.dtsi | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/arch/arm/dts/k3-am62a7-phyboard-lyra-rdk-u-boot.dtsi b/arch/arm/dts/k3-am62a7-phyboard-lyra-rdk-u-boot.dtsi index 73255a18e9b..8afd844460a 100644 --- a/arch/arm/dts/k3-am62a7-phyboard-lyra-rdk-u-boot.dtsi +++ b/arch/arm/dts/k3-am62a7-phyboard-lyra-rdk-u-boot.dtsi @@ -156,6 +156,22 @@ bootph-all; }; +&main_rti1 { + status = "disabled"; +}; + +&main_rti2 { + status = "disabled"; +}; + +&main_rti3 { + status = "disabled"; +}; + +&main_rti4 { + status = "disabled"; +}; + &main_uart0 { bootph-all; }; -- cgit v1.2.3 From dcc85e9aba41c82e9b54d2d925f83233842285a1 Mon Sep 17 00:00:00 2001 From: Wadim Egorov Date: Wed, 30 Jul 2025 17:42:13 +0200 Subject: arch: arm: dts: k3-am642-phyboard-electra: Disable unused watchdogs in U-Boot The watchdog driver probes all available watchdog devices. This causes SMP boot errors when bringing up secondary CPUs. In our setup, only a single watchdog is needed to monitor the boot process until userspace or the OS takes over. Disable all unnecessary watchdog devices in U-Boot to avoid conflicts during CPU bring-up. Signed-off-by: Wadim Egorov --- arch/arm/dts/k3-am642-phyboard-electra-rdk-u-boot.dtsi | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm/dts/k3-am642-phyboard-electra-rdk-u-boot.dtsi b/arch/arm/dts/k3-am642-phyboard-electra-rdk-u-boot.dtsi index c68a48678a2..56547cbd28a 100644 --- a/arch/arm/dts/k3-am642-phyboard-electra-rdk-u-boot.dtsi +++ b/arch/arm/dts/k3-am642-phyboard-electra-rdk-u-boot.dtsi @@ -156,6 +156,10 @@ bootph-all; }; +&main_rti1 { + status = "disabled"; +}; + &sdhci0 { bootph-all; }; -- cgit v1.2.3 From cc6291e3b4a4a8520a3c4bb44eae2ecd8f1e9c0e Mon Sep 17 00:00:00 2001 From: Wadim Egorov Date: Wed, 30 Jul 2025 17:42:16 +0200 Subject: board: phytec: phycore-am62ax: Add watchdog start to bootcmd Allows run-time control over watchdog auto-start and the timeout via setting the environment variable watchdog_timeout_ms. A value of zero means "do not start". Use CONFIG_WATCHDOG_TIMEOUT_MSECS as initial value. Users can enable the watchdog to monitor the boot process until userspace or OS takes over to serve the watchdog. Signed-off-by: Wadim Egorov --- board/phytec/phycore_am62ax/phycore_am62ax.env | 3 +++ configs/phycore_am62ax_a53_defconfig | 7 ++++++- 2 files changed, 9 insertions(+), 1 deletion(-) diff --git a/board/phytec/phycore_am62ax/phycore_am62ax.env b/board/phytec/phycore_am62ax/phycore_am62ax.env index 797904013dc..3f4b3cc4f0d 100644 --- a/board/phytec/phycore_am62ax/phycore_am62ax.env +++ b/board/phytec/phycore_am62ax/phycore_am62ax.env @@ -2,6 +2,7 @@ #include #include #include +#include fdtaddr=0x88000000 loadaddr=0x82000000 @@ -27,3 +28,5 @@ spi_ramdisk_addr=0x2200000 bootmeths=script efi extlinux pxe boot_targets=mmc1 mmc0 spi_flash dhcp + +watchdog=watchdog@e000000 diff --git a/configs/phycore_am62ax_a53_defconfig b/configs/phycore_am62ax_a53_defconfig index 05849d05be4..3572d46dc1f 100644 --- a/configs/phycore_am62ax_a53_defconfig +++ b/configs/phycore_am62ax_a53_defconfig @@ -40,7 +40,7 @@ CONFIG_SPL_LOAD_FIT=y CONFIG_SPL_LOAD_FIT_ADDRESS=0x81000000 CONFIG_BOOTSTD_FULL=y CONFIG_OF_BOARD_SETUP=y -CONFIG_BOOTCOMMAND="bootflow scan -lb; run ${boot}boot" +CONFIG_BOOTCOMMAND="run start_watchdog; bootflow scan -lb; run ${boot}boot" CONFIG_DEFAULT_FDT_FILE="oftree" # CONFIG_BOARD_INIT is not set CONFIG_BOARD_LATE_INIT=y @@ -75,6 +75,7 @@ CONFIG_CMD_MTD=y # CONFIG_CMD_POWEROFF is not set CONFIG_CMD_USB=y CONFIG_CMD_USB_MASS_STORAGE=y +CONFIG_CMD_WDT=y CONFIG_CMD_CACHE=y CONFIG_CMD_EFIDEBUG=y CONFIG_CMD_RTC=y @@ -185,5 +186,9 @@ CONFIG_USB_GADGET_MANUFACTURER="PHYTEC" CONFIG_USB_GADGET_VENDOR_NUM=0x0451 CONFIG_USB_GADGET_PRODUCT_NUM=0x6165 CONFIG_SPL_DFU=y +# CONFIG_WATCHDOG is not set +# CONFIG_WATCHDOG_AUTOSTART is not set +CONFIG_WDT=y +CONFIG_WDT_K3_RTI=y CONFIG_FS_FAT_MAX_CLUSTSIZE=16384 # CONFIG_HEXDUMP is not set -- cgit v1.2.3 From d27b7a1c777abe1bc103c983d0af082345457e7d Mon Sep 17 00:00:00 2001 From: Wadim Egorov Date: Wed, 30 Jul 2025 17:42:14 +0200 Subject: board: phytec: phycore-am62x: Add watchdog start to bootcmd Allows run-time control over watchdog auto-start and the timeout via setting the environment variable watchdog_timeout_ms. A value of zero means "do not start". Use CONFIG_WATCHDOG_TIMEOUT_MSECS as initial value. Users can enable the watchdog to monitor the boot process until userspace or OS takes over to serve the watchdog. Signed-off-by: Wadim Egorov --- board/phytec/phycore_am62x/phycore_am62x.env | 3 +++ configs/phycore_am62x_a53_defconfig | 7 ++++++- include/env/phytec/watchdog.env | 11 +++++++++++ 3 files changed, 20 insertions(+), 1 deletion(-) create mode 100644 include/env/phytec/watchdog.env diff --git a/board/phytec/phycore_am62x/phycore_am62x.env b/board/phytec/phycore_am62x/phycore_am62x.env index 797904013dc..3f4b3cc4f0d 100644 --- a/board/phytec/phycore_am62x/phycore_am62x.env +++ b/board/phytec/phycore_am62x/phycore_am62x.env @@ -2,6 +2,7 @@ #include #include #include +#include fdtaddr=0x88000000 loadaddr=0x82000000 @@ -27,3 +28,5 @@ spi_ramdisk_addr=0x2200000 bootmeths=script efi extlinux pxe boot_targets=mmc1 mmc0 spi_flash dhcp + +watchdog=watchdog@e000000 diff --git a/configs/phycore_am62x_a53_defconfig b/configs/phycore_am62x_a53_defconfig index 978604b0232..931ec39905b 100644 --- a/configs/phycore_am62x_a53_defconfig +++ b/configs/phycore_am62x_a53_defconfig @@ -44,7 +44,7 @@ CONFIG_SPL_LOAD_FIT=y CONFIG_SPL_LOAD_FIT_ADDRESS=0x81000000 CONFIG_BOOTSTD_FULL=y CONFIG_OF_BOARD_SETUP=y -CONFIG_BOOTCOMMAND="bootflow scan -lb; run ${boot}boot" +CONFIG_BOOTCOMMAND="run start_watchdog; bootflow scan -lb; run ${boot}boot" CONFIG_DEFAULT_FDT_FILE="oftree" # CONFIG_BOARD_INIT is not set CONFIG_BOARD_LATE_INIT=y @@ -79,6 +79,7 @@ CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y CONFIG_CMD_MTD=y CONFIG_CMD_USB=y +CONFIG_CMD_WDT=y CONFIG_CMD_CACHE=y CONFIG_CMD_EFIDEBUG=y CONFIG_CMD_RTC=y @@ -175,5 +176,9 @@ CONFIG_USB_GADGET_VENDOR_NUM=0x0451 CONFIG_USB_GADGET_PRODUCT_NUM=0x6165 CONFIG_USB_GADGET_DOWNLOAD=y CONFIG_SPL_DFU=y +# CONFIG_WATCHDOG is not set +# CONFIG_WATCHDOG_AUTOSTART is not set +CONFIG_WDT=y +CONFIG_WDT_K3_RTI=y CONFIG_FS_FAT_MAX_CLUSTSIZE=16384 # CONFIG_HEXDUMP is not set diff --git a/include/env/phytec/watchdog.env b/include/env/phytec/watchdog.env new file mode 100644 index 00000000000..f2e65baf1e9 --- /dev/null +++ b/include/env/phytec/watchdog.env @@ -0,0 +1,11 @@ +watchdog_timeout_ms=CONFIG_WATCHDOG_TIMEOUT_MSECS +start_watchdog= + if test ${watchdog_timeout_ms} -gt 0; then; + if test -z "${watchdog}"; then; + echo No watchdog device set, skipping watchdog start; + else; + wdt dev ${watchdog}; + wdt start ${watchdog_timeout_ms}; + echo Watchdog started, timeout ${watchdog_timeout_ms} ms; + fi; + fi; -- cgit v1.2.3 From e8eab15d14a9fd17ee5e99cc045ca15ff5aa8eb1 Mon Sep 17 00:00:00 2001 From: Wadim Egorov Date: Wed, 30 Jul 2025 17:42:17 +0200 Subject: include: env: phytec: k3: Add deprecation warning to legacy boot flow We switched towards standard boot with still keeping a fallback using legacy boot command alive. Add a deprecation warning to make it more clear that we will remove it in future versions. Signed-off-by: Wadim Egorov --- include/env/phytec/k3_mmc.env | 3 ++- include/env/phytec/k3_net.env | 3 ++- include/env/phytec/k3_spi.env | 4 +++- 3 files changed, 7 insertions(+), 3 deletions(-) diff --git a/include/env/phytec/k3_mmc.env b/include/env/phytec/k3_mmc.env index 3f67e312f65..95d0204b6da 100644 --- a/include/env/phytec/k3_mmc.env +++ b/include/env/phytec/k3_mmc.env @@ -14,7 +14,8 @@ mmcargs=setenv bootargs console=${console} earlycon=${earlycon} ${optargs} mmcloadimage=load mmc ${mmcdev}:${mmcpart} ${kernel_addr_r} Image mmcloadfdt=load mmc ${mmcdev}:${mmcpart} ${fdt_addr_r} ${fdtfile} -mmcboot=if test ${doraucboot} = 1; then run raucinit; fi; +mmcboot=echo DEPRECATION WARNING: mmcboot will be removed in future versions. Use standard boot instead.; + if test ${doraucboot} = 1; then run raucinit; fi; run mmcargs; mmc dev ${mmcdev}; mmc rescan; diff --git a/include/env/phytec/k3_net.env b/include/env/phytec/k3_net.env index 4d5c703cae9..669787928a2 100644 --- a/include/env/phytec/k3_net.env +++ b/include/env/phytec/k3_net.env @@ -12,7 +12,8 @@ netargs=setenv bootargs console=${console} root=/dev/nfs ip=dhcp rw nfsroot=${serverip}:${nfsroot},vers=4,tcp ${optargs} netloadimage=${get_cmd} ${kernel_addr_r} ${serverip}:/Image netloadfdt=${get_cmd} ${fdt_addr_r} ${serverip}:/${fdtfile} -netboot=run netargs; +netboot=echo DEPRECATION WARNING: netboot will be removed in future versions. Use standard boot instead.; + run netargs; setenv autoload no; dhcp; run netloadimage; diff --git a/include/env/phytec/k3_spi.env b/include/env/phytec/k3_spi.env index 8e9cfce3b4c..28fe69b4e57 100644 --- a/include/env/phytec/k3_spi.env +++ b/include/env/phytec/k3_spi.env @@ -10,7 +10,9 @@ spiargs=setenv bootargs console=${console} earlycon=${earlycon} ${optargs} spiloadimage=sf read ${kernel_addr_r} ${spi_image_addr} ${size_kern} spiloadfdt=sf read ${fdt_addr_r} ${spi_fdt_addr} ${size_fdt} spiloadramdisk=sf read ${ramdisk_addr_r} ${spi_ramdisk_addr} ${size_fs} -spiboot=run spiargs; + +spiboot=echo DEPRECATION WARNING: spiboot will be removed in future versions. Use standard boot instead.; + run spiargs; sf probe; run spiloadimage; run spiloadfdt; -- cgit v1.2.3 From 9de098a9f85eaec64389fd7ea1848110e6da36f6 Mon Sep 17 00:00:00 2001 From: Wadim Egorov Date: Wed, 30 Jul 2025 17:42:15 +0200 Subject: board: phytec: phycore-am64x: Add watchdog start to bootcmd Allows run-time control over watchdog auto-start and the timeout via setting the environment variable watchdog_timeout_ms. A value of zero means "do not start". Use CONFIG_WATCHDOG_TIMEOUT_MSECS as initial value. Users can enable the watchdog to monitor the boot process until userspace or OS takes over to serve the watchdog. Signed-off-by: Wadim Egorov --- board/phytec/phycore_am64x/phycore_am64x.env | 3 +++ configs/phycore_am64x_a53_defconfig | 7 ++++++- 2 files changed, 9 insertions(+), 1 deletion(-) diff --git a/board/phytec/phycore_am64x/phycore_am64x.env b/board/phytec/phycore_am64x/phycore_am64x.env index 36ab16e2f7a..3775a27c1a3 100644 --- a/board/phytec/phycore_am64x/phycore_am64x.env +++ b/board/phytec/phycore_am64x/phycore_am64x.env @@ -1,6 +1,7 @@ #include #include #include +#include fdtaddr=0x88000000 loadaddr=0x82000000 @@ -26,3 +27,5 @@ spi_ramdisk_addr=0x2200000 bootmeths=script efi extlinux pxe boot_targets=mmc1 mmc0 spi_flash dhcp + +watchdog=watchdog@e000000 diff --git a/configs/phycore_am64x_a53_defconfig b/configs/phycore_am64x_a53_defconfig index 62c9eec971d..cf1e9061f3c 100644 --- a/configs/phycore_am64x_a53_defconfig +++ b/configs/phycore_am64x_a53_defconfig @@ -39,7 +39,7 @@ CONFIG_SPL_LOAD_FIT=y CONFIG_SPL_LOAD_FIT_ADDRESS=0x81000000 CONFIG_BOOTSTD_FULL=y CONFIG_OF_BOARD_SETUP=y -CONFIG_BOOTCOMMAND="bootflow scan -lb; run ${boot}boot" +CONFIG_BOOTCOMMAND="run start_watchdog; bootflow scan -lb; run ${boot}boot" CONFIG_DEFAULT_FDT_FILE="oftree" # CONFIG_BOARD_INIT is not set CONFIG_BOARD_LATE_INIT=y @@ -77,6 +77,7 @@ CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y CONFIG_CMD_MTD=y CONFIG_CMD_USB=y +CONFIG_CMD_WDT=y CONFIG_CMD_CACHE=y CONFIG_CMD_EFIDEBUG=y CONFIG_CMD_RTC=y @@ -182,4 +183,8 @@ CONFIG_USB_GADGET_VENDOR_NUM=0x0451 CONFIG_USB_GADGET_PRODUCT_NUM=0x6165 CONFIG_USB_GADGET_DOWNLOAD=y CONFIG_USB_FUNCTION_MASS_STORAGE=y +# CONFIG_WATCHDOG is not set +# CONFIG_WATCHDOG_AUTOSTART is not set +CONFIG_WDT=y +CONFIG_WDT_K3_RTI=y CONFIG_FS_FAT_MAX_CLUSTSIZE=16384 -- cgit v1.2.3 From 5bad0bc4f7beeba8e972005fd0901cf368315815 Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Thu, 17 Jul 2025 19:15:21 -0600 Subject: pci: Add missing to pcie_iproc.c This driver references the SZ_ macros while relying on an indirection inclusion of . Add the missing include directly. Signed-off-by: Tom Rini --- drivers/pci/pcie_iproc.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/pci/pcie_iproc.c b/drivers/pci/pcie_iproc.c index 360ef1b011f..a6ed0189178 100644 --- a/drivers/pci/pcie_iproc.c +++ b/drivers/pci/pcie_iproc.c @@ -13,6 +13,7 @@ #include #include #include +#include #define EP_PERST_SOURCE_SELECT_SHIFT 2 #define EP_PERST_SOURCE_SELECT BIT(EP_PERST_SOURCE_SELECT_SHIFT) -- cgit v1.2.3 From cb8e5727089b6069f314a2f232e105f7c2127dbb Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Thu, 17 Jul 2025 19:15:26 -0600 Subject: pci: Tighten some PCI controller dependencies A large number of PCI controllers cannot build without access to some platform specific header files. Express those requirements in Kconfig as well. Signed-off-by: Tom Rini --- drivers/pci/Kconfig | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/drivers/pci/Kconfig b/drivers/pci/Kconfig index 8ffd88c722d..b8568267ff8 100644 --- a/drivers/pci/Kconfig +++ b/drivers/pci/Kconfig @@ -183,6 +183,7 @@ config SYS_FSL_PCI_VER_3_X config PCIE_FSL bool "FSL PowerPC PCIe support" select SYS_FSL_PCI_VER_3_X if ARCH_T2080 || ARCH_T4240 + depends on PPC help Say Y here if you want to enable PCIe controller support on FSL PowerPC MPC85xx, MPC86xx, B series, P series and T series SoCs. @@ -190,6 +191,7 @@ config PCIE_FSL config PCI_MPC85XX bool "MPC85XX PowerPC PCI support" + depends on MPC85xx help Say Y here if you want to enable PCI controller support on FSL PowerPC MPC85xx SoC. @@ -265,6 +267,7 @@ config PCIE_LAYERSCAPE config PCIE_LAYERSCAPE_RC bool "Layerscape PCIe Root Complex mode support" + depends on ARM select PCIE_LAYERSCAPE help Enable Layerscape PCIe Root Complex mode driver support. The Layerscape @@ -286,6 +289,7 @@ config PCI_IOMMU_EXTRA_MAPPINGS config PCIE_LAYERSCAPE_EP bool "Layerscape PCIe Endpoint mode support" + depends on ARM select PCIE_LAYERSCAPE select PCI_ENDPOINT help @@ -296,6 +300,7 @@ config PCIE_LAYERSCAPE_EP config PCIE_LAYERSCAPE_GEN4 bool "Layerscape Gen4 PCIe support" + depends on ARM help Support PCIe Gen4 on NXP Layerscape SoCs, which may have one or several PCIe controllers. The PCIe controller can work in RC or -- cgit v1.2.3 From f0572603514c7a5286121ebd1b13ba1b450512e9 Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Thu, 17 Jul 2025 19:15:30 -0600 Subject: nvme: Tighten requirements on NVME_APPLE driver This driver requires Apple rtkit headers in order to build. Express that requirement in Kconfig as well. Signed-off-by: Tom Rini --- drivers/nvme/Kconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/nvme/Kconfig b/drivers/nvme/Kconfig index d138867666b..b69fc4ed53d 100644 --- a/drivers/nvme/Kconfig +++ b/drivers/nvme/Kconfig @@ -11,6 +11,7 @@ config NVME config NVME_APPLE bool "Apple NVMe controller support" + depends on ARCH_APPLE select NVME help This option enables support for the NVMe storage -- cgit v1.2.3 From 26f857f1e37ccb7dfb93d55650ce35b179ed220f Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Thu, 17 Jul 2025 19:15:48 -0600 Subject: arm: bcm235xx: Remove this SoC As there are no platforms for this SoC, remove the code. Signed-off-by: Tom Rini --- arch/arm/cpu/armv7/Makefile | 1 - arch/arm/cpu/armv7/bcm235xx/Makefile | 10 - arch/arm/cpu/armv7/bcm235xx/clk-bcm235xx.c | 567 ---------------------------- arch/arm/cpu/armv7/bcm235xx/clk-bsc.c | 50 --- arch/arm/cpu/armv7/bcm235xx/clk-core.c | 512 ------------------------- arch/arm/cpu/armv7/bcm235xx/clk-core.h | 491 ------------------------ arch/arm/cpu/armv7/bcm235xx/clk-eth.c | 142 ------- arch/arm/cpu/armv7/bcm235xx/clk-sdio.c | 71 ---- arch/arm/cpu/armv7/bcm235xx/clk-usb-otg.c | 25 -- arch/arm/include/asm/arch-bcm235xx/boot0.h | 10 - arch/arm/include/asm/arch-bcm235xx/gpio.h | 14 - arch/arm/include/asm/arch-bcm235xx/sysmap.h | 30 -- 12 files changed, 1923 deletions(-) delete mode 100644 arch/arm/cpu/armv7/bcm235xx/Makefile delete mode 100644 arch/arm/cpu/armv7/bcm235xx/clk-bcm235xx.c delete mode 100644 arch/arm/cpu/armv7/bcm235xx/clk-bsc.c delete mode 100644 arch/arm/cpu/armv7/bcm235xx/clk-core.c delete mode 100644 arch/arm/cpu/armv7/bcm235xx/clk-core.h delete mode 100644 arch/arm/cpu/armv7/bcm235xx/clk-eth.c delete mode 100644 arch/arm/cpu/armv7/bcm235xx/clk-sdio.c delete mode 100644 arch/arm/cpu/armv7/bcm235xx/clk-usb-otg.c delete mode 100644 arch/arm/include/asm/arch-bcm235xx/boot0.h delete mode 100644 arch/arm/include/asm/arch-bcm235xx/gpio.h delete mode 100644 arch/arm/include/asm/arch-bcm235xx/sysmap.h diff --git a/arch/arm/cpu/armv7/Makefile b/arch/arm/cpu/armv7/Makefile index 318a71f24b1..e3415cfd1d1 100644 --- a/arch/arm/cpu/armv7/Makefile +++ b/arch/arm/cpu/armv7/Makefile @@ -32,7 +32,6 @@ ifneq (,$(filter s5pc1xx exynos,$(SOC))) obj-y += s5p-common/ endif -obj-$(if $(filter bcm235xx,$(SOC)),y) += bcm235xx/ obj-$(if $(filter bcm281xx,$(SOC)),y) += bcm281xx/ obj-$(if $(filter bcmcygnus,$(SOC)),y) += bcmcygnus/ obj-$(if $(filter bcmnsp,$(SOC)),y) += bcmnsp/ diff --git a/arch/arm/cpu/armv7/bcm235xx/Makefile b/arch/arm/cpu/armv7/bcm235xx/Makefile deleted file mode 100644 index 3d09126cabe..00000000000 --- a/arch/arm/cpu/armv7/bcm235xx/Makefile +++ /dev/null @@ -1,10 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0+ -# -# Copyright 2013 Broadcom Corporation. - -obj-y += clk-core.o -obj-y += clk-bcm235xx.o -obj-y += clk-sdio.o -obj-y += clk-bsc.o -obj-$(CONFIG_BCM_SF2_ETH) += clk-eth.o -obj-y += clk-usb-otg.o diff --git a/arch/arm/cpu/armv7/bcm235xx/clk-bcm235xx.c b/arch/arm/cpu/armv7/bcm235xx/clk-bcm235xx.c deleted file mode 100644 index 7f73f893458..00000000000 --- a/arch/arm/cpu/armv7/bcm235xx/clk-bcm235xx.c +++ /dev/null @@ -1,567 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright 2013 Broadcom Corporation. - */ - -/* - * - * bcm235xx-specific clock tables - * - */ - -#include -#include -#include -#include -#include "clk-core.h" - -#define CLOCK_1K 1000 -#define CLOCK_1M (CLOCK_1K * 1000) - -/* declare a reference clock */ -#define DECLARE_REF_CLK(clk_name, clk_parent, clk_rate, clk_div) \ -static struct refclk clk_name = { \ - .clk = { \ - .name = #clk_name, \ - .parent = clk_parent, \ - .rate = clk_rate, \ - .div = clk_div, \ - .ops = &ref_clk_ops, \ - }, \ -} - -/* - * Reference clocks - */ - -/* Declare a list of reference clocks */ -DECLARE_REF_CLK(ref_crystal, 0, 26 * CLOCK_1M, 1); -DECLARE_REF_CLK(var_96m, 0, 96 * CLOCK_1M, 1); -DECLARE_REF_CLK(ref_96m, 0, 96 * CLOCK_1M, 1); -DECLARE_REF_CLK(ref_312m, 0, 312 * CLOCK_1M, 0); -DECLARE_REF_CLK(ref_104m, &ref_312m.clk, 104 * CLOCK_1M, 3); -DECLARE_REF_CLK(ref_52m, &ref_104m.clk, 52 * CLOCK_1M, 2); -DECLARE_REF_CLK(ref_13m, &ref_52m.clk, 13 * CLOCK_1M, 4); -DECLARE_REF_CLK(var_312m, 0, 312 * CLOCK_1M, 0); -DECLARE_REF_CLK(var_104m, &var_312m.clk, 104 * CLOCK_1M, 3); -DECLARE_REF_CLK(var_52m, &var_104m.clk, 52 * CLOCK_1M, 2); -DECLARE_REF_CLK(var_13m, &var_52m.clk, 13 * CLOCK_1M, 4); - -struct refclk_lkup { - struct refclk *procclk; - const char *name; -}; - -/* Lookup table for string to clk tranlation */ -#define MKSTR(x) {&x, #x} -static struct refclk_lkup refclk_str_tbl[] = { - MKSTR(ref_crystal), MKSTR(var_96m), MKSTR(ref_96m), - MKSTR(ref_312m), MKSTR(ref_104m), MKSTR(ref_52m), - MKSTR(ref_13m), MKSTR(var_312m), MKSTR(var_104m), - MKSTR(var_52m), MKSTR(var_13m), -}; - -int refclk_entries = sizeof(refclk_str_tbl)/sizeof(refclk_str_tbl[0]); - -/* convert ref clock string to clock structure pointer */ -struct refclk *refclk_str_to_clk(const char *name) -{ - int i; - struct refclk_lkup *tblp = refclk_str_tbl; - for (i = 0; i < refclk_entries; i++, tblp++) { - if (!(strcmp(name, tblp->name))) - return tblp->procclk; - } - return NULL; -} - -/* frequency tables indexed by freq_id */ -unsigned long master_axi_freq_tbl[8] = { - 26 * CLOCK_1M, - 52 * CLOCK_1M, - 104 * CLOCK_1M, - 156 * CLOCK_1M, - 156 * CLOCK_1M, - 208 * CLOCK_1M, - 312 * CLOCK_1M, - 312 * CLOCK_1M -}; - -unsigned long master_ahb_freq_tbl[8] = { - 26 * CLOCK_1M, - 52 * CLOCK_1M, - 52 * CLOCK_1M, - 52 * CLOCK_1M, - 78 * CLOCK_1M, - 104 * CLOCK_1M, - 104 * CLOCK_1M, - 156 * CLOCK_1M -}; - -unsigned long slave_axi_freq_tbl[8] = { - 26 * CLOCK_1M, - 52 * CLOCK_1M, - 78 * CLOCK_1M, - 104 * CLOCK_1M, - 156 * CLOCK_1M, - 156 * CLOCK_1M -}; - -unsigned long slave_apb_freq_tbl[8] = { - 26 * CLOCK_1M, - 26 * CLOCK_1M, - 39 * CLOCK_1M, - 52 * CLOCK_1M, - 52 * CLOCK_1M, - 78 * CLOCK_1M -}; - -unsigned long esub_freq_tbl[8] = { - 78 * CLOCK_1M, - 156 * CLOCK_1M, - 156 * CLOCK_1M, - 156 * CLOCK_1M, - 208 * CLOCK_1M, - 208 * CLOCK_1M, - 208 * CLOCK_1M -}; - -static struct bus_clk_data bsc1_apb_data = { - .gate = HW_SW_GATE_AUTO(0x0458, 16, 0, 1), -}; - -static struct bus_clk_data bsc2_apb_data = { - .gate = HW_SW_GATE_AUTO(0x045c, 16, 0, 1), -}; - -static struct bus_clk_data bsc3_apb_data = { - .gate = HW_SW_GATE_AUTO(0x0484, 16, 0, 1), -}; - -/* * Master CCU clocks */ -static struct peri_clk_data sdio1_data = { - .gate = HW_SW_GATE(0x0358, 18, 2, 3), - .clocks = CLOCKS("ref_crystal", - "var_52m", - "ref_52m", - "var_96m", - "ref_96m"), - .sel = SELECTOR(0x0a28, 0, 3), - .div = DIVIDER(0x0a28, 4, 14), - .trig = TRIGGER(0x0afc, 9), -}; - -static struct peri_clk_data sdio2_data = { - .gate = HW_SW_GATE(0x035c, 18, 2, 3), - .clocks = CLOCKS("ref_crystal", - "var_52m", - "ref_52m", - "var_96m", - "ref_96m"), - .sel = SELECTOR(0x0a2c, 0, 3), - .div = DIVIDER(0x0a2c, 4, 14), - .trig = TRIGGER(0x0afc, 10), -}; - -static struct peri_clk_data sdio3_data = { - .gate = HW_SW_GATE(0x0364, 18, 2, 3), - .clocks = CLOCKS("ref_crystal", - "var_52m", - "ref_52m", - "var_96m", - "ref_96m"), - .sel = SELECTOR(0x0a34, 0, 3), - .div = DIVIDER(0x0a34, 4, 14), - .trig = TRIGGER(0x0afc, 12), -}; - -static struct peri_clk_data sdio4_data = { - .gate = HW_SW_GATE(0x0360, 18, 2, 3), - .clocks = CLOCKS("ref_crystal", - "var_52m", - "ref_52m", - "var_96m", - "ref_96m"), - .sel = SELECTOR(0x0a30, 0, 3), - .div = DIVIDER(0x0a30, 4, 14), - .trig = TRIGGER(0x0afc, 11), -}; - -static struct peri_clk_data sdio1_sleep_data = { - .clocks = CLOCKS("ref_32k"), - .gate = SW_ONLY_GATE(0x0358, 20, 4), -}; - -static struct peri_clk_data sdio2_sleep_data = { - .clocks = CLOCKS("ref_32k"), - .gate = SW_ONLY_GATE(0x035c, 20, 4), -}; - -static struct peri_clk_data sdio3_sleep_data = { - .clocks = CLOCKS("ref_32k"), - .gate = SW_ONLY_GATE(0x0364, 20, 4), -}; - -static struct peri_clk_data sdio4_sleep_data = { - .clocks = CLOCKS("ref_32k"), - .gate = SW_ONLY_GATE(0x0360, 20, 4), -}; - -static struct bus_clk_data usb_otg_ahb_data = { - .gate = HW_SW_GATE_AUTO(0x0348, 16, 0, 1), -}; - -static struct bus_clk_data sdio1_ahb_data = { - .gate = HW_SW_GATE_AUTO(0x0358, 16, 0, 1), -}; - -static struct bus_clk_data sdio2_ahb_data = { - .gate = HW_SW_GATE_AUTO(0x035c, 16, 0, 1), -}; - -static struct bus_clk_data sdio3_ahb_data = { - .gate = HW_SW_GATE_AUTO(0x0364, 16, 0, 1), -}; - -static struct bus_clk_data sdio4_ahb_data = { - .gate = HW_SW_GATE_AUTO(0x0360, 16, 0, 1), -}; - -/* * Slave CCU clocks */ -static struct peri_clk_data bsc1_data = { - .gate = HW_SW_GATE(0x0458, 18, 2, 3), - .clocks = CLOCKS("ref_crystal", - "var_104m", - "ref_104m", - "var_13m", - "ref_13m"), - .sel = SELECTOR(0x0a64, 0, 3), - .trig = TRIGGER(0x0afc, 23), -}; - -static struct peri_clk_data bsc2_data = { - .gate = HW_SW_GATE(0x045c, 18, 2, 3), - .clocks = CLOCKS("ref_crystal", - "var_104m", - "ref_104m", - "var_13m", - "ref_13m"), - .sel = SELECTOR(0x0a68, 0, 3), - .trig = TRIGGER(0x0afc, 24), -}; - -static struct peri_clk_data bsc3_data = { - .gate = HW_SW_GATE(0x0484, 18, 2, 3), - .clocks = CLOCKS("ref_crystal", - "var_104m", - "ref_104m", - "var_13m", - "ref_13m"), - .sel = SELECTOR(0x0a84, 0, 3), - .trig = TRIGGER(0x0b00, 2), -}; - -/* - * CCU clocks - */ - -static struct ccu_clock kpm_ccu_clk = { - .clk = { - .name = "kpm_ccu_clk", - .ops = &ccu_clk_ops, - .ccu_clk_mgr_base = KONA_MST_CLK_BASE_ADDR, - }, - .num_policy_masks = 1, - .policy_freq_offset = 0x00000008, - .freq_bit_shift = 8, - .policy_ctl_offset = 0x0000000c, - .policy0_mask_offset = 0x00000010, - .policy1_mask_offset = 0x00000014, - .policy2_mask_offset = 0x00000018, - .policy3_mask_offset = 0x0000001c, - .lvm_en_offset = 0x00000034, - .freq_id = 2, - .freq_tbl = master_axi_freq_tbl, -}; - -static struct ccu_clock kps_ccu_clk = { - .clk = { - .name = "kps_ccu_clk", - .ops = &ccu_clk_ops, - .ccu_clk_mgr_base = KONA_SLV_CLK_BASE_ADDR, - }, - .num_policy_masks = 1, - .policy_freq_offset = 0x00000008, - .freq_bit_shift = 8, - .policy_ctl_offset = 0x0000000c, - .policy0_mask_offset = 0x00000010, - .policy1_mask_offset = 0x00000014, - .policy2_mask_offset = 0x00000018, - .policy3_mask_offset = 0x0000001c, - .lvm_en_offset = 0x00000034, - .freq_id = 2, - .freq_tbl = slave_axi_freq_tbl, -}; - -#ifdef CONFIG_BCM_SF2_ETH -static struct ccu_clock esub_ccu_clk = { - .clk = { - .name = "esub_ccu_clk", - .ops = &ccu_clk_ops, - .ccu_clk_mgr_base = ESUB_CLK_BASE_ADDR, - }, - .num_policy_masks = 1, - .policy_freq_offset = 0x00000008, - .freq_bit_shift = 8, - .policy_ctl_offset = 0x0000000c, - .policy0_mask_offset = 0x00000010, - .policy1_mask_offset = 0x00000014, - .policy2_mask_offset = 0x00000018, - .policy3_mask_offset = 0x0000001c, - .lvm_en_offset = 0x00000034, - .freq_id = 2, - .freq_tbl = esub_freq_tbl, -}; -#endif - -/* - * Bus clocks - */ - -/* KPM bus clocks */ -static struct bus_clock usb_otg_ahb_clk = { - .clk = { - .name = "usb_otg_ahb_clk", - .parent = &kpm_ccu_clk.clk, - .ops = &bus_clk_ops, - .ccu_clk_mgr_base = KONA_MST_CLK_BASE_ADDR, - }, - .freq_tbl = master_ahb_freq_tbl, - .data = &usb_otg_ahb_data, -}; - -static struct bus_clock sdio1_ahb_clk = { - .clk = { - .name = "sdio1_ahb_clk", - .parent = &kpm_ccu_clk.clk, - .ops = &bus_clk_ops, - .ccu_clk_mgr_base = KONA_MST_CLK_BASE_ADDR, - }, - .freq_tbl = master_ahb_freq_tbl, - .data = &sdio1_ahb_data, -}; - -static struct bus_clock sdio2_ahb_clk = { - .clk = { - .name = "sdio2_ahb_clk", - .parent = &kpm_ccu_clk.clk, - .ops = &bus_clk_ops, - .ccu_clk_mgr_base = KONA_MST_CLK_BASE_ADDR, - }, - .freq_tbl = master_ahb_freq_tbl, - .data = &sdio2_ahb_data, -}; - -static struct bus_clock sdio3_ahb_clk = { - .clk = { - .name = "sdio3_ahb_clk", - .parent = &kpm_ccu_clk.clk, - .ops = &bus_clk_ops, - .ccu_clk_mgr_base = KONA_MST_CLK_BASE_ADDR, - }, - .freq_tbl = master_ahb_freq_tbl, - .data = &sdio3_ahb_data, -}; - -static struct bus_clock sdio4_ahb_clk = { - .clk = { - .name = "sdio4_ahb_clk", - .parent = &kpm_ccu_clk.clk, - .ops = &bus_clk_ops, - .ccu_clk_mgr_base = KONA_MST_CLK_BASE_ADDR, - }, - .freq_tbl = master_ahb_freq_tbl, - .data = &sdio4_ahb_data, -}; - -static struct bus_clock bsc1_apb_clk = { - .clk = { - .name = "bsc1_apb_clk", - .parent = &kps_ccu_clk.clk, - .ops = &bus_clk_ops, - .ccu_clk_mgr_base = KONA_SLV_CLK_BASE_ADDR, - }, - .freq_tbl = slave_apb_freq_tbl, - .data = &bsc1_apb_data, -}; - -static struct bus_clock bsc2_apb_clk = { - .clk = { - .name = "bsc2_apb_clk", - .parent = &kps_ccu_clk.clk, - .ops = &bus_clk_ops, - .ccu_clk_mgr_base = KONA_SLV_CLK_BASE_ADDR, - }, - .freq_tbl = slave_apb_freq_tbl, - .data = &bsc2_apb_data, -}; - -static struct bus_clock bsc3_apb_clk = { - .clk = { - .name = "bsc3_apb_clk", - .parent = &kps_ccu_clk.clk, - .ops = &bus_clk_ops, - .ccu_clk_mgr_base = KONA_SLV_CLK_BASE_ADDR, - }, - .freq_tbl = slave_apb_freq_tbl, - .data = &bsc3_apb_data, -}; - -/* KPM peripheral */ -static struct peri_clock sdio1_clk = { - .clk = { - .name = "sdio1_clk", - .parent = &ref_52m.clk, - .ops = &peri_clk_ops, - .ccu_clk_mgr_base = KONA_MST_CLK_BASE_ADDR, - }, - .data = &sdio1_data, -}; - -static struct peri_clock sdio2_clk = { - .clk = { - .name = "sdio2_clk", - .parent = &ref_52m.clk, - .ops = &peri_clk_ops, - .ccu_clk_mgr_base = KONA_MST_CLK_BASE_ADDR, - }, - .data = &sdio2_data, -}; - -static struct peri_clock sdio3_clk = { - .clk = { - .name = "sdio3_clk", - .parent = &ref_52m.clk, - .ops = &peri_clk_ops, - .ccu_clk_mgr_base = KONA_MST_CLK_BASE_ADDR, - }, - .data = &sdio3_data, -}; - -static struct peri_clock sdio4_clk = { - .clk = { - .name = "sdio4_clk", - .parent = &ref_52m.clk, - .ops = &peri_clk_ops, - .ccu_clk_mgr_base = KONA_MST_CLK_BASE_ADDR, - }, - .data = &sdio4_data, -}; - -static struct peri_clock sdio1_sleep_clk = { - .clk = { - .name = "sdio1_sleep_clk", - .parent = &kpm_ccu_clk.clk, - .ops = &bus_clk_ops, - .ccu_clk_mgr_base = KONA_MST_CLK_BASE_ADDR, - }, - .data = &sdio1_sleep_data, -}; - -static struct peri_clock sdio2_sleep_clk = { - .clk = { - .name = "sdio2_sleep_clk", - .parent = &kpm_ccu_clk.clk, - .ops = &bus_clk_ops, - .ccu_clk_mgr_base = KONA_MST_CLK_BASE_ADDR, - }, - .data = &sdio2_sleep_data, -}; - -static struct peri_clock sdio3_sleep_clk = { - .clk = { - .name = "sdio3_sleep_clk", - .parent = &kpm_ccu_clk.clk, - .ops = &bus_clk_ops, - .ccu_clk_mgr_base = KONA_MST_CLK_BASE_ADDR, - }, - .data = &sdio3_sleep_data, -}; - -static struct peri_clock sdio4_sleep_clk = { - .clk = { - .name = "sdio4_sleep_clk", - .parent = &kpm_ccu_clk.clk, - .ops = &bus_clk_ops, - .ccu_clk_mgr_base = KONA_MST_CLK_BASE_ADDR, - }, - .data = &sdio4_sleep_data, -}; - -/* KPS peripheral clock */ -static struct peri_clock bsc1_clk = { - .clk = { - .name = "bsc1_clk", - .parent = &ref_13m.clk, - .rate = 13 * CLOCK_1M, - .div = 1, - .ops = &peri_clk_ops, - .ccu_clk_mgr_base = KONA_SLV_CLK_BASE_ADDR, - }, - .data = &bsc1_data, -}; - -static struct peri_clock bsc2_clk = { - .clk = { - .name = "bsc2_clk", - .parent = &ref_13m.clk, - .rate = 13 * CLOCK_1M, - .div = 1, - .ops = &peri_clk_ops, - .ccu_clk_mgr_base = KONA_SLV_CLK_BASE_ADDR, - }, - .data = &bsc2_data, -}; - -static struct peri_clock bsc3_clk = { - .clk = { - .name = "bsc3_clk", - .parent = &ref_13m.clk, - .rate = 13 * CLOCK_1M, - .div = 1, - .ops = &peri_clk_ops, - .ccu_clk_mgr_base = KONA_SLV_CLK_BASE_ADDR, - }, - .data = &bsc3_data, -}; - -/* public table for registering clocks */ -struct clk_lookup arch_clk_tbl[] = { - /* Peripheral clocks */ - CLK_LK(sdio1), - CLK_LK(sdio2), - CLK_LK(sdio3), - CLK_LK(sdio4), - CLK_LK(sdio1_sleep), - CLK_LK(sdio2_sleep), - CLK_LK(sdio3_sleep), - CLK_LK(sdio4_sleep), - CLK_LK(bsc1), - CLK_LK(bsc2), - CLK_LK(bsc3), - /* Bus clocks */ - CLK_LK(usb_otg_ahb), - CLK_LK(sdio1_ahb), - CLK_LK(sdio2_ahb), - CLK_LK(sdio3_ahb), - CLK_LK(sdio4_ahb), - CLK_LK(bsc1_apb), - CLK_LK(bsc2_apb), - CLK_LK(bsc3_apb), -#ifdef CONFIG_BCM_SF2_ETH - CLK_LK(esub_ccu), -#endif -}; - -/* public array size */ -unsigned int arch_clk_tbl_array_size = ARRAY_SIZE(arch_clk_tbl); diff --git a/arch/arm/cpu/armv7/bcm235xx/clk-bsc.c b/arch/arm/cpu/armv7/bcm235xx/clk-bsc.c deleted file mode 100644 index 55dcc2fd78c..00000000000 --- a/arch/arm/cpu/armv7/bcm235xx/clk-bsc.c +++ /dev/null @@ -1,50 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright 2013 Broadcom Corporation. - */ - -#include -#include -#include -#include -#include "clk-core.h" - -/* Enable appropriate clocks for a BSC/I2C port */ -int clk_bsc_enable(void *base) -{ - int ret; - char *bscstr, *apbstr; - - switch ((u32) base) { - case PMU_BSC_BASE_ADDR: - /* PMU clock is always enabled */ - return 0; - case BSC1_BASE_ADDR: - bscstr = "bsc1_clk"; - apbstr = "bsc1_apb_clk"; - break; - case BSC2_BASE_ADDR: - bscstr = "bsc2_clk"; - apbstr = "bsc2_apb_clk"; - break; - case BSC3_BASE_ADDR: - bscstr = "bsc3_clk"; - apbstr = "bsc3_apb_clk"; - break; - default: - printf("%s: base 0x%p not found\n", __func__, base); - return -EINVAL; - } - - /* Note that the bus clock must be enabled first */ - - ret = clk_get_and_enable(apbstr); - if (ret) - return ret; - - ret = clk_get_and_enable(bscstr); - if (ret) - return ret; - - return 0; -} diff --git a/arch/arm/cpu/armv7/bcm235xx/clk-core.c b/arch/arm/cpu/armv7/bcm235xx/clk-core.c deleted file mode 100644 index fa8af1b6941..00000000000 --- a/arch/arm/cpu/armv7/bcm235xx/clk-core.c +++ /dev/null @@ -1,512 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright 2013 Broadcom Corporation. - */ - -/* - * - * bcm235xx architecture clock framework - * - */ - -#include -#include -#include -#include -#include -#include -#include -#include "clk-core.h" - -#define CLK_WR_ACCESS_PASSWORD 0x00a5a501 -#define WR_ACCESS_OFFSET 0 /* common to all clock blocks */ -#define POLICY_CTL_GO 1 /* Load and refresh policy masks */ -#define POLICY_CTL_GO_ATL 4 /* Active Load */ - -/* Helper function */ -int clk_get_and_enable(char *clkstr) -{ - int ret = 0; - struct clk *c; - - debug("%s: %s\n", __func__, clkstr); - - c = clk_get(clkstr); - if (c) { - ret = clk_enable(c); - if (ret) - return ret; - } else { - printf("%s: Couldn't find %s\n", __func__, clkstr); - return -EINVAL; - } - return ret; -} - -/* - * Poll a register in a CCU's address space, returning when the - * specified bit in that register's value is set (or clear). Delay - * a microsecond after each read of the register. Returns true if - * successful, or false if we gave up trying. - * - * Caller must ensure the CCU lock is held. - */ -#define CLK_GATE_DELAY_USEC 2000 -static inline int wait_bit(void *base, u32 offset, u32 bit, bool want) -{ - unsigned int tries; - u32 bit_mask = 1 << bit; - - for (tries = 0; tries < CLK_GATE_DELAY_USEC; tries++) { - u32 val; - bool bit_val; - - val = readl(base + offset); - bit_val = (val & bit_mask) ? 1 : 0; - if (bit_val == want) - return 0; /* success */ - udelay(1); - } - - debug("%s: timeout on addr 0x%p, waiting for bit %d to go to %d\n", - __func__, base + offset, bit, want); - - return -ETIMEDOUT; -} - -/* Enable a peripheral clock */ -static int peri_clk_enable(struct clk *c, int enable) -{ - int ret = 0; - u32 reg; - struct peri_clock *peri_clk = to_peri_clk(c); - struct peri_clk_data *cd = peri_clk->data; - struct bcm_clk_gate *gate = &cd->gate; - void *base = (void *)c->ccu_clk_mgr_base; - - debug("%s: %s\n", __func__, c->name); - - clk_get_rate(c); /* Make sure rate and sel are filled in */ - - /* enable access */ - writel(CLK_WR_ACCESS_PASSWORD, base + WR_ACCESS_OFFSET); - - if (enable) { - debug("%s %s set rate %lu div %lu sel %d parent %lu\n", - __func__, c->name, c->rate, c->div, c->sel, - c->parent->rate); - - /* - * clkgate - only software controllable gates are - * supported by u-boot which includes all clocks - * that matter. This avoids bringing in a lot of extra - * complexity as done in the kernel framework. - */ - if (gate_exists(gate)) { - reg = readl(base + cd->gate.offset); - reg |= (1 << cd->gate.en_bit); - writel(reg, base + cd->gate.offset); - } - - /* div and pll select */ - if (divider_exists(&cd->div)) { - reg = readl(base + cd->div.offset); - bitfield_replace(reg, cd->div.shift, cd->div.width, - c->div - 1); - writel(reg, base + cd->div.offset); - } - - /* frequency selector */ - if (selector_exists(&cd->sel)) { - reg = readl(base + cd->sel.offset); - bitfield_replace(reg, cd->sel.shift, cd->sel.width, - c->sel); - writel(reg, base + cd->sel.offset); - } - - /* trigger */ - if (trigger_exists(&cd->trig)) { - writel((1 << cd->trig.bit), base + cd->trig.offset); - - /* wait for trigger status bit to go to 0 */ - ret = wait_bit(base, cd->trig.offset, cd->trig.bit, 0); - if (ret) - return ret; - } - - /* wait for running (status_bit = 1) */ - ret = wait_bit(base, cd->gate.offset, cd->gate.status_bit, 1); - if (ret) - return ret; - } else { - debug("%s disable clock %s\n", __func__, c->name); - - /* clkgate */ - reg = readl(base + cd->gate.offset); - reg &= ~(1 << cd->gate.en_bit); - writel(reg, base + cd->gate.offset); - - /* wait for stop (status_bit = 0) */ - ret = wait_bit(base, cd->gate.offset, cd->gate.status_bit, 0); - } - - /* disable access */ - writel(0, base + WR_ACCESS_OFFSET); - - return ret; -} - -/* Set the rate of a peripheral clock */ -static int peri_clk_set_rate(struct clk *c, unsigned long rate) -{ - int ret = 0; - int i; - unsigned long diff; - unsigned long new_rate = 0, div = 1; - struct peri_clock *peri_clk = to_peri_clk(c); - struct peri_clk_data *cd = peri_clk->data; - const char **clock; - - debug("%s: %s\n", __func__, c->name); - diff = rate; - - i = 0; - for (clock = cd->clocks; *clock; clock++, i++) { - struct refclk *ref = refclk_str_to_clk(*clock); - if (!ref) { - printf("%s: Lookup of %s failed\n", __func__, *clock); - return -EINVAL; - } - - /* round to the new rate */ - div = ref->clk.rate / rate; - if (div == 0) - div = 1; - - new_rate = ref->clk.rate / div; - - /* get the min diff */ - if (abs(new_rate - rate) < diff) { - diff = abs(new_rate - rate); - c->sel = i; - c->parent = &ref->clk; - c->rate = new_rate; - c->div = div; - } - } - - debug("%s %s set rate %lu div %lu sel %d parent %lu\n", __func__, - c->name, c->rate, c->div, c->sel, c->parent->rate); - return ret; -} - -/* Get the rate of a peripheral clock */ -static unsigned long peri_clk_get_rate(struct clk *c) -{ - struct peri_clock *peri_clk = to_peri_clk(c); - struct peri_clk_data *cd = peri_clk->data; - void *base = (void *)c->ccu_clk_mgr_base; - int div = 1; - const char **clock; - struct refclk *ref; - u32 reg; - - debug("%s: %s\n", __func__, c->name); - if (selector_exists(&cd->sel)) { - reg = readl(base + cd->sel.offset); - c->sel = bitfield_extract(reg, cd->sel.shift, cd->sel.width); - } else { - /* - * For peri clocks that don't have a selector, the single - * reference clock will always exist at index 0. - */ - c->sel = 0; - } - - if (divider_exists(&cd->div)) { - reg = readl(base + cd->div.offset); - div = bitfield_extract(reg, cd->div.shift, cd->div.width); - div += 1; - } - - clock = cd->clocks; - ref = refclk_str_to_clk(clock[c->sel]); - if (!ref) { - printf("%s: Can't lookup %s\n", __func__, clock[c->sel]); - return 0; - } - - c->parent = &ref->clk; - c->div = div; - c->rate = c->parent->rate / c->div; - debug("%s parent rate %lu div %d sel %d rate %lu\n", __func__, - c->parent->rate, div, c->sel, c->rate); - - return c->rate; -} - -/* Peripheral clock operations */ -struct clk_ops peri_clk_ops = { - .enable = peri_clk_enable, - .set_rate = peri_clk_set_rate, - .get_rate = peri_clk_get_rate, -}; - -/* Enable a CCU clock */ -static int ccu_clk_enable(struct clk *c, int enable) -{ - struct ccu_clock *ccu_clk = to_ccu_clk(c); - void *base = (void *)c->ccu_clk_mgr_base; - int ret = 0; - u32 reg; - - debug("%s: %s\n", __func__, c->name); - if (!enable) - return -EINVAL; /* CCU clock cannot shutdown */ - - /* enable access */ - writel(CLK_WR_ACCESS_PASSWORD, base + WR_ACCESS_OFFSET); - - /* config enable for policy engine */ - writel(1, base + ccu_clk->lvm_en_offset); - - /* wait for bit to go to 0 */ - ret = wait_bit(base, ccu_clk->lvm_en_offset, 0, 0); - if (ret) - return ret; - - /* freq ID */ - if (!ccu_clk->freq_bit_shift) - ccu_clk->freq_bit_shift = 8; - - /* Set frequency id for each of the 4 policies */ - reg = ccu_clk->freq_id | - (ccu_clk->freq_id << (ccu_clk->freq_bit_shift)) | - (ccu_clk->freq_id << (ccu_clk->freq_bit_shift * 2)) | - (ccu_clk->freq_id << (ccu_clk->freq_bit_shift * 3)); - writel(reg, base + ccu_clk->policy_freq_offset); - - /* enable all clock mask */ - writel(0x7fffffff, base + ccu_clk->policy0_mask_offset); - writel(0x7fffffff, base + ccu_clk->policy1_mask_offset); - writel(0x7fffffff, base + ccu_clk->policy2_mask_offset); - writel(0x7fffffff, base + ccu_clk->policy3_mask_offset); - - if (ccu_clk->num_policy_masks == 2) { - writel(0x7fffffff, base + ccu_clk->policy0_mask2_offset); - writel(0x7fffffff, base + ccu_clk->policy1_mask2_offset); - writel(0x7fffffff, base + ccu_clk->policy2_mask2_offset); - writel(0x7fffffff, base + ccu_clk->policy3_mask2_offset); - } - - /* start policy engine */ - reg = readl(base + ccu_clk->policy_ctl_offset); - reg |= (POLICY_CTL_GO + POLICY_CTL_GO_ATL); - writel(reg, base + ccu_clk->policy_ctl_offset); - - /* wait till started */ - ret = wait_bit(base, ccu_clk->policy_ctl_offset, 0, 0); - if (ret) - return ret; - - /* disable access */ - writel(0, base + WR_ACCESS_OFFSET); - - return ret; -} - -/* Get the CCU clock rate */ -static unsigned long ccu_clk_get_rate(struct clk *c) -{ - struct ccu_clock *ccu_clk = to_ccu_clk(c); - debug("%s: %s\n", __func__, c->name); - c->rate = ccu_clk->freq_tbl[ccu_clk->freq_id]; - return c->rate; -} - -/* CCU clock operations */ -struct clk_ops ccu_clk_ops = { - .enable = ccu_clk_enable, - .get_rate = ccu_clk_get_rate, -}; - -/* Enable a bus clock */ -static int bus_clk_enable(struct clk *c, int enable) -{ - struct bus_clock *bus_clk = to_bus_clk(c); - struct bus_clk_data *cd = bus_clk->data; - void *base = (void *)c->ccu_clk_mgr_base; - int ret = 0; - u32 reg; - - debug("%s: %s\n", __func__, c->name); - /* enable access */ - writel(CLK_WR_ACCESS_PASSWORD, base + WR_ACCESS_OFFSET); - - /* enable gating */ - reg = readl(base + cd->gate.offset); - if (!!(reg & (1 << cd->gate.status_bit)) == !!enable) - debug("%s already %s\n", c->name, - enable ? "enabled" : "disabled"); - else { - int want = (enable) ? 1 : 0; - reg |= (1 << cd->gate.hw_sw_sel_bit); - - if (enable) - reg |= (1 << cd->gate.en_bit); - else - reg &= ~(1 << cd->gate.en_bit); - - writel(reg, base + cd->gate.offset); - ret = wait_bit(base, cd->gate.offset, cd->gate.status_bit, - want); - if (ret) - return ret; - } - - /* disable access */ - writel(0, base + WR_ACCESS_OFFSET); - - return ret; -} - -/* Get the rate of a bus clock */ -static unsigned long bus_clk_get_rate(struct clk *c) -{ - struct bus_clock *bus_clk = to_bus_clk(c); - struct ccu_clock *ccu_clk; - - debug("%s: %s\n", __func__, c->name); - ccu_clk = to_ccu_clk(c->parent); - - c->rate = bus_clk->freq_tbl[ccu_clk->freq_id]; - c->div = ccu_clk->freq_tbl[ccu_clk->freq_id] / c->rate; - return c->rate; -} - -/* Bus clock operations */ -struct clk_ops bus_clk_ops = { - .enable = bus_clk_enable, - .get_rate = bus_clk_get_rate, -}; - -/* Enable a reference clock */ -static int ref_clk_enable(struct clk *c, int enable) -{ - debug("%s: %s\n", __func__, c->name); - return 0; -} - -/* Reference clock operations */ -struct clk_ops ref_clk_ops = { - .enable = ref_clk_enable, -}; - -/* - * clk.h implementation follows - */ - -/* Initialize the clock framework */ -int clk_init(void) -{ - debug("%s:\n", __func__); - return 0; -} - -/* Get a clock handle, give a name string */ -struct clk *clk_get(const char *con_id) -{ - int i; - struct clk_lookup *clk_tblp; - - debug("%s: %s\n", __func__, con_id); - - clk_tblp = arch_clk_tbl; - for (i = 0; i < arch_clk_tbl_array_size; i++, clk_tblp++) { - if (clk_tblp->con_id) { - if (!con_id || strcmp(clk_tblp->con_id, con_id)) - continue; - return clk_tblp->clk; - } - } - return NULL; -} - -/* Enable a clock */ -int clk_enable(struct clk *c) -{ - int ret = 0; - - debug("%s: %s\n", __func__, c->name); - if (!c->ops || !c->ops->enable) - return -1; - - /* enable parent clock first */ - if (c->parent) - ret = clk_enable(c->parent); - - if (ret) - return ret; - - if (!c->use_cnt) - ret = c->ops->enable(c, 1); - c->use_cnt++; - - return ret; -} - -/* Disable a clock */ -void clk_disable(struct clk *c) -{ - debug("%s: %s\n", __func__, c->name); - if (!c->ops || !c->ops->enable) - return; - - if (c->use_cnt > 0) { - c->use_cnt--; - if (c->use_cnt == 0) - c->ops->enable(c, 0); - } - - /* disable parent */ - if (c->parent) - clk_disable(c->parent); -} - -/* Get the clock rate */ -unsigned long clk_get_rate(struct clk *c) -{ - unsigned long rate; - - if (!c || !c->ops || !c->ops->get_rate) - return 0; - debug("%s: %s\n", __func__, c->name); - - rate = c->ops->get_rate(c); - debug("%s: rate = %ld\n", __func__, rate); - return rate; -} - -/* Set the clock rate */ -int clk_set_rate(struct clk *c, unsigned long rate) -{ - int ret; - - if (!c || !c->ops || !c->ops->set_rate) - return -EINVAL; - debug("%s: %s rate=%ld\n", __func__, c->name, rate); - - if (c->use_cnt) - return -EINVAL; - - ret = c->ops->set_rate(c, rate); - - return ret; -} - -/* Not required for this arch */ -/* -long clk_round_rate(struct clk *clk, unsigned long rate); -int clk_set_parent(struct clk *clk, struct clk *parent); -struct clk *clk_get_parent(struct clk *clk); -*/ diff --git a/arch/arm/cpu/armv7/bcm235xx/clk-core.h b/arch/arm/cpu/armv7/bcm235xx/clk-core.h deleted file mode 100644 index ace384dea78..00000000000 --- a/arch/arm/cpu/armv7/bcm235xx/clk-core.h +++ /dev/null @@ -1,491 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright 2013 Broadcom Corporation. - */ - -#include -#include - -#ifdef CONFIG_CLK_DEBUG -#undef writel -#undef readl -static inline void writel(u32 val, void *addr) -{ - printf("Write [0x%p] = 0x%08x\n", addr, val); - *(u32 *)addr = val; -} - -static inline u32 readl(void *addr) -{ - u32 val = *(u32 *)addr; - printf("Read [0x%p] = 0x%08x\n", addr, val); - return val; -} -#endif - -struct clk; - -struct clk_lookup { - const char *dev_id; - const char *con_id; - struct clk *clk; -}; - -extern struct clk_lookup arch_clk_tbl[]; -extern unsigned int arch_clk_tbl_array_size; - -/** - * struct clk_ops - standard clock operations - * @enable: enable/disable clock, see clk_enable() and clk_disable() - * @set_rate: set the clock rate, see clk_set_rate(). - * @get_rate: get the clock rate, see clk_get_rate(). - * @round_rate: round a given clock rate, see clk_round_rate(). - * @set_parent: set the clock's parent, see clk_set_parent(). - * - * Group the common clock implementations together so that we - * don't have to keep setting the same fiels again. We leave - * enable in struct clk. - * - */ -struct clk_ops { - int (*enable)(struct clk *c, int enable); - int (*set_rate)(struct clk *c, unsigned long rate); - unsigned long (*get_rate)(struct clk *c); - unsigned long (*round_rate)(struct clk *c, unsigned long rate); - int (*set_parent)(struct clk *c, struct clk *parent); -}; - -struct clk { - struct clk *parent; - const char *name; - int use_cnt; - unsigned long rate; /* in HZ */ - - /* programmable divider. 0 means fixed ratio to parent clock */ - unsigned long div; - - struct clk_src *src; - struct clk_ops *ops; - - unsigned long ccu_clk_mgr_base; - int sel; -}; - -struct refclk *refclk_str_to_clk(const char *name); - -/* The common clock framework uses u8 to represent a parent index */ -#define PARENT_COUNT_MAX ((u32)U8_MAX) - -#define BAD_CLK_INDEX U8_MAX /* Can't ever be valid */ -#define BAD_CLK_NAME ((const char *)-1) - -#define BAD_SCALED_DIV_VALUE U64_MAX - -/* - * Utility macros for object flag management. If possible, flags - * should be defined such that 0 is the desired default value. - */ -#define FLAG(type, flag) BCM_CLK_ ## type ## _FLAGS_ ## flag -#define FLAG_SET(obj, type, flag) ((obj)->flags |= FLAG(type, flag)) -#define FLAG_CLEAR(obj, type, flag) ((obj)->flags &= ~(FLAG(type, flag))) -#define FLAG_FLIP(obj, type, flag) ((obj)->flags ^= FLAG(type, flag)) -#define FLAG_TEST(obj, type, flag) (!!((obj)->flags & FLAG(type, flag))) - -/* Clock field state tests */ - -#define gate_exists(gate) FLAG_TEST(gate, GATE, EXISTS) -#define gate_is_enabled(gate) FLAG_TEST(gate, GATE, ENABLED) -#define gate_is_hw_controllable(gate) FLAG_TEST(gate, GATE, HW) -#define gate_is_sw_controllable(gate) FLAG_TEST(gate, GATE, SW) -#define gate_is_sw_managed(gate) FLAG_TEST(gate, GATE, SW_MANAGED) -#define gate_is_no_disable(gate) FLAG_TEST(gate, GATE, NO_DISABLE) - -#define gate_flip_enabled(gate) FLAG_FLIP(gate, GATE, ENABLED) - -#define divider_exists(div) FLAG_TEST(div, DIV, EXISTS) -#define divider_is_fixed(div) FLAG_TEST(div, DIV, FIXED) -#define divider_has_fraction(div) (!divider_is_fixed(div) && \ - (div)->frac_width > 0) - -#define selector_exists(sel) ((sel)->width != 0) -#define trigger_exists(trig) FLAG_TEST(trig, TRIG, EXISTS) - -/* Clock type, used to tell common block what it's part of */ -enum bcm_clk_type { - bcm_clk_none, /* undefined clock type */ - bcm_clk_bus, - bcm_clk_core, - bcm_clk_peri -}; - -/* - * Gating control and status is managed by a 32-bit gate register. - * - * There are several types of gating available: - * - (no gate) - * A clock with no gate is assumed to be always enabled. - * - hardware-only gating (auto-gating) - * Enabling or disabling clocks with this type of gate is - * managed automatically by the hardware. Such clocks can be - * considered by the software to be enabled. The current status - * of auto-gated clocks can be read from the gate status bit. - * - software-only gating - * Auto-gating is not available for this type of clock. - * Instead, software manages whether it's enabled by setting or - * clearing the enable bit. The current gate status of a gate - * under software control can be read from the gate status bit. - * To ensure a change to the gating status is complete, the - * status bit can be polled to verify that the gate has entered - * the desired state. - * - selectable hardware or software gating - * Gating for this type of clock can be configured to be either - * under software or hardware control. Which type is in use is - * determined by the hw_sw_sel bit of the gate register. - */ -struct bcm_clk_gate { - u32 offset; /* gate register offset */ - u32 status_bit; /* 0: gate is disabled; 0: gatge is enabled */ - u32 en_bit; /* 0: disable; 1: enable */ - u32 hw_sw_sel_bit; /* 0: hardware gating; 1: software gating */ - u32 flags; /* BCM_CLK_GATE_FLAGS_* below */ -}; - -/* - * Gate flags: - * HW means this gate can be auto-gated - * SW means the state of this gate can be software controlled - * NO_DISABLE means this gate is (only) enabled if under software control - * SW_MANAGED means the status of this gate is under software control - * ENABLED means this software-managed gate is *supposed* to be enabled - */ -#define BCM_CLK_GATE_FLAGS_EXISTS ((u32)1 << 0) /* Gate is valid */ -#define BCM_CLK_GATE_FLAGS_HW ((u32)1 << 1) /* Can auto-gate */ -#define BCM_CLK_GATE_FLAGS_SW ((u32)1 << 2) /* Software control */ -#define BCM_CLK_GATE_FLAGS_NO_DISABLE ((u32)1 << 3) /* HW or enabled */ -#define BCM_CLK_GATE_FLAGS_SW_MANAGED ((u32)1 << 4) /* SW now in control */ -#define BCM_CLK_GATE_FLAGS_ENABLED ((u32)1 << 5) /* If SW_MANAGED */ - -/* - * Gate initialization macros. - * - * Any gate initially under software control will be enabled. - */ - -/* A hardware/software gate initially under software control */ -#define HW_SW_GATE(_offset, _status_bit, _en_bit, _hw_sw_sel_bit) \ - { \ - .offset = (_offset), \ - .status_bit = (_status_bit), \ - .en_bit = (_en_bit), \ - .hw_sw_sel_bit = (_hw_sw_sel_bit), \ - .flags = FLAG(GATE, HW)|FLAG(GATE, SW)| \ - FLAG(GATE, SW_MANAGED)|FLAG(GATE, ENABLED)| \ - FLAG(GATE, EXISTS), \ - } - -/* A hardware/software gate initially under hardware control */ -#define HW_SW_GATE_AUTO(_offset, _status_bit, _en_bit, _hw_sw_sel_bit) \ - { \ - .offset = (_offset), \ - .status_bit = (_status_bit), \ - .en_bit = (_en_bit), \ - .hw_sw_sel_bit = (_hw_sw_sel_bit), \ - .flags = FLAG(GATE, HW)|FLAG(GATE, SW)| \ - FLAG(GATE, EXISTS), \ - } - -/* A hardware-or-enabled gate (enabled if not under hardware control) */ -#define HW_ENABLE_GATE(_offset, _status_bit, _en_bit, _hw_sw_sel_bit) \ - { \ - .offset = (_offset), \ - .status_bit = (_status_bit), \ - .en_bit = (_en_bit), \ - .hw_sw_sel_bit = (_hw_sw_sel_bit), \ - .flags = FLAG(GATE, HW)|FLAG(GATE, SW)| \ - FLAG(GATE, NO_DISABLE)|FLAG(GATE, EXISTS), \ - } - -/* A software-only gate */ -#define SW_ONLY_GATE(_offset, _status_bit, _en_bit) \ - { \ - .offset = (_offset), \ - .status_bit = (_status_bit), \ - .en_bit = (_en_bit), \ - .flags = FLAG(GATE, SW)|FLAG(GATE, SW_MANAGED)| \ - FLAG(GATE, ENABLED)|FLAG(GATE, EXISTS), \ - } - -/* A hardware-only gate */ -#define HW_ONLY_GATE(_offset, _status_bit) \ - { \ - .offset = (_offset), \ - .status_bit = (_status_bit), \ - .flags = FLAG(GATE, HW)|FLAG(GATE, EXISTS), \ - } - -/* - * Each clock can have zero, one, or two dividers which change the - * output rate of the clock. Each divider can be either fixed or - * variable. If there are two dividers, they are the "pre-divider" - * and the "regular" or "downstream" divider. If there is only one, - * there is no pre-divider. - * - * A fixed divider is any non-zero (positive) value, and it - * indicates how the input rate is affected by the divider. - * - * The value of a variable divider is maintained in a sub-field of a - * 32-bit divider register. The position of the field in the - * register is defined by its offset and width. The value recorded - * in this field is always 1 less than the value it represents. - * - * In addition, a variable divider can indicate that some subset - * of its bits represent a "fractional" part of the divider. Such - * bits comprise the low-order portion of the divider field, and can - * be viewed as representing the portion of the divider that lies to - * the right of the decimal point. Most variable dividers have zero - * fractional bits. Variable dividers with non-zero fraction width - * still record a value 1 less than the value they represent; the - * added 1 does *not* affect the low-order bit in this case, it - * affects the bits above the fractional part only. (Often in this - * code a divider field value is distinguished from the value it - * represents by referring to the latter as a "divisor".) - * - * In order to avoid dealing with fractions, divider arithmetic is - * performed using "scaled" values. A scaled value is one that's - * been left-shifted by the fractional width of a divider. Dividing - * a scaled value by a scaled divisor produces the desired quotient - * without loss of precision and without any other special handling - * for fractions. - * - * The recorded value of a variable divider can be modified. To - * modify either divider (or both), a clock must be enabled (i.e., - * using its gate). In addition, a trigger register (described - * below) must be used to commit the change, and polled to verify - * the change is complete. - */ -struct bcm_clk_div { - union { - struct { /* variable divider */ - u32 offset; /* divider register offset */ - u32 shift; /* field shift */ - u32 width; /* field width */ - u32 frac_width; /* field fraction width */ - - u64 scaled_div; /* scaled divider value */ - }; - u32 fixed; /* non-zero fixed divider value */ - }; - u32 flags; /* BCM_CLK_DIV_FLAGS_* below */ -}; - -/* - * Divider flags: - * EXISTS means this divider exists - * FIXED means it is a fixed-rate divider - */ -#define BCM_CLK_DIV_FLAGS_EXISTS ((u32)1 << 0) /* Divider is valid */ -#define BCM_CLK_DIV_FLAGS_FIXED ((u32)1 << 1) /* Fixed-value */ - -/* Divider initialization macros */ - -/* A fixed (non-zero) divider */ -#define FIXED_DIVIDER(_value) \ - { \ - .fixed = (_value), \ - .flags = FLAG(DIV, EXISTS)|FLAG(DIV, FIXED), \ - } - -/* A divider with an integral divisor */ -#define DIVIDER(_offset, _shift, _width) \ - { \ - .offset = (_offset), \ - .shift = (_shift), \ - .width = (_width), \ - .scaled_div = BAD_SCALED_DIV_VALUE, \ - .flags = FLAG(DIV, EXISTS), \ - } - -/* A divider whose divisor has an integer and fractional part */ -#define FRAC_DIVIDER(_offset, _shift, _width, _frac_width) \ - { \ - .offset = (_offset), \ - .shift = (_shift), \ - .width = (_width), \ - .frac_width = (_frac_width), \ - .scaled_div = BAD_SCALED_DIV_VALUE, \ - .flags = FLAG(DIV, EXISTS), \ - } - -/* - * Clocks may have multiple "parent" clocks. If there is more than - * one, a selector must be specified to define which of the parent - * clocks is currently in use. The selected clock is indicated in a - * sub-field of a 32-bit selector register. The range of - * representable selector values typically exceeds the number of - * available parent clocks. Occasionally the reset value of a - * selector field is explicitly set to a (specific) value that does - * not correspond to a defined input clock. - * - * We register all known parent clocks with the common clock code - * using a packed array (i.e., no empty slots) of (parent) clock - * names, and refer to them later using indexes into that array. - * We maintain an array of selector values indexed by common clock - * index values in order to map between these common clock indexes - * and the selector values used by the hardware. - * - * Like dividers, a selector can be modified, but to do so a clock - * must be enabled, and a trigger must be used to commit the change. - */ -struct bcm_clk_sel { - u32 offset; /* selector register offset */ - u32 shift; /* field shift */ - u32 width; /* field width */ - - u32 parent_count; /* number of entries in parent_sel[] */ - u32 *parent_sel; /* array of parent selector values */ - u8 clk_index; /* current selected index in parent_sel[] */ -}; - -/* Selector initialization macro */ -#define SELECTOR(_offset, _shift, _width) \ - { \ - .offset = (_offset), \ - .shift = (_shift), \ - .width = (_width), \ - .clk_index = BAD_CLK_INDEX, \ - } - -/* - * Making changes to a variable divider or a selector for a clock - * requires the use of a trigger. A trigger is defined by a single - * bit within a register. To signal a change, a 1 is written into - * that bit. To determine when the change has been completed, that - * trigger bit is polled; the read value will be 1 while the change - * is in progress, and 0 when it is complete. - * - * Occasionally a clock will have more than one trigger. In this - * case, the "pre-trigger" will be used when changing a clock's - * selector and/or its pre-divider. - */ -struct bcm_clk_trig { - u32 offset; /* trigger register offset */ - u32 bit; /* trigger bit */ - u32 flags; /* BCM_CLK_TRIG_FLAGS_* below */ -}; - -/* - * Trigger flags: - * EXISTS means this trigger exists - */ -#define BCM_CLK_TRIG_FLAGS_EXISTS ((u32)1 << 0) /* Trigger is valid */ - -/* Trigger initialization macro */ -#define TRIGGER(_offset, _bit) \ - { \ - .offset = (_offset), \ - .bit = (_bit), \ - .flags = FLAG(TRIG, EXISTS), \ - } - -struct bus_clk_data { - struct bcm_clk_gate gate; -}; - -struct core_clk_data { - struct bcm_clk_gate gate; -}; - -struct peri_clk_data { - struct bcm_clk_gate gate; - struct bcm_clk_trig pre_trig; - struct bcm_clk_div pre_div; - struct bcm_clk_trig trig; - struct bcm_clk_div div; - struct bcm_clk_sel sel; - const char *clocks[]; /* must be last; use CLOCKS() to declare */ -}; -#define CLOCKS(...) { __VA_ARGS__, NULL, } -#define NO_CLOCKS { NULL, } /* Must use of no parent clocks */ - -struct refclk { - struct clk clk; -}; - -struct peri_clock { - struct clk clk; - struct peri_clk_data *data; -}; - -struct ccu_clock { - struct clk clk; - - int num_policy_masks; - unsigned long policy_freq_offset; - int freq_bit_shift; /* 8 for most CCUs */ - unsigned long policy_ctl_offset; - unsigned long policy0_mask_offset; - unsigned long policy1_mask_offset; - unsigned long policy2_mask_offset; - unsigned long policy3_mask_offset; - unsigned long policy0_mask2_offset; - unsigned long policy1_mask2_offset; - unsigned long policy2_mask2_offset; - unsigned long policy3_mask2_offset; - unsigned long lvm_en_offset; - - int freq_id; - unsigned long *freq_tbl; -}; - -struct bus_clock { - struct clk clk; - struct bus_clk_data *data; - unsigned long *freq_tbl; -}; - -struct ref_clock { - struct clk clk; -}; - -static inline int is_same_clock(struct clk *a, struct clk *b) -{ - return a == b; -} - -#define to_clk(p) (&((p)->clk)) -#define name_to_clk(name) (&((name##_clk).clk)) -/* declare a struct clk_lookup */ -#define CLK_LK(name) \ -{.con_id = __stringify(name##_clk), .clk = name_to_clk(name),} - -static inline struct refclk *to_refclk(struct clk *clock) -{ - return container_of(clock, struct refclk, clk); -} - -static inline struct peri_clock *to_peri_clk(struct clk *clock) -{ - return container_of(clock, struct peri_clock, clk); -} - -static inline struct ccu_clock *to_ccu_clk(struct clk *clock) -{ - return container_of(clock, struct ccu_clock, clk); -} - -static inline struct bus_clock *to_bus_clk(struct clk *clock) -{ - return container_of(clock, struct bus_clock, clk); -} - -static inline struct ref_clock *to_ref_clk(struct clk *clock) -{ - return container_of(clock, struct ref_clock, clk); -} - -extern struct clk_ops peri_clk_ops; -extern struct clk_ops ccu_clk_ops; -extern struct clk_ops bus_clk_ops; -extern struct clk_ops ref_clk_ops; - -int clk_get_and_enable(char *clkstr); diff --git a/arch/arm/cpu/armv7/bcm235xx/clk-eth.c b/arch/arm/cpu/armv7/bcm235xx/clk-eth.c deleted file mode 100644 index 5f7cc4a102d..00000000000 --- a/arch/arm/cpu/armv7/bcm235xx/clk-eth.c +++ /dev/null @@ -1,142 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright 2014 Broadcom Corporation. - */ - -#include -#include -#include -#include -#include -#include "clk-core.h" - -#define WR_ACCESS_ADDR ESUB_CLK_BASE_ADDR -#define WR_ACCESS_PASSWORD 0xA5A500 - -#define PLLE_POST_RESETB_ADDR (ESUB_CLK_BASE_ADDR + 0x00000C00) - -#define PLLE_RESETB_ADDR (ESUB_CLK_BASE_ADDR + 0x00000C58) -#define PLLE_RESETB_I_PLL_RESETB_PLLE_MASK 0x00010000 -#define PLLE_POST_RESETB_I_POST_RESETB_PLLE_MASK 0x00000001 - -#define PLL_LOCK_ADDR (ESUB_CLK_BASE_ADDR + 0x00000C38) -#define PLL_LOCK_PLL_LOCK_PLLE_MASK 0x00000001 - -#define ESW_SYS_DIV_ADDR (ESUB_CLK_BASE_ADDR + 0x00000A04) -#define ESW_SYS_DIV_PLL_SELECT_MASK 0x00000300 -#define ESW_SYS_DIV_DIV_MASK 0x0000001C -#define ESW_SYS_DIV_PLL_VAR_208M_CLK_SELECT 0x00000100 -#define ESW_SYS_DIV_DIV_SELECT 0x4 -#define ESW_SYS_DIV_TRIGGER_MASK 0x00000001 - -#define ESUB_AXI_DIV_DEBUG_ADDR (ESUB_CLK_BASE_ADDR + 0x00000E04) -#define ESUB_AXI_DIV_DEBUG_PLL_SELECT_MASK 0x0000001C -#define ESUB_AXI_DIV_DEBUG_PLL_SELECT_OVERRIDE_MASK 0x00000040 -#define ESUB_AXI_DIV_DEBUG_PLL_VAR_208M_CLK_SELECT 0x0 -#define ESUB_AXI_DIV_DEBUG_TRIGGER_MASK 0x00000001 - -#define PLL_MAX_RETRY 100 - -/* Enable appropriate clocks for Ethernet */ -int clk_eth_enable(void) -{ - int rc = -1; - int retry_count = 0; - rc = clk_get_and_enable("esub_ccu_clk"); - - /* Enable Access to CCU registers */ - writel((1 | WR_ACCESS_PASSWORD), WR_ACCESS_ADDR); - - writel(readl(PLLE_POST_RESETB_ADDR) & - ~PLLE_POST_RESETB_I_POST_RESETB_PLLE_MASK, - PLLE_POST_RESETB_ADDR); - - /* Take PLL out of reset and put into normal mode */ - writel(readl(PLLE_RESETB_ADDR) | PLLE_RESETB_I_PLL_RESETB_PLLE_MASK, - PLLE_RESETB_ADDR); - - /* Wait for PLL lock */ - rc = -1; - while (retry_count < PLL_MAX_RETRY) { - udelay(100); - if (readl(PLL_LOCK_ADDR) & PLL_LOCK_PLL_LOCK_PLLE_MASK) { - rc = 0; - break; - } - retry_count++; - } - - if (rc == -1) { - printf("%s: ETH-PLL lock timeout, Ethernet is not enabled!\n", - __func__); - return -1; - } - - writel(readl(PLLE_POST_RESETB_ADDR) | - PLLE_POST_RESETB_I_POST_RESETB_PLLE_MASK, - PLLE_POST_RESETB_ADDR); - - /* Switch esw_sys_clk to use 104MHz(208MHz/2) clock */ - writel((readl(ESW_SYS_DIV_ADDR) & - ~(ESW_SYS_DIV_PLL_SELECT_MASK | ESW_SYS_DIV_DIV_MASK)) | - ESW_SYS_DIV_PLL_VAR_208M_CLK_SELECT | ESW_SYS_DIV_DIV_SELECT, - ESW_SYS_DIV_ADDR); - - writel(readl(ESW_SYS_DIV_ADDR) | ESW_SYS_DIV_TRIGGER_MASK, - ESW_SYS_DIV_ADDR); - - /* Wait for trigger complete */ - rc = -1; - retry_count = 0; - while (retry_count < PLL_MAX_RETRY) { - udelay(100); - if (!(readl(ESW_SYS_DIV_ADDR) & ESW_SYS_DIV_TRIGGER_MASK)) { - rc = 0; - break; - } - retry_count++; - } - - if (rc == -1) { - printf("%s: SYS CLK Trigger timeout, Ethernet is not enabled!\n", - __func__); - return -1; - } - - /* switch Esub AXI clock to 208MHz */ - writel((readl(ESUB_AXI_DIV_DEBUG_ADDR) & - ~(ESUB_AXI_DIV_DEBUG_PLL_SELECT_MASK | - ESUB_AXI_DIV_DEBUG_PLL_SELECT_OVERRIDE_MASK | - ESUB_AXI_DIV_DEBUG_TRIGGER_MASK)) | - ESUB_AXI_DIV_DEBUG_PLL_VAR_208M_CLK_SELECT | - ESUB_AXI_DIV_DEBUG_PLL_SELECT_OVERRIDE_MASK, - ESUB_AXI_DIV_DEBUG_ADDR); - - writel(readl(ESUB_AXI_DIV_DEBUG_ADDR) | - ESUB_AXI_DIV_DEBUG_TRIGGER_MASK, - ESUB_AXI_DIV_DEBUG_ADDR); - - /* Wait for trigger complete */ - rc = -1; - retry_count = 0; - while (retry_count < PLL_MAX_RETRY) { - udelay(100); - if (!(readl(ESUB_AXI_DIV_DEBUG_ADDR) & - ESUB_AXI_DIV_DEBUG_TRIGGER_MASK)) { - rc = 0; - break; - } - retry_count++; - } - - if (rc == -1) { - printf("%s: AXI CLK Trigger timeout, Ethernet is not enabled!\n", - __func__); - return -1; - } - - /* Disable Access to CCU registers */ - writel(WR_ACCESS_PASSWORD, WR_ACCESS_ADDR); - - return rc; -} diff --git a/arch/arm/cpu/armv7/bcm235xx/clk-sdio.c b/arch/arm/cpu/armv7/bcm235xx/clk-sdio.c deleted file mode 100644 index f3ff29bebe8..00000000000 --- a/arch/arm/cpu/armv7/bcm235xx/clk-sdio.c +++ /dev/null @@ -1,71 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright 2013 Broadcom Corporation. - */ - -#include -#include -#include -#include -#include "clk-core.h" - -/* Enable appropriate clocks for an SDIO port */ -int clk_sdio_enable(void *base, u32 rate, u32 *actual_ratep) -{ - int ret; - struct clk *c; - - char *clkstr; - char *slpstr; - char *ahbstr; - - switch ((u32) base) { - case CONFIG_SYS_SDIO_BASE0: - clkstr = CONFIG_SYS_SDIO0 "_clk"; - ahbstr = CONFIG_SYS_SDIO0 "_ahb_clk"; - slpstr = CONFIG_SYS_SDIO0 "_sleep_clk"; - break; - case CONFIG_SYS_SDIO_BASE1: - clkstr = CONFIG_SYS_SDIO1 "_clk"; - ahbstr = CONFIG_SYS_SDIO1 "_ahb_clk"; - slpstr = CONFIG_SYS_SDIO1 "_sleep_clk"; - break; - case CONFIG_SYS_SDIO_BASE2: - clkstr = CONFIG_SYS_SDIO2 "_clk"; - ahbstr = CONFIG_SYS_SDIO2 "_ahb_clk"; - slpstr = CONFIG_SYS_SDIO2 "_sleep_clk"; - break; - case CONFIG_SYS_SDIO_BASE3: - clkstr = CONFIG_SYS_SDIO3 "_clk"; - ahbstr = CONFIG_SYS_SDIO3 "_ahb_clk"; - slpstr = CONFIG_SYS_SDIO3 "_sleep_clk"; - break; - default: - printf("%s: base 0x%p not found\n", __func__, base); - return -EINVAL; - } - - ret = clk_get_and_enable(ahbstr); - if (ret) - return ret; - - ret = clk_get_and_enable(slpstr); - if (ret) - return ret; - - c = clk_get(clkstr); - if (c) { - ret = clk_set_rate(c, rate); - if (ret) - return ret; - - ret = clk_enable(c); - if (ret) - return ret; - } else { - printf("%s: Couldn't find %s\n", __func__, clkstr); - return -EINVAL; - } - *actual_ratep = rate; - return 0; -} diff --git a/arch/arm/cpu/armv7/bcm235xx/clk-usb-otg.c b/arch/arm/cpu/armv7/bcm235xx/clk-usb-otg.c deleted file mode 100644 index 87918059408..00000000000 --- a/arch/arm/cpu/armv7/bcm235xx/clk-usb-otg.c +++ /dev/null @@ -1,25 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright 2014 Broadcom Corporation. - */ - -#include -#include -#include "clk-core.h" - -/* Enable appropriate clocks for the USB OTG port */ -int clk_usb_otg_enable(void *base) -{ - char *ahbstr; - - switch ((u32) base) { - case HSOTG_BASE_ADDR: - ahbstr = "usb_otg_ahb_clk"; - break; - default: - printf("%s: base 0x%p not found\n", __func__, base); - return -EINVAL; - } - - return clk_get_and_enable(ahbstr); -} diff --git a/arch/arm/include/asm/arch-bcm235xx/boot0.h b/arch/arm/include/asm/arch-bcm235xx/boot0.h deleted file mode 100644 index 8cde42b89bb..00000000000 --- a/arch/arm/include/asm/arch-bcm235xx/boot0.h +++ /dev/null @@ -1,10 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright 2016 Broadcom Corporation. - */ - -/* BOOT0 header information */ -_start: - ARM_VECTORS - .word 0xbabeface - .word _end - _start diff --git a/arch/arm/include/asm/arch-bcm235xx/gpio.h b/arch/arm/include/asm/arch-bcm235xx/gpio.h deleted file mode 100644 index 82c12bb70c2..00000000000 --- a/arch/arm/include/asm/arch-bcm235xx/gpio.h +++ /dev/null @@ -1,14 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright 2013 Broadcom Corporation. - */ - -#ifndef __ARCH_BCM235XX_GPIO_H -#define __ARCH_BCM235XX_GPIO_H - -/* - * Empty file - cmd_gpio.c requires this. The implementation - * is in drivers/gpio/kona_gpio.c instead of inlined here. - */ - -#endif diff --git a/arch/arm/include/asm/arch-bcm235xx/sysmap.h b/arch/arm/include/asm/arch-bcm235xx/sysmap.h deleted file mode 100644 index ff6debc677c..00000000000 --- a/arch/arm/include/asm/arch-bcm235xx/sysmap.h +++ /dev/null @@ -1,30 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright 2013 Broadcom Corporation. - */ - -#ifndef __ARCH_BCM235XX_SYSMAP_H - -#define BSC1_BASE_ADDR 0x3e016000 -#define BSC2_BASE_ADDR 0x3e017000 -#define BSC3_BASE_ADDR 0x3e018000 -#define GPIO2_BASE_ADDR 0x35003000 -#define HSOTG_BASE_ADDR 0x3f120000 -#define HSOTG_CTRL_BASE_ADDR 0x3f130000 -#define KONA_MST_CLK_BASE_ADDR 0x3f001000 -#define KONA_SLV_CLK_BASE_ADDR 0x3e011000 -#define PMU_BSC_BASE_ADDR 0x3500d000 -#define SDIO1_BASE_ADDR 0x3f180000 -#define SDIO2_BASE_ADDR 0x3f190000 -#define SDIO3_BASE_ADDR 0x3f1a0000 -#define SDIO4_BASE_ADDR 0x3f1b0000 -#define TIMER_BASE_ADDR 0x3e00d000 - -#define HSOTG_DCTL_OFFSET 0x00000804 -#define HSOTG_DCTL_SFTDISCON_MASK 0x00000002 - -#define HSOTG_CTRL_PHY_P1CTL_OFFSET 0x00000008 -#define HSOTG_CTRL_PHY_P1CTL_SOFT_RESET_MASK 0x00000002 -#define HSOTG_CTRL_PHY_P1CTL_NON_DRIVING_MASK 0x00000001 - -#endif -- cgit v1.2.3 From 493c3da3ac530229ca4c4caadd5df041f6c25eb2 Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Thu, 17 Jul 2025 19:15:52 -0600 Subject: sandbox: Add more dummy functions to mimic other architectures This adds more common functions found on other architectures that will allow for more compile-testing of drivers. These are either dummy functions as we do not need them or mappings to existing functions, similar to how other architectures handle it. Signed-off-by: Tom Rini --- arch/sandbox/include/asm/dma-mapping.h | 27 +++++++++++++++++++++++++++ arch/sandbox/include/asm/io.h | 13 +++++++++++++ arch/sandbox/include/asm/processor.h | 3 ++- drivers/i3c/master/dw-i3c-master.c | 4 ---- 4 files changed, 42 insertions(+), 5 deletions(-) diff --git a/arch/sandbox/include/asm/dma-mapping.h b/arch/sandbox/include/asm/dma-mapping.h index 853b0877b33..410760c2231 100644 --- a/arch/sandbox/include/asm/dma-mapping.h +++ b/arch/sandbox/include/asm/dma-mapping.h @@ -1 +1,28 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copied from arch/arm/include/asm/dma-mapping.h which is: + * + * (C) Copyright 2007 + * Stelian Pop + * Lead Tech Design + */ + +#ifndef __ASM_SANDBOX_DMA_MAPPING_H +#define __ASM_SANDBOX_DMA_MAPPING_H + +#include +#include +#include + +static inline void *dma_alloc_coherent(size_t len, unsigned long *handle) +{ + *handle = (unsigned long)memalign(ARCH_DMA_MINALIGN, ROUND(len, ARCH_DMA_MINALIGN)); + return (void *)*handle; +} + +static inline void dma_free_coherent(void *addr) +{ + free(addr); +} + +#endif diff --git a/arch/sandbox/include/asm/io.h b/arch/sandbox/include/asm/io.h index 11ed89e0071..72953828f96 100644 --- a/arch/sandbox/include/asm/io.h +++ b/arch/sandbox/include/asm/io.h @@ -12,6 +12,9 @@ static inline void sync(void) { } +#define mb() sync() +#define dmb() sync() + enum sandboxio_size_t { SB_SIZE_8, SB_SIZE_16, @@ -53,6 +56,16 @@ void sandbox_write(void *addr, unsigned int val, enum sandboxio_size_t size); #define writeq(v, addr) sandbox_write((void *)addr, v, SB_SIZE_64) #endif +#define readb_relaxed readb +#define readw_relaxed readw +#define readl_relaxed readl +#define readq_relaxed readq + +#define writeb_relaxed writeb +#define writew_relaxed writew +#define writel_relaxed writel +#define writeq_relaxed writeq + /* * Clear and set bits in one shot. These macros can be used to clear and * set multiple bits in a register using a single call. These macros can diff --git a/arch/sandbox/include/asm/processor.h b/arch/sandbox/include/asm/processor.h index 8dced6006bd..6521274efb0 100644 --- a/arch/sandbox/include/asm/processor.h +++ b/arch/sandbox/include/asm/processor.h @@ -6,6 +6,7 @@ #ifndef _ASM_PROCESSOR_H #define _ASM_PROCESSOR_H -/* This file is required for PCI */ +/* Assorted dummy functions */ +#define cpu_relax() #endif diff --git a/drivers/i3c/master/dw-i3c-master.c b/drivers/i3c/master/dw-i3c-master.c index d96eb9b134e..0c4af7e528a 100644 --- a/drivers/i3c/master/dw-i3c-master.c +++ b/drivers/i3c/master/dw-i3c-master.c @@ -21,10 +21,6 @@ #include #include -#ifdef CONFIG_SANDBOX -#define cpu_relax() do {} while (0) -#endif - static u8 even_parity(u8 p) { p ^= p >> 4; -- cgit v1.2.3 From bd644d9613ee0cdc3bd2ac3bc7bcc52b09d821e7 Mon Sep 17 00:00:00 2001 From: Andrew Goodbody Date: Fri, 25 Jul 2025 11:41:12 +0100 Subject: clk: cdce9xx: Fix use of dev_read_u32_default The function dev_read_u32_default does not return an error and the variable 'val' is unsigned so testing for >= 0 will always be true. It looks like the code was attempting to return -1 if xtal-load-pf was not present but that cannot work. Instead use dev_read_u32 which returns an error code separately from writing the value into the passed pointer. This issue was found by Smatch. Signed-off-by: Andrew Goodbody Fixes: 260777fc2333 ("clk: cdce9xx: add support for cdce9xx clock synthesizer") Acked-by: Quentin Schulz --- drivers/clk/clk-cdce9xx.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/drivers/clk/clk-cdce9xx.c b/drivers/clk/clk-cdce9xx.c index e5f74e714d5..996cc30683e 100644 --- a/drivers/clk/clk-cdce9xx.c +++ b/drivers/clk/clk-cdce9xx.c @@ -116,8 +116,7 @@ static int cdce9xx_clk_probe(struct udevice *dev) ret = clk_get_by_index(dev, 0, &clk); data->xtal_rate = clk_get_rate(&clk); - val = dev_read_u32_default(dev, "xtal-load-pf", -1); - if (val >= 0) + if (!dev_read_u32(dev, "xtal-load-pf", &val)) cdce9xx_reg_write(dev, CDCE9XX_REG_XCSEL, val << 3); return 0; -- cgit v1.2.3 From 916f4337d1d3db4d16040abff39a5f4419589ead Mon Sep 17 00:00:00 2001 From: Andrew Goodbody Date: Fri, 25 Jul 2025 12:48:22 +0100 Subject: gpio: dwapb_gpio: Using wrong function to free memory In gpio_dwapb_bind plat is used to reference memory allocated by devm_kcalloc but it is attempted to be freed using kfree. Instead free this memory using the correct devm_kfree function. This issue was found by Smatch. Signed-off-by: Andrew Goodbody Acked-by: Quentin Schulz --- drivers/gpio/dwapb_gpio.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpio/dwapb_gpio.c b/drivers/gpio/dwapb_gpio.c index 04639a4cb68..7ab48780332 100644 --- a/drivers/gpio/dwapb_gpio.c +++ b/drivers/gpio/dwapb_gpio.c @@ -193,7 +193,7 @@ static int gpio_dwapb_bind(struct udevice *dev) ofnode_get_name(node)); plat->name = strdup(name); if (!plat->name) { - kfree(plat); + devm_kfree(dev, plat); return -ENOMEM; } } -- cgit v1.2.3 From d78130ac5a5be61832e7652ab86f9880012ab5c9 Mon Sep 17 00:00:00 2001 From: Shiji Yang Date: Sun, 27 Jul 2025 13:35:13 +0800 Subject: arm: dts: mediatek: remove useless SPI property must_tx This property is not documented. And the "mediatek,ipm-spi" SPI driver doesn't check it. Signed-off-by: Shiji Yang --- arch/arm/dts/mt7981-rfb.dts | 2 -- arch/arm/dts/mt7986a-bpi-r3-sd.dts | 1 - arch/arm/dts/mt7986a-rfb.dts | 1 - arch/arm/dts/mt7986a-sd-rfb.dts | 1 - arch/arm/dts/mt7986b-rfb.dts | 1 - arch/arm/dts/mt7986b-sd-rfb.dts | 1 - arch/arm/dts/mt7987a-emmc-rfb-u-boot.dtsi | 1 - arch/arm/dts/mt7987a-rfb-u-boot.dtsi | 2 -- arch/arm/dts/mt7987a-sd-rfb-u-boot.dtsi | 1 - arch/arm/dts/mt7988-rfb.dts | 2 -- arch/arm/dts/mt7988-sd-rfb.dts | 1 - 11 files changed, 14 deletions(-) diff --git a/arch/arm/dts/mt7981-rfb.dts b/arch/arm/dts/mt7981-rfb.dts index 17e6b5af7a2..ad149a34437 100644 --- a/arch/arm/dts/mt7981-rfb.dts +++ b/arch/arm/dts/mt7981-rfb.dts @@ -139,7 +139,6 @@ pinctrl-names = "default"; pinctrl-0 = <&spi_flash_pins>; status = "okay"; - must_tx; enhance_timing; dma_ext; ipm_design; @@ -162,7 +161,6 @@ pinctrl-names = "default"; pinctrl-0 = <&spi2_flash_pins>; status = "okay"; - must_tx; enhance_timing; dma_ext; ipm_design; diff --git a/arch/arm/dts/mt7986a-bpi-r3-sd.dts b/arch/arm/dts/mt7986a-bpi-r3-sd.dts index e01ae4c3dc7..ab6f84a3ece 100644 --- a/arch/arm/dts/mt7986a-bpi-r3-sd.dts +++ b/arch/arm/dts/mt7986a-bpi-r3-sd.dts @@ -173,7 +173,6 @@ pinctrl-names = "default"; pinctrl-0 = <&spi_flash_pins>; status = "okay"; - must_tx; enhance_timing; dma_ext; ipm_design; diff --git a/arch/arm/dts/mt7986a-rfb.dts b/arch/arm/dts/mt7986a-rfb.dts index d4bbb23204a..0d628a2e715 100644 --- a/arch/arm/dts/mt7986a-rfb.dts +++ b/arch/arm/dts/mt7986a-rfb.dts @@ -178,7 +178,6 @@ pinctrl-names = "default"; pinctrl-0 = <&spi_flash_pins>; status = "okay"; - must_tx; enhance_timing; dma_ext; ipm_design; diff --git a/arch/arm/dts/mt7986a-sd-rfb.dts b/arch/arm/dts/mt7986a-sd-rfb.dts index 11823e05bda..632f8b9446d 100644 --- a/arch/arm/dts/mt7986a-sd-rfb.dts +++ b/arch/arm/dts/mt7986a-sd-rfb.dts @@ -138,7 +138,6 @@ pinctrl-names = "default"; pinctrl-0 = <&spi_flash_pins>; status = "okay"; - must_tx; enhance_timing; dma_ext; ipm_design; diff --git a/arch/arm/dts/mt7986b-rfb.dts b/arch/arm/dts/mt7986b-rfb.dts index 0a731fe87fd..44524345468 100644 --- a/arch/arm/dts/mt7986b-rfb.dts +++ b/arch/arm/dts/mt7986b-rfb.dts @@ -165,7 +165,6 @@ pinctrl-names = "default"; pinctrl-0 = <&spi_flash_pins>; status = "okay"; - must_tx; enhance_timing; dma_ext; ipm_design; diff --git a/arch/arm/dts/mt7986b-sd-rfb.dts b/arch/arm/dts/mt7986b-sd-rfb.dts index e5fb4d73e70..d5c4273047a 100644 --- a/arch/arm/dts/mt7986b-sd-rfb.dts +++ b/arch/arm/dts/mt7986b-sd-rfb.dts @@ -134,7 +134,6 @@ pinctrl-names = "default"; pinctrl-0 = <&spi_flash_pins>; status = "okay"; - must_tx; enhance_timing; dma_ext; ipm_design; diff --git a/arch/arm/dts/mt7987a-emmc-rfb-u-boot.dtsi b/arch/arm/dts/mt7987a-emmc-rfb-u-boot.dtsi index 54cf72b3bf8..dc3f70aad64 100644 --- a/arch/arm/dts/mt7987a-emmc-rfb-u-boot.dtsi +++ b/arch/arm/dts/mt7987a-emmc-rfb-u-boot.dtsi @@ -42,7 +42,6 @@ #address-cells = <1>; #size-cells = <0>; status = "okay"; - must_tx; enhance_timing; dma_ext; ipm_design; diff --git a/arch/arm/dts/mt7987a-rfb-u-boot.dtsi b/arch/arm/dts/mt7987a-rfb-u-boot.dtsi index f1ed51e21c4..fa02ff59f6a 100644 --- a/arch/arm/dts/mt7987a-rfb-u-boot.dtsi +++ b/arch/arm/dts/mt7987a-rfb-u-boot.dtsi @@ -28,7 +28,6 @@ #address-cells = <1>; #size-cells = <0>; status = "okay"; - must_tx; enhance_timing; dma_ext; ipm_design; @@ -52,7 +51,6 @@ #address-cells = <1>; #size-cells = <0>; status = "okay"; - must_tx; enhance_timing; dma_ext; ipm_design; diff --git a/arch/arm/dts/mt7987a-sd-rfb-u-boot.dtsi b/arch/arm/dts/mt7987a-sd-rfb-u-boot.dtsi index b07e6da41e2..cf1114e7d99 100644 --- a/arch/arm/dts/mt7987a-sd-rfb-u-boot.dtsi +++ b/arch/arm/dts/mt7987a-sd-rfb-u-boot.dtsi @@ -40,7 +40,6 @@ #address-cells = <1>; #size-cells = <0>; status = "okay"; - must_tx; enhance_timing; dma_ext; ipm_design; diff --git a/arch/arm/dts/mt7988-rfb.dts b/arch/arm/dts/mt7988-rfb.dts index 1694ef8d9c3..6176ef923b2 100644 --- a/arch/arm/dts/mt7988-rfb.dts +++ b/arch/arm/dts/mt7988-rfb.dts @@ -181,7 +181,6 @@ #address-cells = <1>; #size-cells = <0>; status = "okay"; - must_tx; enhance_timing; dma_ext; ipm_design; @@ -204,7 +203,6 @@ #address-cells = <1>; #size-cells = <0>; status = "okay"; - must_tx; enhance_timing; dma_ext; ipm_design; diff --git a/arch/arm/dts/mt7988-sd-rfb.dts b/arch/arm/dts/mt7988-sd-rfb.dts index 63e923137c2..e29a9764187 100644 --- a/arch/arm/dts/mt7988-sd-rfb.dts +++ b/arch/arm/dts/mt7988-sd-rfb.dts @@ -108,7 +108,6 @@ #address-cells = <1>; #size-cells = <0>; status = "okay"; - must_tx; enhance_timing; dma_ext; ipm_design; -- cgit v1.2.3 From 814ddd7824db7d43dbad3bf70154e0e692a00d1e Mon Sep 17 00:00:00 2001 From: Chali Anis Date: Tue, 29 Jul 2025 22:19:08 -0400 Subject: pinctrl: gpio: sx150x: fix compilation warnings. Fixes: 5451504256d3 ("pinctrl: gpio: sx150x: add Semtech SX150x I2C GPIO expander and pinctrl driver") Signed-off-by: Chali Anis --- drivers/pinctrl/pinctrl-sx150x.c | 22 ++++++++++++---------- 1 file changed, 12 insertions(+), 10 deletions(-) diff --git a/drivers/pinctrl/pinctrl-sx150x.c b/drivers/pinctrl/pinctrl-sx150x.c index 324d7af8fcd..cddde8822ed 100644 --- a/drivers/pinctrl/pinctrl-sx150x.c +++ b/drivers/pinctrl/pinctrl-sx150x.c @@ -7,7 +7,6 @@ * */ -#include #include #include #include @@ -22,6 +21,8 @@ #include #include #include +#include +#include #define err(format, arg...) printf("ERR:" format "\n", ##arg) #define dbg(format, arg...) printf("DBG:" format "\n", ##arg) @@ -413,7 +414,7 @@ static int sx150x_reg_read(struct sx150x_pinctrl_priv *pctl, unsigned int reg, { int ret, n; const int width = sx150x_reg_width(pctl, reg); - unsigned int idx, val; + unsigned int val, idx; /* * There are four potential cases covered by this function: @@ -444,8 +445,9 @@ static int sx150x_reg_read(struct sx150x_pinctrl_priv *pctl, unsigned int reg, * reg 3 [ 3 3 2 2 1 1 0 0 ] */ - for (n = width, val = 0, idx = reg; n > 0; n -= 8, idx) { + for (n = width, val = 0; n > 0; n -= 8) { val <<= 8; + idx = reg; ret = dm_i2c_reg_read(pctl->i2c, idx); if (ret < 0) @@ -475,7 +477,6 @@ static int sx150x_reg_write(struct sx150x_pinctrl_priv *pctl, unsigned int reg, if (ret < 0) return ret; - reg; n -= 8; } while (n >= 0); @@ -724,7 +725,7 @@ static const struct udevice_id sx150x_pinctrl_of_match[] = { {}, }; -static const struct pinconf_param sx150x_conf_params[] = { +static const struct pinconf_param __maybe_unused sx150x_conf_params[] = { { "bias-disable", PIN_CONFIG_BIAS_DISABLE, 0 }, { "bias-pull-up", PIN_CONFIG_BIAS_PULL_UP, 1 }, { "bias-pull-down", PIN_CONFIG_BIAS_PULL_DOWN, 1 }, @@ -750,7 +751,7 @@ static const char *sx150x_pinctrl_get_pin_name(struct udevice *dev, return pin_name; } -static int sx150x_pinctrl_conf_set(struct udevice *dev, unsigned int pin, +static int __maybe_unused sx150x_pinctrl_conf_set(struct udevice *dev, unsigned int pin, unsigned int param, unsigned int arg) { int ret; @@ -834,13 +835,11 @@ static int sx150x_pinctrl_conf_set(struct udevice *dev, unsigned int pin, static int sx150x_pinctrl_bind(struct udevice *dev) { struct sx150x_pinctrl_priv *pctl = dev_get_plat(dev); - int ret, reg; + int ret; if (!dev_read_bool(dev, "gpio-controller")) return 0; - reg = (int)dev_read_addr_ptr(dev); - ret = device_bind(dev, &sx150x_gpio_driver, dev_read_name(dev), NULL, dev_ofnode(dev), &pctl->gpio); if (ret) @@ -861,7 +860,10 @@ static int sx150x_pinctrl_probe(struct udevice *dev) pctl->data = drv_data; - reg = (int)dev_read_addr_ptr(dev); + reg = dev_read_u32_default(dev, "reg", -ENODEV); + if (reg < 0) + return -ENODEV; + ret = dm_i2c_probe(dev->parent, reg, 0, &pctl->i2c); if (ret) { err("Cannot find I2C chip %02x (%d)", reg, ret); -- cgit v1.2.3 From 7807ed921314cd7af83fd88162d0b8c6fb20a9ca Mon Sep 17 00:00:00 2001 From: Neil Armstrong Date: Wed, 30 Jul 2025 10:03:39 +0200 Subject: pinctrl: sx150x: reformat and fixup Copyright header The Linux pinctrl-sx150 was originally written as a GPIO driver and fully rewritten by me as a Pinctrl driver and extended by other contributors. Fixup the Copyright header style and correctly report the Copyright headers from the Linux driver. Signed-off-by: Neil Armstrong --- drivers/pinctrl/pinctrl-sx150x.c | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) diff --git a/drivers/pinctrl/pinctrl-sx150x.c b/drivers/pinctrl/pinctrl-sx150x.c index cddde8822ed..0d64f4d5ad6 100644 --- a/drivers/pinctrl/pinctrl-sx150x.c +++ b/drivers/pinctrl/pinctrl-sx150x.c @@ -3,8 +3,12 @@ * Copyright (C) 2024, Exfo Inc - All Rights Reserved * * Author: Anis CHALI - * inspired and adapted from linux driver of sx150x written by Gregory Bean - * + * + * Inspired and adapted from the Linux pinctrl-sx150x driver: + * Copyright (c) 2016, BayLibre, SAS. All rights reserved. + * Author: Neil Armstrong + * Copyright (c) 2010, Code Aurora Forum. All rights reserved. + * Author: Gregory Bean */ #include -- cgit v1.2.3 From 28a87c8e9bc889a875b7b4b84d99ceb905d9d2d8 Mon Sep 17 00:00:00 2001 From: Quentin Schulz Date: Wed, 30 Jul 2025 14:03:18 +0200 Subject: rockchip: add /chosen/bootsource to U-Boot proper DT U-Boot typically can be loaded from different storage media, such as eMMC, SD card, SPI flash, but also from non-persistent media such as USB (via proprietary protocols loading directly into SRAM, or fastboot, DFU, etc..), JTAG, ... This information is usually reported by the BootROM via some proprietary mechanism (some specific address in registers/DRAM for example). For Rockchip, that information is stored in a register (BROM_BOOTSOURCE_ID_ADDR). While we already have the information about which medium was used to load U-Boot proper from SPL (via /chosen/u-boot,spl-boot-device), this new property represents the medium used to load U-Boot first phase (depending on configuration, can be VPL/TPL/SPL) which absolutely may differ from the one used to load U-Boot proper! It would be useful to know which medium was used to load the first phase of U-Boot, for example to check fallback mechanisms (proper loaded from a different medium than first phase) are actually working. For now, this only applies to Rockchip's U-Boot proper DT but could be applied to the kernel's as well and possibly for other architectures or vendors. Signed-off-by: Quentin Schulz --- arch/arm/mach-rockchip/spl-boot-order.c | 34 ++++++++++++++++++++------------- 1 file changed, 21 insertions(+), 13 deletions(-) diff --git a/arch/arm/mach-rockchip/spl-boot-order.c b/arch/arm/mach-rockchip/spl-boot-order.c index 3dce9b30898..1bfd120adc4 100644 --- a/arch/arm/mach-rockchip/spl-boot-order.c +++ b/arch/arm/mach-rockchip/spl-boot-order.c @@ -242,30 +242,38 @@ int spl_decode_boot_device(u32 boot_device, char *buf, size_t buflen) void spl_perform_fixups(struct spl_image_info *spl_image) { + const char *bootrom_ofpath = board_spl_was_booted_from(); void *blob = spl_image_fdt_addr(spl_image); char boot_ofpath[512]; int chosen, ret; - /* - * Inject the ofpath of the device the full U-Boot (or Linux in - * Falcon-mode) was booted from into the FDT, if a FDT has been - * loaded at the same time. - */ if (!blob) return; - ret = spl_decode_boot_device(spl_image->boot_device, boot_ofpath, sizeof(boot_ofpath)); - if (ret) { - pr_err("%s: could not map boot_device to ofpath: %d\n", __func__, ret); - return; - } - chosen = fdt_find_or_add_subnode(blob, 0, "chosen"); if (chosen < 0) { pr_err("%s: could not find/create '/chosen'\n", __func__); return; } - fdt_setprop_string(blob, chosen, - "u-boot,spl-boot-device", boot_ofpath); + + /* + * Inject the ofpath of the device the full U-Boot (or Linux in + * Falcon-mode) was booted from into the FDT. + */ + ret = spl_decode_boot_device(spl_image->boot_device, boot_ofpath, sizeof(boot_ofpath)); + if (ret) + pr_err("%s: could not map boot_device to ofpath: %d\n", __func__, ret); + else + fdt_setprop_string(blob, chosen, + "u-boot,spl-boot-device", boot_ofpath); + + /* + * Inject the ofpath of the device the BootROM loaded the very first + * stage from into the FDT. + */ + if (!bootrom_ofpath) + pr_err("%s: could not map BootROM boot device to ofpath\n", __func__); + else + fdt_setprop_string(blob, chosen, "bootsource", bootrom_ofpath); } #endif -- cgit v1.2.3 From 4266b8a2839f4e3eee2d7ce5f61af0c0ed0fe3b9 Mon Sep 17 00:00:00 2001 From: Andrew Goodbody Date: Mon, 4 Aug 2025 16:32:51 +0100 Subject: net: e1000: Free temporary buffer on exit In do_e1000_spi_checksum a temporary buffer is allocated but never freed. Add code to free on exit. Also refactor the code to make the exit code common. This issue found by Smatch. Signed-off-by: Andrew Goodbody --- drivers/net/e1000_spi.c | 25 +++++++++++++++---------- 1 file changed, 15 insertions(+), 10 deletions(-) diff --git a/drivers/net/e1000_spi.c b/drivers/net/e1000_spi.c index 1e830b99f1d..33d38b57824 100644 --- a/drivers/net/e1000_spi.c +++ b/drivers/net/e1000_spi.c @@ -472,6 +472,7 @@ static int do_e1000_spi_checksum(struct cmd_tbl *cmdtp, struct e1000_hw *hw, uint16_t i, length, checksum = 0, checksum_reg; uint16_t *buffer; bool upd; + int ret = 0; if (argc == 0) upd = 0; @@ -493,14 +494,15 @@ static int do_e1000_spi_checksum(struct cmd_tbl *cmdtp, struct e1000_hw *hw, /* Acquire the EEPROM */ if (e1000_acquire_eeprom(hw)) { E1000_ERR(hw, "EEPROM SPI cannot be acquired!\n"); - return 1; + ret = 1; + goto free_exit; } /* Read the EEPROM */ if (e1000_spi_eeprom_dump(hw, buffer, 0, length, true) < 0) { E1000_ERR(hw, "Interrupted!\n"); - e1000_release_eeprom(hw); - return 1; + ret = 1; + goto release_exit; } /* Compute the checksum and read the expected value */ @@ -513,8 +515,8 @@ static int do_e1000_spi_checksum(struct cmd_tbl *cmdtp, struct e1000_hw *hw, if (checksum_reg == checksum) { printf("%s: INFO: EEPROM checksum is correct! (0x%04hx)\n", hw->name, checksum); - e1000_release_eeprom(hw); - return 0; + ret = 0; + goto release_exit; } /* Hrm, verification failed, print an error */ @@ -524,8 +526,8 @@ static int do_e1000_spi_checksum(struct cmd_tbl *cmdtp, struct e1000_hw *hw, /* If they didn't ask us to update it, just return an error */ if (!upd) { - e1000_release_eeprom(hw); - return 1; + ret = 1; + goto release_exit; } /* Ok, correct it! */ @@ -534,12 +536,15 @@ static int do_e1000_spi_checksum(struct cmd_tbl *cmdtp, struct e1000_hw *hw, if (e1000_spi_eeprom_program(hw, &buffer[i], i * sizeof(uint16_t), sizeof(uint16_t), true)) { E1000_ERR(hw, "Interrupted!\n"); - e1000_release_eeprom(hw); - return 1; + ret = 1; + /* goto release_exit; */ } +release_exit: e1000_release_eeprom(hw); - return 0; +free_exit: + free(buffer); + return ret; } int do_e1000_spi(struct cmd_tbl *cmdtp, struct e1000_hw *hw, -- cgit v1.2.3 From d68db76b95b106227a40fcf41ebf4dccb2225a0e Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Mon, 4 Aug 2025 15:50:08 -0600 Subject: sandbox: Add an additional dummy sync macro There are some drivers which call a "dmb" for a type of sync. Add that as well to sandbox. Signed-off-by: Tom Rini --- arch/sandbox/include/asm/io.h | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/sandbox/include/asm/io.h b/arch/sandbox/include/asm/io.h index 72953828f96..cd3f5d6fd40 100644 --- a/arch/sandbox/include/asm/io.h +++ b/arch/sandbox/include/asm/io.h @@ -14,6 +14,7 @@ static inline void sync(void) #define mb() sync() #define dmb() sync() +#define wmb() sync() enum sandboxio_size_t { SB_SIZE_8, -- cgit v1.2.3 From e2837ecddc244198e3ebeac9ddb18fd439b0131f Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Mon, 4 Aug 2025 15:51:11 -0600 Subject: sm: Rework the Kconfig logic here The symbol "SM" is a library symbol and should not be prompted for. It should be selected by the drivers that use it. In this case we need to add a SANDBOX_SM symbol for the sandbox driver. The meson SM driver cannot build on other platforms, so add the appropriate dependency. Reviewed-by: Peter Robinson Signed-off-by: Tom Rini --- configs/sandbox_defconfig | 2 +- drivers/sm/Kconfig | 11 ++++++++++- drivers/sm/Makefile | 4 ++-- 3 files changed, 13 insertions(+), 4 deletions(-) diff --git a/configs/sandbox_defconfig b/configs/sandbox_defconfig index e9a70b26044..8c6693c693f 100644 --- a/configs/sandbox_defconfig +++ b/configs/sandbox_defconfig @@ -324,7 +324,7 @@ CONFIG_RTC_RV8803=y CONFIG_RTC_HT1380=y CONFIG_SCSI=y CONFIG_SANDBOX_SERIAL=y -CONFIG_SM=y +CONFIG_SANDBOX_SM=y CONFIG_SMEM=y CONFIG_SANDBOX_SMEM=y CONFIG_SOUND=y diff --git a/drivers/sm/Kconfig b/drivers/sm/Kconfig index 926af286330..8e500ed2ede 100644 --- a/drivers/sm/Kconfig +++ b/drivers/sm/Kconfig @@ -1,8 +1,17 @@ config SM - bool "Enable Secure Monitor driver support" + bool config MESON_SM bool "Amlogic Secure Monitor driver" + depends on ARCH_MESON select SM help Say y here to enable the Amlogic secure monitor driver. + +config SANDBOX_SM + bool "Sandbox Secure Monitor driver" + depends on SANDBOX + select SM + help + Say y here to enable the Sandbox driver for the secure monitor + uclass. diff --git a/drivers/sm/Makefile b/drivers/sm/Makefile index da81ee898ab..5ac947350bd 100644 --- a/drivers/sm/Makefile +++ b/drivers/sm/Makefile @@ -1,5 +1,5 @@ # SPDX-License-Identifier: GPL-2.0-only -obj-y += sm-uclass.o -obj-$(CONFIG_SANDBOX) += sandbox-sm.o +obj-$(CONFIG_SM) += sm-uclass.o +obj-$(CONFIG_SANDBOX_SM) += sandbox-sm.o obj-$(CONFIG_MESON_SM) += meson-sm.o -- cgit v1.2.3 From e7a95ee2b575d7f0f44da3b3aeb951508eac1511 Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Mon, 4 Aug 2025 15:52:53 -0600 Subject: pinctrl: Tighten some pinctrl driver dependencies A few pinctrl drivers cannot build without access to some platform specific header files. Express those requirements in Kconfig as well. Signed-off-by: Tom Rini --- drivers/pinctrl/Kconfig | 7 ++++--- drivers/pinctrl/tegra/Kconfig | 4 ++-- 2 files changed, 6 insertions(+), 5 deletions(-) diff --git a/drivers/pinctrl/Kconfig b/drivers/pinctrl/Kconfig index 5e2808abc8a..48119694031 100644 --- a/drivers/pinctrl/Kconfig +++ b/drivers/pinctrl/Kconfig @@ -197,7 +197,7 @@ config PINCTRL_AR933X config PINCTRL_AT91 bool "AT91 pinctrl driver" - depends on DM + depends on DM && ARCH_AT91 help This option is to enable the AT91 pinctrl driver for AT91 PIO controller. @@ -213,13 +213,14 @@ config PINCTRL_AT91 config PINCTRL_AT91PIO4 bool "AT91 PIO4 pinctrl driver" - depends on DM + depends on DM && ARCH_AT91 help This option is to enable the AT91 pinctrl driver for AT91 PIO4 controller which is available on SAMA5D2 SoC. config PINCTRL_INTEL bool "Standard Intel pin-control and pin-mux driver" + depends on X86 help Recent Intel chips such as Apollo Lake (APL) use a common pin control and GPIO scheme. The settings for this come from an SoC-specific @@ -248,7 +249,7 @@ config PINCTRL_QCA953X config PINCTRL_QE bool "QE based pinctrl driver, like on mpc83xx" - depends on DM + depends on DM && MPC83xx help This option is to enable the QE pinctrl driver for QE based io controller. diff --git a/drivers/pinctrl/tegra/Kconfig b/drivers/pinctrl/tegra/Kconfig index 669d8e258e4..d2630289d75 100644 --- a/drivers/pinctrl/tegra/Kconfig +++ b/drivers/pinctrl/tegra/Kconfig @@ -2,7 +2,7 @@ config PINCTRL_TEGRA bool "Nvidia Tegra pinctrl driver" - depends on DM + depends on DM && ARCH_TEGRA help Support pin multiplexing control on Nvidia Tegra SoCs. The driver is an overlay to existing driver and allows @@ -11,7 +11,7 @@ config PINCTRL_TEGRA config SPL_PINCTRL_TEGRA bool "Nvidia Tegra SPL pinctrl driver" - depends on SPL_PINCTRL + depends on SPL_PINCTRL && ARCH_TEGRA help Enables support of pre-DM version of pin multiplexing control driver used on SPL stage for board setup and -- cgit v1.2.3 From 678be99d563199551ed57fd771471eb1d2680e6e Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Mon, 4 Aug 2025 15:53:53 -0600 Subject: pwm: Tighten some pwm driver dependencies A few pwm drivers cannot build without access to some platform specific header files. Express those requirements in Kconfig as well. Signed-off-by: Tom Rini --- drivers/pwm/Kconfig | 9 +++++---- 1 file changed, 5 insertions(+), 4 deletions(-) diff --git a/drivers/pwm/Kconfig b/drivers/pwm/Kconfig index e4c676d75c2..06f42f699de 100644 --- a/drivers/pwm/Kconfig +++ b/drivers/pwm/Kconfig @@ -42,7 +42,7 @@ config PWM_CROS_EC config PWM_EXYNOS bool "Enable support for the Exynos PWM" - depends on DM_PWM + depends on DM_PWM && ARCH_EXYNOS help This PWM is found on Samsung Exynos 5250 and other Samsung SoCs. It supports a programmable period and duty cycle. A 32-bit counter is @@ -51,6 +51,7 @@ config PWM_EXYNOS config PWM_IMX bool "Enable support for i.MX27 and later PWM" + depends on MACH_IMX help This PWM is found i.MX27 and later i.MX SoCs. @@ -70,7 +71,7 @@ config PWM_MTK config PWM_ROCKCHIP bool "Enable support for the Rockchip PWM" - depends on DM_PWM + depends on DM_PWM && ARCH_ROCKCHIP help This PWM is found on RK3288 and other Rockchip SoCs. It supports a programmable period and duty cycle. A 32-bit counter is used. @@ -98,7 +99,7 @@ config PWM_SIFIVE config PWM_TEGRA bool "Enable support for the Tegra PWM" - depends on DM_PWM + depends on DM_PWM && ARCH_TEGRA help This PWM is found on Tegra 20 and other Nvidia SoCs. It supports four channels with a programmable period and duty cycle. Only a @@ -115,7 +116,7 @@ config PWM_STM32 config PWM_SUNXI bool "Enable support for the Allwinner Sunxi PWM" - depends on DM_PWM + depends on DM_PWM && ARCH_SUNXI help This PWM is found on H3, A64 and other Allwinner SoCs. It supports a programmable period and duty cycle. A 16-bit counter is used. -- cgit v1.2.3 From 00ad9ed4a775a6908a8654935f61df38e59178df Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Mon, 4 Aug 2025 15:53:54 -0600 Subject: pwm: pwm-aspeed: Add missing to pwm-aspeed.c This driver references the logarithmic macros while relying on an indirection inclusion of . Add the missing include directly. Signed-off-by: Tom Rini --- drivers/pwm/pwm-aspeed.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/pwm/pwm-aspeed.c b/drivers/pwm/pwm-aspeed.c index ebc9d9a8975..eefe018448f 100644 --- a/drivers/pwm/pwm-aspeed.c +++ b/drivers/pwm/pwm-aspeed.c @@ -46,6 +46,7 @@ #include #include #include +#include #include #include #include -- cgit v1.2.3 From 0ae7725e874a65d86ccdc964048940a490185972 Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Mon, 4 Aug 2025 15:54:25 -0600 Subject: reset: Tighten some reset driver dependencies A few reset drivers cannot build without access to some platform specific header files. Express those requirements in Kconfig as well. Signed-off-by: Tom Rini --- drivers/reset/Kconfig | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/drivers/reset/Kconfig b/drivers/reset/Kconfig index e92bb8a7c39..74c267dfc4e 100644 --- a/drivers/reset/Kconfig +++ b/drivers/reset/Kconfig @@ -74,8 +74,8 @@ config RESET_UNIPHIER config RESET_AST2500 bool "Reset controller driver for AST2500 SoCs" - depends on DM_RESET - default y if ASPEED_AST2500 + depends on DM_RESET && ASPEED_AST2500 + default y help Support for reset controller on AST2500 SoC. Say Y if you want to control reset signals of different peripherals @@ -83,8 +83,8 @@ config RESET_AST2500 config RESET_AST2600 bool "Reset controller driver for AST2600 SoCs" - depends on DM_RESET - default y if ASPEED_AST2600 + depends on DM_RESET && ASPEED_AST2600 + default y help Support for reset controller on AST2600 SoC. Say Y if you want to control reset signals of different peripherals @@ -223,7 +223,7 @@ config RESET_ZYNQMP config RESET_DRA7 bool "Support for TI's DRA7 Reset driver" - depends on DM_RESET + depends on DM_RESET && ARCH_OMAP2PLUS help Support for TI DRA7-RESET subsystem. Basic Assert/Deassert is supported. -- cgit v1.2.3 From 548ae9d1a537464254afac63f802179a24c645d6 Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Mon, 4 Aug 2025 15:54:24 -0600 Subject: remoteproc: Tighten some remoteproc driver dependencies The TI IPU remoteproc driver cannot build without access to some platform specific header files. Express that requirements in Kconfig as well. Signed-off-by: Tom Rini --- drivers/remoteproc/Kconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/remoteproc/Kconfig b/drivers/remoteproc/Kconfig index a3ecea05e20..e9f19a69433 100644 --- a/drivers/remoteproc/Kconfig +++ b/drivers/remoteproc/Kconfig @@ -125,6 +125,7 @@ config REMOTEPROC_TI_PRU config REMOTEPROC_TI_IPU bool "Support for TI's K3 based IPU remoteproc driver" select REMOTEPROC + depends on ARCH_K3 depends on DM depends on SPL_DRIVERS_MISC depends on SPL_FS_LOADER -- cgit v1.2.3 From 01bc65a0e9b2e0bac7af28bf102ee0df4f98b205 Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Mon, 4 Aug 2025 15:57:15 -0600 Subject: soc: Tighten some soc driver dependencies The Qualcomm Snapdragon "SoC" driver cannot build without access to some ARM64 specific functionality. Express that requirements in Kconfig as well. Reviewed-by: Casey Connolly Signed-off-by: Tom Rini --- drivers/soc/qcom/Kconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/soc/qcom/Kconfig b/drivers/soc/qcom/Kconfig index 4aa7833930c..8243805e46a 100644 --- a/drivers/soc/qcom/Kconfig +++ b/drivers/soc/qcom/Kconfig @@ -4,6 +4,7 @@ # menuconfig SOC_QCOM bool "Qualcomm SOC drivers support" + depends on ARM64 help Say Y here if you want to enable Qualcomm SOC drivers support. -- cgit v1.2.3 From 8b0eac68e5cb7b5bc55a4955672159c337f6afa2 Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Mon, 4 Aug 2025 15:57:16 -0600 Subject: sound: Tighten some sound driver dependencies A few sound drivers cannot build without access to some platform specific header files. Express those requirements in Kconfig as well. Reviewed-by: Peter Robinson Signed-off-by: Tom Rini --- drivers/sound/Kconfig | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/drivers/sound/Kconfig b/drivers/sound/Kconfig index 0948d8caab0..81de9b30f39 100644 --- a/drivers/sound/Kconfig +++ b/drivers/sound/Kconfig @@ -23,7 +23,7 @@ config I2S config I2S_ROCKCHIP bool "Enable I2S support for Rockchip SoCs" - depends on I2S + depends on I2S && ARCH_ROCKCHIP help Rockchip SoCs support an I2S interface for sending audio data to an audio codec. This option enables support for this, using one of the @@ -32,7 +32,7 @@ config I2S_ROCKCHIP config I2S_SAMSUNG bool "Enable I2C support for Samsung SoCs" - depends on I2S + depends on I2S && ARCH_EXYNOS help Samsung Exynos SoCs support an I2S interface for sending audio data to an audio codec. This option enables support for this, @@ -51,7 +51,7 @@ config SOUND_DA7219 config SOUND_I8254 bool "Intel i8254 timer / beeper" - depends on SOUND + depends on SOUND && X86 help This enables support for a beeper that uses the i8254 timer chip. This can emit beeps at a fixed frequency. It is possible to control @@ -82,7 +82,7 @@ config SOUND_IVYBRIDGE config I2S_TEGRA bool "Enable I2S support for Nvidia Tegra SoCs" - depends on I2S + depends on I2S && ARCH_TEGRA select TEGRA124_DMA help Nvidia Tegra SoCs support several I2S interfaces for sending audio -- cgit v1.2.3 From 38931172edd71c27101ac19361819d945ae337d8 Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Mon, 4 Aug 2025 15:57:19 -0600 Subject: sysreset: Tighten some sysreset driver dependencies The MPC83xx sysreset driver cannot build without access to some architecture specific header files. Express that requirements in Kconfig as well. Reviewed-by: Peter Robinson Signed-off-by: Tom Rini --- drivers/sysreset/Kconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/sysreset/Kconfig b/drivers/sysreset/Kconfig index 67edf004205..0181f6cd581 100644 --- a/drivers/sysreset/Kconfig +++ b/drivers/sysreset/Kconfig @@ -283,6 +283,7 @@ config SYSRESET_TPL_X86 config SYSRESET_MPC83XX bool "Enable support MPC83xx SoC family reboot driver" + depends on PPC help Reboot support for NXP MPC83xx SoCs. -- cgit v1.2.3 From b86ace06d37bb2ef97dbd79723089f3b46e065a2 Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Mon, 4 Aug 2025 15:57:10 -0600 Subject: rtc: Tighten some rtc driver dependencies The Marvell RTC rtc driver cannot build without access to some platform specific header files. Express that requirements in Kconfig as well. Signed-off-by: Tom Rini --- drivers/rtc/Kconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/rtc/Kconfig b/drivers/rtc/Kconfig index 79b879d68d1..ed903999f06 100644 --- a/drivers/rtc/Kconfig +++ b/drivers/rtc/Kconfig @@ -218,7 +218,7 @@ config RTC_PL031 config RTC_MV bool "Enable Marvell RTC driver" - depends on DM_RTC + depends on DM_RTC && ARCH_KIRKWOOD help Enable Marvell RTC driver. This driver supports the rtc that is present on some Marvell SoCs. -- cgit v1.2.3 From d7daa9274b1f7fad8f24c6020dc6225a1585de2f Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Mon, 4 Aug 2025 15:57:11 -0600 Subject: rtc: mc146818: Fix building on more architectures This driver makes calls to in8/out8(). On PowerPC these are separate and real calls but elsewhere they are able to simply be wrappers to inb/outb. Rework this logic to be able to build this driver on more platforms. Signed-off-by: Tom Rini --- drivers/rtc/mc146818.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/rtc/mc146818.c b/drivers/rtc/mc146818.c index c0d86c6d063..08bc528aeaf 100644 --- a/drivers/rtc/mc146818.c +++ b/drivers/rtc/mc146818.c @@ -11,9 +11,9 @@ #include #include #include - -#if defined(CONFIG_X86) || defined(CONFIG_TARGET_MALTA) #include + +#if !defined(CONFIG_PPC) #define in8(p) inb(p) #define out8(p, v) outb(v, p) #endif -- cgit v1.2.3 From 91122ea8f03b59b1fef7b9861734f6278ca4a123 Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Mon, 4 Aug 2025 15:57:12 -0600 Subject: rtc: pl031: Correct function type of pl031_write_reg When calling writel we do not have a return value to check or pass along. This function should therefore be void and not return what writel gives us. Signed-off-by: Tom Rini --- drivers/rtc/pl031.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/rtc/pl031.c b/drivers/rtc/pl031.c index 855ee913416..6f189bc503e 100644 --- a/drivers/rtc/pl031.c +++ b/drivers/rtc/pl031.c @@ -39,11 +39,11 @@ static inline u32 pl031_read_reg(struct udevice *dev, int reg) return readl(pdata->base + reg); } -static inline u32 pl031_write_reg(struct udevice *dev, int reg, u32 value) +static inline void pl031_write_reg(struct udevice *dev, int reg, u32 value) { struct pl031_plat *pdata = dev_get_plat(dev); - return writel(value, pdata->base + reg); + writel(value, pdata->base + reg); } /* -- cgit v1.2.3 From 37f0a8b8cb032f453487f54a575eb0701f5103e7 Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Mon, 4 Aug 2025 15:57:13 -0600 Subject: serial: Tighten some serial driver dependencies A few serial drivers cannot build without access to some platform specific header files. Express those requirements in Kconfig as well. Signed-off-by: Tom Rini --- drivers/serial/Kconfig | 14 +++++++++----- 1 file changed, 9 insertions(+), 5 deletions(-) diff --git a/drivers/serial/Kconfig b/drivers/serial/Kconfig index 1f2f2468eb0..d7d59e02dd0 100644 --- a/drivers/serial/Kconfig +++ b/drivers/serial/Kconfig @@ -665,6 +665,7 @@ config ARM_DCC config ATMEL_USART bool "Atmel USART support" + depends on ARCH_AT91 help Select this to enable USART support for Atmel SoCs. It can be configured in the device tree, and input clock frequency can @@ -703,8 +704,8 @@ config BCM6345_SERIAL config COREBOOT_SERIAL bool "Coreboot UART support" - depends on DM_SERIAL - default y if SYS_COREBOOT + depends on DM_SERIAL && SYS_COREBOOT + default y select SYS_NS16550 help Select this to enable a ns16550-style UART where the platform data @@ -724,7 +725,7 @@ config COREBOOT_SERIAL_FROM_DBG2 config CORTINA_UART bool "Cortina UART support" - depends on DM_SERIAL + depends on DM_SERIAL && TARGET_PRESIDIO_ASIC help Select this to enable UART support for Cortina-Access UART devices found on CAxxxx SoCs. @@ -738,6 +739,7 @@ config FSL_LINFLEXUART config FSL_LPUART bool "Freescale LPUART support" + depends on MACH_IMX || ARCH_LS1021A || ARCH_LS1028A help Select this to enable a Low Power UART for Freescale VF610 and QorIQ Layerscape devices. @@ -748,12 +750,14 @@ config LPUART config MVEBU_A3700_UART bool "UART support for Armada 3700" + depends on ARCH_MVEBU help Choose this option to add support for UART driver on the Marvell Armada 3700 SoC. The base address is configured via DT. config MCFUART bool "Freescale ColdFire UART support" + depends on M68K help Choose this option to add support for UART driver on the ColdFire SoC's family. The serial communication channel provides a full-duplex @@ -879,7 +883,7 @@ config PL01X_SERIAL config ROCKCHIP_SERIAL bool "Rockchip on-chip UART support" - depends on DM_SERIAL + depends on DM_SERIAL && ARCH_ROCKCHIP select SYS_NS16550 help Select this to enable a debug UART for Rockchip devices when using @@ -1110,7 +1114,7 @@ config MTK_SERIAL config MT7620_SERIAL bool "UART driver for MediaTek MT7620 and earlier SoCs" - depends on DM_SERIAL + depends on DM_SERIAL && SOC_MT7620 help Select this to enable UART support for MediaTek MT7620 and earlier SoCs. This driver uses driver model and requires a device tree -- cgit v1.2.3 From 546be69f05817ac3a16dddc847ee59c4342e7709 Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Mon, 4 Aug 2025 15:57:14 -0600 Subject: serial: linflexuart: Remove unused driver This driver is unused. Remove it. Signed-off-by: Tom Rini --- drivers/serial/Kconfig | 7 -- drivers/serial/Makefile | 1 - drivers/serial/serial_linflexuart.c | 216 ------------------------------------ 3 files changed, 224 deletions(-) delete mode 100644 drivers/serial/serial_linflexuart.c diff --git a/drivers/serial/Kconfig b/drivers/serial/Kconfig index d7d59e02dd0..bc05d2f1508 100644 --- a/drivers/serial/Kconfig +++ b/drivers/serial/Kconfig @@ -730,13 +730,6 @@ config CORTINA_UART Select this to enable UART support for Cortina-Access UART devices found on CAxxxx SoCs. -config FSL_LINFLEXUART - bool "Freescale Linflex UART support" - depends on DM_SERIAL - help - Select this to enable the Linflex serial module found on some - NXP SoCs like S32V234. - config FSL_LPUART bool "Freescale LPUART support" depends on MACH_IMX || ARCH_LS1021A || ARCH_LS1028A diff --git a/drivers/serial/Makefile b/drivers/serial/Makefile index c32e3fcd439..8eaae62b0fc 100644 --- a/drivers/serial/Makefile +++ b/drivers/serial/Makefile @@ -36,7 +36,6 @@ obj-$(CONFIG_SCIF_CONSOLE) += serial_sh.o obj-$(CONFIG_SEMIHOSTING_SERIAL) += serial_semihosting.o obj-$(CONFIG_ZYNQ_SERIAL) += serial_zynq.o obj-$(CONFIG_FSL_LPUART) += serial_lpuart.o -obj-$(CONFIG_FSL_LINFLEXUART) += serial_linflexuart.o obj-$(CONFIG_ARC_SERIAL) += serial_arc.o obj-$(CONFIG_UNIPHIER_SERIAL) += serial_uniphier.o obj-$(CONFIG_STM32_SERIAL) += serial_stm32.o diff --git a/drivers/serial/serial_linflexuart.c b/drivers/serial/serial_linflexuart.c deleted file mode 100644 index 24ecb236d51..00000000000 --- a/drivers/serial/serial_linflexuart.c +++ /dev/null @@ -1,216 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * (C) Copyright 2013-2016 Freescale Semiconductor, Inc. - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#define US1_TDRE (1 << 7) -#define US1_RDRF (1 << 5) -#define UC2_TE (1 << 3) -#define LINCR1_INIT (1 << 0) -#define LINCR1_MME (1 << 4) -#define LINCR1_BF (1 << 7) -#define LINSR_LINS_INITMODE (0x00001000) -#define LINSR_LINS_MASK (0x0000F000) -#define UARTCR_UART (1 << 0) -#define UARTCR_WL0 (1 << 1) -#define UARTCR_PCE (1 << 2) -#define UARTCR_PC0 (1 << 3) -#define UARTCR_TXEN (1 << 4) -#define UARTCR_RXEN (1 << 5) -#define UARTCR_PC1 (1 << 6) -#define UARTSR_DTF (1 << 1) -#define UARTSR_DRF (1 << 2) -#define UARTSR_RMB (1 << 9) - -DECLARE_GLOBAL_DATA_PTR; - -static void _linflex_serial_setbrg(struct linflex_fsl *base, int baudrate) -{ - u32 clk = mxc_get_clock(MXC_UART_CLK); - u32 ibr, fbr; - - if (!baudrate) - baudrate = CONFIG_BAUDRATE; - - ibr = (u32) (clk / (16 * gd->baudrate)); - fbr = (u32) (clk % (16 * gd->baudrate)) * 16; - - __raw_writel(ibr, &base->linibrr); - __raw_writel(fbr, &base->linfbrr); -} - -static int _linflex_serial_getc(struct linflex_fsl *base) -{ - char c; - - if (!(__raw_readb(&base->uartsr) & UARTSR_DRF)) - return -EAGAIN; - - if (!(__raw_readl(&base->uartsr) & UARTSR_RMB)) - return -EAGAIN; - - c = __raw_readl(&base->bdrm); - __raw_writeb((__raw_readb(&base->uartsr) | (UARTSR_DRF | UARTSR_RMB)), - &base->uartsr); - return c; -} - -static int _linflex_serial_putc(struct linflex_fsl *base, const char c) -{ - __raw_writeb(c, &base->bdrl); - - if (!(__raw_readb(&base->uartsr) & UARTSR_DTF)) - return -EAGAIN; - - __raw_writeb((__raw_readb(&base->uartsr) | UARTSR_DTF), &base->uartsr); - - return 0; -} - -/* - * Initialise the serial port with the given baudrate. The settings - * are always 8 data bits, no parity, 1 stop bit, no start bits. - */ -static int _linflex_serial_init(struct linflex_fsl *base) -{ - volatile u32 ctrl; - - /* set the Linflex in master mode amd activate by-pass filter */ - ctrl = LINCR1_BF | LINCR1_MME; - __raw_writel(ctrl, &base->lincr1); - - /* init mode */ - ctrl |= LINCR1_INIT; - __raw_writel(ctrl, &base->lincr1); - - /* waiting for init mode entry - TODO: add a timeout */ - while ((__raw_readl(&base->linsr) & LINSR_LINS_MASK) != - LINSR_LINS_INITMODE); - - /* set UART bit to allow writing other bits */ - __raw_writel(UARTCR_UART, &base->uartcr); - - /* provide data bits, parity, stop bit, etc */ - serial_setbrg(); - - /* 8 bit data, no parity, Tx and Rx enabled, UART mode */ - __raw_writel(UARTCR_PC1 | UARTCR_RXEN | UARTCR_TXEN | UARTCR_PC0 - | UARTCR_WL0 | UARTCR_UART, &base->uartcr); - - ctrl = __raw_readl(&base->lincr1); - ctrl &= ~LINCR1_INIT; - __raw_writel(ctrl, &base->lincr1); /* end init mode */ - - return 0; -} - -struct linflex_serial_plat { - struct linflex_fsl *base_addr; - u8 port_id; /* do we need this? */ -}; - -struct linflex_serial_priv { - struct linflex_fsl *lfuart; -}; - -int linflex_serial_setbrg(struct udevice *dev, int baudrate) -{ - struct linflex_serial_priv *priv = dev_get_priv(dev); - - _linflex_serial_setbrg(priv->lfuart, baudrate); - - return 0; -} - -static int linflex_serial_getc(struct udevice *dev) -{ - struct linflex_serial_priv *priv = dev_get_priv(dev); - - return _linflex_serial_getc(priv->lfuart); -} - -static int linflex_serial_putc(struct udevice *dev, const char ch) -{ - - struct linflex_serial_priv *priv = dev_get_priv(dev); - - return _linflex_serial_putc(priv->lfuart, ch); -} - -static int linflex_serial_pending(struct udevice *dev, bool input) -{ - struct linflex_serial_priv *priv = dev_get_priv(dev); - uint32_t uartsr = __raw_readl(&priv->lfuart->uartsr); - - if (input) - return ((uartsr & UARTSR_DRF) && (uartsr & UARTSR_RMB)) ? 1 : 0; - else - return uartsr & UARTSR_DTF ? 0 : 1; -} - -static void linflex_serial_init_internal(struct linflex_fsl *lfuart) -{ - _linflex_serial_init(lfuart); - _linflex_serial_setbrg(lfuart, CONFIG_BAUDRATE); - return; -} - -static int linflex_serial_probe(struct udevice *dev) -{ - struct linflex_serial_plat *plat = dev_get_plat(dev); - struct linflex_serial_priv *priv = dev_get_priv(dev); - - priv->lfuart = (struct linflex_fsl *)plat->base_addr; - linflex_serial_init_internal(priv->lfuart); - - return 0; -} - -static const struct dm_serial_ops linflex_serial_ops = { - .putc = linflex_serial_putc, - .pending = linflex_serial_pending, - .getc = linflex_serial_getc, - .setbrg = linflex_serial_setbrg, -}; - -U_BOOT_DRIVER(serial_linflex) = { - .name = "serial_linflex", - .id = UCLASS_SERIAL, - .probe = linflex_serial_probe, - .ops = &linflex_serial_ops, - .flags = DM_FLAG_PRE_RELOC, - .priv_auto = sizeof(struct linflex_serial_priv), -}; - -#ifdef CONFIG_DEBUG_UART_LINFLEXUART - -#include - -static inline void _debug_uart_init(void) -{ - struct linflex_fsl *base = (struct linflex_fsl *)CONFIG_VAL(DEBUG_UART_BASE); - - linflex_serial_init_internal(base); -} - -static inline void _debug_uart_putc(int ch) -{ - struct linflex_fsl *base = (struct linflex_fsl *)CONFIG_VAL(DEBUG_UART_BASE); - - /* XXX: Is this OK? Should this use the non-DM version? */ - _linflex_serial_putc(base, ch); -} - -DEBUG_UART_FUNCS - -#endif /* CONFIG_DEBUG_UART_LINFLEXUART */ -- cgit v1.2.3 From c39a8001ca862fbb676ddb788bc86f22c243bb88 Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Mon, 4 Aug 2025 15:54:23 -0600 Subject: ram: Tighten some ram driver dependencies A few ram drivers cannot build without access to some platform specific header files. Express those requirements in Kconfig as well. Signed-off-by: Tom Rini --- drivers/ram/Kconfig | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/ram/Kconfig b/drivers/ram/Kconfig index edb8e254d5b..d6964497309 100644 --- a/drivers/ram/Kconfig +++ b/drivers/ram/Kconfig @@ -39,7 +39,7 @@ config VPL_RAM config STM32_SDRAM bool "Enable STM32 SDRAM support" - depends on RAM + depends on RAM && ARCH_STM32 help STM32F7 family devices support flexible memory controller(FMC) to support external memories like sdram, psram & nand. @@ -47,7 +47,7 @@ config STM32_SDRAM config MPC83XX_SDRAM bool "Enable MPC83XX SDRAM support" - depends on RAM + depends on RAM && MPC83xx help Enable support for the internal DDR Memory Controller of the MPC83xx family of SoCs. Both static configurations, as well as configuring @@ -67,7 +67,7 @@ config K3_AM654_DDRSS config K3_DDRSS bool "Enable K3 DDRSS support" - depends on RAM + depends on RAM && ARCH_K3 choice depends on K3_DDRSS -- cgit v1.2.3 From 145a6f447e47f679218f8886c06622b19f4e22a6 Mon Sep 17 00:00:00 2001 From: Andrew Goodbody Date: Tue, 5 Aug 2025 17:10:26 +0100 Subject: net: phy: cortina: Ensure memory allocated is freed In cs4340_upload_firmware a buffer is allocated with malloc but this is never freed. The pointer to this buffer, addr, is not even kept unchanged. But in some cases addr is not a buffer allocated by malloc. Introduce the use of another pointer to keep track of the buffer and to know if it needs to be freed. This issue was found by Smatch. Signed-off-by: Andrew Goodbody --- drivers/net/phy/cortina.c | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/drivers/net/phy/cortina.c b/drivers/net/phy/cortina.c index be480ecef6c..dec024844b5 100644 --- a/drivers/net/phy/cortina.c +++ b/drivers/net/phy/cortina.c @@ -135,6 +135,7 @@ void cs4340_upload_firmware(struct phy_device *phydev) int i, line_cnt = 0, column_cnt = 0; struct cortina_reg_config fw_temp; char *addr = NULL; + char *to_be_freed = NULL; ulong cortina_fw_addr = (ulong)cs4340_get_fw_addr(); #ifdef CONFIG_TFABOOT @@ -147,6 +148,7 @@ void cs4340_upload_firmware(struct phy_device *phydev) size_t fw_length = CONFIG_CORTINA_FW_LENGTH; addr = malloc(CONFIG_CORTINA_FW_LENGTH); + to_be_freed = addr; ret = nand_read(get_nand_dev_by_index(0), (loff_t)cortina_fw_addr, &fw_length, (u_char *)addr); if (ret == -EUCLEAN) { @@ -158,6 +160,7 @@ void cs4340_upload_firmware(struct phy_device *phydev) struct spi_flash *ucode_flash; addr = malloc(CONFIG_CORTINA_FW_LENGTH); + to_be_freed = addr; ucode_flash = spi_flash_probe(CONFIG_SF_DEFAULT_BUS, CONFIG_SF_DEFAULT_CS, CONFIG_SF_DEFAULT_SPEED, CONFIG_SF_DEFAULT_MODE); if (!ucode_flash) { @@ -179,6 +182,7 @@ void cs4340_upload_firmware(struct phy_device *phydev) puts("Failed to find MMC device for Cortina ucode\n"); } else { addr = malloc(CONFIG_CORTINA_FW_LENGTH); + to_be_freed = addr; printf("MMC read: dev # %u, block # %u, count %u ...\n", dev, blk, cnt); mmc_init(mmc); @@ -199,6 +203,7 @@ void cs4340_upload_firmware(struct phy_device *phydev) size_t fw_length = CONFIG_CORTINA_FW_LENGTH; addr = malloc(CONFIG_CORTINA_FW_LENGTH); + to_be_freed = addr; ret = nand_read(get_nand_dev_by_index(0), (loff_t)cortina_fw_addr, &fw_length, (u_char *)addr); @@ -211,6 +216,7 @@ void cs4340_upload_firmware(struct phy_device *phydev) struct spi_flash *ucode_flash; addr = malloc(CONFIG_CORTINA_FW_LENGTH); + to_be_freed = addr; ucode_flash = spi_flash_probe(CONFIG_SF_DEFAULT_BUS, CONFIG_SF_DEFAULT_CS, CONFIG_SF_DEFAULT_SPEED, CONFIG_SF_DEFAULT_MODE); if (!ucode_flash) { @@ -232,6 +238,7 @@ void cs4340_upload_firmware(struct phy_device *phydev) puts("Failed to find MMC device for Cortina ucode\n"); } else { addr = malloc(CONFIG_CORTINA_FW_LENGTH); + to_be_freed = addr; printf("MMC read: dev # %u, block # %u, count %u ...\n", dev, blk, cnt); mmc_init(mmc); @@ -280,6 +287,8 @@ void cs4340_upload_firmware(struct phy_device *phydev) 0xffff; phy_write(phydev, 0x00, fw_temp.reg_addr, fw_temp.reg_value); } + if (to_be_freed) + free(to_be_freed); } #endif -- cgit v1.2.3 From 1edd1fd539f52cadcb57c0c79c504f46f9540045 Mon Sep 17 00:00:00 2001 From: Andrew Goodbody Date: Wed, 6 Aug 2025 11:43:47 +0100 Subject: net: ti: am65-cpsw-nuss: Initialise ret In am65_cpsw_phy_init it is not certain that ret will be assigned to before it reaches the 'return ret' statement. Initialise ret to ensure that ret is valid. This issue was found by Smatch. Signed-off-by: Andrew Goodbody --- drivers/net/ti/am65-cpsw-nuss.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/net/ti/am65-cpsw-nuss.c b/drivers/net/ti/am65-cpsw-nuss.c index 9b69f36d04d..723dde284fb 100644 --- a/drivers/net/ti/am65-cpsw-nuss.c +++ b/drivers/net/ti/am65-cpsw-nuss.c @@ -628,7 +628,7 @@ static int am65_cpsw_phy_init(struct udevice *dev) struct eth_pdata *pdata = dev_get_plat(dev); struct phy_device *phydev; u32 supported = PHY_GBIT_FEATURES; - int ret; + int ret = 0; phydev = dm_eth_phy_connect(dev); if (!phydev) { -- cgit v1.2.3 From 2a61c56dea1d7860d4a44afad3f54814ff0b805b Mon Sep 17 00:00:00 2001 From: Andrew Goodbody Date: Wed, 6 Aug 2025 11:56:58 +0100 Subject: net: ti: icssg: Remove impossible test port_id is an unsigned variable so cannot be negative. Remove the test checking for port_id being less than 0. This issue was found by Smatch. Signed-off-by: Andrew Goodbody --- drivers/net/ti/icssg_prueth.c | 2 -- 1 file changed, 2 deletions(-) diff --git a/drivers/net/ti/icssg_prueth.c b/drivers/net/ti/icssg_prueth.c index d8df3c9afb0..12a162b9d68 100644 --- a/drivers/net/ti/icssg_prueth.c +++ b/drivers/net/ti/icssg_prueth.c @@ -647,8 +647,6 @@ static int prueth_probe(struct udevice *dev) return -EINVAL; } - if (port_id < 0) - continue; if (disabled) continue; -- cgit v1.2.3 From cb76b208390d98658fc8e97c28dc0080a65c63bc Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Wed, 6 Aug 2025 08:55:02 -0600 Subject: timer: fttmr010_timer: Remove unused driver This driver is unused. Remove it. Signed-off-by: Tom Rini --- drivers/timer/Kconfig | 7 ---- drivers/timer/Makefile | 1 - drivers/timer/fttmr010_timer.c | 91 ------------------------------------------ include/faraday/fttmr010.h | 61 ---------------------------- 4 files changed, 160 deletions(-) delete mode 100644 drivers/timer/fttmr010_timer.c delete mode 100644 include/faraday/fttmr010.h diff --git a/drivers/timer/Kconfig b/drivers/timer/Kconfig index cb6fc0e7fda..d3231441b13 100644 --- a/drivers/timer/Kconfig +++ b/drivers/timer/Kconfig @@ -166,13 +166,6 @@ config DESIGNWARE_APB_TIMER Enables support for the Designware APB Timer driver. This timer is present on Altera SoCFPGA SoCs. -config FTTMR010_TIMER - bool "Faraday Technology timer support" - depends on TIMER - help - Select this to enable support for the timer found on - devices using Faraday Technology's IP. - config GXP_TIMER bool "HPE GXP Timer" depends on TIMER diff --git a/drivers/timer/Makefile b/drivers/timer/Makefile index 21db0d317fe..a72e411fb2f 100644 --- a/drivers/timer/Makefile +++ b/drivers/timer/Makefile @@ -15,7 +15,6 @@ obj-$(CONFIG_$(PHASE_)ATMEL_PIT_TIMER) += atmel_pit_timer.o obj-$(CONFIG_$(PHASE_)ATMEL_TCB_TIMER) += atmel_tcb_timer.o obj-$(CONFIG_CADENCE_TTC_TIMER) += cadence-ttc.o obj-$(CONFIG_DESIGNWARE_APB_TIMER) += dw-apb-timer.o -obj-$(CONFIG_FTTMR010_TIMER) += fttmr010_timer.o obj-$(CONFIG_GXP_TIMER) += gxp-timer.o obj-$(CONFIG_MPC83XX_TIMER) += mpc83xx_timer.o obj-$(CONFIG_NOMADIK_MTU_TIMER) += nomadik-mtu-timer.o diff --git a/drivers/timer/fttmr010_timer.c b/drivers/timer/fttmr010_timer.c deleted file mode 100644 index c41bbfc1d57..00000000000 --- a/drivers/timer/fttmr010_timer.c +++ /dev/null @@ -1,91 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * (C) Copyright 2009 Faraday Technology - * Po-Yu Chuang - * - * 23/08/2022 Port to DM - */ -#include -#include -#include -#include -#include -#include -#include - -#define TIMER_LOAD_VAL 0xffffffff - -struct fttmr010_timer_priv { - struct fttmr010 __iomem *regs; -}; - -static u64 fttmr010_timer_get_count(struct udevice *dev) -{ - struct fttmr010_timer_priv *priv = dev_get_priv(dev); - struct fttmr010 *tmr = priv->regs; - u32 now = TIMER_LOAD_VAL - readl(&tmr->timer3_counter); - - /* increment tbu if tbl has rolled over */ - if (now < gd->arch.tbl) - gd->arch.tbu++; - gd->arch.tbl = now; - - return ((u64)gd->arch.tbu << 32) | gd->arch.tbl; -} - -static int fttmr010_timer_probe(struct udevice *dev) -{ - struct fttmr010_timer_priv *priv = dev_get_priv(dev); - struct fttmr010 *tmr; - unsigned int cr; - - priv->regs = dev_read_addr_ptr(dev); - if (!priv->regs) - return -EINVAL; - tmr = priv->regs; - - debug("Faraday FTTMR010 timer revision 0x%08X\n", readl(&tmr->revision)); - - /* disable timers */ - writel(0, &tmr->cr); - - /* setup timer */ - writel(TIMER_LOAD_VAL, &tmr->timer3_load); - writel(TIMER_LOAD_VAL, &tmr->timer3_counter); - writel(0, &tmr->timer3_match1); - writel(0, &tmr->timer3_match2); - - /* we don't want timer to issue interrupts */ - writel(FTTMR010_TM3_MATCH1 | - FTTMR010_TM3_MATCH2 | - FTTMR010_TM3_OVERFLOW, - &tmr->interrupt_mask); - - cr = readl(&tmr->cr); - cr |= FTTMR010_TM3_CLOCK; /* use external clock */ - cr |= FTTMR010_TM3_ENABLE; - writel(cr, &tmr->cr); - - gd->arch.tbl = 0; - gd->arch.tbu = 0; - - return 0; -} - -static const struct timer_ops fttmr010_timer_ops = { - .get_count = fttmr010_timer_get_count, -}; - -static const struct udevice_id fttmr010_timer_ids[] = { - { .compatible = "faraday,fttmr010-timer" }, - {} -}; - -U_BOOT_DRIVER(fttmr010_timer) = { - .name = "fttmr010_timer", - .id = UCLASS_TIMER, - .of_match = fttmr010_timer_ids, - .priv_auto = sizeof(struct fttmr010_timer_priv), - .probe = fttmr010_timer_probe, - .ops = &fttmr010_timer_ops, -}; diff --git a/include/faraday/fttmr010.h b/include/faraday/fttmr010.h deleted file mode 100644 index 5b1bef38c77..00000000000 --- a/include/faraday/fttmr010.h +++ /dev/null @@ -1,61 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2009 Faraday Technology - * Po-Yu Chuang - */ - -/* - * Timer - */ -#ifndef __FTTMR010_H -#define __FTTMR010_H - -struct fttmr010 { - unsigned int timer1_counter; /* 0x00 */ - unsigned int timer1_load; /* 0x04 */ - unsigned int timer1_match1; /* 0x08 */ - unsigned int timer1_match2; /* 0x0c */ - unsigned int timer2_counter; /* 0x10 */ - unsigned int timer2_load; /* 0x14 */ - unsigned int timer2_match1; /* 0x18 */ - unsigned int timer2_match2; /* 0x1c */ - unsigned int timer3_counter; /* 0x20 */ - unsigned int timer3_load; /* 0x24 */ - unsigned int timer3_match1; /* 0x28 */ - unsigned int timer3_match2; /* 0x2c */ - unsigned int cr; /* 0x30 */ - unsigned int interrupt_state; /* 0x34 */ - unsigned int interrupt_mask; /* 0x38 */ - unsigned int revision; /* 0x3c */ -}; - -/* - * Timer Control Register - */ -#define FTTMR010_TM3_UPDOWN (1 << 11) -#define FTTMR010_TM2_UPDOWN (1 << 10) -#define FTTMR010_TM1_UPDOWN (1 << 9) -#define FTTMR010_TM3_OFENABLE (1 << 8) -#define FTTMR010_TM3_CLOCK (1 << 7) -#define FTTMR010_TM3_ENABLE (1 << 6) -#define FTTMR010_TM2_OFENABLE (1 << 5) -#define FTTMR010_TM2_CLOCK (1 << 4) -#define FTTMR010_TM2_ENABLE (1 << 3) -#define FTTMR010_TM1_OFENABLE (1 << 2) -#define FTTMR010_TM1_CLOCK (1 << 1) -#define FTTMR010_TM1_ENABLE (1 << 0) - -/* - * Timer Interrupt State & Mask Registers - */ -#define FTTMR010_TM3_OVERFLOW (1 << 8) -#define FTTMR010_TM3_MATCH2 (1 << 7) -#define FTTMR010_TM3_MATCH1 (1 << 6) -#define FTTMR010_TM2_OVERFLOW (1 << 5) -#define FTTMR010_TM2_MATCH2 (1 << 4) -#define FTTMR010_TM2_MATCH1 (1 << 3) -#define FTTMR010_TM1_OVERFLOW (1 << 2) -#define FTTMR010_TM1_MATCH2 (1 << 1) -#define FTTMR010_TM1_MATCH1 (1 << 0) - -#endif /* __FTTMR010_H */ -- cgit v1.2.3 From 3f486367bc8ba415fa0acbe72e57bfbfe3ffaca1 Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Wed, 6 Aug 2025 08:55:03 -0600 Subject: timer: Tighten some timer driver dependencies A few timer drivers cannot build without access to some platform specific header files. Express those requirements in Kconfig as well. Signed-off-by: Tom Rini --- drivers/timer/Kconfig | 29 +++++++++++------------------ 1 file changed, 11 insertions(+), 18 deletions(-) diff --git a/drivers/timer/Kconfig b/drivers/timer/Kconfig index d3231441b13..81c154b378a 100644 --- a/drivers/timer/Kconfig +++ b/drivers/timer/Kconfig @@ -96,8 +96,8 @@ config ARM_TWD_TIMER config AST_TIMER bool "Aspeed ast2400/ast2500 timer support" - depends on TIMER - default y if ARCH_ASPEED + depends on TIMER && ARCH_ASPEED + default y help Select this to enable timer for Aspeed ast2400/ast2500 devices. This is a simple sys timer driver, it is compatible with lib/time.c, @@ -108,17 +108,10 @@ config AST_TIMER config AST_IBEX_TIMER bool "Aspeed ast2700 Ibex timer" - depends on TIMER + depends on TIMER && RISCV help Select this to enable a timer support for the Ibex RV32-based MCUs in AST2700. -config ATCPIT100_TIMER - bool "ATCPIT100 timer support" - depends on TIMER - help - Select this to enable a ATCPIT100 timer which will be embedded - in AE3XX, AE250 boards. - config ATMEL_PIT_TIMER bool "Atmel periodic interval timer support" depends on TIMER @@ -161,7 +154,7 @@ config CADENCE_TTC_TIMER config DESIGNWARE_APB_TIMER bool "Designware APB Timer" - depends on TIMER + depends on TIMER && (ARCH_SOCFPGA || ARCH_ROCKCHIP) help Enables support for the Designware APB Timer driver. This timer is present on Altera SoCFPGA SoCs. @@ -175,7 +168,7 @@ config GXP_TIMER config MPC83XX_TIMER bool "MPC83xx timer support" - depends on TIMER + depends on TIMER && PPC help Select this to enable support for the timer found on devices based on the MPC83xx family of SoCs. @@ -217,14 +210,14 @@ config NPCM_TIMER config OMAP_TIMER bool "Omap timer support" - depends on TIMER + depends on TIMER && (ARCH_OMAP2PLUS || ARCH_K3) help Select this to enable an timer for Omap devices. config ORION_TIMER bool "Orion timer support" - depends on TIMER - default y if ARCH_KIRKWOOD || (ARCH_MVEBU && ARMADA_32BIT) + depends on TIMER && (ARCH_KIRKWOOD || (ARCH_MVEBU && ARMADA_32BIT)) + default y select TIMER_EARLY if ARCH_MVEBU help Select this to enable an timer for Orion and Armada devices @@ -239,7 +232,7 @@ config RISCV_TIMER config ROCKCHIP_TIMER bool "Rockchip timer support" - depends on TIMER + depends on TIMER && ARCH_ROCKCHIP help Select this to enable support for the timer found on Rockchip devices. @@ -268,14 +261,14 @@ config SP804_TIMER config STM32_TIMER bool "STM32 timer support" - depends on TIMER + depends on TIMER && ARCH_STM32 help Select this to enable support for the timer found on STM32 devices. config TEGRA_TIMER bool "Tegra timer support" - depends on TIMER + depends on TIMER && ARCH_TEGRA select TIMER_EARLY help Select this to enable support for the timer found on -- cgit v1.2.3 From 26d9bd1ccd6b344d1cc9ddb3d50981b106fed3b8 Mon Sep 17 00:00:00 2001 From: Andrew Goodbody Date: Wed, 6 Aug 2025 16:47:46 +0100 Subject: phy: keystone-usb: Do not negate return code In keystone_usb_init the return code from psc_enable_module should be returned as is rather than being negated. This issue was found by Smatch. Signed-off-by: Andrew Goodbody --- drivers/phy/keystone-usb-phy.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/phy/keystone-usb-phy.c b/drivers/phy/keystone-usb-phy.c index cfc15203d63..460efbe768d 100644 --- a/drivers/phy/keystone-usb-phy.c +++ b/drivers/phy/keystone-usb-phy.c @@ -41,7 +41,7 @@ static int keystone_usb_init(struct phy *phy) rc = psc_enable_module(keystone->psc_domain); if (rc) { debug("Cannot enable USB module"); - return -rc; + return rc; } mdelay(10); -- cgit v1.2.3 From fc96c1de5b719561db15259009a9ef22e671ee3d Mon Sep 17 00:00:00 2001 From: Andrew Goodbody Date: Wed, 6 Aug 2025 18:03:26 +0100 Subject: phy: ti: j721e-wiz: Set error code before goto In j721e_wiz_probe the test for too many lanes jumps to the error exit path without assigning an error code which could lead to calling code silently ignoring the failure. Set the error code. This issue was found by Smatch. Signed-off-by: Andrew Goodbody --- drivers/phy/ti/phy-j721e-wiz.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/phy/ti/phy-j721e-wiz.c b/drivers/phy/ti/phy-j721e-wiz.c index c69a342e2b4..6e2d4bc2b05 100644 --- a/drivers/phy/ti/phy-j721e-wiz.c +++ b/drivers/phy/ti/phy-j721e-wiz.c @@ -1201,6 +1201,7 @@ static int j721e_wiz_probe(struct udevice *dev) if (num_lanes > WIZ_MAX_LANES) { dev_err(dev, "Cannot support %d lanes\n", num_lanes); + rc = -EINVAL; goto err_addr_to_resource; } -- cgit v1.2.3 From 460db5b44dba0ec93bbfec3bdf537fba7a487714 Mon Sep 17 00:00:00 2001 From: Andrew Goodbody Date: Fri, 8 Aug 2025 11:47:43 +0100 Subject: ram: k3-ddrss: Use logical and not bitwise The test for the interrupt LPDDR4_INTR_BIST_DONE is using a bitwise and but the test is simple logic so use the more appropriate logical and. This issue was found by Smatch. Signed-off-by: Andrew Goodbody --- drivers/ram/k3-ddrss/k3-ddrss.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/ram/k3-ddrss/k3-ddrss.c b/drivers/ram/k3-ddrss/k3-ddrss.c index 6590d57ad84..b86e2448eb5 100644 --- a/drivers/ram/k3-ddrss/k3-ddrss.c +++ b/drivers/ram/k3-ddrss/k3-ddrss.c @@ -626,7 +626,7 @@ static void k3_lpddr4_bist_init_mem_region(struct k3_ddrss_desc *ddrss, while (i < BIST_MEM_INIT_TIMEOUT) { status = driverdt->checkctlinterrupt(pd, LPDDR4_INTR_BIST_DONE, &int_status); - if (!status & int_status) { + if (!status && int_status) { /* Clear LPDDR4_INTR_BIST_DONE */ driverdt->ackctlinterrupt(pd, LPDDR4_INTR_BIST_DONE); break; -- cgit v1.2.3 From 64204ab107b51c60e490292ed1eda40a9a64d7d9 Mon Sep 17 00:00:00 2001 From: Andrew Goodbody Date: Thu, 7 Aug 2025 11:04:02 +0100 Subject: pinctrl: single: Remove unreachable code In single_read there is a switch block with a default label. All cases in the switch block, including the default, return directly. So any code following the switch block is unreachable. Remove the unreachable code. This issue was found by Smatch. Signed-off-by: Andrew Goodbody --- drivers/pinctrl/pinctrl-single.c | 2 -- 1 file changed, 2 deletions(-) diff --git a/drivers/pinctrl/pinctrl-single.c b/drivers/pinctrl/pinctrl-single.c index a3802d22d4f..c96b293aadf 100644 --- a/drivers/pinctrl/pinctrl-single.c +++ b/drivers/pinctrl/pinctrl-single.c @@ -109,8 +109,6 @@ static unsigned int single_read(struct udevice *dev, void *reg) default: /* 32 bits */ return readl(reg); } - - return readb(reg); } static void single_write(struct udevice *dev, unsigned int val, void *reg) -- cgit v1.2.3 From 4a2f360bd280b2b5af1c5daffbc189590c83c995 Mon Sep 17 00:00:00 2001 From: Andrew Goodbody Date: Thu, 7 Aug 2025 11:04:03 +0100 Subject: pinctrl: stmfx: Remove duplicated code In stmfx_read_reg there is duplicated code to detect ret < 0 and return ret if so. Remove one version of it. This issue was found by Smatch. Signed-off-by: Andrew Goodbody --- drivers/pinctrl/pinctrl-stmfx.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/pinctrl/pinctrl-stmfx.c b/drivers/pinctrl/pinctrl-stmfx.c index 61f335c4eb1..0d5778faef9 100644 --- a/drivers/pinctrl/pinctrl-stmfx.c +++ b/drivers/pinctrl/pinctrl-stmfx.c @@ -87,7 +87,7 @@ static int stmfx_read_reg(struct udevice *dev, u8 reg_base, uint offset) if (ret < 0) return ret; - return ret < 0 ? ret : !!(ret & mask); + return !!(ret & mask); } static int stmfx_write_reg(struct udevice *dev, u8 reg_base, uint offset, -- cgit v1.2.3 From 6e212f32aaf312002a1ab1f3c18925e7c053f694 Mon Sep 17 00:00:00 2001 From: Stanley Chu Date: Thu, 7 Aug 2025 13:32:18 +0800 Subject: arm: dts: npcm8xx: add pinmux for VCD input Add pinmux to select the HSYNC signal as the VCD input. Signed-off-by: Stanley Chu Signed-off-by: Jim Liu --- arch/arm/dts/nuvoton-npcm8xx-u-boot.dtsi | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm/dts/nuvoton-npcm8xx-u-boot.dtsi b/arch/arm/dts/nuvoton-npcm8xx-u-boot.dtsi index bc047d4b443..6f933355d9e 100644 --- a/arch/arm/dts/nuvoton-npcm8xx-u-boot.dtsi +++ b/arch/arm/dts/nuvoton-npcm8xx-u-boot.dtsi @@ -1056,5 +1056,9 @@ groups = "jtag2"; function = "jtag2"; }; + vcdhs_pins: vcdhs-pins { + groups = "vcdhs"; + function = "vcdhs"; + }; }; }; -- cgit v1.2.3 From ad3a33e57742bab08a8ca1a9e34c262b6fbf0268 Mon Sep 17 00:00:00 2001 From: Stanley Chu Date: Thu, 7 Aug 2025 13:32:19 +0800 Subject: pinctrl: npcm8xx: add support for setting VCD input source Add pinmux for the VCD input to use the HSYNC signal. Signed-off-by: Stanley Chu Signed-off-by: Jim Liu --- drivers/pinctrl/nuvoton/pinctrl-npcm8xx.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/pinctrl/nuvoton/pinctrl-npcm8xx.c b/drivers/pinctrl/nuvoton/pinctrl-npcm8xx.c index 67e564f85c3..c960ca3393d 100644 --- a/drivers/pinctrl/nuvoton/pinctrl-npcm8xx.c +++ b/drivers/pinctrl/nuvoton/pinctrl-npcm8xx.c @@ -23,6 +23,7 @@ #define TIPRSTC 0x50 #define CORSTC 0x5c #define FLOCKR1 0x74 +#define INTCR 0x3c #define INTCR4 0xc0 #define I2CSEGSEL 0xe0 #define MFSEL1 0x260 @@ -280,6 +281,7 @@ struct npcm8xx_pinctrl_priv { FUNC(lkgpo2, FLOCKR1, 8, 9) \ FUNC(nprd_smi, FLOCKR1, 20, 190) \ FUNC(mmcwp, FLOCKR1, 24, 153) \ + FUNC(vcdhs, INTCR, 27) \ FUNC(rg2refck, INTCR4, 6) \ FUNC(r1en, INTCR4, 12) \ FUNC(r2en, INTCR4, 13) \ -- cgit v1.2.3 From 3c632fc090dab1838cedb525e09d049a903c37a6 Mon Sep 17 00:00:00 2001 From: Stanley Chu Date: Thu, 7 Aug 2025 13:32:20 +0800 Subject: i2c: npcm: fix consecutive dm_i2c_read/write error When doing a dm_i2c_read followed by a dm_i2c_write, the subsequent transaction may get npcm_i2c_check_sda error because the module is still busy in STOP condition in previous dm_i2c_read. Always check and wait for module to be out of busy before starting an i2c transaction. Signed-off-by: Stanley Chu Signed-off-by: Jim Liu --- drivers/i2c/npcm_i2c.c | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/drivers/i2c/npcm_i2c.c b/drivers/i2c/npcm_i2c.c index c64752e1467..bff0d04f1a5 100644 --- a/drivers/i2c/npcm_i2c.c +++ b/drivers/i2c/npcm_i2c.c @@ -34,6 +34,7 @@ #define SMBCTL3_SDA_LVL BIT(6) /* SMBCST */ +#define SMBCST_BUSY BIT(0) #define SMBCST_BB BIT(1) #define SMBCST_TGSCL BIT(5) @@ -479,11 +480,17 @@ static int npcm_i2c_xfer(struct udevice *dev, struct npcm_i2c_bus *bus = dev_get_priv(dev); struct npcm_i2c_regs *reg = bus->reg; int ret = 0, err = 0; + u8 val; if (nmsgs < 1 || nmsgs > 2) { printf("%s: commands not support\n", __func__); return -EREMOTEIO; } + + /* Wait for module out of busy */ + if (readb_poll_timeout(®->cst, val, !(val & SMBCST_BUSY), 1000)) + return -EBUSY; + /* clear ST register */ writeb(0xFF, ®->st); -- cgit v1.2.3 From 59a1c2875597c234eb2cde3ba2e48880523ab92e Mon Sep 17 00:00:00 2001 From: Jim Liu Date: Thu, 7 Aug 2025 13:32:21 +0800 Subject: arm: dts: nuvoton: Change timer node npcm_timer driver is changed to use SECCNT counter. Signed-off-by: Jim Liu --- arch/arm/dts/nuvoton-common-npcm8xx.dtsi | 13 +++++-------- 1 file changed, 5 insertions(+), 8 deletions(-) diff --git a/arch/arm/dts/nuvoton-common-npcm8xx.dtsi b/arch/arm/dts/nuvoton-common-npcm8xx.dtsi index db7517cc9ba..be06b2a0cae 100644 --- a/arch/arm/dts/nuvoton-common-npcm8xx.dtsi +++ b/arch/arm/dts/nuvoton-common-npcm8xx.dtsi @@ -62,6 +62,11 @@ reg = <0x0 0xf0801000 0x0 0x1000>; }; + timer0: timer@f0801068 { + compatible = "nuvoton,npcm845-timer"; + reg = <0x0 0xf0801068 0x0 0x8>; + }; + sdhci0: sdhci@f0842000 { compatible = "nuvoton,npcm845-sdhci"; reg = <0x0 0xf0842000 0x0 0x100>; @@ -157,14 +162,6 @@ status = "disabled"; }; - timer0: timer@8000 { - compatible = "nuvoton,npcm845-timer"; - interrupts = ; - reg = <0x8000 0x1C>; - clocks = <&clk NPCM8XX_CLK_REFCLK>; - clock-names = "refclk"; - }; - serial0: serial@0 { compatible = "nuvoton,npcm845-uart", "nuvoton,npcm750-uart"; reg = <0x0 0x1000>; -- cgit v1.2.3 From 121927e37be0725139d5b07d08361ac266685808 Mon Sep 17 00:00:00 2001 From: Jim Liu Date: Thu, 7 Aug 2025 13:32:22 +0800 Subject: misc: npcm_host_intf: Add Arbel eSPI workaround Enabling an eSPI channel(e.g. Peripheral Channel) during an eSPI transaction might cause the BMC eSPI module to transition to a wrong state and therefore respond with FATAL_ERROR on incoming transaction. Add workaround to avoid the module getting into the wrong state. Signed-off-by: Stanley Chu Signed-off-by: Jim Liu --- drivers/misc/npcm_host_intf.c | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/drivers/misc/npcm_host_intf.c b/drivers/misc/npcm_host_intf.c index 58bab888c3c..2c89bd7a167 100644 --- a/drivers/misc/npcm_host_intf.c +++ b/drivers/misc/npcm_host_intf.c @@ -22,6 +22,8 @@ /* ESPI Register offsets */ #define ESPICFG 0x4 #define ESPIHINDP 0x80 +#define ESPI_TEN 0xF0 +#define ESPI_ENG 0xF1 /* MFSEL bit fileds */ #define MFSEL1_LPCSEL BIT(26) @@ -40,6 +42,9 @@ #define AUTO_HS2 BIT(12) #define AUTO_HS3 BIT(16) +#define ESPI_TEN_ENABLE 0x55 +#define ESPI_TEN_DISABLE 0 + static int npcm_host_intf_bind(struct udevice *dev) { struct regmap *syscon; @@ -83,6 +88,13 @@ static int npcm_host_intf_bind(struct udevice *dev) val &= ~(CHSUPP_MASK | IOMODE_MASK | MAXFREQ_MASK); val |= IOMODE_SDQ | MAXFREQ_33MHZ | FIELD_PREP(CHSUPP_MASK, ch_supp); writel(val, base + ESPICFG); + + if (device_is_compatible(dev, "nuvoton,npcm845-host-intf")) { + /* Workaround: avoid eSPI module getting into wrong state */ + writeb(ESPI_TEN_ENABLE, base + ESPI_TEN); + writeb(BIT(6), base + ESPI_ENG); + writeb(ESPI_TEN_DISABLE, base + ESPI_TEN); + } } else if (!strcmp(type, "lpc")) { /* Select LPC pin function */ regmap_update_bits(syscon, MFSEL4, MFSEL4_ESPISEL, 0); -- cgit v1.2.3 From 987880581646d5836d2485e5f7a5af6ce8600da1 Mon Sep 17 00:00:00 2001 From: Jim Liu Date: Thu, 7 Aug 2025 13:32:23 +0800 Subject: misc: npcm_host_intf: Disable pending KCS/BPC interrupts If there is an unhandled KCS/BPC pending interrupt after reboot, the KCS/BPC Linux driver may trigger interrupts immediately upon registering the irq. However, since the driver is not yet initialized to handle them, this can lead to unexpected behavior. To prevent this, disable KCS/BPC interrupts in u-boot to avoid pending interrupts from being raised before the Linux driver is fully initialized. Signed-off-by: Stanley Chu Signed-off-by: Jim Liu --- arch/arm/dts/nuvoton-common-npcm8xx.dtsi | 2 +- drivers/misc/npcm_host_intf.c | 21 ++++++++++++++++++++- 2 files changed, 21 insertions(+), 2 deletions(-) diff --git a/arch/arm/dts/nuvoton-common-npcm8xx.dtsi b/arch/arm/dts/nuvoton-common-npcm8xx.dtsi index be06b2a0cae..6866005336f 100644 --- a/arch/arm/dts/nuvoton-common-npcm8xx.dtsi +++ b/arch/arm/dts/nuvoton-common-npcm8xx.dtsi @@ -141,7 +141,7 @@ host_intf: host_intf@9f000 { compatible = "nuvoton,npcm845-host-intf"; - reg = <0x9f000 0x1000>; + reg = <0x9f000 0x1000>, <0x7000 0x40>; type = "espi"; ioaddr = <0x4e>; channel-support = <0xf>; diff --git a/drivers/misc/npcm_host_intf.c b/drivers/misc/npcm_host_intf.c index 2c89bd7a167..e3b0663625b 100644 --- a/drivers/misc/npcm_host_intf.c +++ b/drivers/misc/npcm_host_intf.c @@ -45,10 +45,20 @@ #define ESPI_TEN_ENABLE 0x55 #define ESPI_TEN_DISABLE 0 +/* KCS/BPC interrupt control */ +#define BPCFEN 0x46 +#define FRIE BIT(3) +#define HRIE BIT(4) +#define KCS1CTL 0x18 +#define KCS2CTL 0x2a +#define KCS3CTL 0x3c +#define IBFIE BIT(0) +#define OBEIE BIT(1) + static int npcm_host_intf_bind(struct udevice *dev) { struct regmap *syscon; - void __iomem *base; + void __iomem *base, *kcs_base; u32 ch_supp, val; u32 ioaddr; const char *type; @@ -104,6 +114,15 @@ static int npcm_host_intf_bind(struct udevice *dev) /* Release host wait */ setbits_8(SMC_CTL_REG_ADDR, SMC_CTL_HOSTWAIT); + kcs_base = dev_read_addr_index_ptr(dev, 1); + if (kcs_base) { + /* Disable KCS/BPC interrupts */ + clrbits_8(kcs_base + BPCFEN, FRIE | HRIE); + clrbits_8(kcs_base + KCS1CTL, IBFIE | OBEIE); + clrbits_8(kcs_base + KCS2CTL, IBFIE | OBEIE); + clrbits_8(kcs_base + KCS3CTL, IBFIE | OBEIE); + } + return 0; } -- cgit v1.2.3 From 58fa3b5159cf4090ed926507d7778ebd1dc0686f Mon Sep 17 00:00:00 2001 From: Jim Liu Date: Thu, 7 Aug 2025 13:32:24 +0800 Subject: configs: npcm: remove CONFIG_SYS_SKIP_UART_INIT Set the uart clock frequency according to dts by default. If CONFIG_SYS_SKIP_UART_INIT is not enabled, no need to do board_set_console to change the console bootarg. Signed-off-by: Jim Liu --- board/nuvoton/arbel_evb/arbel_evb.c | 9 ++++++++- board/nuvoton/poleg_evb/poleg_evb.c | 2 ++ configs/arbel_evb_defconfig | 1 - configs/poleg_evb_defconfig | 1 - 4 files changed, 10 insertions(+), 3 deletions(-) diff --git a/board/nuvoton/arbel_evb/arbel_evb.c b/board/nuvoton/arbel_evb/arbel_evb.c index 16dbaa96e8c..05c4dd187fe 100644 --- a/board/nuvoton/arbel_evb/arbel_evb.c +++ b/board/nuvoton/arbel_evb/arbel_evb.c @@ -94,5 +94,12 @@ int dram_init_banksize(void) return 0; } -EVENT_SPY_SIMPLE(EVT_LAST_STAGE_INIT, board_set_console); +static int last_stage_init(void) +{ +#ifdef CONFIG_SYS_SKIP_UART_INIT + return board_set_console(); +#endif + return 0; +} +EVENT_SPY_SIMPLE(EVT_LAST_STAGE_INIT, last_stage_init); diff --git a/board/nuvoton/poleg_evb/poleg_evb.c b/board/nuvoton/poleg_evb/poleg_evb.c index 0a3c052a019..9dfe9744363 100644 --- a/board/nuvoton/poleg_evb/poleg_evb.c +++ b/board/nuvoton/poleg_evb/poleg_evb.c @@ -64,7 +64,9 @@ static int last_stage_init(void) } sprintf(value, "ttyS%d,115200n8", dev->seq_); env_set("console", value); +#ifdef CONFIG_SYS_SKIP_UART_INIT return board_set_console(); +#endif } return 0; diff --git a/configs/arbel_evb_defconfig b/configs/arbel_evb_defconfig index 8572ad204d8..11ad19f56db 100644 --- a/configs/arbel_evb_defconfig +++ b/configs/arbel_evb_defconfig @@ -17,7 +17,6 @@ CONFIG_SYS_LOAD_ADDR=0x06208000 CONFIG_WATCHDOG_TIMEOUT_MSECS=120000 # CONFIG_PSCI_RESET is not set CONFIG_ARCH_NPCM8XX=y -CONFIG_SYS_SKIP_UART_INIT=y CONFIG_TARGET_ARBEL_EVB=y CONFIG_ENV_ADDR=0x807C0000 # CONFIG_EFI_LOADER is not set diff --git a/configs/poleg_evb_defconfig b/configs/poleg_evb_defconfig index a87e918117c..0803fb1a857 100644 --- a/configs/poleg_evb_defconfig +++ b/configs/poleg_evb_defconfig @@ -16,7 +16,6 @@ CONFIG_DEFAULT_DEVICE_TREE="nuvoton-npcm750-evb" CONFIG_DM_RESET=y CONFIG_SYS_LOAD_ADDR=0x10000000 CONFIG_TARGET_POLEG=y -CONFIG_SYS_SKIP_UART_INIT=y CONFIG_ENV_ADDR=0x80100000 CONFIG_FIT=y CONFIG_USE_BOOTCOMMAND=y -- cgit v1.2.3 From b0465eb88f0406ba286df9ee056b9a62c8ab9c80 Mon Sep 17 00:00:00 2001 From: Ilias Apalodimas Date: Thu, 7 Aug 2025 11:08:14 +0300 Subject: test/py: Correctly restore the DT after capsule tests Some capsule tests are changing the sandbox DT to test various features, e.g authenticated capsule updates, versioning support etc. However, no one restores the original DT and the CI pops errors looking like /u-boot Bloblist at 100 not found (err=-2) Failed to find FDT file '/tmp/sandbox/persistent-data/scratch/EFI/CapsuleTestData/test_ver.dtb' initcall_run_f(): initcall fdtdec_setup() failed if sandbox is restarted. So let's restore the proper DT after done with the capsule testing. Signed-off-by: Ilias Apalodimas Reviewed-by: Tom Rini --- test/py/tests/test_efi_capsule/capsule_common.py | 2 ++ 1 file changed, 2 insertions(+) diff --git a/test/py/tests/test_efi_capsule/capsule_common.py b/test/py/tests/test_efi_capsule/capsule_common.py index 04dabc176c4..8c66411929e 100644 --- a/test/py/tests/test_efi_capsule/capsule_common.py +++ b/test/py/tests/test_efi_capsule/capsule_common.py @@ -137,6 +137,8 @@ def do_reboot_dtb_specified(u_boot_config, ubman, dtb_filename): dtb_filename -- DTB file name. """ mnt_point = u_boot_config.persistent_data_dir + '/scratch' + old_dtb = ubman.config.dtb ubman.config.dtb = mnt_point + CAPSULE_DATA_DIR \ + f'/{dtb_filename}' ubman.restart_uboot() + ubman.config.dtb = old_dtb -- cgit v1.2.3 From 5096f81bda1cfac2a8a325e850442bf463be2f00 Mon Sep 17 00:00:00 2001 From: Ilias Apalodimas Date: Thu, 7 Aug 2025 11:08:15 +0300 Subject: test/py: Read from the correct offset when initializing capsules The current code writes values to a flash offset defined by a function argument. However, when reading it back we always read from a static offset. Adjust the reads to use the correct offset. Signed-off-by: Ilias Apalodimas Reviewed-by: Tom Rini --- test/py/tests/test_efi_capsule/capsule_common.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/test/py/tests/test_efi_capsule/capsule_common.py b/test/py/tests/test_efi_capsule/capsule_common.py index 8c66411929e..8aaddfc19d6 100644 --- a/test/py/tests/test_efi_capsule/capsule_common.py +++ b/test/py/tests/test_efi_capsule/capsule_common.py @@ -42,7 +42,7 @@ def init_content(ubman, target, filename, expected): 'sf probe 0:0', f'fatload host 0:1 4000000 {CAPSULE_DATA_DIR}/{filename}', f'sf write 4000000 {target} 10', - 'sf read 5000000 100000 10', + f'sf read 5000000 {target} 10', 'md.b 5000000 10']) assert expected in ''.join(output) -- cgit v1.2.3 From fa2a2e20d0b4d7af92ee118d66f3245055cc9ba3 Mon Sep 17 00:00:00 2001 From: Ilias Apalodimas Date: Thu, 7 Aug 2025 11:08:16 +0300 Subject: test/py: Fix race conditions on EFI capsule tests efi_capsule_data() is called in each of the EFI tests to create and setup the files we need. However, it also recreates the spi.bin file that holds the SPI flash contents we rely on for the test validation. This leads to weird errors since reading from the flash returns 0, instead of the expected value if the file has been recreated. Always restart our sandbox instance if the files are recreated. Signed-off-by: Ilias Apalodimas --- test/py/tests/test_efi_capsule/conftest.py | 1 + 1 file changed, 1 insertion(+) diff --git a/test/py/tests/test_efi_capsule/conftest.py b/test/py/tests/test_efi_capsule/conftest.py index 961d2e0b3c1..45c06c42fd2 100644 --- a/test/py/tests/test_efi_capsule/conftest.py +++ b/test/py/tests/test_efi_capsule/conftest.py @@ -103,6 +103,7 @@ def efi_capsule_data(request, ubman): pytest.skip('Setup failed: %s' % exception.cmd) return else: + ubman.restart_uboot() yield image_path finally: call('rm -rf %s' % mnt_point, shell=True) -- cgit v1.2.3 From fc2686d2a87391dd1b165e44ffd525b61c93e521 Mon Sep 17 00:00:00 2001 From: Ilias Apalodimas Date: Thu, 7 Aug 2025 11:08:17 +0300 Subject: test/py: Fix capsule update tests Capsule updates tests have been skipped since commit 659f97eb1fc3 ("scripts/Makefile.lib: EFI: Use capsule CRT instead of ESL file") Remove that check since it's not needed anymore and re-enable the tests. Fixes: 659f97eb1fc3 ("scripts/Makefile.lib: EFI: Use capsule CRT instead of ESL file") Signed-off-by: Ilias Apalodimas --- test/py/tests/test_efi_capsule/conftest.py | 2 -- 1 file changed, 2 deletions(-) diff --git a/test/py/tests/test_efi_capsule/conftest.py b/test/py/tests/test_efi_capsule/conftest.py index 45c06c42fd2..ad0cda59ebf 100644 --- a/test/py/tests/test_efi_capsule/conftest.py +++ b/test/py/tests/test_efi_capsule/conftest.py @@ -44,8 +44,6 @@ def efi_capsule_data(request, ubman): % (key_dir, data_dir), shell=True) check_call('cp %s/capsule_pub_key_good.crt %s/SIGNER.crt' % (key_dir, data_dir), shell=True) - check_call('cp %s/capsule_pub_esl_good.esl %s/SIGNER.esl' - % (key_dir, data_dir), shell=True) check_call('cp %s/capsule_priv_key_bad.key %s/SIGNER2.key' % (key_dir, data_dir), shell=True) -- cgit v1.2.3 From e416d165723c56658b4a688e790cdcd968c6cfc9 Mon Sep 17 00:00:00 2001 From: Andrew Goodbody Date: Thu, 7 Aug 2025 10:16:55 +0100 Subject: pinctrl: nexell: Cannot test unsigned to be negative In s5pxx18_pinctrl_set_state testing count to be negative will always fail as count is unsigned despite receiving the return value of a function that returns an int. Change count and idx to be of type int to allow the test to work as expected and remove the need for any implicit casts. Also change pin to be u32 which is what all called functions expect. This issue was found by Smatch. Signed-off-by: Andrew Goodbody --- drivers/pinctrl/nexell/pinctrl-s5pxx18.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/pinctrl/nexell/pinctrl-s5pxx18.c b/drivers/pinctrl/nexell/pinctrl-s5pxx18.c index e7d0994f29e..a6ae5764fbc 100644 --- a/drivers/pinctrl/nexell/pinctrl-s5pxx18.c +++ b/drivers/pinctrl/nexell/pinctrl-s5pxx18.c @@ -130,7 +130,8 @@ static int is_pin_alive(const char *name) static int s5pxx18_pinctrl_set_state(struct udevice *dev, struct udevice *config) { - unsigned int count, idx, pin; + u32 pin; + int count, idx; unsigned int pinfunc, pinpud, pindrv; unsigned long reg; const char *name; -- cgit v1.2.3 From 6139d5f2521593edc64421976d7830e44121745b Mon Sep 17 00:00:00 2001 From: Ilias Apalodimas Date: Tue, 12 Aug 2025 09:03:25 +0300 Subject: tools: fit_info: Make usage() static The function is only used locally so declare it as static. Signed-off-by: Ilias Apalodimas --- tools/fit_info.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/tools/fit_info.c b/tools/fit_info.c index b2642ec5b76..c9e4236d09f 100644 --- a/tools/fit_info.c +++ b/tools/fit_info.c @@ -26,7 +26,7 @@ #include #include -void usage(char *cmdname) +static void usage(char *cmdname) { fprintf(stderr, "Usage: %s -f fit file -n node -p property\n" " -f ==> set fit file which is used'\n" -- cgit v1.2.3 From 544bf0aa599f9afd8ac5224b005edd4b5bb374ed Mon Sep 17 00:00:00 2001 From: Ilias Apalodimas Date: Tue, 12 Aug 2025 09:10:20 +0300 Subject: tools: aisimage: Make aisimage_check_params() static We are trying to enable -Wmissing-prototypes and this functiion is only used locally. Mark it as static. Signed-off-by: Ilias Apalodimas --- tools/aisimage.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/tools/aisimage.c b/tools/aisimage.c index c5b33b559b0..7a44b2d6ab6 100644 --- a/tools/aisimage.c +++ b/tools/aisimage.c @@ -387,7 +387,7 @@ static void aisimage_set_header(void *ptr, struct stat *sbuf, int ifd, { } -int aisimage_check_params(struct image_tool_params *params) +static int aisimage_check_params(struct image_tool_params *params) { if (!params) return CFG_INVALID; -- cgit v1.2.3 From da938a4254b4cf9d4e7b894a0a30536b0d9266c5 Mon Sep 17 00:00:00 2001 From: Andrew Goodbody Date: Tue, 12 Aug 2025 11:36:53 +0100 Subject: sound: rt5677: Cannot test unsigned for being negative In rt5677_bic_or the call to rt5677_i2c_read returns an int so old should also be an int to receive that value and then be able to test it for being negative which would indicate an error. This issue was found by Smatch. Signed-off-by: Andrew Goodbody --- drivers/sound/rt5677.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/sound/rt5677.c b/drivers/sound/rt5677.c index b5c997c6dd5..a9d1e94951a 100644 --- a/drivers/sound/rt5677.c +++ b/drivers/sound/rt5677.c @@ -94,8 +94,8 @@ static int rt5677_i2c_write(struct rt5677_priv *priv, uint reg, uint data) static int rt5677_bic_or(struct rt5677_priv *priv, uint reg, uint bic, uint set) { - uint old, new_value; - int ret; + uint new_value; + int old, ret; old = rt5677_i2c_read(priv, reg); if (old < 0) -- cgit v1.2.3 From 58998fed9e63e8310a96229565d2996ad29d191e Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Tue, 12 Aug 2025 11:59:07 -0600 Subject: sandbox: Improve dummy local_irq_save implementation Normally, local_save_flags is used as part of the local_irq_* macros, so remove that as it's unused. Make local_irq_save do something to the passed variable so that it won't trigger unused variable warnings later. Signed-off-by: Tom Rini --- arch/sandbox/include/asm/system.h | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/arch/sandbox/include/asm/system.h b/arch/sandbox/include/asm/system.h index 7933b6292e2..73f34683b27 100644 --- a/arch/sandbox/include/asm/system.h +++ b/arch/sandbox/include/asm/system.h @@ -7,10 +7,9 @@ #define __ASM_SANDBOX_SYSTEM_H /* Define this as nops for sandbox architecture */ -#define local_irq_save(x) +#define local_irq_save(x) do { (x) = 0; } while (0) #define local_irq_enable() #define local_irq_disable() -#define local_save_flags(x) #define local_irq_restore(x) #endif -- cgit v1.2.3 From 66ff673a8e9f56d2c08a32d12867094c77ea5fd3 Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Tue, 12 Aug 2025 11:59:08 -0600 Subject: sandbox: Add generic asm/atomic.h In order to compile code that uses on sandbox, we must provide this header. RISC-V shows us today how to do so with the generic header implementation, so copy that. Signed-off-by: Tom Rini --- arch/sandbox/include/asm/atomic.h | 15 +++++++++++++++ 1 file changed, 15 insertions(+) create mode 100644 arch/sandbox/include/asm/atomic.h diff --git a/arch/sandbox/include/asm/atomic.h b/arch/sandbox/include/asm/atomic.h new file mode 100644 index 00000000000..2fe49f52f34 --- /dev/null +++ b/arch/sandbox/include/asm/atomic.h @@ -0,0 +1,15 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Based on arch/riscv/include/asm/atomic.h which is: + * Copyright 2023 SiFive, Inc. + */ + +#ifndef __SANDBOX_ATOMIC_H +#define __SANDBOX_ATOMIC_H + +/* use the generic asm/atomic.h until we define a better one */ + +#include +#include + +#endif -- cgit v1.2.3 From f780ad4be9fe84fbdd874455c7518e0576e4d845 Mon Sep 17 00:00:00 2001 From: Andrew Goodbody Date: Fri, 8 Aug 2025 13:00:22 +0100 Subject: remoteproc: ti_k3_arm64: Cannot set or compare u8 to 16bits In the struct ti_sci_proc the fields proc_id and host_id are declared as u8 so cannot be set to nor compared with a macro defined with a value using 16 bits. Change the macro to only use 8 bits to make the code work as expected. This issue was found by Smatch. Signed-off-by: Andrew Goodbody --- drivers/remoteproc/ti_k3_arm64_rproc.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/remoteproc/ti_k3_arm64_rproc.c b/drivers/remoteproc/ti_k3_arm64_rproc.c index d3eb957b2e4..403c6bed2e8 100644 --- a/drivers/remoteproc/ti_k3_arm64_rproc.c +++ b/drivers/remoteproc/ti_k3_arm64_rproc.c @@ -19,7 +19,7 @@ #include #include "ti_sci_proc.h" -#define INVALID_ID 0xffff +#define INVALID_ID 0xff #define GTC_CNTCR_REG 0x0 #define GTC_CNTFID0_REG 0x20 -- cgit v1.2.3 From c9cd480b5c5496b809d954424ce3554673c278d3 Mon Sep 17 00:00:00 2001 From: Andrew Goodbody Date: Fri, 8 Aug 2025 13:00:23 +0100 Subject: remoteproc: k3-r5: Ensure ret is initialised In k3_r5f_split_reset and k3_r5f_unprepare ret may not have been assigned to before the code reaches the return ret at the function exit. This issue was found by Smatch. Signed-off-by: Andrew Goodbody --- drivers/remoteproc/ti_k3_r5f_rproc.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/remoteproc/ti_k3_r5f_rproc.c b/drivers/remoteproc/ti_k3_r5f_rproc.c index f4bab6868ee..3a25ef6bf87 100644 --- a/drivers/remoteproc/ti_k3_r5f_rproc.c +++ b/drivers/remoteproc/ti_k3_r5f_rproc.c @@ -441,7 +441,7 @@ proc_release: static int k3_r5f_split_reset(struct k3_r5f_core *core) { - int ret; + int ret = 0; dev_dbg(core->dev, "%s\n", __func__); @@ -476,7 +476,7 @@ static int k3_r5f_unprepare(struct udevice *dev) { struct k3_r5f_core *core = dev_get_priv(dev); struct k3_r5f_cluster *cluster = core->cluster; - int ret; + int ret = 0; dev_dbg(dev, "%s\n", __func__); -- cgit v1.2.3 From b90927bd0d81096239ff4a48a71c3d9e87ef7209 Mon Sep 17 00:00:00 2001 From: Andrew Goodbody Date: Tue, 12 Aug 2025 11:13:49 +0100 Subject: soc: ti: k3-navss-ringacc: NULL check before dereference Move the first dereference of ring to after the NULL check has occurred. This will prevent any possible dereference of NULL. This issue was found by Smatch. Signed-off-by: Andrew Goodbody --- drivers/soc/ti/k3-navss-ringacc.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/drivers/soc/ti/k3-navss-ringacc.c b/drivers/soc/ti/k3-navss-ringacc.c index 14114a65830..ac29158d489 100644 --- a/drivers/soc/ti/k3-navss-ringacc.c +++ b/drivers/soc/ti/k3-navss-ringacc.c @@ -632,12 +632,14 @@ err_free_ops: int k3_nav_ringacc_ring_cfg(struct k3_nav_ring *ring, struct k3_nav_ring_cfg *cfg) { - struct k3_nav_ringacc *ringacc = ring->parent; + struct k3_nav_ringacc *ringacc; int ret = 0; if (!ring || !cfg) return -EINVAL; + ringacc = ring->parent; + if (ringacc->dual_ring) return k3_dmaring_ring_cfg(ring, cfg); -- cgit v1.2.3 From 13ca68b104ea75d54e86816ba6d86ef5e70a2668 Mon Sep 17 00:00:00 2001 From: Andrew Goodbody Date: Tue, 12 Aug 2025 11:13:50 +0100 Subject: soc: ti: k3-navss-ringacc: Do not use uninitialised variable In k3_nav_ringacc_probe_dt there can be no error code returned from dev_read_u32_default so ret is not assigned to and should not be used. Remove the use of ret from the dev_err call as it is unitialised. This issue was found by Smatch. Signed-off-by: Andrew Goodbody --- drivers/soc/ti/k3-navss-ringacc.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/soc/ti/k3-navss-ringacc.c b/drivers/soc/ti/k3-navss-ringacc.c index ac29158d489..d37c454143b 100644 --- a/drivers/soc/ti/k3-navss-ringacc.c +++ b/drivers/soc/ti/k3-navss-ringacc.c @@ -932,7 +932,7 @@ static int k3_nav_ringacc_probe_dt(struct k3_nav_ringacc *ringacc) ringacc->num_rings = dev_read_u32_default(dev, "ti,num-rings", 0); if (!ringacc->num_rings) { - dev_err(dev, "ti,num-rings read failure %d\n", ret); + dev_err(dev, "ti,num-rings read failure\n"); return -EINVAL; } -- cgit v1.2.3 From 520d9c2521f4082209ce5121be1b3c1eae98994c Mon Sep 17 00:00:00 2001 From: Neha Malcom Francis Date: Tue, 12 Aug 2025 18:13:16 +0530 Subject: ram: k3-ddrss: Use DDR address instead of system address for ecc_regions Let ecc_regions[x].start reflect the start of the ECC region in terms of DDR addressing rather than system addressing. This will make it easier to extend the usage of the same ecc_regions structure for multi-DDR systems as well. Reviewed-by: Udit Kumar Signed-off-by: Neha Malcom Francis --- drivers/ram/k3-ddrss/k3-ddrss.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/ram/k3-ddrss/k3-ddrss.c b/drivers/ram/k3-ddrss/k3-ddrss.c index b86e2448eb5..f19a17ecec7 100644 --- a/drivers/ram/k3-ddrss/k3-ddrss.c +++ b/drivers/ram/k3-ddrss/k3-ddrss.c @@ -752,7 +752,7 @@ static void k3_ddrss_lpddr4_ecc_init(struct k3_ddrss_desc *ddrss) u32 val; /* Only Program region 0 which covers full ddr space */ - k3_ddrss_set_ecc_range_r0(base, ecc_region_start - ddrss->ddr_bank_base[0], ecc_range); + k3_ddrss_set_ecc_range_r0(base, ecc_region_start, ecc_range); /* Enable ECC, RMW, WR_ALLOC */ writel(DDRSS_ECC_CTRL_REG_ECC_EN | DDRSS_ECC_CTRL_REG_RMW_EN | @@ -817,7 +817,7 @@ static int k3_ddrss_probe(struct udevice *dev) k3_ddrss_lpddr4_ecc_calc_reserved_mem(ddrss); /* Always configure one region that covers full DDR space */ - ddrss->ecc_regions[0].start = ddrss->ddr_bank_base[0]; + ddrss->ecc_regions[0].start = 0; ddrss->ecc_regions[0].range = ddrss->ddr_ram_size - ddrss->ecc_reserved_space; k3_ddrss_lpddr4_ecc_init(ddrss); } -- cgit v1.2.3 From e511c651f6dd0ec89a4b7dec25140540740cf13e Mon Sep 17 00:00:00 2001 From: Neha Malcom Francis Date: Tue, 12 Aug 2025 18:13:17 +0530 Subject: ram: k3-ddrss: s/K3_DDRSS_MAX_ECC_REGIONS/K3_DDRSS_MAX_ECC_REG To prevent checkpatch warning once we start using this macro more frequently, shorten the length of it. While at it, also move the structure k3_ddrss_ecc_region above k3_msmc so that future patches can have it as a member of k3_msmc. Reviewed-by: Udit Kumar Signed-off-by: Neha Malcom Francis --- drivers/ram/k3-ddrss/k3-ddrss.c | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) diff --git a/drivers/ram/k3-ddrss/k3-ddrss.c b/drivers/ram/k3-ddrss/k3-ddrss.c index f19a17ecec7..2fdbd4609a8 100644 --- a/drivers/ram/k3-ddrss/k3-ddrss.c +++ b/drivers/ram/k3-ddrss/k3-ddrss.c @@ -121,6 +121,13 @@ enum emif_active { EMIF_ALL }; +#define K3_DDRSS_MAX_ECC_REG 3 + +struct k3_ddrss_ecc_region { + u64 start; + u64 range; +}; + struct k3_msmc { enum intrlv_gran gran; enum intrlv_size size; @@ -129,13 +136,6 @@ struct k3_msmc { enum emif_active active; }; -#define K3_DDRSS_MAX_ECC_REGIONS 3 - -struct k3_ddrss_ecc_region { - u64 start; - u64 range; -}; - struct k3_ddrss_desc { struct udevice *dev; void __iomem *ddrss_ss_cfg; @@ -155,7 +155,7 @@ struct k3_ddrss_desc { lpddr4_obj *driverdt; lpddr4_config config; lpddr4_privatedata pd; - struct k3_ddrss_ecc_region ecc_regions[K3_DDRSS_MAX_ECC_REGIONS]; + struct k3_ddrss_ecc_region ecc_regions[K3_DDRSS_MAX_ECC_REG]; u64 ecc_reserved_space; u64 ddr_bank_base[CONFIG_NR_DRAM_BANKS]; u64 ddr_bank_size[CONFIG_NR_DRAM_BANKS]; -- cgit v1.2.3 From 1c70e33b0aca6d5d84145636400e496feb19c8b9 Mon Sep 17 00:00:00 2001 From: Neha Malcom Francis Date: Tue, 12 Aug 2025 18:13:18 +0530 Subject: ram: k3-ddrss: Add comment about ecc_reserved_space The reserved space needed for storing the parity remains the same no matter the size of the region that is being protected. Add this as a comment for better code understanding. Reviewed-by: Udit Kumar Signed-off-by: Neha Malcom Francis --- drivers/ram/k3-ddrss/k3-ddrss.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/drivers/ram/k3-ddrss/k3-ddrss.c b/drivers/ram/k3-ddrss/k3-ddrss.c index 2fdbd4609a8..d35adc840f4 100644 --- a/drivers/ram/k3-ddrss/k3-ddrss.c +++ b/drivers/ram/k3-ddrss/k3-ddrss.c @@ -737,6 +737,12 @@ static void k3_ddrss_lpddr4_ecc_calc_reserved_mem(struct k3_ddrss_desc *ddrss) { fdtdec_setup_mem_size_base_lowest(); + /* + * For every 512-byte data block, 64 bytes are used to store inline ECC + * information into a reserved region. It remains 1/9th of the total DDR + * size irrespective of the size of the region under protection. + */ + ddrss->ecc_reserved_space = ddrss->ddr_ram_size; do_div(ddrss->ecc_reserved_space, 9); -- cgit v1.2.3 From f43f710122541f870ba164e8121445003032c71c Mon Sep 17 00:00:00 2001 From: Neha Malcom Francis Date: Tue, 12 Aug 2025 18:13:19 +0530 Subject: ram: k3-ddrss: Add support for a partial inline ECC region Instead of defaulting to choosing the entire DDR region when enabling inline ECC, allow picking of a range within the DDR space using DT to enable. It expects such a node within the memory node, in the absence of which we resort to enabling inline ECC for the entire DDR region: inline_ecc: protected@9e780000 { device_type = "ecc"; reg = <0x9e780000 0x0080000>; bootph-all; }; Signed-off-by: Neha Malcom Francis --- drivers/ram/k3-ddrss/k3-ddrss.c | 60 ++++++++++++++++++++++++++++++++++++++--- 1 file changed, 57 insertions(+), 3 deletions(-) diff --git a/drivers/ram/k3-ddrss/k3-ddrss.c b/drivers/ram/k3-ddrss/k3-ddrss.c index d35adc840f4..61d4f3d7aa4 100644 --- a/drivers/ram/k3-ddrss/k3-ddrss.c +++ b/drivers/ram/k3-ddrss/k3-ddrss.c @@ -155,6 +155,7 @@ struct k3_ddrss_desc { lpddr4_obj *driverdt; lpddr4_config config; lpddr4_privatedata pd; + struct k3_ddrss_ecc_region ecc_range; struct k3_ddrss_ecc_region ecc_regions[K3_DDRSS_MAX_ECC_REG]; u64 ecc_reserved_space; u64 ddr_bank_base[CONFIG_NR_DRAM_BANKS]; @@ -733,6 +734,30 @@ static void k3_ddrss_ddr_reg_init(struct k3_ddrss_desc *ddrss) writel(DDRSS_ECC_CTRL_REG_DEFAULT, ddrss->ddrss_ss_cfg + DDRSS_ECC_CTRL_REG); } +static void k3_ddrss_ddr_inline_ecc_base_size_calc(struct k3_ddrss_ecc_region *range) +{ + fdt_addr_t base; + fdt_size_t size; + ofnode node1; + + node1 = ofnode_null(); + + do { + node1 = ofnode_by_prop_value(node1, "device_type", "ecc", 4); + } while (!ofnode_is_enabled(node1)); + + base = ofnode_get_addr_size(node1, "reg", &size); + + if (base == FDT_ADDR_T_NONE) { + debug("%s: Failed to get ECC node reg and size\n", __func__); + range->start = 0; + range->range = 0; + } else { + range->start = base; + range->range = size; + } +} + static void k3_ddrss_lpddr4_ecc_calc_reserved_mem(struct k3_ddrss_desc *ddrss) { fdtdec_setup_mem_size_base_lowest(); @@ -783,8 +808,11 @@ static void k3_ddrss_lpddr4_ecc_init(struct k3_ddrss_desc *ddrss) static int k3_ddrss_probe(struct udevice *dev) { + u64 end; int ret; struct k3_ddrss_desc *ddrss = dev_get_priv(dev); + __maybe_unused u64 ddr_ram_size, ecc_res; + __maybe_unused struct k3_ddrss_ecc_region *range = &ddrss->ecc_range; debug("%s(dev=%p)\n", __func__, dev); @@ -822,9 +850,35 @@ static int k3_ddrss_probe(struct udevice *dev) k3_ddrss_lpddr4_ecc_calc_reserved_mem(ddrss); - /* Always configure one region that covers full DDR space */ - ddrss->ecc_regions[0].start = 0; - ddrss->ecc_regions[0].range = ddrss->ddr_ram_size - ddrss->ecc_reserved_space; + k3_ddrss_ddr_inline_ecc_base_size_calc(range); + + end = ddrss->ecc_range.start + ddrss->ecc_range.range; + ddr_ram_size = ddrss->ddr_ram_size; + ecc_res = ddrss->ecc_reserved_space; + + if (!range->range) { + /* Configure entire DDR space by default */ + debug("%s: Defaulting to protecting entire DDR space using inline ECC\n", + __func__); + ddrss->ecc_range.start = ddrss->ddr_bank_base[0]; + ddrss->ecc_range.range = ddr_ram_size - ecc_res; + } else { + ddrss->ecc_range.start = range->start; + ddrss->ecc_range.range = range->range; + } + + /* + * As we are converting the system address to the DDR controller + * address, account for case when the region is in the second + * bank + */ + if (end > (ddr_ram_size - ecc_res)) + ddrss->ecc_regions[0].range = ddr_ram_size - ecc_res; + else + ddrss->ecc_regions[0].range = ddrss->ecc_range.range; + + ddrss->ecc_regions[0].start = ddrss->ecc_range.start - ddrss->ddr_bank_base[0]; + k3_ddrss_lpddr4_ecc_init(ddrss); } -- cgit v1.2.3 From 3a0793fe9be3f0e6026d31dec8545a6b0e102ccd Mon Sep 17 00:00:00 2001 From: Neha Malcom Francis Date: Tue, 12 Aug 2025 18:13:20 +0530 Subject: ram: k3-ddrss: Add CONFIG_K3_MULTI_DDR As we increase the functionalities that the K3 DDRSS sub-system support, it is becoming more evident that the same logic cannot apply to both single as well as multiple DDR controller devices. Add CONFIG_K3_MULTI_DDR to be used to differentiate between the two. Reviewed-by: Udit Kumar Signed-off-by: Neha Malcom Francis --- drivers/ram/Kconfig | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/drivers/ram/Kconfig b/drivers/ram/Kconfig index d6964497309..cfbfa1252d0 100644 --- a/drivers/ram/Kconfig +++ b/drivers/ram/Kconfig @@ -128,6 +128,16 @@ config K3_INLINE_ECC need to be primed with a predefined value prior to enabling ECC check. +config K3_MULTI_DDR + bool "Enable support for multiple K3 DDRSS controllers" + depends on K3_DDRSS + help + Enabling this option adds support for configuring multiple DDR memory + controllers for K3 devices. The external memory interleave layer + present in the MSMC (Multicore Shared Memory Controller) is + responsible for interleaving between the controllers. + default y if SOC_K3_J721S2 || SOC_K3_J784S4 + source "drivers/ram/aspeed/Kconfig" source "drivers/ram/cadence/Kconfig" source "drivers/ram/octeon/Kconfig" -- cgit v1.2.3 From 2310aac8ae0180ad78da1d44657f846610296e4d Mon Sep 17 00:00:00 2001 From: Neha Malcom Francis Date: Tue, 12 Aug 2025 18:13:21 +0530 Subject: ram: k3-ddrss: Add support for number of controllers under MSMC In K3 multi-DDR systems, the MSMC is responsible for the interleave mechanism across all the DDR controllers. Add support for MSMC to obtain the number of controllers it's responsible for using the DT. Reviewed-by: Udit Kumar Signed-off-by: Neha Malcom Francis --- drivers/ram/k3-ddrss/k3-ddrss.c | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/drivers/ram/k3-ddrss/k3-ddrss.c b/drivers/ram/k3-ddrss/k3-ddrss.c index 61d4f3d7aa4..075e664ff1a 100644 --- a/drivers/ram/k3-ddrss/k3-ddrss.c +++ b/drivers/ram/k3-ddrss/k3-ddrss.c @@ -134,6 +134,7 @@ struct k3_msmc { enum ecc_enable enable; enum emif_config config; enum emif_active active; + u32 num_ddr_controllers; }; struct k3_ddrss_desc { @@ -1013,6 +1014,13 @@ static int k3_msmc_probe(struct udevice *dev) return -EINVAL; } + ret = device_get_child_count(dev); + if (ret <= 0) { + dev_err(dev, "no child ddr nodes present"); + return -EINVAL; + } + msmc->num_ddr_controllers = ret; + return 0; } -- cgit v1.2.3 From c32ac5b3b934942fdcd97ee631ca2362032e0e53 Mon Sep 17 00:00:00 2001 From: Neha Malcom Francis Date: Tue, 12 Aug 2025 18:13:22 +0530 Subject: ram: k3-ddrss: Add support for MSMC calculation of DDR inline ECC regions Add support for calculation of the protected regions for each DDR in multi-DDR systems. Since MSMC is the parent node of the individual DDRs as well as responsible for their interleaving, it only makes sense for MSMC to contain the logic for dividing the regions. Signed-off-by: Neha Malcom Francis --- drivers/ram/k3-ddrss/k3-ddrss.c | 106 ++++++++++++++++++++++++++++++++++++++++ 1 file changed, 106 insertions(+) diff --git a/drivers/ram/k3-ddrss/k3-ddrss.c b/drivers/ram/k3-ddrss/k3-ddrss.c index 075e664ff1a..c7938000314 100644 --- a/drivers/ram/k3-ddrss/k3-ddrss.c +++ b/drivers/ram/k3-ddrss/k3-ddrss.c @@ -59,6 +59,7 @@ #define SINGLE_DDR_SUBSYSTEM 0x1 #define MULTI_DDR_SUBSYSTEM 0x2 +#define MAX_MULTI_DDR 4 #define MULTI_DDR_CFG0 0x00114100 #define MULTI_DDR_CFG1 0x00114104 @@ -82,6 +83,24 @@ enum intrlv_gran { GRAN_16GB }; +u64 gran_bytes[] = { + 0x80, + 0x200, + 0x800, + 0x1000, + 0x4000, + 0x8000, + 0x80000, + 0x40000000, + 0x60000000, + 0x80000000, + 0xC0000000, + 0x100000000, + 0x180000000, + 0x200000000, + 0x400000000 +}; + enum intrlv_size { SIZE_0, SIZE_128MB, @@ -135,6 +154,7 @@ struct k3_msmc { enum emif_config config; enum emif_active active; u32 num_ddr_controllers; + struct k3_ddrss_ecc_region R0[MAX_MULTI_DDR]; }; struct k3_ddrss_desc { @@ -942,6 +962,80 @@ U_BOOT_DRIVER(k3_ddrss) = { .priv_auto = sizeof(struct k3_ddrss_desc), }; +__maybe_unused static int k3_msmc_calculate_r0_regions(struct k3_msmc *msmc) +{ + u32 n1; + u32 size, ret = 0; + u32 gran = gran_bytes[msmc->gran]; + u32 num_ddr = msmc->num_ddr_controllers; + struct k3_ddrss_ecc_region *range = NULL; + struct k3_ddrss_ecc_region R[num_ddr]; + + range = kzalloc(sizeof(range), GFP_KERNEL); + if (!range) { + ret = -ENOMEM; + return ret; + } + + k3_ddrss_ddr_inline_ecc_base_size_calc(range); + + if (!range->range) { + ret = -EINVAL; + goto range_err; + } + + memset(R, 0, num_ddr); + + /* Find the first controller in the range */ + n1 = ((range->start / gran) % num_ddr); + size = range->range; + + if (size < gran) { + R[n1].start = range->start - 0x80000000; + R[n1].range = range->start + range->range - 0x80000000; + } else { + u32 chunk_start_addr = range->start; + u32 chunk_size = range->range; + + while (chunk_size > 0) { + u32 edge; + u32 end = range->start + range->range; + + if ((chunk_start_addr % gran) == 0) + edge = chunk_start_addr + gran; + else + edge = ((chunk_start_addr + (gran - 1)) & (-gran)); + + if (edge > end) + break; + + if (R[n1].start == 0) + R[n1].start = chunk_start_addr; + + R[n1].range = edge - R[n1].start; + chunk_size = end - edge; + chunk_start_addr = edge; + + if (n1 == (num_ddr - 1)) + n1 = 0; + else + n1++; + } + + for (int i = 0; i < num_ddr; i++) + R[i].start = (R[i].start - 0x80000000 - (gran * i)) / num_ddr; + } + + for (int i = 0; i < num_ddr; i++) { + msmc->R0[i].start = R[i].start; + msmc->R0[i].range = R[i].range; + } + +range_err: + free(range); + return ret; +} + static int k3_msmc_set_config(struct k3_msmc *msmc) { u32 ddr_cfg0 = 0; @@ -1021,6 +1115,18 @@ static int k3_msmc_probe(struct udevice *dev) } msmc->num_ddr_controllers = ret; + if (IS_ENABLED(CONFIG_K3_MULTI_DDR) && IS_ENABLED(CONFIG_K3_INLINE_ECC)) { + ret = k3_msmc_calculate_r0_regions(msmc); + if (ret) { + /* Default to enabling inline ECC for entire DDR region */ + debug("%s: calculation of inline ECC regions failed, defaulting to entire region\n", + __func__); + + /* Use first R0 entry as a flag to denote MSMC calculation failure */ + msmc->R0[0].start = -1; + } + } + return 0; } -- cgit v1.2.3 From d1efbc8d65702f9eb7d032e904e092a2fd3075b3 Mon Sep 17 00:00:00 2001 From: Neha Malcom Francis Date: Tue, 12 Aug 2025 18:13:23 +0530 Subject: ram: k3-ddrss: Add support for partial inline ECC in multi-DDR systems The existing approach does not account for interleaving in the DDRs when setting up regions. There is support for MSMC to calculate the regions for each DDR, so modify k3_ddrss_probe to set the regions accordingly for multi-DDR systems. Signed-off-by: Neha Malcom Francis --- drivers/ram/k3-ddrss/k3-ddrss.c | 62 +++++++++++++++++++++++++++++++++-------- 1 file changed, 50 insertions(+), 12 deletions(-) diff --git a/drivers/ram/k3-ddrss/k3-ddrss.c b/drivers/ram/k3-ddrss/k3-ddrss.c index c7938000314..9b4c0c68d91 100644 --- a/drivers/ram/k3-ddrss/k3-ddrss.c +++ b/drivers/ram/k3-ddrss/k3-ddrss.c @@ -829,11 +829,13 @@ static void k3_ddrss_lpddr4_ecc_init(struct k3_ddrss_desc *ddrss) static int k3_ddrss_probe(struct udevice *dev) { - u64 end; + u64 end, bank0, bank1; int ret; struct k3_ddrss_desc *ddrss = dev_get_priv(dev); __maybe_unused u64 ddr_ram_size, ecc_res; + __maybe_unused u32 inst, st; __maybe_unused struct k3_ddrss_ecc_region *range = &ddrss->ecc_range; + __maybe_unused struct k3_msmc *msmc_parent = NULL; debug("%s(dev=%p)\n", __func__, dev); @@ -874,31 +876,67 @@ static int k3_ddrss_probe(struct udevice *dev) k3_ddrss_ddr_inline_ecc_base_size_calc(range); end = ddrss->ecc_range.start + ddrss->ecc_range.range; + inst = ddrss->instance; ddr_ram_size = ddrss->ddr_ram_size; ecc_res = ddrss->ecc_reserved_space; + bank0 = ddrss->ddr_bank_base[0]; + bank1 = ddrss->ddr_bank_base[1]; if (!range->range) { /* Configure entire DDR space by default */ debug("%s: Defaulting to protecting entire DDR space using inline ECC\n", __func__); - ddrss->ecc_range.start = ddrss->ddr_bank_base[0]; + ddrss->ecc_range.start = bank0; ddrss->ecc_range.range = ddr_ram_size - ecc_res; } else { ddrss->ecc_range.start = range->start; ddrss->ecc_range.range = range->range; } - /* - * As we are converting the system address to the DDR controller - * address, account for case when the region is in the second - * bank - */ - if (end > (ddr_ram_size - ecc_res)) - ddrss->ecc_regions[0].range = ddr_ram_size - ecc_res; - else - ddrss->ecc_regions[0].range = ddrss->ecc_range.range; + st = ddrss->ecc_range.start; + + if (!CONFIG_IS_ENABLED(K3_MULTI_DDR)) { + if (end > (ddr_ram_size - ecc_res)) + ddrss->ecc_regions[0].range = ddr_ram_size - ecc_res; + else + ddrss->ecc_regions[0].range = ddrss->ecc_range.range; - ddrss->ecc_regions[0].start = ddrss->ecc_range.start - ddrss->ddr_bank_base[0]; + /* Check in which bank we are */ + if (st > bank1) + ddrss->ecc_regions[0].start = st - bank1 + ddrss->ddr_bank_size[0]; + else + ddrss->ecc_regions[0].start = st - bank0; + } else { + /* For multi-DDR, we rely on MSMC's calculation of regions for each DDR */ + msmc_parent = kzalloc(sizeof(msmc_parent), GFP_KERNEL); + if (!msmc_parent) + return -ENOMEM; + + msmc_parent = dev_get_priv(dev->parent); + if (!msmc_parent) { + printf("%s: could not get MSMC parent to set up inline ECC regions\n", + __func__); + kfree(msmc_parent); + return -EINVAL; + } + + if (msmc_parent->R0[0].start < 0) { + /* Configure entire DDR space by default */ + ddrss->ecc_regions[0].start = ddrss->ddr_bank_base[0]; + ddrss->ecc_regions[0].range = ddr_ram_size - ecc_res; + } else { + end = msmc_parent->R0[inst].start + msmc_parent->R0[inst].range; + + if (end > (ddr_ram_size - ecc_res)) + ddrss->ecc_regions[0].range = ddr_ram_size - ecc_res; + else + ddrss->ecc_regions[0].range = msmc_parent->R0[inst].range; + + ddrss->ecc_regions[0].start = msmc_parent->R0[inst].start; + } + + kfree(msmc_parent); + } k3_ddrss_lpddr4_ecc_init(ddrss); } -- cgit v1.2.3 From 0824703fb2b49ed64edee6f8db483bedfa0189dd Mon Sep 17 00:00:00 2001 From: Neha Malcom Francis Date: Tue, 12 Aug 2025 18:13:24 +0530 Subject: ram: k3-ddrss: Support multiple ECC regions for a single controller K3 Inline ECC mechanism can support up to 3 regions of inline ECC, add this support for single controller. Signed-off-by: Neha Malcom Francis --- drivers/ram/k3-ddrss/k3-ddrss.c | 125 ++++++++++++++++++++++++++-------------- 1 file changed, 83 insertions(+), 42 deletions(-) diff --git a/drivers/ram/k3-ddrss/k3-ddrss.c b/drivers/ram/k3-ddrss/k3-ddrss.c index 9b4c0c68d91..5144470b931 100644 --- a/drivers/ram/k3-ddrss/k3-ddrss.c +++ b/drivers/ram/k3-ddrss/k3-ddrss.c @@ -176,7 +176,7 @@ struct k3_ddrss_desc { lpddr4_obj *driverdt; lpddr4_config config; lpddr4_privatedata pd; - struct k3_ddrss_ecc_region ecc_range; + struct k3_ddrss_ecc_region ecc_ranges[K3_DDRSS_MAX_ECC_REG]; struct k3_ddrss_ecc_region ecc_regions[K3_DDRSS_MAX_ECC_REG]; u64 ecc_reserved_space; u64 ddr_bank_base[CONFIG_NR_DRAM_BANKS]; @@ -576,10 +576,26 @@ void k3_lpddr4_start(struct k3_ddrss_desc *ddrss) } } -static void k3_ddrss_set_ecc_range_r0(u32 base, u64 start_address, u64 size) +static void k3_ddrss_set_ecc_range_rx(u32 x, u32 base, u64 start_address, u64 size) { - writel((start_address) >> 16, base + DDRSS_ECC_R0_STR_ADDR_REG); - writel((start_address + size - 1) >> 16, base + DDRSS_ECC_R0_END_ADDR_REG); + u32 start_reg, end_reg; + + switch (x) { + case 1: + start_reg = DDRSS_ECC_R1_STR_ADDR_REG; + end_reg = DDRSS_ECC_R1_END_ADDR_REG; + break; + case 2: + start_reg = DDRSS_ECC_R2_STR_ADDR_REG; + end_reg = DDRSS_ECC_R2_END_ADDR_REG; + break; + default: + start_reg = DDRSS_ECC_R0_STR_ADDR_REG; + end_reg = DDRSS_ECC_R0_END_ADDR_REG; + break; + } + writel((start_address) >> 16, base + start_reg); + writel((start_address + size - 1) >> 16, base + end_reg); } #define BIST_MODE_MEM_INIT 4 @@ -755,27 +771,40 @@ static void k3_ddrss_ddr_reg_init(struct k3_ddrss_desc *ddrss) writel(DDRSS_ECC_CTRL_REG_DEFAULT, ddrss->ddrss_ss_cfg + DDRSS_ECC_CTRL_REG); } +ofnode get_next_ecc_node(ofnode ecc) +{ + do { + ecc = ofnode_by_prop_value(ecc, "device_type", "ecc", 4); + } while (!ofnode_is_enabled(ecc)); + + return ecc; +} + static void k3_ddrss_ddr_inline_ecc_base_size_calc(struct k3_ddrss_ecc_region *range) { fdt_addr_t base; fdt_size_t size; - ofnode node1; - - node1 = ofnode_null(); - - do { - node1 = ofnode_by_prop_value(node1, "device_type", "ecc", 4); - } while (!ofnode_is_enabled(node1)); - - base = ofnode_get_addr_size(node1, "reg", &size); + ofnode ecc_node = ofnode_null(); - if (base == FDT_ADDR_T_NONE) { - debug("%s: Failed to get ECC node reg and size\n", __func__); + ecc_node = get_next_ecc_node(ecc_node); + if (!ofnode_valid(ecc_node)) { + debug("%s: No ECC node, enabling for entire region\n", __func__); range->start = 0; range->range = 0; - } else { + return; + } + + for (int i = 0; i < K3_DDRSS_MAX_ECC_REG; i++) { + base = ofnode_get_addr_size(ecc_node, "reg", &size); + if (base == FDT_ADDR_T_NONE) { + range->start = 0; + range->range = 0; + break; + } range->start = base; range->range = size; + range++; + ecc_node = get_next_ecc_node(ecc_node); } } @@ -798,13 +827,21 @@ static void k3_ddrss_lpddr4_ecc_calc_reserved_mem(struct k3_ddrss_desc *ddrss) static void k3_ddrss_lpddr4_ecc_init(struct k3_ddrss_desc *ddrss) { - u64 ecc_region_start = ddrss->ecc_regions[0].start; - u64 ecc_range = ddrss->ecc_regions[0].range; + u64 ecc_region0_start = ddrss->ecc_regions[0].start; + u64 ecc_range0 = ddrss->ecc_regions[0].range; + u64 ecc_region1_start = ddrss->ecc_regions[1].start; + u64 ecc_range1 = ddrss->ecc_regions[1].range; + u64 ecc_region2_start = ddrss->ecc_regions[2].start; + u64 ecc_range2 = ddrss->ecc_regions[2].range; u32 base = (u32)ddrss->ddrss_ss_cfg; u32 val; /* Only Program region 0 which covers full ddr space */ - k3_ddrss_set_ecc_range_r0(base, ecc_region_start, ecc_range); + k3_ddrss_set_ecc_range_rx(0, base, ecc_region0_start, ecc_range0); + if (ecc_range1) + k3_ddrss_set_ecc_range_rx(1, base, ecc_region1_start, ecc_range1); + if (ecc_range2) + k3_ddrss_set_ecc_range_rx(2, base, ecc_region2_start, ecc_range2); /* Enable ECC, RMW, WR_ALLOC */ writel(DDRSS_ECC_CTRL_REG_ECC_EN | DDRSS_ECC_CTRL_REG_RMW_EN | @@ -829,12 +866,12 @@ static void k3_ddrss_lpddr4_ecc_init(struct k3_ddrss_desc *ddrss) static int k3_ddrss_probe(struct udevice *dev) { - u64 end, bank0, bank1; + u64 end, bank0, bank1, bank0_size; int ret; struct k3_ddrss_desc *ddrss = dev_get_priv(dev); __maybe_unused u64 ddr_ram_size, ecc_res; - __maybe_unused u32 inst, st; - __maybe_unused struct k3_ddrss_ecc_region *range = &ddrss->ecc_range; + __maybe_unused u32 inst; + __maybe_unused struct k3_ddrss_ecc_region *range = ddrss->ecc_ranges; __maybe_unused struct k3_msmc *msmc_parent = NULL; debug("%s(dev=%p)\n", __func__, dev); @@ -875,39 +912,43 @@ static int k3_ddrss_probe(struct udevice *dev) k3_ddrss_ddr_inline_ecc_base_size_calc(range); - end = ddrss->ecc_range.start + ddrss->ecc_range.range; - inst = ddrss->instance; - ddr_ram_size = ddrss->ddr_ram_size; - ecc_res = ddrss->ecc_reserved_space; bank0 = ddrss->ddr_bank_base[0]; bank1 = ddrss->ddr_bank_base[1]; + bank0_size = ddrss->ddr_bank_size[0]; if (!range->range) { /* Configure entire DDR space by default */ debug("%s: Defaulting to protecting entire DDR space using inline ECC\n", __func__); - ddrss->ecc_range.start = bank0; - ddrss->ecc_range.range = ddr_ram_size - ecc_res; + ddrss->ecc_ranges[0].start = bank0; + ddrss->ecc_ranges[0].range = ddr_ram_size - ecc_res; } else { - ddrss->ecc_range.start = range->start; - ddrss->ecc_range.range = range->range; + ddrss->ecc_ranges[0].start = range->start; + ddrss->ecc_ranges[0].range = range->range; } - st = ddrss->ecc_range.start; - if (!CONFIG_IS_ENABLED(K3_MULTI_DDR)) { - if (end > (ddr_ram_size - ecc_res)) - ddrss->ecc_regions[0].range = ddr_ram_size - ecc_res; - else - ddrss->ecc_regions[0].range = ddrss->ecc_range.range; + struct k3_ddrss_ecc_region *r = range; - /* Check in which bank we are */ - if (st > bank1) - ddrss->ecc_regions[0].start = st - bank1 + ddrss->ddr_bank_size[0]; - else - ddrss->ecc_regions[0].start = st - bank0; + for (int i = 0; (i < K3_DDRSS_MAX_ECC_REG) && (r->range != 0); i++, r++) { + end = r->start + r->range; + ddr_ram_size = ddrss->ddr_ram_size; + ecc_res = ddrss->ecc_reserved_space; + + if (end > (ddr_ram_size - ecc_res)) + ddrss->ecc_regions[i].range = ddr_ram_size - ecc_res; + else + ddrss->ecc_regions[i].range = r->range; + + /* Check in which bank we are */ + if (r->start > bank1) + ddrss->ecc_regions[i].start = r->start - bank1 + bank0_size; + else + ddrss->ecc_regions[i].start = r->start - bank0; + } } else { /* For multi-DDR, we rely on MSMC's calculation of regions for each DDR */ + inst = ddrss->instance; msmc_parent = kzalloc(sizeof(msmc_parent), GFP_KERNEL); if (!msmc_parent) return -ENOMEM; @@ -922,7 +963,7 @@ static int k3_ddrss_probe(struct udevice *dev) if (msmc_parent->R0[0].start < 0) { /* Configure entire DDR space by default */ - ddrss->ecc_regions[0].start = ddrss->ddr_bank_base[0]; + ddrss->ecc_regions[0].start = bank0; ddrss->ecc_regions[0].range = ddr_ram_size - ecc_res; } else { end = msmc_parent->R0[inst].start + msmc_parent->R0[inst].range; -- cgit v1.2.3 From 3943531a54680b76813960655458e88f49f6bfb7 Mon Sep 17 00:00:00 2001 From: Chintan Vankar Date: Thu, 31 Jul 2025 13:29:36 +0530 Subject: net: ti: am65-cpsw-nuss: Define bind method for CPSW driver CPSW driver is defined as UCLASS_MISC driver which needs to be probed explicitly. Define bind method for CPSW driver to scan and bind ethernet-ports with UCLASS_ETH driver which will eventually probe CPSW driver and avoid probing CPSW driver explicitly. Signed-off-by: Chintan Vankar --- drivers/net/ti/am65-cpsw-nuss.c | 40 +++++++++++++++++++++++++++++++++------- 1 file changed, 33 insertions(+), 7 deletions(-) diff --git a/drivers/net/ti/am65-cpsw-nuss.c b/drivers/net/ti/am65-cpsw-nuss.c index 9b69f36d04d..754076d807c 100644 --- a/drivers/net/ti/am65-cpsw-nuss.c +++ b/drivers/net/ti/am65-cpsw-nuss.c @@ -705,7 +705,6 @@ static int am65_cpsw_probe_nuss(struct udevice *dev) struct am65_cpsw_common *cpsw_common = dev_get_priv(dev); ofnode ports_np, node; int ret, i; - struct udevice *port_dev; cpsw_common->dev = dev; cpsw_common->ss_base = dev_read_addr(dev); @@ -732,6 +731,7 @@ static int am65_cpsw_probe_nuss(struct udevice *dev) ports_np = dev_read_subnode(dev, "ethernet-ports"); if (!ofnode_valid(ports_np)) { ret = -ENOENT; + dev_err(dev, "Invalid device tree node %d\n", ret); goto out; } @@ -763,12 +763,6 @@ static int am65_cpsw_probe_nuss(struct udevice *dev) continue; cpsw_common->ports[port_id].disabled = disabled; - if (disabled) - continue; - - ret = device_bind_driver_to_node(dev, "am65_cpsw_nuss_port", ofnode_get_name(node), node, &port_dev); - if (ret) - dev_err(dev, "Failed to bind to %s node\n", ofnode_get_name(node)); } for (i = 0; i < AM65_CPSW_CPSWNU_MAX_PORTS; i++) { @@ -798,6 +792,37 @@ out: return ret; } +static int am65_cpsw_nuss_bind(struct udevice *dev) +{ + struct uclass_driver *drv; + struct udevice *port_dev; + ofnode ports_np, node; + int ret; + + drv = lists_uclass_lookup(UCLASS_ETH); + if (!drv) { + puts("Cannot find eth driver"); + return -ENOENT; + } + + ports_np = dev_read_subnode(dev, "ethernet-ports"); + if (!ofnode_valid(ports_np)) + return -ENOENT; + + ofnode_for_each_subnode(node, ports_np) { + const char *node_name; + + node_name = ofnode_get_name(node); + + ret = device_bind_driver_to_node(dev, "am65_cpsw_nuss_port", node_name, node, + &port_dev); + if (ret) + dev_err(dev, "Failed to bind to %s node\n", node_name); + } + + return ret; +} + static const struct udevice_id am65_cpsw_nuss_ids[] = { { .compatible = "ti,am654-cpsw-nuss" }, { .compatible = "ti,j721e-cpsw-nuss" }, @@ -809,6 +834,7 @@ U_BOOT_DRIVER(am65_cpsw_nuss) = { .name = "am65_cpsw_nuss", .id = UCLASS_MISC, .of_match = am65_cpsw_nuss_ids, + .bind = am65_cpsw_nuss_bind, .probe = am65_cpsw_probe_nuss, .priv_auto = sizeof(struct am65_cpsw_common), }; -- cgit v1.2.3 From 50ededad3204072a5fe6b8ee49826643e7c8e7aa Mon Sep 17 00:00:00 2001 From: Chintan Vankar Date: Thu, 31 Jul 2025 13:29:37 +0530 Subject: arch: mach-k3: common: Remove explicit probing of CPSW driver This reverts commit e58d9284850fa78d364d264087fe744717963675. Bind method of am65_cpsw_nuss driver will ensure binding of it's child driver am65_cpsw_nuss_ports, and there is no need to call CPSW driver explicitly. Remove explicit probing of CPSW driver for AM62x. Signed-off-by: Chintan Vankar --- arch/arm/mach-k3/common.c | 11 ----------- 1 file changed, 11 deletions(-) diff --git a/arch/arm/mach-k3/common.c b/arch/arm/mach-k3/common.c index f8c53b286eb..5483ac9906c 100644 --- a/arch/arm/mach-k3/common.c +++ b/arch/arm/mach-k3/common.c @@ -322,17 +322,6 @@ void spl_board_prepare_for_linux(void) int misc_init_r(void) { - if (IS_ENABLED(CONFIG_TI_AM65_CPSW_NUSS)) { - struct udevice *dev; - int ret; - - ret = uclass_get_device_by_driver(UCLASS_MISC, - DM_DRIVER_GET(am65_cpsw_nuss), - &dev); - if (ret) - printf("Failed to probe am65_cpsw_nuss driver\n"); - } - if (IS_ENABLED(CONFIG_TI_ICSSG_PRUETH)) { struct udevice *dev; int ret; -- cgit v1.2.3 From 3967d64740b69cda6b2642036bfb9269b05a7e35 Mon Sep 17 00:00:00 2001 From: Chintan Vankar Date: Thu, 31 Jul 2025 13:29:38 +0530 Subject: Revert "mach-k3: am642_init: Probe AM65 CPSW NUSS for R5/A53 SPL" This reverts commit 93c43a8365fae0f188ac091d129542470ddaf62d. Bind method of "am65_cpsw_nuss" driver will ensure binding of it's child driver "am65_cpsw_nuss_ports", and there is no need to probe CPSW driver explicitly. Signed-off-by: Chintan Vankar --- arch/arm/mach-k3/am64x/am642_init.c | 7 ------- 1 file changed, 7 deletions(-) diff --git a/arch/arm/mach-k3/am64x/am642_init.c b/arch/arm/mach-k3/am64x/am642_init.c index 41812b7dbf7..219798315db 100644 --- a/arch/arm/mach-k3/am64x/am642_init.c +++ b/arch/arm/mach-k3/am64x/am642_init.c @@ -263,13 +263,6 @@ void board_init_f(ulong dummy) if (ret) panic("DRAM init failed: %d\n", ret); #endif - if (IS_ENABLED(CONFIG_SPL_ETH) && IS_ENABLED(CONFIG_TI_AM65_CPSW_NUSS) && - spl_boot_device() == BOOT_DEVICE_ETHERNET) { - struct udevice *cpswdev; - - if (uclass_get_device_by_driver(UCLASS_MISC, DM_DRIVER_GET(am65_cpsw_nuss), &cpswdev)) - printf("Failed to probe am65_cpsw_nuss driver\n"); - } } u32 spl_mmc_boot_mode(struct mmc *mmc, const u32 boot_device) -- cgit v1.2.3 From b4a0702c924851906b1c127b3c9884e8a4870bd1 Mon Sep 17 00:00:00 2001 From: Chintan Vankar Date: Thu, 31 Jul 2025 13:29:39 +0530 Subject: Revert "arm: mach-k3: am62x: am625_init: Probe AM65 CPSW NUSS" This reverts commit 35bddf889652081f150f60740618851b5d4817f4. Bind method of "am65_cpsw_nuss" driver will ensure binding of it's child driver "am65_cpsw_nuss_ports", and there is no need to probe CPSW driver explicitly. Signed-off-by: Chintan Vankar --- arch/arm/mach-k3/am62x/am625_init.c | 9 --------- 1 file changed, 9 deletions(-) diff --git a/arch/arm/mach-k3/am62x/am625_init.c b/arch/arm/mach-k3/am62x/am625_init.c index a422919fab1..8f4ddf59753 100644 --- a/arch/arm/mach-k3/am62x/am625_init.c +++ b/arch/arm/mach-k3/am62x/am625_init.c @@ -294,15 +294,6 @@ void board_init_f(ulong dummy) } spl_enable_cache(); - if (IS_ENABLED(CONFIG_SPL_ETH) && IS_ENABLED(CONFIG_TI_AM65_CPSW_NUSS) && - spl_boot_device() == BOOT_DEVICE_ETHERNET) { - struct udevice *cpswdev; - - if (uclass_get_device_by_driver(UCLASS_MISC, DM_DRIVER_GET(am65_cpsw_nuss), - &cpswdev)) - printf("Failed to probe am65_cpsw_nuss driver\n"); - } - fixup_a53_cpu_freq_by_speed_grade(); } -- cgit v1.2.3 From 0b092a2aa81b84eba1ea48f87c04b0be62afd1e9 Mon Sep 17 00:00:00 2001 From: Chintan Vankar Date: Thu, 31 Jul 2025 13:29:40 +0530 Subject: arm: mach-k3: j721s2: Update SoC auto-gen data to enable Ethernet boot Update dev-data and clk-data to include CPSW device which is required to enable Ethernet boot. Reviewed-by: Bryan Brattlof Signed-off-by: Chintan Vankar --- arch/arm/mach-k3/r5/j721s2/clk-data.c | 58 +++++++++++++++++++++++++++++++++-- arch/arm/mach-k3/r5/j721s2/dev-data.c | 3 +- 2 files changed, 57 insertions(+), 4 deletions(-) diff --git a/arch/arm/mach-k3/r5/j721s2/clk-data.c b/arch/arm/mach-k3/r5/j721s2/clk-data.c index 0c5c321c1eb..0130c9c4b86 100644 --- a/arch/arm/mach-k3/r5/j721s2/clk-data.c +++ b/arch/arm/mach-k3/r5/j721s2/clk-data.c @@ -5,7 +5,7 @@ * This file is auto generated. Please do not hand edit and report any issues * to Dave Gerlach . * - * Copyright (C) 2020-2021 Texas Instruments Incorporated - https://www.ti.com/ + * Copyright (C) 2020-2025 Texas Instruments Incorporated - https://www.ti.com/ */ #include @@ -55,6 +55,32 @@ static const char * const mcu_ospi_ref_clk_sel_out1_parents[] = { "hsdiv4_16fft_mcu_2_hsdivout4_clk", }; +static const char * const wkup_gpio0_clksel_out0_parents[] = { + "k3_pll_ctrl_wrap_wkup_0_chip_div1_clk_clk", + "k3_pll_ctrl_wrap_wkup_0_chip_div1_clk_clk", + "j7am_wakeup_16ff_wkup_0_wkup_rcosc_32k_clk", + "j7am_wakeup_16ff_wkup_0_wkup_rcosc_12p5m_clk", +}; + +static const char * const cpsw2g_cpts_rclk_sel_out0_parents[] = { + "hsdiv4_16fft_main_3_hsdivout1_clk", + "postdiv3_16fft_main_0_hsdivout6_clk", + "board_0_mcu_cpts0_rft_clk_out", + "board_0_cpts0_rft_clk_out", + "board_0_mcu_ext_refclk0_out", + "board_0_ext_refclk1_out", + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + "hsdiv4_16fft_mcu_2_hsdivout1_clk", + "k3_pll_ctrl_wrap_wkup_0_chip_div1_clk_clk", +}; + static const char * const mcu_usart_clksel_out0_parents[] = { "hsdiv4_16fft_mcu_1_hsdivout3_clk", "postdiv3_16fft_main_1_hsdivout5_clk", @@ -174,7 +200,11 @@ static const struct clk_data clk_list[] = { CLK_FIXED_RATE("board_0_hfosc1_clk_out", 0, 0), CLK_FIXED_RATE("board_0_mcu_ospi0_dqs_out", 0, 0), CLK_FIXED_RATE("board_0_mcu_ospi1_dqs_out", 0, 0), + CLK_FIXED_RATE("board_0_mcu_rgmii1_rxc_out", 0, 0), + CLK_FIXED_RATE("board_0_mcu_rmii1_ref_clk_out", 0, 0), CLK_FIXED_RATE("board_0_wkup_i2c0_scl_out", 0, 0), + CLK_FIXED_RATE("cpsw_2guss_mcu_0_mdio_mdclk_o", 0, 0), + CLK_FIXED_RATE("cpsw_2guss_mcu_0_rgmii1_txc_o", 0, 0), CLK_FIXED_RATE("fss_mcu_0_hyperbus1p0_0_hpb_out_clk_n", 0, 0), CLK_FIXED_RATE("fss_mcu_0_hyperbus1p0_0_hpb_out_clk_p", 0, 0), CLK_FIXED_RATE("fss_mcu_0_ospi_0_ospi_oclk_clk", 0, 0), @@ -199,6 +229,8 @@ static const struct clk_data clk_list[] = { CLK_DIV("k3_pll_ctrl_wrap_wkup_0_chip_div1_clk_clk", "k3_pll_ctrl_wrap_wkup_0_sysclkout_clk", 0x42010118, 0, 5, 0, 0), CLK_MUX("mcu_ospi_ref_clk_sel_out0", mcu_ospi_ref_clk_sel_out0_parents, 2, 0x40f08030, 0, 1, 0), CLK_MUX("mcu_ospi_ref_clk_sel_out1", mcu_ospi_ref_clk_sel_out1_parents, 2, 0x40f08034, 0, 1, 0), + CLK_MUX("wkup_gpio0_clksel_out0", wkup_gpio0_clksel_out0_parents, 4, 0x43008070, 0, 2, 0), + CLK_MUX("cpsw2g_cpts_rclk_sel_out0", cpsw2g_cpts_rclk_sel_out0_parents, 16, 0x40f08050, 8, 4, 0), CLK_MUX("mcu_usart_clksel_out0", mcu_usart_clksel_out0_parents, 2, 0x40f081c0, 0, 1, 0), CLK_MUX("wkup_i2c_mcupll_bypass_out0", wkup_i2c_mcupll_bypass_out0_parents, 2, 0x43008060, 0, 1, 0), CLK_MUX("main_pll_hfosc_sel_out0", main_pll_hfosc_sel_out0_parents, 2, 0x43008080, 0, 1, 0), @@ -275,6 +307,24 @@ static const struct dev_clk soc_dev_clk_data[] = { DEV_CLK(4, 0, "hsdiv0_16fft_main_8_hsdivout0_clk"), DEV_CLK(4, 1, "hsdiv0_16fft_main_7_hsdivout0_clk"), DEV_CLK(4, 2, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"), + DEV_CLK(29, 3, "cpsw2g_cpts_rclk_sel_out0"), + DEV_CLK(29, 4, "hsdiv4_16fft_main_3_hsdivout1_clk"), + DEV_CLK(29, 5, "postdiv3_16fft_main_0_hsdivout6_clk"), + DEV_CLK(29, 6, "board_0_mcu_cpts0_rft_clk_out"), + DEV_CLK(29, 7, "board_0_cpts0_rft_clk_out"), + DEV_CLK(29, 8, "board_0_mcu_ext_refclk0_out"), + DEV_CLK(29, 9, "board_0_ext_refclk1_out"), + DEV_CLK(29, 18, "hsdiv4_16fft_mcu_2_hsdivout1_clk"), + DEV_CLK(29, 19, "k3_pll_ctrl_wrap_wkup_0_chip_div1_clk_clk"), + DEV_CLK(29, 20, "hsdiv4_16fft_mcu_2_hsdivout0_clk"), + DEV_CLK(29, 21, "hsdiv4_16fft_mcu_2_hsdivout0_clk"), + DEV_CLK(29, 22, "board_0_mcu_rgmii1_rxc_out"), + DEV_CLK(29, 26, "board_0_mcu_rmii1_ref_clk_out"), + DEV_CLK(29, 28, "k3_pll_ctrl_wrap_wkup_0_chip_div1_clk_clk"), + DEV_CLK(29, 29, "hsdiv4_16fft_mcu_2_hsdivout0_clk"), + DEV_CLK(29, 30, "hsdiv4_16fft_mcu_2_hsdivout0_clk"), + DEV_CLK(29, 32, "hsdiv4_16fft_mcu_2_hsdivout0_clk"), + DEV_CLK(29, 33, "hsdiv4_16fft_mcu_2_hsdivout0_clk"), DEV_CLK(43, 0, "postdiv3_16fft_main_0_hsdivout8_clk"), DEV_CLK(43, 1, "hsdiv4_16fft_main_0_hsdivout3_clk"), DEV_CLK(43, 2, "gluelogic_hfosc0_clkout"), @@ -367,6 +417,7 @@ static const struct dev_clk soc_dev_clk_data[] = { DEV_CLK(157, 187, "fss_mcu_0_ospi_1_ospi_oclk_clk"), DEV_CLK(157, 194, "emmcsd4ss_main_0_emmcsdss_io_clk_o"), DEV_CLK(157, 197, "j7am_ddr_ew_wrap_dv_wrap_main_0_ddrss_io_ck_n"), + DEV_CLK(157, 207, "cpsw_2guss_mcu_0_mdio_mdclk_o"), DEV_CLK(157, 208, "j7am_ddr_ew_wrap_dv_wrap_main_1_ddrss_io_ck_n"), DEV_CLK(157, 214, "fss_mcu_0_hyperbus1p0_0_hpb_out_clk_p"), DEV_CLK(157, 221, "mcu_clkout_mux_out0"), @@ -374,6 +425,7 @@ static const struct dev_clk soc_dev_clk_data[] = { DEV_CLK(157, 223, "hsdiv4_16fft_mcu_2_hsdivout0_clk"), DEV_CLK(157, 225, "emmc8ss_16ffc_main_0_emmcss_io_clk"), DEV_CLK(157, 231, "fss_mcu_0_hyperbus1p0_0_hpb_out_clk_n"), + DEV_CLK(157, 244, "cpsw_2guss_mcu_0_rgmii1_txc_o"), DEV_CLK(157, 352, "dpi0_ext_clksel_out0"), DEV_CLK(180, 0, "gluelogic_hfosc0_clkout"), DEV_CLK(180, 2, "k3_pll_ctrl_wrap_wkup_0_chip_div1_clk_clk"), @@ -400,7 +452,7 @@ static const struct dev_clk soc_dev_clk_data[] = { const struct ti_k3_clk_platdata j721s2_clk_platdata = { .clk_list = clk_list, - .clk_list_cnt = 105, + .clk_list_cnt = ARRAY_SIZE(clk_list), .soc_dev_clk_data = soc_dev_clk_data, - .soc_dev_clk_data_cnt = 124, + .soc_dev_clk_data_cnt = ARRAY_SIZE(soc_dev_clk_data), }; diff --git a/arch/arm/mach-k3/r5/j721s2/dev-data.c b/arch/arm/mach-k3/r5/j721s2/dev-data.c index df70c5e5d7c..b78550707c5 100644 --- a/arch/arm/mach-k3/r5/j721s2/dev-data.c +++ b/arch/arm/mach-k3/r5/j721s2/dev-data.c @@ -5,7 +5,7 @@ * This file is auto generated. Please do not hand edit and report any issues * to Dave Gerlach . * - * Copyright (C) 2020-2021 Texas Instruments Incorporated - https://www.ti.com/ + * Copyright (C) 2020-2025 Texas Instruments Incorporated - https://www.ti.com/ */ #include "k3-dev.h" @@ -47,6 +47,7 @@ static struct ti_lpsc soc_lpsc_list[] = { }; static struct ti_dev soc_dev_list[] = { + PSC_DEV(29, &soc_lpsc_list[0]), PSC_DEV(35, &soc_lpsc_list[0]), PSC_DEV(108, &soc_lpsc_list[0]), PSC_DEV(109, &soc_lpsc_list[0]), -- cgit v1.2.3 From e85b090165ec55ef7e19bdd7fc11e9e6f74ec58e Mon Sep 17 00:00:00 2001 From: Chintan Vankar Date: Thu, 31 Jul 2025 13:29:41 +0530 Subject: arm: mach-k3: j721s2_spl: Alias Ethernet boot to CPGMAC This is required to enable spl_net boot on SK-AM68. Signed-off-by: Chintan Vankar --- arch/arm/mach-k3/include/mach/j721s2_spl.h | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/mach-k3/include/mach/j721s2_spl.h b/arch/arm/mach-k3/include/mach/j721s2_spl.h index d8fae2c8b45..47a61281d94 100644 --- a/arch/arm/mach-k3/include/mach/j721s2_spl.h +++ b/arch/arm/mach-k3/include/mach/j721s2_spl.h @@ -12,6 +12,7 @@ #define BOOT_DEVICE_OSPI 0x01 #define BOOT_DEVICE_QSPI 0x02 #define BOOT_DEVICE_SPI 0x03 +#define BOOT_DEVICE_CPGMAC 0x04 #define BOOT_DEVICE_ETHERNET 0x04 #define BOOT_DEVICE_I2C 0x06 #define BOOT_DEVICE_UART 0x07 -- cgit v1.2.3 From 333b50d32d76ded3d69e3f65d47ca0de1d32dcc4 Mon Sep 17 00:00:00 2001 From: Chintan Vankar Date: Thu, 31 Jul 2025 13:29:42 +0530 Subject: net: ti: Kconfig: Enable SPL_SYSCON config for CPSW TI's Ethernet switch needs system controllers enabled in R5SPL stage while booting via Ethernet. Enable SPL_SYSCON config for CONFIG_TI_AM65_CPSW_NUSS. Reviewed-by: Alexander Sverdlin Signed-off-by: Chintan Vankar --- drivers/net/ti/Kconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/net/ti/Kconfig b/drivers/net/ti/Kconfig index ddfa95a0b7e..3d495a56670 100644 --- a/drivers/net/ti/Kconfig +++ b/drivers/net/ti/Kconfig @@ -46,6 +46,7 @@ config TI_AM65_CPSW_NUSS imply MISC imply SYSCON imply MDIO_TI_CPSW + imply SPL_SYSCON select PHYLIB help This driver supports TI K3 MCU CPSW Nuss Ethernet controller -- cgit v1.2.3 From 07774020f75b51fc3437d697528cac5978b407ac Mon Sep 17 00:00:00 2001 From: Chintan Vankar Date: Thu, 31 Jul 2025 13:29:43 +0530 Subject: configs: am68_sk_r5_ethboot: Add configs for enabling Ethernet boot in R5SPL Add configs for enabling Ethernet boot in R5SPL, also disable not required configs to avoid memory limitation. Signed-off-by: Chintan Vankar --- configs/am68_sk_r5_ethboot_defconfig | 23 +++++++++++++++++++++++ 1 file changed, 23 insertions(+) create mode 100644 configs/am68_sk_r5_ethboot_defconfig diff --git a/configs/am68_sk_r5_ethboot_defconfig b/configs/am68_sk_r5_ethboot_defconfig new file mode 100644 index 00000000000..f0815b781d5 --- /dev/null +++ b/configs/am68_sk_r5_ethboot_defconfig @@ -0,0 +1,23 @@ +#include + +CONFIG_ARM=y +CONFIG_ARCH_K3=y +CONFIG_SOC_K3_J721S2=y +CONFIG_TARGET_J721S2_R5_EVM=y +CONFIG_DEFAULT_DEVICE_TREE="k3-am68-sk-r5-base-board" +CONFIG_SPL_BOARD_INIT=y +CONFIG_SPL_DMA=y +CONFIG_SPL_ETH=y +CONFIG_SPL_NET=y +CONFIG_SPL_NET_VCI_STRING="AM68 U-Boot R5 SPL" +CONFIG_TI_K3_NAVSS_UDMA=y +CONFIG_TI_AM65_CPSW_NUSS=y +CONFIG_SPI=n +CONFIG_SPL_SPI=n +CONFIG_DM_SPI=n +CONFIG_MTD=n +CONFIG_SPL_MTD=n +CONFIG_SPL_NAND_SPI_SUPPORT=n +CONFIG_NOR_SUPPORT=n +CONFIG_SPL_NOR_SUPPORT=n +CONFIG_SYS_MALLOC_CLEAR_ON_INIT=n -- cgit v1.2.3 From 3325b13d53f5a8991185936adc981678eb6d1b97 Mon Sep 17 00:00:00 2001 From: Chintan Vankar Date: Thu, 31 Jul 2025 13:29:44 +0530 Subject: configs: am68_sk_a72_ethboot: Enable configs required for Ethernet boot Enable config options needed to support Ethernet boot on AM68-SK. Signed-off-by: Chintan Vankar --- configs/am68_sk_a72_ethboot_defconfig | 14 ++++++++++++++ 1 file changed, 14 insertions(+) create mode 100644 configs/am68_sk_a72_ethboot_defconfig diff --git a/configs/am68_sk_a72_ethboot_defconfig b/configs/am68_sk_a72_ethboot_defconfig new file mode 100644 index 00000000000..d9d6ca6088e --- /dev/null +++ b/configs/am68_sk_a72_ethboot_defconfig @@ -0,0 +1,14 @@ +#include + +CONFIG_ARM=y +CONFIG_ARCH_K3=y +CONFIG_SOC_K3_J721S2=y +CONFIG_TARGET_J721S2_A72_EVM=y +CONFIG_DEFAULT_DEVICE_TREE="ti/k3-am68-sk-base-board" +CONFIG_SPL_STACK_R_ADDR=0x82000000 +CONFIG_SPL_DRIVERS_MISC=y +CONFIG_SPL_BOARD_INIT=y +CONFIG_SPL_DMA=y +CONFIG_SPL_ETH=y +CONFIG_SPL_NET=y +CONFIG_SPL_NET_VCI_STRING="AM68 U-Boot A72 SPL" -- cgit v1.2.3 From 6fc2a6a97171e0d4ecb8cef9385fb1a0a0a14611 Mon Sep 17 00:00:00 2001 From: Andreas Dannenberg Date: Thu, 31 Jul 2025 13:29:45 +0530 Subject: arm: mach-k3: am62p: Update SoC auto-gen data to enable Ethernet boot Update dev-data and clk-data to enable Ethernet boot using CPSW on SK-AM62P-LP. Signed-off-by: Andreas Dannenberg Signed-off-by: Chintan Vankar --- arch/arm/mach-k3/r5/am62px/clk-data.c | 44 ++++++++++++++++++++++++++++++++--- arch/arm/mach-k3/r5/am62px/dev-data.c | 24 ++++++++++--------- 2 files changed, 54 insertions(+), 14 deletions(-) diff --git a/arch/arm/mach-k3/r5/am62px/clk-data.c b/arch/arm/mach-k3/r5/am62px/clk-data.c index bc62d1d0d08..b552a2be74d 100644 --- a/arch/arm/mach-k3/r5/am62px/clk-data.c +++ b/arch/arm/mach-k3/r5/am62px/clk-data.c @@ -5,7 +5,7 @@ * This file is auto generated. Please do not hand edit and report any issues * to Bryan Brattlof . * - * Copyright (C) 2020-2023 Texas Instruments Incorporated - https://www.ti.com/ + * Copyright (C) 2020-2025 Texas Instruments Incorporated - https://www.ti.com/ */ #include @@ -62,6 +62,17 @@ static const char * const clkout0_ctrl_out0_parents[] = { "hsdiv4_16fft_main_2_hsdivout1_clk10", }; +static const char * const main_cp_gemac_cpts_clk_sel_out0_parents[] = { + "postdiv4_16ff_main_2_hsdivout5_clk", + "postdiv4_16ff_main_0_hsdivout6_clk", + "board_0_cp_gemac_cpts0_rft_clk_out", + NULL, + "board_0_mcu_ext_refclk0_out", + "board_0_ext_refclk1_out", + NULL, + "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk", +}; + static const char * const main_emmcsd0_refclk_sel_out0_parents[] = { "postdiv4_16ff_main_0_hsdivout5_clk", "hsdiv4_16fft_main_2_hsdivout2_clk", @@ -99,8 +110,8 @@ static const char * const main_timerclkn_sel_out0_parents[] = { "board_0_cp_gemac_cpts0_rft_clk_out", "hsdiv4_16fft_main_1_hsdivout3_clk", "postdiv4_16ff_main_2_hsdivout6_clk", - NULL, - NULL, + "cpsw_3guss_am67_main_0_cpts_genf0", + "cpsw_3guss_am67_main_0_cpts_genf1", NULL, NULL, NULL, @@ -148,7 +159,12 @@ static const struct clk_data clk_list[] = { CLK_FIXED_RATE("board_0_mmc1_clk_out", 0, 0), CLK_FIXED_RATE("board_0_ospi0_dqs_out", 0, 0), CLK_FIXED_RATE("board_0_ospi0_lbclko_out", 0, 0), + CLK_FIXED_RATE("board_0_rmii1_ref_clk_out", 0, 0), + CLK_FIXED_RATE("board_0_rmii2_ref_clk_out", 0, 0), CLK_FIXED_RATE("board_0_tck_out", 0, 0), + CLK_FIXED_RATE("cpsw_3guss_am67_main_0_cpts_genf0", 0, 0), + CLK_FIXED_RATE("cpsw_3guss_am67_main_0_cpts_genf1", 0, 0), + CLK_FIXED_RATE("cpsw_3guss_am67_main_0_mdio_mdclk_o", 0, 0), CLK_FIXED_RATE("dmtimer_dmc1ms_main_0_timer_pwm", 0, 0), CLK_FIXED_RATE("emmcsd4ss_main_0_emmcsdss_io_clk_o", 0, 0), CLK_FIXED_RATE("fss_ul_main_0_ospi_0_ospi_oclk_clk", 0, 0), @@ -201,6 +217,7 @@ static const struct clk_data clk_list[] = { CLK_MUX_PLLCTRL("sam62_pll_ctrl_wrap_mcu_0_sysclkout_clk", sam62_pll_ctrl_wrap_mcu_0_sysclkout_clk_parents, 2, 0x4020000, 0), CLK_DIV("sam62_pll_ctrl_wrap_mcu_0_chip_div1_clk_clk", "sam62_pll_ctrl_wrap_mcu_0_sysclkout_clk", 0x4020118, 0, 5, 0, 0), CLK_MUX("clkout0_ctrl_out0", clkout0_ctrl_out0_parents, 2, 0x108010, 0, 1, 0), + CLK_MUX("main_cp_gemac_cpts_clk_sel_out0", main_cp_gemac_cpts_clk_sel_out0_parents, 8, 0x108140, 0, 3, 0), CLK_MUX("main_emmcsd0_refclk_sel_out0", main_emmcsd0_refclk_sel_out0_parents, 2, 0x108160, 0, 1, 0), CLK_MUX("main_emmcsd1_refclk_sel_out0", main_emmcsd1_refclk_sel_out0_parents, 2, 0x108168, 0, 1, 0), CLK_MUX("main_gtcclk_sel_out0", main_gtcclk_sel_out0_parents, 8, 0x43008030, 0, 3, 0), @@ -216,6 +233,24 @@ static const struct clk_data clk_list[] = { }; static const struct dev_clk soc_dev_clk_data[] = { + DEV_CLK(13, 0, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"), + DEV_CLK(13, 3, "main_cp_gemac_cpts_clk_sel_out0"), + DEV_CLK(13, 4, "postdiv4_16ff_main_2_hsdivout5_clk"), + DEV_CLK(13, 5, "postdiv4_16ff_main_0_hsdivout6_clk"), + DEV_CLK(13, 6, "board_0_cp_gemac_cpts0_rft_clk_out"), + DEV_CLK(13, 8, "board_0_mcu_ext_refclk0_out"), + DEV_CLK(13, 9, "board_0_ext_refclk1_out"), + DEV_CLK(13, 11, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"), + DEV_CLK(13, 13, "hsdiv4_16fft_main_2_hsdivout1_clk"), + DEV_CLK(13, 14, "hsdiv4_16fft_main_2_hsdivout1_clk"), + DEV_CLK(13, 15, "hsdiv4_16fft_main_2_hsdivout1_clk"), + DEV_CLK(13, 16, "hsdiv4_16fft_main_2_hsdivout1_clk"), + DEV_CLK(13, 17, "hsdiv4_16fft_main_2_hsdivout1_clk"), + DEV_CLK(13, 19, "hsdiv4_16fft_main_2_hsdivout1_clk"), + DEV_CLK(13, 20, "hsdiv4_16fft_main_2_hsdivout1_clk"), + DEV_CLK(13, 21, "hsdiv4_16fft_main_2_hsdivout1_clk"), + DEV_CLK(13, 22, "board_0_rmii1_ref_clk_out"), + DEV_CLK(13, 23, "board_0_rmii2_ref_clk_out"), DEV_CLK(16, 0, "hsdiv4_16fft_main_0_hsdivout1_clk"), DEV_CLK(16, 1, "hsdiv4_16fft_main_0_hsdivout2_clk"), DEV_CLK(16, 2, "hsdiv4_16fft_main_0_hsdivout3_clk"), @@ -240,6 +275,8 @@ static const struct dev_clk soc_dev_clk_data[] = { DEV_CLK(36, 10, "board_0_cp_gemac_cpts0_rft_clk_out"), DEV_CLK(36, 11, "hsdiv4_16fft_main_1_hsdivout3_clk"), DEV_CLK(36, 12, "postdiv4_16ff_main_2_hsdivout6_clk"), + DEV_CLK(36, 13, "cpsw_3guss_am67_main_0_cpts_genf0"), + DEV_CLK(36, 14, "cpsw_3guss_am67_main_0_cpts_genf1"), DEV_CLK(57, 1, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"), DEV_CLK(57, 2, "main_emmcsd0_refclk_sel_out0"), DEV_CLK(57, 3, "postdiv4_16ff_main_0_hsdivout5_clk"), @@ -286,6 +323,7 @@ static const struct dev_clk soc_dev_clk_data[] = { DEV_CLK(157, 40, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"), DEV_CLK(157, 54, "mshsi2c_main_0_porscl"), DEV_CLK(157, 91, "sam62_pll_ctrl_wrap_mcu_0_sysclkout_clk"), + DEV_CLK(157, 96, "cpsw_3guss_am67_main_0_mdio_mdclk_o"), DEV_CLK(157, 101, "emmcsd4ss_main_0_emmcsdss_io_clk_o"), DEV_CLK(157, 103, "emmcsd4ss_main_0_emmcsdss_io_clk_o"), DEV_CLK(157, 143, "fss_ul_main_0_ospi_0_ospi_oclk_clk"), diff --git a/arch/arm/mach-k3/r5/am62px/dev-data.c b/arch/arm/mach-k3/r5/am62px/dev-data.c index 3cc211ea202..63e6beb4d57 100644 --- a/arch/arm/mach-k3/r5/am62px/dev-data.c +++ b/arch/arm/mach-k3/r5/am62px/dev-data.c @@ -5,7 +5,7 @@ * This file is auto generated. Please do not hand edit and report any issues * to Bryan Brattlof . * - * Copyright (C) 2020-2023 Texas Instruments Incorporated - https://www.ti.com/ + * Copyright (C) 2020-2025 Texas Instruments Incorporated - https://www.ti.com/ */ #include "k3-dev.h" @@ -31,11 +31,12 @@ static struct ti_lpsc soc_lpsc_list[] = { [6] = PSC_LPSC(24, &soc_psc_list[0], &soc_pd_list[0], &soc_lpsc_list[8]), [7] = PSC_LPSC(28, &soc_psc_list[0], &soc_pd_list[0], &soc_lpsc_list[8]), [8] = PSC_LPSC(34, &soc_psc_list[0], &soc_pd_list[0], &soc_lpsc_list[8]), - [9] = PSC_LPSC(53, &soc_psc_list[0], &soc_pd_list[1], &soc_lpsc_list[8]), - [10] = PSC_LPSC(56, &soc_psc_list[0], &soc_pd_list[2], &soc_lpsc_list[9]), - [11] = PSC_LPSC(72, &soc_psc_list[0], &soc_pd_list[3], &soc_lpsc_list[8]), - [12] = PSC_LPSC(73, &soc_psc_list[0], &soc_pd_list[3], &soc_lpsc_list[11]), - [13] = PSC_LPSC(74, &soc_psc_list[0], &soc_pd_list[3], &soc_lpsc_list[12]), + [9] = PSC_LPSC(42, &soc_psc_list[0], &soc_pd_list[0], &soc_lpsc_list[8]), + [10] = PSC_LPSC(53, &soc_psc_list[0], &soc_pd_list[1], &soc_lpsc_list[8]), + [11] = PSC_LPSC(56, &soc_psc_list[0], &soc_pd_list[2], &soc_lpsc_list[10]), + [12] = PSC_LPSC(72, &soc_psc_list[0], &soc_pd_list[3], &soc_lpsc_list[8]), + [13] = PSC_LPSC(73, &soc_psc_list[0], &soc_pd_list[3], &soc_lpsc_list[12]), + [14] = PSC_LPSC(74, &soc_psc_list[0], &soc_pd_list[3], &soc_lpsc_list[13]), }; static struct ti_dev soc_dev_list[] = { @@ -52,11 +53,12 @@ static struct ti_dev soc_dev_list[] = { PSC_DEV(36, &soc_lpsc_list[8]), PSC_DEV(102, &soc_lpsc_list[8]), PSC_DEV(146, &soc_lpsc_list[8]), - PSC_DEV(166, &soc_lpsc_list[9]), - PSC_DEV(135, &soc_lpsc_list[10]), - PSC_DEV(170, &soc_lpsc_list[11]), - PSC_DEV(177, &soc_lpsc_list[12]), - PSC_DEV(55, &soc_lpsc_list[13]), + PSC_DEV(13, &soc_lpsc_list[9]), + PSC_DEV(166, &soc_lpsc_list[10]), + PSC_DEV(135, &soc_lpsc_list[11]), + PSC_DEV(170, &soc_lpsc_list[12]), + PSC_DEV(177, &soc_lpsc_list[13]), + PSC_DEV(55, &soc_lpsc_list[14]), }; const struct ti_k3_pd_platdata am62px_pd_platdata = { -- cgit v1.2.3 From 3bab8f17fb17c59f83ef409eb14b3aec92cd3f9b Mon Sep 17 00:00:00 2001 From: Andreas Dannenberg Date: Thu, 31 Jul 2025 13:29:46 +0530 Subject: board: ti: am62px: evm: Enable cache for AM62p Enable cache for AM62p to optimize performance of CPU to access data from memory. Reviewed-by: Alexander Sverdlin Signed-off-by: Andreas Dannenberg Signed-off-by: Chintan Vankar --- board/ti/am62px/evm.c | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/board/ti/am62px/evm.c b/board/ti/am62px/evm.c index 2e85363cf5f..c06e3878d67 100644 --- a/board/ti/am62px/evm.c +++ b/board/ti/am62px/evm.c @@ -9,6 +9,7 @@ #include #include #include +#include #include #include #include @@ -41,6 +42,13 @@ struct efi_capsule_update_info update_info = { .images = fw_images, }; +#if IS_ENABLED(CONFIG_SPL_BUILD) +void spl_board_init(void) +{ + enable_caches(); +} +#endif + #if defined(CONFIG_XPL_BUILD) void spl_perform_fixups(struct spl_image_info *spl_image) { -- cgit v1.2.3 From c8c2da2ab817d78efdad88b85ef4449dd5719e01 Mon Sep 17 00:00:00 2001 From: Andreas Dannenberg Date: Thu, 31 Jul 2025 13:29:47 +0530 Subject: configs: am62px_evm_r5_ethboot: Add configs to enable Ethernet boot in R5SPL Add configs for enabling Ethernet boot in R5SPL, also disable not required configs to avoid memory limitation. Signed-off-by: Andreas Dannenberg Signed-off-by: Chintan Vankar --- configs/am62px_evm_r5_ethboot_defconfig | 29 +++++++++++++++++++++++++++++ 1 file changed, 29 insertions(+) create mode 100644 configs/am62px_evm_r5_ethboot_defconfig diff --git a/configs/am62px_evm_r5_ethboot_defconfig b/configs/am62px_evm_r5_ethboot_defconfig new file mode 100644 index 00000000000..dfd944ad7c0 --- /dev/null +++ b/configs/am62px_evm_r5_ethboot_defconfig @@ -0,0 +1,29 @@ +#include + +CONFIG_ARM=y +CONFIG_ARCH_K3=y +CONFIG_SOC_K3_AM62P5=y +CONFIG_TARGET_AM62P5_R5_EVM=y +CONFIG_DEFAULT_DEVICE_TREE="k3-am62p5-r5-sk" +CONFIG_NET=y +CONFIG_SPL_BOARD_INIT=y +CONFIG_SPL_DMA=y +CONFIG_SPL_ENV_SUPPORT=y +CONFIG_SPL_ETH=y +CONFIG_SPL_I2C=y +CONFIG_SPL_NET=y +CONFIG_SPL_NET_VCI_STRING="AM62PX U-Boot R5 SPL" +CONFIG_SPL_DRIVERS_MISC=y +CONFIG_TI_AM65_CPSW_NUSS=y +CONFIG_TI_K3_NAVSS_UDMA=y +CONFIG_SPL_SPI=n +CONFIG_SPL_MMC=n +CONFIG_SPL_MTD_LOAD=n +CONFIG_SPL_NAND_SPI_SUPPORT=n +CONFIG_SPL_DM_DEVICE_REMOVE=n +CONFIG_DM_MTD=n +CONFIG_MTD_SPI_NAND=n +CONFIG_DM_SPI_FLASH=n +CONFIG_SPI=n +CONFIG_DM_SPI=n +CONFIG_CADENCE_QSPI=n -- cgit v1.2.3 From c1f1d28c44543dc0fd74653215e25f5153ddd398 Mon Sep 17 00:00:00 2001 From: Chintan Vankar Date: Thu, 31 Jul 2025 13:29:48 +0530 Subject: configs: am62px_evm_a53_ethboot: Enable configs required for Ethboot Enable config options needed to support Ethernet boot on SK-AM62P-LP. Signed-off-by: Chintan Vankar --- configs/am62px_evm_a53_ethboot_defconfig | 13 +++++++++++++ 1 file changed, 13 insertions(+) create mode 100644 configs/am62px_evm_a53_ethboot_defconfig diff --git a/configs/am62px_evm_a53_ethboot_defconfig b/configs/am62px_evm_a53_ethboot_defconfig new file mode 100644 index 00000000000..57da40d4b2e --- /dev/null +++ b/configs/am62px_evm_a53_ethboot_defconfig @@ -0,0 +1,13 @@ +#include + +CONFIG_ARM=y +CONFIG_ARCH_K3=y +CONFIG_SOC_K3_AM62P5=y +CONFIG_TARGET_AM62P5_A53_EVM=y +CONFIG_DEFAULT_DEVICE_TREE="ti/k3-am62p5-sk" +CONFIG_SPL_STACK_R_ADDR=0x82000000 +CONFIG_SPL_DRIVERS_MISC=y +CONFIG_SPL_DMA=y +CONFIG_SPL_ETH=y +CONFIG_SPL_NET=y +CONFIG_SPL_NET_VCI_STRING="AM62PX U-Boot A53 SPL" -- cgit v1.2.3 From a02009f3a816e7de42fccff895397906304290ef Mon Sep 17 00:00:00 2001 From: Chintan Vankar Date: Thu, 31 Jul 2025 13:29:49 +0530 Subject: arm: mach-k3: j722s: Update SoC autogenerated data to enable Ethernet boot Update dev-data and clk-data to include CPSW device which is required to enable Ethernet boot. Signed-off-by: Chintan Vankar --- arch/arm/mach-k3/r5/j722s/clk-data.c | 50 ++++++++++++++++++++++++++++-------- arch/arm/mach-k3/r5/j722s/dev-data.c | 34 ++++++++++++------------ 2 files changed, 56 insertions(+), 28 deletions(-) diff --git a/arch/arm/mach-k3/r5/j722s/clk-data.c b/arch/arm/mach-k3/r5/j722s/clk-data.c index b4f27af333d..238d57d0aa0 100644 --- a/arch/arm/mach-k3/r5/j722s/clk-data.c +++ b/arch/arm/mach-k3/r5/j722s/clk-data.c @@ -5,7 +5,7 @@ * This file is auto generated. Please do not hand edit and report any issues * to Bryan Brattlof . * - * Copyright (C) 2024 Texas Instruments Incorporated - https://www.ti.com/ + * Copyright (C) 2020-2025 Texas Instruments Incorporated - https://www.ti.com/ */ #include @@ -57,9 +57,15 @@ static const char * const clkout0_ctrl_out0_parents[] = { "hsdiv4_16fft_main_2_hsdivout1_clk", }; -static const char * const main_emmcsd0_refclk_sel_out0_parents[] = { - "postdiv4_16ff_main_0_hsdivout5_clk", - "hsdiv4_16fft_main_2_hsdivout2_clk", +static const char * const main_cp_gemac_cpts_clk_sel_out0_parents[] = { + "postdiv4_16ff_main_2_hsdivout5_clk", + "postdiv4_16ff_main_0_hsdivout6_clk", + "board_0_cp_gemac_cpts0_rft_clk_out", + NULL, + "board_0_mcu_ext_refclk0_out", + "board_0_ext_refclk1_out", + NULL, + "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk", }; static const char * const main_emmcsd1_refclk_sel_out0_parents[] = { @@ -94,8 +100,8 @@ static const char * const main_timerclkn_sel_out0_parents[] = { "board_0_cp_gemac_cpts0_rft_clk_out", "hsdiv4_16fft_main_1_hsdivout3_clk", "postdiv4_16ff_main_2_hsdivout6_clk", - NULL, - NULL, + "cpsw_3guss_am67_main_0_cpts_genf0", + "cpsw_3guss_am67_main_0_cpts_genf1", NULL, NULL, NULL, @@ -143,7 +149,12 @@ static const struct clk_data clk_list[] = { CLK_FIXED_RATE("board_0_mmc1_clk_out", 0, 0), CLK_FIXED_RATE("board_0_ospi0_dqs_out", 0, 0), CLK_FIXED_RATE("board_0_ospi0_lbclko_out", 0, 0), + CLK_FIXED_RATE("board_0_rmii1_ref_clk_out", 0, 0), + CLK_FIXED_RATE("board_0_rmii2_ref_clk_out", 0, 0), CLK_FIXED_RATE("board_0_tck_out", 0, 0), + CLK_FIXED_RATE("cpsw_3guss_am67_main_0_cpts_genf0", 0, 0), + CLK_FIXED_RATE("cpsw_3guss_am67_main_0_cpts_genf1", 0, 0), + CLK_FIXED_RATE("cpsw_3guss_am67_main_0_mdio_mdclk_o", 0, 0), CLK_FIXED_RATE("dmtimer_dmc1ms_main_0_timer_pwm", 0, 0), CLK_FIXED_RATE("emmcsd4ss_main_0_emmcsdss_io_clk_o", 0, 0), CLK_FIXED_RATE("fss_ul_main_0_ospi_0_ospi_oclk_clk", 0, 0), @@ -194,7 +205,7 @@ static const struct clk_data clk_list[] = { CLK_MUX_PLLCTRL("sam62_pll_ctrl_wrap_mcu_0_sysclkout_clk", sam62_pll_ctrl_wrap_mcu_0_sysclkout_clk_parents, 2, 0x4020000, 0), CLK_DIV("sam62_pll_ctrl_wrap_mcu_0_chip_div1_clk_clk", "sam62_pll_ctrl_wrap_mcu_0_sysclkout_clk", 0x4020118, 0, 5, 0, 0), CLK_MUX("clkout0_ctrl_out0", clkout0_ctrl_out0_parents, 2, 0x108010, 0, 1, 0), - CLK_MUX("main_emmcsd0_refclk_sel_out0", main_emmcsd0_refclk_sel_out0_parents, 2, 0x108160, 0, 1, 0), + CLK_MUX("main_cp_gemac_cpts_clk_sel_out0", main_cp_gemac_cpts_clk_sel_out0_parents, 8, 0x108140, 0, 3, 0), CLK_MUX("main_emmcsd1_refclk_sel_out0", main_emmcsd1_refclk_sel_out0_parents, 2, 0x108168, 0, 1, 0), CLK_MUX("main_gtcclk_sel_out0", main_gtcclk_sel_out0_parents, 8, 0x43008030, 0, 3, 0), CLK_MUX("main_ospi_ref_clk_sel_out0", main_ospi_ref_clk_sel_out0_parents, 2, 0x108500, 0, 1, 0), @@ -209,6 +220,24 @@ static const struct clk_data clk_list[] = { }; static const struct dev_clk soc_dev_clk_data[] = { + DEV_CLK(13, 0, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"), + DEV_CLK(13, 3, "main_cp_gemac_cpts_clk_sel_out0"), + DEV_CLK(13, 4, "postdiv4_16ff_main_2_hsdivout5_clk"), + DEV_CLK(13, 5, "postdiv4_16ff_main_0_hsdivout6_clk"), + DEV_CLK(13, 6, "board_0_cp_gemac_cpts0_rft_clk_out"), + DEV_CLK(13, 8, "board_0_mcu_ext_refclk0_out"), + DEV_CLK(13, 9, "board_0_ext_refclk1_out"), + DEV_CLK(13, 11, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"), + DEV_CLK(13, 13, "hsdiv4_16fft_main_2_hsdivout1_clk"), + DEV_CLK(13, 14, "hsdiv4_16fft_main_2_hsdivout1_clk"), + DEV_CLK(13, 15, "hsdiv4_16fft_main_2_hsdivout1_clk"), + DEV_CLK(13, 16, "hsdiv4_16fft_main_2_hsdivout1_clk"), + DEV_CLK(13, 17, "hsdiv4_16fft_main_2_hsdivout1_clk"), + DEV_CLK(13, 19, "hsdiv4_16fft_main_2_hsdivout1_clk"), + DEV_CLK(13, 20, "hsdiv4_16fft_main_2_hsdivout1_clk"), + DEV_CLK(13, 21, "hsdiv4_16fft_main_2_hsdivout1_clk"), + DEV_CLK(13, 22, "board_0_rmii1_ref_clk_out"), + DEV_CLK(13, 23, "board_0_rmii2_ref_clk_out"), DEV_CLK(16, 0, "hsdiv4_16fft_main_0_hsdivout1_clk"), DEV_CLK(16, 1, "hsdiv4_16fft_main_0_hsdivout2_clk"), DEV_CLK(16, 2, "hsdiv4_16fft_main_0_hsdivout3_clk"), @@ -233,10 +262,8 @@ static const struct dev_clk soc_dev_clk_data[] = { DEV_CLK(36, 10, "board_0_cp_gemac_cpts0_rft_clk_out"), DEV_CLK(36, 11, "hsdiv4_16fft_main_1_hsdivout3_clk"), DEV_CLK(36, 12, "postdiv4_16ff_main_2_hsdivout6_clk"), - DEV_CLK(57, 1, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"), - DEV_CLK(57, 2, "main_emmcsd0_refclk_sel_out0"), - DEV_CLK(57, 3, "postdiv4_16ff_main_0_hsdivout5_clk"), - DEV_CLK(57, 4, "hsdiv4_16fft_main_2_hsdivout2_clk"), + DEV_CLK(36, 13, "cpsw_3guss_am67_main_0_cpts_genf0"), + DEV_CLK(36, 14, "cpsw_3guss_am67_main_0_cpts_genf1"), DEV_CLK(58, 0, "main_emmcsd1_io_clklb_sel_out0"), DEV_CLK(58, 1, "board_0_mmc1_clklb_out"), DEV_CLK(58, 2, "board_0_mmc1_clk_out"), @@ -279,6 +306,7 @@ static const struct dev_clk soc_dev_clk_data[] = { DEV_CLK(157, 62, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"), DEV_CLK(157, 74, "mshsi2c_main_0_porscl"), DEV_CLK(157, 135, "sam62_pll_ctrl_wrap_mcu_0_sysclkout_clk"), + DEV_CLK(157, 140, "cpsw_3guss_am67_main_0_mdio_mdclk_o"), DEV_CLK(157, 143, "emmcsd4ss_main_0_emmcsdss_io_clk_o"), DEV_CLK(157, 145, "emmcsd4ss_main_0_emmcsdss_io_clk_o"), DEV_CLK(157, 157, "fss_ul_main_0_ospi_0_ospi_oclk_clk"), diff --git a/arch/arm/mach-k3/r5/j722s/dev-data.c b/arch/arm/mach-k3/r5/j722s/dev-data.c index 59176c98999..d6832266884 100644 --- a/arch/arm/mach-k3/r5/j722s/dev-data.c +++ b/arch/arm/mach-k3/r5/j722s/dev-data.c @@ -5,7 +5,7 @@ * This file is auto generated. Please do not hand edit and report any issues * to Bryan Brattlof . * - * Copyright (C) 2024 Texas Instruments Incorporated - https://www.ti.com/ + * Copyright (C) 2020-2025 Texas Instruments Incorporated - https://www.ti.com/ */ #include "k3-dev.h" @@ -23,16 +23,16 @@ static struct ti_pd soc_pd_list[] = { static struct ti_lpsc soc_lpsc_list[] = { [0] = PSC_LPSC(0, &soc_psc_list[0], &soc_pd_list[0], NULL), - [1] = PSC_LPSC(12, &soc_psc_list[0], &soc_pd_list[0], &soc_lpsc_list[5]), - [2] = PSC_LPSC(13, &soc_psc_list[0], &soc_pd_list[0], &soc_lpsc_list[5]), - [3] = PSC_LPSC(20, &soc_psc_list[0], &soc_pd_list[0], &soc_lpsc_list[7]), - [4] = PSC_LPSC(21, &soc_psc_list[0], &soc_pd_list[0], &soc_lpsc_list[7]), - [5] = PSC_LPSC(23, &soc_psc_list[0], &soc_pd_list[0], &soc_lpsc_list[7]), - [6] = PSC_LPSC(28, &soc_psc_list[0], &soc_pd_list[0], &soc_lpsc_list[7]), - [7] = PSC_LPSC(34, &soc_psc_list[0], &soc_pd_list[0], &soc_lpsc_list[7]), - [8] = PSC_LPSC(53, &soc_psc_list[0], &soc_pd_list[1], &soc_lpsc_list[7]), + [1] = PSC_LPSC(12, &soc_psc_list[0], &soc_pd_list[0], &soc_lpsc_list[4]), + [2] = PSC_LPSC(13, &soc_psc_list[0], &soc_pd_list[0], &soc_lpsc_list[4]), + [3] = PSC_LPSC(21, &soc_psc_list[0], &soc_pd_list[0], &soc_lpsc_list[6]), + [4] = PSC_LPSC(23, &soc_psc_list[0], &soc_pd_list[0], &soc_lpsc_list[6]), + [5] = PSC_LPSC(28, &soc_psc_list[0], &soc_pd_list[0], &soc_lpsc_list[6]), + [6] = PSC_LPSC(34, &soc_psc_list[0], &soc_pd_list[0], &soc_lpsc_list[6]), + [7] = PSC_LPSC(42, &soc_psc_list[0], &soc_pd_list[0], &soc_lpsc_list[6]), + [8] = PSC_LPSC(53, &soc_psc_list[0], &soc_pd_list[1], &soc_lpsc_list[6]), [9] = PSC_LPSC(56, &soc_psc_list[0], &soc_pd_list[2], &soc_lpsc_list[8]), - [10] = PSC_LPSC(72, &soc_psc_list[0], &soc_pd_list[3], &soc_lpsc_list[7]), + [10] = PSC_LPSC(72, &soc_psc_list[0], &soc_pd_list[3], &soc_lpsc_list[6]), [11] = PSC_LPSC(73, &soc_psc_list[0], &soc_pd_list[3], &soc_lpsc_list[10]), [12] = PSC_LPSC(74, &soc_psc_list[0], &soc_pd_list[3], &soc_lpsc_list[11]), }; @@ -43,13 +43,13 @@ static struct ti_dev soc_dev_list[] = { PSC_DEV(61, &soc_lpsc_list[0]), PSC_DEV(178, &soc_lpsc_list[1]), PSC_DEV(179, &soc_lpsc_list[2]), - PSC_DEV(57, &soc_lpsc_list[3]), - PSC_DEV(58, &soc_lpsc_list[4]), - PSC_DEV(161, &soc_lpsc_list[5]), - PSC_DEV(75, &soc_lpsc_list[6]), - PSC_DEV(36, &soc_lpsc_list[7]), - PSC_DEV(102, &soc_lpsc_list[7]), - PSC_DEV(146, &soc_lpsc_list[7]), + PSC_DEV(58, &soc_lpsc_list[3]), + PSC_DEV(161, &soc_lpsc_list[4]), + PSC_DEV(75, &soc_lpsc_list[5]), + PSC_DEV(36, &soc_lpsc_list[6]), + PSC_DEV(102, &soc_lpsc_list[6]), + PSC_DEV(146, &soc_lpsc_list[6]), + PSC_DEV(13, &soc_lpsc_list[7]), PSC_DEV(166, &soc_lpsc_list[8]), PSC_DEV(135, &soc_lpsc_list[9]), PSC_DEV(170, &soc_lpsc_list[10]), -- cgit v1.2.3 From 80b529d8776fe48eb595bc3eaf739751b5bea15c Mon Sep 17 00:00:00 2001 From: Chintan Vankar Date: Thu, 31 Jul 2025 13:29:50 +0530 Subject: board: ti: j722s: evm: Enable cache for J722s Enable cache for J722s to optimize performance of CPU to access data from memory. Reviewed-by: Alexander Sverdlin Signed-off-by: Chintan Vankar --- board/ti/j722s/evm.c | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/board/ti/j722s/evm.c b/board/ti/j722s/evm.c index d2b94913c12..32d767cb7d2 100644 --- a/board/ti/j722s/evm.c +++ b/board/ti/j722s/evm.c @@ -8,6 +8,7 @@ #include #include +#include #include #include #include @@ -15,6 +16,13 @@ #include #include "../common/fdt_ops.h" +#if IS_ENABLED(CONFIG_SPL_BUILD) +void spl_board_init(void) +{ + enable_caches(); +} +#endif + #if defined(CONFIG_XPL_BUILD) void spl_perform_fixups(struct spl_image_info *spl_image) { -- cgit v1.2.3 From d449db6cd7c896d69e2dba2b902797d9b329beef Mon Sep 17 00:00:00 2001 From: Chintan Vankar Date: Thu, 31 Jul 2025 13:29:51 +0530 Subject: configs: j722s_evm_r5_ethboot: Add configs to enable Ethernet boot in R5SPL Add configs to enable Ethernet boot in R5SPL, also disable not required configs to avoid memory limitation. Signed-off-by: Chintan Vankar --- configs/j722s_evm_r5_ethboot_defconfig | 30 ++++++++++++++++++++++++++++++ 1 file changed, 30 insertions(+) create mode 100644 configs/j722s_evm_r5_ethboot_defconfig diff --git a/configs/j722s_evm_r5_ethboot_defconfig b/configs/j722s_evm_r5_ethboot_defconfig new file mode 100644 index 00000000000..fd58485bff2 --- /dev/null +++ b/configs/j722s_evm_r5_ethboot_defconfig @@ -0,0 +1,30 @@ +#include + +CONFIG_ARM=y +CONFIG_ARCH_K3=y +CONFIG_SOC_K3_J722S=y +CONFIG_TARGET_J722S_R5_EVM=y +CONFIG_DEFAULT_DEVICE_TREE="k3-j722s-r5-evm" +CONFIG_NET=y +CONFIG_SPL_DRIVERS_MISC=y +CONFIG_SPL_BOARD_INIT=y +CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x200000 +CONFIG_SPL_DMA=y +CONFIG_SPL_ENV_SUPPORT=y +CONFIG_SPL_ETH=y +CONFIG_SPL_I2C=y +CONFIG_SPL_NET=y +CONFIG_SPL_NET_VCI_STRING="J722S U-Boot R5 SPL" +CONFIG_TI_K3_NAVSS_UDMA=y +CONFIG_TI_AM65_CPSW_NUSS=y +CONFIG_SPL_MMC=n +CONFIG_SPL_SPI=n +CONFIG_SPL_MTD_LOAD=n +CONFIG_SPL_NAND_SPI_SUPPORT=n +CONFIG_SPL_DM_DEVICE_REMOVE=n +CONFIG_DM_MTD=n +CONFIG_MTD_SPI_NAND=n +CONFIG_DM_SPI_FLASH=n +CONFIG_SPI=n +CONFIG_DM_SPI=n +CONFIG_CADENCE_QSPI=n -- cgit v1.2.3 From 9def2b0fc17d5ed1162d6a8fbe9a06ec26557512 Mon Sep 17 00:00:00 2001 From: Chintan Vankar Date: Thu, 31 Jul 2025 13:29:52 +0530 Subject: configs: j722s_evm_a53_ethboot: Enable configs required for Ethernet boot Enable configs required to support Ethernet boot for J722S. Signed-off-by: Chintan Vankar --- configs/j722s_evm_a53_ethboot_defconfig | 13 +++++++++++++ 1 file changed, 13 insertions(+) create mode 100644 configs/j722s_evm_a53_ethboot_defconfig diff --git a/configs/j722s_evm_a53_ethboot_defconfig b/configs/j722s_evm_a53_ethboot_defconfig new file mode 100644 index 00000000000..a5a2a15849c --- /dev/null +++ b/configs/j722s_evm_a53_ethboot_defconfig @@ -0,0 +1,13 @@ +#include + +CONFIG_ARM=y +CONFIG_ARCH_K3=y +CONFIG_SOC_K3_J722S=y +CONFIG_TARGET_J722S_A53_EVM=y +CONFIG_DEFAULT_DEVICE_TREE="ti/k3-j722s-evm" +CONFIG_SPL_STACK_R_ADDR=0x82000000 +CONFIG_SPL_DRIVERS_MISC=y +CONFIG_SPL_DMA=y +CONFIG_SPL_ETH=y +CONFIG_SPL_NET=y +CONFIG_SPL_NET_VCI_STRING="J722S U-Boot A53 SPL" -- cgit v1.2.3 From 8eecd9edb58e57018ce1a9adf9283d88541e974f Mon Sep 17 00:00:00 2001 From: Chintan Vankar Date: Thu, 31 Jul 2025 13:29:53 +0530 Subject: arm: mach-k3: j784s4: Update SoC auto-gen data to enable Ethernet boot Update dev-data and clk-data to include CPSW device which is required to enable Ethernet boot for SK-AM69. Signed-off-by: Chintan Vankar --- arch/arm/mach-k3/r5/j784s4/clk-data.c | 54 +++++++++++++++++++++++++++++++---- arch/arm/mach-k3/r5/j784s4/dev-data.c | 1 + 2 files changed, 50 insertions(+), 5 deletions(-) diff --git a/arch/arm/mach-k3/r5/j784s4/clk-data.c b/arch/arm/mach-k3/r5/j784s4/clk-data.c index 97d969271ec..24780eb6562 100644 --- a/arch/arm/mach-k3/r5/j784s4/clk-data.c +++ b/arch/arm/mach-k3/r5/j784s4/clk-data.c @@ -57,6 +57,25 @@ static const char * const wkup_gpio0_clksel_out0_parents[] = { "j7am_wakeup_16ff_wkup_0_wkup_rcosc_12p5m_clk", }; +static const char * const cpsw2g_cpts_rclk_sel_out0_parents[] = { + "hsdiv4_16fft_main_3_hsdivout1_clk", + "postdiv3_16fft_main_0_hsdivout6_clk", + "board_0_mcu_cpts0_rft_clk_out", + "board_0_cpts0_rft_clk_out", + "board_0_mcu_ext_refclk0_out", + "board_0_ext_refclk1_out", + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + "hsdiv4_16fft_mcu_2_hsdivout1_clk", + "k3_pll_ctrl_wrap_wkup_0_chip_div1_clk_clk", +}; + static const char * const mcu_usart_clksel_out0_parents[] = { "hsdiv4_16fft_mcu_1_hsdivout3_clk", "postdiv3_16fft_main_1_hsdivout5_clk", @@ -132,6 +151,11 @@ static const char * const main_pll_hfosc_sel_out8_parents[] = { "board_0_hfosc1_clk_out", }; +static const char * const mcu_clkout_mux_out0_parents[] = { + "hsdiv4_16fft_mcu_2_hsdivout0_clk", + "hsdiv4_16fft_mcu_2_hsdivout1_clk", +}; + static const char * const usb0_refclk_sel_out0_parents[] = { "gluelogic_hfosc0_clkout", "board_0_hfosc1_clk_out", @@ -142,11 +166,6 @@ static const char * const emmcsd1_lb_clksel_out0_parents[] = { "board_0_mmc1_clk_out", }; -static const char * const mcu_clkout_mux_out0_parents[] = { - "hsdiv4_16fft_mcu_2_hsdivout0_clk", - "hsdiv4_16fft_mcu_2_hsdivout1_clk", -}; - static const char * const k3_pll_ctrl_wrap_main_0_sysclkout_clk_parents[] = { "main_pll_hfosc_sel_out0", "hsdiv4_16fft_main_0_hsdivout0_clk", @@ -201,7 +220,11 @@ static const struct clk_data clk_list[] = { CLK_FIXED_RATE("board_0_hfosc1_clk_out", 0, 0), CLK_FIXED_RATE("board_0_mcu_ospi0_dqs_out", 0, 0), CLK_FIXED_RATE("board_0_mcu_ospi1_dqs_out", 0, 0), + CLK_FIXED_RATE("board_0_mcu_rgmii1_rxc_out", 0, 0), + CLK_FIXED_RATE("board_0_mcu_rmii1_ref_clk_out", 0, 0), CLK_FIXED_RATE("board_0_wkup_i2c0_scl_out", 0, 0), + CLK_FIXED_RATE("cpsw_2guss_mcu_0_mdio_mdclk_o", 0, 0), + CLK_FIXED_RATE("cpsw_2guss_mcu_0_rgmii1_txc_o", 0, 0), CLK_FIXED_RATE("fss_mcu_0_hyperbus1p0_0_hpb_out_clk_n", 0, 0), CLK_FIXED_RATE("fss_mcu_0_hyperbus1p0_0_hpb_out_clk_p", 0, 0), CLK_FIXED_RATE("fss_mcu_0_ospi_0_ospi_oclk_clk", 0, 0), @@ -224,6 +247,7 @@ static const struct clk_data clk_list[] = { CLK_MUX("mcu_ospi_ref_clk_sel_out0", mcu_ospi_ref_clk_sel_out0_parents, 2, 0x40f08030, 0, 1, 0), CLK_MUX("mcu_ospi_ref_clk_sel_out1", mcu_ospi_ref_clk_sel_out1_parents, 2, 0x40f08034, 0, 1, 0), CLK_MUX("wkup_gpio0_clksel_out0", wkup_gpio0_clksel_out0_parents, 4, 0x43008070, 0, 2, 0), + CLK_MUX("cpsw2g_cpts_rclk_sel_out0", cpsw2g_cpts_rclk_sel_out0_parents, 16, 0x40f08050, 8, 4, 0), CLK_MUX("mcu_usart_clksel_out0", mcu_usart_clksel_out0_parents, 2, 0x40f081c0, 0, 1, 0), CLK_MUX("wkup_i2c_mcupll_bypass_out0", wkup_i2c_mcupll_bypass_out0_parents, 2, 0x43008060, 0, 1, 0), CLK_MUX("wkup_usart_clksel_out0", wkup_usart_clksel_out0_parents, 2, 0x43008064, 0, 1, 0), @@ -317,6 +341,24 @@ static const struct dev_clk soc_dev_clk_data[] = { DEV_CLK(61, 15, "hsdiv4_16fft_mcu_2_hsdivout1_clk"), DEV_CLK(61, 16, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"), DEV_CLK(61, 17, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"), + DEV_CLK(63, 0, "k3_pll_ctrl_wrap_wkup_0_chip_div1_clk_clk"), + DEV_CLK(63, 3, "cpsw2g_cpts_rclk_sel_out0"), + DEV_CLK(63, 4, "hsdiv4_16fft_main_3_hsdivout1_clk"), + DEV_CLK(63, 5, "postdiv3_16fft_main_0_hsdivout6_clk"), + DEV_CLK(63, 6, "board_0_mcu_cpts0_rft_clk_out"), + DEV_CLK(63, 7, "board_0_cpts0_rft_clk_out"), + DEV_CLK(63, 8, "board_0_mcu_ext_refclk0_out"), + DEV_CLK(63, 9, "board_0_ext_refclk1_out"), + DEV_CLK(63, 18, "hsdiv4_16fft_mcu_2_hsdivout1_clk"), + DEV_CLK(63, 19, "k3_pll_ctrl_wrap_wkup_0_chip_div1_clk_clk"), + DEV_CLK(63, 20, "hsdiv4_16fft_mcu_2_hsdivout0_clk"), + DEV_CLK(63, 21, "hsdiv4_16fft_mcu_2_hsdivout0_clk"), + DEV_CLK(63, 22, "hsdiv4_16fft_mcu_2_hsdivout0_clk"), + DEV_CLK(63, 24, "board_0_mcu_rgmii1_rxc_out"), + DEV_CLK(63, 27, "hsdiv4_16fft_mcu_2_hsdivout0_clk"), + DEV_CLK(63, 28, "hsdiv4_16fft_mcu_2_hsdivout0_clk"), + DEV_CLK(63, 29, "hsdiv4_16fft_mcu_2_hsdivout0_clk"), + DEV_CLK(63, 30, "board_0_mcu_rmii1_ref_clk_out"), DEV_CLK(78, 0, "postdiv3_16fft_main_0_hsdivout8_clk"), DEV_CLK(78, 1, "hsdiv4_16fft_main_0_hsdivout2_clk"), DEV_CLK(78, 2, "hsdiv4_16fft_main_0_hsdivout3_clk"), @@ -353,10 +395,12 @@ static const struct dev_clk soc_dev_clk_data[] = { DEV_CLK(157, 176, "hsdiv4_16fft_mcu_2_hsdivout1_clk"), DEV_CLK(157, 179, "fss_mcu_0_hyperbus1p0_0_hpb_out_clk_p"), DEV_CLK(157, 180, "fss_mcu_0_hyperbus1p0_0_hpb_out_clk_n"), + DEV_CLK(157, 190, "cpsw_2guss_mcu_0_mdio_mdclk_o"), DEV_CLK(157, 224, "fss_mcu_0_ospi_0_ospi_oclk_clk"), DEV_CLK(157, 226, "fss_mcu_0_ospi_0_ospi_oclk_clk"), DEV_CLK(157, 228, "fss_mcu_0_ospi_1_ospi_oclk_clk"), DEV_CLK(157, 230, "fss_mcu_0_ospi_1_ospi_oclk_clk"), + DEV_CLK(157, 233, "cpsw_2guss_mcu_0_rgmii1_txc_o"), DEV_CLK(157, 239, "k3_pll_ctrl_wrap_wkup_0_chip_div1_clk_clk"), DEV_CLK(157, 243, "emmcsd4ss_main_0_emmcsdss_io_clk_o"), DEV_CLK(157, 245, "emmcsd4ss_main_0_emmcsdss_io_clk_o"), diff --git a/arch/arm/mach-k3/r5/j784s4/dev-data.c b/arch/arm/mach-k3/r5/j784s4/dev-data.c index b32b4ba9588..19901821225 100644 --- a/arch/arm/mach-k3/r5/j784s4/dev-data.c +++ b/arch/arm/mach-k3/r5/j784s4/dev-data.c @@ -54,6 +54,7 @@ static struct ti_lpsc soc_lpsc_list[] = { }; static struct ti_dev soc_dev_list[] = { + PSC_DEV(63, &soc_lpsc_list[0]), PSC_DEV(35, &soc_lpsc_list[0]), PSC_DEV(160, &soc_lpsc_list[0]), PSC_DEV(161, &soc_lpsc_list[0]), -- cgit v1.2.3 From 721d5c30f5704c78e7e45fa0234c8096a1bcd683 Mon Sep 17 00:00:00 2001 From: Chintan Vankar Date: Thu, 31 Jul 2025 13:29:54 +0530 Subject: arm: mach-k3: j784s4_spl: Alias Ethernet boot to CPGMAC This is required to enable spl_net boot on SK-AM69. Signed-off-by: Chintan Vankar --- arch/arm/mach-k3/include/mach/j784s4_spl.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm/mach-k3/include/mach/j784s4_spl.h b/arch/arm/mach-k3/include/mach/j784s4_spl.h index d481a46c675..3814dc95d01 100644 --- a/arch/arm/mach-k3/include/mach/j784s4_spl.h +++ b/arch/arm/mach-k3/include/mach/j784s4_spl.h @@ -44,4 +44,6 @@ #define K3_PRIMARY_BOOTMODE 0x0 #define K3_BACKUP_BOOTMODE 0x1 +#define BOOT_DEVICE_CPGMAC 0x04 + #endif -- cgit v1.2.3 From 02b2a3277116d80137e62cb931dd365eda54790c Mon Sep 17 00:00:00 2001 From: Chintan Vankar Date: Thu, 31 Jul 2025 13:29:55 +0530 Subject: configs: am69_sk_r5_ethboot: Add configs to enable Ethernet boot in R5SPL Add configs required to enable Ethernet boot for SK-AM69. Signed-off-by: Chintan Vankar --- configs/am69_sk_r5_ethboot_defconfig | 15 +++++++++++++++ 1 file changed, 15 insertions(+) create mode 100644 configs/am69_sk_r5_ethboot_defconfig diff --git a/configs/am69_sk_r5_ethboot_defconfig b/configs/am69_sk_r5_ethboot_defconfig new file mode 100644 index 00000000000..c85aa72cf04 --- /dev/null +++ b/configs/am69_sk_r5_ethboot_defconfig @@ -0,0 +1,15 @@ +#include + +CONFIG_ARM=y +CONFIG_ARCH_K3=y +CONFIG_SOC_K3_J784S4=y +CONFIG_TARGET_J784S4_R5_EVM=y +CONFIG_DEFAULT_DEVICE_TREE="k3-am69-r5-sk" +CONFIG_SPL_ETH=y +CONFIG_SPL_NET=y +CONFIG_SPL_NET_VCI_STRING="AM69 U-Boot R5 SPL" +CONFIG_TI_AM65_CPSW_NUSS=y +CONFIG_TI_I2C_BOARD_DETECT=y +CONFIG_NET_RANDOM_ETHADDR=y +CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y +CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x84000000 -- cgit v1.2.3 From 841d3d06ce2c1fb9d7a785bd7df5a1b6b70003bb Mon Sep 17 00:00:00 2001 From: Chintan Vankar Date: Thu, 31 Jul 2025 13:29:56 +0530 Subject: configs: am69_sk_a72_ethboot: Add configs to enable Ethernet boot Add configs required to enable Ethernet boot for SK-AM69. Signed-off-by: Chintan Vankar --- configs/am69_sk_a72_ethboot_defconfig | 11 +++++++++++ 1 file changed, 11 insertions(+) create mode 100644 configs/am69_sk_a72_ethboot_defconfig diff --git a/configs/am69_sk_a72_ethboot_defconfig b/configs/am69_sk_a72_ethboot_defconfig new file mode 100644 index 00000000000..676db01b2e2 --- /dev/null +++ b/configs/am69_sk_a72_ethboot_defconfig @@ -0,0 +1,11 @@ +#include + +CONFIG_ARM=y +CONFIG_ARCH_K3=y +CONFIG_SOC_K3_J784S4=y +CONFIG_TARGET_J784S4_A72_EVM=y +CONFIG_DEFAULT_DEVICE_TREE="ti/k3-am69-sk" +CONFIG_SPL_ETH=y +CONFIG_SPL_NET=y +CONFIG_SPL_NET_VCI_STRING="AM69 U-Boot A72 SPL" +CONFIG_SYS_K3_SPL_ATF=y -- cgit v1.2.3 From afbed1ba2f8776b06ef821212b14a3e34bdcd2bd Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Tue, 12 Aug 2025 14:46:10 -0300 Subject: env: fat: Add support for NVME Add support for retrieving the FAT environment from an NVME device, the same way it can be retrieved from MMC, SCSI, or VIRTIO. To use the FAT environment from an NVME device, pass CONFIG_ENV_FAT_INTERFACE="nvme" in the defconfig. Signed-off-by: Fabio Estevam --- env/fat.c | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/env/fat.c b/env/fat.c index 65ee1c8e086..412d95dc305 100644 --- a/env/fat.c +++ b/env/fat.c @@ -14,8 +14,10 @@ #include #include #include +#include #include #include +#include #include #include #include @@ -136,6 +138,14 @@ static int env_fat_load(void) if (!strcmp(ifname, "virtio")) virtio_init(); #endif +#if defined(CONFIG_NVME) + if (!strcmp(ifname, "nvme")) { + if (IS_ENABLED(CONFIG_PCI)) + pci_init(); + + nvme_scan_namespace(); + } +#endif #endif part = blk_get_device_part_str(ifname, dev_and_part, &dev_desc, &info, 1); -- cgit v1.2.3 From 7b21bf086053679c5ef1ea612072a78018370281 Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Tue, 12 Aug 2025 14:46:11 -0300 Subject: env: ext4: Add support for NVME Add support for retrieving the EXT4 environment from an NVME device, the same way it can be retrieved from MMC, SCSI, or VIRTIO. To use the EXT4 environment from an NVME device, pass CONFIG_ENV_EXT4_INTERFACE="nvme" in the defconfig. Signed-off-by: Fabio Estevam --- env/ext4.c | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/env/ext4.c b/env/ext4.c index d92c844ea6c..c8122b4d22c 100644 --- a/env/ext4.c +++ b/env/ext4.c @@ -22,6 +22,7 @@ #include #include +#include #include #include #include @@ -30,6 +31,7 @@ #include #include #include +#include #include #include #include @@ -156,6 +158,14 @@ static int env_ext4_load(void) virtio_init(); #endif +#if defined(CONFIG_NVME) + if (!strcmp(ifname, "nvme")) { + if (IS_ENABLED(CONFIG_PCI)) + pci_init(); + + nvme_scan_namespace(); + } +#endif part = blk_get_device_part_str(ifname, dev_and_part, &dev_desc, &info, 1); if (part < 0) -- cgit v1.2.3 From 82444e3ecd0ea8404ed6fd1dd3710bfd8d641f52 Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Tue, 12 Aug 2025 14:46:12 -0300 Subject: env: fat: Standardize the interface type check Make the interface type check consistent among the other interface types by checking it agains the ifname string. The ifname string contains the string returned by env_fat_get_intf(), which returns the CONFIG_ENV_FAT_INTERFACE value. No functional change. Signed-off-by: Fabio Estevam --- env/fat.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/env/fat.c b/env/fat.c index 412d95dc305..58c279ff769 100644 --- a/env/fat.c +++ b/env/fat.c @@ -131,7 +131,7 @@ static int env_fat_load(void) #endif #ifndef CONFIG_XPL_BUILD #if defined(CONFIG_AHCI) || defined(CONFIG_SCSI) - if (!strcmp(CONFIG_ENV_FAT_INTERFACE, "scsi")) + if (!strcmp(ifname, "scsi")) scsi_scan(true); #endif #if defined(CONFIG_VIRTIO) -- cgit v1.2.3 From 2b751d42c35c36f7e3739d7bc7064f014e1263c7 Mon Sep 17 00:00:00 2001 From: Andrew Goodbody Date: Tue, 12 Aug 2025 11:26:06 +0100 Subject: sound: maxim_codec: Fix coding mistake In maxim_i2c_read the code mistakenly just returned the return value from dm_i2c_read leaving the following code unreachable. Instead assign ret to be the return value from dm_i2c_read so that the following code can operate as expected. This issue was found by Smatch. Signed-off-by: Andrew Goodbody --- drivers/sound/maxim_codec.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/sound/maxim_codec.c b/drivers/sound/maxim_codec.c index 98f094c0e9a..505a739ad7d 100644 --- a/drivers/sound/maxim_codec.c +++ b/drivers/sound/maxim_codec.c @@ -45,7 +45,7 @@ unsigned int maxim_i2c_read(struct maxim_priv *priv, unsigned int reg, { int ret; - return dm_i2c_read(priv->dev, reg, data, 1); + ret = dm_i2c_read(priv->dev, reg, data, 1); if (ret != 0) { debug("%s: Error while reading register %#04x\n", __func__, reg); -- cgit v1.2.3 From e4507f4a0a7ac3b5346934df19c2daed626cc404 Mon Sep 17 00:00:00 2001 From: Maxim Kochetkov Date: Wed, 13 Aug 2025 08:54:32 +0300 Subject: serial-uclass: set GD_FLG_SERIAL_READY only when cur_serial_dev is assigned serial_find_console_or_panic() may left cur_serial_dev unassigned if REQUIRE_SERIAL_CONSOLE is not set. Setting GD_FLG_SERIAL_READY in this situation confuses serial console code. It tries to use unassigned driver instead of debug port and stops printing. So check cur_serial_dev before setting GD_FLG_SERIAL_READY to allow console to keep printing via debug port. Signed-off-by: Maxim Kochetkov --- drivers/serial/serial-uclass.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/serial/serial-uclass.c b/drivers/serial/serial-uclass.c index a08678dde4e..7b381ca12a0 100644 --- a/drivers/serial/serial-uclass.c +++ b/drivers/serial/serial-uclass.c @@ -191,7 +191,8 @@ int serial_init(void) { #if CONFIG_IS_ENABLED(SERIAL_PRESENT) serial_find_console_or_panic(); - gd->flags |= GD_FLG_SERIAL_READY; + if (gd->cur_serial_dev) + gd->flags |= GD_FLG_SERIAL_READY; if (IS_ENABLED(CONFIG_OF_SERIAL_BAUD)) { int ret = 0; -- cgit v1.2.3 From 18d0cee4e065a01fb3649cc6e1502254e68d50c6 Mon Sep 17 00:00:00 2001 From: Leo Yu-Chi Liang Date: Wed, 13 Aug 2025 14:16:35 +0800 Subject: common: spl: fix compilation warning Explicitly specify the type by replacing macro with variable to fix the possible compilation warning. Signed-off-by: Leo Yu-Chi Liang --- common/spl/spl.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/common/spl/spl.c b/common/spl/spl.c index ed443c645a7..55ad497c86d 100644 --- a/common/spl/spl.c +++ b/common/spl/spl.c @@ -278,8 +278,8 @@ void spl_set_header_raw_uboot(struct spl_image_info *spl_image) } else { spl_image->entry_point = CONFIG_SYS_UBOOT_START; spl_image->load_addr = CONFIG_TEXT_BASE; - log_debug("Default load addr %x (u_boot_pos=%lx)\n", - CONFIG_TEXT_BASE, u_boot_pos); + log_debug("Default load addr %lx (u_boot_pos=%lx)\n", + spl_image->load_addr, u_boot_pos); } spl_image->os = IH_OS_U_BOOT; spl_image->name = xpl_name(xpl_next_phase()); -- cgit v1.2.3 From 29ce50acbb40d64aabf789640a2866a9f71aefa6 Mon Sep 17 00:00:00 2001 From: John Ma Date: Wed, 13 Aug 2025 14:31:16 -0700 Subject: board: phytec: common: k3: Making setup_mac_from_eeprom optional Making the setup_mac_from_eeprom optional for boards without CONFIG_PHYTEC_SOM_DETECTION_BLOCKS. Signed-off-by: John Ma Reviewed-by: Wadim Egorov --- board/phytec/common/k3/board.c | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/board/phytec/common/k3/board.c b/board/phytec/common/k3/board.c index 7f34d71d530..647f93a1d7a 100644 --- a/board/phytec/common/k3/board.c +++ b/board/phytec/common/k3/board.c @@ -176,6 +176,7 @@ static void boot_targets_setup(void) env_set("boot_targets", boot_targets); } +#if IS_ENABLED(CONFIG_PHYTEC_SOM_DETECTION_BLOCKS) static void setup_mac_from_eeprom(void) { struct phytec_api3_element *block_element; @@ -197,13 +198,15 @@ static void setup_mac_from_eeprom(void) } } } +#endif int board_late_init(void) { boot_targets_setup(); - if (IS_ENABLED(CONFIG_PHYTEC_SOM_DETECTION_BLOCKS)) - setup_mac_from_eeprom(); +#if IS_ENABLED(CONFIG_PHYTEC_SOM_DETECTION_BLOCKS) + setup_mac_from_eeprom(); +#endif #if IS_ENABLED(CONFIG_EFI_HAVE_CAPSULE_SUPPORT) configure_capsule_updates(); -- cgit v1.2.3 From 15642829127cd503838f28254a1f3e080103ca4b Mon Sep 17 00:00:00 2001 From: Hari Nagalla Date: Wed, 13 Aug 2025 16:47:05 -0500 Subject: remoteproc: k3-r5: Add support for single cpu mode Add early boot support for AM64 single cpu mode configuration. In single CPU mode the 2nd core of the R5F cluster can't be used or unavailable. Signed-off-by: Hari Nagalla --- drivers/remoteproc/ti_k3_r5f_rproc.c | 11 +++++++++-- 1 file changed, 9 insertions(+), 2 deletions(-) diff --git a/drivers/remoteproc/ti_k3_r5f_rproc.c b/drivers/remoteproc/ti_k3_r5f_rproc.c index 3a25ef6bf87..48401bc6eb6 100644 --- a/drivers/remoteproc/ti_k3_r5f_rproc.c +++ b/drivers/remoteproc/ti_k3_r5f_rproc.c @@ -233,7 +233,7 @@ static int k3_r5f_prepare(struct udevice *dev) dev_dbg(dev, "%s\n", __func__); - if (cluster->mode == CLUSTER_MODE_LOCKSTEP) + if ((cluster->mode == CLUSTER_MODE_LOCKSTEP) || (cluster->mode == CLUSTER_MODE_SINGLECPU)) ret = k3_r5f_lockstep_release(cluster); else ret = k3_r5f_split_release(core); @@ -269,6 +269,13 @@ static int k3_r5f_core_sanity_check(struct k3_r5f_core *core) return -EINVAL; } + if (cluster->mode == CLUSTER_MODE_SINGLECPU && !is_primary_core(core)) { + dev_err(core->dev, + "Invalid op: Trying to start secondary core %d in single CPU mode\n", + core->tsp.proc_id); + return -EINVAL; + } + if (cluster->mode == CLUSTER_MODE_SPLIT && !is_primary_core(core)) { if (!core->cluster->cores[0]->in_use) { dev_err(core->dev, @@ -768,7 +775,7 @@ static void k3_r5f_core_adjust_tcm_sizes(struct k3_r5f_core *core) { struct k3_r5f_cluster *cluster = core->cluster; - if (cluster->mode == CLUSTER_MODE_LOCKSTEP) + if ((cluster->mode == CLUSTER_MODE_LOCKSTEP) || (cluster->mode == CLUSTER_MODE_SINGLECPU)) return; if (!core->ipdata->tcm_is_double) -- cgit v1.2.3 From 55014ce40e29fc4a8d5ec146b02ea0c660b03087 Mon Sep 17 00:00:00 2001 From: Philip Molloy Date: Thu, 14 Aug 2025 13:28:13 +0000 Subject: mach-sc5xx: generate U-Boot proper in ADI ldr format Generating an ldr boot stream containing U-Boot Proper was never added to U-Boot because it is done by the ADI Yocto layer. Add it to U-Boot to support projects that do not use that layer. Signed-off-by: Philip Molloy --- arch/arm/mach-sc5xx/config.mk | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm/mach-sc5xx/config.mk b/arch/arm/mach-sc5xx/config.mk index e7e4c9a1181..266d2e3a777 100644 --- a/arch/arm/mach-sc5xx/config.mk +++ b/arch/arm/mach-sc5xx/config.mk @@ -12,5 +12,7 @@ ifdef CONFIG_XPL_BUILD INPUTS-y += $(obj)/u-boot-spl.ldr endif +INPUTS-y += u-boot.ldr + LDR_FLAGS += --bcode=$(CONFIG_SC_BOOT_MODE) LDR_FLAGS += --use-vmas -- cgit v1.2.3 From 2792cbf5d281b519692c546849638b2141046a4e Mon Sep 17 00:00:00 2001 From: Anshul Dalal Date: Thu, 14 Aug 2025 20:51:43 +0530 Subject: remoteproc: k3: update compatible for am654 syscon The existing compatible name for U-Boot's k3 system controller driver i.e "ti,am625-system-controller" has been added to linux[1] device-tree. This compatible in kernel is meant for configuring the Control Module registers (CTRL_MMR0). However in U-Boot, the matching driver was being used to load the system firmware on the secure M-cores by the R5 SPL and therefore must be updated to a different compatible to avoid conflicts. Therefore, this patch renames all references of the compatible to "ti,am654-tisci-rproc-r5". The "-r5" is appended so as to avoid any future conflicts since r5 specific compatibles should only be useful for U-Boot. [1]: 5959618631fe ("dt-bindings: mfd: ti,j721e-system-controller: Add compatible string for AM654") https://lore.kernel.org/r/20250421214620.3770172-2-afd@ti.com Signed-off-by: Anshul Dalal --- arch/arm/dts/k3-am62-r5-lp-sk.dts | 2 +- arch/arm/dts/k3-am625-r5-beagleplay.dts | 2 +- arch/arm/dts/k3-am625-r5-phycore-som-2gb.dts | 2 +- arch/arm/dts/k3-am625-r5-sk.dts | 2 +- arch/arm/dts/k3-am625-verdin-r5.dts | 2 +- arch/arm/dts/k3-am62a7-r5-phycore-som-2gb.dts | 2 +- arch/arm/dts/k3-am62a7-r5-sk.dts | 2 +- arch/arm/dts/k3-am62p5-r5-sk.dts | 2 +- arch/arm/dts/k3-am62p5-verdin-r5.dts | 2 +- arch/arm/dts/k3-am642-r5-evm.dts | 2 +- arch/arm/dts/k3-am642-r5-phycore-som-2gb.dts | 2 +- arch/arm/dts/k3-am642-r5-sk.dts | 2 +- arch/arm/dts/k3-am654-r5-base-board.dts | 2 +- arch/arm/dts/k3-am67a-r5-beagley-ai.dts | 2 +- arch/arm/dts/k3-j7200-r5-common-proc-board.dts | 2 +- arch/arm/dts/k3-j721e-r5.dtsi | 2 +- arch/arm/dts/k3-j721s2-r5.dtsi | 2 +- arch/arm/dts/k3-j722s-r5-evm.dts | 2 +- arch/arm/dts/k3-j784s4-r5.dtsi | 2 +- doc/device-tree-bindings/power/ti,sci-pm-domain.txt | 2 +- doc/device-tree-bindings/remoteproc/k3-system-controller.txt | 4 ++-- doc/device-tree-bindings/reset/ti,sci-reset.txt | 2 +- drivers/remoteproc/k3_system_controller.c | 2 +- 23 files changed, 24 insertions(+), 24 deletions(-) diff --git a/arch/arm/dts/k3-am62-r5-lp-sk.dts b/arch/arm/dts/k3-am62-r5-lp-sk.dts index 135e8d49b91..95cd9b707c7 100644 --- a/arch/arm/dts/k3-am62-r5-lp-sk.dts +++ b/arch/arm/dts/k3-am62-r5-lp-sk.dts @@ -64,7 +64,7 @@ &cbass_main { sysctrler: sysctrler { - compatible = "ti,am654-system-controller"; + compatible = "ti,am654-tisci-rproc-r5"; mboxes= <&secure_proxy_main 1>, <&secure_proxy_main 0>, <&secure_proxy_sa3 0>; diff --git a/arch/arm/dts/k3-am625-r5-beagleplay.dts b/arch/arm/dts/k3-am625-r5-beagleplay.dts index f4b2cd8904e..bba69871fd2 100644 --- a/arch/arm/dts/k3-am625-r5-beagleplay.dts +++ b/arch/arm/dts/k3-am625-r5-beagleplay.dts @@ -70,7 +70,7 @@ &cbass_main { sysctrler: sysctrler { - compatible = "ti,am654-system-controller"; + compatible = "ti,am654-tisci-rproc-r5"; mboxes= <&secure_proxy_main 1>, <&secure_proxy_main 0>, <&secure_proxy_sa3 0>; mbox-names = "tx", "rx", "boot_notify"; bootph-pre-ram; diff --git a/arch/arm/dts/k3-am625-r5-phycore-som-2gb.dts b/arch/arm/dts/k3-am625-r5-phycore-som-2gb.dts index 7132fae36fa..03dc81a4afa 100644 --- a/arch/arm/dts/k3-am625-r5-phycore-som-2gb.dts +++ b/arch/arm/dts/k3-am625-r5-phycore-som-2gb.dts @@ -69,7 +69,7 @@ &cbass_main { sysctrler: sysctrler { - compatible = "ti,am654-system-controller"; + compatible = "ti,am654-tisci-rproc-r5"; mboxes= <&secure_proxy_main 1>, <&secure_proxy_main 0>, <&secure_proxy_sa3 0>; mbox-names = "tx", "rx", "boot_notify"; bootph-pre-ram; diff --git a/arch/arm/dts/k3-am625-r5-sk.dts b/arch/arm/dts/k3-am625-r5-sk.dts index 34c501dd51b..67589f941ba 100644 --- a/arch/arm/dts/k3-am625-r5-sk.dts +++ b/arch/arm/dts/k3-am625-r5-sk.dts @@ -64,7 +64,7 @@ &cbass_main { sysctrler: sysctrler { - compatible = "ti,am654-system-controller"; + compatible = "ti,am654-tisci-rproc-r5"; mboxes= <&secure_proxy_main 1>, <&secure_proxy_main 0>, <&secure_proxy_sa3 0>; mbox-names = "tx", "rx", "boot_notify"; bootph-pre-ram; diff --git a/arch/arm/dts/k3-am625-verdin-r5.dts b/arch/arm/dts/k3-am625-verdin-r5.dts index 39e8ab8158e..fb431c96337 100644 --- a/arch/arm/dts/k3-am625-verdin-r5.dts +++ b/arch/arm/dts/k3-am625-verdin-r5.dts @@ -53,7 +53,7 @@ &cbass_main { sysctrler: sysctrler { - compatible = "ti,am654-system-controller"; + compatible = "ti,am654-tisci-rproc-r5"; mboxes= <&secure_proxy_main 1>, <&secure_proxy_main 0>, <&secure_proxy_sa3 0>; mbox-names = "tx", "rx", "boot_notify"; bootph-pre-ram; diff --git a/arch/arm/dts/k3-am62a7-r5-phycore-som-2gb.dts b/arch/arm/dts/k3-am62a7-r5-phycore-som-2gb.dts index 63b7864a469..96860e80e9a 100644 --- a/arch/arm/dts/k3-am62a7-r5-phycore-som-2gb.dts +++ b/arch/arm/dts/k3-am62a7-r5-phycore-som-2gb.dts @@ -70,7 +70,7 @@ }; sysctrler: sysctrler { - compatible = "ti,am654-system-controller"; + compatible = "ti,am654-tisci-rproc-r5"; mboxes= <&secure_proxy_main 1>, <&secure_proxy_main 0>, <&sa3_secproxy 0>; diff --git a/arch/arm/dts/k3-am62a7-r5-sk.dts b/arch/arm/dts/k3-am62a7-r5-sk.dts index 49e62533a95..64923c2c710 100644 --- a/arch/arm/dts/k3-am62a7-r5-sk.dts +++ b/arch/arm/dts/k3-am62a7-r5-sk.dts @@ -63,7 +63,7 @@ &cbass_main { sysctrler: sysctrler { - compatible = "ti,am654-system-controller"; + compatible = "ti,am654-tisci-rproc-r5"; mboxes= <&secure_proxy_main 1>, <&secure_proxy_main 0>, <&secure_proxy_sa3 0>; diff --git a/arch/arm/dts/k3-am62p5-r5-sk.dts b/arch/arm/dts/k3-am62p5-r5-sk.dts index b18b4ce1272..e45d2bf6a0b 100644 --- a/arch/arm/dts/k3-am62p5-r5-sk.dts +++ b/arch/arm/dts/k3-am62p5-r5-sk.dts @@ -69,7 +69,7 @@ }; sysctrler: sysctrler { - compatible = "ti,am654-system-controller"; + compatible = "ti,am654-tisci-rproc-r5"; mboxes= <&secure_proxy_main 1>, <&secure_proxy_main 0>, <&sa3_secproxy 0>; diff --git a/arch/arm/dts/k3-am62p5-verdin-r5.dts b/arch/arm/dts/k3-am62p5-verdin-r5.dts index 983a3bfe670..17739086935 100644 --- a/arch/arm/dts/k3-am62p5-verdin-r5.dts +++ b/arch/arm/dts/k3-am62p5-verdin-r5.dts @@ -57,7 +57,7 @@ }; sysctrler: sysctrler { - compatible = "ti,am654-system-controller"; + compatible = "ti,am654-tisci-rproc-r5"; mboxes= <&secure_proxy_main 1>, <&secure_proxy_main 0>, <&sa3_secproxy 0>; diff --git a/arch/arm/dts/k3-am642-r5-evm.dts b/arch/arm/dts/k3-am642-r5-evm.dts index 933f75095b1..67b8587d3b2 100644 --- a/arch/arm/dts/k3-am642-r5-evm.dts +++ b/arch/arm/dts/k3-am642-r5-evm.dts @@ -43,7 +43,7 @@ &cbass_main { sysctrler: sysctrler { - compatible = "ti,am654-system-controller"; + compatible = "ti,am654-tisci-rproc-r5"; mboxes= <&secure_proxy_main 1>, <&secure_proxy_main 0>; mbox-names = "tx", "rx"; bootph-pre-ram; diff --git a/arch/arm/dts/k3-am642-r5-phycore-som-2gb.dts b/arch/arm/dts/k3-am642-r5-phycore-som-2gb.dts index 40c25d5dbb6..32a10b24327 100644 --- a/arch/arm/dts/k3-am642-r5-phycore-som-2gb.dts +++ b/arch/arm/dts/k3-am642-r5-phycore-som-2gb.dts @@ -63,7 +63,7 @@ &cbass_main { sysctrler: sysctrler { - compatible = "ti,am654-system-controller"; + compatible = "ti,am654-tisci-rproc-r5"; mboxes= <&secure_proxy_main 1>, <&secure_proxy_main 0>; mbox-names = "tx", "rx"; bootph-pre-ram; diff --git a/arch/arm/dts/k3-am642-r5-sk.dts b/arch/arm/dts/k3-am642-r5-sk.dts index 6e31dfd97c5..cfc548a1cea 100644 --- a/arch/arm/dts/k3-am642-r5-sk.dts +++ b/arch/arm/dts/k3-am642-r5-sk.dts @@ -43,7 +43,7 @@ &cbass_main { sysctrler: sysctrler { - compatible = "ti,am654-system-controller"; + compatible = "ti,am654-tisci-rproc-r5"; mboxes= <&secure_proxy_main 1>, <&secure_proxy_main 0>; mbox-names = "tx", "rx"; bootph-pre-ram; diff --git a/arch/arm/dts/k3-am654-r5-base-board.dts b/arch/arm/dts/k3-am654-r5-base-board.dts index ab5195eb15c..99eb8a2d442 100644 --- a/arch/arm/dts/k3-am654-r5-base-board.dts +++ b/arch/arm/dts/k3-am654-r5-base-board.dts @@ -47,7 +47,7 @@ &cbass_wakeup { sysctrler: sysctrler { - compatible = "ti,am654-system-controller"; + compatible = "ti,am654-tisci-rproc-r5"; mboxes= <&secure_proxy_mcu 4>, <&secure_proxy_mcu 5>; mbox-names = "tx", "rx"; bootph-pre-ram; diff --git a/arch/arm/dts/k3-am67a-r5-beagley-ai.dts b/arch/arm/dts/k3-am67a-r5-beagley-ai.dts index 664be358a97..45d104e8e3f 100644 --- a/arch/arm/dts/k3-am67a-r5-beagley-ai.dts +++ b/arch/arm/dts/k3-am67a-r5-beagley-ai.dts @@ -69,7 +69,7 @@ }; sysctrler: sysctrler { - compatible = "ti,am654-system-controller"; + compatible = "ti,am654-tisci-rproc-r5"; mboxes= <&secure_proxy_main 1>, <&secure_proxy_main 0>, <&sa3_secproxy 0>; diff --git a/arch/arm/dts/k3-j7200-r5-common-proc-board.dts b/arch/arm/dts/k3-j7200-r5-common-proc-board.dts index 9ac29110324..e35b767a7e3 100644 --- a/arch/arm/dts/k3-j7200-r5-common-proc-board.dts +++ b/arch/arm/dts/k3-j7200-r5-common-proc-board.dts @@ -69,7 +69,7 @@ &cbass_mcu_wakeup { sysctrler: sysctrler { - compatible = "ti,am654-system-controller"; + compatible = "ti,am654-tisci-rproc-r5"; mboxes= <&secure_proxy_mcu 4>, <&secure_proxy_mcu 5>; mbox-names = "tx", "rx"; diff --git a/arch/arm/dts/k3-j721e-r5.dtsi b/arch/arm/dts/k3-j721e-r5.dtsi index 786a41c5e90..7398f9b05ec 100644 --- a/arch/arm/dts/k3-j721e-r5.dtsi +++ b/arch/arm/dts/k3-j721e-r5.dtsi @@ -66,7 +66,7 @@ &cbass_mcu_wakeup { sysctrler: sysctrler { bootph-pre-ram; - compatible = "ti,am654-system-controller"; + compatible = "ti,am654-tisci-rproc-r5"; mboxes= <&secure_proxy_mcu 4>, <&secure_proxy_mcu 5>; mbox-names = "tx", "rx"; }; diff --git a/arch/arm/dts/k3-j721s2-r5.dtsi b/arch/arm/dts/k3-j721s2-r5.dtsi index a820f516015..c1c12e217d2 100644 --- a/arch/arm/dts/k3-j721s2-r5.dtsi +++ b/arch/arm/dts/k3-j721s2-r5.dtsi @@ -63,7 +63,7 @@ &cbass_mcu_wakeup { sysctrler: sysctrler { - compatible = "ti,am654-system-controller"; + compatible = "ti,am654-tisci-rproc-r5"; mboxes= <&secure_proxy_mcu 4>, <&secure_proxy_mcu 5>, <&secure_proxy_sa3 5>; mbox-names = "tx", "rx", "boot_notify"; bootph-pre-ram; diff --git a/arch/arm/dts/k3-j722s-r5-evm.dts b/arch/arm/dts/k3-j722s-r5-evm.dts index 286ab50d3da..02a3494a877 100644 --- a/arch/arm/dts/k3-j722s-r5-evm.dts +++ b/arch/arm/dts/k3-j722s-r5-evm.dts @@ -68,7 +68,7 @@ }; sysctrler: sysctrler { - compatible = "ti,am654-system-controller"; + compatible = "ti,am654-tisci-rproc-r5"; mboxes= <&secure_proxy_main 1>, <&secure_proxy_main 0>, <&sa3_secproxy 0>; diff --git a/arch/arm/dts/k3-j784s4-r5.dtsi b/arch/arm/dts/k3-j784s4-r5.dtsi index a1394115b8b..78444dc4e14 100644 --- a/arch/arm/dts/k3-j784s4-r5.dtsi +++ b/arch/arm/dts/k3-j784s4-r5.dtsi @@ -61,7 +61,7 @@ &cbass_mcu_wakeup { sysctrler: sysctrler { - compatible = "ti,am654-system-controller"; + compatible = "ti,am654-tisci-rproc-r5"; mboxes= <&secure_proxy_mcu 4>, <&secure_proxy_mcu 5>, <&secure_proxy_sa3 5>; diff --git a/doc/device-tree-bindings/power/ti,sci-pm-domain.txt b/doc/device-tree-bindings/power/ti,sci-pm-domain.txt index 72d9fbc833c..81f6314230f 100644 --- a/doc/device-tree-bindings/power/ti,sci-pm-domain.txt +++ b/doc/device-tree-bindings/power/ti,sci-pm-domain.txt @@ -30,7 +30,7 @@ Required Properties: Example (AM65x): ---------------- sysfw: sysfw { - compatible = "ti,am654-system-controller"; + compatible = "ti,am654-tisci-rproc-r5"; ... k3_pds: power-controller { compatible = "ti,sci-pm-domain"; diff --git a/doc/device-tree-bindings/remoteproc/k3-system-controller.txt b/doc/device-tree-bindings/remoteproc/k3-system-controller.txt index 33dc46812ed..7de57ad4f00 100644 --- a/doc/device-tree-bindings/remoteproc/k3-system-controller.txt +++ b/doc/device-tree-bindings/remoteproc/k3-system-controller.txt @@ -8,7 +8,7 @@ This driver communicates with ROM for loading this firmware. Required properties: -------------------- -- compatible: Shall be: "ti,am654-system-controller" +- compatible: Shall be: "ti,am654-tisci-rproc-r5-r5" - mbox-names: "tx" for Transfer channel "rx" for Receive channel - mboxes: Corresponding phandles to mailbox channels. @@ -21,7 +21,7 @@ Example: -------- system-controller: system-controller { - compatible = "ti,am654-system-controller"; + compatible = "ti,am654-tisci-rproc-r5-r5"; mboxes= <&secproxy 4>, <&secproxy 5>; mbox-names = "tx", "rx"; }; diff --git a/doc/device-tree-bindings/reset/ti,sci-reset.txt b/doc/device-tree-bindings/reset/ti,sci-reset.txt index e7e2d13f9fb..740b2dfea64 100644 --- a/doc/device-tree-bindings/reset/ti,sci-reset.txt +++ b/doc/device-tree-bindings/reset/ti,sci-reset.txt @@ -23,7 +23,7 @@ Required Properties: Example (AM65x): ---------------- sysfw: sysfw { - compatible = "ti,am654-system-controller"; + compatible = "ti,am654-tisci-rproc-r5"; ... k3_reset: reset-controller { compatible = "ti,sci-reset"; diff --git a/drivers/remoteproc/k3_system_controller.c b/drivers/remoteproc/k3_system_controller.c index 71238a6058a..e59c010de7e 100644 --- a/drivers/remoteproc/k3_system_controller.c +++ b/drivers/remoteproc/k3_system_controller.c @@ -327,7 +327,7 @@ static const struct k3_sysctrler_desc k3_sysctrler_am654_desc = { static const struct udevice_id k3_sysctrler_ids[] = { { - .compatible = "ti,am654-system-controller", + .compatible = "ti,am654-tisci-rproc-r5", .data = (ulong)&k3_sysctrler_am654_desc, }, {} -- cgit v1.2.3 From 0b0641470b3037e7e212b40c7101c1269653f86e Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Thu, 14 Aug 2025 15:14:35 -0300 Subject: Kconfig: Convert SYS_EARLY_PCI_INIT to Kconfig The CONFIG_SYS_EARLY_PCI_INIT symbol is currently not supported by Kconfig. Make it a Kconfig symbol so that users could select it via defconfig. Signed-off-by: Fabio Estevam Reviewed-by: Tom Rini --- common/Kconfig | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/common/Kconfig b/common/Kconfig index a2f653f7e72..cb17f056153 100644 --- a/common/Kconfig +++ b/common/Kconfig @@ -833,6 +833,13 @@ config PCI_INIT_R case of DM PCI-based Ethernet devices, which will not be detected without having the enumeration performed earlier. +config SYS_EARLY_PCI_INIT + bool "Enumerate PCI buses early during init" + depends on PCI + help + Do early PCI configuration before the eMMC gets initialised, + because PCI resources are crucial for eMMC access on some boards. + config RESET_PHY_R bool "Reset ethernet PHY during init" help -- cgit v1.2.3 From 51214ffcc543dde83ad687c35cb2de61a34e0602 Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Thu, 14 Aug 2025 15:14:36 -0300 Subject: qemu_arm: Select CONFIG_SYS_EARLY_PCI_INIT Select CONFIG_SYS_EARLY_PCI_INIT so that eMMC emulation can work. Signed-off-by: Fabio Estevam Reviewed-by: Tom Rini Tested-by: Jan Kiszka --- board/emulation/qemu-arm/Kconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/board/emulation/qemu-arm/Kconfig b/board/emulation/qemu-arm/Kconfig index 80ab9d8e1c3..447061b25cd 100644 --- a/board/emulation/qemu-arm/Kconfig +++ b/board/emulation/qemu-arm/Kconfig @@ -8,6 +8,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select HAS_CUSTOM_SYS_INIT_SP_ADDR select QFW if ACPI select QFW_MMIO if CMD_QFW + imply SYS_EARLY_PCI_INIT imply VIRTIO_MMIO imply VIRTIO_PCI imply VIRTIO_NET -- cgit v1.2.3 From 91595c96a53360dce696c2da694b1983c91d64f6 Mon Sep 17 00:00:00 2001 From: Rasmus Villemoes Date: Fri, 15 Aug 2025 08:17:19 +0200 Subject: i2c: omap24xx_i2c: remove unused members of struct omap_i2c The clk and clk_id members of struct omap_i2c are not used anywhere, and AFAICT never have been. Signed-off-by: Rasmus Villemoes Reviewed-by: Aniket Limaye --- drivers/i2c/omap24xx_i2c.c | 2 -- 1 file changed, 2 deletions(-) diff --git a/drivers/i2c/omap24xx_i2c.c b/drivers/i2c/omap24xx_i2c.c index a6361d3d17d..2c6f8ea5901 100644 --- a/drivers/i2c/omap24xx_i2c.c +++ b/drivers/i2c/omap24xx_i2c.c @@ -134,12 +134,10 @@ static const u8 __maybe_unused reg_map_ip_v2[] = { }; struct omap_i2c { - struct udevice *clk; int ip_rev; struct i2c *regs; unsigned int speed; int waitdelay; - int clk_id; }; static inline const u8 *omap_i2c_get_ip_reg_map(int ip_rev) -- cgit v1.2.3 From 5727df875002ee8233c983aaed923c04a945be8c Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Wed, 6 Aug 2025 08:55:17 -0600 Subject: tpm: tpm_tis_st33zp24: Remove unused drivers The tpm_tis_st33zp24_i2c and tpm_tis_st33zp24_spi drivers are unused. Remove them. Signed-off-by: Tom Rini Reviewed-by: Ilias Apalodimas Signed-off-by: Ilias Apalodimas --- README | 11 - drivers/tpm/Kconfig | 18 - drivers/tpm/Makefile | 2 - drivers/tpm/tpm_tis_st33zp24_i2c.c | 545 ------------------------------ drivers/tpm/tpm_tis_st33zp24_spi.c | 674 ------------------------------------- 5 files changed, 1250 deletions(-) delete mode 100644 drivers/tpm/tpm_tis_st33zp24_i2c.c delete mode 100644 drivers/tpm/tpm_tis_st33zp24_spi.c diff --git a/README b/README index 65305e6a037..07cfded6be5 100644 --- a/README +++ b/README @@ -390,17 +390,6 @@ The following options need to be configured: CONFIG_TPM_TIS_I2C_BURST_LIMITATION Define the burst count bytes upper limit - CONFIG_TPM_ST33ZP24 - Support for STMicroelectronics TPM devices. Requires DM_TPM support. - - CONFIG_TPM_ST33ZP24_I2C - Support for STMicroelectronics ST33ZP24 I2C devices. - Requires TPM_ST33ZP24 and I2C. - - CONFIG_TPM_ST33ZP24_SPI - Support for STMicroelectronics ST33ZP24 SPI devices. - Requires TPM_ST33ZP24 and SPI. - CONFIG_TPM_ATMEL_TWI Support for Atmel TWI TPM device. Requires I2C support. diff --git a/drivers/tpm/Kconfig b/drivers/tpm/Kconfig index 01bc686d367..219ea606b50 100644 --- a/drivers/tpm/Kconfig +++ b/drivers/tpm/Kconfig @@ -75,24 +75,6 @@ config TPM_AUTH_SESSIONS TPM_LoadKey2 and TPM_GetPubKey are provided. Both features are available using the 'tpm' command, too. -config TPM_ST33ZP24_I2C - bool "STMicroelectronics ST33ZP24 I2C TPM" - depends on TPM_V1 && DM_I2C - ---help--- - This driver supports STMicroelectronics TPM devices connected on the I2C bus. - The usual tpm operations and the 'tpm' command can be used to talk - to the device using the standard TPM Interface Specification (TIS) - protocol - -config TPM_ST33ZP24_SPI - bool "STMicroelectronics ST33ZP24 SPI TPM" - depends on TPM_V1 && DM_SPI - ---help--- - This driver supports STMicroelectronics TPM devices connected on the SPI bus. - The usual tpm operations and the 'tpm' command can be used to talk - to the device using the standard TPM Interface Specification (TIS) - protocol - config TPM_FLUSH_RESOURCES bool "Enable TPM resource flushing support" depends on TPM_V1 diff --git a/drivers/tpm/Makefile b/drivers/tpm/Makefile index 76e516dbbaf..b83ce703ec0 100644 --- a/drivers/tpm/Makefile +++ b/drivers/tpm/Makefile @@ -7,8 +7,6 @@ obj-$(CONFIG_TPM_ATMEL_TWI) += tpm_atmel_twi.o obj-$(CONFIG_TPM_TIS_INFINEON) += tpm_tis_infineon.o obj-$(CONFIG_TPM_TIS_LPC) += tpm_tis_lpc.o obj-$(CONFIG_TPM_TIS_SANDBOX) += tpm_tis_sandbox.o sandbox_common.o -obj-$(CONFIG_TPM_ST33ZP24_I2C) += tpm_tis_st33zp24_i2c.o -obj-$(CONFIG_TPM_ST33ZP24_SPI) += tpm_tis_st33zp24_spi.o obj-$(CONFIG_$(PHASE_)TPM2_CR50_I2C) += cr50_i2c.o obj-$(CONFIG_TPM2_TIS_SANDBOX) += tpm2_tis_sandbox.o sandbox_common.o diff --git a/drivers/tpm/tpm_tis_st33zp24_i2c.c b/drivers/tpm/tpm_tis_st33zp24_i2c.c deleted file mode 100644 index 1a265b28b22..00000000000 --- a/drivers/tpm/tpm_tis_st33zp24_i2c.c +++ /dev/null @@ -1,545 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * STMicroelectronics TPM ST33ZP24 I2C UBOOT driver - * - * Copyright (C) 2016, STMicroelectronics - All Rights Reserved - * Author(s): Christophe Ricard for STMicroelectronics. - * - * Description: Device driver for ST33ZP24 I2C TPM TCG. - * - * This device driver implements the TPM interface as defined in - * the TCG TPM Interface Spec version 1.21, revision 1.0 and the - * STMicroelectronics Protocol Stack Specification version 1.2.0. - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include "tpm_tis.h" -#include "tpm_internal.h" - -#define TPM_ACCESS 0x0 -#define TPM_STS 0x18 -#define TPM_DATA_FIFO 0x24 - -#define LOCALITY0 0 - -#define TPM_DUMMY_BYTE 0xAA -#define TPM_ST33ZP24_I2C_SLAVE_ADDR 0x13 - -#define TPM_WRITE_DIRECTION 0x80 - -/* - * st33zp24_i2c_write8_reg - * Send byte to the TIS register according to the ST33ZP24 I2C protocol. - * @param: tpm_register, the tpm tis register where the data should be written - * @param: tpm_data, the tpm_data to write inside the tpm_register - * @param: tpm_size, The length of the data - * @return: Number of byte written successfully else an error code. - */ -static int st33zp24_i2c_write8_reg(struct udevice *dev, u8 tpm_register, - const u8 *tpm_data, size_t tpm_size) -{ - struct tpm_chip_priv *chip_priv = dev_get_uclass_priv(dev); - - chip_priv->buf[0] = tpm_register; - memcpy(chip_priv->buf + 1, tpm_data, tpm_size); - - return dm_i2c_write(dev, 0, chip_priv->buf, tpm_size + 1); -} - -/* -* st33zp24_i2c_read8_reg -* Recv byte from the TIS register according to the ST33ZP24 I2C protocol. -* @param: tpm_register, the tpm tis register where the data should be read -* @param: tpm_data, the TPM response -* @param: tpm_size, tpm TPM response size to read. -* @return: Number of byte read successfully else an error code. -*/ -static int st33zp24_i2c_read8_reg(struct udevice *dev, u8 tpm_register, - u8 *tpm_data, size_t tpm_size) -{ - int status; - u8 data; - - data = TPM_DUMMY_BYTE; - status = st33zp24_i2c_write8_reg(dev, tpm_register, &data, 1); - if (status < 0) - return status; - - return dm_i2c_read(dev, 0, tpm_data, tpm_size); -} - -/* - * st33zp24_i2c_write - * Send byte to the TIS register according to the ST33ZP24 I2C protocol. - * @param: phy_id, the phy description - * @param: tpm_register, the tpm tis register where the data should be written - * @param: tpm_data, the tpm_data to write inside the tpm_register - * @param: tpm_size, the length of the data - * @return: number of byte written successfully: should be one if success. - */ -static int st33zp24_i2c_write(struct udevice *dev, u8 tpm_register, - const u8 *tpm_data, size_t tpm_size) -{ - return st33zp24_i2c_write8_reg(dev, tpm_register | TPM_WRITE_DIRECTION, - tpm_data, tpm_size); -} - -/* - * st33zp24_i2c_read - * Recv byte from the TIS register according to the ST33ZP24 I2C protocol. - * @param: phy_id, the phy description - * @param: tpm_register, the tpm tis register where the data should be read - * @param: tpm_data, the TPM response - * @param: tpm_size, tpm TPM response size to read. - * @return: number of byte read successfully: should be one if success. - */ -static int st33zp24_i2c_read(struct udevice *dev, u8 tpm_register, - u8 *tpm_data, size_t tpm_size) -{ - return st33zp24_i2c_read8_reg(dev, tpm_register, tpm_data, tpm_size); -} - -/* - * st33zp24_i2c_release_locality release the active locality - * @param: chip, the tpm chip description. - */ -static void st33zp24_i2c_release_locality(struct udevice *dev) -{ - u8 data = TPM_ACCESS_ACTIVE_LOCALITY; - - st33zp24_i2c_write(dev, TPM_ACCESS, &data, 1); -} - -/* - * st33zp24_i2c_check_locality if the locality is active - * @param: chip, the tpm chip description - * @return: the active locality or -EACCES. - */ -static int st33zp24_i2c_check_locality(struct udevice *dev) -{ - struct tpm_chip *chip = dev_get_priv(dev); - u8 data; - u8 status; - - status = st33zp24_i2c_read(dev, TPM_ACCESS, &data, 1); - if (!status && (data & - (TPM_ACCESS_ACTIVE_LOCALITY | TPM_ACCESS_VALID)) == - (TPM_ACCESS_ACTIVE_LOCALITY | TPM_ACCESS_VALID)) - return chip->locality; - - return -EACCES; -} - -/* - * st33zp24_i2c_request_locality request the TPM locality - * @param: chip, the chip description - * @return: the active locality or negative value. - */ -static int st33zp24_i2c_request_locality(struct udevice *dev) -{ - struct tpm_chip *chip = dev_get_priv(dev); - unsigned long start, stop; - long ret; - u8 data; - - if (st33zp24_i2c_check_locality(dev) == chip->locality) - return chip->locality; - - data = TPM_ACCESS_REQUEST_USE; - ret = st33zp24_i2c_write(dev, TPM_ACCESS, &data, 1); - if (ret < 0) - return ret; - - /* wait for locality activated */ - start = get_timer(0); - stop = chip->timeout_a; - do { - if (st33zp24_i2c_check_locality(dev) >= 0) - return chip->locality; - udelay(TPM_TIMEOUT_MS * 1000); - } while (get_timer(start) < stop); - - return -EACCES; -} - -/* - * st33zp24_i2c_status return the TPM_STS register - * @param: chip, the tpm chip description - * @return: the TPM_STS register value. - */ -static u8 st33zp24_i2c_status(struct udevice *dev) -{ - u8 data; - - st33zp24_i2c_read(dev, TPM_STS, &data, 1); - - return data; -} - -/* - * st33zp24_i2c_get_burstcount return the burstcount address 0x19 0x1A - * @param: chip, the chip description - * return: the burstcount or -TPM_DRIVER_ERR in case of error. - */ -static int st33zp24_i2c_get_burstcount(struct udevice *dev) -{ - struct tpm_chip *chip = dev_get_priv(dev); - unsigned long start, stop; - int burstcnt, status; - u8 tpm_reg, temp; - - /* wait for burstcount */ - start = get_timer(0); - stop = chip->timeout_d; - do { - tpm_reg = TPM_STS + 1; - status = st33zp24_i2c_read(dev, tpm_reg, &temp, 1); - if (status < 0) - return -EBUSY; - - tpm_reg = TPM_STS + 2; - burstcnt = temp; - status = st33zp24_i2c_read(dev, tpm_reg, &temp, 1); - if (status < 0) - return -EBUSY; - - burstcnt |= temp << 8; - if (burstcnt) - return burstcnt; - udelay(TIS_SHORT_TIMEOUT_MS * 1000); - } while (get_timer(start) < stop); - - return -EBUSY; -} - -/* - * st33zp24_i2c_cancel, cancel the current command execution or - * set STS to COMMAND READY. - * @param: chip, tpm_chip description. - */ -static void st33zp24_i2c_cancel(struct udevice *dev) -{ - u8 data; - - data = TPM_STS_COMMAND_READY; - st33zp24_i2c_write(dev, TPM_STS, &data, 1); -} - -/* - * st33zp24_i2c_wait_for_stat wait for a TPM_STS value - * @param: chip, the tpm chip description - * @param: mask, the value mask to wait - * @param: timeout, the timeout - * @param: status, - * @return: the tpm status, 0 if success, -ETIME if timeout is reached. - */ -static int st33zp24_i2c_wait_for_stat(struct udevice *dev, u8 mask, - unsigned long timeout, int *status) -{ - unsigned long start, stop; - - /* Check current status */ - *status = st33zp24_i2c_status(dev); - if ((*status & mask) == mask) - return 0; - - start = get_timer(0); - stop = timeout; - do { - udelay(TPM_TIMEOUT_MS * 1000); - *status = st33zp24_i2c_status(dev); - if ((*status & mask) == mask) - return 0; - } while (get_timer(start) < stop); - - return -ETIME; -} - -/* - * st33zp24_i2c_recv_data receive data - * @param: chip, the tpm chip description - * @param: buf, the buffer where the data are received - * @param: count, the number of data to receive - * @return: the number of bytes read from TPM FIFO. - */ -static int st33zp24_i2c_recv_data(struct udevice *dev, u8 *buf, size_t count) -{ - struct tpm_chip *chip = dev_get_priv(dev); - int size = 0, burstcnt, len, ret, status; - - while (size < count && - st33zp24_i2c_wait_for_stat(dev, TPM_STS_DATA_AVAIL | TPM_STS_VALID, - chip->timeout_c, &status) == 0) { - burstcnt = st33zp24_i2c_get_burstcount(dev); - if (burstcnt < 0) - return burstcnt; - len = min_t(int, burstcnt, count - size); - ret = st33zp24_i2c_read(dev, TPM_DATA_FIFO, buf + size, len); - if (ret < 0) - return ret; - - size += len; - } - - return size; -} - -/* - * st33zp24_i2c_recv received TPM response through TPM phy. - * @param: chip, tpm_chip description. - * @param: buf, the buffer to store data. - * @param: count, the number of bytes that can received (sizeof buf). - * @return: Returns zero in case of success else -EIO. - */ -static int st33zp24_i2c_recv(struct udevice *dev, u8 *buf, size_t count) -{ - struct tpm_chip *chip = dev_get_priv(dev); - int size; - unsigned int expected; - - if (!chip) - return -ENODEV; - - if (count < TPM_HEADER_SIZE) { - size = -EIO; - goto out; - } - - size = st33zp24_i2c_recv_data(dev, buf, TPM_HEADER_SIZE); - if (size < TPM_HEADER_SIZE) { - debug("TPM error, unable to read header\n"); - goto out; - } - - expected = get_unaligned_be32(buf + 2); - if (expected > count || expected < TPM_HEADER_SIZE) { - size = -EIO; - goto out; - } - - size += st33zp24_i2c_recv_data(dev, &buf[TPM_HEADER_SIZE], - expected - TPM_HEADER_SIZE); - if (size < expected) { - debug("TPM error, unable to read remaining bytes of result\n"); - size = -EIO; - goto out; - } - -out: - st33zp24_i2c_cancel(dev); - st33zp24_i2c_release_locality(dev); - - return size; -} - -/* - * st33zp24_i2c_send send TPM commands through TPM phy. - * @param: chip, tpm_chip description. - * @param: buf, the buffer to send. - * @param: len, the number of bytes to send. - * @return: Returns zero in case of success else the negative error code. - */ -static int st33zp24_i2c_send(struct udevice *dev, const u8 *buf, size_t len) -{ - struct tpm_chip *chip = dev_get_priv(dev); - u32 i, size; - int burstcnt, ret, status; - u8 data, tpm_stat; - - if (!chip) - return -ENODEV; - if (len < TPM_HEADER_SIZE) - return -EIO; - - ret = st33zp24_i2c_request_locality(dev); - if (ret < 0) - return ret; - - tpm_stat = st33zp24_i2c_status(dev); - if ((tpm_stat & TPM_STS_COMMAND_READY) == 0) { - st33zp24_i2c_cancel(dev); - if (st33zp24_i2c_wait_for_stat(dev, TPM_STS_COMMAND_READY, - chip->timeout_b, &status) < 0) { - ret = -ETIME; - goto out_err; - } - } - - for (i = 0; i < len - 1;) { - burstcnt = st33zp24_i2c_get_burstcount(dev); - if (burstcnt < 0) - return burstcnt; - - size = min_t(int, len - i - 1, burstcnt); - ret = st33zp24_i2c_write(dev, TPM_DATA_FIFO, buf + i, size); - if (ret < 0) - goto out_err; - - i += size; - } - - tpm_stat = st33zp24_i2c_status(dev); - if ((tpm_stat & TPM_STS_DATA_EXPECT) == 0) { - ret = -EIO; - goto out_err; - } - - ret = st33zp24_i2c_write(dev, TPM_DATA_FIFO, buf + len - 1, 1); - if (ret < 0) - goto out_err; - - tpm_stat = st33zp24_i2c_status(dev); - if ((tpm_stat & TPM_STS_DATA_EXPECT) != 0) { - ret = -EIO; - goto out_err; - } - - data = TPM_STS_GO; - ret = st33zp24_i2c_write(dev, TPM_STS, &data, 1); - if (ret < 0) - goto out_err; - - return len; - -out_err: - st33zp24_i2c_cancel(dev); - st33zp24_i2c_release_locality(dev); - - return ret; -} - -static int st33zp24_i2c_cleanup(struct udevice *dev) -{ - st33zp24_i2c_cancel(dev); - /* - * The TPM needs some time to clean up here, - * so we sleep rather than keeping the bus busy - */ - mdelay(2); - st33zp24_i2c_release_locality(dev); - - return 0; -} - -static int st33zp24_i2c_init(struct udevice *dev) -{ - struct tpm_chip *chip = dev_get_priv(dev); - - chip->is_open = 1; - - /* Default timeouts - these could move to the device tree */ - chip->timeout_a = TIS_SHORT_TIMEOUT_MS; - chip->timeout_b = TIS_LONG_TIMEOUT_MS; - chip->timeout_c = TIS_SHORT_TIMEOUT_MS; - chip->timeout_d = TIS_SHORT_TIMEOUT_MS; - - chip->locality = LOCALITY0; - - /* - * A timeout query to TPM can be placed here. - * Standard timeout values are used so far - */ - - return 0; -} - -static int st33zp24_i2c_open(struct udevice *dev) -{ - struct tpm_chip *chip = dev_get_priv(dev); - int rc; - - debug("%s: start\n", __func__); - if (chip->is_open) - return -EBUSY; - - rc = st33zp24_i2c_init(dev); - if (rc < 0) - chip->is_open = 0; - - return rc; -} - -static int st33zp24_i2c_close(struct udevice *dev) -{ - struct tpm_chip *chip = dev_get_priv(dev); - - if (chip->is_open) { - st33zp24_i2c_release_locality(dev); - chip->is_open = 0; - chip->vend_dev = 0; - } - - return 0; -} - -static int st33zp24_i2c_get_desc(struct udevice *dev, char *buf, int size) -{ - struct tpm_chip *chip = dev_get_priv(dev); - - if (size < 50) - return -ENOSPC; - - return snprintf(buf, size, "1.2 TPM (%s, chip type %s device-id 0x%x)", - chip->is_open ? "open" : "closed", - dev->name, - chip->vend_dev >> 16); -} - -static const struct tpm_ops st33zp24_i2c_tpm_ops = { - .open = st33zp24_i2c_open, - .close = st33zp24_i2c_close, - .recv = st33zp24_i2c_recv, - .send = st33zp24_i2c_send, - .cleanup = st33zp24_i2c_cleanup, - .get_desc = st33zp24_i2c_get_desc, -}; - -static int st33zp24_i2c_probe(struct udevice *dev) -{ - struct tpm_chip *chip = dev_get_priv(dev); - - /* Default timeouts */ - chip->timeout_a = TIS_SHORT_TIMEOUT_MS; - chip->timeout_b = TIS_LONG_TIMEOUT_MS; - chip->timeout_c = TIS_SHORT_TIMEOUT_MS; - chip->timeout_d = TIS_SHORT_TIMEOUT_MS; - - chip->locality = LOCALITY0; - - i2c_set_chip_offset_len(dev, 0); - - debug("ST33ZP24 I2C TPM from STMicroelectronics found\n"); - - return 0; -} - -static int st33zp24_i2c_remove(struct udevice *dev) -{ - st33zp24_i2c_release_locality(dev); - - return 0; -} - -static const struct udevice_id st33zp24_i2c_ids[] = { - { .compatible = "st,st33zp24-i2c" }, - { } -}; - -U_BOOT_DRIVER(st33zp24_i2c) = { - .name = "st33zp24-i2c", - .id = UCLASS_TPM, - .of_match = of_match_ptr(st33zp24_i2c_ids), - .probe = st33zp24_i2c_probe, - .remove = st33zp24_i2c_remove, - .ops = &st33zp24_i2c_tpm_ops, - .priv_auto = sizeof(struct tpm_chip), -}; diff --git a/drivers/tpm/tpm_tis_st33zp24_spi.c b/drivers/tpm/tpm_tis_st33zp24_spi.c deleted file mode 100644 index 2cf690328d8..00000000000 --- a/drivers/tpm/tpm_tis_st33zp24_spi.c +++ /dev/null @@ -1,674 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * STMicroelectronics TPM ST33ZP24 SPI UBOOT driver - * - * Copyright (C) 2016, STMicroelectronics - All Rights Reserved - * Author(s): Christophe Ricard for STMicroelectronics. - * - * Description: Device driver for ST33ZP24 SPI TPM TCG. - * - * This device driver implements the TPM interface as defined in - * the TCG TPM Interface Spec version 1.21, revision 1.0 and the - * STMicroelectronics Protocol Stack Specification version 1.2.0. - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include "tpm_tis.h" -#include "tpm_internal.h" - -#define TPM_ACCESS 0x0 -#define TPM_STS 0x18 -#define TPM_DATA_FIFO 0x24 - -#define LOCALITY0 0 - -#define TPM_DATA_FIFO 0x24 -#define TPM_INTF_CAPABILITY 0x14 - -#define TPM_DUMMY_BYTE 0x00 -#define TPM_WRITE_DIRECTION 0x80 - -#define MAX_SPI_LATENCY 15 -#define LOCALITY0 0 - -#define ST33ZP24_OK 0x5A -#define ST33ZP24_UNDEFINED_ERR 0x80 -#define ST33ZP24_BADLOCALITY 0x81 -#define ST33ZP24_TISREGISTER_UKNOWN 0x82 -#define ST33ZP24_LOCALITY_NOT_ACTIVATED 0x83 -#define ST33ZP24_HASH_END_BEFORE_HASH_START 0x84 -#define ST33ZP24_BAD_COMMAND_ORDER 0x85 -#define ST33ZP24_INCORECT_RECEIVED_LENGTH 0x86 -#define ST33ZP24_TPM_FIFO_OVERFLOW 0x89 -#define ST33ZP24_UNEXPECTED_READ_FIFO 0x8A -#define ST33ZP24_UNEXPECTED_WRITE_FIFO 0x8B -#define ST33ZP24_CMDRDY_SET_WHEN_PROCESSING_HASH_END 0x90 -#define ST33ZP24_DUMMY_BYTES 0x00 - -/* - * TPM command can be up to 2048 byte, A TPM response can be up to - * 1024 byte. - * Between command and response, there are latency byte (up to 15 - * usually on st33zp24 2 are enough). - * - * Overall when sending a command and expecting an answer we need if - * worst case: - * 2048 (for the TPM command) + 1024 (for the TPM answer). We need - * some latency byte before the answer is available (max 15). - * We have 2048 + 1024 + 15. - */ -#define ST33ZP24_SPI_BUFFER_SIZE (TPM_BUFSIZE + (TPM_BUFSIZE / 2) +\ - MAX_SPI_LATENCY) - -struct st33zp24_spi_phy { - int latency; - - u8 tx_buf[ST33ZP24_SPI_BUFFER_SIZE]; - u8 rx_buf[ST33ZP24_SPI_BUFFER_SIZE]; -}; - -static int st33zp24_spi_status_to_errno(u8 code) -{ - switch (code) { - case ST33ZP24_OK: - return 0; - case ST33ZP24_UNDEFINED_ERR: - case ST33ZP24_BADLOCALITY: - case ST33ZP24_TISREGISTER_UKNOWN: - case ST33ZP24_LOCALITY_NOT_ACTIVATED: - case ST33ZP24_HASH_END_BEFORE_HASH_START: - case ST33ZP24_BAD_COMMAND_ORDER: - case ST33ZP24_UNEXPECTED_READ_FIFO: - case ST33ZP24_UNEXPECTED_WRITE_FIFO: - case ST33ZP24_CMDRDY_SET_WHEN_PROCESSING_HASH_END: - return -EPROTO; - case ST33ZP24_INCORECT_RECEIVED_LENGTH: - case ST33ZP24_TPM_FIFO_OVERFLOW: - return -EMSGSIZE; - case ST33ZP24_DUMMY_BYTES: - return -ENOSYS; - } - return code; -} - -/* - * st33zp24_spi_send - * Send byte to TPM register according to the ST33ZP24 SPI protocol. - * @param: tpm, the chip description - * @param: tpm_register, the tpm tis register where the data should be written - * @param: tpm_data, the tpm_data to write inside the tpm_register - * @param: tpm_size, The length of the data - * @return: should be zero if success else a negative error code. - */ -static int st33zp24_spi_write(struct udevice *dev, u8 tpm_register, - const u8 *tpm_data, size_t tpm_size) -{ - int total_length = 0, ret; - struct spi_slave *slave = dev_get_parent_priv(dev); - struct st33zp24_spi_phy *phy = dev_get_plat(dev); - - u8 *tx_buf = (u8 *)phy->tx_buf; - u8 *rx_buf = phy->rx_buf; - - tx_buf[total_length++] = TPM_WRITE_DIRECTION | LOCALITY0; - tx_buf[total_length++] = tpm_register; - - if (tpm_size > 0 && tpm_register == TPM_DATA_FIFO) { - tx_buf[total_length++] = tpm_size >> 8; - tx_buf[total_length++] = tpm_size; - } - memcpy(tx_buf + total_length, tpm_data, tpm_size); - total_length += tpm_size; - - memset(tx_buf + total_length, TPM_DUMMY_BYTE, phy->latency); - - total_length += phy->latency; - - ret = spi_claim_bus(slave); - if (ret < 0) - return ret; - - ret = spi_xfer(slave, total_length * 8, tx_buf, rx_buf, - SPI_XFER_BEGIN | SPI_XFER_END); - if (ret < 0) - return ret; - - spi_release_bus(slave); - - if (ret == 0) - ret = rx_buf[total_length - 1]; - - return st33zp24_spi_status_to_errno(ret); -} - -/* - * spi_st33zp24_spi_read8_reg - * Recv byte from the TIS register according to the ST33ZP24 SPI protocol. - * @param: tpm, the chip description - * @param: tpm_loc, the locality to read register from - * @param: tpm_register, the tpm tis register where the data should be read - * @param: tpm_data, the TPM response - * @param: tpm_size, tpm TPM response size to read. - * @return: should be zero if success else a negative error code. - */ -static u8 st33zp24_spi_read8_reg(struct udevice *dev, u8 tpm_register, - u8 *tpm_data, size_t tpm_size) -{ - int total_length = 0, ret; - struct spi_slave *slave = dev_get_parent_priv(dev); - struct st33zp24_spi_phy *phy = dev_get_plat(dev); - - u8 *tx_buf = (u8 *)phy->tx_buf; - u8 *rx_buf = phy->rx_buf; - - /* Pre-Header */ - tx_buf[total_length++] = LOCALITY0; - tx_buf[total_length++] = tpm_register; - - memset(&tx_buf[total_length], TPM_DUMMY_BYTE, - phy->latency + tpm_size); - total_length += phy->latency + tpm_size; - - ret = spi_claim_bus(slave); - if (ret < 0) - return 0; - - ret = spi_xfer(slave, total_length * 8, tx_buf, rx_buf, - SPI_XFER_BEGIN | SPI_XFER_END); - if (ret < 0) - return 0; - - spi_release_bus(slave); - - if (tpm_size > 0 && ret == 0) { - ret = rx_buf[total_length - tpm_size - 1]; - memcpy(tpm_data, rx_buf + total_length - tpm_size, tpm_size); - } - return ret; -} - -/* - * st33zp24_spi_recv - * Recv byte from the TIS register according to the ST33ZP24 SPI protocol. - * @param: phy_id, the phy description - * @param: tpm_register, the tpm tis register where the data should be read - * @param: tpm_data, the TPM response - * @param: tpm_size, tpm TPM response size to read. - * @return: number of byte read successfully: should be one if success. - */ -static int st33zp24_spi_read(struct udevice *dev, u8 tpm_register, - u8 *tpm_data, size_t tpm_size) -{ - int ret; - - ret = st33zp24_spi_read8_reg(dev, tpm_register, tpm_data, tpm_size); - if (!st33zp24_spi_status_to_errno(ret)) - return tpm_size; - - return ret; -} - -static int st33zp24_spi_evaluate_latency(struct udevice *dev) -{ - int latency = 1, status = 0; - u8 data = 0; - struct st33zp24_spi_phy *phy = dev_get_plat(dev); - - while (!status && latency < MAX_SPI_LATENCY) { - phy->latency = latency; - status = st33zp24_spi_read8_reg(dev, TPM_INTF_CAPABILITY, - &data, 1); - latency++; - } - if (status < 0) - return status; - if (latency == MAX_SPI_LATENCY) - return -ENODEV; - - return latency - 1; -} - -/* - * st33zp24_spi_release_locality release the active locality - * @param: chip, the tpm chip description. - */ -static void st33zp24_spi_release_locality(struct udevice *dev) -{ - u8 data = TPM_ACCESS_ACTIVE_LOCALITY; - - st33zp24_spi_write(dev, TPM_ACCESS, &data, 1); -} - -/* - * st33zp24_spi_check_locality if the locality is active - * @param: chip, the tpm chip description - * @return: the active locality or -EACCES. - */ -static int st33zp24_spi_check_locality(struct udevice *dev) -{ - u8 data; - u8 status; - struct tpm_chip *chip = dev_get_priv(dev); - - status = st33zp24_spi_read(dev, TPM_ACCESS, &data, 1); - if (status && (data & - (TPM_ACCESS_ACTIVE_LOCALITY | TPM_ACCESS_VALID)) == - (TPM_ACCESS_ACTIVE_LOCALITY | TPM_ACCESS_VALID)) - return chip->locality; - - return -EACCES; -} - -/* - * st33zp24_spi_request_locality request the TPM locality - * @param: chip, the chip description - * @return: the active locality or negative value. - */ -static int st33zp24_spi_request_locality(struct udevice *dev) -{ - unsigned long start, stop; - long ret; - u8 data; - struct tpm_chip *chip = dev_get_priv(dev); - - if (st33zp24_spi_check_locality(dev) == chip->locality) - return chip->locality; - - data = TPM_ACCESS_REQUEST_USE; - ret = st33zp24_spi_write(dev, TPM_ACCESS, &data, 1); - if (ret < 0) - return ret; - - /* wait for locality activated */ - start = get_timer(0); - stop = chip->timeout_a; - do { - if (st33zp24_spi_check_locality(dev) >= 0) - return chip->locality; - udelay(TPM_TIMEOUT_MS * 1000); - } while (get_timer(start) < stop); - - return -EACCES; -} - -/* - * st33zp24_spi_status return the TPM_STS register - * @param: chip, the tpm chip description - * @return: the TPM_STS register value. - */ -static u8 st33zp24_spi_status(struct udevice *dev) -{ - u8 data; - - st33zp24_spi_read(dev, TPM_STS, &data, 1); - return data; -} - -/* - * st33zp24_spi_get_burstcount return the burstcount address 0x19 0x1A - * @param: chip, the chip description - * return: the burstcount or -TPM_DRIVER_ERR in case of error. - */ -static int st33zp24_spi_get_burstcount(struct udevice *dev) -{ - struct tpm_chip *chip = dev_get_priv(dev); - unsigned long start, stop; - int burstcnt, status; - u8 tpm_reg, temp; - - /* wait for burstcount */ - start = get_timer(0); - stop = chip->timeout_d; - do { - tpm_reg = TPM_STS + 1; - status = st33zp24_spi_read(dev, tpm_reg, &temp, 1); - if (status < 0) - return -EBUSY; - - tpm_reg = TPM_STS + 2; - burstcnt = temp; - status = st33zp24_spi_read(dev, tpm_reg, &temp, 1); - if (status < 0) - return -EBUSY; - - burstcnt |= temp << 8; - if (burstcnt) - return burstcnt; - udelay(TIS_SHORT_TIMEOUT_MS * 1000); - } while (get_timer(start) < stop); - - return -EBUSY; -} - -/* - * st33zp24_spi_cancel, cancel the current command execution or - * set STS to COMMAND READY. - * @param: chip, tpm_chip description. - */ -static void st33zp24_spi_cancel(struct udevice *dev) -{ - u8 data; - - data = TPM_STS_COMMAND_READY; - st33zp24_spi_write(dev, TPM_STS, &data, 1); -} - -/* - * st33zp24_spi_wait_for_stat wait for a TPM_STS value - * @param: chip, the tpm chip description - * @param: mask, the value mask to wait - * @param: timeout, the timeout - * @param: status, - * @return: the tpm status, 0 if success, -ETIME if timeout is reached. - */ -static int st33zp24_spi_wait_for_stat(struct udevice *dev, u8 mask, - unsigned long timeout, int *status) -{ - unsigned long start, stop; - - /* Check current status */ - *status = st33zp24_spi_status(dev); - if ((*status & mask) == mask) - return 0; - - start = get_timer(0); - stop = timeout; - do { - udelay(TPM_TIMEOUT_MS * 1000); - *status = st33zp24_spi_status(dev); - if ((*status & mask) == mask) - return 0; - } while (get_timer(start) < stop); - - return -ETIME; -} - -/* - * st33zp24_spi_recv_data receive data - * @param: chip, the tpm chip description - * @param: buf, the buffer where the data are received - * @param: count, the number of data to receive - * @return: the number of bytes read from TPM FIFO. - */ -static int st33zp24_spi_recv_data(struct udevice *dev, u8 *buf, size_t count) -{ - struct tpm_chip *chip = dev_get_priv(dev); - int size = 0, burstcnt, len, ret, status; - - while (size < count && - st33zp24_spi_wait_for_stat(dev, TPM_STS_DATA_AVAIL | TPM_STS_VALID, - chip->timeout_c, &status) == 0) { - burstcnt = st33zp24_spi_get_burstcount(dev); - if (burstcnt < 0) - return burstcnt; - len = min_t(int, burstcnt, count - size); - ret = st33zp24_spi_read(dev, TPM_DATA_FIFO, buf + size, len); - if (ret < 0) - return ret; - - size += len; - } - return size; -} - -/* - * st33zp24_spi_recv received TPM response through TPM phy. - * @param: chip, tpm_chip description. - * @param: buf, the buffer to store data. - * @param: count, the number of bytes that can received (sizeof buf). - * @return: Returns zero in case of success else -EIO. - */ -static int st33zp24_spi_recv(struct udevice *dev, u8 *buf, size_t count) -{ - struct tpm_chip *chip = dev_get_priv(dev); - int size; - unsigned int expected; - - if (!chip) - return -ENODEV; - - if (count < TPM_HEADER_SIZE) { - size = -EIO; - goto out; - } - - size = st33zp24_spi_recv_data(dev, buf, TPM_HEADER_SIZE); - if (size < TPM_HEADER_SIZE) { - debug("TPM error, unable to read header\n"); - goto out; - } - - expected = get_unaligned_be32(buf + 2); - if (expected > count || expected < TPM_HEADER_SIZE) { - size = -EIO; - goto out; - } - - size += st33zp24_spi_recv_data(dev, &buf[TPM_HEADER_SIZE], - expected - TPM_HEADER_SIZE); - if (size < expected) { - debug("TPM error, unable to read remaining bytes of result\n"); - size = -EIO; - goto out; - } - -out: - st33zp24_spi_cancel(dev); - st33zp24_spi_release_locality(dev); - - return size; -} - -/* - * st33zp24_spi_send send TPM commands through TPM phy. - * @param: chip, tpm_chip description. - * @param: buf, the buffer to send. - * @param: len, the number of bytes to send. - * @return: Returns zero in case of success else the negative error code. - */ -static int st33zp24_spi_send(struct udevice *dev, const u8 *buf, size_t len) -{ - struct tpm_chip *chip = dev_get_priv(dev); - u32 i, size; - int burstcnt, ret, status; - u8 data, tpm_stat; - - if (!chip) - return -ENODEV; - if (len < TPM_HEADER_SIZE) - return -EIO; - - ret = st33zp24_spi_request_locality(dev); - if (ret < 0) - return ret; - - tpm_stat = st33zp24_spi_status(dev); - if ((tpm_stat & TPM_STS_COMMAND_READY) == 0) { - st33zp24_spi_cancel(dev); - if (st33zp24_spi_wait_for_stat(dev, TPM_STS_COMMAND_READY, - chip->timeout_b, &status) < 0) { - ret = -ETIME; - goto out_err; - } - } - - for (i = 0; i < len - 1;) { - burstcnt = st33zp24_spi_get_burstcount(dev); - if (burstcnt < 0) - return burstcnt; - - size = min_t(int, len - i - 1, burstcnt); - ret = st33zp24_spi_write(dev, TPM_DATA_FIFO, buf + i, size); - if (ret < 0) - goto out_err; - - i += size; - } - - tpm_stat = st33zp24_spi_status(dev); - if ((tpm_stat & TPM_STS_DATA_EXPECT) == 0) { - ret = -EIO; - goto out_err; - } - - ret = st33zp24_spi_write(dev, TPM_DATA_FIFO, buf + len - 1, 1); - if (ret < 0) - goto out_err; - - tpm_stat = st33zp24_spi_status(dev); - if ((tpm_stat & TPM_STS_DATA_EXPECT) != 0) { - ret = -EIO; - goto out_err; - } - - data = TPM_STS_GO; - ret = st33zp24_spi_write(dev, TPM_STS, &data, 1); - if (ret < 0) - goto out_err; - - return len; - -out_err: - st33zp24_spi_cancel(dev); - st33zp24_spi_release_locality(dev); - - return ret; -} - -static int st33zp24_spi_cleanup(struct udevice *dev) -{ - st33zp24_spi_cancel(dev); - /* - * The TPM needs some time to clean up here, - * so we sleep rather than keeping the bus busy - */ - mdelay(2); - st33zp24_spi_release_locality(dev); - - return 0; -} - -static int st33zp24_spi_init(struct udevice *dev) -{ - struct tpm_chip *chip = dev_get_priv(dev); - struct st33zp24_spi_phy *phy = dev_get_plat(dev); - - chip->is_open = 1; - - /* Default timeouts - these could move to the device tree */ - chip->timeout_a = TIS_SHORT_TIMEOUT_MS; - chip->timeout_b = TIS_LONG_TIMEOUT_MS; - chip->timeout_c = TIS_SHORT_TIMEOUT_MS; - chip->timeout_d = TIS_SHORT_TIMEOUT_MS; - - chip->locality = LOCALITY0; - - phy->latency = st33zp24_spi_evaluate_latency(dev); - if (phy->latency <= 0) - return -ENODEV; - - /* - * A timeout query to TPM can be placed here. - * Standard timeout values are used so far - */ - - return 0; -} - -static int st33zp24_spi_open(struct udevice *dev) -{ - struct tpm_chip *chip = dev_get_priv(dev); - int rc; - - debug("%s: start\n", __func__); - if (chip->is_open) - return -EBUSY; - - rc = st33zp24_spi_init(dev); - if (rc < 0) - chip->is_open = 0; - - return rc; -} - -static int st33zp24_spi_close(struct udevice *dev) -{ - struct tpm_chip *chip = dev_get_priv(dev); - - if (chip->is_open) { - st33zp24_spi_release_locality(dev); - chip->is_open = 0; - chip->vend_dev = 0; - } - - return 0; -} - -static int st33zp24_spi_get_desc(struct udevice *dev, char *buf, int size) -{ - struct tpm_chip *chip = dev_get_priv(dev); - - if (size < 50) - return -ENOSPC; - - return snprintf(buf, size, "1.2 TPM (%s, chip type %s device-id 0x%x)", - chip->is_open ? "open" : "closed", - dev->name, - chip->vend_dev >> 16); -} - -const struct tpm_ops st33zp24_spi_tpm_ops = { - .open = st33zp24_spi_open, - .close = st33zp24_spi_close, - .recv = st33zp24_spi_recv, - .send = st33zp24_spi_send, - .cleanup = st33zp24_spi_cleanup, - .get_desc = st33zp24_spi_get_desc, -}; - -static int st33zp24_spi_probe(struct udevice *dev) -{ - struct tpm_chip_priv *uc_priv = dev_get_uclass_priv(dev); - - uc_priv->duration_ms[TPM_SHORT] = TIS_SHORT_TIMEOUT_MS; - uc_priv->duration_ms[TPM_MEDIUM] = TIS_LONG_TIMEOUT_MS; - uc_priv->duration_ms[TPM_LONG] = TIS_LONG_TIMEOUT_MS; - uc_priv->retry_time_ms = TPM_TIMEOUT_MS; - - debug("ST33ZP24 SPI TPM from STMicroelectronics found\n"); - - return 0; -} - -static int st33zp24_spi_remove(struct udevice *dev) -{ - st33zp24_spi_release_locality(dev); - - return 0; -} - -static const struct udevice_id st33zp24_spi_ids[] = { - { .compatible = "st,st33zp24-spi" }, - { } -}; - -U_BOOT_DRIVER(st33zp24_spi_spi) = { - .name = "st33zp24-spi", - .id = UCLASS_TPM, - .of_match = of_match_ptr(st33zp24_spi_ids), - .probe = st33zp24_spi_probe, - .remove = st33zp24_spi_remove, - .ops = &st33zp24_spi_tpm_ops, - .priv_auto = sizeof(struct tpm_chip), - .plat_auto = sizeof(struct st33zp24_spi_phy), -}; -- cgit v1.2.3 From 80afd60d9c7e24ef193b0d59ce98a3d86a70fcb5 Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Wed, 6 Aug 2025 08:55:18 -0600 Subject: tpm: cr50_i2c: Make use of 'z' for printing size_t When printing the contents of an size_t variable we need to use z prefix to the format character in order to get the correct format type depending on 32 or 64bit-ness. Signed-off-by: Tom Rini Reviewed-by: Ilias Apalodimas Signed-off-by: Ilias Apalodimas --- drivers/tpm/cr50_i2c.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/tpm/cr50_i2c.c b/drivers/tpm/cr50_i2c.c index 5b2d5ccb146..14a94f8d4a8 100644 --- a/drivers/tpm/cr50_i2c.c +++ b/drivers/tpm/cr50_i2c.c @@ -388,7 +388,7 @@ static int cr50_i2c_recv(struct udevice *dev, u8 *buf, size_t buf_len) int status; int ret; - log_debug("%s: buf_len=%x\n", __func__, buf_len); + log_debug("%s: buf_len=%zx\n", __func__, buf_len); if (buf_len < TPM_HEADER_SIZE) return -E2BIG; @@ -465,7 +465,7 @@ static int cr50_i2c_send(struct udevice *dev, const u8 *buf, size_t len) ulong timeout; int ret; - log_debug("len=%x\n", len); + log_debug("len=%zx\n", len); timeout = timer_get_us() + TIMEOUT_LONG_US; do { ret = cr50_i2c_status(dev); -- cgit v1.2.3 From 83b1c7fd7119ae654aba70b2451b519035b5403d Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Wed, 6 Aug 2025 08:55:19 -0600 Subject: tpm: tpm_tis_infineon: Make use of 'z' for printing size_t When printing the contents of an size_t variable we need to use z prefix to the format character in order to get the correct format type depending on 32 or 64bit-ness. Signed-off-by: Tom Rini Reviewed-by: Ilias Apalodimas Signed-off-by: Ilias Apalodimas --- drivers/tpm/tpm_tis_infineon.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/tpm/tpm_tis_infineon.c b/drivers/tpm/tpm_tis_infineon.c index e2f6238cbc7..de6566fdb9e 100644 --- a/drivers/tpm/tpm_tis_infineon.c +++ b/drivers/tpm/tpm_tis_infineon.c @@ -396,7 +396,7 @@ static int tpm_tis_i2c_recv(struct udevice *dev, u8 *buf, size_t count) expected = get_unaligned_be32(buf + TPM_RSP_SIZE_BYTE); if ((size_t)expected > count || (size_t)expected < TPM_HEADER_SIZE) { - debug("Error size=%x, expected=%x, count=%x\n", size, expected, + debug("Error size=%x, expected=%x, count=%zx\n", size, expected, count); return -ENOSPC; } @@ -429,7 +429,7 @@ static int tpm_tis_i2c_send(struct udevice *dev, const u8 *buf, size_t len) int retry = 0; u8 sts = TPM_STS_GO; - debug("%s: len=%d\n", __func__, len); + debug("%s: len=%zd\n", __func__, len); if (len > TPM_DEV_BUFSIZE) return -E2BIG; /* Command is too long for our tpm, sorry */ -- cgit v1.2.3 From 73b23838c44b152deef68b7c22d923f0ca7a563f Mon Sep 17 00:00:00 2001 From: Andrew Goodbody Date: Wed, 13 Aug 2025 11:40:05 +0100 Subject: tpm: tis_infineon: Cannot test unsigned for being negative tpm_tis_i2c_get_burstcount returns a size_t but also returns -EBUSY if the TPM is surrently busy. As size_t is an unsigned type simply testing for < 0 will not work so change the test for being equal to -EBUSY which will work. Also remove the trivial comments. This issue was found by Smatch. Signed-off-by: Andrew Goodbody Acked-by: Ilias Apalodimas Signed-off-by: Ilias Apalodimas --- drivers/tpm/tpm_tis_infineon.c | 6 ++---- 1 file changed, 2 insertions(+), 4 deletions(-) diff --git a/drivers/tpm/tpm_tis_infineon.c b/drivers/tpm/tpm_tis_infineon.c index de6566fdb9e..30f23f8610a 100644 --- a/drivers/tpm/tpm_tis_infineon.c +++ b/drivers/tpm/tpm_tis_infineon.c @@ -353,8 +353,7 @@ static int tpm_tis_i2c_recv_data(struct udevice *dev, u8 *buf, size_t count) while (size < count) { burstcnt = tpm_tis_i2c_get_burstcount(dev); - /* burstcount < 0 -> tpm is busy */ - if (burstcnt < 0) + if (burstcnt == -EBUSY) return burstcnt; /* Limit received data to max left */ @@ -449,8 +448,7 @@ static int tpm_tis_i2c_send(struct udevice *dev, const u8 *buf, size_t len) burstcnt = tpm_tis_i2c_get_burstcount(dev); - /* burstcount < 0 -> tpm is busy */ - if (burstcnt < 0) + if (burstcnt == -EBUSY) return burstcnt; while (count < len) { -- cgit v1.2.3 From 1fa340932946b337c7fd58cf8f825bb0c95f3e95 Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Tue, 22 Jul 2025 10:15:05 +0200 Subject: xilinx: Make XILINX_OF_BOARD_DTB_ADDR depending on OF_BOARD only board_fdt_blob_setup() is guarded by OF_BOARD already that's why make no sense to depend also on OF_SEPARATE. Signed-off-by: Michal Simek Link: https://lore.kernel.org/r/063b2e618afb05a32d66218f3631a5f23b30ea3e.1753172103.git.michal.simek@amd.com --- board/xilinx/Kconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/board/xilinx/Kconfig b/board/xilinx/Kconfig index f7152d6ee6d..5c3240da073 100644 --- a/board/xilinx/Kconfig +++ b/board/xilinx/Kconfig @@ -55,7 +55,7 @@ config XILINX_OF_BOARD_DTB_ADDR default 0x8000 if MICROBLAZE default 0x100000 if ARCH_ZYNQ || ARCH_ZYNQMP default 0x83000000 if TARGET_XILINX_MBV - depends on OF_BOARD || OF_SEPARATE + depends on OF_BOARD help Offset in the memory where the board configuration DTB is placed. -- cgit v1.2.3 From d0e8a208f6f09c1719fe17b3208b5b239f42cf69 Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Wed, 23 Jul 2025 11:06:46 +0200 Subject: serial: uartlite: Use private data instead of platform plat data should be used only in probe or of_to_plat to fill it information from DT. Then in probe platform data should be stored in private structure which should be used by the other driver functions. Signed-off-by: Michal Simek Link: https://lore.kernel.org/r/8d32af596f80a2220d9f5d7fb98476e6d2b5f303.1753261604.git.michal.simek@amd.com --- drivers/serial/serial_xuartlite.c | 20 ++++++++++++++------ 1 file changed, 14 insertions(+), 6 deletions(-) diff --git a/drivers/serial/serial_xuartlite.c b/drivers/serial/serial_xuartlite.c index eb234108746..00155aba5eb 100644 --- a/drivers/serial/serial_xuartlite.c +++ b/drivers/serial/serial_xuartlite.c @@ -35,6 +35,10 @@ struct uartlite_plat { struct uartlite *regs; }; +struct uartlite_priv { + struct uartlite *regs; +}; + static u32 uart_in32(void __iomem *addr) { if (little_endian) @@ -53,8 +57,8 @@ static void uart_out32(void __iomem *addr, u32 val) static int uartlite_serial_putc(struct udevice *dev, const char ch) { - struct uartlite_plat *plat = dev_get_plat(dev); - struct uartlite *regs = plat->regs; + struct uartlite_priv *priv = dev_get_priv(dev); + struct uartlite *regs = priv->regs; if (uart_in32(®s->status) & SR_TX_FIFO_FULL) return -EAGAIN; @@ -66,8 +70,8 @@ static int uartlite_serial_putc(struct udevice *dev, const char ch) static int uartlite_serial_getc(struct udevice *dev) { - struct uartlite_plat *plat = dev_get_plat(dev); - struct uartlite *regs = plat->regs; + struct uartlite_priv *priv = dev_get_priv(dev); + struct uartlite *regs = priv->regs; if (!(uart_in32(®s->status) & SR_RX_FIFO_VALID_DATA)) return -EAGAIN; @@ -77,8 +81,8 @@ static int uartlite_serial_getc(struct udevice *dev) static int uartlite_serial_pending(struct udevice *dev, bool input) { - struct uartlite_plat *plat = dev_get_plat(dev); - struct uartlite *regs = plat->regs; + struct uartlite_priv *priv = dev_get_priv(dev); + struct uartlite *regs = priv->regs; if (input) return uart_in32(®s->status) & SR_RX_FIFO_VALID_DATA; @@ -89,9 +93,12 @@ static int uartlite_serial_pending(struct udevice *dev, bool input) static int uartlite_serial_probe(struct udevice *dev) { struct uartlite_plat *plat = dev_get_plat(dev); + struct uartlite_priv *priv = dev_get_priv(dev); struct uartlite *regs = plat->regs; int ret; + priv->regs = regs; + uart_out32(®s->control, 0); uart_out32(®s->control, ULITE_CONTROL_RST_RX | ULITE_CONTROL_RST_TX); ret = uart_in32(®s->status); @@ -131,6 +138,7 @@ U_BOOT_DRIVER(serial_uartlite) = { .id = UCLASS_SERIAL, .of_match = uartlite_serial_ids, .of_to_plat = uartlite_serial_of_to_plat, + .priv_auto = sizeof(struct uartlite_priv), .plat_auto = sizeof(struct uartlite_plat), .probe = uartlite_serial_probe, .ops = &uartlite_serial_ops, -- cgit v1.2.3 From 3a85a27e34624f1b0f08979ea914e0cadfcbf74d Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Wed, 23 Jul 2025 11:06:47 +0200 Subject: serial: uartlite: Add support for OF_PLATDATA The first change is to list DM_DRIVER_ALIAS for compatible string to be able to match the driver. Only xps one is listed because opb one is likely unused for quite a long time. The second change is to add dtplat structure to plat data and fill register base in probe. Signed-off-by: Michal Simek Link: https://lore.kernel.org/r/b494dbad529e919d33977b8ea6e6dbcd14e78907.1753261604.git.michal.simek@amd.com --- drivers/serial/serial_xuartlite.c | 19 ++++++++++++++++++- 1 file changed, 18 insertions(+), 1 deletion(-) diff --git a/drivers/serial/serial_xuartlite.c b/drivers/serial/serial_xuartlite.c index 00155aba5eb..6bfd0e085e8 100644 --- a/drivers/serial/serial_xuartlite.c +++ b/drivers/serial/serial_xuartlite.c @@ -32,7 +32,11 @@ struct uartlite { }; struct uartlite_plat { +#if CONFIG_IS_ENABLED(OF_PLATDATA) + struct dtd_serial_uartlite dtplat; +#else struct uartlite *regs; +#endif }; struct uartlite_priv { @@ -94,9 +98,16 @@ static int uartlite_serial_probe(struct udevice *dev) { struct uartlite_plat *plat = dev_get_plat(dev); struct uartlite_priv *priv = dev_get_priv(dev); - struct uartlite *regs = plat->regs; + struct uartlite *regs; int ret; +#if CONFIG_IS_ENABLED(OF_PLATDATA) + struct dtd_serial_uartlite *dtplat = &plat->dtplat; + + regs = (struct uartlite *)dtplat->reg[0]; +#else + regs = plat->regs; +#endif priv->regs = regs; uart_out32(®s->control, 0); @@ -112,6 +123,7 @@ static int uartlite_serial_probe(struct udevice *dev) return 0; } +#if !CONFIG_IS_ENABLED(OF_PLATDATA) static int uartlite_serial_of_to_plat(struct udevice *dev) { struct uartlite_plat *plat = dev_get_plat(dev); @@ -120,6 +132,7 @@ static int uartlite_serial_of_to_plat(struct udevice *dev) return 0; } +#endif static const struct dm_serial_ops uartlite_serial_ops = { .putc = uartlite_serial_putc, @@ -137,13 +150,17 @@ U_BOOT_DRIVER(serial_uartlite) = { .name = "serial_uartlite", .id = UCLASS_SERIAL, .of_match = uartlite_serial_ids, +#if !CONFIG_IS_ENABLED(OF_PLATDATA) .of_to_plat = uartlite_serial_of_to_plat, +#endif .priv_auto = sizeof(struct uartlite_priv), .plat_auto = sizeof(struct uartlite_plat), .probe = uartlite_serial_probe, .ops = &uartlite_serial_ops, }; +DM_DRIVER_ALIAS(serial_uartlite, xlnx_xps_uartlite_1_00_a) + #ifdef CONFIG_DEBUG_UART_UARTLITE #include -- cgit v1.2.3 From 6d491e8913f07b9ad4f9a86fdb0aab2007e72af3 Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Fri, 25 Jul 2025 14:01:20 +0200 Subject: clk: zynqmp: Mark zynqmp_clk_ops as const Operations are not changing that's why mark them as const which ensure that structure will be moved from .data section to .rodata section. Signed-off-by: Michal Simek Link: https://lore.kernel.org/r/92eb9e90189d8b96246966633478662076da7185.1753444878.git.michal.simek@amd.com --- drivers/clk/clk_zynqmp.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/clk/clk_zynqmp.c b/drivers/clk/clk_zynqmp.c index 4f67c958d0f..7a433a667a4 100644 --- a/drivers/clk/clk_zynqmp.c +++ b/drivers/clk/clk_zynqmp.c @@ -882,7 +882,7 @@ static int zynqmp_clk_enable(struct clk *clk) return ret; } -static struct clk_ops zynqmp_clk_ops = { +static const struct clk_ops zynqmp_clk_ops = { .set_rate = zynqmp_clk_set_rate, .get_rate = zynqmp_clk_get_rate, .enable = zynqmp_clk_enable, -- cgit v1.2.3 From 4b2679efc5f50ac38b9c2f20b3beec56283efddb Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Fri, 25 Jul 2025 14:01:21 +0200 Subject: mailbox: zynqmp-ipi: Mark zynqmp_ipi_dest_mbox_ops as const Operations are not changing that's why mark them as const which ensure that structure will be moved from .data section to .rodata section. Also mark them as static because they are not used out of this file. Signed-off-by: Michal Simek Link: https://lore.kernel.org/r/b7e5dc8841f6e904a7365f2ed45248609c007ddd.1753444878.git.michal.simek@amd.com --- drivers/mailbox/zynqmp-ipi.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/mailbox/zynqmp-ipi.c b/drivers/mailbox/zynqmp-ipi.c index f62277385fb..79266c56e79 100644 --- a/drivers/mailbox/zynqmp-ipi.c +++ b/drivers/mailbox/zynqmp-ipi.c @@ -241,7 +241,7 @@ static int zynqmp_ipi_probe(struct udevice *dev) return 0; }; -struct mbox_ops zynqmp_ipi_dest_mbox_ops = { +static const struct mbox_ops zynqmp_ipi_dest_mbox_ops = { .send = zynqmp_ipi_send, .recv = zynqmp_ipi_recv, }; -- cgit v1.2.3 From 25801ef2d46d44fe1a137971bf4e4d1c0cc529ce Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Fri, 25 Jul 2025 14:01:22 +0200 Subject: dm: core: Mark root_info as const root_info driver structure is not changing that's why mark them as const which ensure that structure will be moved from .data section to .rodata section. Signed-off-by: Michal Simek Link: https://lore.kernel.org/r/18d92a93a9863ed0452e82a1f8e0ff9205adb4f9.1753444878.git.michal.simek@amd.com --- drivers/core/root.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/core/root.c b/drivers/core/root.c index e53381e3b32..d43645f34dd 100644 --- a/drivers/core/root.c +++ b/drivers/core/root.c @@ -32,7 +32,7 @@ DECLARE_GLOBAL_DATA_PTR; -static struct driver_info root_info = { +static const struct driver_info root_info = { .name = "root_driver", }; -- cgit v1.2.3 From 029f26eb5f1556febc80041a38b4c37f4cc91d6a Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Thu, 31 Jul 2025 09:06:18 +0200 Subject: CI: Wire mbv32 combinations After upgrading to QEMU 10 by commit 1d782a3f229c ("Docker, CI: Update to latest Ubuntu and Dockerfile") let's wire mbv32 which is the part of QEMU to have it under regression. Reviewed-by: Tom Rini Signed-off-by: Michal Simek Link: https://lore.kernel.org/r/02e5c14552b05200ece94136db0077cbdd47738c.1753945577.git.michal.simek@amd.com --- .azure-pipelines.yml | 20 ++++++++++++++++++-- .gitlab-ci.yml | 32 ++++++++++++++++++++++++++++++-- 2 files changed, 48 insertions(+), 4 deletions(-) diff --git a/.azure-pipelines.yml b/.azure-pipelines.yml index 8209d2b329c..d4bf43e7a92 100644 --- a/.azure-pipelines.yml +++ b/.azure-pipelines.yml @@ -258,11 +258,11 @@ stages: ln -s u_boot_boardenv_qemu_arm64_na.py /tmp/uboot-test-hooks/py/travis-ci/u_boot_boardenv_qemu_arm64_lwip_na.py ln -s travis-ci /tmp/uboot-test-hooks/bin/\`hostname\` ln -s travis-ci /tmp/uboot-test-hooks/py/\`hostname\` - if [[ "\${TEST_PY_BD}" == "qemu-riscv32_spl" ]]; then + if [[ "\${TEST_PY_BD}" == "qemu-riscv32_spl" ]] || [[ "\${TEST_PY_BD}" == "xilinx_mbv32_smode" ]]; then wget -O - https://github.com/riscv-software-src/opensbi/releases/download/v1.3.1/opensbi-1.3.1-rv-bin.tar.xz | tar -C /tmp -xJ; export OPENSBI=/tmp/opensbi-1.3.1-rv-bin/share/opensbi/ilp32/generic/firmware/fw_dynamic.bin; fi - if [[ "\${TEST_PY_BD}" == "qemu-riscv64_spl" ]] || [[ "\${TEST_PY_BD}" == "sifive_unleashed" ]]; then + if [[ "\${TEST_PY_BD}" == "qemu-riscv64_spl" ]] || [[ "\${TEST_PY_BD}" == "sifive_unleashed" ]] || [[ "\${TEST_PY_BD}" == "xilinx_mbv64_smode" ]]; then wget -O - https://github.com/riscv-software-src/opensbi/releases/download/v1.3.1/opensbi-1.3.1-rv-bin.tar.xz | tar -C /tmp -xJ; export OPENSBI=/tmp/opensbi-1.3.1-rv-bin/share/opensbi/lp64/generic/firmware/fw_dynamic.bin; fi @@ -540,6 +540,22 @@ stages: TEST_PY_BD: "sifive_unleashed" TEST_PY_ID: "--id spi-nor_qemu" TEST_PY_TEST_SPEC: "not sleep" + xilinx_mbv32: + TEST_PY_BD: "xilinx_mbv32" + TEST_PY_ID: "--id qemu" + TEST_PY_TEST_SPEC: "not sleep" + xilinx_mbv32_smode test.py: + TEST_PY_BD: "xilinx_mbv32_smode" + TEST_PY_ID: "--id qemu" + TEST_PY_TEST_SPEC: "not sleep" + xilinx_mbv64 test.py: + TEST_PY_BD: "xilinx_mbv64" + TEST_PY_ID: "--id qemu" + TEST_PY_TEST_SPEC: "not sleep" + xilinx_mbv64_smode test.py: + TEST_PY_BD: "xilinx_mbv64_smode" + TEST_PY_ID: "--id qemu" + TEST_PY_TEST_SPEC: "not sleep" xilinx_zynq_virt: TEST_PY_BD: "xilinx_zynq_virt" TEST_PY_ID: "--id qemu" diff --git a/.gitlab-ci.yml b/.gitlab-ci.yml index 85401d3e09b..b83cd1a5b23 100644 --- a/.gitlab-ci.yml +++ b/.gitlab-ci.yml @@ -43,11 +43,11 @@ stages: - ln -s u_boot_boardenv_qemu_arm64_na.py /tmp/uboot-test-hooks/py/travis-ci/u_boot_boardenv_qemu_arm64_lwip_na.py - ln -s travis-ci /tmp/uboot-test-hooks/bin/`hostname` - ln -s travis-ci /tmp/uboot-test-hooks/py/`hostname` - - if [[ "${TEST_PY_BD}" == "qemu-riscv32_spl" ]]; then + - if [[ "${TEST_PY_BD}" == "qemu-riscv32_spl" ]] || [[ "${TEST_PY_BD}" == "xilinx_mbv32_smode" ]]; then wget -O - https://github.com/riscv-software-src/opensbi/releases/download/v1.3.1/opensbi-1.3.1-rv-bin.tar.xz | tar -C /tmp -xJ; export OPENSBI=/tmp/opensbi-1.3.1-rv-bin/share/opensbi/ilp32/generic/firmware/fw_dynamic.bin; fi - - if [[ "${TEST_PY_BD}" == "qemu-riscv64_spl" ]] || [[ "${TEST_PY_BD}" == "sifive_unleashed" ]]; then + - if [[ "${TEST_PY_BD}" == "qemu-riscv64_spl" ]] || [[ "${TEST_PY_BD}" == "sifive_unleashed" ]] || [[ "${TEST_PY_BD}" == "xilinx_mbv64_smode" ]]; then wget -O - https://github.com/riscv-software-src/opensbi/releases/download/v1.3.1/opensbi-1.3.1-rv-bin.tar.xz | tar -C /tmp -xJ; export OPENSBI=/tmp/opensbi-1.3.1-rv-bin/share/opensbi/lp64/generic/firmware/fw_dynamic.bin; fi @@ -550,6 +550,34 @@ vexpress_fvp_bloblist test.py: - ${DEFAULT_AMD64_TAG} <<: *buildman_and_testpy_dfn +xilinx_mbv32 test.py: + variables: + TEST_PY_BD: "xilinx_mbv32" + TEST_PY_TEST_SPEC: "not sleep" + TEST_PY_ID: "--id qemu" + <<: *buildman_and_testpy_dfn + +xilinx_mbv32_smode test.py: + variables: + TEST_PY_BD: "xilinx_mbv32_smode" + TEST_PY_TEST_SPEC: "not sleep" + TEST_PY_ID: "--id qemu" + <<: *buildman_and_testpy_dfn + +xilinx_mbv64 test.py: + variables: + TEST_PY_BD: "xilinx_mbv64" + TEST_PY_TEST_SPEC: "not sleep" + TEST_PY_ID: "--id qemu" + <<: *buildman_and_testpy_dfn + +xilinx_mbv64_smode test.py: + variables: + TEST_PY_BD: "xilinx_mbv64_smode" + TEST_PY_TEST_SPEC: "not sleep" + TEST_PY_ID: "--id qemu" + <<: *buildman_and_testpy_dfn + xilinx_zynq_virt test.py: variables: TEST_PY_BD: "xilinx_zynq_virt" -- cgit v1.2.3 From a51b7dfc6fec0aa76367114af59a7114b040b090 Mon Sep 17 00:00:00 2001 From: Venkatesh Yadav Abbarapu Date: Thu, 24 Jul 2025 10:14:02 +0530 Subject: ufs: amd-versal2: Configure RMMI and M-PHY registers for HS mode Configure RMMI and M-PHY registers for HS mode required for selection of bit rate series A or B. If it is not a calibrated part, then switch back to SLOWAUTO_MODE and skip all these configurations. Implemented below sequence as per the DWC RMMI databook. 1. Override RMMI CBRATESEL with the desired rate. 2. Set TX_CFGUPDT_0 to 1'b1 for one TX_CFGCLK_0 cycle. 3. Override PHY rx_req to 1, then poll on PHY rx_ack register till it goes 1(both lanes). 4. Override PHY rx_req to 0, then poll on PHY rx_ack register till it goes 0(both lanes). 5. Remove PHY rx_req override(both lanes). 6. Start the LS PMC. Signed-off-by: Venkatesh Yadav Abbarapu Reviewed-by: Neil Armstrong Link: https://lore.kernel.org/r/20250724044402.260149-1-venkatesh.abbarapu@amd.com Signed-off-by: Michal Simek --- drivers/ufs/ufs-amd-versal2.c | 112 ++++++++++++++++++++++++++++++++++++++++++ drivers/ufs/ufs.c | 15 ++++++ drivers/ufs/ufs.h | 3 ++ drivers/ufs/ufshcd-dwc.h | 3 ++ 4 files changed, 133 insertions(+) diff --git a/drivers/ufs/ufs-amd-versal2.c b/drivers/ufs/ufs-amd-versal2.c index 1c5ed538370..896dda2de4e 100644 --- a/drivers/ufs/ufs-amd-versal2.c +++ b/drivers/ufs/ufs-amd-versal2.c @@ -26,6 +26,10 @@ #define MPHY_FAST_RX_AFE_CAL BIT(2) #define MPHY_FW_CALIB_CFG_VAL BIT(8) +#define MPHY_RX_OVRD_EN BIT(3) +#define MPHY_RX_OVRD_VAL BIT(2) +#define MPHY_RX_ACK_MASK BIT(0) + #define TX_RX_CFG_RDY_MASK GENMASK(3, 0) #define TIMEOUT_MICROSEC 1000000L @@ -422,10 +426,118 @@ static int ufs_versal2_link_startup_notify(struct ufs_hba *hba, return ret; } +static int ufs_versal2_phy_ratesel(struct ufs_hba *hba, u32 activelanes, u32 rx_req) +{ + u32 time_left, reg, lane; + int ret; + + for (lane = 0; lane < activelanes; lane++) { + time_left = TIMEOUT_MICROSEC; + ret = ufs_versal2_phy_reg_read(hba, RX_OVRD_IN_1(lane), ®); + if (ret) + return ret; + + reg |= MPHY_RX_OVRD_EN; + if (rx_req) + reg |= MPHY_RX_OVRD_VAL; + else + reg &= ~MPHY_RX_OVRD_VAL; + + ret = ufs_versal2_phy_reg_write(hba, RX_OVRD_IN_1(lane), reg); + if (ret) + return ret; + + do { + ret = ufs_versal2_phy_reg_read(hba, RX_PCS_OUT(lane), ®); + if (ret) + return ret; + + reg &= MPHY_RX_ACK_MASK; + if (reg == rx_req) + break; + + time_left--; + mdelay(5); + } while (time_left); + + if (!time_left) { + dev_err(hba->dev, "Invalid Rx Ack value.\n"); + return -ETIMEDOUT; + } + } + + return 0; +} + +static int ufs_get_max_pwr_mode(struct ufs_hba *hba, + struct ufs_pwr_mode_info *max_pwr_info) +{ + struct ufs_versal2_priv *priv = dev_get_priv(hba->dev); + u32 lane, reg, rate = 0; + int ret = 0; + + /* If it is not a calibrated part, switch PWRMODE to SLOW_MODE */ + if (!priv->attcompval0 && !priv->attcompval1 && + !priv->ctlecompval0 && !priv->ctlecompval1) { + max_pwr_info->info.pwr_rx = SLOWAUTO_MODE; + max_pwr_info->info.pwr_tx = SLOWAUTO_MODE; + max_pwr_info->info.gear_rx = UFS_PWM_G1; + max_pwr_info->info.gear_tx = UFS_PWM_G1; + max_pwr_info->info.lane_tx = 1; + max_pwr_info->info.lane_rx = 1; + max_pwr_info->info.hs_rate = 0; + return 0; + } + + if (max_pwr_info->info.pwr_rx == SLOWAUTO_MODE || + max_pwr_info->info.pwr_tx == SLOWAUTO_MODE) + return 0; + + if (max_pwr_info->info.hs_rate == PA_HS_MODE_B) + rate = 1; + + /* Select the rate */ + ret = ufshcd_dme_set(hba, UIC_ARG_MIB(CBRATESEL), rate); + if (ret) + return ret; + + ret = ufshcd_dme_set(hba, UIC_ARG_MIB(VS_MPHYCFGUPDT), 1); + if (ret) + return ret; + + ret = ufs_versal2_phy_ratesel(hba, max_pwr_info->info.lane_tx, 1); + if (ret) + return ret; + + ret = ufs_versal2_phy_ratesel(hba, max_pwr_info->info.lane_tx, 0); + if (ret) + return ret; + + /* Remove rx_req override */ + for (lane = 0; lane < max_pwr_info->info.lane_tx; lane++) { + ret = ufs_versal2_phy_reg_read(hba, RX_OVRD_IN_1(lane), ®); + if (ret) + return ret; + + reg &= ~MPHY_RX_OVRD_EN; + ret = ufs_versal2_phy_reg_write(hba, RX_OVRD_IN_1(lane), reg); + if (ret) + return ret; + } + + if (max_pwr_info->info.lane_tx == UFS_LANE_2 && + max_pwr_info->info.lane_rx == UFS_LANE_2) + ret = ufshcd_dme_configure_adapt(hba, max_pwr_info->info.gear_tx, + PA_INITIAL_ADAPT); + + return 0; +} + static struct ufs_hba_ops ufs_versal2_hba_ops = { .init = ufs_versal2_init, .link_startup_notify = ufs_versal2_link_startup_notify, .hce_enable_notify = ufs_versal2_hce_enable_notify, + .get_max_pwr_mode = ufs_get_max_pwr_mode, }; static int ufs_versal2_probe(struct udevice *dev) diff --git a/drivers/ufs/ufs.c b/drivers/ufs/ufs.c index 91f6ad3bfef..57e6e8c013b 100644 --- a/drivers/ufs/ufs.c +++ b/drivers/ufs/ufs.c @@ -226,6 +226,21 @@ static int ufshcd_send_uic_cmd(struct ufs_hba *hba, struct uic_command *uic_cmd) return 0; } +int ufshcd_dme_configure_adapt(struct ufs_hba *hba, + int agreed_gear, + int adapt_val) +{ + int ret; + + if (agreed_gear < UFS_HS_G4) + adapt_val = PA_NO_ADAPT; + + ret = ufshcd_dme_set(hba, + UIC_ARG_MIB(PA_TXHSADAPTTYPE), + adapt_val); + return ret; +} + /** * ufshcd_dme_set_attr - UIC command for DME_SET, DME_PEER_SET * diff --git a/drivers/ufs/ufs.h b/drivers/ufs/ufs.h index 53137fae3a8..0337ac5996b 100644 --- a/drivers/ufs/ufs.h +++ b/drivers/ufs/ufs.h @@ -428,6 +428,9 @@ enum uic_link_state { #define ATTR_SET_NOR 0 /* NORMAL */ #define ATTR_SET_ST 1 /* STATIC */ +int ufshcd_dme_configure_adapt(struct ufs_hba *hba, + int agreed_gear, + int adapt_val); int ufshcd_dme_set_attr(struct ufs_hba *hba, u32 attr_sel, u8 attr_set, u32 mib_val, u8 peer); int ufshcd_dme_get_attr(struct ufs_hba *hba, u32 attr_sel, diff --git a/drivers/ufs/ufshcd-dwc.h b/drivers/ufs/ufshcd-dwc.h index fc1bcca8ccb..f7d27736f44 100644 --- a/drivers/ufs/ufshcd-dwc.h +++ b/drivers/ufs/ufshcd-dwc.h @@ -17,6 +17,7 @@ #define CBREFCLKCTRL2 0x8132 #define CBCRCTRL 0x811F #define CBC10DIRECTCONF2 0x810E +#define CBRATESEL 0x8114 #define CBCREGADDRLSB 0x8116 #define CBCREGADDRMSB 0x8117 #define CBCREGWRLSB 0x8118 @@ -32,6 +33,8 @@ #define MRX_FSM_STATE 0xC1 /* M-PHY registers */ +#define RX_OVRD_IN_1(n) (0x3006 + ((n) * 0x100)) +#define RX_PCS_OUT(n) (0x300F + ((n) * 0x100)) #define FAST_FLAGS(n) (0x401C + ((n) * 0x100)) #define RX_AFE_ATT_IDAC(n) (0x4000 + ((n) * 0x100)) #define RX_AFE_CTLE_IDAC(n) (0x4001 + ((n) * 0x100)) -- cgit v1.2.3 From 88a1816a9b4ef6a202a832c7f59099ddae903e6b Mon Sep 17 00:00:00 2001 From: Dominik Haller Date: Fri, 15 Aug 2025 13:10:48 +0200 Subject: board: phytec: common: Add PHYTEC_EEPROM_BUS to Kconfig Add the option to choose a different bus number than 0 for the i2c eeprom based som detection. Signed-off-by: Dominik Haller Signed-off-by: Wadim Egorov --- board/phytec/common/Kconfig | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/board/phytec/common/Kconfig b/board/phytec/common/Kconfig index 65451a3b20d..08d6e5f3683 100644 --- a/board/phytec/common/Kconfig +++ b/board/phytec/common/Kconfig @@ -59,3 +59,9 @@ config PHYTEC_AM64_SOM_DETECTION help Support of I2C EEPROM based SoM detection. Supported for PHYTEC AM64x boards. + +config PHYTEC_EEPROM_BUS + int "Board EEPROM's I2C bus number" + range 0 8 + default 0 + depends on PHYTEC_SOM_DETECTION -- cgit v1.2.3 From 437f663e6c35bb210a115bbbd295efbd9d9c54a1 Mon Sep 17 00:00:00 2001 From: Dominik Haller Date: Fri, 15 Aug 2025 13:10:49 +0200 Subject: board: phytec: common: k3: Use CONFIG_PHYTEC_EEPROM_BUS Use CONFIG_PHYTEC_EEPROM_BUS instead of the hard coded value for the i2c bus. Signed-off-by: Dominik Haller Signed-off-by: Wadim Egorov --- board/phytec/common/k3/board.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/board/phytec/common/k3/board.c b/board/phytec/common/k3/board.c index 7f34d71d530..50d4a7c0d27 100644 --- a/board/phytec/common/k3/board.c +++ b/board/phytec/common/k3/board.c @@ -182,7 +182,7 @@ static void setup_mac_from_eeprom(void) struct phytec_eeprom_data data; int ret; - ret = phytec_eeprom_data_setup(&data, 0, EEPROM_ADDR); + ret = phytec_eeprom_data_setup(&data, CONFIG_PHYTEC_EEPROM_BUS, EEPROM_ADDR); if (ret || !data.valid) return; @@ -245,7 +245,7 @@ static void fdt_apply_som_overlays(void *blob) memcpy(fdt_copy, blob, fdt_size); - err = phytec_eeprom_data_setup(&data, 0, EEPROM_ADDR); + err = phytec_eeprom_data_setup(&data, CONFIG_PHYTEC_EEPROM_BUS, EEPROM_ADDR); if (err) goto fixup_error; @@ -292,7 +292,7 @@ int ft_board_setup(void *blob, struct bd_info *bd) fdt_apply_som_overlays(blob); fdt_copy_fixed_partitions(blob); - ret = phytec_eeprom_data_setup(&data, 0, EEPROM_ADDR); + ret = phytec_eeprom_data_setup(&data, CONFIG_PHYTEC_EEPROM_BUS, EEPROM_ADDR); if (ret || !data.valid) return 0; -- cgit v1.2.3 From 7e86c8f1dc1dceb50294902f95b3ecf21f8af687 Mon Sep 17 00:00:00 2001 From: Wadim Egorov Date: Fri, 15 Aug 2025 13:10:51 +0200 Subject: configs: phycore_am62ax_a53_defconfig: Resync after savedefconfig Remove PHYTEC_SOM_DETECTION_BLOCKS after it was enabled per default for this platform. Signed-off-by: Wadim Egorov --- configs/phycore_am62ax_a53_defconfig | 1 - 1 file changed, 1 deletion(-) diff --git a/configs/phycore_am62ax_a53_defconfig b/configs/phycore_am62ax_a53_defconfig index 05849d05be4..4ec7fa77865 100644 --- a/configs/phycore_am62ax_a53_defconfig +++ b/configs/phycore_am62ax_a53_defconfig @@ -6,7 +6,6 @@ CONFIG_SPL_LIBCOMMON_SUPPORT=y CONFIG_SPL_LIBGENERIC_SUPPORT=y CONFIG_SOC_K3_AM62A7=y CONFIG_PHYTEC_SOM_DETECTION=y -CONFIG_PHYTEC_SOM_DETECTION_BLOCKS=y CONFIG_TARGET_PHYCORE_AM62AX_A53=y CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x80480000 -- cgit v1.2.3 From 9cf4f522fc96e29df4ab23f5bcbbbe432ae32237 Mon Sep 17 00:00:00 2001 From: Wadim Egorov Date: Fri, 15 Aug 2025 13:10:50 +0200 Subject: board: phytec: phycore-am62a: Update SoM detection Kconfig options Drop SUPPORT_EXTENSION_SCAN and enable PHYTEC_SOM_DETECTION_BLOCKS to align with other PHYTEC platforms. These options were missed when phyCORE-AM62Ax support was added. Signed-off-by: Wadim Egorov --- board/phytec/common/Kconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/board/phytec/common/Kconfig b/board/phytec/common/Kconfig index 08d6e5f3683..a72f66ee3f5 100644 --- a/board/phytec/common/Kconfig +++ b/board/phytec/common/Kconfig @@ -42,7 +42,7 @@ config PHYTEC_AM62A_SOM_DETECTION bool "Support SoM detection for AM62Ax PHYTEC platforms" depends on (TARGET_PHYCORE_AM62AX_A53 || TARGET_PHYCORE_AM62AX_R5) && \ PHYTEC_SOM_DETECTION - select SUPPORT_EXTENSION_SCAN + select PHYTEC_SOM_DETECTION_BLOCKS depends on SPL_I2C && DM_I2C default y help -- cgit v1.2.3 From b5da53046c303d7cff586b366f225dc4c3b64686 Mon Sep 17 00:00:00 2001 From: "Lucien.Jheng" Date: Sun, 17 Aug 2025 23:02:03 +0800 Subject: misc: fs_loader: Add request_firmware_into_buf_via_script() for flexible firmware loading via U-Boot script This commit introduces a new API, request_firmware_into_buf_via_script(), to the fs_loader framework. This function allows firmware to be loaded into memory using a user-defined U-Boot script, providing greater flexibility for firmware loading scenarios that cannot be handled by static file paths or device/partition selection alone. Key features: - The API runs a specified U-Boot script (by name), which is responsible for loading the firmware into memory by any means (e.g., load from MMC, USB, network, etc.). - The script must set two environment variables: 'fw_addr' (the memory address where the firmware is loaded) and 'fw_size' (the size of the firmware in bytes). - The function validates these variables, copies the firmware into a newly allocated buffer (using memdup), and returns the pointer via the provided double pointer argument. - The maximum allowed firmware size is checked to prevent buffer overflows. - The environment variables are cleared after use to avoid stale data. - Detailed error messages are provided for all failure conditions to aid debugging. Usage example: 1. Define a U-Boot script in the environment that loads the firmware and sets the required variables: => env set my_fw_script 'load mmc 0:1 ${loadaddr} firmware.bin && env set fw_addr ${loadaddr} && env set fw_size ${filesize}' 2. In your code, call the new API: void *fw_buf = NULL; int ret = request_firmware_into_buf_via_script(&fw_buf, 0x46000000, "my_fw_script"); if (ret < 0) return ret; This approach allows board integrators and users to customize the firmware loading process without modifying the source code, simply by changing the script in the U-Boot environment. Signed-off-by: Lucien.Jheng Reviewed-by: Marek Vasut [trini: Fix printf of size_t needing to use %zx] Signed-off-by: Tom Rini --- drivers/misc/fs_loader.c | 46 ++++++++++++++++++++++++++++++++++++++++++++++ include/fs_loader.h | 24 ++++++++++++++++++++++++ 2 files changed, 70 insertions(+) diff --git a/drivers/misc/fs_loader.c b/drivers/misc/fs_loader.c index 66803f4b997..60296d55f23 100644 --- a/drivers/misc/fs_loader.c +++ b/drivers/misc/fs_loader.c @@ -228,6 +228,52 @@ int request_firmware_into_buf(struct udevice *dev, return ret; } +int request_firmware_into_buf_via_script(void **buf, size_t max_size, + const char *script_name) +{ + ulong addr, size; + int ret; + char cmd[32]; + + if (!buf || !script_name || !max_size) + return -EINVAL; + + /* Create command to run the firmware loading script */ + snprintf(cmd, sizeof(cmd), "run %s", script_name); + + /* Run the firmware loading script */ + ret = run_command_list(cmd, -1, 0); + if (ret) { + log_err("Firmware loading script '%s' not defined or failed.\n", + script_name); + return -EINVAL; + } + + /* Find out where the firmware got loaded and how long it is */ + addr = env_get_hex("fw_addr", 0); + size = env_get_hex("fw_size", 0); + + /* Clear the variables set by the firmware loading script */ + env_set("fw_addr", NULL); + env_set("fw_size", NULL); + + if (!addr || !size) { + log_err("Firmware address (0x%lx) or size (0x%lx) are invalid.\n", + addr, size); + return -EINVAL; + } + + if (size > max_size) { + log_err("Loaded firmware size 0x%lx exceeded maximum allowed size 0x%zx.\n", + size, max_size); + return -E2BIG; + } + + memcpy(*buf, (void *)addr, size); + + return 0; +} + static int fs_loader_of_to_plat(struct udevice *dev) { u32 phandlepart[2]; diff --git a/include/fs_loader.h b/include/fs_loader.h index 5eb5b7ab4a1..a433be1eb99 100644 --- a/include/fs_loader.h +++ b/include/fs_loader.h @@ -64,4 +64,28 @@ int request_firmware_into_buf(struct udevice *dev, * Return: 0 on success, negative value on error */ int get_fs_loader(struct udevice **dev); + +/** + * request_firmware_into_buf_via_script() - + * Load firmware using a U-Boot script and copy to buffer + * @buf: Pointer to a pointer where the firmware buffer will be stored. + * @max_size: Maximum allowed size for the firmware to be loaded. + * @script_name: Name of the U-Boot script to execute for firmware loading. + * + * Executes a U-Boot script (@script_name) that loads firmware into + * memory and sets the environment variables 'fw_addr' (address) and + * 'fw_size' (size in bytes). On success, copies the firmware + * from the given address to user buffer @buf. + * + * The script must set these environment variables: + * fw_addr - Address where firmware is loaded in memory + * fw_size - Size of the firmware in bytes + * + * The script should be defined in the U-Boot environment, for example: + * env set script_name 'load mmc 0:1 ${loadaddr} firmware.bin && + * env set fw_addr ${loadaddr} && env set fw_size ${filesize} + * Return: 0 on success, negative value on error. + */ +int request_firmware_into_buf_via_script(void **buf, size_t max_size, + const char *script_name); #endif -- cgit v1.2.3 From 377159bfb8ee35ce16200818cfa55cdfba8c69e9 Mon Sep 17 00:00:00 2001 From: Andrew Goodbody Date: Thu, 24 Jul 2025 16:32:55 +0100 Subject: ddr: fsl: Provide initial value for zqcs_init In the case of !zq_en zqcs_init is never assigned to although its value is used. Correct by initialising zqcs_init to 0. This issue was found by Smatch. Signed-off-by: Andrew Goodbody Signed-off-by: Peng Fan --- drivers/ddr/fsl/ctrl_regs.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/ddr/fsl/ctrl_regs.c b/drivers/ddr/fsl/ctrl_regs.c index 9a25192c079..fea08c9000f 100644 --- a/drivers/ddr/fsl/ctrl_regs.c +++ b/drivers/ddr/fsl/ctrl_regs.c @@ -2173,7 +2173,7 @@ static void set_ddr_zq_cntl(fsl_ddr_cfg_regs_t *ddr, unsigned int zq_en) /* Normal Operation Short Calibration Time (tZQCS) */ unsigned int zqcs = 0; #ifdef CONFIG_SYS_FSL_DDR4 - unsigned int zqcs_init; + unsigned int zqcs_init = 0; #endif if (zq_en) { -- cgit v1.2.3 From 44d321f0092a42b2295bd6eac41199604cf7d8c9 Mon Sep 17 00:00:00 2001 From: Andrew Goodbody Date: Mon, 4 Aug 2025 17:03:57 +0100 Subject: net: fm: Correct test for timeout In bmi_rx_port_disable and bmi_tx_port_disable the use of post-decrement on the test in the while loop for a timeout means that timeout will be equal to -1 on exit in that case. Adjust the test for this expected value. This issue was found by Smatch. Signed-off-by: Andrew Goodbody Signed-off-by: Peng Fan --- drivers/net/fm/eth.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/net/fm/eth.c b/drivers/net/fm/eth.c index 63fe4b2d33c..c83b789693a 100644 --- a/drivers/net/fm/eth.c +++ b/drivers/net/fm/eth.c @@ -169,7 +169,7 @@ static void bmi_rx_port_disable(struct fm_bmi_rx_port *rx_port) /* wait until the rx port is not busy */ while ((in_be32(&rx_port->fmbm_rst) & FMBM_RST_BSY) && timeout--) ; - if (!timeout) + if (timeout == -1) printf("%s - timeout\n", __func__); } @@ -199,7 +199,7 @@ static void bmi_tx_port_disable(struct fm_bmi_tx_port *tx_port) /* wait until the tx port is not busy */ while ((in_be32(&tx_port->fmbm_tst) & FMBM_TST_BSY) && timeout--) ; - if (!timeout) + if (timeout == -1) printf("%s - timeout\n", __func__); } -- cgit v1.2.3 From 270798a4209aeb23fce72ebf10e62630f474e431 Mon Sep 17 00:00:00 2001 From: Andrew Goodbody Date: Mon, 4 Aug 2025 17:03:58 +0100 Subject: net: fm: NULL check dev before dereference In fm_eth_bind there is a dereference of dev before it is NULL checked. Add a NULL check before the first dereference and remove a later NULL check that is now redundant. This issue was found by Smatch. Signed-off-by: Andrew Goodbody Signed-off-by: Peng Fan --- drivers/net/fm/eth.c | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/drivers/net/fm/eth.c b/drivers/net/fm/eth.c index c83b789693a..f0e7c0eca42 100644 --- a/drivers/net/fm/eth.c +++ b/drivers/net/fm/eth.c @@ -727,12 +727,15 @@ static int fm_eth_bind(struct udevice *dev) char mac_name[11]; u32 fm, num; + if (!dev) + return -EINVAL; + if (ofnode_read_u32(ofnode_get_parent(dev_ofnode(dev)), "cell-index", &fm)) { printf("FMan node property cell-index missing\n"); return -EINVAL; } - if (dev && dev_read_u32(dev, "cell-index", &num)) { + if (dev_read_u32(dev, "cell-index", &num)) { printf("FMan MAC node property cell-index missing\n"); return -EINVAL; } -- cgit v1.2.3 From 5b95f666fbd8f9c9c43726c7ced229762e4a35e0 Mon Sep 17 00:00:00 2001 From: Andrew Goodbody Date: Mon, 4 Aug 2025 17:03:59 +0100 Subject: net: fm: Correct test for timeout In memac_wait_until_free and memac_wait_until_done the use of post-decrement on the test in the while loop for a timeout means that timeout will be equal to -1 on exit in that case. Adjust the test for this expected value. This issue was found by Smatch. Signed-off-by: Andrew Goodbody Signed-off-by: Peng Fan --- drivers/net/fm/memac_phy.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/net/fm/memac_phy.c b/drivers/net/fm/memac_phy.c index 26425d94ae5..1ad3c053593 100644 --- a/drivers/net/fm/memac_phy.c +++ b/drivers/net/fm/memac_phy.c @@ -46,7 +46,7 @@ static int memac_wait_until_free(struct memac_mdio_controller *regs) while ((memac_in_32(®s->mdio_stat) & MDIO_STAT_BSY) && timeout--) ; - if (!timeout) { + if (timeout == -1) { printf("timeout waiting for MDIO bus to be free\n"); return -ETIMEDOUT; } @@ -64,7 +64,7 @@ static int memac_wait_until_done(struct memac_mdio_controller *regs) while ((memac_in_32(®s->mdio_stat) & MDIO_STAT_BSY) && timeout--) ; - if (!timeout) { + if (timeout == -1) { printf("timeout waiting for MDIO operation to complete\n"); return -ETIMEDOUT; } -- cgit v1.2.3 From f4c2a12611d3ffdbd624ededf0fce192f26dddaf Mon Sep 17 00:00:00 2001 From: Andrew Goodbody Date: Mon, 4 Aug 2025 17:56:55 +0100 Subject: net: fsl_enetc: Fix copy/paste error In netc_blk_ctrl_probe the test for failure of the function clk_prepare_enable should not return PTR_ERR(ipg_clk) as it does not check IS_ERR(ipg_clk) instead it should return err as that is what is holding the error code in this case. This issue was found by Smatch. Signed-off-by: Andrew Goodbody Signed-off-by: Peng Fan --- drivers/net/fsl_enetc_netc_blk_ctrl.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/net/fsl_enetc_netc_blk_ctrl.c b/drivers/net/fsl_enetc_netc_blk_ctrl.c index 46b68d3d8a4..fecd66eb15a 100644 --- a/drivers/net/fsl_enetc_netc_blk_ctrl.c +++ b/drivers/net/fsl_enetc_netc_blk_ctrl.c @@ -293,7 +293,7 @@ static int netc_blk_ctrl_probe(struct udevice *dev) err = clk_prepare_enable(ipg_clk); if (err) { dev_err(dev, "Enable ipg clock failed\n"); - return PTR_ERR(ipg_clk); + return err; } regs = dev_read_addr_name(dev, "ierb"); -- cgit v1.2.3 From 756580d090e5dcb3c45d1f0147cc596ae4efd961 Mon Sep 17 00:00:00 2001 From: Andrew Goodbody Date: Mon, 4 Aug 2025 17:56:56 +0100 Subject: net: fsl-mc: NULL check dflt_dpio before dereference In dpio_exit there is a NULL check for dflt_dpio but it happens after dpio_dflt has been dereferenced a number of times already. Instead move the NULL check to first thing in the function. Also assign NULL to dflt_dpio after free in both dpio_init and dpio_exit. This issue was found by Smatch. Signed-off-by: Andrew Goodbody Signed-off-by: Peng Fan --- drivers/net/fsl-mc/mc.c | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) diff --git a/drivers/net/fsl-mc/mc.c b/drivers/net/fsl-mc/mc.c index 86daf0fb2bb..999a9912e2f 100644 --- a/drivers/net/fsl-mc/mc.c +++ b/drivers/net/fsl-mc/mc.c @@ -1178,6 +1178,7 @@ err_get_api_ver: dflt_dpio->dpio_id); err_create: free(dflt_dpio); + dflt_dpio = NULL; err_calloc: return err; } @@ -1186,6 +1187,9 @@ static int dpio_exit(void) { int err; + if (!dflt_dpio) + return -ENODEV; + err = dpio_disable(dflt_mc_io, MC_CMD_NO_FLAGS, dflt_dpio->dpio_handle); if (err < 0) { printf("dpio_disable() failed: %d\n", err); @@ -1211,8 +1215,8 @@ static int dpio_exit(void) printf("Exit: DPIO.%d\n", dflt_dpio->dpio_id); #endif - if (dflt_dpio) - free(dflt_dpio); + free(dflt_dpio); + dflt_dpio = NULL; return 0; err: -- cgit v1.2.3 From 9ca756cee7e8f9d6ecc0a69fa785caabd61f3f6a Mon Sep 17 00:00:00 2001 From: Andrew Goodbody Date: Mon, 4 Aug 2025 17:56:57 +0100 Subject: net: fsl-mc: NULL check dflt_dpbp before dereference In dpbp_exit there is a NULL check for dflt_dpbp after it is dereferenced a number of times. Instead move the NULL check to early in the function. Also assign NULL to dflt_dpbp after free in both dpbp_init and dpbp_exit. This issue was found by Smatch. Signed-off-by: Andrew Goodbody Signed-off-by: Peng Fan --- drivers/net/fsl-mc/mc.c | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) diff --git a/drivers/net/fsl-mc/mc.c b/drivers/net/fsl-mc/mc.c index 999a9912e2f..8c882c7fcf5 100644 --- a/drivers/net/fsl-mc/mc.c +++ b/drivers/net/fsl-mc/mc.c @@ -1438,6 +1438,7 @@ err_close: err_open: err_create: free(dflt_dpbp); + dflt_dpbp = NULL; err_calloc: return err; } @@ -1446,6 +1447,9 @@ static int dpbp_exit(void) { int err; + if (!dflt_dpbp) + return -ENODEV; + err = dpbp_destroy(dflt_mc_io, dflt_dprc_handle, MC_CMD_NO_FLAGS, dflt_dpbp->dpbp_id); if (err < 0) { @@ -1457,8 +1461,8 @@ static int dpbp_exit(void) printf("Exit: DPBP.%d\n", dflt_dpbp->dpbp_attr.id); #endif - if (dflt_dpbp) - free(dflt_dpbp); + free(dflt_dpbp); + dflt_dpbp = NULL; return 0; err: -- cgit v1.2.3 From 010a4c5c553763430b3e9628ae2c82de3d5f45dd Mon Sep 17 00:00:00 2001 From: Andrew Goodbody Date: Mon, 4 Aug 2025 17:56:58 +0100 Subject: net: fsl-mc: NULL check dflt_dpni before dereference In dpni_exit there is a NULL check for dflt_dpni after it is dereferenced a number of times. Instead move the NULL check to early in the function. Also assign NULL to dflt_dpni after free in both dpni_init and dpni_exit. This issue was found by Smatch. Signed-off-by: Andrew Goodbody Signed-off-by: Peng Fan --- drivers/net/fsl-mc/mc.c | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) diff --git a/drivers/net/fsl-mc/mc.c b/drivers/net/fsl-mc/mc.c index 8c882c7fcf5..aad852f8151 100644 --- a/drivers/net/fsl-mc/mc.c +++ b/drivers/net/fsl-mc/mc.c @@ -1539,6 +1539,7 @@ err_get_version: dflt_dpni->dpni_id); err_create: free(dflt_dpni); + dflt_dpni = NULL; err_calloc: return err; } @@ -1547,6 +1548,9 @@ static int dpni_exit(void) { int err; + if (!dflt_dpni) + return -ENODEV; + err = dpni_destroy(dflt_mc_io, dflt_dprc_handle, MC_CMD_NO_FLAGS, dflt_dpni->dpni_id); if (err < 0) { @@ -1558,8 +1562,8 @@ static int dpni_exit(void) printf("Exit: DPNI.%d\n", dflt_dpni->dpni_id); #endif - if (dflt_dpni) - free(dflt_dpni); + free(dflt_dpni); + dflt_dpni = NULL; return 0; err: -- cgit v1.2.3 From 05b11146363039a00bff09c77be077ebdaf1f5d0 Mon Sep 17 00:00:00 2001 From: Andrew Goodbody Date: Mon, 4 Aug 2025 17:56:59 +0100 Subject: net: fsl-mc: Incorrect variable used in error path In mc_fixup_dpc_mac_addr noff is assigned the return value from fdt_add_subnode so that is the variable that should be passed to fdt_strerror and returned when negative. This issue was found by Smatch. Signed-off-by: Andrew Goodbody Signed-off-by: Peng Fan --- drivers/net/fsl-mc/mc.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/net/fsl-mc/mc.c b/drivers/net/fsl-mc/mc.c index aad852f8151..c8ed702f50a 100644 --- a/drivers/net/fsl-mc/mc.c +++ b/drivers/net/fsl-mc/mc.c @@ -366,8 +366,8 @@ static int mc_fixup_dpc_mac_addr(void *blob, int dpmac_id, noff = fdt_add_subnode(blob, nodeoffset, mac_name); if (noff < 0) { printf("fdt_add_subnode: err=%s\n", - fdt_strerror(err)); - return err; + fdt_strerror(noff)); + return noff; } /* add default property of fixed link */ -- cgit v1.2.3 From dc37adfc040877db359abdc7eab19adffb8fc722 Mon Sep 17 00:00:00 2001 From: Andrew Goodbody Date: Fri, 8 Aug 2025 11:29:33 +0100 Subject: drivers: qe: avoid double free() Avoid calling free(addr) twice if the device for ucode is not found. This patch repeats a similar fix but that only applied to code without CONFIG_TFABOOT enabled. This patch applies to the code with CONFIG_TFABOOT enabled. This issue was found by Smatch. Signed-off-by: Andrew Goodbody Signed-off-by: Peng Fan --- drivers/qe/qe.c | 1 - 1 file changed, 1 deletion(-) diff --git a/drivers/qe/qe.c b/drivers/qe/qe.c index 69b7de084e5..25880db37cf 100644 --- a/drivers/qe/qe.c +++ b/drivers/qe/qe.c @@ -255,7 +255,6 @@ void u_qe_init(void) struct mmc *mmc = find_mmc_device(CONFIG_ENV_MMC_DEVICE_INDEX); if (!mmc) { - free(addr); printf("\nMMC cannot find device for ucode\n"); } else { printf("\nMMC read: dev # %u, block # %u, count %u ...\n", -- cgit v1.2.3 From 4d3183723f34d58cb5decec77e8bf64b84d309d1 Mon Sep 17 00:00:00 2001 From: Andrew Goodbody Date: Mon, 11 Aug 2025 17:25:17 +0100 Subject: serial: lpuart: Return value from correct variable In get_lpuart_clk_rate if the call to clk_get_rate returns an error then the call to return should pass the value of the error which is in rate rather than ret which will be 0 as its value is not affected by this error. This issue was found by Smatch. Signed-off-by: Andrew Goodbody Signed-off-by: Peng Fan --- drivers/serial/serial_lpuart.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/serial/serial_lpuart.c b/drivers/serial/serial_lpuart.c index 93602797b83..9fdb6503085 100644 --- a/drivers/serial/serial_lpuart.c +++ b/drivers/serial/serial_lpuart.c @@ -129,7 +129,7 @@ static int get_lpuart_clk_rate(struct udevice *dev, u32 *clk_rate) rate = clk_get_rate(&clk); if ((long)rate <= 0) { dev_err(dev, "Failed to get clk rate: %ld\n", (long)rate); - return ret; + return rate; } *clk_rate = rate; return 0; -- cgit v1.2.3 From 1363f9c1a0652448687a4a457507881aa1670ba2 Mon Sep 17 00:00:00 2001 From: Tomas Alvarez Vanoli Date: Wed, 20 Aug 2025 10:17:19 +0200 Subject: fsl_dspi: set scaler values for CS-SCK and SCK-CS delays These values were calculated but not set. They are required for the calculation of the delays, as stated in the "QorIQ LS1043A Reference Manual, Rev. 6, 07/2020" page 2172. The delays are calculated as (1/freq)*PCSSCK*CSSCK and (1/freq)*PASC*ASC. Signed-off-by: Tomas Alvarez Vanoli Reviewed-by: Vladimir Oltean Signed-off-by: Peng Fan --- drivers/spi/fsl_dspi.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/drivers/spi/fsl_dspi.c b/drivers/spi/fsl_dspi.c index 545561ad116..412993ad377 100644 --- a/drivers/spi/fsl_dspi.c +++ b/drivers/spi/fsl_dspi.c @@ -473,7 +473,9 @@ static int fsl_dspi_child_pre_probe(struct udevice *dev) priv->ctar_val[slave_plat->cs[0]] = DSPI_CTAR_DEFAULT_VALUE | DSPI_CTAR_PCSSCK(pcssck) | - DSPI_CTAR_PASC(pasc); + DSPI_CTAR_CSSCK(cssck) | + DSPI_CTAR_PASC(pasc) | + DSPI_CTAR_ASC(asc); debug("DSPI pre_probe slave device on CS %u, max_hz %u, mode 0x%x.\n", slave_plat->cs[0], slave_plat->max_hz, slave_plat->mode); -- cgit v1.2.3 From 8b97d7569a48d15949cc9274f40bae013e24a2a4 Mon Sep 17 00:00:00 2001 From: "Anthony Pighin (Nokia)" Date: Wed, 27 Aug 2025 16:12:21 +0800 Subject: drivers: crypto: fsl: rng: Reinitialize job ring u-boot internals were being corrupted following an EFI callback to get_rng(). One of the many footprints was a corruption of the EFI protocols linked list. A request for >16 bytes of random data is broken into smaller requests. Those requests are fed in a loop to the CAAM RNG, which uses a job queue ring for interaction. However, the job queue descriptor is created only at probe time. That descriptor may end up needing an endian swap (LS1046A) before being fed to the CAAM RNG. This corrupts the descriptor for the next iteration, since it will be blindly endian swapped yet again. Two issues arise. The number of words to endian swap is taken from the input descriptor itself. So on the second iteration, the length has been corrupted. This results in a corruption past the end of the descriptor: whatever is after in memory is endian swapped too. Second, some of the entries in the descriptor are DMA addresses. If the descriptor is still somehow considered valid after swapping, the data at the corrupted DMA address is now trampled. Linux properly initializes the descriptor for each iteration. This is what is now done with this commit. Signed-off-by: Anthony Pighin Signed-off-by: Peng Fan --- drivers/crypto/fsl/rng.c | 21 ++++++++++++++++----- 1 file changed, 16 insertions(+), 5 deletions(-) diff --git a/drivers/crypto/fsl/rng.c b/drivers/crypto/fsl/rng.c index 786a710f5fb..06f37a8b4de 100644 --- a/drivers/crypto/fsl/rng.c +++ b/drivers/crypto/fsl/rng.c @@ -23,11 +23,26 @@ struct caam_rng_priv { u8 data[CAAM_RNG_MAX_FIFO_STORE_SIZE] __aligned(ARCH_DMA_MINALIGN); }; +static int caam_init_desc(struct caam_rng_priv *priv) +{ + ulong size = ALIGN(CAAM_RNG_DESC_LEN, ARCH_DMA_MINALIGN); + + inline_cnstr_jobdesc_rng(priv->desc, priv->data, + CAAM_RNG_MAX_FIFO_STORE_SIZE); + + flush_dcache_range((unsigned long)priv->desc, + (unsigned long)priv->desc + size); + + return 0; +} + static int caam_rng_read_one(struct caam_rng_priv *priv) { int size = ALIGN(CAAM_RNG_MAX_FIFO_STORE_SIZE, ARCH_DMA_MINALIGN); int ret; + caam_init_desc(priv); + ret = run_descriptor_jr(priv->desc); if (ret < 0) return -EIO; @@ -63,12 +78,8 @@ static int caam_rng_read(struct udevice *dev, void *data, size_t len) static int caam_rng_probe(struct udevice *dev) { struct caam_rng_priv *priv = dev_get_priv(dev); - ulong size = ALIGN(CAAM_RNG_DESC_LEN, ARCH_DMA_MINALIGN); - inline_cnstr_jobdesc_rng(priv->desc, priv->data, - CAAM_RNG_MAX_FIFO_STORE_SIZE); - flush_dcache_range((unsigned long)priv->desc, - (unsigned long)priv->desc + size); + caam_init_desc(priv); return 0; } -- cgit v1.2.3 From 446b7b8f2d9b5b9bcd473c91f1e45cbb77be6c5f Mon Sep 17 00:00:00 2001 From: Andrew Goodbody Date: Thu, 7 Aug 2025 15:28:57 +0100 Subject: power: axp: Remove redundant code In axp_init after checking the chip ID there is an else clause that returns ret. ret is guaranteed to be 0 at this point as the code would have returned above if not. The next statement is a return 0 so the return ret is redundant, remove it. This issue was found by Smatch. Signed-off-by: Andrew Goodbody Reviewed-by: Quentin Schulz --- drivers/power/axp818.c | 2 -- 1 file changed, 2 deletions(-) diff --git a/drivers/power/axp818.c b/drivers/power/axp818.c index 83ae6ecc138..01f9a209dc6 100644 --- a/drivers/power/axp818.c +++ b/drivers/power/axp818.c @@ -248,8 +248,6 @@ int axp_init(void) if (!(axp_chip_id == 0x51)) return -ENODEV; - else - return ret; return 0; } -- cgit v1.2.3 From aa136393c8fd448e903e3fd3297efb13e54c42d7 Mon Sep 17 00:00:00 2001 From: Andrew Goodbody Date: Thu, 7 Aug 2025 15:28:58 +0100 Subject: power: power_i2c: ret is uninitialised if not DM_I2C In pmic_reg_read ret is only assigned to inside #if CONFIG_IS_ENABLED(DM_I2C) so move the test and return ret inside as well and also guard the declaration of ret with CONFIG_IS_ENABLED(DM_I2C) to prevent a warning about an unused variable. This issue was found by Smatch. Signed-off-by: Andrew Goodbody Reviewed-by: Quentin Schulz --- drivers/power/power_i2c.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/power/power_i2c.c b/drivers/power/power_i2c.c index c2fc1c6b42f..58289ecce67 100644 --- a/drivers/power/power_i2c.c +++ b/drivers/power/power_i2c.c @@ -75,7 +75,7 @@ int pmic_reg_read(struct pmic *p, u32 reg, u32 *val) { unsigned char buf[4] = { 0 }; u32 ret_val = 0; - int ret; + int __maybe_unused ret; if (check_reg(p, reg)) return -EINVAL; @@ -91,9 +91,9 @@ int pmic_reg_read(struct pmic *p, u32 reg, u32 *val) return -ENXIO; } ret = dm_i2c_read(dev, reg, buf, pmic_i2c_tx_num); -#endif if (ret) return ret; +#endif switch (pmic_i2c_tx_num) { case 3: -- cgit v1.2.3 From 42f959d0b091b779f235d7d0e54a794d4d857917 Mon Sep 17 00:00:00 2001 From: Andrew Goodbody Date: Thu, 7 Aug 2025 17:35:18 +0100 Subject: power: regulator: lp873x: Cannot test unsigned for being negative In lp873x_buck_val and lp873x_ldo_val hex is an unsigned variable being assigned the return value from a function that returns int. Change hex to be an int so that the following test for an error as a negative value will work as expected. This issue was found by Smatch. Signed-off-by: Andrew Goodbody Reviewed-by: Frieder Schrempf --- drivers/power/regulator/lp873x_regulator.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/drivers/power/regulator/lp873x_regulator.c b/drivers/power/regulator/lp873x_regulator.c index 271a7e45139..62d91a23f77 100644 --- a/drivers/power/regulator/lp873x_regulator.c +++ b/drivers/power/regulator/lp873x_regulator.c @@ -83,8 +83,8 @@ static int lp873x_buck_hex2volt(int hex) static int lp873x_buck_val(struct udevice *dev, int op, int *uV) { - unsigned int hex, adr; - int ret; + unsigned int adr; + int hex, ret; struct dm_regulator_uclass_plat *uc_pdata; uc_pdata = dev_get_uclass_plat(dev); @@ -177,8 +177,8 @@ static int lp873x_ldo_hex2volt(int hex) static int lp873x_ldo_val(struct udevice *dev, int op, int *uV) { - unsigned int hex, adr; - int ret; + unsigned int adr; + int hex, ret; struct dm_regulator_uclass_plat *uc_pdata; -- cgit v1.2.3 From 8f90028ccdbfc74487c4b40bd6fe5d34c3309b7a Mon Sep 17 00:00:00 2001 From: Andrew Goodbody Date: Thu, 7 Aug 2025 17:35:19 +0100 Subject: power: regulator: lp87565: Cannot test unsigned for being negative In lp87565_buck_val hex is an unsigned variable being assigned the return value from a function that returns int. Change hex to be an int so that the following test for an error as a negative value will work as expected. This issue was found by Smatch. Signed-off-by: Andrew Goodbody Reviewed-by: Frieder Schrempf --- drivers/power/regulator/lp87565_regulator.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/power/regulator/lp87565_regulator.c b/drivers/power/regulator/lp87565_regulator.c index 2212cb5c651..ea9c7685e9f 100644 --- a/drivers/power/regulator/lp87565_regulator.c +++ b/drivers/power/regulator/lp87565_regulator.c @@ -82,8 +82,8 @@ static int lp87565_buck_val2volt(int val) static int lp87565_buck_val(struct udevice *dev, int op, int *uV) { - unsigned int hex, adr; - int ret; + unsigned int adr; + int hex, ret; struct dm_regulator_uclass_plat *uc_pdata; uc_pdata = dev_get_uclass_plat(dev); -- cgit v1.2.3 From 96312ed79630838b09368c8c07ec164fd40a025c Mon Sep 17 00:00:00 2001 From: Andrew Goodbody Date: Thu, 7 Aug 2025 17:35:20 +0100 Subject: power: regulator: palmas: Cannot test unsigned for being negative In palmas_smps_val and palmas_ldo_val hex is an unsigned variable being assigned the return value from a function that returns int. Change hex to be an int so that the following test for an error as a negative value will work as expected. This issue was found by Smatch. Signed-off-by: Andrew Goodbody Reviewed-by: Frieder Schrempf --- drivers/power/regulator/palmas_regulator.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/drivers/power/regulator/palmas_regulator.c b/drivers/power/regulator/palmas_regulator.c index 2286eac93fb..7212062c8c8 100644 --- a/drivers/power/regulator/palmas_regulator.c +++ b/drivers/power/regulator/palmas_regulator.c @@ -115,8 +115,8 @@ static int palmas_smps_hex2volt(int hex, bool range) static int palmas_smps_val(struct udevice *dev, int op, int *uV) { - unsigned int hex, adr; - int ret; + unsigned int adr; + int hex, ret; bool range; struct dm_regulator_uclass_plat *uc_pdata; @@ -251,8 +251,8 @@ static int palmas_ldo_hex2volt(int hex) static int palmas_ldo_val(struct udevice *dev, int op, int *uV) { - unsigned int hex, adr; - int ret; + unsigned int adr; + int hex, ret; struct dm_regulator_uclass_plat *uc_pdata; -- cgit v1.2.3 From cdc0e32e9c56fc3d14007d4c93394e8bcc8daa08 Mon Sep 17 00:00:00 2001 From: Andrew Goodbody Date: Thu, 7 Aug 2025 17:35:21 +0100 Subject: power: regulator: rzg2l-usbphy: Add parenthesis to return expression In order to get the expected result from rzg2l_usbphy_regulator_get_enable the return expression needs parenthesis so that the binary and is performed before the double logical not. This issue was found by Smatch. Signed-off-by: Andrew Goodbody Reviewed-by: Frieder Schrempf --- drivers/power/regulator/rzg2l-usbphy-regulator.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/power/regulator/rzg2l-usbphy-regulator.c b/drivers/power/regulator/rzg2l-usbphy-regulator.c index 451f04c140e..0354555d0b5 100644 --- a/drivers/power/regulator/rzg2l-usbphy-regulator.c +++ b/drivers/power/regulator/rzg2l-usbphy-regulator.c @@ -27,7 +27,7 @@ static int rzg2l_usbphy_regulator_get_enable(struct udevice *dev) { struct rzg2l_usbphy_ctrl_priv *priv = dev_get_priv(dev->parent); - return !!readl(priv->regs + VBENCTL) & VBENCTL_VBUS_SEL; + return !!(readl(priv->regs + VBENCTL) & VBENCTL_VBUS_SEL); } static const struct dm_regulator_ops rzg2l_usbphy_regulator_ops = { -- cgit v1.2.3 From c18435e648f7004dee1a80d06dbc06223d3b76b3 Mon Sep 17 00:00:00 2001 From: Andrew Goodbody Date: Thu, 7 Aug 2025 17:35:23 +0100 Subject: power: regulator: tps65941: Cannot test unsigned for being negative In tps65941_buck_val and tps65941_ldo_val hex is an unsigned variable being assigned the return value from a function that returns int. Change hex to be an int so that the following test for an error as a negative value will work as expected. This issue was found by Smatch. Signed-off-by: Andrew Goodbody Reviewed-by: Frieder Schrempf --- drivers/power/regulator/tps65941_regulator.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/drivers/power/regulator/tps65941_regulator.c b/drivers/power/regulator/tps65941_regulator.c index 13f94b730d4..2561d6f4c6c 100644 --- a/drivers/power/regulator/tps65941_regulator.c +++ b/drivers/power/regulator/tps65941_regulator.c @@ -277,8 +277,8 @@ static const struct tps65941_reg_conv_ops buck_conv_ops[] = { static int tps65941_buck_val(struct udevice *dev, int op, int *uV) { - unsigned int hex, adr; - int ret, delta, uwait, slew, idx; + unsigned int adr; + int hex, ret, delta, uwait, slew, idx; struct dm_regulator_uclass_plat *uc_pdata; const struct tps65941_reg_conv_ops *conv_ops; ulong chip_id; @@ -479,8 +479,8 @@ static const struct tps65941_reg_conv_ops ldo_conv_ops[] = { static int tps65941_ldo_val(struct udevice *dev, int op, int *uV) { - unsigned int hex, adr; - int ret, ret_volt, idx, ldo_bypass; + unsigned int adr; + int hex, ret, ret_volt, idx, ldo_bypass; struct dm_regulator_uclass_plat *uc_pdata; const struct tps65941_reg_conv_ops *conv_ops; ulong chip_id; -- cgit v1.2.3 From 31a309ff3eca5a9bb4fa8228d5270d792e7e0522 Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Fri, 4 Jul 2025 15:50:20 -0600 Subject: power: Correct dependencies on POWER_LEGACY The POWER_LEGACY option functionally depends on not having DM_PMIC enabled, so add that here. Signed-off-by: Tom Rini --- drivers/power/Kconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/power/Kconfig b/drivers/power/Kconfig index eed65058e66..fd1c871f0db 100644 --- a/drivers/power/Kconfig +++ b/drivers/power/Kconfig @@ -15,6 +15,7 @@ if POWER config POWER_LEGACY bool "Legacy power support" + depends on !DM_PMIC help Note: This is a legacy option. Use DM_PMIC instead. -- cgit v1.2.3 From 9d875d674ff830a6036153a4c390c75267e775b6 Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Fri, 4 Jul 2025 15:50:21 -0600 Subject: power: Split *POWER_LEGACY portion of out to new header The commends in include/power/pmic.h say that once SPL_DM_PMIC exists we should update things. This has been true for some time, so let us update this to have the legacy portions in their own header, which should not be directly included. This cleans up the logic within the file too slightly. Signed-off-by: Tom Rini --- include/power/pmic.h | 89 ++---------------------------------------- include/power/pmic_legacy.h | 94 +++++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 97 insertions(+), 86 deletions(-) create mode 100644 include/power/pmic_legacy.h diff --git a/include/power/pmic.h b/include/power/pmic.h index 636221692d0..4aee07383a9 100644 --- a/include/power/pmic.h +++ b/include/power/pmic.h @@ -17,76 +17,9 @@ enum { PMIC_I2C, PMIC_SPI, PMIC_NONE}; -/* TODO: Change to !CONFIG_IS_ENABLED(DM_PMIC) when SPL_DM_PMIC exists */ #if CONFIG_IS_ENABLED(POWER_LEGACY) -enum { I2C_PMIC, I2C_NUM, }; -enum { PMIC_READ, PMIC_WRITE, }; -enum { PMIC_SENSOR_BYTE_ORDER_LITTLE, PMIC_SENSOR_BYTE_ORDER_BIG, }; - -enum { - PMIC_CHARGER_DISABLE, - PMIC_CHARGER_ENABLE, -}; - -struct p_i2c { - unsigned char addr; - unsigned char *buf; - unsigned char tx_num; -}; - -struct p_spi { - unsigned int cs; - unsigned int mode; - unsigned int bitlen; - unsigned int clk; - unsigned int flags; - u32 (*prepare_tx)(u32 reg, u32 *val, u32 write); -}; - -struct pmic; -struct power_fg { - int (*fg_battery_check) (struct pmic *p, struct pmic *bat); - int (*fg_battery_update) (struct pmic *p, struct pmic *bat); -}; - -struct power_chrg { - int (*chrg_type) (struct pmic *p); - int (*chrg_bat_present) (struct pmic *p); - int (*chrg_state) (struct pmic *p, int state, int current); -}; - -struct power_battery { - struct battery *bat; - int (*battery_init) (struct pmic *bat, struct pmic *p1, - struct pmic *p2, struct pmic *p3); - int (*battery_charge) (struct pmic *bat); - /* Keep info about power devices involved with battery operation */ - struct pmic *chrg, *fg, *muic; -}; - -struct pmic { - const char *name; - unsigned char bus; - unsigned char interface; - unsigned char sensor_byte_order; - unsigned int number_of_regs; - union hw { - struct p_i2c i2c; - struct p_spi spi; - } hw; - - void (*low_power_mode) (void); - struct power_battery *pbat; - struct power_chrg *chrg; - struct power_fg *fg; - - struct pmic *parent; - struct list_head list; -}; -#endif /* CONFIG_IS_ENABLED(POWER_LEGACY) */ - -/* TODO: Change to CONFIG_IS_ENABLED(DM_PMIC) when SPL_DM_PMIC exists */ -#if defined(CONFIG_DM_PMIC) || !CONFIG_IS_ENABLED(POWER_LEGACY) +#include +#else /** * U-Boot PMIC Framework * ===================== @@ -308,23 +241,7 @@ struct uc_pmic_priv { uint trans_len; }; -#endif /* DM_PMIC */ - -/* TODO: Change to CONFIG_IS_ENABLED(DM_PMIC) when SPL_DM_PMIC exists */ -#if CONFIG_IS_ENABLED(POWER_LEGACY) - -/* Legacy API, do not use */ -int pmic_init(unsigned char bus); -int power_init_board(void); -int pmic_dialog_init(unsigned char bus); -int check_reg(struct pmic *p, u32 reg); -struct pmic *pmic_alloc(void); -struct pmic *pmic_get(const char *s); -int pmic_probe(struct pmic *p); -int pmic_reg_read(struct pmic *p, u32 reg, u32 *val); -int pmic_reg_write(struct pmic *p, u32 reg, u32 val); -int pmic_set_output(struct pmic *p, u32 reg, int ldo, int on); -#endif /* CONFIG_IS_ENABLED(POWER_LEGACY) */ +#endif #define pmic_i2c_addr (p->hw.i2c.addr) #define pmic_i2c_tx_num (p->hw.i2c.tx_num) diff --git a/include/power/pmic_legacy.h b/include/power/pmic_legacy.h new file mode 100644 index 00000000000..7c244060b4a --- /dev/null +++ b/include/power/pmic_legacy.h @@ -0,0 +1,94 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2014-2015 Samsung Electronics + * Przemyslaw Marczak + * + * Copyright (C) 2011-2012 Samsung Electronics + * Lukasz Majewski + */ + +#ifndef __POWER_PMIC_LEGACY_H__ +#define __POWER_PMIC_LEGACY_H__ + +#ifndef __CORE_PMIC_H_ +#error "Do not include directly" +#endif + +enum { I2C_PMIC, I2C_NUM, }; +enum { PMIC_READ, PMIC_WRITE, }; +enum { PMIC_SENSOR_BYTE_ORDER_LITTLE, PMIC_SENSOR_BYTE_ORDER_BIG, }; + +enum { + PMIC_CHARGER_DISABLE, + PMIC_CHARGER_ENABLE, +}; + +struct p_i2c { + unsigned char addr; + unsigned char *buf; + unsigned char tx_num; +}; + +struct p_spi { + unsigned int cs; + unsigned int mode; + unsigned int bitlen; + unsigned int clk; + unsigned int flags; + u32 (*prepare_tx)(u32 reg, u32 *val, u32 write); +}; + +struct pmic; +struct power_fg { + int (*fg_battery_check) (struct pmic *p, struct pmic *bat); + int (*fg_battery_update) (struct pmic *p, struct pmic *bat); +}; + +struct power_chrg { + int (*chrg_type) (struct pmic *p); + int (*chrg_bat_present) (struct pmic *p); + int (*chrg_state) (struct pmic *p, int state, int current); +}; + +struct power_battery { + struct battery *bat; + int (*battery_init) (struct pmic *bat, struct pmic *p1, + struct pmic *p2, struct pmic *p3); + int (*battery_charge) (struct pmic *bat); + /* Keep info about power devices involved with battery operation */ + struct pmic *chrg, *fg, *muic; +}; + +struct pmic { + const char *name; + unsigned char bus; + unsigned char interface; + unsigned char sensor_byte_order; + unsigned int number_of_regs; + union hw { + struct p_i2c i2c; + struct p_spi spi; + } hw; + + void (*low_power_mode) (void); + struct power_battery *pbat; + struct power_chrg *chrg; + struct power_fg *fg; + + struct pmic *parent; + struct list_head list; +}; + +/* Legacy API, do not use */ +int pmic_init(unsigned char bus); +int power_init_board(void); +int pmic_dialog_init(unsigned char bus); +int check_reg(struct pmic *p, u32 reg); +struct pmic *pmic_alloc(void); +struct pmic *pmic_get(const char *s); +int pmic_probe(struct pmic *p); +int pmic_reg_read(struct pmic *p, u32 reg, u32 *val); +int pmic_reg_write(struct pmic *p, u32 reg, u32 val); +int pmic_set_output(struct pmic *p, u32 reg, int ldo, int on); + +#endif -- cgit v1.2.3 From 384079802a3eec3fff9578903285acc93ceda76f Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Mon, 4 Aug 2025 15:51:13 -0600 Subject: power: Tighten some power driver dependencies The MediaTek mt6323 power driver cannot build without access to some platform specific header files. Express that requirements in Kconfig as well. Signed-off-by: Tom Rini --- drivers/power/Kconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/power/Kconfig b/drivers/power/Kconfig index fd1c871f0db..d17337c0c3f 100644 --- a/drivers/power/Kconfig +++ b/drivers/power/Kconfig @@ -463,6 +463,7 @@ config TWL4030_POWER config POWER_MT6323 bool "Poweroff driver for mediatek mt6323" + depends on ARCH_MEDIATEK select CMD_POWEROFF help This adds poweroff driver for mt6323 -- cgit v1.2.3 From c9ffeefeb3efedd754e3ffa3440bfeb15cea00c3 Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Mon, 18 Aug 2025 10:54:06 -0600 Subject: test: Update logic for video test The video test here is specific to the sandbox SDL video driver, so only build it when that is enabled rather than VIDEO is enabled. Reported-by: Alison Chaiken Signed-off-by: Tom Rini --- test/dm/Makefile | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/test/dm/Makefile b/test/dm/Makefile index 474e77a2151..2db0e3b8dfd 100644 --- a/test/dm/Makefile +++ b/test/dm/Makefile @@ -126,7 +126,7 @@ obj-$(CONFIG_TEE) += tee.o obj-$(CONFIG_TIMER) += timer.o obj-$(CONFIG_TPM_V2) += tpm.o obj-$(CONFIG_DM_USB) += usb.o -obj-$(CONFIG_VIDEO) += video.o +obj-$(CONFIG_VIDEO_SANDBOX_SDL) += video.o ifeq ($(CONFIG_VIRTIO_SANDBOX),y) obj-y += virtio.o obj-$(CONFIG_VIRTIO_RNG) += virtio_device.o -- cgit v1.2.3 From 58b8ff0b663a7491c1964e1e3a8d1d88ef707077 Mon Sep 17 00:00:00 2001 From: Andrew Goodbody Date: Thu, 7 Aug 2025 17:35:22 +0100 Subject: power: regulator: tps65910: Cannot test unsigned for being negative The code in tps65910_regulator.c treats the field supply in struct tps65910_regulator_pdata as an int and even tests the value for being negative so change it from a u32 to int so that the code all works as expected. This issue was found by Smatch. Signed-off-by: Andrew Goodbody Signed-off-by: Peng Fan --- include/power/tps65910_pmic.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/include/power/tps65910_pmic.h b/include/power/tps65910_pmic.h index 2026ec2f426..8fa02f33ab1 100644 --- a/include/power/tps65910_pmic.h +++ b/include/power/tps65910_pmic.h @@ -123,7 +123,7 @@ enum { /* platform data */ struct tps65910_regulator_pdata { - u32 supply; /* regulator supply voltage in uV */ + int supply; /* regulator supply voltage in uV */ uint unit; /* unit-address according to DT */ }; -- cgit v1.2.3 From b7360bd9e8e05dcfd1b4e5fd1c996aabf919e180 Mon Sep 17 00:00:00 2001 From: Frieder Schrempf Date: Mon, 11 Aug 2025 15:11:57 +0200 Subject: Revert "pmic: pca9450: Add optional SD_VSEL GPIO for LDO5" This reverts commit 2add0511757e2c5897a88b57c5ea8c912140e60f. It turns out that all boards using the PCA9450 actually have the SD_VSEL input connected to the VSELECT signal of the SoCs SD/MMC interface. Therefore we don't need manual control for this signal via GPIO and there aren't any users. This is equivalent to the following change in Linux: c73be62caabb ("Revert "regulator: pca9450: Add SD_VSEL GPIO for LDO5"") Signed-off-by: Frieder Schrempf Signed-off-by: Peng Fan --- drivers/power/pmic/pca9450.c | 22 ---------------------- 1 file changed, 22 deletions(-) diff --git a/drivers/power/pmic/pca9450.c b/drivers/power/pmic/pca9450.c index 9d875f8bdbe..0e3d14abf15 100644 --- a/drivers/power/pmic/pca9450.c +++ b/drivers/power/pmic/pca9450.c @@ -6,12 +6,9 @@ #include #include #include -#include #include -#include #include #include -#include #include #include #include @@ -29,10 +26,6 @@ static const struct pmic_child_info pmic_children_info[] = { { }, }; -struct pca9450_priv { - struct gpio_desc *sd_vsel_gpio; -}; - static int pca9450_reg_count(struct udevice *dev) { return PCA9450_REG_NUM; @@ -85,21 +78,7 @@ static int pca9450_bind(struct udevice *dev) static int pca9450_probe(struct udevice *dev) { - struct pca9450_priv *priv = dev_get_priv(dev); unsigned int reset_ctrl; - int ret = 0; - - if (CONFIG_IS_ENABLED(DM_GPIO) && CONFIG_IS_ENABLED(DM_REGULATOR_PCA9450)) { - priv->sd_vsel_gpio = devm_gpiod_get_optional(dev, "sd-vsel", - GPIOD_IS_OUT | - GPIOD_IS_OUT_ACTIVE); - if (IS_ERR(priv->sd_vsel_gpio)) { - ret = PTR_ERR(priv->sd_vsel_gpio); - dev_err(dev, "Failed to request SD_VSEL GPIO: %d\n", ret); - if (ret) - return ret; - } - } if (ofnode_read_bool(dev_ofnode(dev), "nxp,wdog_b-warm-reset")) reset_ctrl = PCA9450_PMIC_RESET_WDOG_B_CFG_WARM; @@ -132,5 +111,4 @@ U_BOOT_DRIVER(pmic_pca9450) = { .bind = pca9450_bind, .probe = pca9450_probe, .ops = &pca9450_ops, - .priv_auto = sizeof(struct pca9450_priv), }; -- cgit v1.2.3 From 8a04fbd9afd635d37c9afc1b56d014d134861e29 Mon Sep 17 00:00:00 2001 From: Frieder Schrempf Date: Mon, 11 Aug 2025 15:11:58 +0200 Subject: pmic: pca9450: Fix enable register for LDO5 The LDO5 regulator has two configuration registers, but only LDO5CTRL_L contains the bits for enabling/disabling the regulator. This is equivalent to the following change in Linux: f5aab0438ef1 ("regulator: pca9450: Fix enable register for LDO5") Fixes: 326337fb005f ("pmic: pca9450: Add regulator driver") Signed-off-by: Frieder Schrempf Signed-off-by: Peng Fan --- drivers/power/regulator/pca9450.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/power/regulator/pca9450.c b/drivers/power/regulator/pca9450.c index a2a34244723..27db55e688d 100644 --- a/drivers/power/regulator/pca9450.c +++ b/drivers/power/regulator/pca9450.c @@ -144,7 +144,7 @@ static struct pca9450_plat pca9450_reg_data[] = { PCA_DATA("LDO4", PCA9450_LDO4CTRL, HW_STATE_CONTROL, PCA9450_LDO4CTRL, PCA9450_LDO34_MASK, pca9450_ldo34_vranges), - PCA_DATA("LDO5", PCA9450_LDO5CTRL_H, HW_STATE_CONTROL, + PCA_DATA("LDO5", PCA9450_LDO5CTRL_L, HW_STATE_CONTROL, PCA9450_LDO5CTRL_H, PCA9450_LDO5_MASK, pca9450_ldo5_vranges), }; -- cgit v1.2.3 From addfe4544630a96a1cd03daf822a196af42b7a73 Mon Sep 17 00:00:00 2001 From: Frieder Schrempf Date: Mon, 11 Aug 2025 15:11:59 +0200 Subject: pmic: pca9450: Fix control register for LDO5 For LDO5 we need to be able to check the status of the SD_VSEL input in order to know which control register is used. Read the status of the SD_VSEL signal via GPIO and use the correct register accordingly. To use this, the LDO5 node in the devicetree needs the sd-vsel-gpios property to reference the GPIO that is used to read back the SD_VSEL status internally. Please note that the SION bit in the IOMUX must be set if the signal is muxed as VSELECT and controlled by the USDHC controller. This is equivalent to the following change in Linux: 3ce6f4f943dd ("regulator: pca9450: Fix control register for LDO5") Signed-off-by: Frieder Schrempf Signed-off-by: Peng Fan --- drivers/power/regulator/pca9450.c | 31 +++++++++++++++++++++++++++++-- 1 file changed, 29 insertions(+), 2 deletions(-) diff --git a/drivers/power/regulator/pca9450.c b/drivers/power/regulator/pca9450.c index 27db55e688d..9d8d142b464 100644 --- a/drivers/power/regulator/pca9450.c +++ b/drivers/power/regulator/pca9450.c @@ -7,9 +7,12 @@ * ROHM BD71837 regulator driver */ +#include #include +#include #include #include +#include #include #include #include @@ -52,6 +55,7 @@ struct pca9450_plat { u8 volt_mask; struct pca9450_vrange *ranges; unsigned int numranges; + struct gpio_desc *sd_vsel_gpio; }; #define PCA_RANGE(_min, _vstep, _sel_low, _sel_hi) \ @@ -222,13 +226,23 @@ static int pca9450_set_enable(struct udevice *dev, bool enable) val); } +static u8 pca9450_get_vsel_reg(struct pca9450_plat *plat) +{ + if (!strcmp(plat->name, "LDO5") && + (plat->sd_vsel_gpio && !dm_gpio_get_value(plat->sd_vsel_gpio)) { + return PCA9450_LDO5CTRL_L; + } + + return plat->volt_reg; +} + static int pca9450_get_value(struct udevice *dev) { struct pca9450_plat *plat = dev_get_plat(dev); unsigned int reg, tmp; int i, ret; - ret = pmic_reg_read(dev->parent, plat->volt_reg); + ret = pmic_reg_read(dev->parent, pca9450_get_vsel_reg(plat)); if (ret < 0) return ret; @@ -274,7 +288,7 @@ static int pca9450_set_value(struct udevice *dev, int uvolt) if (!found) return -EINVAL; - return pmic_clrsetbits(dev->parent, plat->volt_reg, + return pmic_clrsetbits(dev->parent, pca9450_get_vsel_reg(plat), plat->volt_mask, sel); } @@ -335,6 +349,19 @@ static int pca9450_regulator_probe(struct udevice *dev) *plat = pca9450_reg_data[i]; + if (!strcmp(plat->name, "LDO5")) { + if (CONFIG_IS_ENABLED(DM_GPIO) && CONFIG_IS_ENABLED(DM_REGULATOR_PCA9450)) { + plat->sd_vsel_gpio = devm_gpiod_get_optional(dev, "sd-vsel", + GPIOD_IS_IN); + if (IS_ERR(plat->sd_vsel_gpio)) { + ret = PTR_ERR(plat->sd_vsel_gpio); + dev_err(dev, "Failed to request SD_VSEL GPIO: %d\n", ret); + if (ret) + return ret; + } + } + } + return 0; } -- cgit v1.2.3 From 281829f5ca1645c3bffa130d04753a1a76b64dfb Mon Sep 17 00:00:00 2001 From: Frieder Schrempf Date: Mon, 11 Aug 2025 15:12:00 +0200 Subject: pmic: pca9450: Handle hardware with fixed SD_VSEL for LDO5 There are two ways to set the output voltage of the LD05 regulator. First by writing to the voltage selection registers and second by toggling the SD_VSEL signal. Usually board designers connect SD_VSEL to the VSELECT signal controlled by the USDHC controller, but in some cases the signal is hardwired to a fixed low level (therefore selecting 3.3V as initial value for allowing to boot from the SD card). In these cases, the voltage is only determined by the value of the LDO5CTRL_L register. Introduce a property nxp,sd-vsel-fixed-low to let the driver know that SD_VSEL is low and there is no GPIO to actually get that information from dynamically. This is equivalent to the following change in Linux: c8c1ab2c5cb7 ("regulator: pca9450: Handle hardware with fixed SD_VSEL for LDO5") Signed-off-by: Frieder Schrempf Signed-off-by: Peng Fan --- drivers/power/regulator/pca9450.c | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/drivers/power/regulator/pca9450.c b/drivers/power/regulator/pca9450.c index 9d8d142b464..3bb0c71dde7 100644 --- a/drivers/power/regulator/pca9450.c +++ b/drivers/power/regulator/pca9450.c @@ -56,6 +56,7 @@ struct pca9450_plat { struct pca9450_vrange *ranges; unsigned int numranges; struct gpio_desc *sd_vsel_gpio; + bool sd_vsel_fixed_low; }; #define PCA_RANGE(_min, _vstep, _sel_low, _sel_hi) \ @@ -229,7 +230,8 @@ static int pca9450_set_enable(struct udevice *dev, bool enable) static u8 pca9450_get_vsel_reg(struct pca9450_plat *plat) { if (!strcmp(plat->name, "LDO5") && - (plat->sd_vsel_gpio && !dm_gpio_get_value(plat->sd_vsel_gpio)) { + ((plat->sd_vsel_gpio && !dm_gpio_get_value(plat->sd_vsel_gpio)) || + plat->sd_vsel_fixed_low)) { return PCA9450_LDO5CTRL_L; } @@ -360,6 +362,8 @@ static int pca9450_regulator_probe(struct udevice *dev) return ret; } } + + plat->sd_vsel_fixed_low = dev_read_bool(dev, "nxp,sd-vsel-fixed-low"); } return 0; -- cgit v1.2.3 From 925f63b0209483cd04b014cc8b5deab1f20267b7 Mon Sep 17 00:00:00 2001 From: Frieder Schrempf Date: Mon, 11 Aug 2025 15:12:01 +0200 Subject: arm: dts: imx8mp-data-modul-edm-sbc: Remove deprecated sd-vsel-gpios The sd-vsel-gpios property in the root of the PMIC node is deprecated and therefore not parsed by the driver anymore. We can safely remove this as it wasn't used anyway due to the pad not having the correct pinmux settings. Signed-off-by: Frieder Schrempf Reviewed-by: Marek Vasut Signed-off-by: Peng Fan --- arch/arm/dts/imx8mp-data-modul-edm-sbc.dts | 1 - 1 file changed, 1 deletion(-) diff --git a/arch/arm/dts/imx8mp-data-modul-edm-sbc.dts b/arch/arm/dts/imx8mp-data-modul-edm-sbc.dts index 8066f7fb649..6b40106e3bd 100644 --- a/arch/arm/dts/imx8mp-data-modul-edm-sbc.dts +++ b/arch/arm/dts/imx8mp-data-modul-edm-sbc.dts @@ -344,7 +344,6 @@ pinctrl-0 = <&pinctrl_pmic>; interrupt-parent = <&gpio1>; interrupts = <3 IRQ_TYPE_LEVEL_LOW>; - sd-vsel-gpios = <&gpio1 4 GPIO_ACTIVE_HIGH>; /* * i.MX 8M Plus Data Sheet for Consumer Products -- cgit v1.2.3 From dc0a12fecea789de83015319f3e9aeddd0a824a2 Mon Sep 17 00:00:00 2001 From: Frieder Schrempf Date: Mon, 11 Aug 2025 15:12:02 +0200 Subject: arm: dts: imx8mp-dhcom-som: Remove deprecated sd-vsel-gpios The sd-vsel-gpios property in the root of the PMIC node is deprecated and therefore not parsed by the driver anymore. We can safely remove this as it wasn't used anyway due to the pad not having the correct pinmux settings. Signed-off-by: Frieder Schrempf Reviewed-by: Marek Vasut Signed-off-by: Peng Fan --- arch/arm/dts/imx8mp-dhcom-som.dtsi | 1 - 1 file changed, 1 deletion(-) diff --git a/arch/arm/dts/imx8mp-dhcom-som.dtsi b/arch/arm/dts/imx8mp-dhcom-som.dtsi index f2d99d05854..c1ca3805737 100644 --- a/arch/arm/dts/imx8mp-dhcom-som.dtsi +++ b/arch/arm/dts/imx8mp-dhcom-som.dtsi @@ -245,7 +245,6 @@ pinctrl-0 = <&pinctrl_pmic>; interrupt-parent = <&gpio1>; interrupts = <3 IRQ_TYPE_LEVEL_LOW>; - sd-vsel-gpios = <&gpio1 4 GPIO_ACTIVE_HIGH>; /* * i.MX 8M Plus Data Sheet for Consumer Products -- cgit v1.2.3 From 38443338c7d491852d21d6c5e7e742fc347b9a44 Mon Sep 17 00:00:00 2001 From: Henrik Grimler Date: Fri, 22 Aug 2025 20:33:23 +0200 Subject: power: pmic: s2mps11: look for both {voltage-,}regulators Linux's DTSes uses regulators { }; while u-boot's DTSes uses voltage-regulators { };. Look for regulators, and fallback to voltage-regulators if not found, so that both type of DTSes can be used with the driver. Signed-off-by: Henrik Grimler Reviewed-by: Anand Moon Signed-off-by: Peng Fan --- drivers/power/pmic/s2mps11.c | 11 +++++++---- 1 file changed, 7 insertions(+), 4 deletions(-) diff --git a/drivers/power/pmic/s2mps11.c b/drivers/power/pmic/s2mps11.c index 17780017035..3aa8cad0827 100644 --- a/drivers/power/pmic/s2mps11.c +++ b/drivers/power/pmic/s2mps11.c @@ -52,11 +52,14 @@ static int s2mps11_probe(struct udevice *dev) ofnode regulators_node; int children; - regulators_node = dev_read_subnode(dev, "voltage-regulators"); + regulators_node = dev_read_subnode(dev, "regulators"); if (!ofnode_valid(regulators_node)) { - debug("%s: %s regulators subnode not found!\n", __func__, - dev->name); - return -ENXIO; + regulators_node = dev_read_subnode(dev, "voltage-regulators"); + if (!ofnode_valid(regulators_node)) { + debug("%s: %s regulators subnode not found!\n", __func__, + dev->name); + return -ENXIO; + } } debug("%s: '%s' - found regulators subnode\n", __func__, dev->name); -- cgit v1.2.3 From 8575c09a42efc438eacb55483135deb322f98fdc Mon Sep 17 00:00:00 2001 From: Henrik Grimler Date: Fri, 22 Aug 2025 20:33:24 +0200 Subject: ARM: dts: exynos5422-odroidxu3: rename s2mps11 regulators node With this both linux and u-boot uses the same node name, which simplifies devicetree parsing in s2mps11 driver. Signed-off-by: Henrik Grimler Reviewed-by: Anand Moon Signed-off-by: Peng Fan --- arch/arm/dts/exynos5422-odroidxu3.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/dts/exynos5422-odroidxu3.dts b/arch/arm/dts/exynos5422-odroidxu3.dts index ef25cf77447..e147fcb8643 100644 --- a/arch/arm/dts/exynos5422-odroidxu3.dts +++ b/arch/arm/dts/exynos5422-odroidxu3.dts @@ -40,7 +40,7 @@ s2mps11_pmic@66 { compatible = "samsung,s2mps11-pmic"; reg = <0x66>; - voltage-regulators { + regulators { ldo1_reg: LDO1 { regulator-name = "vdd_ldo1"; regulator-min-microvolt = <1000000>; -- cgit v1.2.3 From 983a16f38627c49704811c12ca7c6d134b08289c Mon Sep 17 00:00:00 2001 From: Henrik Grimler Date: Fri, 22 Aug 2025 20:33:25 +0200 Subject: power: pmic: s2mps11: remove check for voltage-regulators node All devicetrees that use s2mps11 driver have been converted to use regulators { };, so we can safely drop the voltage-regulators fallback check. Signed-off-by: Henrik Grimler Reviewed-by: Anand Moon Signed-off-by: Peng Fan --- drivers/power/pmic/s2mps11.c | 9 +++------ 1 file changed, 3 insertions(+), 6 deletions(-) diff --git a/drivers/power/pmic/s2mps11.c b/drivers/power/pmic/s2mps11.c index 3aa8cad0827..6e819579030 100644 --- a/drivers/power/pmic/s2mps11.c +++ b/drivers/power/pmic/s2mps11.c @@ -54,12 +54,9 @@ static int s2mps11_probe(struct udevice *dev) regulators_node = dev_read_subnode(dev, "regulators"); if (!ofnode_valid(regulators_node)) { - regulators_node = dev_read_subnode(dev, "voltage-regulators"); - if (!ofnode_valid(regulators_node)) { - debug("%s: %s regulators subnode not found!\n", __func__, - dev->name); - return -ENXIO; - } + debug("%s: %s regulators subnode not found!\n", __func__, + dev->name); + return -ENXIO; } debug("%s: '%s' - found regulators subnode\n", __func__, dev->name); -- cgit v1.2.3 From 89cad7ed6fdfdb3bcbb5c6d42b3d178c55d6c8d9 Mon Sep 17 00:00:00 2001 From: Henrik Grimler Date: Fri, 22 Aug 2025 20:33:26 +0200 Subject: ARM: dts: exynos4210-universal_c210: rename max8998 regulators node Linux uses just regulators { }; instead of voltage-regulators { };, so this change aligns the DTSes found in the two projects. The max8998 driver does not yet parse the regulators node, so we can safely change its name without breaking anything. Signed-off-by: Henrik Grimler Signed-off-by: Peng Fan --- arch/arm/dts/exynos4210-universal_c210.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/dts/exynos4210-universal_c210.dts b/arch/arm/dts/exynos4210-universal_c210.dts index c87b92be609..cfa99b62828 100644 --- a/arch/arm/dts/exynos4210-universal_c210.dts +++ b/arch/arm/dts/exynos4210-universal_c210.dts @@ -77,7 +77,7 @@ max8998-pmic@66 { compatible = "maxim,max8998"; reg = <0x66 0 0>; - voltage-regulators { + regulators { ldo2_reg: LDO2 { regulator-name = "VALIVE_1.2V"; regulator-min-microvolt = <1200000>; -- cgit v1.2.3 From e64d1a03171d3a3cf62210f930497a25bc4f4f55 Mon Sep 17 00:00:00 2001 From: Henrik Grimler Date: Fri, 22 Aug 2025 20:33:27 +0200 Subject: ARM: dts: s5c1xx-goni: rename max8998-pmic regulators node Linux uses just regulators { }; instead of voltage-regulators { };, so this change aligns the DTSes found in the two projects. The max8998 driver does not yet parse the regulators node, so we can safely change its name without breaking anything. Signed-off-by: Henrik Grimler Signed-off-by: Peng Fan --- arch/arm/dts/s5pc1xx-goni.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/dts/s5pc1xx-goni.dts b/arch/arm/dts/s5pc1xx-goni.dts index 90e3405040a..6c15a87ffb0 100644 --- a/arch/arm/dts/s5pc1xx-goni.dts +++ b/arch/arm/dts/s5pc1xx-goni.dts @@ -45,7 +45,7 @@ compatible = "maxim,max8998"; reg = <0x66 0 0>; - voltage-regulators { + regulators { ldo2_reg: LDO2 { regulator-compatible = "LDO2"; regulator-name = "VALIVE_1.1V"; -- cgit v1.2.3 From 0fdd3b4243359fd81d11923b711c28230795cc54 Mon Sep 17 00:00:00 2001 From: Henrik Grimler Date: Fri, 22 Aug 2025 20:33:28 +0200 Subject: power: pmic: fix typo and capitalisation in max8997 Kconfig help msg To make the help message slightly easier to understand. Signed-off-by: Henrik Grimler Signed-off-by: Peng Fan --- drivers/power/pmic/Kconfig | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/power/pmic/Kconfig b/drivers/power/pmic/Kconfig index ec7ccc3a63f..b1a5b1c2a1f 100644 --- a/drivers/power/pmic/Kconfig +++ b/drivers/power/pmic/Kconfig @@ -228,9 +228,9 @@ config PMIC_MAX8997 This is a Power Management IC with RTC, Fuel Gauge, MUIC control on Chip. - 21x LDOs - 12x GPIOs - - Haptic Motor driver + - Haptic motor driver - RTC with two alarms - - Fueal Gauge and One backup battery charger + - Fuel Gauge and one backup battery charger - MUIC - Others -- cgit v1.2.3 From 920404409cf1bb7644199b4194bf137fc62cff82 Mon Sep 17 00:00:00 2001 From: Henrik Grimler Date: Fri, 22 Aug 2025 20:33:29 +0200 Subject: power: pmic: max8997: support maxim,max8997-pmic compatible as well Linux's DTSes uses maxim,max8997-pmic, so check for this compatible as well so that max8997 pmic driver can support both u-boot and Linux's DTSes. Signed-off-by: Henrik Grimler Signed-off-by: Peng Fan --- drivers/power/pmic/max8997.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/power/pmic/max8997.c b/drivers/power/pmic/max8997.c index 4afa6c84ef8..ecdad505b26 100644 --- a/drivers/power/pmic/max8997.c +++ b/drivers/power/pmic/max8997.c @@ -47,6 +47,7 @@ static struct dm_pmic_ops max8997_ops = { static const struct udevice_id max8997_ids[] = { { .compatible = "maxim,max8997" }, + { .compatible = "maxim,max8997-pmic" }, { }, }; -- cgit v1.2.3 From 1ca245d1c51173f73a98861244a33add45cb50d5 Mon Sep 17 00:00:00 2001 From: Henrik Grimler Date: Fri, 22 Aug 2025 20:33:30 +0200 Subject: ARM: dts: exynos4210-trats: use maxim,max8997-pmic compatible Instead of maxim,max8997. Linux uses maxim,max8997-pmic, so with this change we align the trats DTS with its linux counterpart. Signed-off-by: Henrik Grimler Signed-off-by: Peng Fan --- arch/arm/dts/exynos4210-trats.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/dts/exynos4210-trats.dts b/arch/arm/dts/exynos4210-trats.dts index 88e9c0ed2bb..2947d79f0cd 100644 --- a/arch/arm/dts/exynos4210-trats.dts +++ b/arch/arm/dts/exynos4210-trats.dts @@ -102,7 +102,7 @@ status = "okay"; max8997-pmic@66 { - compatible = "maxim,max8997"; + compatible = "maxim,max8997-pmic"; reg = <0x66 0 0>; voltage-regulators { valive_reg: LDO2 { -- cgit v1.2.3 From 31c376cf4f383e57ce2053c3e4b8c7138fdb1e6e Mon Sep 17 00:00:00 2001 From: Henrik Grimler Date: Fri, 22 Aug 2025 20:33:31 +0200 Subject: power: pmic: max8997: drop maxim,max8997 compatible All u-boot users now use maxim,max8997-pmic instead, as does Linux's DTSes, so we can now safely drop the maxim,max8997 compatible. Signed-off-by: Henrik Grimler Reviewed-by: Anand Moon Signed-off-by: Peng Fan --- drivers/power/pmic/max8997.c | 1 - 1 file changed, 1 deletion(-) diff --git a/drivers/power/pmic/max8997.c b/drivers/power/pmic/max8997.c index ecdad505b26..fb65a3ca730 100644 --- a/drivers/power/pmic/max8997.c +++ b/drivers/power/pmic/max8997.c @@ -46,7 +46,6 @@ static struct dm_pmic_ops max8997_ops = { }; static const struct udevice_id max8997_ids[] = { - { .compatible = "maxim,max8997" }, { .compatible = "maxim,max8997-pmic" }, { }, }; -- cgit v1.2.3 From cec29c00bc4c3cfd4312b9444da0cc77f161442e Mon Sep 17 00:00:00 2001 From: Henrik Grimler Date: Fri, 22 Aug 2025 20:33:32 +0200 Subject: ARM: dts: trats: rename max8997-pmic regulators node Linux uses just regulators { }; instead of voltage-regulators { };, so this change aligns the DTSes found in the two projects. The max8997 driver does not yet parse the regulators node, so we can safely change its name without breaking anything. Signed-off-by: Henrik Grimler Signed-off-by: Peng Fan --- arch/arm/dts/exynos4210-trats.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/dts/exynos4210-trats.dts b/arch/arm/dts/exynos4210-trats.dts index 2947d79f0cd..38b168950df 100644 --- a/arch/arm/dts/exynos4210-trats.dts +++ b/arch/arm/dts/exynos4210-trats.dts @@ -104,7 +104,7 @@ max8997-pmic@66 { compatible = "maxim,max8997-pmic"; reg = <0x66 0 0>; - voltage-regulators { + regulators { valive_reg: LDO2 { regulator-name = "VALIVE_1.1V_C210"; regulator-min-microvolt = <1100000>; -- cgit v1.2.3 From a65798ddbb88b06539e2a109d686edd3fb3a8173 Mon Sep 17 00:00:00 2001 From: Henrik Grimler Date: Fri, 22 Aug 2025 20:33:33 +0200 Subject: board: samsung: odroid: drop exynos_power_init exynos_power_init sets up regulators for the emmc and sdcard, but these regulators are already marked as always-on and boot-on and hence are handled already by the regulator-uclass. Since we currently try to set them up twice we get error -114 (EALREADY) from exynos_power_init on every boot: LDO20@VDDQ_EMMC_1.8V: set 1800000 uV; enabling (ret: -114) LDO22@VDDQ_EMMC_2.8V: set 2800000 uV; enabling (ret: -114) LDO21@TFLASH_2.8V: set 2800000 uV; enabling (ret: -114) Remove the superfluous exynos_power_init to silence these errors. Signed-off-by: Henrik Grimler Reviewed-by: Anand Moon Signed-off-by: Peng Fan --- board/samsung/odroid/odroid.c | 15 --------------- 1 file changed, 15 deletions(-) diff --git a/board/samsung/odroid/odroid.c b/board/samsung/odroid/odroid.c index 84d6d919f07..a48b8e94b77 100644 --- a/board/samsung/odroid/odroid.c +++ b/board/samsung/odroid/odroid.c @@ -428,21 +428,6 @@ void exynos_init(void) board_gpio_init(); } -int exynos_power_init(void) -{ - const char *mmc_regulators[] = { - "VDDQ_EMMC_1.8V", - "VDDQ_EMMC_2.8V", - "TFLASH_2.8V", - NULL, - }; - - if (regulator_list_autoset(mmc_regulators, NULL, true)) - pr_err("Unable to init all mmc regulators\n"); - - return 0; -} - #ifdef CONFIG_USB_GADGET static int s5pc210_phy_control(int on) { -- cgit v1.2.3 From 9065b87f35018a4e993e7dfb8a8ec29474785f76 Mon Sep 17 00:00:00 2001 From: Primoz Fiser Date: Thu, 28 Aug 2025 13:24:04 +0200 Subject: power: pmic: pca9450: Add support for system reset The family of PCA9450 PMICs have the ability to perform system resets. Restarting via PMIC is preferred method of restarting the system as all the peripherals are brought to a know state after a power-cycle. The PCA9450 features a cold restart procedure which is initiated by an I2C command 0x14 to the SW_RST register. Support in Linux for restarting via PCA9450 PMIC has been added by Linux commit 6157e62b07d9 ("regulator: pca9450: Add restart handler"). Now add support for it also in the U-Boot via sysreset framework. Signed-off-by: Primoz Fiser Reviewed-by: Paul Geurts Signed-off-by: Peng Fan --- drivers/power/pmic/pca9450.c | 44 ++++++++++++++++++++++++++++++++++++++++++++ include/power/pca9450.h | 2 ++ 2 files changed, 46 insertions(+) diff --git a/drivers/power/pmic/pca9450.c b/drivers/power/pmic/pca9450.c index 0e3d14abf15..8b98c2239e1 100644 --- a/drivers/power/pmic/pca9450.c +++ b/drivers/power/pmic/pca9450.c @@ -6,13 +6,17 @@ #include #include #include +#include +#include #include #include #include +#include #include #include #include #include +#include DECLARE_GLOBAL_DATA_PTR; @@ -79,6 +83,15 @@ static int pca9450_bind(struct udevice *dev) static int pca9450_probe(struct udevice *dev) { unsigned int reset_ctrl; + int ret; + + if (CONFIG_IS_ENABLED(SYSRESET)) { + ret = device_bind_driver_to_node(dev, "pca9450_sysreset", + "pca9450_sysreset", + dev_ofnode(dev), NULL); + if (ret) + return ret; + } if (ofnode_read_bool(dev_ofnode(dev), "nxp,wdog_b-warm-reset")) reset_ctrl = PCA9450_PMIC_RESET_WDOG_B_CFG_WARM; @@ -112,3 +125,34 @@ U_BOOT_DRIVER(pmic_pca9450) = { .probe = pca9450_probe, .ops = &pca9450_ops, }; + +#ifdef CONFIG_SYSRESET +static int pca9450_sysreset_request(struct udevice *dev, enum sysreset_t type) +{ + u8 cmd = PCA9450_SW_RST_COLD_RST; + + if (type != SYSRESET_COLD) + return -EPROTONOSUPPORT; + + if (pmic_write(dev->parent, PCA9450_SW_RST, &cmd, 1)) { + dev_err(dev, "reset command failed\n"); + } else { + /* tRESTART is 250ms, delay 300ms just to be sure */ + mdelay(300); + /* Should not get here, warn if we do */ + dev_warn(dev, "didn't respond to reset command\n"); + } + + return -EINPROGRESS; +} + +static struct sysreset_ops pca9450_sysreset_ops = { + .request = pca9450_sysreset_request, +}; + +U_BOOT_DRIVER(pca9450_sysreset) = { + .name = "pca9450_sysreset", + .id = UCLASS_SYSRESET, + .ops = &pca9450_sysreset_ops, +}; +#endif /* CONFIG_SYSRESET */ diff --git a/include/power/pca9450.h b/include/power/pca9450.h index e5ab09fb8c8..9119ef793b1 100644 --- a/include/power/pca9450.h +++ b/include/power/pca9450.h @@ -75,4 +75,6 @@ enum { #define PCA9450_PMIC_RESET_WDOG_B_CFG_WARM 0x40 #define PCA9450_PMIC_RESET_WDOG_B_CFG_COLD_LDO12 0x80 +#define PCA9450_SW_RST_COLD_RST 0x14 + #endif -- cgit v1.2.3 From ad197b31b3f88d53c349995d8bbaeba4b18b8f2b Mon Sep 17 00:00:00 2001 From: Primoz Fiser Date: Thu, 28 Aug 2025 13:24:05 +0200 Subject: power: pmic: pca9450: Add support for reset status PCA9450 PMIC supports reading the reset status from the PWRON_STAT register. Bits 7-4 give indication of the PMIC reset cause: - PWRON (BIT7) - Power ON triggered by PMIC_ON_REQ input line, - WDOGB (BIT6) - Boot after cold reset by WDOGB pin (watchdog reset), - SW_RST (BIT5) - Boot after cold reset initiated by the software, - PMIC_RST (BIT4) - Boot after PMIC_RST_B input line trigger. Add support for reading reset status via the sysreset framework in a convenient printable format. Signed-off-by: Primoz Fiser Reviewed-by: Paul Geurts Signed-off-by: Peng Fan --- drivers/power/pmic/pca9450.c | 38 ++++++++++++++++++++++++++++++++++++++ include/power/pca9450.h | 5 +++++ 2 files changed, 43 insertions(+) diff --git a/drivers/power/pmic/pca9450.c b/drivers/power/pmic/pca9450.c index 8b98c2239e1..e5c1f037b61 100644 --- a/drivers/power/pmic/pca9450.c +++ b/drivers/power/pmic/pca9450.c @@ -146,8 +146,46 @@ static int pca9450_sysreset_request(struct udevice *dev, enum sysreset_t type) return -EINPROGRESS; } +int pca9450_sysreset_get_status(struct udevice *dev, char *buf, int size) +{ + const char *reason; + int ret; + u8 reg; + + ret = pmic_read(dev->parent, PCA9450_PWRON_STAT, ®, 1); + if (ret) + return ret; + + switch (reg) { + case PCA9450_PWRON_STAT_PWRON_MASK: + reason = "PWRON"; + break; + case PCA9450_PWRON_STAT_WDOG_MASK: + reason = "WDOGB"; + break; + case PCA9450_PWRON_STAT_SW_RST_MASK: + reason = "SW_RST"; + break; + case PCA9450_PWRON_STAT_PMIC_RST_MASK: + reason = "PMIC_RST"; + break; + default: + reason = "UNKNOWN"; + break; + } + + ret = snprintf(buf, size, "Reset Status: %s\n", reason); + if (ret < 0) { + dev_err(dev, "Write reset status error (err = %d)\n", ret); + return -EIO; + } + + return 0; +} + static struct sysreset_ops pca9450_sysreset_ops = { .request = pca9450_sysreset_request, + .get_status = pca9450_sysreset_get_status, }; U_BOOT_DRIVER(pca9450_sysreset) = { diff --git a/include/power/pca9450.h b/include/power/pca9450.h index 9119ef793b1..41b7f95c034 100644 --- a/include/power/pca9450.h +++ b/include/power/pca9450.h @@ -75,6 +75,11 @@ enum { #define PCA9450_PMIC_RESET_WDOG_B_CFG_WARM 0x40 #define PCA9450_PMIC_RESET_WDOG_B_CFG_COLD_LDO12 0x80 +#define PCA9450_PWRON_STAT_PWRON_MASK 0x80 +#define PCA9450_PWRON_STAT_WDOG_MASK 0x40 +#define PCA9450_PWRON_STAT_SW_RST_MASK 0x20 +#define PCA9450_PWRON_STAT_PMIC_RST_MASK 0x10 + #define PCA9450_SW_RST_COLD_RST 0x14 #endif -- cgit v1.2.3 From 95994d4e5996610c8205597b2849b48eaaf2baff Mon Sep 17 00:00:00 2001 From: Andrew Goodbody Date: Wed, 30 Jul 2025 17:52:56 +0100 Subject: mmc: iproc_sdhci: Cannot test unsigned variable for negative In sdhci_iproc_execute_tuning the variable tuning_loop_counter is unsigned and therefore will always fail the test for it being less than 0. Fix this by changing the variable type to be s8. This issue was found by Smatch. Signed-off-by: Andrew Goodbody Reviewed-by: Peng Fan Signed-off-by: Peng Fan --- drivers/mmc/iproc_sdhci.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/mmc/iproc_sdhci.c b/drivers/mmc/iproc_sdhci.c index 7ab74ff117a..654672a546f 100644 --- a/drivers/mmc/iproc_sdhci.c +++ b/drivers/mmc/iproc_sdhci.c @@ -182,7 +182,7 @@ static int sdhci_iproc_execute_tuning(struct mmc *mmc, u8 opcode) u32 ctrl; u32 blocksize = SDHCI_MAKE_BLKSZ(SDHCI_DEFAULT_BOUNDARY_ARG, 64); struct sdhci_host *host = dev_get_priv(mmc->dev); - char tuning_loop_counter = MAX_TUNING_LOOP; + s8 tuning_loop_counter = MAX_TUNING_LOOP; int ret = 0; sdhci_start_tuning(host); -- cgit v1.2.3 From 140562d3a2b447079499d773a7d21ec1728692cb Mon Sep 17 00:00:00 2001 From: Bhimeswararao Matsa Date: Fri, 29 Aug 2025 07:41:31 +0530 Subject: mmc: core: drop space before newline in trace printf Remove unnecessary whitespace before '\n' in trace printf format strings (checkpatch warning QUOTED_WHITESPACE_BEFORE_NEWLINE). No functional change intended. Signed-off-by: Bhimeswararao Matsa Signed-off-by: Peng Fan --- drivers/mmc/mmc.c | 14 +++++++------- 1 file changed, 7 insertions(+), 7 deletions(-) diff --git a/drivers/mmc/mmc.c b/drivers/mmc/mmc.c index 5f2efbe6df9..20afcffde3d 100644 --- a/drivers/mmc/mmc.c +++ b/drivers/mmc/mmc.c @@ -125,21 +125,21 @@ void mmmc_trace_after_send(struct mmc *mmc, struct mmc_cmd *cmd, int ret) printf("\t\tMMC_RSP_NONE\n"); break; case MMC_RSP_R1: - printf("\t\tMMC_RSP_R1,5,6,7 \t 0x%08x \n", + printf("\t\tMMC_RSP_R1,5,6,7 \t 0x%08x\n", cmd->response[0]); break; case MMC_RSP_R1b: - printf("\t\tMMC_RSP_R1b\t\t 0x%08x \n", + printf("\t\tMMC_RSP_R1b\t\t 0x%08x\n", cmd->response[0]); break; case MMC_RSP_R2: - printf("\t\tMMC_RSP_R2\t\t 0x%08x \n", + printf("\t\tMMC_RSP_R2\t\t 0x%08x\n", cmd->response[0]); - printf("\t\t \t\t 0x%08x \n", + printf("\t\t \t\t 0x%08x\n", cmd->response[1]); - printf("\t\t \t\t 0x%08x \n", + printf("\t\t \t\t 0x%08x\n", cmd->response[2]); - printf("\t\t \t\t 0x%08x \n", + printf("\t\t \t\t 0x%08x\n", cmd->response[3]); printf("\n"); printf("\t\t\t\t\tDUMPING DATA\n"); @@ -154,7 +154,7 @@ void mmmc_trace_after_send(struct mmc *mmc, struct mmc_cmd *cmd, int ret) } break; case MMC_RSP_R3: - printf("\t\tMMC_RSP_R3,4\t\t 0x%08x \n", + printf("\t\tMMC_RSP_R3,4\t\t 0x%08x\n", cmd->response[0]); break; default: -- cgit v1.2.3 From 86c5c25b6ca99025ac8ebcbe5c53ea0f398d1f44 Mon Sep 17 00:00:00 2001 From: Rasmus Villemoes Date: Fri, 22 Aug 2025 20:18:46 +0200 Subject: memtest: don't volatile-qualify local variables It is obviously important that the addr pointer used to access the memory region being tested is volatile-qualified, to prevent the compiler from optimizing out the "write this value, read it back, check that it is what we expect". However, none of these auxiliary variables have any such need for, effectively, being forced to live on the stack and cause each and every reference to them to do a memory access. This makes the memtest about 15% faster on a beagleboneblack. Before: => dcache off => time mtest 0x81000000 0x81100000 0 1 Testing 81000000 ... 81100000: Iteration: 1 Tested 1 iteration(s) with 0 errors. time: 10.868 seconds After: => dcache off => time mtest 0x81000000 0x81100000 0 1 Testing 81000000 ... 81100000: Iteration: 1 Tested 1 iteration(s) with 0 errors. time: 9.209 seconds [Without the 'dcache off', there's no difference in the time, about 0.6s, but the memtest cannot usefully be done with dcache enabled.] Signed-off-by: Rasmus Villemoes Tested-by: Anshul Dalal --- cmd/mem.c | 9 +++------ 1 file changed, 3 insertions(+), 6 deletions(-) diff --git a/cmd/mem.c b/cmd/mem.c index b8afe62e474..3bba46ad7da 100644 --- a/cmd/mem.c +++ b/cmd/mem.c @@ -719,12 +719,9 @@ static ulong mem_test_alt(vu_long *buf, ulong start_addr, ulong end_addr, ulong errs = 0; ulong val, readback; int j; - vu_long offset; - vu_long test_offset; - vu_long pattern; - vu_long temp; - vu_long anti_pattern; - vu_long num_words; + ulong offset, test_offset; + ulong pattern, anti_pattern; + ulong temp, num_words; static const ulong bitpattern[] = { 0x00000001, /* single bit */ 0x00000003, /* two adjacent bits */ -- cgit v1.2.3 From 835915bb7d2b76d7e422b6d60628a0f7cef30ddb Mon Sep 17 00:00:00 2001 From: Rasmus Villemoes Date: Fri, 22 Aug 2025 20:18:47 +0200 Subject: memtest: only call schedule() once for every 256 words A function call itself for every word written or read+written in these loops is bad enough. But since the memory test must be run with dcache disabled, the schedule() call, traversing the linked list of registered cyclic clients, and accessing the 'struct cyclic_info' for each to see if any are due for a callback, is quite expensive. On a beagleboneblack, testing a modest 16MiB region takes 2.5 minutes: => dcache off => time mtest 0x81000000 0x82000000 0 1 Testing 81000000 ... 82000000: Iteration: 1 Tested 1 iteration(s) with 0 errors. time: 2 minutes, 28.946 seconds There is really no need for calling schedule() so frequently. It is quite easy to limit the calls to once for every 256 words by using a u8 variable. With that, the same test as above becomes 37 times faster: => dcache off => time mtest 0x81000000 0x82000000 0 1 Testing 81000000 ... 82000000: Iteration: 1 Tested 1 iteration(s) with 0 errors. time: 4.052 seconds Note that we are still making a total of 3 loops * (4 * 2^20 words/loop) / (256 words/call) = 49152 calls during those ~4000 milliseconds, so the schedule() calls are still done less than 0.1ms apart. These numbers are just for a beagleboneblack, other boards may have a slower memory, but we are _two orders of magnitude_ away from schedule() "only" being called at 100Hz, which is still more than enough to ensure any watchdog is kept happy. Signed-off-by: Rasmus Villemoes Tested-by: Anshul Dalal --- cmd/mem.c | 11 ++++++++--- 1 file changed, 8 insertions(+), 3 deletions(-) diff --git a/cmd/mem.c b/cmd/mem.c index 3bba46ad7da..b67368dfba5 100644 --- a/cmd/mem.c +++ b/cmd/mem.c @@ -732,6 +732,8 @@ static ulong mem_test_alt(vu_long *buf, ulong start_addr, ulong end_addr, 0x00000055, /* four non-adjacent bits */ 0xaaaaaaaa, /* alternating 1/0 */ }; + /* Rate-limit schedule() calls to one for every 256 words. */ + u8 count = 0; num_words = (end_addr - start_addr) / sizeof(vu_long); @@ -887,7 +889,8 @@ static ulong mem_test_alt(vu_long *buf, ulong start_addr, ulong end_addr, * Fill memory with a known pattern. */ for (pattern = 1, offset = 0; offset < num_words; pattern++, offset++) { - schedule(); + if (!count++) + schedule(); addr[offset] = pattern; } @@ -895,7 +898,8 @@ static ulong mem_test_alt(vu_long *buf, ulong start_addr, ulong end_addr, * Check each location and invert it for the second pass. */ for (pattern = 1, offset = 0; offset < num_words; pattern++, offset++) { - schedule(); + if (!count++) + schedule(); temp = addr[offset]; if (temp != pattern) { printf("\nFAILURE (read/write) @ 0x%.8lx:" @@ -915,7 +919,8 @@ static ulong mem_test_alt(vu_long *buf, ulong start_addr, ulong end_addr, * Check each location for the inverted pattern and zero it. */ for (pattern = 1, offset = 0; offset < num_words; pattern++, offset++) { - schedule(); + if (!count++) + schedule(); anti_pattern = ~pattern; temp = addr[offset]; if (temp != anti_pattern) { -- cgit v1.2.3 From 42529beba5a262992b53893477e0de646c1754b6 Mon Sep 17 00:00:00 2001 From: Rasmus Villemoes Date: Fri, 22 Aug 2025 20:18:48 +0200 Subject: memtest: remove use of vu_long typedef in mem_test_alt Hiding a qualifier such as "volatile" inside a typedef makes the code much harder to understand. Since addr and dummy being volatile-qualified are important for the correctness of the test code, make it more obvious by spelling it out as "volatile ulong". Signed-off-by: Rasmus Villemoes Tested-by: Anshul Dalal --- cmd/mem.c | 20 ++++++++++---------- 1 file changed, 10 insertions(+), 10 deletions(-) diff --git a/cmd/mem.c b/cmd/mem.c index b67368dfba5..d5d7ca2790b 100644 --- a/cmd/mem.c +++ b/cmd/mem.c @@ -712,10 +712,10 @@ static int do_mem_loopw(struct cmd_tbl *cmdtp, int flag, int argc, #endif /* CONFIG_LOOPW */ #ifdef CONFIG_CMD_MEMTEST -static ulong mem_test_alt(vu_long *buf, ulong start_addr, ulong end_addr, - vu_long *dummy) +static ulong mem_test_alt(volatile ulong *buf, ulong start_addr, ulong end_addr, + volatile ulong *dummy) { - vu_long *addr; + volatile ulong *addr; ulong errs = 0; ulong val, readback; int j; @@ -735,7 +735,7 @@ static ulong mem_test_alt(vu_long *buf, ulong start_addr, ulong end_addr, /* Rate-limit schedule() calls to one for every 256 words. */ u8 count = 0; - num_words = (end_addr - start_addr) / sizeof(vu_long); + num_words = (end_addr - start_addr) / sizeof(ulong); /* * Data line test: write a pattern to the first @@ -817,8 +817,8 @@ static ulong mem_test_alt(vu_long *buf, ulong start_addr, ulong end_addr, * * Returns: 0 if the test succeeds, 1 if the test fails. */ - pattern = (vu_long)0xaaaaaaaaaaaaaaaa; - anti_pattern = (vu_long)0x5555555555555555; + pattern = (ulong)0xaaaaaaaaaaaaaaaa; + anti_pattern = (ulong)0x5555555555555555; debug("%s:%d: length = 0x%.8lx\n", __func__, __LINE__, num_words); /* @@ -839,7 +839,7 @@ static ulong mem_test_alt(vu_long *buf, ulong start_addr, ulong end_addr, if (temp != pattern) { printf("\nFAILURE: Address bit stuck high @ 0x%.8lx:" " expected 0x%.8lx, actual 0x%.8lx\n", - start_addr + offset*sizeof(vu_long), + start_addr + offset*sizeof(ulong), pattern, temp); errs++; if (ctrlc()) @@ -861,7 +861,7 @@ static ulong mem_test_alt(vu_long *buf, ulong start_addr, ulong end_addr, printf("\nFAILURE: Address bit stuck low or" " shorted @ 0x%.8lx: expected 0x%.8lx," " actual 0x%.8lx\n", - start_addr + offset*sizeof(vu_long), + start_addr + offset*sizeof(ulong), pattern, temp); errs++; if (ctrlc()) @@ -904,7 +904,7 @@ static ulong mem_test_alt(vu_long *buf, ulong start_addr, ulong end_addr, if (temp != pattern) { printf("\nFAILURE (read/write) @ 0x%.8lx:" " expected 0x%.8lx, actual 0x%.8lx)\n", - start_addr + offset*sizeof(vu_long), + start_addr + offset*sizeof(ulong), pattern, temp); errs++; if (ctrlc()) @@ -926,7 +926,7 @@ static ulong mem_test_alt(vu_long *buf, ulong start_addr, ulong end_addr, if (temp != anti_pattern) { printf("\nFAILURE (read/write): @ 0x%.8lx:" " expected 0x%.8lx, actual 0x%.8lx)\n", - start_addr + offset*sizeof(vu_long), + start_addr + offset*sizeof(ulong), anti_pattern, temp); errs++; if (ctrlc()) -- cgit v1.2.3 From eb314cb566abe0c6eb675c9c857a0cd1bb8c5cf9 Mon Sep 17 00:00:00 2001 From: Frieder Schrempf Date: Mon, 25 Aug 2025 15:54:25 +0200 Subject: imx: kontron-sl-mx6ul: Fix include statements for local header The header from the local directory should use double quotes instead of brackets. Otherwise the compiler might not search the local directory. Fixes: 93935acc6f1d ("imx: imx6ul: kontron-sl-mx6ul: Select correct boot and env device") Signed-off-by: Frieder Schrempf --- board/kontron/sl-mx6ul/sl-mx6ul-common.c | 2 +- board/kontron/sl-mx6ul/sl-mx6ul.c | 3 ++- board/kontron/sl-mx6ul/spl.c | 3 ++- 3 files changed, 5 insertions(+), 3 deletions(-) diff --git a/board/kontron/sl-mx6ul/sl-mx6ul-common.c b/board/kontron/sl-mx6ul/sl-mx6ul-common.c index 1f24acdfa3d..bda71a330ca 100644 --- a/board/kontron/sl-mx6ul/sl-mx6ul-common.c +++ b/board/kontron/sl-mx6ul/sl-mx6ul-common.c @@ -6,7 +6,7 @@ #include #include -#include +#include "sl-mx6ul-common.h" bool sl_mx6ul_is_spi_nor_boot(void) { diff --git a/board/kontron/sl-mx6ul/sl-mx6ul.c b/board/kontron/sl-mx6ul/sl-mx6ul.c index 0f45ea84fc7..16d89c64d61 100644 --- a/board/kontron/sl-mx6ul/sl-mx6ul.c +++ b/board/kontron/sl-mx6ul/sl-mx6ul.c @@ -9,7 +9,8 @@ #include #include #include -#include + +#include "sl-mx6ul-common.h" DECLARE_GLOBAL_DATA_PTR; diff --git a/board/kontron/sl-mx6ul/spl.c b/board/kontron/sl-mx6ul/spl.c index 33e5337bcbc..8d55273dd9c 100644 --- a/board/kontron/sl-mx6ul/spl.c +++ b/board/kontron/sl-mx6ul/spl.c @@ -18,7 +18,8 @@ #include #include #include -#include + +#include "sl-mx6ul-common.h" DECLARE_GLOBAL_DATA_PTR; -- cgit v1.2.3 From 7118d961cccdb3cf86f3e2eebf19c476bba5aca9 Mon Sep 17 00:00:00 2001 From: Frieder Schrempf Date: Mon, 25 Aug 2025 15:54:26 +0200 Subject: imx: kontron-sl-mx6ul: Enable standard boot and disable legacy distro boot Disable the legacy distro boot and use bootstd instead. Signed-off-by: Frieder Schrempf --- configs/kontron-sl-mx6ul_defconfig | 3 ++- include/configs/kontron-sl-mx6ul.h | 12 ------------ 2 files changed, 2 insertions(+), 13 deletions(-) diff --git a/configs/kontron-sl-mx6ul_defconfig b/configs/kontron-sl-mx6ul_defconfig index 9ee02259948..b04cd75a7d4 100644 --- a/configs/kontron-sl-mx6ul_defconfig +++ b/configs/kontron-sl-mx6ul_defconfig @@ -25,7 +25,7 @@ CONFIG_SYS_MEMTEST_START=0x80000000 CONFIG_SYS_MEMTEST_END=0x90000000 CONFIG_FIT=y CONFIG_SPL_LOAD_FIT=y -CONFIG_DISTRO_DEFAULTS=y +CONFIG_BOOTSTD_FULL=y CONFIG_OF_BOARD_SETUP=y CONFIG_FDT_FIXUP_PARTITIONS=y CONFIG_SYS_PBSIZE=532 @@ -50,6 +50,7 @@ CONFIG_CMD_USB=y CONFIG_CMD_USB_SDP=y CONFIG_CMD_USB_MASS_STORAGE=y CONFIG_CMD_CACHE=y +CONFIG_CMD_SYSBOOT=y CONFIG_CMD_EXT4_WRITE=y CONFIG_CMD_FS_UUID=y CONFIG_CMD_MTDPARTS=y diff --git a/include/configs/kontron-sl-mx6ul.h b/include/configs/kontron-sl-mx6ul.h index 015df01db4e..e2152eb05ed 100644 --- a/include/configs/kontron-sl-mx6ul.h +++ b/include/configs/kontron-sl-mx6ul.h @@ -24,22 +24,10 @@ /* Board and environment settings */ #define CFG_MXC_UART_BASE UART4_BASE -/* Boot order for distro boot */ -#define BOOT_TARGET_DEVICES(func) \ - func(MMC, mmc, 1) \ - func(MMC, mmc, 0) \ - func(UBIFS, ubifs, 0, UBI, boot) \ - func(USB, usb, 0) \ - func(PXE, pxe, na) \ - func(DHCP, dhcp, na) -#include - /* MMC Configs */ #ifdef CONFIG_FSL_USDHC #define CFG_SYS_FSL_ESDHC_ADDR USDHC1_BASE_ADDR #define CFG_SYS_FSL_USDHC_NUM 2 #endif -#define CFG_EXTRA_ENV_SETTINGS BOOTENV - #endif /* __KONTRON_MX6UL_CONFIG_H */ -- cgit v1.2.3 From 8addeb94c72bfac9561a1bae3844a94c05cefb47 Mon Sep 17 00:00:00 2001 From: Frieder Schrempf Date: Mon, 25 Aug 2025 15:54:27 +0200 Subject: imx: kontron-sl-mx6ul: Set CONFIG_SDP_LOADADDR to fix SDP boot We need to set CONFIG_SDP_LOADADDR to a valid RAM address to make SDP boot work. Use the end of the DDR (256 MiB minimum) as other boards do. Signed-off-by: Frieder Schrempf --- configs/kontron-sl-mx6ul_defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/configs/kontron-sl-mx6ul_defconfig b/configs/kontron-sl-mx6ul_defconfig index b04cd75a7d4..7ecf2bbaa9f 100644 --- a/configs/kontron-sl-mx6ul_defconfig +++ b/configs/kontron-sl-mx6ul_defconfig @@ -107,5 +107,6 @@ CONFIG_USB_GADGET_MANUFACTURER="FSL" CONFIG_USB_GADGET_VENDOR_NUM=0x0525 CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 CONFIG_CI_UDC=y +CONFIG_SDP_LOADADDR=0x8f7fffc0 CONFIG_USB_GADGET_DOWNLOAD=y CONFIG_SPL_USB_SDP_SUPPORT=y -- cgit v1.2.3 From 048fdda977abe8ebb51dfab7450f7a5b80465059 Mon Sep 17 00:00:00 2001 From: Frieder Schrempf Date: Mon, 25 Aug 2025 15:54:28 +0200 Subject: imx: kontron-sl-mx6ul: Enable second ethernet interface This ensures both interfaces can be used in U-Boot and both MAC addresses are exported to the Linux kernel devicetree. Signed-off-by: Frieder Schrempf --- arch/arm/dts/imx6ul-kontron-bl-common-u-boot.dtsi | 12 +++++++----- 1 file changed, 7 insertions(+), 5 deletions(-) diff --git a/arch/arm/dts/imx6ul-kontron-bl-common-u-boot.dtsi b/arch/arm/dts/imx6ul-kontron-bl-common-u-boot.dtsi index 39cc6d05d3f..042bda7462a 100644 --- a/arch/arm/dts/imx6ul-kontron-bl-common-u-boot.dtsi +++ b/arch/arm/dts/imx6ul-kontron-bl-common-u-boot.dtsi @@ -30,9 +30,6 @@ * in Linux we can't assign the shared reset GPIO to the PHYs, as this * would cause Linux to reset both PHYs every time one of them gets * reinitialized. - * - * Also we disable the second ethernet as it currently doesn't work with - * the devicetree setup in U-Boot. */ &fec1 { @@ -53,11 +50,16 @@ clocks = <&clks IMX6UL_CLK_ENET_REF>; clock-names = "rmii-ref"; }; + + ethphy2: ethernet-phy@2 { + reg = <2>; + micrel,led-mode = <0>; + clocks = <&clks IMX6UL_CLK_ENET2_REF>; + clock-names = "rmii-ref"; + }; }; }; &fec2 { - status = "disabled"; - /delete-property/ phy-handle; /delete-node/ mdio; }; -- cgit v1.2.3 From f3406a2364eaac81735594d5cb6c10d38bd25c8f Mon Sep 17 00:00:00 2001 From: Annette Kobou Date: Mon, 25 Aug 2025 15:54:29 +0200 Subject: imx: kontron-sl-mx6ul: Enable fastboot support Enable support for fastboot commands via USB. Signed-off-by: Annette Kobou Signed-off-by: Frieder Schrempf --- configs/kontron-sl-mx6ul_defconfig | 9 ++++++++- 1 file changed, 8 insertions(+), 1 deletion(-) diff --git a/configs/kontron-sl-mx6ul_defconfig b/configs/kontron-sl-mx6ul_defconfig index 7ecf2bbaa9f..1831f99db46 100644 --- a/configs/kontron-sl-mx6ul_defconfig +++ b/configs/kontron-sl-mx6ul_defconfig @@ -23,6 +23,7 @@ CONFIG_SPL_SPI_FLASH_SUPPORT=y CONFIG_SPL_SPI=y CONFIG_SYS_MEMTEST_START=0x80000000 CONFIG_SYS_MEMTEST_END=0x90000000 +# CONFIG_ANDROID_BOOT_IMAGE is not set CONFIG_FIT=y CONFIG_SPL_LOAD_FIT=y CONFIG_BOOTSTD_FULL=y @@ -69,6 +70,13 @@ CONFIG_USE_HOSTNAME=y CONFIG_HOSTNAME="kontron-mx6ul" CONFIG_BOOTCOUNT_LIMIT=y CONFIG_BOOTCOUNT_ENV=y +CONFIG_USB_FUNCTION_FASTBOOT=y +CONFIG_FASTBOOT_FLASH=y +CONFIG_FASTBOOT_UUU_SUPPORT=y +CONFIG_FASTBOOT_FLASH_MMC_DEV=0 +CONFIG_FASTBOOT_MMC_BOOT_SUPPORT=y +CONFIG_FASTBOOT_MMC_USER_SUPPORT=y +CONFIG_FASTBOOT_MMC_USER_NAME="mmc1" CONFIG_DM_I2C=y CONFIG_FSL_USDHC=y CONFIG_MTD=y @@ -108,5 +116,4 @@ CONFIG_USB_GADGET_VENDOR_NUM=0x0525 CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 CONFIG_CI_UDC=y CONFIG_SDP_LOADADDR=0x8f7fffc0 -CONFIG_USB_GADGET_DOWNLOAD=y CONFIG_SPL_USB_SDP_SUPPORT=y -- cgit v1.2.3 From 6bd59313e0c9550e49d1973d664f896dab08c8f9 Mon Sep 17 00:00:00 2001 From: Oualid Derouiche Date: Mon, 25 Aug 2025 15:54:30 +0200 Subject: imx: kontron-sl-mx6ul: Enable redundant environment This aligns the MTD partitions on the SPI NOR with the kernel devicetree and enables the redundant environment. Signed-off-by: Oualid Derouiche Signed-off-by: Frieder Schrempf --- configs/kontron-sl-mx6ul_defconfig | 8 +++++--- 1 file changed, 5 insertions(+), 3 deletions(-) diff --git a/configs/kontron-sl-mx6ul_defconfig b/configs/kontron-sl-mx6ul_defconfig index 1831f99db46..a5ee4d67c00 100644 --- a/configs/kontron-sl-mx6ul_defconfig +++ b/configs/kontron-sl-mx6ul_defconfig @@ -7,9 +7,9 @@ CONFIG_SPL_LIBCOMMON_SUPPORT=y CONFIG_SPL_LIBGENERIC_SUPPORT=y CONFIG_NR_DRAM_BANKS=1 CONFIG_SF_DEFAULT_SPEED=10000000 -CONFIG_ENV_SIZE=0x10000 +CONFIG_ENV_SIZE=0x8000 CONFIG_ENV_OFFSET=0xF0000 -CONFIG_ENV_SECT_SIZE=0x10000 +CONFIG_ENV_SECT_SIZE=0x4000 CONFIG_MX6UL=y CONFIG_TARGET_KONTRON_MX6UL=y CONFIG_DM_GPIO=y @@ -19,6 +19,7 @@ CONFIG_SPL_SERIAL=y CONFIG_BOOTCOUNT_BOOTLIMIT=3 CONFIG_SF_DEFAULT_BUS=1 CONFIG_SPL=y +CONFIG_ENV_OFFSET_REDUND=0xF8000 CONFIG_SPL_SPI_FLASH_SUPPORT=y CONFIG_SPL_SPI=y CONFIG_SYS_MEMTEST_START=0x80000000 @@ -56,7 +57,7 @@ CONFIG_CMD_EXT4_WRITE=y CONFIG_CMD_FS_UUID=y CONFIG_CMD_MTDPARTS=y CONFIG_MTDIDS_DEFAULT="nor0=spi1.0,spi-nand0=spi4.0" -CONFIG_MTDPARTS_DEFAULT="mtdparts=spi1.0:128k(spl),832k(u-boot),64k(env);spi4.0:-(UBI)" +CONFIG_MTDPARTS_DEFAULT="mtdparts=spi1.0:960k(u-boot),32k(env),32k(env_redundant);spi4.0:-(UBI)" CONFIG_CMD_UBI=y CONFIG_OF_CONTROL=y CONFIG_SPL_OF_CONTROL=y @@ -64,6 +65,7 @@ CONFIG_OF_LIST="imx6ul-kontron-bl imx6ull-kontron-bl" CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_MMC=y CONFIG_ENV_IS_IN_SPI_FLASH=y +CONFIG_ENV_REDUNDANT=y CONFIG_USE_ETHPRIME=y CONFIG_ETHPRIME="eth0" CONFIG_USE_HOSTNAME=y -- cgit v1.2.3 From 410d9ccc0388b77b1e21ba218b2e21138930c90f Mon Sep 17 00:00:00 2001 From: Annette Kobou Date: Mon, 25 Aug 2025 15:54:31 +0200 Subject: imx: kontron-sl-mx6ul: Autostart fastboot if booted from USB For booting via USB we want to automatically start the fastboot command in order to access the board via uuu or other tools. This allows for easier bringup of new boards during development and manufacturing. Signed-off-by: Annette Kobou Signed-off-by: Frieder Schrempf --- board/kontron/sl-mx6ul/sl-mx6ul.c | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/board/kontron/sl-mx6ul/sl-mx6ul.c b/board/kontron/sl-mx6ul/sl-mx6ul.c index 16d89c64d61..e33907ee124 100644 --- a/board/kontron/sl-mx6ul/sl-mx6ul.c +++ b/board/kontron/sl-mx6ul/sl-mx6ul.c @@ -5,7 +5,9 @@ #include #include +#include #include +#include #include #include #include @@ -87,6 +89,16 @@ int board_init(void) return 0; } +int board_late_init(void) +{ + if (is_boot_from_usb()) { + env_set("bootdelay", "0"); + env_set("bootcmd", "fastboot 0"); + } + + return 0; +} + enum env_location env_get_location(enum env_operation op, int prio) { if (prio) -- cgit v1.2.3 From 9e26426ceb0aacc52b3cf693fdeac3b13cb8e6f9 Mon Sep 17 00:00:00 2001 From: Frieder Schrempf Date: Mon, 25 Aug 2025 15:54:32 +0200 Subject: imx: kontron-sl-mx6ul: Enable watchdog and sysreset Enable the watchdog and sysreset drivers and the wdt command. This also fixes the non-working 'reset' command. Signed-off-by: Frieder Schrempf --- configs/kontron-sl-mx6ul_defconfig | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/configs/kontron-sl-mx6ul_defconfig b/configs/kontron-sl-mx6ul_defconfig index a5ee4d67c00..fed29e77936 100644 --- a/configs/kontron-sl-mx6ul_defconfig +++ b/configs/kontron-sl-mx6ul_defconfig @@ -51,6 +51,7 @@ CONFIG_CMD_SF_TEST=y CONFIG_CMD_USB=y CONFIG_CMD_USB_SDP=y CONFIG_CMD_USB_MASS_STORAGE=y +CONFIG_CMD_WDT=y CONFIG_CMD_CACHE=y CONFIG_CMD_SYSBOOT=y CONFIG_CMD_EXT4_WRITE=y @@ -107,6 +108,9 @@ CONFIG_DM_SPI=y CONFIG_FSL_QSPI=y # CONFIG_FSL_QSPI_AHB_FULL_MAP is not set CONFIG_MXC_SPI=y +CONFIG_SYSRESET=y +CONFIG_SYSRESET_WATCHDOG=y +CONFIG_SYSRESET_WATCHDOG_AUTO=y CONFIG_IMX_THERMAL=y CONFIG_USB=y CONFIG_SPL_USB_HOST=y @@ -119,3 +123,4 @@ CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 CONFIG_CI_UDC=y CONFIG_SDP_LOADADDR=0x8f7fffc0 CONFIG_SPL_USB_SDP_SUPPORT=y +CONFIG_IMX_WATCHDOG=y -- cgit v1.2.3 From 827e45f28ffb60eae4ce839d22121eda4c34a458 Mon Sep 17 00:00:00 2001 From: Eberhard Stoll Date: Mon, 25 Aug 2025 15:54:33 +0200 Subject: imx: kontron-sl-mx6ul: Enable CONFIG_ENV_IS_NOWHERE For some cases it is beneficial to not store the environment in persistent memory, but instead use the default environment and keep it in volatile RAM only. Allow this by enabling CONFIG_ENV_IS_NOWHERE. Signed-off-by: Eberhard Stoll Signed-off-by: Frieder Schrempf --- configs/kontron-sl-mx6ul_defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/configs/kontron-sl-mx6ul_defconfig b/configs/kontron-sl-mx6ul_defconfig index fed29e77936..052d7a76610 100644 --- a/configs/kontron-sl-mx6ul_defconfig +++ b/configs/kontron-sl-mx6ul_defconfig @@ -64,6 +64,7 @@ CONFIG_OF_CONTROL=y CONFIG_SPL_OF_CONTROL=y CONFIG_OF_LIST="imx6ul-kontron-bl imx6ull-kontron-bl" CONFIG_ENV_OVERWRITE=y +CONFIG_ENV_IS_NOWHERE=y CONFIG_ENV_IS_IN_MMC=y CONFIG_ENV_IS_IN_SPI_FLASH=y CONFIG_ENV_REDUNDANT=y -- cgit v1.2.3 From 6bfd81c3394cfa02d9e5d45e8ad4ca8634b177fe Mon Sep 17 00:00:00 2001 From: Eberhard Stoll Date: Mon, 25 Aug 2025 15:54:34 +0200 Subject: imx: kontron-sl-mx6ul: Force default environment for serial loader boot In case of booting from serial loader (USB) we want to always use the default environment in order to get a defined state that is independent of any environment stored in persistent memory. This way we can avoid corruption of the boot process during development and manufacturing by existing environment settings in flash. Signed-off-by: Eberhard Stoll Signed-off-by: Frieder Schrempf --- board/kontron/sl-mx6ul/sl-mx6ul.c | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) diff --git a/board/kontron/sl-mx6ul/sl-mx6ul.c b/board/kontron/sl-mx6ul/sl-mx6ul.c index e33907ee124..65f9b75c1a0 100644 --- a/board/kontron/sl-mx6ul/sl-mx6ul.c +++ b/board/kontron/sl-mx6ul/sl-mx6ul.c @@ -104,10 +104,16 @@ enum env_location env_get_location(enum env_operation op, int prio) if (prio) return ENVL_UNKNOWN; + if (CONFIG_IS_ENABLED(ENV_IS_NOWHERE) && is_boot_from_usb()) + return ENVL_NOWHERE; + if (sl_mx6ul_is_spi_nor_boot() && CONFIG_IS_ENABLED(ENV_IS_IN_SPI_FLASH)) return ENVL_SPI_FLASH; else if (CONFIG_IS_ENABLED(ENV_IS_IN_MMC)) return ENVL_MMC; - return ENVL_NOWHERE; + if (CONFIG_IS_ENABLED(ENV_IS_NOWHERE)) + return ENVL_NOWHERE; + + return ENVL_UNKNOWN; } -- cgit v1.2.3 From 1f87a8ac6b3d1823b908615ff210065683fda805 Mon Sep 17 00:00:00 2001 From: Frieder Schrempf Date: Mon, 25 Aug 2025 15:54:35 +0200 Subject: imx: kontron-sl-mx6ul: Switch to OF_UPSTREAM Use the upstream devicetrees instead of the local ones. Signed-off-by: Frieder Schrempf [fabio: Remove imx6ul-kontron-bl.dtb and imx6ull-kontron-bl.dtb from Makefile] --- arch/arm/dts/Makefile | 4 +- arch/arm/dts/imx6ul-kontron-bl-43.dts | 103 -------- arch/arm/dts/imx6ul-kontron-bl-common.dtsi | 406 ----------------------------- arch/arm/dts/imx6ul-kontron-bl.dts | 16 -- arch/arm/dts/imx6ul-kontron-sl-common.dtsi | 137 ---------- arch/arm/dts/imx6ul-kontron-sl.dtsi | 14 - arch/arm/dts/imx6ull-kontron-bl.dts | 15 -- arch/arm/dts/imx6ull-kontron-sl.dtsi | 13 - configs/kontron-sl-mx6ul_defconfig | 5 +- 9 files changed, 4 insertions(+), 709 deletions(-) delete mode 100644 arch/arm/dts/imx6ul-kontron-bl-43.dts delete mode 100644 arch/arm/dts/imx6ul-kontron-bl-common.dtsi delete mode 100644 arch/arm/dts/imx6ul-kontron-bl.dts delete mode 100644 arch/arm/dts/imx6ul-kontron-sl-common.dtsi delete mode 100644 arch/arm/dts/imx6ul-kontron-sl.dtsi delete mode 100644 arch/arm/dts/imx6ull-kontron-bl.dts delete mode 100644 arch/arm/dts/imx6ull-kontron-sl.dtsi diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index ff8f1ed1ac0..7ada4131ab2 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -833,9 +833,7 @@ dtb-$(CONFIG_MX6UL) += \ imx6ul-liteboard.dtb \ imx6ul-phytec-segin-ff-rdk-nand.dtb \ imx6ul-pico-hobbit.dtb \ - imx6ul-pico-pi.dtb \ - imx6ul-kontron-bl.dtb \ - imx6ull-kontron-bl.dtb + imx6ul-pico-pi.dtb dtb-$(CONFIG_MX6ULL) += \ imx6ull-14x14-evk.dtb \ diff --git a/arch/arm/dts/imx6ul-kontron-bl-43.dts b/arch/arm/dts/imx6ul-kontron-bl-43.dts deleted file mode 100644 index 0c643706a15..00000000000 --- a/arch/arm/dts/imx6ul-kontron-bl-43.dts +++ /dev/null @@ -1,103 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Copyright (C) 2017 exceet electronics GmbH - * Copyright (C) 2018 Kontron Electronics GmbH - * Copyright (c) 2019 Krzysztof Kozlowski - */ - -#include "imx6ul-kontron-bl.dts" - -/ { - model = "Kontron BL i.MX6UL 43 (N631X S 43)"; - compatible = "kontron,bl-imx6ul-43", "kontron,bl-imx6ul", - "kontron,sl-imx6ul", "fsl,imx6ul"; - - backlight { - compatible = "pwm-backlight"; - pwms = <&pwm7 0 5000000>; - brightness-levels = <0 4 8 16 32 64 128 255>; - default-brightness-level = <6>; - status = "okay"; - }; -}; - -&i2c4 { - touchscreen@5d { - compatible = "goodix,gt928"; - reg = <0x5d>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_cap_touch>; - interrupt-parent = <&gpio5>; - interrupts = <6 IRQ_TYPE_LEVEL_LOW>; - reset-gpios = <&gpio5 8 GPIO_ACTIVE_HIGH>; - irq-gpios = <&gpio5 6 GPIO_ACTIVE_HIGH>; - }; -}; - -&lcdif { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_lcdif_dat &pinctrl_lcdif_ctrl>; - /* Leave status disabled because of missing display panel node */ -}; - -&pwm7 { - #pwm-cells = <2>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pwm7>; - status = "okay"; -}; - -&iomuxc { - pinctrl_cap_touch: captouchgrp { - fsl,pins = < - MX6UL_PAD_SNVS_TAMPER6__GPIO5_IO06 0x1b0b0 /* Touch Interrupt */ - MX6UL_PAD_SNVS_TAMPER7__GPIO5_IO07 0x1b0b0 /* Touch Reset */ - MX6UL_PAD_SNVS_TAMPER8__GPIO5_IO08 0x1b0b0 /* Touch Wake */ - >; - }; - - pinctrl_lcdif_ctrl: lcdifctrlgrp { - fsl,pins = < - MX6UL_PAD_LCD_CLK__LCDIF_CLK 0x79 - MX6UL_PAD_LCD_ENABLE__LCDIF_ENABLE 0x79 - MX6UL_PAD_LCD_HSYNC__LCDIF_HSYNC 0x79 - MX6UL_PAD_LCD_VSYNC__LCDIF_VSYNC 0x79 - MX6UL_PAD_LCD_RESET__LCDIF_RESET 0x79 - >; - }; - - pinctrl_lcdif_dat: lcdifdatgrp { - fsl,pins = < - MX6UL_PAD_LCD_DATA00__LCDIF_DATA00 0x79 - MX6UL_PAD_LCD_DATA01__LCDIF_DATA01 0x79 - MX6UL_PAD_LCD_DATA02__LCDIF_DATA02 0x79 - MX6UL_PAD_LCD_DATA03__LCDIF_DATA03 0x79 - MX6UL_PAD_LCD_DATA04__LCDIF_DATA04 0x79 - MX6UL_PAD_LCD_DATA05__LCDIF_DATA05 0x79 - MX6UL_PAD_LCD_DATA06__LCDIF_DATA06 0x79 - MX6UL_PAD_LCD_DATA07__LCDIF_DATA07 0x79 - MX6UL_PAD_LCD_DATA08__LCDIF_DATA08 0x79 - MX6UL_PAD_LCD_DATA09__LCDIF_DATA09 0x79 - MX6UL_PAD_LCD_DATA10__LCDIF_DATA10 0x79 - MX6UL_PAD_LCD_DATA11__LCDIF_DATA11 0x79 - MX6UL_PAD_LCD_DATA12__LCDIF_DATA12 0x79 - MX6UL_PAD_LCD_DATA13__LCDIF_DATA13 0x79 - MX6UL_PAD_LCD_DATA14__LCDIF_DATA14 0x79 - MX6UL_PAD_LCD_DATA15__LCDIF_DATA15 0x79 - MX6UL_PAD_LCD_DATA16__LCDIF_DATA16 0x79 - MX6UL_PAD_LCD_DATA17__LCDIF_DATA17 0x79 - MX6UL_PAD_LCD_DATA18__LCDIF_DATA18 0x79 - MX6UL_PAD_LCD_DATA19__LCDIF_DATA19 0x79 - MX6UL_PAD_LCD_DATA20__LCDIF_DATA20 0x79 - MX6UL_PAD_LCD_DATA21__LCDIF_DATA21 0x79 - MX6UL_PAD_LCD_DATA22__LCDIF_DATA22 0x79 - MX6UL_PAD_LCD_DATA23__LCDIF_DATA23 0x79 - >; - }; - - pinctrl_pwm7: pwm7grp { - fsl,pins = < - MX6UL_PAD_CSI_VSYNC__PWM7_OUT 0x110b0 - >; - }; -}; diff --git a/arch/arm/dts/imx6ul-kontron-bl-common.dtsi b/arch/arm/dts/imx6ul-kontron-bl-common.dtsi deleted file mode 100644 index a6cf0f21c66..00000000000 --- a/arch/arm/dts/imx6ul-kontron-bl-common.dtsi +++ /dev/null @@ -1,406 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Copyright (C) 2017 exceet electronics GmbH - * Copyright (C) 2018 Kontron Electronics GmbH - * Copyright (c) 2019 Krzysztof Kozlowski - */ - -#include - -/ { - gpio-leds { - compatible = "gpio-leds"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_gpio_leds>; - - led1 { - label = "debug-led1"; - gpios = <&gpio1 30 GPIO_ACTIVE_LOW>; - default-state = "off"; - linux,default-trigger = "heartbeat"; - }; - - led2 { - label = "debug-led2"; - gpios = <&gpio5 3 GPIO_ACTIVE_LOW>; - default-state = "off"; - }; - - led3 { - label = "debug-led3"; - gpios = <&gpio5 2 GPIO_ACTIVE_LOW>; - default-state = "off"; - }; - }; - - pwm-beeper { - compatible = "pwm-beeper"; - pwms = <&pwm8 0 5000>; - }; - - reg_3v3: regulator-3v3 { - compatible = "regulator-fixed"; - regulator-name = "3v3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - reg_5v: regulator-5v { - compatible = "regulator-fixed"; - regulator-name = "5v"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - }; - - reg_usb_otg1_vbus: regulator-usb-otg1-vbus { - compatible = "regulator-fixed"; - regulator-name = "usb_otg1_vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - gpio = <&gpio1 4 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - reg_vref_adc: regulator-vref-adc { - compatible = "regulator-fixed"; - regulator-name = "vref-adc"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; -}; - -&adc1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_adc1>; - num-channels = <3>; - vref-supply = <®_vref_adc>; - status = "okay"; -}; - -&can2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_flexcan2>; - status = "okay"; -}; - -&ecspi1 { - cs-gpios = <&gpio4 26 GPIO_ACTIVE_LOW>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ecspi1>; - status = "okay"; - - eeprom@0 { - compatible = "anvo,anv32e61w", "atmel,at25"; - reg = <0>; - spi-max-frequency = <20000000>; - spi-cpha; - spi-cpol; - pagesize = <1>; - size = <8192>; - address-width = <16>; - }; -}; - -&fec1 { - pinctrl-0 = <&pinctrl_enet1>; - /delete-node/ mdio; -}; - -&fec2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_enet2 &pinctrl_enet2_mdio>; - phy-mode = "rmii"; - phy-handle = <ðphy2>; - status = "okay"; - - mdio { - #address-cells = <1>; - #size-cells = <0>; - - ethphy1: ethernet-phy@1 { - reg = <1>; - micrel,led-mode = <0>; - clocks = <&clks IMX6UL_CLK_ENET_REF>; - clock-names = "rmii-ref"; - }; - - ethphy2: ethernet-phy@2 { - reg = <2>; - micrel,led-mode = <0>; - clocks = <&clks IMX6UL_CLK_ENET2_REF>; - clock-names = "rmii-ref"; - }; - }; -}; - -&i2c1 { - clock-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c1>; - status = "okay"; -}; - -&i2c4 { - clock-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c4>; - status = "okay"; - - rtc@32 { - compatible = "epson,rx8900"; - reg = <0x32>; - }; -}; - -&pwm8 { - #pwm-cells = <2>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pwm8>; - status = "okay"; -}; - -&uart1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart1>; - status = "okay"; -}; - -&uart2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart2>; - linux,rs485-enabled-at-boot-time; - rs485-rx-during-tx; - rs485-rts-active-low; - uart-has-rtscts; - status = "okay"; -}; - -&uart3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart3>; - uart-has-rtscts; - status = "okay"; -}; - -&uart4 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart4>; - status = "okay"; -}; - -&usbotg1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usbotg1>; - dr_mode = "otg"; - srp-disable; - hnp-disable; - adp-disable; - over-current-active-low; - vbus-supply = <®_usb_otg1_vbus>; - status = "okay"; -}; - -&usbotg2 { - dr_mode = "host"; - disable-over-current; - vbus-supply = <®_5v>; - status = "okay"; -}; - -&usdhc1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usdhc1>; - cd-gpios = <&gpio1 19 GPIO_ACTIVE_LOW>; - keep-power-in-suspend; - wakeup-source; - vmmc-supply = <®_3v3>; - voltage-ranges = <3300 3300>; - no-1-8-v; - status = "okay"; -}; - -&usdhc2 { - pinctrl-names = "default", "state_100mhz", "state_200mhz"; - pinctrl-0 = <&pinctrl_usdhc2>; - pinctrl-1 = <&pinctrl_usdhc2_100mhz>; - pinctrl-2 = <&pinctrl_usdhc2_200mhz>; - non-removable; - keep-power-in-suspend; - wakeup-source; - vmmc-supply = <®_3v3>; - voltage-ranges = <3300 3300>; - no-1-8-v; - status = "okay"; -}; - -&iomuxc { - pinctrl-0 = <&pinctrl_reset_out &pinctrl_gpio>; - - pinctrl_adc1: adc1grp { - fsl,pins = < - MX6UL_PAD_GPIO1_IO02__GPIO1_IO02 0xb0 - MX6UL_PAD_GPIO1_IO03__GPIO1_IO03 0xb0 - MX6UL_PAD_GPIO1_IO08__GPIO1_IO08 0xb0 - >; - }; - - pinctrl_ecspi1: ecspi1grp { - fsl,pins = < - MX6UL_PAD_CSI_DATA07__ECSPI1_MISO 0x100b1 - MX6UL_PAD_CSI_DATA06__ECSPI1_MOSI 0x100b1 - MX6UL_PAD_CSI_DATA04__ECSPI1_SCLK 0x100b1 - MX6UL_PAD_CSI_DATA05__GPIO4_IO26 0x100b1 /* ECSPI1-CS1 */ - >; - }; - - pinctrl_enet2: enet2grp { - fsl,pins = < - MX6UL_PAD_ENET2_RX_EN__ENET2_RX_EN 0x1b0b0 - MX6UL_PAD_ENET2_RX_ER__ENET2_RX_ER 0x1b0b0 - MX6UL_PAD_ENET2_RX_DATA0__ENET2_RDATA00 0x1b0b0 - MX6UL_PAD_ENET2_RX_DATA1__ENET2_RDATA01 0x1b0b0 - MX6UL_PAD_ENET2_TX_EN__ENET2_TX_EN 0x1b0b0 - MX6UL_PAD_ENET2_TX_DATA0__ENET2_TDATA00 0x1b0b0 - MX6UL_PAD_ENET2_TX_DATA1__ENET2_TDATA01 0x1b0b0 - MX6UL_PAD_ENET2_TX_CLK__ENET2_REF_CLK2 0x4001b009 - >; - }; - - pinctrl_enet2_mdio: enet2mdiogrp { - fsl,pins = < - MX6UL_PAD_GPIO1_IO07__ENET2_MDC 0x1b0b0 - MX6UL_PAD_GPIO1_IO06__ENET2_MDIO 0x1b0b0 - >; - }; - - pinctrl_flexcan2: flexcan2grp{ - fsl,pins = < - MX6UL_PAD_UART2_RTS_B__FLEXCAN2_RX 0x1b020 - MX6UL_PAD_UART2_CTS_B__FLEXCAN2_TX 0x1b020 - >; - }; - - pinctrl_gpio: gpiogrp { - fsl,pins = < - MX6UL_PAD_SNVS_TAMPER5__GPIO5_IO05 0x1b0b0 /* DOUT1 */ - MX6UL_PAD_SNVS_TAMPER4__GPIO5_IO04 0x1b0b0 /* DIN1 */ - MX6UL_PAD_SNVS_TAMPER1__GPIO5_IO01 0x1b0b0 /* DOUT2 */ - MX6UL_PAD_SNVS_TAMPER0__GPIO5_IO00 0x1b0b0 /* DIN2 */ - >; - }; - - pinctrl_gpio_leds: gpioledsgrp { - fsl,pins = < - MX6UL_PAD_UART5_TX_DATA__GPIO1_IO30 0x1b0b0 /* LED H14 */ - MX6UL_PAD_SNVS_TAMPER3__GPIO5_IO03 0x1b0b0 /* LED H15 */ - MX6UL_PAD_SNVS_TAMPER2__GPIO5_IO02 0x1b0b0 /* LED H16 */ - >; - }; - - pinctrl_i2c1: i2c1grp { - fsl,pins = < - MX6UL_PAD_CSI_PIXCLK__I2C1_SCL 0x4001b8b0 - MX6UL_PAD_CSI_MCLK__I2C1_SDA 0x4001b8b0 - >; - }; - - pinctrl_i2c4: i2c4grp { - fsl,pins = < - MX6UL_PAD_UART2_TX_DATA__I2C4_SCL 0x4001f8b0 - MX6UL_PAD_UART2_RX_DATA__I2C4_SDA 0x4001f8b0 - >; - }; - - pinctrl_pwm8: pwm8grp { - fsl,pins = < - MX6UL_PAD_CSI_HSYNC__PWM8_OUT 0x110b0 - >; - }; - - pinctrl_uart1: uart1grp { - fsl,pins = < - MX6UL_PAD_UART1_TX_DATA__UART1_DCE_TX 0x1b0b1 - MX6UL_PAD_UART1_RX_DATA__UART1_DCE_RX 0x1b0b1 - >; - }; - - pinctrl_uart2: uart2grp { - fsl,pins = < - MX6UL_PAD_NAND_DATA04__UART2_DCE_TX 0x1b0b1 - MX6UL_PAD_NAND_DATA05__UART2_DCE_RX 0x1b0b1 - MX6UL_PAD_NAND_DATA06__UART2_DCE_CTS 0x1b0b1 - /* - * mux unused RTS to make sure it doesn't cause - * any interrupts when it is undefined - */ - MX6UL_PAD_NAND_DATA07__UART2_DCE_RTS 0x1b0b1 - >; - }; - - pinctrl_uart3: uart3grp { - fsl,pins = < - MX6UL_PAD_UART3_TX_DATA__UART3_DCE_TX 0x1b0b1 - MX6UL_PAD_UART3_RX_DATA__UART3_DCE_RX 0x1b0b1 - MX6UL_PAD_UART3_CTS_B__UART3_DCE_CTS 0x1b0b1 - MX6UL_PAD_UART3_RTS_B__UART3_DCE_RTS 0x1b0b1 - >; - }; - - pinctrl_uart4: uart4grp { - fsl,pins = < - MX6UL_PAD_UART4_TX_DATA__UART4_DCE_TX 0x1b0b1 - MX6UL_PAD_UART4_RX_DATA__UART4_DCE_RX 0x1b0b1 - >; - }; - - pinctrl_usbotg1: usbotg1 { - fsl,pins = < - MX6UL_PAD_GPIO1_IO04__GPIO1_IO04 0x1b0b0 - >; - }; - - pinctrl_usdhc1: usdhc1grp { - fsl,pins = < - MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x17059 - MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x10059 - MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x17059 - MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x17059 - MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x17059 - MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x17059 - MX6UL_PAD_UART1_RTS_B__GPIO1_IO19 0x100b1 /* SD1_CD */ - >; - }; - - pinctrl_usdhc2: usdhc2grp { - fsl,pins = < - MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x10059 - MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x17059 - MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x17059 - MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x17059 - MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x17059 - MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x17059 - >; - }; - - pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp { - fsl,pins = < - MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x100b9 - MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x170b9 - MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x170b9 - MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x170b9 - MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x170b9 - MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x170b9 - >; - }; - - pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp { - fsl,pins = < - MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x100f9 - MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x170f9 - MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x170f9 - MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x170f9 - MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x170f9 - MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x170f9 - >; - }; -}; diff --git a/arch/arm/dts/imx6ul-kontron-bl.dts b/arch/arm/dts/imx6ul-kontron-bl.dts deleted file mode 100644 index dadf6d3d5f5..00000000000 --- a/arch/arm/dts/imx6ul-kontron-bl.dts +++ /dev/null @@ -1,16 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Copyright (C) 2017 exceet electronics GmbH - * Copyright (C) 2018 Kontron Electronics GmbH - * Copyright (c) 2019 Krzysztof Kozlowski - */ - -/dts-v1/; - -#include "imx6ul-kontron-sl.dtsi" -#include "imx6ul-kontron-bl-common.dtsi" - -/ { - model = "Kontron BL i.MX6UL (N631X S)"; - compatible = "kontron,bl-imx6ul", "kontron,sl-imx6ul", "fsl,imx6ul"; -}; diff --git a/arch/arm/dts/imx6ul-kontron-sl-common.dtsi b/arch/arm/dts/imx6ul-kontron-sl-common.dtsi deleted file mode 100644 index dcf88f61034..00000000000 --- a/arch/arm/dts/imx6ul-kontron-sl-common.dtsi +++ /dev/null @@ -1,137 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Copyright (C) 2017 exceet electronics GmbH - * Copyright (C) 2018 Kontron Electronics GmbH - * Copyright (c) 2019 Krzysztof Kozlowski - */ - -#include - -/ { - chosen { - stdout-path = &uart4; - }; - - memory@80000000 { - reg = <0x80000000 0x10000000>; - device_type = "memory"; - }; -}; - -&ecspi2 { - cs-gpios = <&gpio4 22 GPIO_ACTIVE_LOW>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ecspi2>; - status = "okay"; - - flash@0 { - compatible = "mxicy,mx25v8035f", "jedec,spi-nor"; - spi-max-frequency = <50000000>; - reg = <0>; - }; -}; - -&fec1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_enet1 &pinctrl_enet1_mdio>; - phy-mode = "rmii"; - phy-handle = <ðphy1>; - status = "okay"; - - mdio { - #address-cells = <1>; - #size-cells = <0>; - - ethphy1: ethernet-phy@1 { - reg = <1>; - micrel,led-mode = <0>; - clocks = <&clks IMX6UL_CLK_ENET_REF>; - clock-names = "rmii-ref"; - }; - }; -}; - -&fec2 { - phy-mode = "rmii"; - status = "disabled"; -}; - -&qspi { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_qspi>; - status = "okay"; - - spi-flash@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "spi-nand"; - spi-max-frequency = <104000000>; - spi-tx-bus-width = <4>; - spi-rx-bus-width = <4>; - reg = <0>; - }; -}; - -&wdog1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_wdog>; - fsl,ext-reset-output; - status = "okay"; -}; - -&iomuxc { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_reset_out>; - - pinctrl_ecspi2: ecspi2grp { - fsl,pins = < - MX6UL_PAD_CSI_DATA03__ECSPI2_MISO 0x100b1 - MX6UL_PAD_CSI_DATA02__ECSPI2_MOSI 0x100b1 - MX6UL_PAD_CSI_DATA00__ECSPI2_SCLK 0x100b1 - MX6UL_PAD_CSI_DATA01__GPIO4_IO22 0x100b1 - >; - }; - - pinctrl_enet1: enet1grp { - fsl,pins = < - MX6UL_PAD_ENET1_RX_EN__ENET1_RX_EN 0x1b0b0 - MX6UL_PAD_ENET1_RX_ER__ENET1_RX_ER 0x1b0b0 - MX6UL_PAD_ENET1_RX_DATA0__ENET1_RDATA00 0x1b0b0 - MX6UL_PAD_ENET1_RX_DATA1__ENET1_RDATA01 0x1b0b0 - MX6UL_PAD_ENET1_TX_EN__ENET1_TX_EN 0x1b0b0 - MX6UL_PAD_ENET1_TX_DATA0__ENET1_TDATA00 0x1b0b0 - MX6UL_PAD_ENET1_TX_DATA1__ENET1_TDATA01 0x1b0b0 - MX6UL_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 0x4001b009 - >; - }; - - pinctrl_enet1_mdio: enet1mdiogrp { - fsl,pins = < - MX6UL_PAD_GPIO1_IO07__ENET1_MDC 0x1b0b0 - MX6UL_PAD_GPIO1_IO06__ENET1_MDIO 0x1b0b0 - >; - }; - - pinctrl_qspi: qspigrp { - fsl,pins = < - MX6UL_PAD_NAND_WP_B__QSPI_A_SCLK 0x70a1 - MX6UL_PAD_NAND_READY_B__QSPI_A_DATA00 0x70a1 - MX6UL_PAD_NAND_CE0_B__QSPI_A_DATA01 0x70a1 - MX6UL_PAD_NAND_CE1_B__QSPI_A_DATA02 0x70a1 - MX6UL_PAD_NAND_CLE__QSPI_A_DATA03 0x70a1 - MX6UL_PAD_NAND_DQS__QSPI_A_SS0_B 0x70a1 - >; - }; - - pinctrl_reset_out: rstoutgrp { - fsl,pins = < - MX6UL_PAD_SNVS_TAMPER9__GPIO5_IO09 0x1b0b0 - >; - }; - - pinctrl_wdog: wdoggrp { - fsl,pins = < - MX6UL_PAD_GPIO1_IO09__WDOG1_WDOG_ANY 0x18b0 - >; - }; -}; diff --git a/arch/arm/dts/imx6ul-kontron-sl.dtsi b/arch/arm/dts/imx6ul-kontron-sl.dtsi deleted file mode 100644 index 0580d043e5a..00000000000 --- a/arch/arm/dts/imx6ul-kontron-sl.dtsi +++ /dev/null @@ -1,14 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Copyright (C) 2017 exceet electronics GmbH - * Copyright (C) 2018 Kontron Electronics GmbH - * Copyright (c) 2019 Krzysztof Kozlowski - */ - -#include "imx6ul.dtsi" -#include "imx6ul-kontron-sl-common.dtsi" - -/ { - model = "Kontron SL i.MX6UL (N631X SOM)"; - compatible = "kontron,sl-imx6ul", "fsl,imx6ul"; -}; diff --git a/arch/arm/dts/imx6ull-kontron-bl.dts b/arch/arm/dts/imx6ull-kontron-bl.dts deleted file mode 100644 index fa016465cdb..00000000000 --- a/arch/arm/dts/imx6ull-kontron-bl.dts +++ /dev/null @@ -1,15 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Copyright (C) 2017 exceet electronics GmbH - * Copyright (C) 2019 Kontron Electronics GmbH - */ - -/dts-v1/; - -#include "imx6ull-kontron-sl.dtsi" -#include "imx6ul-kontron-bl-common.dtsi" - -/ { - model = "Kontron BL i.MX6ULL (N641X S)"; - compatible = "kontron,bl-imx6ull", "kontron,sl-imx6ull", "fsl,imx6ull"; -}; diff --git a/arch/arm/dts/imx6ull-kontron-sl.dtsi b/arch/arm/dts/imx6ull-kontron-sl.dtsi deleted file mode 100644 index 93f10eb3494..00000000000 --- a/arch/arm/dts/imx6ull-kontron-sl.dtsi +++ /dev/null @@ -1,13 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Copyright (C) 2017 exceet electronics GmbH - * Copyright (C) 2018 Kontron Electronics GmbH - */ - -#include "imx6ull.dtsi" -#include "imx6ul-kontron-sl-common.dtsi" - -/ { - model = "Kontron SL i.MX6ULL (N641X SOM)"; - compatible = "kontron,sl-imx6ull", "fsl,imx6ull"; -}; diff --git a/configs/kontron-sl-mx6ul_defconfig b/configs/kontron-sl-mx6ul_defconfig index 052d7a76610..8e35d894dae 100644 --- a/configs/kontron-sl-mx6ul_defconfig +++ b/configs/kontron-sl-mx6ul_defconfig @@ -13,7 +13,7 @@ CONFIG_ENV_SECT_SIZE=0x4000 CONFIG_MX6UL=y CONFIG_TARGET_KONTRON_MX6UL=y CONFIG_DM_GPIO=y -CONFIG_DEFAULT_DEVICE_TREE="imx6ul-kontron-bl" +CONFIG_DEFAULT_DEVICE_TREE="nxp/imx/imx6ul-kontron-bl" CONFIG_SPL_MMC=y CONFIG_SPL_SERIAL=y CONFIG_BOOTCOUNT_BOOTLIMIT=3 @@ -62,7 +62,8 @@ CONFIG_MTDPARTS_DEFAULT="mtdparts=spi1.0:960k(u-boot),32k(env),32k(env_redundant CONFIG_CMD_UBI=y CONFIG_OF_CONTROL=y CONFIG_SPL_OF_CONTROL=y -CONFIG_OF_LIST="imx6ul-kontron-bl imx6ull-kontron-bl" +CONFIG_OF_UPSTREAM=y +CONFIG_OF_LIST="nxp/imx/imx6ul-kontron-bl nxp/imx/imx6ull-kontron-bl" CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_NOWHERE=y CONFIG_ENV_IS_IN_MMC=y -- cgit v1.2.3 From d95c4bebf40cddff5b284abfb591eb47f84ebb12 Mon Sep 17 00:00:00 2001 From: Ilias Apalodimas Date: Tue, 12 Aug 2025 09:08:06 +0300 Subject: tools: imx8image: Make imx8image_check_params() static We are trying to enable -Wmissing-prototypes and this functiion is only used locally. Mark it as static. Signed-off-by: Ilias Apalodimas Acked-by: Peng Fan --- tools/imx8image.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/tools/imx8image.c b/tools/imx8image.c index 5a76643c06e..3cea536b8e8 100644 --- a/tools/imx8image.c +++ b/tools/imx8image.c @@ -23,7 +23,7 @@ static uint8_t cntr_version; static uint32_t custom_partition; static uint32_t scfw_flags; -int imx8image_check_params(struct image_tool_params *params) +static int imx8image_check_params(struct image_tool_params *params) { return 0; } -- cgit v1.2.3 From 8c690095b84741717598d6bbc39116c8028adbd9 Mon Sep 17 00:00:00 2001 From: Primoz Fiser Date: Thu, 21 Aug 2025 08:46:14 +0200 Subject: arm: dts: imx93-phyboard-segin-u-boot: Clean-up already upstream nodes Clean-up "imx93-phyboard-segin-u-boot.dtsi" internal device-tree from nodes already part of the upstream device-tree since commit 79f3e77133bd ("Subtree merge tag 'v6.16-dts' of dts repo [1] into dts/upstream"). No functional change is made with this commit. Signed-off-by: Primoz Fiser --- arch/arm/dts/imx93-phyboard-segin-u-boot.dtsi | 219 ++++---------------------- 1 file changed, 35 insertions(+), 184 deletions(-) diff --git a/arch/arm/dts/imx93-phyboard-segin-u-boot.dtsi b/arch/arm/dts/imx93-phyboard-segin-u-boot.dtsi index 0c3ca2961c9..0c8d0ba9693 100644 --- a/arch/arm/dts/imx93-phyboard-segin-u-boot.dtsi +++ b/arch/arm/dts/imx93-phyboard-segin-u-boot.dtsi @@ -69,6 +69,16 @@ bootph-some-ram; }; +&pinctrl_lpi2c3 { + bootph-pre-ram; + bootph-some-ram; +}; + +&pinctrl_pmic { + bootph-pre-ram; + bootph-some-ram; +}; + &pinctrl_reg_usdhc2_vmmc { bootph-pre-ram; }; @@ -83,6 +93,16 @@ bootph-some-ram; }; +&pinctrl_usdhc1_100mhz { + bootph-pre-ram; + bootph-some-ram; +}; + +&pinctrl_usdhc1_200mhz { + bootph-pre-ram; + bootph-some-ram; +}; + &pinctrl_usdhc2_cd { bootph-pre-ram; bootph-some-ram; @@ -128,31 +148,9 @@ bootph-some-ram; }; -/* - * Remove once USB support is added to imx93-phyboard-segin.dts upstream. - */ -&usbotg1 { - disable-over-current; - dr_mode = "otg"; - status = "okay"; -}; - -&usbotg2 { - disable-over-current; - dr_mode = "host"; - status = "okay"; -}; - &usdhc1 { bootph-pre-ram; bootph-some-ram; - /* - * Remove pinctrl assignments once they are added to imx93-phycore-som.dtsi - */ - pinctrl-names = "default", "state_100mhz", "state_200mhz"; - pinctrl-0 = <&pinctrl_usdhc1>; - pinctrl-1 = <&pinctrl_usdhc1_100mhz>; - pinctrl-2 = <&pinctrl_usdhc1_200mhz>; }; &usdhc2 { @@ -174,6 +172,21 @@ &lpi2c3 { bootph-pre-ram; bootph-some-ram; + + pmic@25 { + bootph-pre-ram; + bootph-some-ram; + + regulators { + bootph-pre-ram; + bootph-some-ram; + }; + }; + + eeprom@50 { + bootph-pre-ram; + bootph-some-ram; + }; }; &s4muap { @@ -209,165 +222,3 @@ bootph-all; bootph-pre-ram; }; - -/* - * The two nodes below won't be needed once nxp,pca9451a - * support is added to the Linux kernel. - */ -&iomuxc { - pinctrl_lpi2c3: lpi2c3grp { - bootph-pre-ram; - fsl,pins = < - MX93_PAD_GPIO_IO28__LPI2C3_SDA 0x40000b9e - MX93_PAD_GPIO_IO29__LPI2C3_SCL 0x40000b9e - >; - }; - - pinctrl_pmic: pmicgrp { - bootph-pre-ram; - fsl,pins = < - MX93_PAD_ENET2_RD3__GPIO4_IO27 0x31e - >; - }; - - /* - * Remove pinctrl_usdhc1_100mhz and pinctrl_usdhc1_200mhz once they - * are added to imx93-phycore-som.dtsi - */ - /* need to config the SION for data and cmd pad, refer to ERR052021 */ - pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp { - bootph-pre-ram; - bootph-some-ram; - fsl,pins = < - MX93_PAD_SD1_CLK__USDHC1_CLK 0x17be - MX93_PAD_SD1_CMD__USDHC1_CMD 0x4000139e - MX93_PAD_SD1_DATA0__USDHC1_DATA0 0x4000138e - MX93_PAD_SD1_DATA1__USDHC1_DATA1 0x4000139e - MX93_PAD_SD1_DATA2__USDHC1_DATA2 0x400013be - MX93_PAD_SD1_DATA3__USDHC1_DATA3 0x4000139e - MX93_PAD_SD1_DATA4__USDHC1_DATA4 0x4000139e - MX93_PAD_SD1_DATA5__USDHC1_DATA5 0x4000139e - MX93_PAD_SD1_DATA6__USDHC1_DATA6 0x4000139e - MX93_PAD_SD1_DATA7__USDHC1_DATA7 0x4000139e - MX93_PAD_SD1_STROBE__USDHC1_STROBE 0x179e - >; - }; - - /* need to config the SION for data and cmd pad, refer to ERR052021 */ - pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp { - bootph-pre-ram; - bootph-some-ram; - fsl,pins = < - MX93_PAD_SD1_CLK__USDHC1_CLK 0x17be - MX93_PAD_SD1_CMD__USDHC1_CMD 0x4000139e - MX93_PAD_SD1_DATA0__USDHC1_DATA0 0x4000139e - MX93_PAD_SD1_DATA1__USDHC1_DATA1 0x400013be - MX93_PAD_SD1_DATA2__USDHC1_DATA2 0x400013be - MX93_PAD_SD1_DATA3__USDHC1_DATA3 0x400013be - MX93_PAD_SD1_DATA4__USDHC1_DATA4 0x400013be - MX93_PAD_SD1_DATA5__USDHC1_DATA5 0x400013be - MX93_PAD_SD1_DATA6__USDHC1_DATA6 0x400013be - MX93_PAD_SD1_DATA7__USDHC1_DATA7 0x400013be - MX93_PAD_SD1_STROBE__USDHC1_STROBE 0x179e - >; - }; -}; - -&lpi2c3 { - bootph-pre-ram; - bootph-some-ram; - clock-frequency = <400000>; - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&pinctrl_lpi2c3>; - pinctrl-1 = <&pinctrl_lpi2c3>; - status = "okay"; - - pmic@25 { - bootph-pre-ram; - bootph-some-ram; - compatible = "nxp,pca9451a"; - reg = <0x25>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pmic>; - interrupt-parent = <&gpio4>; - interrupts = <27 IRQ_TYPE_LEVEL_LOW>; - - regulators { - bootph-pre-ram; - bootph-some-ram; - buck1: BUCK1 { - regulator-name = "VDD_SOC"; - regulator-min-microvolt = <610000>; - regulator-max-microvolt = <950000>; - regulator-boot-on; - regulator-always-on; - regulator-ramp-delay = <3125>; - }; - - buck2: BUCK2 { - regulator-name = "VDDQ_0V6"; - regulator-min-microvolt = <600000>; - regulator-max-microvolt = <600000>; - regulator-boot-on; - regulator-always-on; - }; - - buck4: BUCK4 { - regulator-name = "VDD_3V3_BUCK"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - regulator-always-on; - }; - - buck5: BUCK5 { - regulator-name = "VDD_1V8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-boot-on; - regulator-always-on; - }; - - buck6: BUCK6 { - regulator-name = "VDD_1V1"; - regulator-min-microvolt = <1100000>; - regulator-max-microvolt = <1100000>; - regulator-boot-on; - regulator-always-on; - }; - - ldo1: LDO1 { - regulator-name = "PMIC_SNVS_1V8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-boot-on; - regulator-always-on; - }; - - ldo4: LDO4 { - regulator-name = "VDD_0V8"; - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <800000>; - regulator-boot-on; - regulator-always-on; - }; - - ldo5: LDO5 { - regulator-name = "NVCC_SD2"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - regulator-always-on; - }; - }; - }; - - eeprom@50 { - bootph-pre-ram; - bootph-some-ram; - compatible = "atmel,24c32"; - reg = <0x50>; - pagesize = <32>; - vcc-supply = <&buck4>; - }; -}; -- cgit v1.2.3 From d271a01dbeba746bb35c4a068afc3ccfc5fc91d5 Mon Sep 17 00:00:00 2001 From: Primoz Fiser Date: Thu, 28 Aug 2025 10:20:07 +0200 Subject: configs: imx93-phycore_defconfig: Disable CONFIG_AHAB_BOOT By default, lets disable configuration option CONFIG_AHAB_BOOT=y on the phyCORE-i.MX93 based boards. This option is only used in the secureboot context which is not provided by default anyway. Lets remove it from the defconfig to not give false impressions it is supported out of the box for this board. On the other hand, in the context of PHYTEC secureboot, this option is selected by the distro which enables CONFIG_AHAB_BOOT among other secure boot related options and tweaks needed to properly support it. Signed-off-by: Primoz Fiser Reviewed-by: Martin Schwan --- configs/imx93-phycore_defconfig | 1 - 1 file changed, 1 deletion(-) diff --git a/configs/imx93-phycore_defconfig b/configs/imx93-phycore_defconfig index af149128ed4..53cd28dfcba 100644 --- a/configs/imx93-phycore_defconfig +++ b/configs/imx93-phycore_defconfig @@ -13,7 +13,6 @@ CONFIG_ENV_OFFSET=0x700000 CONFIG_IMX_CONFIG="arch/arm/mach-imx/imx9/imximage.cfg" CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="freescale/imx93-phyboard-segin" -CONFIG_AHAB_BOOT=y CONFIG_TARGET_PHYCORE_IMX93=y CONFIG_OF_LIBFDT_OVERLAY=y CONFIG_SYS_MONITOR_LEN=524288 -- cgit v1.2.3 From b4ab315a0a5c32607d0d12734d0d3cb03d813e8b Mon Sep 17 00:00:00 2001 From: Primoz Fiser Date: Thu, 28 Aug 2025 10:20:08 +0200 Subject: board: phytec: phycore-imx93: Use CONFIG_PHYTEC_EEPROM_BUS Switch to use CONFIG_PHYTEC_EEPROM_BUS instead of the hard coded value of 2 for the EEPROM I2C bus for both SPL and U-Boot proper. Possible since commit 88a1816a9b4e ("board: phytec: common: Add PHYTEC_EEPROM_BUS to Kconfig"). Signed-off-by: Primoz Fiser Reviewed-by: Wadim Egorov --- board/phytec/phycore_imx93/phycore-imx93.c | 2 +- board/phytec/phycore_imx93/spl.c | 2 +- configs/imx93-phycore_defconfig | 1 + 3 files changed, 3 insertions(+), 2 deletions(-) diff --git a/board/phytec/phycore_imx93/phycore-imx93.c b/board/phytec/phycore_imx93/phycore-imx93.c index fab66caf2a1..c6a4e923b07 100644 --- a/board/phytec/phycore_imx93/phycore-imx93.c +++ b/board/phytec/phycore_imx93/phycore-imx93.c @@ -20,7 +20,7 @@ DECLARE_GLOBAL_DATA_PTR; int board_init(void) { - int ret = phytec_eeprom_data_setup(NULL, 2, EEPROM_ADDR); + int ret = phytec_eeprom_data_setup(NULL, CONFIG_PHYTEC_EEPROM_BUS, EEPROM_ADDR); if (ret) printf("%s: EEPROM data init failed\n", __func__); diff --git a/board/phytec/phycore_imx93/spl.c b/board/phytec/phycore_imx93/spl.c index beaa536c600..7feee4bcf6f 100644 --- a/board/phytec/phycore_imx93/spl.c +++ b/board/phytec/phycore_imx93/spl.c @@ -52,7 +52,7 @@ void spl_dram_init(void) int ret; enum phytec_imx93_ddr_eeprom_code ddr_opt = PHYTEC_IMX93_DDR_INVALID; - ret = phytec_eeprom_data_setup(NULL, 2, EEPROM_ADDR); + ret = phytec_eeprom_data_setup(NULL, CONFIG_PHYTEC_EEPROM_BUS, EEPROM_ADDR); if (ret && !IS_ENABLED(CONFIG_PHYCORE_IMX93_RAM_TYPE_FIX)) goto out; diff --git a/configs/imx93-phycore_defconfig b/configs/imx93-phycore_defconfig index 53cd28dfcba..0acdfd2bf53 100644 --- a/configs/imx93-phycore_defconfig +++ b/configs/imx93-phycore_defconfig @@ -7,6 +7,7 @@ CONFIG_SPL_LIBCOMMON_SUPPORT=y CONFIG_SPL_LIBGENERIC_SUPPORT=y CONFIG_NR_DRAM_BANKS=2 CONFIG_PHYTEC_SOM_DETECTION=y +CONFIG_PHYTEC_EEPROM_BUS=2 CONFIG_ENV_SOURCE_FILE="phycore_imx93" CONFIG_ENV_SIZE=0x10000 CONFIG_ENV_OFFSET=0x700000 -- cgit v1.2.3 From 5d75b4f8767d4e27ea4074f2b06bec2d6f78bfb4 Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Fri, 29 Aug 2025 16:28:15 -0300 Subject: imx8m[m,n,p]_evk: Add redundant environment support For reliable Over The Air update, it is recommended that redundant environment is used. Add redundant environment support for the i.MX8M EVK boards. While at it, increase the environment size and adjust the offset. Signed-off-by: Fabio Estevam --- configs/imx8mn_ddr4_evk_defconfig | 6 ++++-- configs/imx8mn_evk_defconfig | 6 ++++-- configs/imx8mp_evk_defconfig | 6 ++++-- configs/imx8mq_evk_defconfig | 6 ++++-- 4 files changed, 16 insertions(+), 8 deletions(-) diff --git a/configs/imx8mn_ddr4_evk_defconfig b/configs/imx8mn_ddr4_evk_defconfig index a80ceab56f5..c0c22f99078 100644 --- a/configs/imx8mn_ddr4_evk_defconfig +++ b/configs/imx8mn_ddr4_evk_defconfig @@ -5,8 +5,8 @@ CONFIG_SYS_MALLOC_LEN=0x2000000 CONFIG_SPL_GPIO=y CONFIG_SPL_LIBCOMMON_SUPPORT=y CONFIG_SPL_LIBGENERIC_SUPPORT=y -CONFIG_ENV_SIZE=0x1000 -CONFIG_ENV_OFFSET=0x400000 +CONFIG_ENV_SIZE=0x4000 +CONFIG_ENV_OFFSET=0x200000 CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="freescale/imx8mn-ddr4-evk" CONFIG_TARGET_IMX8MN_DDR4_EVK=y @@ -22,6 +22,7 @@ CONFIG_SPL_BSS_MAX_SIZE=0x2000 CONFIG_SYS_BOOTM_LEN=0x2000000 CONFIG_SYS_LOAD_ADDR=0x42000000 CONFIG_SPL=y +CONFIG_ENV_OFFSET_REDUND=0x204000 CONFIG_SPL_IMX_ROMAPI_LOADADDR=0x48000000 CONFIG_FIT=y CONFIG_FIT_EXTERNAL_OFFSET=0x3000 @@ -64,6 +65,7 @@ CONFIG_OF_CONTROL=y CONFIG_SPL_OF_CONTROL=y CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_MMC=y +CONFIG_ENV_REDUNDANT=y CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_ENV_MMC_DEVICE_INDEX=1 CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y diff --git a/configs/imx8mn_evk_defconfig b/configs/imx8mn_evk_defconfig index 47a30946818..0d6d31abba3 100644 --- a/configs/imx8mn_evk_defconfig +++ b/configs/imx8mn_evk_defconfig @@ -5,8 +5,8 @@ CONFIG_SYS_MALLOC_LEN=0x2000000 CONFIG_SPL_GPIO=y CONFIG_SPL_LIBCOMMON_SUPPORT=y CONFIG_SPL_LIBGENERIC_SUPPORT=y -CONFIG_ENV_SIZE=0x1000 -CONFIG_ENV_OFFSET=0x400000 +CONFIG_ENV_SIZE=0x4000 +CONFIG_ENV_OFFSET=0x200000 CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="freescale/imx8mn-evk" CONFIG_TARGET_IMX8MN_EVK=y @@ -22,6 +22,7 @@ CONFIG_SPL_BSS_MAX_SIZE=0x2000 CONFIG_SYS_BOOTM_LEN=0x2000000 CONFIG_SYS_LOAD_ADDR=0x42000000 CONFIG_SPL=y +CONFIG_ENV_OFFSET_REDUND=0x204000 CONFIG_SPL_IMX_ROMAPI_LOADADDR=0x48000000 CONFIG_EFI_SET_TIME=y CONFIG_EFI_MM_COMM_TEE=y @@ -82,6 +83,7 @@ CONFIG_OF_CONTROL=y CONFIG_SPL_OF_CONTROL=y CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_MMC=y +CONFIG_ENV_REDUNDANT=y CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y CONFIG_SPL_DM=y diff --git a/configs/imx8mp_evk_defconfig b/configs/imx8mp_evk_defconfig index 0ad1acb94b6..5c3c8a2ca57 100644 --- a/configs/imx8mp_evk_defconfig +++ b/configs/imx8mp_evk_defconfig @@ -5,8 +5,8 @@ CONFIG_SYS_MALLOC_LEN=0x2000000 CONFIG_SPL_GPIO=y CONFIG_SPL_LIBCOMMON_SUPPORT=y CONFIG_SPL_LIBGENERIC_SUPPORT=y -CONFIG_ENV_SIZE=0x1000 -CONFIG_ENV_OFFSET=0x400000 +CONFIG_ENV_SIZE=0x4000 +CONFIG_ENV_OFFSET=0x200000 CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="freescale/imx8mp-evk" CONFIG_TARGET_IMX8MP_EVK=y @@ -22,6 +22,7 @@ CONFIG_SPL_BSS_MAX_SIZE=0x400 CONFIG_SYS_BOOTM_LEN=0x2000000 CONFIG_SYS_LOAD_ADDR=0x40480000 CONFIG_SPL=y +CONFIG_ENV_OFFSET_REDUND=0x20400 CONFIG_SPL_IMX_ROMAPI_LOADADDR=0x48000000 CONFIG_EFI_MM_COMM_TEE=y CONFIG_EFI_VAR_BUF_SIZE=139264 @@ -77,6 +78,7 @@ CONFIG_OF_CONTROL=y CONFIG_SPL_OF_CONTROL=y CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_MMC=y +CONFIG_ENV_REDUNDANT=y CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_ENV_MMC_DEVICE_INDEX=1 CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y diff --git a/configs/imx8mq_evk_defconfig b/configs/imx8mq_evk_defconfig index 21bb04d18a8..10de69689e9 100644 --- a/configs/imx8mq_evk_defconfig +++ b/configs/imx8mq_evk_defconfig @@ -5,8 +5,8 @@ CONFIG_SYS_MALLOC_LEN=0x600000 CONFIG_SPL_GPIO=y CONFIG_SPL_LIBCOMMON_SUPPORT=y CONFIG_SPL_LIBGENERIC_SUPPORT=y -CONFIG_ENV_SIZE=0x1000 -CONFIG_ENV_OFFSET=0x400000 +CONFIG_ENV_SIZE=0x4000 +CONFIG_ENV_OFFSET=0x200000 CONFIG_SYS_I2C_MXC_I2C1=y CONFIG_SYS_I2C_MXC_I2C2=y CONFIG_SYS_I2C_MXC_I2C3=y @@ -25,6 +25,7 @@ CONFIG_SPL_BSS_START_ADDR=0x180000 CONFIG_SPL_BSS_MAX_SIZE=0x2000 CONFIG_SYS_LOAD_ADDR=0x40480000 CONFIG_SPL=y +CONFIG_ENV_OFFSET_REDUND=0x204000 CONFIG_IMX_BOOTAUX=y CONFIG_REMAKE_ELF=y CONFIG_EFI_MM_COMM_TEE=y @@ -75,6 +76,7 @@ CONFIG_CMD_EXT4_WRITE=y CONFIG_OF_CONTROL=y CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_MMC=y +CONFIG_ENV_REDUNDANT=y CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_ENV_MMC_DEVICE_INDEX=1 CONFIG_USE_ETHPRIME=y -- cgit v1.2.3 From 28d6f787b0deb3f66118857297a855233eba18d1 Mon Sep 17 00:00:00 2001 From: Benjamin Hahn Date: Tue, 2 Sep 2025 08:07:32 +0200 Subject: Add imx8mp-libra-fpsc board Add new imx8mp-libra-fpsc board. Bootph tags as well as USB device tree nodes are in u-boot.dtsi for now and will be removed when upstreamed. The Libra i.MX 8M Plus FPSC is a single board computer. It uses an i.MX 8M Plus FPSC [1] System on Module which utilizes the FPSC standard [2]. [1] https://www.phytec.eu/en/produkte/system-on-modules/phycore-imx-8m-plus-fpsc [2] https://www.phytec.eu/en/produkte/system-on-modules/fpsc Signed-off-by: Benjamin Hahn Reviewed-by: Teresa Remmet Tested-by: Teresa Remmet Signed-off-by: Yannic Moog --- arch/arm/dts/imx8mp-libra-rdk-fpsc-u-boot.dtsi | 131 ++ arch/arm/mach-imx/imx8m/Kconfig | 10 + board/phytec/imx8mp-libra-fpsc/Kconfig | 16 + board/phytec/imx8mp-libra-fpsc/MAINTAINERS | 9 + board/phytec/imx8mp-libra-fpsc/Makefile | 10 + board/phytec/imx8mp-libra-fpsc/imx8mp-libra-fpsc.c | 89 + .../phytec/imx8mp-libra-fpsc/imx8mp-libra-fpsc.env | 19 + board/phytec/imx8mp-libra-fpsc/imximage-8mp-sd.cfg | 9 + board/phytec/imx8mp-libra-fpsc/lpddr4_timing.c | 1813 ++++++++++++++++++++ board/phytec/imx8mp-libra-fpsc/spl.c | 132 ++ configs/imx8mp-libra-fpsc_defconfig | 175 ++ doc/board/phytec/imx8mp-libra-fpsc.rst | 83 + doc/board/phytec/index.rst | 1 + include/configs/imx8mp-libra-fpsc.h | 27 + 14 files changed, 2524 insertions(+) create mode 100644 arch/arm/dts/imx8mp-libra-rdk-fpsc-u-boot.dtsi create mode 100644 board/phytec/imx8mp-libra-fpsc/Kconfig create mode 100644 board/phytec/imx8mp-libra-fpsc/MAINTAINERS create mode 100644 board/phytec/imx8mp-libra-fpsc/Makefile create mode 100644 board/phytec/imx8mp-libra-fpsc/imx8mp-libra-fpsc.c create mode 100644 board/phytec/imx8mp-libra-fpsc/imx8mp-libra-fpsc.env create mode 100644 board/phytec/imx8mp-libra-fpsc/imximage-8mp-sd.cfg create mode 100644 board/phytec/imx8mp-libra-fpsc/lpddr4_timing.c create mode 100644 board/phytec/imx8mp-libra-fpsc/spl.c create mode 100644 configs/imx8mp-libra-fpsc_defconfig create mode 100644 doc/board/phytec/imx8mp-libra-fpsc.rst create mode 100644 include/configs/imx8mp-libra-fpsc.h diff --git a/arch/arm/dts/imx8mp-libra-rdk-fpsc-u-boot.dtsi b/arch/arm/dts/imx8mp-libra-rdk-fpsc-u-boot.dtsi new file mode 100644 index 00000000000..1320f1540ed --- /dev/null +++ b/arch/arm/dts/imx8mp-libra-rdk-fpsc-u-boot.dtsi @@ -0,0 +1,131 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Copyright (C) 2025 PHYTEC Messtechnik GmbH + */ + +#include "imx8mp-u-boot.dtsi" + +/ { + wdt-reboot { + compatible = "wdt-reboot"; + wdt = <&wdog1>; + bootph-pre-ram; + }; + + bootstd { + bootph-verify; + compatible = "u-boot,boot-std"; + + filename-prefixes = "/", "/boot/"; + bootdev-order = "mmc2", "mmc1", "ethernet"; + + efi { + compatible = "u-boot,distro-efi"; + }; + + rauc { + compatible = "u-boot,distro-rauc"; + }; + + script { + compatible = "u-boot,script"; + }; + }; +}; + +®_usdhc2_vmmc { + bootph-pre-ram; +}; + +&pinctrl_uart4 { + bootph-pre-ram; +}; + +&pinctrl_usdhc2 { + bootph-pre-ram; +}; + +&pinctrl_usdhc3 { + bootph-pre-ram; +}; + +&pinctrl_wdog { + bootph-pre-ram; +}; + +&gpio1 { + bootph-pre-ram; +}; + +&gpio2 { + bootph-pre-ram; +}; + +&gpio3 { + bootph-pre-ram; +}; + +&gpio4 { + bootph-pre-ram; +}; + +&gpio5 { + bootph-pre-ram; +}; + +&uart4 { + bootph-pre-ram; +}; + +&i2c1 { + bootph-pre-ram; +}; + +&pmic { + bootph-pre-ram; +}; + +/* USB1 Type-C */ +&usb3_phy0 { + status = "okay"; +}; + +&usb3_0 { + fsl,over-current-active-low; + fsl,power-active-low; + status = "okay"; +}; + +&usb_dwc3_0 { + dr_mode = "peripheral"; + status = "okay"; +}; + +/* USB2 4-port USB3.0 HUB */ +&usb3_phy1 { + vbus-supply = <®_vdd_5v0>; + status = "okay"; +}; + +&usb3_1 { + fsl,permanently-attached; + fsl,disable-port-power-control; + status = "okay"; +}; + +&usb_dwc3_1 { + dr_mode = "host"; + status = "okay"; +}; + +&usdhc2 { + bootph-pre-ram; +}; + +&usdhc3 { + bootph-pre-ram; +}; + +&wdog1 { + bootph-pre-ram; +}; diff --git a/arch/arm/mach-imx/imx8m/Kconfig b/arch/arm/mach-imx/imx8m/Kconfig index 74416a78847..e7bc154b805 100644 --- a/arch/arm/mach-imx/imx8m/Kconfig +++ b/arch/arm/mach-imx/imx8m/Kconfig @@ -345,6 +345,15 @@ config TARGET_PHYCORE_IMX8MP select IMX8M_LPDDR4 imply OF_UPSTREAM +config TARGET_IMX8MP_LIBRA_FPSC + bool "PHYTEC Libra i.MX 8M Plus FPSC" + select IMX8MP + select SUPPORT_SPL + select IMX8M_LPDDR4 + imply OF_UPSTREAM + help + Libra i.MX8M Plus FPSC is an SBC based on the NXP i.MX 8M Plus SoC. + config TARGET_IMX8MM_CL_IOT_GATE bool "CompuLab iot-gate-imx8" select IMX8MM @@ -409,6 +418,7 @@ source "board/kontron/sl-mx8mm/Kconfig" source "board/menlo/mx8menlo/Kconfig" source "board/msc/sm2s_imx8mp/Kconfig" source "board/mntre/imx8mq_reform2/Kconfig" +source "board/phytec/imx8mp-libra-fpsc/Kconfig" source "board/phytec/phycore_imx8mm/Kconfig" source "board/phytec/phycore_imx8mp/Kconfig" source "board/polyhex/imx8mp_debix_model_a/Kconfig" diff --git a/board/phytec/imx8mp-libra-fpsc/Kconfig b/board/phytec/imx8mp-libra-fpsc/Kconfig new file mode 100644 index 00000000000..4961611f7b2 --- /dev/null +++ b/board/phytec/imx8mp-libra-fpsc/Kconfig @@ -0,0 +1,16 @@ +if TARGET_IMX8MP_LIBRA_FPSC + +config SYS_BOARD + default "imx8mp-libra-fpsc" + +config SYS_VENDOR + default "phytec" + +config IMX_CONFIG + default "board/phytec/imx8mp-libra-fpsc/imximage-8mp-sd.cfg" + +config SYS_CONFIG_NAME + default "imx8mp-libra-fpsc" + +source "board/phytec/common/Kconfig" +endif diff --git a/board/phytec/imx8mp-libra-fpsc/MAINTAINERS b/board/phytec/imx8mp-libra-fpsc/MAINTAINERS new file mode 100644 index 00000000000..1fd99888a2e --- /dev/null +++ b/board/phytec/imx8mp-libra-fpsc/MAINTAINERS @@ -0,0 +1,9 @@ +Libra-i.MX 8M Plus +M: Teresa Remmet +W: https://www.phytec.eu/en/produkte/system-on-modules/phycore-imx-8m-plus-fpsc/ +S: Maintained +F: arch/arm/dts/imx8mp-libra-rdk-fpsc-u-boot.dtsi +F: board/phytec/imx8mp-libra-fpsc/ +F: configs/imx8mp-libra-fpsc_defconfig +F: include/configs/imx8mp-libra-fpsc.h +F: doc/board/phytec/imx8mp-libra-fpsc.rst diff --git a/board/phytec/imx8mp-libra-fpsc/Makefile b/board/phytec/imx8mp-libra-fpsc/Makefile new file mode 100644 index 00000000000..21b35d9142f --- /dev/null +++ b/board/phytec/imx8mp-libra-fpsc/Makefile @@ -0,0 +1,10 @@ +# SPDX-License-Identifier: GPL-2.0-or-later +# +# Copyright (C) 2025 PHYTEC Messtechnik GmbH + +obj-y += imx8mp-libra-fpsc.o + +ifdef CONFIG_XPL_BUILD +obj-y += spl.o +obj-$(CONFIG_IMX8M_LPDDR4) += lpddr4_timing.o +endif diff --git a/board/phytec/imx8mp-libra-fpsc/imx8mp-libra-fpsc.c b/board/phytec/imx8mp-libra-fpsc/imx8mp-libra-fpsc.c new file mode 100644 index 00000000000..ffa21da1b34 --- /dev/null +++ b/board/phytec/imx8mp-libra-fpsc/imx8mp-libra-fpsc.c @@ -0,0 +1,89 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Copyright (C) 2025 PHYTEC Messtechnik GmbH + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define EEPROM_ADDR 0x51 + +#define TUSB_PORT_POL_CRTL_REG 0xB +#define TUSB_CUSTOM_POL BIT(7) +#define TUSB_P0_POL BIT(0) + +/* + * WORKAROUND for PCM-937-L 1618.0, 1618.1. + * USB HUB TUSB8042A has swapped upstream pin polarity. + * Set i2c registers to inform the hub that the lines + * are swapped. + */ +void tusb8042a_swap_lines(void) +{ + const u8 pol_swap_val = (TUSB_CUSTOM_POL | TUSB_P0_POL); + const int addr = 0x44; + struct udevice *dev = 0; + int ret = i2c_get_chip_for_busnum(2, addr, 1, &dev); + + if (!ret) + dm_i2c_write(dev, TUSB_PORT_POL_CRTL_REG, &pol_swap_val, 1); + else + printf("TUSB8042A: Failed to fixup USB HUB.\n"); +} + +int board_init(void) +{ + tusb8042a_swap_lines(); + + return 0; +} + +int board_mmc_get_env_dev(int devno) +{ + return devno; +} + +int board_late_init(void) +{ + switch (get_boot_device()) { + case SD2_BOOT: + env_set_ulong("mmcdev", 1); + if (!strcmp(env_get("boot_targets"), env_get_default("boot_targets"))) + env_set("boot_targets", "mmc1 mmc2 ethernet"); + break; + case MMC3_BOOT: + env_set_ulong("mmcdev", 2); + break; + case USB_BOOT: + printf("Detect USB boot. Will enter fastboot mode!\n"); + if (!strcmp(env_get("bootcmd"), env_get_default("bootcmd"))) + env_set("bootcmd", "fastboot 0; bootflow scan -lb;"); + break; + default: + break; + } + + return 0; +} + +int board_phys_sdram_size(phys_size_t *size) +{ + if (!size) + return -EINVAL; + + *size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE + PHYS_SDRAM_2_SIZE); + + return 0; +} diff --git a/board/phytec/imx8mp-libra-fpsc/imx8mp-libra-fpsc.env b/board/phytec/imx8mp-libra-fpsc/imx8mp-libra-fpsc.env new file mode 100644 index 00000000000..c744248ab7a --- /dev/null +++ b/board/phytec/imx8mp-libra-fpsc/imx8mp-libra-fpsc.env @@ -0,0 +1,19 @@ +boot_script_dhcp=boot.scr.uimg +console=ttymxc3,CONFIG_BAUDRATE +emmc_dev=2 /* This is needed by built-in uuu flash scripts */ +fdtfile=CONFIG_DEFAULT_FDT_FILE +fdt_addr_r=0x40480000 +fdt_overlay_addr_r=0x404a0000 +fit_fdtconf=conf-imx8mp-libra-rdk-fpsc.dtb +kernel_addr_r=0x40a00000 +kernel_comp_addr_r=0x43a00000 +kernel_comp_size=0x1e00000 +mmcroot=2 +pxefile_addr_r=0x45800000 +ramdisk_addr_r=0x45802000 +scriptaddr=0x47600000 +script_offset_f=0x0 +script_size_f=0x2000 +sd_dev=1 /* This is needed by built-in uuu flash scripts */ +ip_dyn=yes +nfsroot=/srv/nfs diff --git a/board/phytec/imx8mp-libra-fpsc/imximage-8mp-sd.cfg b/board/phytec/imx8mp-libra-fpsc/imximage-8mp-sd.cfg new file mode 100644 index 00000000000..6dedf1724ab --- /dev/null +++ b/board/phytec/imx8mp-libra-fpsc/imximage-8mp-sd.cfg @@ -0,0 +1,9 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2021 NXP + */ + + +ROM_VERSION v2 +BOOT_FROM sd +LOADER u-boot-spl-ddr.bin 0x920000 diff --git a/board/phytec/imx8mp-libra-fpsc/lpddr4_timing.c b/board/phytec/imx8mp-libra-fpsc/lpddr4_timing.c new file mode 100644 index 00000000000..1b501828726 --- /dev/null +++ b/board/phytec/imx8mp-libra-fpsc/lpddr4_timing.c @@ -0,0 +1,1813 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright 2025 NXP + * + * Code generated with DDR Tool v3.5.0_9-1ddf053d. + * DDR PHY FW2020.06 + */ + +#include +#include + +/* Initialize DDRC registers */ +struct dram_cfg_param ddr_ddrc_cfg[] = { + {0x3d400304, 0x1}, + {0x3d400030, 0x1}, + {0x3d400000, 0xa1080020}, + {0x3d400020, 0x1323}, + {0x3d400024, 0x1e84800}, + {0x3d400064, 0x7a0118}, + {0x3d400070, 0x7027f90}, + {0x3d400074, 0x790}, + {0x3d4000d0, 0xc00307a3}, + {0x3d4000d4, 0xc50000}, + {0x3d4000dc, 0xf4003f}, + {0x3d4000e0, 0xe30000}, + {0x3d4000e8, 0x440048}, + {0x3d4000ec, 0x140048}, + {0x3d400100, 0x2028222a}, + {0x3d400104, 0x8083f}, + {0x3d40010c, 0xe0e000}, + {0x3d400110, 0x12040a12}, + {0x3d400114, 0x2050f0f}, + {0x3d400118, 0x1010009}, + {0x3d40011c, 0x502}, + {0x3d400130, 0x20800}, + {0x3d400134, 0xe100002}, + {0x3d400138, 0x120}, + {0x3d400144, 0xc80064}, + {0x3d400180, 0x3e8001e}, + {0x3d400184, 0x3207a12}, + {0x3d400188, 0x0}, + {0x3d400190, 0x4a3820e}, + {0x3d400194, 0x80303}, + {0x3d4001b4, 0x230e}, + {0x3d4001a0, 0xe0400018}, + {0x3d4001a4, 0xdf00e4}, + {0x3d4001a8, 0x80000000}, + {0x3d4001b0, 0x11}, + {0x3d4001c0, 0x7}, + {0x3d4001c4, 0x1}, + {0x3d4000f4, 0x799}, + {0x3d400108, 0x9141d1c}, + {0x3d400200, 0x1f}, + {0x3d400208, 0x0}, + {0x3d40020c, 0x0}, + {0x3d400210, 0x1f1f}, + {0x3d400204, 0x80808}, + {0x3d400214, 0x7070707}, + {0x3d400218, 0x7070707}, + {0x3d40021c, 0xf0f}, + {0x3d400250, 0x1705}, + {0x3d400254, 0x2c}, + {0x3d40025c, 0x4000030}, + {0x3d400264, 0x900093e7}, + {0x3d40026c, 0x2005574}, + {0x3d400400, 0x111}, + {0x3d400404, 0x72ff}, + {0x3d400408, 0x72ff}, + {0x3d400494, 0x2100e07}, + {0x3d400498, 0x620096}, + {0x3d40049c, 0x1100e07}, + {0x3d4004a0, 0xc8012c}, + {0x3d400028, 0x0}, +}; + +/* PHY Initialize Configuration */ +struct dram_cfg_param ddr_ddrphy_cfg[] = { + {0x100a0, 0x0}, + {0x100a1, 0x1}, + {0x100a2, 0x2}, + {0x100a3, 0x3}, + {0x100a4, 0x4}, + {0x100a5, 0x5}, + {0x100a6, 0x6}, + {0x100a7, 0x7}, + {0x110a0, 0x0}, + {0x110a1, 0x1}, + {0x110a2, 0x3}, + {0x110a3, 0x4}, + {0x110a4, 0x5}, + {0x110a5, 0x2}, + {0x110a6, 0x7}, + {0x110a7, 0x6}, + {0x120a0, 0x0}, + {0x120a1, 0x1}, + {0x120a2, 0x3}, + {0x120a3, 0x2}, + {0x120a4, 0x5}, + {0x120a5, 0x4}, + {0x120a6, 0x7}, + {0x120a7, 0x6}, + {0x130a0, 0x0}, + {0x130a1, 0x1}, + {0x130a2, 0x2}, + {0x130a3, 0x3}, + {0x130a4, 0x4}, + {0x130a5, 0x5}, + {0x130a6, 0x6}, + {0x130a7, 0x7}, + {0x1005f, 0x1ff}, + {0x1015f, 0x1ff}, + {0x1105f, 0x1ff}, + {0x1115f, 0x1ff}, + {0x1205f, 0x1ff}, + {0x1215f, 0x1ff}, + {0x1305f, 0x1ff}, + {0x1315f, 0x1ff}, + {0x55, 0x1ff}, + {0x1055, 0x1ff}, + {0x2055, 0x1ff}, + {0x3055, 0x1ff}, + {0x4055, 0x1ff}, + {0x5055, 0x1ff}, + {0x6055, 0x1ff}, + {0x7055, 0x1ff}, + {0x8055, 0x1ff}, + {0x9055, 0x1ff}, + {0x200c5, 0x18}, + {0x2002e, 0x2}, + {0x90204, 0x0}, + {0x20024, 0x1e3}, + {0x2003a, 0x2}, + {0x2007d, 0x212}, + {0x2007c, 0x61}, + {0x20056, 0x3}, + {0x1004d, 0x600}, + {0x1014d, 0x600}, + {0x1104d, 0x600}, + {0x1114d, 0x600}, + {0x1204d, 0x600}, + {0x1214d, 0x600}, + {0x1304d, 0x600}, + {0x1314d, 0x600}, + {0x10049, 0x618}, + {0x10149, 0x618}, + {0x11049, 0x618}, + {0x11149, 0x618}, + {0x12049, 0x618}, + {0x12149, 0x618}, + {0x13049, 0x618}, + {0x13149, 0x618}, + {0x43, 0x21}, + {0x1043, 0x21}, + {0x2043, 0x21}, + {0x3043, 0x21}, + {0x4043, 0x21}, + {0x5043, 0x21}, + {0x6043, 0x21}, + {0x7043, 0x21}, + {0x8043, 0x21}, + {0x9043, 0x21}, + {0x20018, 0x3}, + {0x20075, 0x4}, + {0x20050, 0x0}, + {0x20008, 0x3e8}, + {0x20088, 0x9}, + {0x200b2, 0xdc}, + {0x10043, 0x5a1}, + {0x10143, 0x5a1}, + {0x11043, 0x5a1}, + {0x11143, 0x5a1}, + {0x12043, 0x5a1}, + {0x12143, 0x5a1}, + {0x13043, 0x5a1}, + {0x13143, 0x5a1}, + {0x200fa, 0x1}, + {0x20019, 0x1}, + {0x200f0, 0x0}, + {0x200f1, 0x0}, + {0x200f2, 0x4444}, + {0x200f3, 0x8888}, + {0x200f4, 0x5555}, + {0x200f5, 0x0}, + {0x200f6, 0x0}, + {0x200f7, 0xf000}, + {0x20025, 0x0}, + {0x2002d, 0x1}, + {0x2002c, 0x0}, +}; + +/* PHY trained csr */ +struct dram_cfg_param ddr_ddrphy_trained_csr[] = { + {0x1005f, 0x0}, + {0x1015f, 0x0}, + {0x1105f, 0x0}, + {0x1115f, 0x0}, + {0x1205f, 0x0}, + {0x1215f, 0x0}, + {0x1305f, 0x0}, + {0x1315f, 0x0}, + {0x55, 0x0}, + {0x1055, 0x0}, + {0x2055, 0x0}, + {0x3055, 0x0}, + {0x4055, 0x0}, + {0x5055, 0x0}, + {0x6055, 0x0}, + {0x7055, 0x0}, + {0x8055, 0x0}, + {0x9055, 0x0}, + {0x200c5, 0x0}, + {0x2002e, 0x0}, + {0x90204, 0x0}, + {0x20024, 0x0}, + {0x2003a, 0x0}, + {0x2007d, 0x0}, + {0x2007c, 0x0}, + {0x20056, 0x0}, + {0x1004d, 0x0}, + {0x1014d, 0x0}, + {0x1104d, 0x0}, + {0x1114d, 0x0}, + {0x1204d, 0x0}, + {0x1214d, 0x0}, + {0x1304d, 0x0}, + {0x1314d, 0x0}, + {0x10049, 0x0}, + {0x10149, 0x0}, + {0x11049, 0x0}, + {0x11149, 0x0}, + {0x12049, 0x0}, + {0x12149, 0x0}, + {0x13049, 0x0}, + {0x13149, 0x0}, + {0x43, 0x0}, + {0x1043, 0x0}, + {0x2043, 0x0}, + {0x3043, 0x0}, + {0x4043, 0x0}, + {0x5043, 0x0}, + {0x6043, 0x0}, + {0x7043, 0x0}, + {0x8043, 0x0}, + {0x9043, 0x0}, + {0x20018, 0x0}, + {0x20075, 0x0}, + {0x20050, 0x0}, + {0x20008, 0x0}, + {0x20088, 0x0}, + {0x200b2, 0x0}, + {0x10043, 0x0}, + {0x10143, 0x0}, + {0x11043, 0x0}, + {0x11143, 0x0}, + {0x12043, 0x0}, + {0x12143, 0x0}, + {0x13043, 0x0}, + {0x13143, 0x0}, + {0x200fa, 0x0}, + {0x20019, 0x0}, + {0x200f0, 0x0}, + {0x200f1, 0x0}, + {0x200f2, 0x0}, + {0x200f3, 0x0}, + {0x200f4, 0x0}, + {0x200f5, 0x0}, + {0x200f6, 0x0}, + {0x200f7, 0x0}, + {0x20025, 0x0}, + {0x2002d, 0x0}, + {0x2002c, 0x0}, + {0xd0000, 0x0}, + {0x90000, 0x0}, + {0x90001, 0x0}, + {0x90002, 0x0}, + {0x90003, 0x0}, + {0x90004, 0x0}, + {0x90005, 0x0}, + {0x90029, 0x0}, + {0x9002a, 0x0}, + {0x9002b, 0x0}, + {0x9002c, 0x0}, + {0x9002d, 0x0}, + {0x9002e, 0x0}, + {0x9002f, 0x0}, + {0x90030, 0x0}, + {0x90031, 0x0}, + {0x90032, 0x0}, + {0x90033, 0x0}, + {0x90034, 0x0}, + {0x90035, 0x0}, + {0x90036, 0x0}, + {0x90037, 0x0}, + {0x90038, 0x0}, + {0x90039, 0x0}, + {0x9003a, 0x0}, + {0x9003b, 0x0}, + {0x9003c, 0x0}, + {0x9003d, 0x0}, + {0x9003e, 0x0}, + {0x9003f, 0x0}, + {0x90040, 0x0}, + {0x90041, 0x0}, + {0x90042, 0x0}, + {0x90043, 0x0}, + {0x90044, 0x0}, + {0x90045, 0x0}, + {0x90046, 0x0}, + {0x90047, 0x0}, + {0x90048, 0x0}, + {0x90049, 0x0}, + {0x9004a, 0x0}, + {0x9004b, 0x0}, + {0x9004c, 0x0}, + {0x9004d, 0x0}, + {0x9004e, 0x0}, + {0x9004f, 0x0}, + {0x90050, 0x0}, + {0x90051, 0x0}, + {0x90052, 0x0}, + {0x90053, 0x0}, + {0x90054, 0x0}, + {0x90055, 0x0}, + {0x90056, 0x0}, + {0x90057, 0x0}, + {0x90058, 0x0}, + {0x90059, 0x0}, + {0x9005a, 0x0}, + {0x9005b, 0x0}, + {0x9005c, 0x0}, + {0x9005d, 0x0}, + {0x9005e, 0x0}, + {0x9005f, 0x0}, + {0x90060, 0x0}, + {0x90061, 0x0}, + {0x90062, 0x0}, + {0x90063, 0x0}, + {0x90064, 0x0}, + {0x90065, 0x0}, + {0x90066, 0x0}, + {0x90067, 0x0}, + {0x90068, 0x0}, + {0x90069, 0x0}, + {0x9006a, 0x0}, + {0x9006b, 0x0}, + {0x9006c, 0x0}, + {0x9006d, 0x0}, + {0x9006e, 0x0}, + {0x9006f, 0x0}, + {0x90070, 0x0}, + {0x90071, 0x0}, + {0x90072, 0x0}, + {0x90073, 0x0}, + {0x90074, 0x0}, + {0x90075, 0x0}, + {0x90076, 0x0}, + {0x90077, 0x0}, + {0x90078, 0x0}, + {0x90079, 0x0}, + {0x9007a, 0x0}, + {0x9007b, 0x0}, + {0x9007c, 0x0}, + {0x9007d, 0x0}, + {0x9007e, 0x0}, + {0x9007f, 0x0}, + {0x90080, 0x0}, + {0x90081, 0x0}, + {0x90082, 0x0}, + {0x90083, 0x0}, + {0x90084, 0x0}, + {0x90085, 0x0}, + {0x90086, 0x0}, + {0x90087, 0x0}, + {0x90088, 0x0}, + {0x90089, 0x0}, + {0x9008a, 0x0}, + {0x9008b, 0x0}, + {0x9008c, 0x0}, + {0x9008d, 0x0}, + {0x9008e, 0x0}, + {0x9008f, 0x0}, + {0x90090, 0x0}, + {0x90091, 0x0}, + {0x90092, 0x0}, + {0x90093, 0x0}, + {0x90094, 0x0}, + {0x90095, 0x0}, + {0x90096, 0x0}, + {0x90097, 0x0}, + {0x90098, 0x0}, + {0x90099, 0x0}, + {0x9009a, 0x0}, + {0x9009b, 0x0}, + {0x9009c, 0x0}, + {0x9009d, 0x0}, + {0x9009e, 0x0}, + {0x9009f, 0x0}, + {0x900a0, 0x0}, + {0x900a1, 0x0}, + {0x900a2, 0x0}, + {0x900a3, 0x0}, + {0x40000, 0x0}, + {0x40020, 0x0}, + {0x40040, 0x0}, + {0x40060, 0x0}, + {0x40001, 0x0}, + {0x40021, 0x0}, + {0x40041, 0x0}, + {0x40061, 0x0}, + {0x40002, 0x0}, + {0x40022, 0x0}, + {0x40042, 0x0}, + {0x40062, 0x0}, + {0x40003, 0x0}, + {0x40023, 0x0}, + {0x40043, 0x0}, + {0x40063, 0x0}, + {0x40004, 0x0}, + {0x40024, 0x0}, + {0x40044, 0x0}, + {0x40064, 0x0}, + {0x40005, 0x0}, + {0x40025, 0x0}, + {0x40045, 0x0}, + {0x40065, 0x0}, + {0x40006, 0x0}, + {0x40026, 0x0}, + {0x40046, 0x0}, + {0x40066, 0x0}, + {0x40007, 0x0}, + {0x40027, 0x0}, + {0x40047, 0x0}, + {0x40067, 0x0}, + {0x40008, 0x0}, + {0x40028, 0x0}, + {0x40048, 0x0}, + {0x40068, 0x0}, + {0x40009, 0x0}, + {0x40029, 0x0}, + {0x40049, 0x0}, + {0x40069, 0x0}, + {0x4000a, 0x0}, + {0x4002a, 0x0}, + {0x4004a, 0x0}, + {0x4006a, 0x0}, + {0x4000b, 0x0}, + {0x4002b, 0x0}, + {0x4004b, 0x0}, + {0x4006b, 0x0}, + {0x4000c, 0x0}, + {0x4002c, 0x0}, + {0x4004c, 0x0}, + {0x4006c, 0x0}, + {0x4000d, 0x0}, + {0x4002d, 0x0}, + {0x4004d, 0x0}, + {0x4006d, 0x0}, + {0x4000e, 0x0}, + {0x4002e, 0x0}, + {0x4004e, 0x0}, + {0x4006e, 0x0}, + {0x4000f, 0x0}, + {0x4002f, 0x0}, + {0x4004f, 0x0}, + {0x4006f, 0x0}, + {0x40010, 0x0}, + {0x40030, 0x0}, + {0x40050, 0x0}, + {0x40070, 0x0}, + {0x40011, 0x0}, + {0x40031, 0x0}, + {0x40051, 0x0}, + {0x40071, 0x0}, + {0x40012, 0x0}, + {0x40032, 0x0}, + {0x40052, 0x0}, + {0x40072, 0x0}, + {0x40013, 0x0}, + {0x40033, 0x0}, + {0x40053, 0x0}, + {0x40073, 0x0}, + {0x40014, 0x0}, + {0x40034, 0x0}, + {0x40054, 0x0}, + {0x40074, 0x0}, + {0x40015, 0x0}, + {0x40035, 0x0}, + {0x40055, 0x0}, + {0x40075, 0x0}, + {0x40016, 0x0}, + {0x40036, 0x0}, + {0x40056, 0x0}, + {0x40076, 0x0}, + {0x40017, 0x0}, + {0x40037, 0x0}, + {0x40057, 0x0}, + {0x40077, 0x0}, + {0x40018, 0x0}, + {0x40038, 0x0}, + {0x40058, 0x0}, + {0x40078, 0x0}, + {0x40019, 0x0}, + {0x40039, 0x0}, + {0x40059, 0x0}, + {0x40079, 0x0}, + {0x4001a, 0x0}, + {0x4003a, 0x0}, + {0x4005a, 0x0}, + {0x4007a, 0x0}, + {0x900a4, 0x0}, + {0x900a5, 0x0}, + {0x900a6, 0x0}, + {0x900a7, 0x0}, + {0x900a8, 0x0}, + {0x900a9, 0x0}, + {0x900aa, 0x0}, + {0x900ab, 0x0}, + {0x900ac, 0x0}, + {0x900ad, 0x0}, + {0x900ae, 0x0}, + {0x900af, 0x0}, + {0x900b0, 0x0}, + {0x900b1, 0x0}, + {0x900b2, 0x0}, + {0x900b3, 0x0}, + {0x900b4, 0x0}, + {0x900b5, 0x0}, + {0x900b6, 0x0}, + {0x900b7, 0x0}, + {0x900b8, 0x0}, + {0x900b9, 0x0}, + {0x900ba, 0x0}, + {0x900bb, 0x0}, + {0x900bc, 0x0}, + {0x900bd, 0x0}, + {0x900be, 0x0}, + {0x900bf, 0x0}, + {0x900c0, 0x0}, + {0x900c1, 0x0}, + {0x900c2, 0x0}, + {0x900c3, 0x0}, + {0x900c4, 0x0}, + {0x900c5, 0x0}, + {0x900c6, 0x0}, + {0x900c7, 0x0}, + {0x900c8, 0x0}, + {0x900c9, 0x0}, + {0x900ca, 0x0}, + {0x900cb, 0x0}, + {0x900cc, 0x0}, + {0x900cd, 0x0}, + {0x900ce, 0x0}, + {0x900cf, 0x0}, + {0x900d0, 0x0}, + {0x900d1, 0x0}, + {0x900d2, 0x0}, + {0x900d3, 0x0}, + {0x900d4, 0x0}, + {0x900d5, 0x0}, + {0x900d6, 0x0}, + {0x900d7, 0x0}, + {0x900d8, 0x0}, + {0x900d9, 0x0}, + {0x900da, 0x0}, + {0x900db, 0x0}, + {0x900dc, 0x0}, + {0x900dd, 0x0}, + {0x900de, 0x0}, + {0x900df, 0x0}, + {0x900e0, 0x0}, + {0x900e1, 0x0}, + {0x900e2, 0x0}, + {0x900e3, 0x0}, + {0x900e4, 0x0}, + {0x900e5, 0x0}, + {0x900e6, 0x0}, + {0x900e7, 0x0}, + {0x900e8, 0x0}, + {0x900e9, 0x0}, + {0x900ea, 0x0}, + {0x900eb, 0x0}, + {0x900ec, 0x0}, + {0x900ed, 0x0}, + {0x900ee, 0x0}, + {0x900ef, 0x0}, + {0x900f0, 0x0}, + {0x900f1, 0x0}, + {0x900f2, 0x0}, + {0x900f3, 0x0}, + {0x900f4, 0x0}, + {0x900f5, 0x0}, + {0x900f6, 0x0}, + {0x900f7, 0x0}, + {0x900f8, 0x0}, + {0x900f9, 0x0}, + {0x900fa, 0x0}, + {0x900fb, 0x0}, + {0x900fc, 0x0}, + {0x900fd, 0x0}, + {0x900fe, 0x0}, + {0x900ff, 0x0}, + {0x90100, 0x0}, + {0x90101, 0x0}, + {0x90102, 0x0}, + {0x90103, 0x0}, + {0x90104, 0x0}, + {0x90105, 0x0}, + {0x90106, 0x0}, + {0x90107, 0x0}, + {0x90108, 0x0}, + {0x90109, 0x0}, + {0x9010a, 0x0}, + {0x9010b, 0x0}, + {0x9010c, 0x0}, + {0x9010d, 0x0}, + {0x9010e, 0x0}, + {0x9010f, 0x0}, + {0x90110, 0x0}, + {0x90111, 0x0}, + {0x90112, 0x0}, + {0x90113, 0x0}, + {0x90114, 0x0}, + {0x90115, 0x0}, + {0x90116, 0x0}, + {0x90117, 0x0}, + {0x90118, 0x0}, + {0x90119, 0x0}, + {0x9011a, 0x0}, + {0x9011b, 0x0}, + {0x9011c, 0x0}, + {0x9011d, 0x0}, + {0x9011e, 0x0}, + {0x9011f, 0x0}, + {0x90120, 0x0}, + {0x90121, 0x0}, + {0x90122, 0x0}, + {0x90123, 0x0}, + {0x90124, 0x0}, + {0x90125, 0x0}, + {0x90126, 0x0}, + {0x90127, 0x0}, + {0x90128, 0x0}, + {0x90129, 0x0}, + {0x9012a, 0x0}, + {0x9012b, 0x0}, + {0x9012c, 0x0}, + {0x9012d, 0x0}, + {0x9012e, 0x0}, + {0x9012f, 0x0}, + {0x90130, 0x0}, + {0x90131, 0x0}, + {0x90132, 0x0}, + {0x90133, 0x0}, + {0x90134, 0x0}, + {0x90135, 0x0}, + {0x90136, 0x0}, + {0x90137, 0x0}, + {0x90138, 0x0}, + {0x90139, 0x0}, + {0x9013a, 0x0}, + {0x9013b, 0x0}, + {0x9013c, 0x0}, + {0x9013d, 0x0}, + {0x9013e, 0x0}, + {0x9013f, 0x0}, + {0x90140, 0x0}, + {0x90141, 0x0}, + {0x90142, 0x0}, + {0x90143, 0x0}, + {0x90144, 0x0}, + {0x90145, 0x0}, + {0x90146, 0x0}, + {0x90147, 0x0}, + {0x90148, 0x0}, + {0x90149, 0x0}, + {0x9014a, 0x0}, + {0x9014b, 0x0}, + {0x9014c, 0x0}, + {0x9014d, 0x0}, + {0x9014e, 0x0}, + {0x9014f, 0x0}, + {0x90150, 0x0}, + {0x90151, 0x0}, + {0x90152, 0x0}, + {0x90153, 0x0}, + {0x90154, 0x0}, + {0x90155, 0x0}, + {0x90156, 0x0}, + {0x90157, 0x0}, + {0x90158, 0x0}, + {0x90159, 0x0}, + {0x9015a, 0x0}, + {0x9015b, 0x0}, + {0x9015c, 0x0}, + {0x9015d, 0x0}, + {0x9015e, 0x0}, + {0x9015f, 0x0}, + {0x90160, 0x0}, + {0x90161, 0x0}, + {0x90162, 0x0}, + {0x90163, 0x0}, + {0x90164, 0x0}, + {0x90165, 0x0}, + {0x90166, 0x0}, + {0x90167, 0x0}, + {0x90168, 0x0}, + {0x90169, 0x0}, + {0x9016a, 0x0}, + {0x9016b, 0x0}, + {0x9016c, 0x0}, + {0x9016d, 0x0}, + {0x9016e, 0x0}, + {0x9016f, 0x0}, + {0x90170, 0x0}, + {0x90171, 0x0}, + {0x90172, 0x0}, + {0x90173, 0x0}, + {0x90174, 0x0}, + {0x90175, 0x0}, + {0x90176, 0x0}, + {0x90177, 0x0}, + {0x90178, 0x0}, + {0x90179, 0x0}, + {0x9017a, 0x0}, + {0x9017b, 0x0}, + {0x9017c, 0x0}, + {0x9017d, 0x0}, + {0x9017e, 0x0}, + {0x9017f, 0x0}, + {0x90180, 0x0}, + {0x90181, 0x0}, + {0x90006, 0x0}, + {0x90007, 0x0}, + {0x90008, 0x0}, + {0x90009, 0x0}, + {0x9000a, 0x0}, + {0x9000b, 0x0}, + {0xd00e7, 0x0}, + {0x90017, 0x0}, + {0x9001f, 0x0}, + {0x90026, 0x0}, + {0x400d0, 0x0}, + {0x400d1, 0x0}, + {0x400d2, 0x0}, + {0x400d3, 0x0}, + {0x400d4, 0x0}, + {0x400d5, 0x0}, + {0x400d6, 0x0}, + {0x400d7, 0x0}, + {0x200be, 0x0}, + {0x2000b, 0x0}, + {0x2000c, 0x0}, + {0x2000d, 0x0}, + {0x2000e, 0x0}, + {0x9000c, 0x0}, + {0x9000d, 0x0}, + {0x9000e, 0x0}, + {0x9000f, 0x0}, + {0x90010, 0x0}, + {0x90011, 0x0}, + {0x90012, 0x0}, + {0x90013, 0x0}, + {0x20010, 0x0}, + {0x20011, 0x0}, + {0x40080, 0x0}, + {0x40081, 0x0}, + {0x40082, 0x0}, + {0x40083, 0x0}, + {0x40084, 0x0}, + {0x40085, 0x0}, + {0x400fd, 0x0}, + {0x10011, 0x0}, + {0x10012, 0x0}, + {0x10013, 0x0}, + {0x10018, 0x0}, + {0x10002, 0x0}, + {0x100b2, 0x0}, + {0x101b4, 0x0}, + {0x102b4, 0x0}, + {0x103b4, 0x0}, + {0x104b4, 0x0}, + {0x105b4, 0x0}, + {0x106b4, 0x0}, + {0x107b4, 0x0}, + {0x108b4, 0x0}, + {0x11011, 0x0}, + {0x11012, 0x0}, + {0x11013, 0x0}, + {0x11018, 0x0}, + {0x11002, 0x0}, + {0x110b2, 0x0}, + {0x111b4, 0x0}, + {0x112b4, 0x0}, + {0x113b4, 0x0}, + {0x114b4, 0x0}, + {0x115b4, 0x0}, + {0x116b4, 0x0}, + {0x117b4, 0x0}, + {0x118b4, 0x0}, + {0x12011, 0x0}, + {0x12012, 0x0}, + {0x12013, 0x0}, + {0x12018, 0x0}, + {0x12002, 0x0}, + {0x120b2, 0x0}, + {0x121b4, 0x0}, + {0x122b4, 0x0}, + {0x123b4, 0x0}, + {0x124b4, 0x0}, + {0x125b4, 0x0}, + {0x126b4, 0x0}, + {0x127b4, 0x0}, + {0x128b4, 0x0}, + {0x13011, 0x0}, + {0x13012, 0x0}, + {0x13013, 0x0}, + {0x13018, 0x0}, + {0x13002, 0x0}, + {0x130b2, 0x0}, + {0x131b4, 0x0}, + {0x132b4, 0x0}, + {0x133b4, 0x0}, + {0x134b4, 0x0}, + {0x135b4, 0x0}, + {0x136b4, 0x0}, + {0x137b4, 0x0}, + {0x138b4, 0x0}, + {0x20089, 0x0}, + {0xc0080, 0x0}, + {0x200cb, 0x0}, + {0x10068, 0x0}, + {0x10069, 0x0}, + {0x10168, 0x0}, + {0x10169, 0x0}, + {0x10268, 0x0}, + {0x10269, 0x0}, + {0x10368, 0x0}, + {0x10369, 0x0}, + {0x10468, 0x0}, + {0x10469, 0x0}, + {0x10568, 0x0}, + {0x10569, 0x0}, + {0x10668, 0x0}, + {0x10669, 0x0}, + {0x10768, 0x0}, + {0x10769, 0x0}, + {0x10868, 0x0}, + {0x10869, 0x0}, + {0x100aa, 0x0}, + {0x10062, 0x0}, + {0x10001, 0x0}, + {0x100a0, 0x0}, + {0x100a1, 0x0}, + {0x100a2, 0x0}, + {0x100a3, 0x0}, + {0x100a4, 0x0}, + {0x100a5, 0x0}, + {0x100a6, 0x0}, + {0x100a7, 0x0}, + {0x11068, 0x0}, + {0x11069, 0x0}, + {0x11168, 0x0}, + {0x11169, 0x0}, + {0x11268, 0x0}, + {0x11269, 0x0}, + {0x11368, 0x0}, + {0x11369, 0x0}, + {0x11468, 0x0}, + {0x11469, 0x0}, + {0x11568, 0x0}, + {0x11569, 0x0}, + {0x11668, 0x0}, + {0x11669, 0x0}, + {0x11768, 0x0}, + {0x11769, 0x0}, + {0x11868, 0x0}, + {0x11869, 0x0}, + {0x110aa, 0x0}, + {0x11062, 0x0}, + {0x11001, 0x0}, + {0x110a0, 0x0}, + {0x110a1, 0x0}, + {0x110a2, 0x0}, + {0x110a3, 0x0}, + {0x110a4, 0x0}, + {0x110a5, 0x0}, + {0x110a6, 0x0}, + {0x110a7, 0x0}, + {0x12068, 0x0}, + {0x12069, 0x0}, + {0x12168, 0x0}, + {0x12169, 0x0}, + {0x12268, 0x0}, + {0x12269, 0x0}, + {0x12368, 0x0}, + {0x12369, 0x0}, + {0x12468, 0x0}, + {0x12469, 0x0}, + {0x12568, 0x0}, + {0x12569, 0x0}, + {0x12668, 0x0}, + {0x12669, 0x0}, + {0x12768, 0x0}, + {0x12769, 0x0}, + {0x12868, 0x0}, + {0x12869, 0x0}, + {0x120aa, 0x0}, + {0x12062, 0x0}, + {0x12001, 0x0}, + {0x120a0, 0x0}, + {0x120a1, 0x0}, + {0x120a2, 0x0}, + {0x120a3, 0x0}, + {0x120a4, 0x0}, + {0x120a5, 0x0}, + {0x120a6, 0x0}, + {0x120a7, 0x0}, + {0x13068, 0x0}, + {0x13069, 0x0}, + {0x13168, 0x0}, + {0x13169, 0x0}, + {0x13268, 0x0}, + {0x13269, 0x0}, + {0x13368, 0x0}, + {0x13369, 0x0}, + {0x13468, 0x0}, + {0x13469, 0x0}, + {0x13568, 0x0}, + {0x13569, 0x0}, + {0x13668, 0x0}, + {0x13669, 0x0}, + {0x13768, 0x0}, + {0x13769, 0x0}, + {0x13868, 0x0}, + {0x13869, 0x0}, + {0x130aa, 0x0}, + {0x13062, 0x0}, + {0x13001, 0x0}, + {0x130a0, 0x0}, + {0x130a1, 0x0}, + {0x130a2, 0x0}, + {0x130a3, 0x0}, + {0x130a4, 0x0}, + {0x130a5, 0x0}, + {0x130a6, 0x0}, + {0x130a7, 0x0}, + {0x80, 0x0}, + {0x1080, 0x0}, + {0x2080, 0x0}, + {0x3080, 0x0}, + {0x4080, 0x0}, + {0x5080, 0x0}, + {0x6080, 0x0}, + {0x7080, 0x0}, + {0x8080, 0x0}, + {0x9080, 0x0}, + {0x10020, 0x0}, + {0x10080, 0x0}, + {0x10081, 0x0}, + {0x100d0, 0x0}, + {0x100d1, 0x0}, + {0x1008c, 0x0}, + {0x1008d, 0x0}, + {0x10180, 0x0}, + {0x10181, 0x0}, + {0x101d0, 0x0}, + {0x101d1, 0x0}, + {0x1018c, 0x0}, + {0x1018d, 0x0}, + {0x100c0, 0x0}, + {0x100c1, 0x0}, + {0x101c0, 0x0}, + {0x101c1, 0x0}, + {0x102c0, 0x0}, + {0x102c1, 0x0}, + {0x103c0, 0x0}, + {0x103c1, 0x0}, + {0x104c0, 0x0}, + {0x104c1, 0x0}, + {0x105c0, 0x0}, + {0x105c1, 0x0}, + {0x106c0, 0x0}, + {0x106c1, 0x0}, + {0x107c0, 0x0}, + {0x107c1, 0x0}, + {0x108c0, 0x0}, + {0x108c1, 0x0}, + {0x100ae, 0x0}, + {0x100af, 0x0}, + {0x11020, 0x0}, + {0x11080, 0x0}, + {0x11081, 0x0}, + {0x110d0, 0x0}, + {0x110d1, 0x0}, + {0x1108c, 0x0}, + {0x1108d, 0x0}, + {0x11180, 0x0}, + {0x11181, 0x0}, + {0x111d0, 0x0}, + {0x111d1, 0x0}, + {0x1118c, 0x0}, + {0x1118d, 0x0}, + {0x110c0, 0x0}, + {0x110c1, 0x0}, + {0x111c0, 0x0}, + {0x111c1, 0x0}, + {0x112c0, 0x0}, + {0x112c1, 0x0}, + {0x113c0, 0x0}, + {0x113c1, 0x0}, + {0x114c0, 0x0}, + {0x114c1, 0x0}, + {0x115c0, 0x0}, + {0x115c1, 0x0}, + {0x116c0, 0x0}, + {0x116c1, 0x0}, + {0x117c0, 0x0}, + {0x117c1, 0x0}, + {0x118c0, 0x0}, + {0x118c1, 0x0}, + {0x110ae, 0x0}, + {0x110af, 0x0}, + {0x12020, 0x0}, + {0x12080, 0x0}, + {0x12081, 0x0}, + {0x120d0, 0x0}, + {0x120d1, 0x0}, + {0x1208c, 0x0}, + {0x1208d, 0x0}, + {0x12180, 0x0}, + {0x12181, 0x0}, + {0x121d0, 0x0}, + {0x121d1, 0x0}, + {0x1218c, 0x0}, + {0x1218d, 0x0}, + {0x120c0, 0x0}, + {0x120c1, 0x0}, + {0x121c0, 0x0}, + {0x121c1, 0x0}, + {0x122c0, 0x0}, + {0x122c1, 0x0}, + {0x123c0, 0x0}, + {0x123c1, 0x0}, + {0x124c0, 0x0}, + {0x124c1, 0x0}, + {0x125c0, 0x0}, + {0x125c1, 0x0}, + {0x126c0, 0x0}, + {0x126c1, 0x0}, + {0x127c0, 0x0}, + {0x127c1, 0x0}, + {0x128c0, 0x0}, + {0x128c1, 0x0}, + {0x120ae, 0x0}, + {0x120af, 0x0}, + {0x13020, 0x0}, + {0x13080, 0x0}, + {0x13081, 0x0}, + {0x130d0, 0x0}, + {0x130d1, 0x0}, + {0x1308c, 0x0}, + {0x1308d, 0x0}, + {0x13180, 0x0}, + {0x13181, 0x0}, + {0x131d0, 0x0}, + {0x131d1, 0x0}, + {0x1318c, 0x0}, + {0x1318d, 0x0}, + {0x130c0, 0x0}, + {0x130c1, 0x0}, + {0x131c0, 0x0}, + {0x131c1, 0x0}, + {0x132c0, 0x0}, + {0x132c1, 0x0}, + {0x133c0, 0x0}, + {0x133c1, 0x0}, + {0x134c0, 0x0}, + {0x134c1, 0x0}, + {0x135c0, 0x0}, + {0x135c1, 0x0}, + {0x136c0, 0x0}, + {0x136c1, 0x0}, + {0x137c0, 0x0}, + {0x137c1, 0x0}, + {0x138c0, 0x0}, + {0x138c1, 0x0}, + {0x130ae, 0x0}, + {0x130af, 0x0}, + {0x90201, 0x0}, + {0x90202, 0x0}, + {0x90203, 0x0}, + {0x90205, 0x0}, + {0x90206, 0x0}, + {0x90207, 0x0}, + {0x90208, 0x0}, + {0x20020, 0x0}, + {0x20077, 0x0}, + {0x20072, 0x0}, + {0x20073, 0x0}, + {0x400c0, 0x0}, + {0x10040, 0x0}, + {0x10140, 0x0}, + {0x10240, 0x0}, + {0x10340, 0x0}, + {0x10440, 0x0}, + {0x10540, 0x0}, + {0x10640, 0x0}, + {0x10740, 0x0}, + {0x10840, 0x0}, + {0x11040, 0x0}, + {0x11140, 0x0}, + {0x11240, 0x0}, + {0x11340, 0x0}, + {0x11440, 0x0}, + {0x11540, 0x0}, + {0x11640, 0x0}, + {0x11740, 0x0}, + {0x11840, 0x0}, + {0x12040, 0x0}, + {0x12140, 0x0}, + {0x12240, 0x0}, + {0x12340, 0x0}, + {0x12440, 0x0}, + {0x12540, 0x0}, + {0x12640, 0x0}, + {0x12740, 0x0}, + {0x12840, 0x0}, + {0x13040, 0x0}, + {0x13140, 0x0}, + {0x13240, 0x0}, + {0x13340, 0x0}, + {0x13440, 0x0}, + {0x13540, 0x0}, + {0x13640, 0x0}, + {0x13740, 0x0}, + {0x13840, 0x0}, +}; + +/* P0 message block parameter for training firmware */ +struct dram_cfg_param ddr_fsp0_cfg[] = { + {0xd0000, 0x0}, + {0x54003, 0xfa0}, + {0x54004, 0x2}, + {0x54005, 0x3c3c}, + {0x54006, 0x11}, + {0x54008, 0x131f}, + {0x54009, 0xc8}, + {0x5400b, 0x2}, + {0x5400f, 0x100}, + {0x54012, 0x110}, + {0x54019, 0x3ff4}, + {0x5401a, 0xe3}, + {0x5401b, 0x4844}, + {0x5401c, 0x4800}, + {0x5401e, 0x14}, + {0x5401f, 0x3ff4}, + {0x54020, 0xe3}, + {0x54021, 0x4844}, + {0x54022, 0x4800}, + {0x54024, 0x14}, + {0x5402b, 0x1000}, + {0x5402c, 0x1}, + {0x54032, 0xf400}, + {0x54033, 0xe33f}, + {0x54034, 0x4400}, + {0x54035, 0x48}, + {0x54036, 0x48}, + {0x54037, 0x1400}, + {0x54038, 0xf400}, + {0x54039, 0xe33f}, + {0x5403a, 0x4400}, + {0x5403b, 0x48}, + {0x5403c, 0x48}, + {0x5403d, 0x1400}, + {0xd0000, 0x1} +}; + +/* P0 2D message block parameter for training firmware */ +struct dram_cfg_param ddr_fsp0_2d_cfg[] = { + {0xd0000, 0x0}, + {0x54003, 0xfa0}, + {0x54004, 0x2}, + {0x54005, 0x3c3c}, + {0x54006, 0x11}, + {0x54008, 0x61}, + {0x54009, 0xc8}, + {0x5400b, 0x2}, + {0x5400f, 0x100}, + {0x54010, 0x1f7f}, + {0x54012, 0x110}, + {0x54019, 0x3ff4}, + {0x5401a, 0xe3}, + {0x5401b, 0x4844}, + {0x5401c, 0x4800}, + {0x5401e, 0x14}, + {0x5401f, 0x3ff4}, + {0x54020, 0xe3}, + {0x54021, 0x4844}, + {0x54022, 0x4800}, + {0x54024, 0x14}, + {0x5402b, 0x1000}, + {0x5402c, 0x1}, + {0x54032, 0xf400}, + {0x54033, 0xe33f}, + {0x54034, 0x4400}, + {0x54035, 0x48}, + {0x54036, 0x48}, + {0x54037, 0x1400}, + {0x54038, 0xf400}, + {0x54039, 0xe33f}, + {0x5403a, 0x4400}, + {0x5403b, 0x48}, + {0x5403c, 0x48}, + {0x5403d, 0x1400}, + {0xd0000, 0x1} +}; + +/* DRAM PHY init engine image */ +struct dram_cfg_param ddr_phy_pie[] = { + {0xd0000, 0x0}, + {0x90000, 0x10}, + {0x90001, 0x400}, + {0x90002, 0x10e}, + {0x90003, 0x0}, + {0x90004, 0x0}, + {0x90005, 0x8}, + {0x90029, 0xb}, + {0x9002a, 0x480}, + {0x9002b, 0x109}, + {0x9002c, 0x8}, + {0x9002d, 0x448}, + {0x9002e, 0x139}, + {0x9002f, 0x8}, + {0x90030, 0x478}, + {0x90031, 0x109}, + {0x90032, 0x0}, + {0x90033, 0xe8}, + {0x90034, 0x109}, + {0x90035, 0x2}, + {0x90036, 0x10}, + {0x90037, 0x139}, + {0x90038, 0xb}, + {0x90039, 0x7c0}, + {0x9003a, 0x139}, + {0x9003b, 0x44}, + {0x9003c, 0x633}, + {0x9003d, 0x159}, + {0x9003e, 0x14f}, + {0x9003f, 0x630}, + {0x90040, 0x159}, + {0x90041, 0x47}, + {0x90042, 0x633}, + {0x90043, 0x149}, + {0x90044, 0x4f}, + {0x90045, 0x633}, + {0x90046, 0x179}, + {0x90047, 0x8}, + {0x90048, 0xe0}, + {0x90049, 0x109}, + {0x9004a, 0x0}, + {0x9004b, 0x7c8}, + {0x9004c, 0x109}, + {0x9004d, 0x0}, + {0x9004e, 0x1}, + {0x9004f, 0x8}, + {0x90050, 0x0}, + {0x90051, 0x45a}, + {0x90052, 0x9}, + {0x90053, 0x0}, + {0x90054, 0x448}, + {0x90055, 0x109}, + {0x90056, 0x40}, + {0x90057, 0x633}, + {0x90058, 0x179}, + {0x90059, 0x1}, + {0x9005a, 0x618}, + {0x9005b, 0x109}, + {0x9005c, 0x40c0}, + {0x9005d, 0x633}, + {0x9005e, 0x149}, + {0x9005f, 0x8}, + {0x90060, 0x4}, + {0x90061, 0x48}, + {0x90062, 0x4040}, + {0x90063, 0x633}, + {0x90064, 0x149}, + {0x90065, 0x0}, + {0x90066, 0x4}, + {0x90067, 0x48}, + {0x90068, 0x40}, + {0x90069, 0x633}, + {0x9006a, 0x149}, + {0x9006b, 0x10}, + {0x9006c, 0x4}, + {0x9006d, 0x18}, + {0x9006e, 0x0}, + {0x9006f, 0x4}, + {0x90070, 0x78}, + {0x90071, 0x549}, + {0x90072, 0x633}, + {0x90073, 0x159}, + {0x90074, 0xd49}, + {0x90075, 0x633}, + {0x90076, 0x159}, + {0x90077, 0x94a}, + {0x90078, 0x633}, + {0x90079, 0x159}, + {0x9007a, 0x441}, + {0x9007b, 0x633}, + {0x9007c, 0x149}, + {0x9007d, 0x42}, + {0x9007e, 0x633}, + {0x9007f, 0x149}, + {0x90080, 0x1}, + {0x90081, 0x633}, + {0x90082, 0x149}, + {0x90083, 0x0}, + {0x90084, 0xe0}, + {0x90085, 0x109}, + {0x90086, 0xa}, + {0x90087, 0x10}, + {0x90088, 0x109}, + {0x90089, 0x9}, + {0x9008a, 0x3c0}, + {0x9008b, 0x149}, + {0x9008c, 0x9}, + {0x9008d, 0x3c0}, + {0x9008e, 0x159}, + {0x9008f, 0x18}, + {0x90090, 0x10}, + {0x90091, 0x109}, + {0x90092, 0x0}, + {0x90093, 0x3c0}, + {0x90094, 0x109}, + {0x90095, 0x18}, + {0x90096, 0x4}, + {0x90097, 0x48}, + {0x90098, 0x18}, + {0x90099, 0x4}, + {0x9009a, 0x58}, + {0x9009b, 0xb}, + {0x9009c, 0x10}, + {0x9009d, 0x109}, + {0x9009e, 0x1}, + {0x9009f, 0x10}, + {0x900a0, 0x109}, + {0x900a1, 0x5}, + {0x900a2, 0x7c0}, + {0x900a3, 0x109}, + {0x40000, 0x811}, + {0x40020, 0x880}, + {0x40040, 0x0}, + {0x40060, 0x0}, + {0x40001, 0x4008}, + {0x40021, 0x83}, + {0x40041, 0x4f}, + {0x40061, 0x0}, + {0x40002, 0x4040}, + {0x40022, 0x83}, + {0x40042, 0x51}, + {0x40062, 0x0}, + {0x40003, 0x811}, + {0x40023, 0x880}, + {0x40043, 0x0}, + {0x40063, 0x0}, + {0x40004, 0x720}, + {0x40024, 0xf}, + {0x40044, 0x1740}, + {0x40064, 0x0}, + {0x40005, 0x16}, + {0x40025, 0x83}, + {0x40045, 0x4b}, + {0x40065, 0x0}, + {0x40006, 0x716}, + {0x40026, 0xf}, + {0x40046, 0x2001}, + {0x40066, 0x0}, + {0x40007, 0x716}, + {0x40027, 0xf}, + {0x40047, 0x2800}, + {0x40067, 0x0}, + {0x40008, 0x716}, + {0x40028, 0xf}, + {0x40048, 0xf00}, + {0x40068, 0x0}, + {0x40009, 0x720}, + {0x40029, 0xf}, + {0x40049, 0x1400}, + {0x40069, 0x0}, + {0x4000a, 0xe08}, + {0x4002a, 0xc15}, + {0x4004a, 0x0}, + {0x4006a, 0x0}, + {0x4000b, 0x625}, + {0x4002b, 0x15}, + {0x4004b, 0x0}, + {0x4006b, 0x0}, + {0x4000c, 0x4028}, + {0x4002c, 0x80}, + {0x4004c, 0x0}, + {0x4006c, 0x0}, + {0x4000d, 0xe08}, + {0x4002d, 0xc1a}, + {0x4004d, 0x0}, + {0x4006d, 0x0}, + {0x4000e, 0x625}, + {0x4002e, 0x1a}, + {0x4004e, 0x0}, + {0x4006e, 0x0}, + {0x4000f, 0x4040}, + {0x4002f, 0x80}, + {0x4004f, 0x0}, + {0x4006f, 0x0}, + {0x40010, 0x2604}, + {0x40030, 0x15}, + {0x40050, 0x0}, + {0x40070, 0x0}, + {0x40011, 0x708}, + {0x40031, 0x5}, + {0x40051, 0x0}, + {0x40071, 0x2002}, + {0x40012, 0x8}, + {0x40032, 0x80}, + {0x40052, 0x0}, + {0x40072, 0x0}, + {0x40013, 0x2604}, + {0x40033, 0x1a}, + {0x40053, 0x0}, + {0x40073, 0x0}, + {0x40014, 0x708}, + {0x40034, 0xa}, + {0x40054, 0x0}, + {0x40074, 0x2002}, + {0x40015, 0x4040}, + {0x40035, 0x80}, + {0x40055, 0x0}, + {0x40075, 0x0}, + {0x40016, 0x60a}, + {0x40036, 0x15}, + {0x40056, 0x1200}, + {0x40076, 0x0}, + {0x40017, 0x61a}, + {0x40037, 0x15}, + {0x40057, 0x1300}, + {0x40077, 0x0}, + {0x40018, 0x60a}, + {0x40038, 0x1a}, + {0x40058, 0x1200}, + {0x40078, 0x0}, + {0x40019, 0x642}, + {0x40039, 0x1a}, + {0x40059, 0x1300}, + {0x40079, 0x0}, + {0x4001a, 0x4808}, + {0x4003a, 0x880}, + {0x4005a, 0x0}, + {0x4007a, 0x0}, + {0x900a4, 0x0}, + {0x900a5, 0x790}, + {0x900a6, 0x11a}, + {0x900a7, 0x8}, + {0x900a8, 0x7aa}, + {0x900a9, 0x2a}, + {0x900aa, 0x10}, + {0x900ab, 0x7b2}, + {0x900ac, 0x2a}, + {0x900ad, 0x0}, + {0x900ae, 0x7c8}, + {0x900af, 0x109}, + {0x900b0, 0x10}, + {0x900b1, 0x10}, + {0x900b2, 0x109}, + {0x900b3, 0x10}, + {0x900b4, 0x2a8}, + {0x900b5, 0x129}, + {0x900b6, 0x8}, + {0x900b7, 0x370}, + {0x900b8, 0x129}, + {0x900b9, 0xa}, + {0x900ba, 0x3c8}, + {0x900bb, 0x1a9}, + {0x900bc, 0xc}, + {0x900bd, 0x408}, + {0x900be, 0x199}, + {0x900bf, 0x14}, + {0x900c0, 0x790}, + {0x900c1, 0x11a}, + {0x900c2, 0x8}, + {0x900c3, 0x4}, + {0x900c4, 0x18}, + {0x900c5, 0xe}, + {0x900c6, 0x408}, + {0x900c7, 0x199}, + {0x900c8, 0x8}, + {0x900c9, 0x8568}, + {0x900ca, 0x108}, + {0x900cb, 0x18}, + {0x900cc, 0x790}, + {0x900cd, 0x16a}, + {0x900ce, 0x8}, + {0x900cf, 0x1d8}, + {0x900d0, 0x169}, + {0x900d1, 0x10}, + {0x900d2, 0x8558}, + {0x900d3, 0x168}, + {0x900d4, 0x70}, + {0x900d5, 0x788}, + {0x900d6, 0x16a}, + {0x900d7, 0x1ff8}, + {0x900d8, 0x85a8}, + {0x900d9, 0x1e8}, + {0x900da, 0x50}, + {0x900db, 0x798}, + {0x900dc, 0x16a}, + {0x900dd, 0x60}, + {0x900de, 0x7a0}, + {0x900df, 0x16a}, + {0x900e0, 0x8}, + {0x900e1, 0x8310}, + {0x900e2, 0x168}, + {0x900e3, 0x8}, + {0x900e4, 0xa310}, + {0x900e5, 0x168}, + {0x900e6, 0xa}, + {0x900e7, 0x408}, + {0x900e8, 0x169}, + {0x900e9, 0x6e}, + {0x900ea, 0x0}, + {0x900eb, 0x68}, + {0x900ec, 0x0}, + {0x900ed, 0x408}, + {0x900ee, 0x169}, + {0x900ef, 0x0}, + {0x900f0, 0x8310}, + {0x900f1, 0x168}, + {0x900f2, 0x0}, + {0x900f3, 0xa310}, + {0x900f4, 0x168}, + {0x900f5, 0x1ff8}, + {0x900f6, 0x85a8}, + {0x900f7, 0x1e8}, + {0x900f8, 0x68}, + {0x900f9, 0x798}, + {0x900fa, 0x16a}, + {0x900fb, 0x78}, + {0x900fc, 0x7a0}, + {0x900fd, 0x16a}, + {0x900fe, 0x68}, + {0x900ff, 0x790}, + {0x90100, 0x16a}, + {0x90101, 0x8}, + {0x90102, 0x8b10}, + {0x90103, 0x168}, + {0x90104, 0x8}, + {0x90105, 0xab10}, + {0x90106, 0x168}, + {0x90107, 0xa}, + {0x90108, 0x408}, + {0x90109, 0x169}, + {0x9010a, 0x58}, + {0x9010b, 0x0}, + {0x9010c, 0x68}, + {0x9010d, 0x0}, + {0x9010e, 0x408}, + {0x9010f, 0x169}, + {0x90110, 0x0}, + {0x90111, 0x8b10}, + {0x90112, 0x168}, + {0x90113, 0x1}, + {0x90114, 0xab10}, + {0x90115, 0x168}, + {0x90116, 0x0}, + {0x90117, 0x1d8}, + {0x90118, 0x169}, + {0x90119, 0x80}, + {0x9011a, 0x790}, + {0x9011b, 0x16a}, + {0x9011c, 0x18}, + {0x9011d, 0x7aa}, + {0x9011e, 0x6a}, + {0x9011f, 0xa}, + {0x90120, 0x0}, + {0x90121, 0x1e9}, + {0x90122, 0x8}, + {0x90123, 0x8080}, + {0x90124, 0x108}, + {0x90125, 0xf}, + {0x90126, 0x408}, + {0x90127, 0x169}, + {0x90128, 0xc}, + {0x90129, 0x0}, + {0x9012a, 0x68}, + {0x9012b, 0x9}, + {0x9012c, 0x0}, + {0x9012d, 0x1a9}, + {0x9012e, 0x0}, + {0x9012f, 0x408}, + {0x90130, 0x169}, + {0x90131, 0x0}, + {0x90132, 0x8080}, + {0x90133, 0x108}, + {0x90134, 0x8}, + {0x90135, 0x7aa}, + {0x90136, 0x6a}, + {0x90137, 0x0}, + {0x90138, 0x8568}, + {0x90139, 0x108}, + {0x9013a, 0xb7}, + {0x9013b, 0x790}, + {0x9013c, 0x16a}, + {0x9013d, 0x1f}, + {0x9013e, 0x0}, + {0x9013f, 0x68}, + {0x90140, 0x8}, + {0x90141, 0x8558}, + {0x90142, 0x168}, + {0x90143, 0xf}, + {0x90144, 0x408}, + {0x90145, 0x169}, + {0x90146, 0xd}, + {0x90147, 0x0}, + {0x90148, 0x68}, + {0x90149, 0x0}, + {0x9014a, 0x408}, + {0x9014b, 0x169}, + {0x9014c, 0x0}, + {0x9014d, 0x8558}, + {0x9014e, 0x168}, + {0x9014f, 0x8}, + {0x90150, 0x3c8}, + {0x90151, 0x1a9}, + {0x90152, 0x3}, + {0x90153, 0x370}, + {0x90154, 0x129}, + {0x90155, 0x20}, + {0x90156, 0x2aa}, + {0x90157, 0x9}, + {0x90158, 0x8}, + {0x90159, 0xe8}, + {0x9015a, 0x109}, + {0x9015b, 0x0}, + {0x9015c, 0x8140}, + {0x9015d, 0x10c}, + {0x9015e, 0x10}, + {0x9015f, 0x8138}, + {0x90160, 0x104}, + {0x90161, 0x8}, + {0x90162, 0x448}, + {0x90163, 0x109}, + {0x90164, 0xf}, + {0x90165, 0x7c0}, + {0x90166, 0x109}, + {0x90167, 0x0}, + {0x90168, 0xe8}, + {0x90169, 0x109}, + {0x9016a, 0x47}, + {0x9016b, 0x630}, + {0x9016c, 0x109}, + {0x9016d, 0x8}, + {0x9016e, 0x618}, + {0x9016f, 0x109}, + {0x90170, 0x8}, + {0x90171, 0xe0}, + {0x90172, 0x109}, + {0x90173, 0x0}, + {0x90174, 0x7c8}, + {0x90175, 0x109}, + {0x90176, 0x8}, + {0x90177, 0x8140}, + {0x90178, 0x10c}, + {0x90179, 0x0}, + {0x9017a, 0x478}, + {0x9017b, 0x109}, + {0x9017c, 0x0}, + {0x9017d, 0x1}, + {0x9017e, 0x8}, + {0x9017f, 0x8}, + {0x90180, 0x4}, + {0x90181, 0x0}, + {0x90006, 0x8}, + {0x90007, 0x7c8}, + {0x90008, 0x109}, + {0x90009, 0x0}, + {0x9000a, 0x400}, + {0x9000b, 0x106}, + {0xd00e7, 0x400}, + {0x90017, 0x0}, + {0x9001f, 0x29}, + {0x90026, 0x68}, + {0x400d0, 0x0}, + {0x400d1, 0x101}, + {0x400d2, 0x105}, + {0x400d3, 0x107}, + {0x400d4, 0x10f}, + {0x400d5, 0x202}, + {0x400d6, 0x20a}, + {0x400d7, 0x20b}, + {0x2003a, 0x2}, + {0x200be, 0x3}, + {0x2000b, 0x7d}, + {0x2000c, 0xfa}, + {0x2000d, 0x9c4}, + {0x2000e, 0x2c}, + {0x9000c, 0x0}, + {0x9000d, 0x173}, + {0x9000e, 0x60}, + {0x9000f, 0x6110}, + {0x90010, 0x2152}, + {0x90011, 0xdfbd}, + {0x90012, 0x2060}, + {0x90013, 0x6152}, + {0x20010, 0x5a}, + {0x20011, 0x3}, + {0x40080, 0xe0}, + {0x40081, 0x12}, + {0x40082, 0xe0}, + {0x40083, 0x12}, + {0x40084, 0xe0}, + {0x40085, 0x12}, + {0x400fd, 0xf}, + {0x10011, 0x1}, + {0x10012, 0x1}, + {0x10013, 0x180}, + {0x10018, 0x1}, + {0x10002, 0x6209}, + {0x100b2, 0x1}, + {0x101b4, 0x1}, + {0x102b4, 0x1}, + {0x103b4, 0x1}, + {0x104b4, 0x1}, + {0x105b4, 0x1}, + {0x106b4, 0x1}, + {0x107b4, 0x1}, + {0x108b4, 0x1}, + {0x11011, 0x1}, + {0x11012, 0x1}, + {0x11013, 0x180}, + {0x11018, 0x1}, + {0x11002, 0x6209}, + {0x110b2, 0x1}, + {0x111b4, 0x1}, + {0x112b4, 0x1}, + {0x113b4, 0x1}, + {0x114b4, 0x1}, + {0x115b4, 0x1}, + {0x116b4, 0x1}, + {0x117b4, 0x1}, + {0x118b4, 0x1}, + {0x12011, 0x1}, + {0x12012, 0x1}, + {0x12013, 0x180}, + {0x12018, 0x1}, + {0x12002, 0x6209}, + {0x120b2, 0x1}, + {0x121b4, 0x1}, + {0x122b4, 0x1}, + {0x123b4, 0x1}, + {0x124b4, 0x1}, + {0x125b4, 0x1}, + {0x126b4, 0x1}, + {0x127b4, 0x1}, + {0x128b4, 0x1}, + {0x13011, 0x1}, + {0x13012, 0x1}, + {0x13013, 0x180}, + {0x13018, 0x1}, + {0x13002, 0x6209}, + {0x130b2, 0x1}, + {0x131b4, 0x1}, + {0x132b4, 0x1}, + {0x133b4, 0x1}, + {0x134b4, 0x1}, + {0x135b4, 0x1}, + {0x136b4, 0x1}, + {0x137b4, 0x1}, + {0x138b4, 0x1}, + {0x20089, 0x1}, + {0x20088, 0x19}, + {0xc0080, 0x2}, + {0xd0000, 0x1}, +}; + +struct dram_fsp_msg ddr_dram_fsp_msg[] = { + { + /* P0 4000mts 1D */ + .drate = 4000, + .fw_type = FW_1D_IMAGE, + .fsp_cfg = ddr_fsp0_cfg, + .fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_cfg), + }, + { + /* P0 4000mts 2D */ + .drate = 4000, + .fw_type = FW_2D_IMAGE, + .fsp_cfg = ddr_fsp0_2d_cfg, + .fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_2d_cfg), + }, +}; + +/* ddr timing config params */ +struct dram_timing_info dram_timing = { + .ddrc_cfg = ddr_ddrc_cfg, + .ddrc_cfg_num = ARRAY_SIZE(ddr_ddrc_cfg), + .ddrphy_cfg = ddr_ddrphy_cfg, + .ddrphy_cfg_num = ARRAY_SIZE(ddr_ddrphy_cfg), + .fsp_msg = ddr_dram_fsp_msg, + .fsp_msg_num = ARRAY_SIZE(ddr_dram_fsp_msg), + .ddrphy_trained_csr = ddr_ddrphy_trained_csr, + .ddrphy_trained_csr_num = ARRAY_SIZE(ddr_ddrphy_trained_csr), + .ddrphy_pie = ddr_phy_pie, + .ddrphy_pie_num = ARRAY_SIZE(ddr_phy_pie), + .fsp_table = { 4000, }, +}; diff --git a/board/phytec/imx8mp-libra-fpsc/spl.c b/board/phytec/imx8mp-libra-fpsc/spl.c new file mode 100644 index 00000000000..d704d588579 --- /dev/null +++ b/board/phytec/imx8mp-libra-fpsc/spl.c @@ -0,0 +1,132 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Copyright (C) 2025 PHYTEC Messtechnik GmbH + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#if IS_ENABLED(CONFIG_PHYTEC_SOM_DETECTION) +#include "../common/imx8m_som_detection.h" +#endif + +DECLARE_GLOBAL_DATA_PTR; + +#define EEPROM_ADDR 0x51 + +int spl_board_boot_device(enum boot_device boot_dev_spl) +{ + return BOOT_DEVICE_BOOTROM; +} + +void spl_dram_init(void) +{ +#if IS_ENABLED(CONFIG_PHYTEC_SOM_DETECTION) + int ret; + + ret = phytec_eeprom_data_setup(NULL, 0, EEPROM_ADDR); + if (!ret) { + ret = phytec_imx8m_detect(NULL); + if (!ret) + phytec_print_som_info(NULL); + } +#endif + + ddr_init(&dram_timing); +} + +#define I2C_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_HYS | PAD_CTL_PUE | PAD_CTL_PE) +#define PC MUX_PAD_CTRL(I2C_PAD_CTRL) +struct i2c_pads_info i2c_pad_info1 = { + .scl = { + .i2c_mode = MX8MP_PAD_I2C1_SCL__I2C1_SCL | PC, + .gpio_mode = MX8MP_PAD_I2C1_SCL__GPIO5_IO14 | PC, + .gp = IMX_GPIO_NR(5, 14), + }, + .sda = { + .i2c_mode = MX8MP_PAD_I2C1_SDA__I2C1_SDA | PC, + .gpio_mode = MX8MP_PAD_I2C1_SDA__GPIO5_IO15 | PC, + .gp = IMX_GPIO_NR(5, 15), + }, +}; + +int power_init_board(void) +{ + struct pmic *p; + int ret; + + ret = power_pca9450_init(0, 0x25); + if (ret) + printf("power init failed"); + p = pmic_get("PCA9450"); + pmic_probe(p); + + /* BUCKxOUT_DVS0/1 control BUCK123 output */ + pmic_reg_write(p, PCA9450_BUCK123_DVS, 0x29); + + /* Increase VDD_SOC and VDD_ARM to OD voltage 0.95V */ + pmic_reg_write(p, PCA9450_BUCK1OUT_DVS0, 0x1C); + pmic_reg_write(p, PCA9450_BUCK2OUT_DVS0, 0x1C); + + /* Set BUCK1 DVS1 to suspend controlled through PMIC_STBY_REQ */ + pmic_reg_write(p, PCA9450_BUCK1OUT_DVS1, 0x14); + pmic_reg_write(p, PCA9450_BUCK1CTRL, 0x59); + + /* Set WDOG_B_CFG to cold reset */ + pmic_reg_write(p, PCA9450_RESET_CTRL, 0xA1); + + return 0; +} + +void spl_board_init(void) +{ + arch_misc_init(); + + /* Set GIC clock to 500Mhz for OD VDD_SOC. */ + clock_enable(CCGR_GIC, 0); + clock_set_target_val(GIC_CLK_ROOT, CLK_ROOT_ON | CLK_ROOT_SOURCE_SEL(5)); + clock_enable(CCGR_GIC, 1); +} + +int board_fit_config_name_match(const char *name) +{ + return 0; +} + +void board_init_f(ulong dummy) +{ + int ret; + + arch_cpu_init(); + + ret = spl_early_init(); + if (ret) { + debug("spl_early_init() failed: %d\n", ret); + hang(); + } + + preloader_console_init(); + + enable_tzc380(); + + setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1); + + power_init_board(); + + /* DDR initialization */ + spl_dram_init(); +} diff --git a/configs/imx8mp-libra-fpsc_defconfig b/configs/imx8mp-libra-fpsc_defconfig new file mode 100644 index 00000000000..a23e604425d --- /dev/null +++ b/configs/imx8mp-libra-fpsc_defconfig @@ -0,0 +1,175 @@ +CONFIG_ARM=y +CONFIG_ARCH_IMX8M=y +CONFIG_TEXT_BASE=0x40200000 +CONFIG_SYS_MALLOC_LEN=0x2000000 +CONFIG_SPL_GPIO=y +CONFIG_SPL_LIBCOMMON_SUPPORT=y +CONFIG_SPL_LIBGENERIC_SUPPORT=y +CONFIG_SF_DEFAULT_SPEED=80000000 +CONFIG_ENV_SIZE=0x10000 +CONFIG_ENV_OFFSET=0x3C0000 +CONFIG_ENV_SECT_SIZE=0x10000 +CONFIG_SYS_I2C_MXC_I2C1=y +CONFIG_DM_GPIO=y +CONFIG_DEFAULT_DEVICE_TREE="freescale/imx8mp-libra-rdk-fpsc" +CONFIG_IMX8M_OPTEE_LOAD_ADDR=0x7e000000 +CONFIG_TARGET_IMX8MP_LIBRA_FPSC=y +CONFIG_OF_LIBFDT_OVERLAY=y +CONFIG_SYS_MONITOR_LEN=524288 +CONFIG_SPL_MMC=y +CONFIG_SPL_SERIAL=y +CONFIG_SPL_DRIVERS_MISC=y +CONFIG_SPL_STACK=0x960000 +CONFIG_SPL_TEXT_BASE=0x920000 +CONFIG_SPL_HAS_BSS_LINKER_SECTION=y +CONFIG_SPL_BSS_START_ADDR=0x98fc00 +CONFIG_SPL_BSS_MAX_SIZE=0x400 +CONFIG_SYS_LOAD_ADDR=0x47602000 +CONFIG_SPL=y +CONFIG_ENV_OFFSET_REDUND=0x3e0000 +CONFIG_IMX_BOOTAUX=y +CONFIG_SPL_IMX_ROMAPI_LOADADDR=0x48000000 +# CONFIG_ANDROID_BOOT_IMAGE is not set +CONFIG_FIT=y +CONFIG_FIT_EXTERNAL_OFFSET=0x3000 +CONFIG_SPL_LOAD_FIT=y +CONFIG_BOOTSTD_FULL=y +CONFIG_OF_SYSTEM_SETUP=y +CONFIG_FDT_FIXUP_PARTITIONS=y +CONFIG_DEFAULT_FDT_FILE="imx8mp-libra-rdk-fpsc.dtb" +CONFIG_SYS_CBSIZE=2048 +CONFIG_SYS_PBSIZE=2074 +CONFIG_BOARD_LATE_INIT=y +CONFIG_SPL_MAX_SIZE=0x26000 +CONFIG_SPL_BOARD_INIT=y +CONFIG_SPL_BOOTROM_SUPPORT=y +CONFIG_SPL_SYS_MALLOC_SIMPLE=y +# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set +CONFIG_SPL_HAVE_INIT_STACK=y +CONFIG_SPL_SYS_MALLOC=y +CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y +CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x42200000 +CONFIG_SPL_SYS_MALLOC_SIZE=0x80000 +CONFIG_SPL_SYS_MMCSD_RAW_MODE=y +CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x300 +CONFIG_SPL_I2C=y +CONFIG_SPL_NOR_SUPPORT=y +CONFIG_SPL_POWER=y +CONFIG_SPL_WATCHDOG=y +CONFIG_SYS_PROMPT="u-boot=> " +CONFIG_CMD_ERASEENV=y +CONFIG_CMD_EEPROM=y +CONFIG_SYS_I2C_EEPROM_ADDR_LEN=2 +CONFIG_SYS_EEPROM_SIZE=4096 +CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=5 +CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5 +CONFIG_CMD_CLK=y +CONFIG_CMD_FUSE=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_MMC_REG=y +CONFIG_CMD_MTD=y +CONFIG_CMD_SF_TEST=y +CONFIG_CMD_USB=y +CONFIG_CMD_USB_SDP=y +CONFIG_CMD_USB_MASS_STORAGE=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_REGULATOR=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_MTDPARTS=y +CONFIG_OF_CONTROL=y +CONFIG_SPL_OF_CONTROL=y +CONFIG_ENV_OVERWRITE=y +CONFIG_ENV_IS_IN_MMC=y +CONFIG_ENV_IS_IN_SPI_FLASH=y +CONFIG_ENV_REDUNDANT=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_MMC_DEVICE_INDEX=2 +CONFIG_NET_RANDOM_ETHADDR=y +CONFIG_SPL_DM=y +CONFIG_CLK_COMPOSITE_CCF=y +CONFIG_SPL_CLK_IMX8MP=y +CONFIG_CLK_IMX8MP=y +CONFIG_FSL_CAAM=y +CONFIG_USB_FUNCTION_FASTBOOT=y +CONFIG_FASTBOOT_BUF_ADDR=0x42800000 +CONFIG_FASTBOOT_BUF_SIZE=0x13000000 +CONFIG_FASTBOOT_FLASH=y +CONFIG_FASTBOOT_UUU_SUPPORT=y +CONFIG_FASTBOOT_FLASH_MMC_DEV=2 +CONFIG_FASTBOOT_MMC_BOOT_SUPPORT=y +CONFIG_FASTBOOT_MMC_BOOT1_NAME="mmc2boot0" +CONFIG_FASTBOOT_MMC_BOOT2_NAME="mmc2boot1" +CONFIG_FASTBOOT_MMC_USER_SUPPORT=y +CONFIG_FASTBOOT_MMC_USER_NAME="mmc2" +CONFIG_MXC_GPIO=y +CONFIG_DM_I2C=y +# CONFIG_SPL_DM_I2C is not set +CONFIG_SPL_SYS_I2C_LEGACY=y +CONFIG_I2C_EEPROM=y +CONFIG_SYS_I2C_EEPROM_ADDR=0x51 +CONFIG_SUPPORT_EMMC_BOOT=y +CONFIG_MMC_IO_VOLTAGE=y +CONFIG_MMC_UHS_SUPPORT=y +CONFIG_MMC_HS400_ES_SUPPORT=y +CONFIG_MMC_HS400_SUPPORT=y +CONFIG_FSL_USDHC=y +CONFIG_MTD=y +CONFIG_DM_MTD=y +CONFIG_DM_SPI_FLASH=y +CONFIG_SPI_FLASH_BAR=y +CONFIG_SPI_FLASH_MACRONIX=y +CONFIG_SPI_FLASH_SPANSION=y +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_SPI_FLASH_SST=y +CONFIG_SPI_FLASH_WINBOND=y +# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set +CONFIG_SPI_FLASH_MTD=y +CONFIG_PHY_TI_DP83867=y +CONFIG_DM_ETH_PHY=y +CONFIG_PHY_GIGE=y +CONFIG_DWC_ETH_QOS=y +CONFIG_DWC_ETH_QOS_IMX=y +CONFIG_FEC_MXC=y +CONFIG_RGMII=y +CONFIG_MII=y +CONFIG_PHY_IMX8MQ_USB=y +CONFIG_PINCTRL=y +CONFIG_SPL_PINCTRL=y +CONFIG_PINCTRL_IMX8M=y +CONFIG_SPL_POWER_LEGACY=y +CONFIG_POWER_DOMAIN=y +CONFIG_IMX8M_POWER_DOMAIN=y +CONFIG_IMX8MP_HSIOMIX_BLKCTRL=y +CONFIG_POWER_PCA9450=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_SPL_POWER_I2C=y +CONFIG_DM_RNG=y +CONFIG_DM_SERIAL=y +CONFIG_MXC_UART=y +CONFIG_SPI=y +CONFIG_DM_SPI=y +CONFIG_NXP_FSPI=y +CONFIG_SYSRESET=y +CONFIG_SPL_SYSRESET=y +CONFIG_SYSRESET_PSCI=y +CONFIG_SYSRESET_WATCHDOG=y +CONFIG_TEE=y +CONFIG_OPTEE=y +CONFIG_DM_THERMAL=y +CONFIG_USB=y +CONFIG_DM_USB_GADGET=y +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_XHCI_DWC3=y +CONFIG_USB_XHCI_DWC3_OF_SIMPLE=y +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_DWC3=y +CONFIG_USB_DWC3_GENERIC=y +CONFIG_USB_GADGET=y +CONFIG_USB_GADGET_MANUFACTURER="PHYTEC" +CONFIG_USB_GADGET_VENDOR_NUM=0x0525 +CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 +CONFIG_IMX_WATCHDOG=y diff --git a/doc/board/phytec/imx8mp-libra-fpsc.rst b/doc/board/phytec/imx8mp-libra-fpsc.rst new file mode 100644 index 00000000000..26752ac1882 --- /dev/null +++ b/doc/board/phytec/imx8mp-libra-fpsc.rst @@ -0,0 +1,83 @@ +.. SPDX-License-Identifier: GPL-2.0+ + +Libra i.MX 8M Plus FPSC +======================= + +The Libra i.MX 8M Plus FPSC is a SBC based with the phyCORE-i.MX 8M Plus FPSC +SoM. +The phyCORE-i.MX 8M Plus FPSC with 2GB of main memory is supported. + +Quick Start +----------- + +- Build the ARM Trusted firmware binary +- Build the OP-TEE binary +- Get ddr firmware +- Build U-Boot +- Boot + +Build the ARM Trusted firmware binary +------------------------------------- + +.. code-block:: bash + + $ git clone https://git.trustedfirmware.org/TF-A/trusted-firmware-a.git + $ cd trusted-firmware-a + $ make -j $(nproc) \ + CROSS_COMPILE=aarch64-linux-gnu- \ + PLAT=imx8mp \ + IMX_BOOT_UART_BASE=0x30a60000 \ + BL32_BASE=0x7e000000 \ + SPD=opteed \ + bl31 + +Build the OP-TEE binary +----------------------- + +.. code-block:: bash + + $ git clone https://github.com/OP-TEE/optee_os.git + $ cd optee_os + $ make -j $(nproc) \ + CROSS_COMPILE=aarch64-linux-gnu- \ + CFG_TEE_BENCHMARK=n \ + O=out/arm \ + PLATFORM=imx-mx8mp_libra_fpsc + +Get the ddr firmware +-------------------- + +.. code-block:: bash + + $ wget https://www.nxp.com/lgfiles/NMG/MAD/YOCTO/firmware-imx-8.28-994fa14.bin + $ chmod +x firmware-imx-8.28-994fa14.bin + $ ./firmware-imx-8.28-994fa14.bin + +Build U-Boot for SD card +------------------------ + +Copy binaries +^^^^^^^^^^^^^ + +.. code-block:: bash + + $ cp /build/imx8mp/release/bl31.bin . + $ cp /out/arm/core/tee-raw.bin tee.bin + $ cp firmware-imx-8.28-994fa14/firmware/ddr/synopsys/lpddr4*.bin . + +Build U-Boot +^^^^^^^^^^^^ + +.. code-block:: bash + + $ make -j $(nproc) \ + CROSS_COMPILE=aarch64-linux-gnu- \ + imx8mp-libra-fpsc_defconfig \ + flash.bin + +Flash SD card +^^^^^^^^^^^^^ + +.. code-block:: bash + + $ sudo dd if=flash.bin of=/dev/sd[x] bs=1024 seek=32 conv=fsync diff --git a/doc/board/phytec/index.rst b/doc/board/phytec/index.rst index 1ae30c2dcd5..e24040a496e 100644 --- a/doc/board/phytec/index.rst +++ b/doc/board/phytec/index.rst @@ -6,6 +6,7 @@ PHYTEC .. toctree:: :maxdepth: 2 + imx8mp-libra-fpsc imx8mm-phygate-tauri-l imx93-phycore phycore-am62x diff --git a/include/configs/imx8mp-libra-fpsc.h b/include/configs/imx8mp-libra-fpsc.h new file mode 100644 index 00000000000..cde91dc3642 --- /dev/null +++ b/include/configs/imx8mp-libra-fpsc.h @@ -0,0 +1,27 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later + * + * Copyright (C) 2025 PHYTEC Messtechnik GmbH + */ + +#ifndef __IMX8MP_LIBRA_FPSC_H +#define __IMX8MP_LIBRA_FPSC_H + +#include +#include + +#define CFG_SYS_UBOOT_BASE \ + (QSPI0_AMBA_BASE + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512) + +/* Link Definitions */ + +#define CFG_SYS_INIT_RAM_ADDR 0x40000000 +#define CFG_SYS_INIT_RAM_SIZE SZ_512K + +#define CFG_SYS_SDRAM_BASE 0x40000000 + +#define PHYS_SDRAM 0x40000000 +#define PHYS_SDRAM_SIZE (SZ_2G + SZ_1G) /* 3GB */ +#define PHYS_SDRAM_2 0x100000000 +#define PHYS_SDRAM_2_SIZE (SZ_4G + SZ_1G) /* 5GB */ + +#endif /* __IMX8MP_LIBRA_FPSC_H */ -- cgit v1.2.3 From e0f9a4fb576c3f4233393194161e48941823cbc3 Mon Sep 17 00:00:00 2001 From: Ben Hoelker Date: Mon, 18 Aug 2025 10:30:00 +1200 Subject: drivers: rtc: max313xx: Add delay after setting date The MAX31331 was not correctly updating the seconds when setting the time and would return the seconds previously set. Like the MAX31343, a delay needs to be added after setting the time. Wait one second after writing so that the date command shows the correct time. Reviewed-by: Chris Packham Reviewed-by: Bruce Adams Signed-off-by: Ben Hoelker --- drivers/rtc/max313xx.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/rtc/max313xx.c b/drivers/rtc/max313xx.c index 2cb3f245041..f0d38b10c97 100644 --- a/drivers/rtc/max313xx.c +++ b/drivers/rtc/max313xx.c @@ -308,6 +308,7 @@ static int max313xx_set_time(struct udevice *dev, const struct rtc_time *t) return ret; break; + case ID_MAX31331: case ID_MAX31343: /* Time is not updated for 1 second after writing */ /* Sleep here so the date command shows the new time */ -- cgit v1.2.3 From a3f0a8e7a1be4843363967e63d8e5c7b725ce2fc Mon Sep 17 00:00:00 2001 From: Alif Zakuan Yuslaimi Date: Sun, 17 Aug 2025 19:55:02 -0700 Subject: misc: fs_loader: Initialize actread variable Initialize the actread variable to prevent undefined behavior that can occur if the variable is used before being assigned a value. This will help to prevent potential issues, especially if actread is used (e.g., read, incremented, or returned) before being explicitly set elsewhere in the code. Signed-off-by: Alif Zakuan Yuslaimi --- drivers/misc/fs_loader.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/misc/fs_loader.c b/drivers/misc/fs_loader.c index 60296d55f23..1fdfd8636e0 100644 --- a/drivers/misc/fs_loader.c +++ b/drivers/misc/fs_loader.c @@ -148,7 +148,7 @@ static int _request_firmware_prepare(struct udevice *dev, */ static int fw_get_filesystem_firmware(struct udevice *dev) { - loff_t actread; + loff_t actread = 0; char *storage_interface, *dev_part, *ubi_mtdpart, *ubi_volume; int ret; -- cgit v1.2.3 From aff7f1314a14ab2af5dbb04a33744c1c4db5aef7 Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Mon, 18 Aug 2025 10:51:19 -0600 Subject: boot: Add LEGACY_IMAGE_FORMAT to DISTRO_DEFAULTS At this time there are still major Linux distributions which by default boot using LEGACY_IMAGE_FORMAT type scripts. Add this option to DISTRO_DEFAULTS to ensure these platforms can still boot. Fixes: d780965927d4 ("Drop the special am335x_boneblack_vboot target") Reported-by: Sascha Silbe Tested-By: Sascha Silbe Signed-off-by: Tom Rini --- boot/Kconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/boot/Kconfig b/boot/Kconfig index 2993cd7f9ba..124f6db3e6e 100644 --- a/boot/Kconfig +++ b/boot/Kconfig @@ -1162,6 +1162,7 @@ config DISTRO_DEFAULTS select CMD_SYSBOOT select HUSH_PARSER select SYS_LONGHELP + select LEGACY_IMAGE_FORMAT help Note: These scripts have been replaced by Standard Boot. Do not use them on new boards. See 'Migrating from distro_boot' at -- cgit v1.2.3 From 122c25c00a238b55ac6745eb961c5ea66b45be8c Mon Sep 17 00:00:00 2001 From: Rasmus Villemoes Date: Tue, 19 Aug 2025 12:55:54 +0200 Subject: common/spl: use memmove() in load_simple_fit() I had trouble booting some am335x boards (both beagleboneblack and a custom board). SPL would start just fine, and apparently load U-Boot proper, but it would hang when jumping to U-Boot. While debugging, I stumbled on this memcpy() which from code inspection very much looked to have overlapping src and dst, and indeed a simple printf revealed calling memcpy(0x8087bf68, 0x8087bf80, 0xf7f8) Now, it will always be with src > dst, our memcpy() implementations "most likely" do forward-copying, and in the end it turned out that this wasn't the culprit after all [*]. But to avoid me or others barking up the wrong tree in the future, and because this use of memcpy() is technically undefined, use memmove() instead. [*] That was 358d1cc232c ("spl: Align FDT load address"), which has since been fixed in master but not the v2025.07 I worked of by 52caad0d14a ("ARM: Align image end to 8 bytes to fit DT alignment"). Signed-off-by: Rasmus Villemoes Reviewed-by: Heinrich Schuchardt --- common/spl/spl_fit.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/common/spl/spl_fit.c b/common/spl/spl_fit.c index 25f3c822a49..746c3d2fa28 100644 --- a/common/spl/spl_fit.c +++ b/common/spl/spl_fit.c @@ -353,7 +353,7 @@ static int load_simple_fit(struct spl_load_info *info, ulong fit_offset, } length = loadEnd - CONFIG_SYS_LOAD_ADDR; } else { - memcpy(load_ptr, src, length); + memmove(load_ptr, src, length); } if (image_info) { -- cgit v1.2.3 From ae84ef8c625f6454747b5d13192e1a16649761b2 Mon Sep 17 00:00:00 2001 From: Jan Kiszka Date: Sat, 23 Aug 2025 13:29:49 +0200 Subject: tools: Drop meaningless comment from Makefile Introduced by 245b1029e1af, probably a debug left-over. Signed-off-by: Jan Kiszka Reviewed-by: Heiko Schocher --- tools/Makefile | 1 - 1 file changed, 1 deletion(-) diff --git a/tools/Makefile b/tools/Makefile index 02297e8c93a..7eb17f92116 100644 --- a/tools/Makefile +++ b/tools/Makefile @@ -344,7 +344,6 @@ $(LOGO_DATA_H): $(obj)/bmp_logo $(LOGO_BMP) else $(LOGO_DATA_H): $(obj)/bmp_logo $(LOGO_BMP) $(obj)/bmp_logo --gen-data $(LOGO_BMP) > $@ -#endif endif # Let clean descend into subdirs -- cgit v1.2.3 From a5b483a52a5561030ab3e50923a215fbed49d006 Mon Sep 17 00:00:00 2001 From: Mark Kettenis Date: Sat, 23 Aug 2025 16:03:56 +0200 Subject: pci: apple: Fix use of uninitialized variable Replace use of uninitialized variable with the PCI device number in an error message as this is what we use elsewhere to derive the PCIe port number. Use ofnode_read_pci_addr() to read the PCI address of the node and derive the device number from that. Signed-off-by: Mark Kettenis Reported-by: Andrew Goodbody --- drivers/pci/pcie_apple.c | 18 +++++++++++++----- 1 file changed, 13 insertions(+), 5 deletions(-) diff --git a/drivers/pci/pcie_apple.c b/drivers/pci/pcie_apple.c index 6a8e715d4b6..f5fda9835dc 100644 --- a/drivers/pci/pcie_apple.c +++ b/drivers/pci/pcie_apple.c @@ -246,8 +246,9 @@ static int apple_pcie_setup_port(struct apple_pcie_priv *pcie, ofnode np) { struct apple_pcie_port *port; struct gpio_desc reset; + struct fdt_pci_addr pci_addr; fdt_addr_t addr; - u32 stat, idx; + u32 stat; int ret; char name[16]; @@ -259,12 +260,13 @@ static int apple_pcie_setup_port(struct apple_pcie_priv *pcie, ofnode np) if (!port) return -ENOMEM; - ret = ofnode_read_u32_index(np, "reg", 0, &idx); + ret = ofnode_read_pci_addr(np, FDT_PCI_SPACE_CONFIG, "reg", + &pci_addr, NULL); if (ret) return ret; /* Use the first reg entry to work out the port index */ - port->idx = idx >> 11; + port->idx = PCI_DEV(pci_addr.phys_hi); port->pcie = pcie; port->reset = reset; port->np = np; @@ -333,9 +335,10 @@ static int apple_pcie_setup_port(struct apple_pcie_priv *pcie, ofnode np) static int apple_pcie_probe(struct udevice *dev) { struct apple_pcie_priv *pcie = dev_get_priv(dev); + struct fdt_pci_addr pci_addr; fdt_addr_t addr; ofnode of_port; - int i, ret; + int ret; pcie->hw = (struct reg_info *)dev_get_driver_data(dev); @@ -357,9 +360,14 @@ static int apple_pcie_probe(struct udevice *dev) of_port = ofnode_next_subnode(of_port)) { if (!ofnode_is_enabled(of_port)) continue; + ret = ofnode_read_pci_addr(of_port, FDT_PCI_SPACE_CONFIG, + "reg", &pci_addr, NULL); + if (ret) + continue; ret = apple_pcie_setup_port(pcie, of_port); if (ret) { - dev_err(pcie->dev, "Port %d setup fail: %d\n", i, ret); + dev_err(pcie->dev, "Port %d setup fail: %d\n", + PCI_DEV(pci_addr.phys_hi), ret); return ret; } } -- cgit v1.2.3 From 5d01a971804e3f7f7d320870acf5418bd8497535 Mon Sep 17 00:00:00 2001 From: Ilias Apalodimas Date: Tue, 2 Sep 2025 09:08:12 +0300 Subject: arm64: Properly clear BSS Brock reports a breakage on an RK3568 SoC. His patch is correct but he never followed up on the requested changes. We currently use ldr to calculate the address of __bss_start and __bss_end. However the absolute addresses of the literal pool are never relocated and we end up clearing the wrong memory section. Use PC-relative addressing instead. Link: https://lore.kernel.org/u-boot/zfknlzcemnnaka5w2er5wjwefwoidrpndc4gjhx6d5xr6nlcjr@pasfayjiutii/ Suggested-by: brock_zheng Reported-by: brock_zheng Signed-off-by: Ilias Apalodimas --- arch/arm/lib/crt0_64.S | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/arch/arm/lib/crt0_64.S b/arch/arm/lib/crt0_64.S index f3f279f2c39..3e7627aa389 100644 --- a/arch/arm/lib/crt0_64.S +++ b/arch/arm/lib/crt0_64.S @@ -158,8 +158,10 @@ relocation_return: /* * Clear BSS section */ - ldr x0, =__bss_start /* this is auto-relocated! */ - ldr x1, =__bss_end /* this is auto-relocated! */ + adrp x0, __bss_start + add x0, x0, #:lo12:__bss_start + adrp x1, __bss_end + add x1, x1, #:lo12:__bss_end clear_loop: str xzr, [x0], #8 cmp x0, x1 -- cgit v1.2.3 From c9d4e82670ec4e4bab5681710de4240a3fb42fe8 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Wed, 3 Sep 2025 16:22:26 +0200 Subject: env: Fix up indent Replace #define with #define to be consistent in the entire file. No functional change. Signed-off-by: Marek Vasut Reviewed-by: Tom Rini --- include/env_default.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/include/env_default.h b/include/env_default.h index 9caf22cdd1d..ae2cfbcbc45 100644 --- a/include/env_default.h +++ b/include/env_default.h @@ -79,10 +79,10 @@ const char default_environment[] = { #ifdef CONFIG_USE_BOOTFILE "bootfile=" CONFIG_BOOTFILE "\0" #endif -#ifdef CONFIG_SYS_LOAD_ADDR +#ifdef CONFIG_SYS_LOAD_ADDR "loadaddr=" __stringify(CONFIG_SYS_LOAD_ADDR)"\0" #endif -#ifdef CONFIG_ENV_VARS_UBOOT_CONFIG +#ifdef CONFIG_ENV_VARS_UBOOT_CONFIG "arch=" CONFIG_SYS_ARCH "\0" #ifdef CONFIG_SYS_CPU "cpu=" CONFIG_SYS_CPU "\0" -- cgit v1.2.3 From 3c34fd46b6efd0501662ba3f0aeff2aeac9a584d Mon Sep 17 00:00:00 2001 From: Ilias Apalodimas Date: Fri, 29 Aug 2025 11:16:15 +0300 Subject: tools: fdtgrep: Mark util_version() as static The function is only used locally. Enabling -Wmissing-prototypes triggers a warning. Mark it as static. Signed-off-by: Ilias Apalodimas --- tools/fdtgrep.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/tools/fdtgrep.c b/tools/fdtgrep.c index 037176bc9ef..6372defedc2 100644 --- a/tools/fdtgrep.c +++ b/tools/fdtgrep.c @@ -1109,7 +1109,7 @@ void util_usage(const char *errmsg, const char *synopsis, util_usage(errmsg, usage_synopsis, usage_short_opts, \ usage_long_opts, usage_opts_help) -void util_version(void) +static void util_version(void) { printf("Version: %s\n", "(U-Boot)"); exit(0); -- cgit v1.2.3 From 9fe4e088f3d2ba15323ae4bff7f6b592152e326c Mon Sep 17 00:00:00 2001 From: Ilias Apalodimas Date: Fri, 29 Aug 2025 11:16:16 +0300 Subject: tools: fdtgrep: Mark util_usage() as static The function is only used locally. Enabling -Wmissing-prototypes triggers a warning. Mark it as static. Signed-off-by: Ilias Apalodimas --- tools/fdtgrep.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/tools/fdtgrep.c b/tools/fdtgrep.c index 6372defedc2..b4c041070f5 100644 --- a/tools/fdtgrep.c +++ b/tools/fdtgrep.c @@ -1040,7 +1040,7 @@ static const char * const usage_opts_help[] = { #define util_getopt_long() getopt_long(argc, argv, usage_short_opts, \ usage_long_opts, NULL) -void util_usage(const char *errmsg, const char *synopsis, +static void util_usage(const char *errmsg, const char *synopsis, const char *short_opts, struct option const long_opts[], const char * const opts_help[]) { -- cgit v1.2.3 From 867d762bc515850b00245cbcf21cf2b2d39a2a5d Mon Sep 17 00:00:00 2001 From: Ilias Apalodimas Date: Fri, 29 Aug 2025 11:16:17 +0300 Subject: tools: mkimage: Mark copy_datafile() as static The function is only used locally. Enabling -Wmissing-prototypes triggers a warning. Mark it as static. Signed-off-by: Ilias Apalodimas --- tools/mkimage.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/tools/mkimage.c b/tools/mkimage.c index 361711c53b2..847453970ab 100644 --- a/tools/mkimage.c +++ b/tools/mkimage.c @@ -445,7 +445,7 @@ static void verify_image(const struct image_type_params *tparams) (void)close(ifd); } -void copy_datafile(int ifd, char *file) +static void copy_datafile(int ifd, char *file) { if (!file) return; -- cgit v1.2.3 From 3ae031135da1f21ec22e20fac5d7ba9776487166 Mon Sep 17 00:00:00 2001 From: Ilias Apalodimas Date: Fri, 29 Aug 2025 11:16:18 +0300 Subject: tools: rkcommon: Mark rkcommon_is_header_v2() as static The function is only used locally. Enabling -Wmissing-prototypes triggers a warning. Mark it as static. Signed-off-by: Ilias Apalodimas Reviewed-by: Quentin Schulz --- tools/rkcommon.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/tools/rkcommon.c b/tools/rkcommon.c index a0caa029cc0..d191ea72c63 100644 --- a/tools/rkcommon.c +++ b/tools/rkcommon.c @@ -279,7 +279,7 @@ bool rkcommon_need_rc4_spl(struct image_tool_params *params) return info->spl_rc4; } -bool rkcommon_is_header_v2(struct image_tool_params *params) +static bool rkcommon_is_header_v2(struct image_tool_params *params) { struct spl_info *info = rkcommon_get_spl_info(params->imagename); -- cgit v1.2.3 From 5ab15814e8f051968a4da8c96339ff0c80c5f811 Mon Sep 17 00:00:00 2001 From: Ilias Apalodimas Date: Fri, 29 Aug 2025 11:16:19 +0300 Subject: tool: fit_info: Mark usage() as static The function is only used locally. Enabling -Wmissing-prototypes triggers a warning. Mark it as static. Signed-off-by: Ilias Apalodimas --- tools/fit_info.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/tools/fit_info.c b/tools/fit_info.c index b2642ec5b76..c9e4236d09f 100644 --- a/tools/fit_info.c +++ b/tools/fit_info.c @@ -26,7 +26,7 @@ #include #include -void usage(char *cmdname) +static void usage(char *cmdname) { fprintf(stderr, "Usage: %s -f fit file -n node -p property\n" " -f ==> set fit file which is used'\n" -- cgit v1.2.3 From 39f7af39bb2e7e03ea4621e57a976d41dcaaf0a6 Mon Sep 17 00:00:00 2001 From: Ilias Apalodimas Date: Fri, 29 Aug 2025 11:16:20 +0300 Subject: tools: fit_check_sign: Mark usage() as static The function is only used locally. Enabling -Wmissing-prototypes triggers a warning. Mark it as static. Signed-off-by: Ilias Apalodimas --- tools/fit_check_sign.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/tools/fit_check_sign.c b/tools/fit_check_sign.c index 32d0fdb8829..ab3266aff20 100644 --- a/tools/fit_check_sign.c +++ b/tools/fit_check_sign.c @@ -23,7 +23,7 @@ #include #include -void usage(char *cmdname) +static void usage(char *cmdname) { fprintf(stderr, "Usage: %s -f fit file -k key file -c config name\n" " -f ==> set fit file which should be checked'\n" -- cgit v1.2.3 From f006837eada06cdf41b9935eb6c73618e4ae0bf0 Mon Sep 17 00:00:00 2001 From: Ilias Apalodimas Date: Fri, 29 Aug 2025 11:16:21 +0300 Subject: tools: imx8mimage: Mark build_image() as static The function is only used locally. Enabling -Wmissing-prototypes triggers a warning. Mark it as static. Signed-off-by: Ilias Apalodimas --- tools/imx8mimage.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/tools/imx8mimage.c b/tools/imx8mimage.c index 0f24ba75c0f..fe1aff35b4d 100644 --- a/tools/imx8mimage.c +++ b/tools/imx8mimage.c @@ -475,7 +475,7 @@ static int generate_fspi_header (int ifd) } #endif -void build_image(int ofd) +static void build_image(int ofd) { int file_off, header_hdmi_off = 0, header_image_off; -- cgit v1.2.3 From 1e73651a71d1cf2a718b9a8250a794d626b9eecb Mon Sep 17 00:00:00 2001 From: Ilias Apalodimas Date: Fri, 29 Aug 2025 11:16:22 +0300 Subject: tools: imx8image: Mark imx8mimage_check_params() as static The function is only used locally. Enabling -Wmissing-prototypes triggers a warning. Mark it as static. Signed-off-by: Ilias Apalodimas --- tools/imx8mimage.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/tools/imx8mimage.c b/tools/imx8mimage.c index fe1aff35b4d..3e974923652 100644 --- a/tools/imx8mimage.c +++ b/tools/imx8mimage.c @@ -49,7 +49,7 @@ static uint32_t get_cfg_value(char *token, char *name, int linenr) return value; } -int imx8mimage_check_params(struct image_tool_params *params) +static int imx8mimage_check_params(struct image_tool_params *params) { return 0; } -- cgit v1.2.3 From 371a76e845504c9ba7ca216b6edfb4ae4ec14e56 Mon Sep 17 00:00:00 2001 From: Jan Kiszka Date: Sat, 23 Aug 2025 17:21:09 +0200 Subject: tools: Do not generate logo when cross-building This cannot work (unless qemu-user is registered in binfmt_misc) as the tools will be for a different architecture. Fixes "make cross_tools" in case CONFIG_VIDEO_LOGO is enabled. Signed-off-by: Jan Kiszka Reviewed-by: Tom Rini --- tools/Makefile | 2 ++ 1 file changed, 2 insertions(+) diff --git a/tools/Makefile b/tools/Makefile index 7eb17f92116..ae6a3052646 100644 --- a/tools/Makefile +++ b/tools/Makefile @@ -333,7 +333,9 @@ HOST_EXTRACFLAGS += -include $(srctree)/include/compiler.h \ -D__KERNEL_STRICT_NAMES \ -D_GNU_SOURCE +ifeq ($(CROSS_BUILD_TOOLS),) __build: $(LOGO-y) +endif $(LOGO_H): $(obj)/bmp_logo $(LOGO_BMP) $(obj)/bmp_logo --gen-info $(LOGO_BMP) > $@ -- cgit v1.2.3 From 1f8fd9d37d69ecc269943a273d3bca4c1be2384e Mon Sep 17 00:00:00 2001 From: Tony Dinh Date: Tue, 26 Aug 2025 12:37:17 -0700 Subject: fs: ext4fs: Add initialization failure recovery path in ext4fs_write Don't invoke ext4fs_deinit() in ext4fs_write() if the failure occurs during initialization. It would result in a crash since ext4fs_init() has already done that. Signed-off-by: Tony Dinh Reviewed-by: Tom Rini --- fs/ext4/ext4_write.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/fs/ext4/ext4_write.c b/fs/ext4/ext4_write.c index dd8ed40f888..5b290f0d80d 100644 --- a/fs/ext4/ext4_write.c +++ b/fs/ext4/ext4_write.c @@ -877,7 +877,8 @@ int ext4fs_write(const char *fname, const char *buffer, if (ext4fs_init() != 0) { printf("error in File System init\n"); - goto fail; + /* Skip ext4fs_deinit since ext4fs_init() already done that */ + goto fail_init; } missing_feat = le32_to_cpu(fs->sb->feature_incompat) & ~EXT4_FEATURE_INCOMPAT_SUPP; @@ -1050,6 +1051,7 @@ int ext4fs_write(const char *fname, const char *buffer, return 0; fail: ext4fs_deinit(); +fail_init: free(inode_buffer); free(g_parent_inode); free(temp_ptr); -- cgit v1.2.3 From 8c599da5060c2bb4c085a7d92794c8134f61ef25 Mon Sep 17 00:00:00 2001 From: Tony Dinh Date: Tue, 26 Aug 2025 12:45:37 -0700 Subject: fs: ext4fs: add CONFIG_EXT4_MAX_JOURNAL_ENTRIES to Kconfig Add maximum ext4 journal entries to Kconfig. It is necessary since the number of journal entries is proportional to disk capacity. For example, an ext4 4TB HDD partition could require approximately 500 entries. Signed-off-by: Tony Dinh Reviewed-by: Tom Rini --- fs/ext4/Kconfig | 8 ++++++++ fs/ext4/ext4_journal.h | 2 +- 2 files changed, 9 insertions(+), 1 deletion(-) diff --git a/fs/ext4/Kconfig b/fs/ext4/Kconfig index 8ddaebebd48..a2faa9f878a 100644 --- a/fs/ext4/Kconfig +++ b/fs/ext4/Kconfig @@ -12,3 +12,11 @@ config EXT4_WRITE help This provides support for creating and writing new files to an existing ext4 filesystem partition. + +config EXT4_MAX_JOURNAL_ENTRIES + int "Maximum numbers of journal entries for ext4 filesystem" + default 100 + depends on EXT4_WRITE + help + This provides support for allocating the maximum number of + journal entries in disks formatted with ext4 filesysyem. diff --git a/fs/ext4/ext4_journal.h b/fs/ext4/ext4_journal.h index 43fb8e76641..a492df49fbe 100644 --- a/fs/ext4/ext4_journal.h +++ b/fs/ext4/ext4_journal.h @@ -38,7 +38,7 @@ #define EXT3_JOURNAL_FLAG_LAST_TAG 8 /* Maximum entries in 1 journal transaction */ -#define MAX_JOURNAL_ENTRIES 100 +#define MAX_JOURNAL_ENTRIES CONFIG_EXT4_MAX_JOURNAL_ENTRIES struct journal_log { char *buf; int blknr; -- cgit v1.2.3 From 320d1d04eb52d5bf450e93a91788c2dcc9594de3 Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Wed, 27 Aug 2025 12:38:36 -0600 Subject: checkpatch.pl: Ignore mdelay instead of udelay Whereas in Linux, on ARM there is the notion of delay operations and mdelay and udelay are not the same, here we just have udelay and mdelay is a trivial wrapper. Tell checkpatch to not complain here. Reported-by: Bhimeswararao Matsa Signed-off-by: Tom Rini --- .checkpatch.conf | 3 +++ 1 file changed, 3 insertions(+) diff --git a/.checkpatch.conf b/.checkpatch.conf index c368d414726..0827f347f6e 100644 --- a/.checkpatch.conf +++ b/.checkpatch.conf @@ -19,6 +19,9 @@ # Not Linux, so we don't recommend usleep_range() over udelay() --ignore USLEEP_RANGE +# We also do not have a functionally different mdelay() and udelay() +--ignore LONG_UDELAY + # Ignore networking block comment style --ignore NETWORKING_BLOCK_COMMENT_STYLE -- cgit v1.2.3 From 5964c6f4ef0934130f41c347c771dfb97210490c Mon Sep 17 00:00:00 2001 From: Bhimeswararao Matsa Date: Fri, 29 Aug 2025 07:41:29 +0530 Subject: i2c: davinci: prefer kernel types (u8/u32) Replace uint8_t/uint32_t with u8/u32 to match U-Boot style (checkpatch PREFER_KERNEL_TYPES). No functional change. Signed-off-by: Bhimeswararao Matsa --- drivers/i2c/davinci_i2c.c | 17 +++++++++-------- 1 file changed, 9 insertions(+), 8 deletions(-) diff --git a/drivers/i2c/davinci_i2c.c b/drivers/i2c/davinci_i2c.c index 39132747208..9bba0600e3e 100644 --- a/drivers/i2c/davinci_i2c.c +++ b/drivers/i2c/davinci_i2c.c @@ -19,6 +19,7 @@ #include #include #include +#include #include "davinci_i2c.h" /* Information about i2c controller */ @@ -87,7 +88,7 @@ static void _flush_rx(struct i2c_regs *i2c_base) static uint _davinci_i2c_setspeed(struct i2c_regs *i2c_base, uint speed) { - uint32_t div, psc; + u32 div, psc; psc = 2; /* SCLL + SCLH */ @@ -122,10 +123,10 @@ static void _davinci_i2c_init(struct i2c_regs *i2c_base, udelay(1000); } -static int _davinci_i2c_read(struct i2c_regs *i2c_base, uint8_t chip, - uint32_t addr, int alen, uint8_t *buf, int len) +static int _davinci_i2c_read(struct i2c_regs *i2c_base, u8 chip, + u32 addr, int alen, u8 *buf, int len) { - uint32_t tmp; + u32 tmp; int i; if ((alen < 0) || (alen > 2)) { @@ -220,10 +221,10 @@ static int _davinci_i2c_read(struct i2c_regs *i2c_base, uint8_t chip, return 0; } -static int _davinci_i2c_write(struct i2c_regs *i2c_base, uint8_t chip, - uint32_t addr, int alen, uint8_t *buf, int len) +static int _davinci_i2c_write(struct i2c_regs *i2c_base, u8 chip, + u32 addr, int alen, u8 *buf, int len) { - uint32_t tmp; + u32 tmp; int i; if ((alen < 0) || (alen > 2)) { @@ -302,7 +303,7 @@ static int _davinci_i2c_write(struct i2c_regs *i2c_base, uint8_t chip, return 0; } -static int _davinci_i2c_probe_chip(struct i2c_regs *i2c_base, uint8_t chip) +static int _davinci_i2c_probe_chip(struct i2c_regs *i2c_base, u8 chip) { int rc = 1; -- cgit v1.2.3 From c85b8071e7d3fd333f8a2fdd28083cb5ec3a0645 Mon Sep 17 00:00:00 2001 From: Heinrich Schuchardt Date: Sat, 30 Aug 2025 22:39:54 +0200 Subject: virtio: blk: support block sizes exceeding 512 bytes QEMU allows to specify the logical block size via parameter logical_block_size of a virtio-blk-device. The communication channel via virtqueues remains based on 512 byte blocks even if the logical_block_size is larger. Consider the logical block size in the block device driver. Reported-by: Emil Renner Berthing Signed-off-by: Heinrich Schuchardt Tested-by: Emil Renner Berthing --- drivers/virtio/virtio_blk.c | 25 ++++++++++++++++++++++--- 1 file changed, 22 insertions(+), 3 deletions(-) diff --git a/drivers/virtio/virtio_blk.c b/drivers/virtio/virtio_blk.c index 2f999fc8bbe..4224e3c17f4 100644 --- a/drivers/virtio/virtio_blk.c +++ b/drivers/virtio/virtio_blk.c @@ -12,10 +12,17 @@ #include #include #include +#include #include "virtio_blk.h" +/** + * struct virtio_blk_priv - private date for virtio block device + */ struct virtio_blk_priv { + /** @virtqueue - virtqueue to process */ struct virtqueue *vq; + /** @blksz_shift - log2 of block size divided by 512 */ + u32 blksz_shift; }; static const u32 feature[] = { @@ -71,6 +78,8 @@ static ulong virtio_blk_do_req(struct udevice *dev, u64 sector, u8 status; int ret; + sector <<= priv->blksz_shift; + blkcnt <<= priv->blksz_shift; virtio_blk_init_header_sg(dev, sector, type, &out_hdr, &hdr_sg); sgs[num_out++] = &hdr_sg; @@ -109,7 +118,7 @@ static ulong virtio_blk_do_req(struct udevice *dev, u64 sector, ; log_debug("done\n"); - return status == VIRTIO_BLK_S_OK ? blkcnt : -EIO; + return status == VIRTIO_BLK_S_OK ? blkcnt >> priv->blksz_shift : -EIO; } static ulong virtio_blk_read(struct udevice *dev, lbaint_t start, @@ -177,15 +186,25 @@ static int virtio_blk_probe(struct udevice *dev) struct blk_desc *desc = dev_get_uclass_plat(dev); u64 cap; int ret; + u32 blk_size; ret = virtio_find_vqs(dev, 1, &priv->vq); if (ret) return ret; - desc->blksz = 512; - desc->log2blksz = 9; virtio_cread(dev, struct virtio_blk_config, capacity, &cap); desc->lba = cap; + if (!virtio_has_feature(dev, VIRTIO_BLK_F_BLK_SIZE)) { + virtio_cread(dev, struct virtio_blk_config, blk_size, &blk_size); + desc->blksz = blk_size; + if (!is_power_of_2(blk_size) || desc->blksz < 512) + return -EIO; + } else { + desc->blksz = 512; + } + desc->log2blksz = LOG2(desc->blksz); + priv->blksz_shift = desc->log2blksz - 9; + desc->lba >>= priv->blksz_shift; return 0; } -- cgit v1.2.3 From 6fd45dd488f9605e2f634c7e5da4ac2925c118c8 Mon Sep 17 00:00:00 2001 From: Judith Mendez Date: Wed, 20 Aug 2025 16:56:34 -0500 Subject: mach-k3: am62*: Fix backup from eMMC boot mode Currently logic in spl_mmc_boot_mode only lookes at main devstat to determine the bootmode to return. Thus, when using: 'eMMC boot' as primary boot mode and 'MMCSD boot from eMMC UDA' as backup boot mode, 'eMMC boot' is always selected. Add check for bootindex to determine if ROM boot via backup boot mode and return MMCSD_MODE_FS which is the only supported backup bootmode with eMMC device. Signed-off-by: Judith Mendez Reviewed-by: Anshul Dalal Reviewed-by: Moteen Shah --- arch/arm/mach-k3/am62ax/am62a7_init.c | 5 +++++ arch/arm/mach-k3/am62px/am62p5_init.c | 5 +++++ arch/arm/mach-k3/am62x/am625_init.c | 5 +++++ 3 files changed, 15 insertions(+) diff --git a/arch/arm/mach-k3/am62ax/am62a7_init.c b/arch/arm/mach-k3/am62ax/am62a7_init.c index 00173e6836b..48d578e7d6f 100644 --- a/arch/arm/mach-k3/am62ax/am62a7_init.c +++ b/arch/arm/mach-k3/am62ax/am62a7_init.c @@ -218,6 +218,11 @@ u32 spl_mmc_boot_mode(struct mmc *mmc, const u32 boot_device) u32 bootmode_cfg = (devstat & MAIN_DEVSTAT_PRIMARY_BOOTMODE_CFG_MASK) >> MAIN_DEVSTAT_PRIMARY_BOOTMODE_CFG_SHIFT; + if (bootindex != K3_PRIMARY_BOOTMODE) { + pr_alert("Fallback to backup bootmode MMCSD_MODE_FS\n"); + return MMCSD_MODE_FS; + } + switch (bootmode) { case BOOT_DEVICE_EMMC: if (IS_ENABLED(CONFIG_SUPPORT_EMMC_BOOT)) diff --git a/arch/arm/mach-k3/am62px/am62p5_init.c b/arch/arm/mach-k3/am62px/am62p5_init.c index 44a2d445d24..aebd5200b0d 100644 --- a/arch/arm/mach-k3/am62px/am62p5_init.c +++ b/arch/arm/mach-k3/am62px/am62p5_init.c @@ -264,6 +264,11 @@ u32 spl_mmc_boot_mode(struct mmc *mmc, const u32 boot_device) u32 bootmode_cfg = (devstat & MAIN_DEVSTAT_PRIMARY_BOOTMODE_CFG_MASK) >> MAIN_DEVSTAT_PRIMARY_BOOTMODE_CFG_SHIFT; + if (bootindex != K3_PRIMARY_BOOTMODE) { + pr_alert("Fallback to backup bootmode MMCSD_MODE_FS\n"); + return MMCSD_MODE_FS; + } + switch (bootmode) { case BOOT_DEVICE_EMMC: if (IS_ENABLED(CONFIG_SUPPORT_EMMC_BOOT)) diff --git a/arch/arm/mach-k3/am62x/am625_init.c b/arch/arm/mach-k3/am62x/am625_init.c index 8f4ddf59753..14f93ac998f 100644 --- a/arch/arm/mach-k3/am62x/am625_init.c +++ b/arch/arm/mach-k3/am62x/am625_init.c @@ -305,6 +305,11 @@ u32 spl_mmc_boot_mode(struct mmc *mmc, const u32 boot_device) u32 bootmode_cfg = (devstat & MAIN_DEVSTAT_PRIMARY_BOOTMODE_CFG_MASK) >> MAIN_DEVSTAT_PRIMARY_BOOTMODE_CFG_SHIFT; + if (bootindex != K3_PRIMARY_BOOTMODE) { + pr_alert("Fallback to backup bootmode MMCSD_MODE_FS\n"); + return MMCSD_MODE_FS; + } + switch (bootmode) { case BOOT_DEVICE_EMMC: if (IS_ENABLED(CONFIG_SUPPORT_EMMC_BOOT)) -- cgit v1.2.3 From e3e7d0d29aa1cb151650e4531c04dda613c374ac Mon Sep 17 00:00:00 2001 From: Udit Kumar Date: Sat, 23 Aug 2025 13:36:15 +0530 Subject: arm: mach-k3: increase max resasg_entries Increase max resasg_entries to accommodate max size of largest device J784S4. Link: https://software-dl.ti.com/tisci/esd/latest/5_soc_doc/j784s4/resasg_types.html Reported-by: Jared McArthur Signed-off-by: Udit Kumar --- arch/arm/mach-k3/schema.yaml | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm/mach-k3/schema.yaml b/arch/arm/mach-k3/schema.yaml index c8dd2e79e7d..8c4691f24ed 100644 --- a/arch/arm/mach-k3/schema.yaml +++ b/arch/arm/mach-k3/schema.yaml @@ -344,7 +344,7 @@ properties: resasg_entries: type: array minItems: 0 - maxItems: 468 + maxItems: 586 items: type: object properties: @@ -420,7 +420,7 @@ properties: resasg_entries: type: array minItems: 0 - maxItems: 468 + maxItems: 586 items: type: object properties: -- cgit v1.2.3 From 8633643769b5d5b30567b89a1c0fb00b8f2ac7b2 Mon Sep 17 00:00:00 2001 From: Judith Mendez Date: Mon, 25 Aug 2025 10:23:10 -0500 Subject: board: ti: am65x: Overwrite get_overlay_mmc Unlike other K3 SoC's, am65 SoC has the capability to detect daughter cards and automatically generate a list of white-space separated overlays in name_overlays environment variable. When applied during boot with get_overlay_mmc, the path to overlays with default distribution is incorrect where path is currently: boot/dtb and the overlays exist in boot/dtb/ti. Fix the path in get_overlay_mmc so that overlays are automatically applied correctly during boot time. Signed-off-by: Judith Mendez --- board/ti/am65x/am65x.env | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/board/ti/am65x/am65x.env b/board/ti/am65x/am65x.env index 631997e4c97..b6cdfc9bd96 100644 --- a/board/ti/am65x/am65x.env +++ b/board/ti/am65x/am65x.env @@ -17,6 +17,15 @@ bootpart=1:2 bootdir=/boot rd_spec=- +get_overlay_mmc= + fdt address ${fdtaddr}; + fdt resize 0x100000; + for overlay in $name_overlays; + do; + load mmc ${bootpart} ${dtboaddr} ${bootdir}/dtb/ti/${overlay} && + fdt apply ${dtboaddr}; + done; + init_ubi= run args_all args_ubi; sf probe; -- cgit v1.2.3 From 4d1caf58d22f8be26ded411d5774eaa6eaa3714f Mon Sep 17 00:00:00 2001 From: Bhimeswararao Matsa Date: Mon, 1 Sep 2025 20:09:45 +0530 Subject: board: ti: fdt_ops: make ti_set_fdt_env() const-correct Make the fdt_map parameter a pointer to const, since the function only reads the mapping table. This improves API correctness and allows maps to live in read-only data. No functional change intended Signed-off-by: Bhimeswararao Matsa --- board/ti/common/fdt_ops.c | 2 +- board/ti/common/fdt_ops.h | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/board/ti/common/fdt_ops.c b/board/ti/common/fdt_ops.c index 47df5726ff0..0486d2e7802 100644 --- a/board/ti/common/fdt_ops.c +++ b/board/ti/common/fdt_ops.c @@ -9,7 +9,7 @@ #include #include "fdt_ops.h" -void ti_set_fdt_env(const char *board_name, struct ti_fdt_map *fdt_map) +void ti_set_fdt_env(const char *board_name, const struct ti_fdt_map *fdt_map) { char *fdt_file_name = NULL; char fdtfile[TI_FDT_FILE_MAX]; diff --git a/board/ti/common/fdt_ops.h b/board/ti/common/fdt_ops.h index 5d304994fb6..5375303ba8e 100644 --- a/board/ti/common/fdt_ops.h +++ b/board/ti/common/fdt_ops.h @@ -37,6 +37,6 @@ struct ti_fdt_map { * @board_name: match to search with (max of TI_BOARD_NAME_MAX chars) * @fdt_map: NULL terminated array of device tree file name matches. */ -void ti_set_fdt_env(const char *board_name, struct ti_fdt_map *fdt_map); +void ti_set_fdt_env(const char *board_name, const struct ti_fdt_map *fdt_map); #endif /* __FDT_OPS_H */ -- cgit v1.2.3 From 49a3ad7a5e6aa9333c2685e98f6280ff4ae3650a Mon Sep 17 00:00:00 2001 From: Steffen Kothe Date: Sun, 31 Aug 2025 15:17:05 +0000 Subject: arm: mach-k3: am64_hardware.h: Add CTRLMMR_MCU_RST_SRC reset cause bit mappings AM64X SoCs use similar but not identical bit mappings like the AM62X family. In detail does the AM64X not support PORZ and WDT as reset caused. Add the mapping according to the technical reference manual into the SoC specific header. Signed-off-by: Steffen Kothe Reviewed-by: Bryan Brattlof --- arch/arm/mach-k3/include/mach/am64_hardware.h | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) diff --git a/arch/arm/mach-k3/include/mach/am64_hardware.h b/arch/arm/mach-k3/include/mach/am64_hardware.h index 105b42986de..95ba488ba17 100644 --- a/arch/arm/mach-k3/include/mach/am64_hardware.h +++ b/arch/arm/mach-k3/include/mach/am64_hardware.h @@ -46,6 +46,26 @@ /* Use Last 2K as Scratch pad */ #define TI_SRAM_SCRATCH_BOARD_EEPROM_START 0x7019f800 + +/* Reset Reason Detection */ +#define CTRLMMR_MCU_RST_SRC (MCU_CTRL_MMR0_BASE + 0x18178) + +/* Reset causes by bit mapping */ +#define RST_SRC_SAFETY_ERR BIT(31) +#define RST_SRC_MAIN_ESM_ERR BIT(30) +#define RST_SRC_SW_MAIN_POR_FROM_MAIN BIT(25) +#define RST_SRC_SW_MAIN_POR_FROM_MCU BIT(24) +#define RST_SRC_SW_MAIN_WARM_FROM_MAIN BIT(21) +#define RST_SRC_SW_MAIN_WARM_FROM_MCU BIT(20) +#define RST_SRC_SW_MCU_WARM_RST BIT(16) +#define RST_SRC_SMS_WARM_RST BIT(13) +#define RST_SRC_SMS_COLD_RST BIT(12) +#define RST_SRC_DEBUG_RST BIT(8) +#define RST_SRC_THERMAL_RST BIT(4) +#define RST_SRC_MAIN_RESET_PIN BIT(2) +#define RST_SRC_MCU_RESET_PIN BIT(0) + + #if defined(CONFIG_SYS_K3_SPL_ATF) && !defined(__ASSEMBLY__) #define AM64X_DEV_RTI8 127 -- cgit v1.2.3 From 3d9bd76b07fa2e3de167f6d8916bcb6cce6484af Mon Sep 17 00:00:00 2001 From: Steffen Kothe Date: Sun, 31 Aug 2025 15:17:06 +0000 Subject: arm: mach-k3: am64x: Implement get_reset_reason() Implement get_reset_reason() for AM64x to enable reporting of the reset cause in the cpuinfo output. Notice that the AM64x does not support dedicated reset cause bits for WDT and PORZ as the AM62x does. An explanation of this difference is not part of the technical reference manual and remains unclear. Signed-off-by: Steffen Kothe Reviewed-by: Bryan Brattlof --- arch/arm/mach-k3/am64x/boot.c | 36 ++++++++++++++++++++++++++++++++++++ 1 file changed, 36 insertions(+) diff --git a/arch/arm/mach-k3/am64x/boot.c b/arch/arm/mach-k3/am64x/boot.c index ce8ae941be6..f88f92b9f23 100644 --- a/arch/arm/mach-k3/am64x/boot.c +++ b/arch/arm/mach-k3/am64x/boot.c @@ -103,3 +103,39 @@ u32 get_boot_device(void) return bootmedia; } + +const char *get_reset_reason(void) +{ + u32 reset_reason = readl(CTRLMMR_MCU_RST_SRC); + + /* After reading reset source register, software must clear it */ + if (reset_reason) + writel(reset_reason, CTRLMMR_MCU_RST_SRC); + + if (reset_reason == 0 || + (reset_reason & (RST_SRC_SW_MAIN_POR_FROM_MAIN | + RST_SRC_SW_MAIN_POR_FROM_MCU))) + return "POR"; + + if (reset_reason & (RST_SRC_SAFETY_ERR | RST_SRC_MAIN_ESM_ERR)) + return "ESM"; + + if (reset_reason & (RST_SRC_SW_MAIN_WARM_FROM_MAIN | + RST_SRC_SW_MAIN_WARM_FROM_MCU | + RST_SRC_SW_MCU_WARM_RST)) + return "RST"; + + if (reset_reason & (RST_SRC_SMS_WARM_RST | RST_SRC_SMS_COLD_RST)) + return "DMSC"; + + if (reset_reason & RST_SRC_DEBUG_RST) + return "JTAG"; + + if (reset_reason & RST_SRC_THERMAL_RST) + return "THERMAL"; + + if (reset_reason & (RST_SRC_MAIN_RESET_PIN | RST_SRC_MCU_RESET_PIN)) + return "PIN"; + + return "UNKNOWN"; +} -- cgit v1.2.3 From 7e2c23eacd8e6fe76306ebf3cd6e31d52695b617 Mon Sep 17 00:00:00 2001 From: Heinrich Schuchardt Date: Mon, 1 Sep 2025 17:16:35 +0200 Subject: bloblist: use correct types for physical addresses It is expected that bloblists are stored in high memory beyond 2 GiB. We must not use int as data type for these addresses but phys_addr_t. Fixes: f9ef9fb033d5 ("bloblist: Handle alignment with a void entry") Signed-off-by: Heinrich Schuchardt Reviewed-by: Ilias Apalodimas --- common/bloblist.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/common/bloblist.c b/common/bloblist.c index 6e4f020d7c4..d5fa62249a9 100644 --- a/common/bloblist.c +++ b/common/bloblist.c @@ -149,7 +149,8 @@ static int bloblist_addrec(uint tag, int size, int align_log2, { struct bloblist_hdr *hdr = gd->bloblist; struct bloblist_rec *rec; - int data_start, aligned_start, new_alloced; + phys_addr_t data_start, aligned_start; + phys_size_t new_alloced; if (!align_log2) align_log2 = BLOBLIST_BLOB_ALIGN_LOG2; -- cgit v1.2.3 From 559f11e66cf78a7cf57100086bba11a5a516cd25 Mon Sep 17 00:00:00 2001 From: Heinrich Schuchardt Date: Mon, 1 Sep 2025 19:03:08 +0200 Subject: bloblist: adjust default bloblist size after reloc If neither CONFIG_BLOBLIST_FIXED NOR CONFIG_BLOBLIST_ALLOC is set, currently CONFIG_BLOBLIST_SIZE_RELOC defaults to 0 except if * CONFIG_ARM=y && CONFIG_EFI_LOADER=y && GENERATE_ACPI_TABLE=y. A size of zero never makes sense for a bloblist. When using QFW we need more than 64 KiB to host the ACPI table. In this case CONFIG_BLOBLIST_ALLOC is used. Set a reasonable default. Remove the CONFIG_BLOBLIST_SIZE_RELOC in ARM QEMU defconfigs which are not compatible with ACPI tables passed from QEMU. Reported-by: Emil Renner Berthing Fixes: 6f9b015c138b ("common: Enable BLOBLIST_TABLES on arm") Signed-off-by: Heinrich Schuchardt Acked-by: Ilias Apalodimas --- common/Kconfig | 4 ++-- configs/qemu_arm64_defconfig | 1 - configs/qemu_arm_defconfig | 1 - 3 files changed, 2 insertions(+), 4 deletions(-) diff --git a/common/Kconfig b/common/Kconfig index cb17f056153..66dcc8cde15 100644 --- a/common/Kconfig +++ b/common/Kconfig @@ -1128,8 +1128,8 @@ config BLOBLIST_SIZE config BLOBLIST_SIZE_RELOC hex "Size of bloblist after relocation" - default BLOBLIST_SIZE if BLOBLIST_FIXED || BLOBLIST_ALLOC - default 0x20000 if (ARM && EFI_LOADER && GENERATE_ACPI_TABLE) + default BLOBLIST_SIZE if BLOBLIST_FIXED + default 0x20000 help Sets the size of the bloblist in bytes after relocation. Since U-Boot has a lot more memory available then, it is possible to use a larger diff --git a/configs/qemu_arm64_defconfig b/configs/qemu_arm64_defconfig index 358bb1aeeb9..12ed6b61239 100644 --- a/configs/qemu_arm64_defconfig +++ b/configs/qemu_arm64_defconfig @@ -2,7 +2,6 @@ CONFIG_ARM=y CONFIG_KVM_VIRT_INS=y CONFIG_ARCH_QEMU=y CONFIG_SYS_MALLOC_LEN=0x1000000 -CONFIG_BLOBLIST_SIZE_RELOC=0x2000 CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x40200000 CONFIG_ENV_SIZE=0x40000 CONFIG_ENV_SECT_SIZE=0x40000 diff --git a/configs/qemu_arm_defconfig b/configs/qemu_arm_defconfig index d5890bf87fb..e6d4414cf0d 100644 --- a/configs/qemu_arm_defconfig +++ b/configs/qemu_arm_defconfig @@ -3,7 +3,6 @@ CONFIG_KVM_VIRT_INS=y CONFIG_ARM_SMCCC=y CONFIG_ARCH_QEMU=y CONFIG_SYS_MALLOC_LEN=0x1000000 -CONFIG_BLOBLIST_SIZE_RELOC=0x2000 CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x40200000 CONFIG_ENV_SIZE=0x40000 CONFIG_ENV_SECT_SIZE=0x40000 -- cgit v1.2.3 From 6dfd14e1228e6e14462f377987bc896d6b7f1dd5 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Wed, 3 Sep 2025 00:01:55 +0200 Subject: mkimage: Add support for bundling TFA BL31 in mkimage -f auto Introduce two new parameters to be used with mkimage -f auto to bundle TFA BL31 image into fitImage, using auto-generated fitImage. Add -y to specify TFA BL31 file name and -Y to specify TFA BL31 load and entry point address. This is meant to be used with systems which boot all of TFA BL31, Linux and its DT from a single fitImage, all booted by U-Boot. Example invocation: " $ mkimage -E -A arm64 -C none -e 0x50200000 -a 0x50200000 -f auto \ -d arch/arm64/boot/Image \ -b arch/arm64/boot/dts/renesas/r8a779g3-sparrow-hawk.dtb \ -y ../tfa/build/rcar_gen4/release/bl31.bin -Y 0x46400000 \ /path/to/output/fitImage " Documentation update and test are also included, the test validates both positive and negative test cases, where fitImage does not include TFA BL31 and does include TFA BL31 blobs. Signed-off-by: Marek Vasut --- doc/mkimage.1 | 12 +++++++ include/image.h | 1 + test/py/tests/test_fit_auto_signed.py | 67 +++++++++++++++++++++++++++++++++++ tools/fit_image.c | 52 +++++++++++++++++++++++++-- tools/imagetool.h | 2 ++ tools/mkimage.c | 15 +++++++- 6 files changed, 146 insertions(+), 3 deletions(-) diff --git a/doc/mkimage.1 b/doc/mkimage.1 index d0a038a880a..75b6b48a0cf 100644 --- a/doc/mkimage.1 +++ b/doc/mkimage.1 @@ -239,6 +239,18 @@ Set the command will not load the image data, and instead will assume it is already accessible at the load address (such as via memory-mapped flash). . +.TP +.B \-y +.TQ +.B \-\-tfa-bl31-file +Append TFA BL31 file to the image. +. +.TP +.B \-Y +.TQ +.B \-\-tfa-bl31-addr +Set TFA BL31 file load and entry point address. +. .SS Options for creating FIT images . .TP diff --git a/include/image.h b/include/image.h index b695cc39447..fc2f2487095 100644 --- a/include/image.h +++ b/include/image.h @@ -1104,6 +1104,7 @@ int booti_setup(ulong image, ulong *relocated_addr, ulong *size, #define FIT_STANDALONE_PROP "standalone" #define FIT_SCRIPT_PROP "script" #define FIT_PHASE_PROP "phase" +#define FIT_TFA_BL31_PROP "tfa-bl31" #define FIT_MAX_HASH_LEN HASH_MAX_DIGEST_SIZE diff --git a/test/py/tests/test_fit_auto_signed.py b/test/py/tests/test_fit_auto_signed.py index cdfd341c6f5..0b5dbd5401c 100644 --- a/test/py/tests/test_fit_auto_signed.py +++ b/test/py/tests/test_fit_auto_signed.py @@ -117,6 +117,23 @@ class SignedFitHelper(object): algo = self.__fdt_get_string(f'{node}/signature', 'algo') assert algo == sign_algo + "\n", "Missing expected signature algo!" + def check_fit_loadables(self, present): + """Test that loadables contains both kernel and TFA BL31 entries. + + Each configuration must have a loadables property which lists both + kernel-1 and tfa-bl31-1 strings in the string list. + """ + if present: + assert "/images/tfa-bl31-1" in self.images_nodes + else: + assert "/images/tfa-bl31-1" not in self.images_nodes + for node in self.confgs_nodes: + loadables = self.__fdt_get_string(f'{node}', 'loadables') + assert "kernel-1" in loadables + if present: + assert "tfa-bl31-1" in loadables + else: + assert "tfa-bl31-1" not in loadables @pytest.mark.buildconfigspec('fit_signature') @pytest.mark.requiredtool('fdtget') @@ -139,6 +156,7 @@ def test_fit_auto_signed(ubman): kernel_file = f'{tempdir}/vmlinuz' dt1_file = f'{tempdir}/dt-1.dtb' dt2_file = f'{tempdir}/dt-2.dtb' + tfa_file = f'{tempdir}/tfa-bl31.bin' key_name = 'sign-key' sign_algo = 'sha256,rsa4096' key_file = f'{tempdir}/{key_name}.key' @@ -154,6 +172,9 @@ def test_fit_auto_signed(ubman): with open(dt2_file, 'wb') as fd: fd.write(os.urandom(256)) + with open(tfa_file, 'wb') as fd: + fd.write(os.urandom(256)) + # Create 4096 RSA key and write to file to be read by mkimage key = RSA.generate(bits=4096) verifier = pkcs1_15.new(key) @@ -173,6 +194,8 @@ def test_fit_auto_signed(ubman): fit.check_fit_crc32_images() + fit.check_fit_loadables(present=False) + # 2 - Create auto FIT with signed images, and verify it utils.run_and_log(ubman, mkimage + ' -fauto' + b_args + s_args + " " + fit_file) @@ -183,6 +206,8 @@ def test_fit_auto_signed(ubman): fit.check_fit_signed_images(key_name, sign_algo, verifier) + fit.check_fit_loadables(present=False) + # 3 - Create auto FIT with signed configs and hashed images, and verify it utils.run_and_log(ubman, mkimage + ' -fauto-conf' + b_args + s_args + " " + fit_file) @@ -192,3 +217,45 @@ def test_fit_auto_signed(ubman): raise ValueError('FIT-3 has no "/image" nor "/configuration" nodes') fit.check_fit_signed_confgs(key_name, sign_algo) + + fit.check_fit_loadables(present=False) + + # Run the same tests as 1/2/3 above, but this time with TFA BL31 + # options -y tfa-bl31.bin -Y 0x12340000 to cover both mkimage with + # and without TFA BL31 use cases. + b_args = " -d" + kernel_file + " -b" + dt1_file + " -b" + dt2_file + " -y" + tfa_file + " -Y 0x12340000" + + # 4 - Create auto FIT with images crc32 checksum, and verify it + utils.run_and_log(ubman, mkimage + ' -fauto' + b_args + " " + fit_file) + + fit = SignedFitHelper(ubman, fit_file) + if fit.build_nodes_sets() == 0: + raise ValueError('FIT-4 has no "/image" nor "/configuration" nodes') + + fit.check_fit_crc32_images() + + fit.check_fit_loadables(present=True) + + # 5 - Create auto FIT with signed images, and verify it + utils.run_and_log(ubman, mkimage + ' -fauto' + b_args + s_args + " " + + fit_file) + + fit = SignedFitHelper(ubman, fit_file) + if fit.build_nodes_sets() == 0: + raise ValueError('FIT-5 has no "/image" nor "/configuration" nodes') + + fit.check_fit_signed_images(key_name, sign_algo, verifier) + + fit.check_fit_loadables(present=True) + + # 6 - Create auto FIT with signed configs and hashed images, and verify it + utils.run_and_log(ubman, mkimage + ' -fauto-conf' + b_args + s_args + " " + + fit_file) + + fit = SignedFitHelper(ubman, fit_file) + if fit.build_nodes_sets() == 0: + raise ValueError('FIT-6 has no "/image" nor "/configuration" nodes') + + fit.check_fit_signed_confgs(key_name, sign_algo) + + fit.check_fit_loadables(present=True) diff --git a/tools/fit_image.c b/tools/fit_image.c index 331be5ae71d..10849733816 100644 --- a/tools/fit_image.c +++ b/tools/fit_image.c @@ -173,6 +173,13 @@ static int fit_calc_size(struct image_tool_params *params) total_size += size; } + if (params->fit_tfa_bl31) { + size = imagetool_get_filesize(params, params->fit_tfa_bl31); + if (size < 0) + return -1; + total_size += size; + } + for (cont = params->content_head; cont; cont = cont->next) { size = imagetool_get_filesize(params, cont->fname); if (size < 0) @@ -402,6 +409,30 @@ static int fit_write_images(struct image_tool_params *params, char *fdt) fdt_end_node(fdt); } + /* And a TFA BL31 file if available */ + if (params->fit_tfa_bl31) { + fdt_begin_node(fdt, FIT_TFA_BL31_PROP "-1"); + + fdt_property_string(fdt, FIT_TYPE_PROP, FIT_TFA_BL31_PROP); + fdt_property_string(fdt, FIT_OS_PROP, + genimg_get_os_short_name(params->os)); + fdt_property_string(fdt, FIT_ARCH_PROP, + genimg_get_arch_short_name(params->arch)); + get_basename(str, sizeof(str), params->fit_tfa_bl31); + fdt_property_string(fdt, FIT_DESC_PROP, str); + + ret = fdt_property_file(params, fdt, FIT_DATA_PROP, + params->fit_tfa_bl31); + if (ret) + return ret; + fdt_property_u32(fdt, FIT_LOAD_PROP, params->fit_tfa_bl31_addr); + fdt_property_u32(fdt, FIT_ENTRY_PROP, params->fit_tfa_bl31_addr); + fit_add_hash_or_sign(params, fdt, true); + if (ret) + return ret; + fdt_end_node(fdt); + } + fdt_end_node(fdt); return 0; @@ -421,7 +452,7 @@ static void fit_write_configs(struct image_tool_params *params, char *fdt) struct content_info *cont; const char *typename; char str[100]; - int upto; + int upto, len; fdt_begin_node(fdt, "configurations"); fdt_property_string(fdt, FIT_DEFAULT_PROP, "conf-1"); @@ -439,8 +470,16 @@ static void fit_write_configs(struct image_tool_params *params, char *fdt) typename = genimg_get_type_short_name(params->fit_image_type); snprintf(str, sizeof(str), "%s-1", typename); + len = strlen(str); fdt_property_string(fdt, typename, str); - fdt_property_string(fdt, FIT_LOADABLE_PROP, str); + + if (params->fit_tfa_bl31) { + snprintf(str, sizeof(str), "%s-1." FIT_TFA_BL31_PROP "-1", typename); + str[len] = 0; + len += strlen(FIT_TFA_BL31_PROP "-1") + 1; + } + + fdt_property(fdt, FIT_LOADABLE_PROP, str, len + 1); if (params->fit_ramdisk) fdt_property_string(fdt, FIT_RAMDISK_PROP, @@ -456,8 +495,17 @@ static void fit_write_configs(struct image_tool_params *params, char *fdt) fdt_begin_node(fdt, "conf-1"); typename = genimg_get_type_short_name(params->fit_image_type); snprintf(str, sizeof(str), "%s-1", typename); + len = strlen(str); fdt_property_string(fdt, typename, str); + if (params->fit_tfa_bl31) { + snprintf(str, sizeof(str), "%s-1." FIT_TFA_BL31_PROP "-1", typename); + str[len] = 0; + len += strlen(FIT_TFA_BL31_PROP "-1") + 1; + } + + fdt_property(fdt, FIT_LOADABLE_PROP, str, len + 1); + if (params->fit_ramdisk) fdt_property_string(fdt, FIT_RAMDISK_PROP, FIT_RAMDISK_PROP "-1"); diff --git a/tools/imagetool.h b/tools/imagetool.h index 57be608210a..866b8834fd7 100644 --- a/tools/imagetool.h +++ b/tools/imagetool.h @@ -99,6 +99,8 @@ struct image_tool_params { const char *engine_id; /* Engine to use for signing */ bool reset_timestamp; /* Reset the timestamp on an existing image */ struct image_summary summary; /* results of signing process */ + char *fit_tfa_bl31; /* TFA BL31 file to include */ + unsigned int fit_tfa_bl31_addr; /* TFA BL31 load and entry point address */ }; /* diff --git a/tools/mkimage.c b/tools/mkimage.c index 847453970ab..12183270776 100644 --- a/tools/mkimage.c +++ b/tools/mkimage.c @@ -160,7 +160,7 @@ static int add_content(int type, const char *fname) } static const char optstring[] = - "a:A:b:B:c:C:d:D:e:Ef:Fg:G:i:k:K:ln:N:o:O:p:qrR:stT:vVx"; + "a:A:b:B:c:C:d:D:e:Ef:Fg:G:i:k:K:ln:N:o:O:p:qrR:stT:vVxy:Y:"; static const struct option longopts[] = { { "load-address", required_argument, NULL, 'a' }, @@ -196,6 +196,8 @@ static const struct option longopts[] = { { "verbose", no_argument, NULL, 'v' }, { "version", no_argument, NULL, 'V' }, { "xip", no_argument, NULL, 'x' }, + { "tfa-bl31-file", no_argument, NULL, 'y' }, + { "tfa-bl31-addr", no_argument, NULL, 'Y' }, { /* sentinel */ }, }; @@ -367,6 +369,17 @@ static void process_args(int argc, char **argv) case 'x': params.xflag++; break; + case 'y': + params.fit_tfa_bl31 = optarg; + break; + case 'Y': + params.fit_tfa_bl31_addr = strtoull(optarg, &ptr, 16); + if (*ptr) { + fprintf(stderr, "%s: invalid TFA BL31 address %s\n", + params.cmdname, optarg); + exit(EXIT_FAILURE); + } + break; default: usage("Invalid option"); } -- cgit v1.2.3 From 4c822970d366415e717730606734e815993a70bb Mon Sep 17 00:00:00 2001 From: Osama Abdelkader Date: Wed, 3 Sep 2025 00:24:11 +0200 Subject: sandbox: replace deprecated getenv() with env_get() use env_get() instead of getenv() for consistency. Signed-off-by: Osama Abdelkader --- arch/sandbox/cpu/os.c | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/arch/sandbox/cpu/os.c b/arch/sandbox/cpu/os.c index f5c9a8aecf2..adb6b586946 100644 --- a/arch/sandbox/cpu/os.c +++ b/arch/sandbox/cpu/os.c @@ -35,6 +35,7 @@ #include #include #include +#include /* Environment variable for time offset */ #define ENV_TIME_OFFSET "UBOOT_SB_TIME_OFFSET" @@ -283,7 +284,7 @@ int os_unmap(void *buf, int size) int os_persistent_file(char *buf, int maxsize, const char *fname) { - const char *dirname = getenv("U_BOOT_PERSISTENT_DATA_DIR"); + const char *dirname = env_get("U_BOOT_PERSISTENT_DATA_DIR"); char *ptr; int len; @@ -1014,7 +1015,7 @@ long os_get_time_offset(void) { const char *offset; - offset = getenv(ENV_TIME_OFFSET); + offset = env_get(ENV_TIME_OFFSET); if (offset) return strtol(offset, NULL, 0); return 0; @@ -1132,7 +1133,7 @@ static void *fuzzer_thread(void * ptr) const char *fuzz_test; /* Find which test to run from an environment variable. */ - fuzz_test = getenv("UBOOT_SB_FUZZ_TEST"); + fuzz_test = env_get("UBOOT_SB_FUZZ_TEST"); if (!fuzz_test) os_abort(); -- cgit v1.2.3 From f0c1704f56dba70da93f30131564af777c29c1bd Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Fri, 12 Sep 2025 16:34:58 -0600 Subject: Revert "sandbox: replace deprecated getenv() with env_get()" While testing changes, I missed that Gitlab had failed CI with pytest failures due to this change. This reverts commit 4c822970d366415e717730606734e815993a70bb. Cc: Osama Abdelkader Signed-off-by: Tom Rini --- arch/sandbox/cpu/os.c | 7 +++---- 1 file changed, 3 insertions(+), 4 deletions(-) diff --git a/arch/sandbox/cpu/os.c b/arch/sandbox/cpu/os.c index adb6b586946..f5c9a8aecf2 100644 --- a/arch/sandbox/cpu/os.c +++ b/arch/sandbox/cpu/os.c @@ -35,7 +35,6 @@ #include #include #include -#include /* Environment variable for time offset */ #define ENV_TIME_OFFSET "UBOOT_SB_TIME_OFFSET" @@ -284,7 +283,7 @@ int os_unmap(void *buf, int size) int os_persistent_file(char *buf, int maxsize, const char *fname) { - const char *dirname = env_get("U_BOOT_PERSISTENT_DATA_DIR"); + const char *dirname = getenv("U_BOOT_PERSISTENT_DATA_DIR"); char *ptr; int len; @@ -1015,7 +1014,7 @@ long os_get_time_offset(void) { const char *offset; - offset = env_get(ENV_TIME_OFFSET); + offset = getenv(ENV_TIME_OFFSET); if (offset) return strtol(offset, NULL, 0); return 0; @@ -1133,7 +1132,7 @@ static void *fuzzer_thread(void * ptr) const char *fuzz_test; /* Find which test to run from an environment variable. */ - fuzz_test = env_get("UBOOT_SB_FUZZ_TEST"); + fuzz_test = getenv("UBOOT_SB_FUZZ_TEST"); if (!fuzz_test) os_abort(); -- cgit v1.2.3 From 83bb1c438486a03184795b0dfa970271496b24bf Mon Sep 17 00:00:00 2001 From: Anshul Dalal Date: Tue, 2 Sep 2025 10:27:07 +0530 Subject: board: ti: common: Kconfig: add CMD_MEMINFO Add CMD_MEMINFO and CMD_MEMINFO_MAP to list of configs implied by TI_COMMON_CMD_OPTIONS. This allows users to easily view the memory configuration and the memory maps at runtime. Signed-off-by: Anshul Dalal --- board/ti/common/Kconfig | 2 ++ 1 file changed, 2 insertions(+) diff --git a/board/ti/common/Kconfig b/board/ti/common/Kconfig index 2de4212d9b8..f481812247c 100644 --- a/board/ti/common/Kconfig +++ b/board/ti/common/Kconfig @@ -40,6 +40,8 @@ config TI_COMMON_CMD_OPTIONS imply CMD_GPIO imply CMD_GPT imply CMD_I2C + imply CMD_MEMINFO + imply CMD_MEMINFO_MAP imply CMD_MII imply CMD_MMC imply CMD_MMC_REG -- cgit v1.2.3 From 7aa5271def6ba16ff4426aa164b7bb743673b3c3 Mon Sep 17 00:00:00 2001 From: Anshul Dalal Date: Wed, 3 Sep 2025 16:47:02 +0530 Subject: mach-k3: fix reading size and addr from fdt on R5 fdtdec_get_addr_size uses architecture dependent datatypes which causes the 32-bit R5 to fail when reading the 64-bit size and addr fields of reg nodes from the fdt. Therefore change it to a common api for both 64 and 32 bit platforms to allow for fdt fixups from R5. Fixes: 8b0fc29de0e3 ("arm: mach-k3: am62: Fixup TF-A/OP-TEE reserved-memory node in FDT") Signed-off-by: Anshul Dalal Reviewed-by: Dhruva Gole --- arch/arm/mach-k3/common_fdt.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/arch/arm/mach-k3/common_fdt.c b/arch/arm/mach-k3/common_fdt.c index 2777354c6ab..1e6786f6c20 100644 --- a/arch/arm/mach-k3/common_fdt.c +++ b/arch/arm/mach-k3/common_fdt.c @@ -140,7 +140,9 @@ int fdt_fixup_reserved(void *blob, const char *name, return -EINVAL; if (!strncmp(node_name, name, strlen(name))) { /* Read out old size first */ - addr = fdtdec_get_addr_size(blob, subnode, "reg", &size); + addr = fdtdec_get_addr_size_auto_parent( + blob, nodeoffset, subnode, "reg", 0, &size, + false); if (addr == FDT_ADDR_T_NONE) return -EINVAL; new_size = size; -- cgit v1.2.3 From 8db442e1a03b048fd34651b3e48ffdcc0bf7868b Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Wed, 3 Sep 2025 16:20:52 +0200 Subject: env: Remove usb_ignorelist and env_fdt_path from ifdef CONFIG_ENV_VARS_UBOOT_CONFIG The CONFIG_ENV_VARS_UBOOT_CONFIG should protect only U-Boot configuration variables in environment, those are arch, cpu, board, board_name, vendor, soc. It should certainly not hide usb_ignorelist or env_fdt_path from the environment. Fix it. Signed-off-by: Marek Vasut Reviewed-by: Tom Rini --- include/env_default.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/include/env_default.h b/include/env_default.h index ae2cfbcbc45..7f8dc1c35a7 100644 --- a/include/env_default.h +++ b/include/env_default.h @@ -97,6 +97,7 @@ const char default_environment[] = { #ifdef CONFIG_SYS_SOC "soc=" CONFIG_SYS_SOC "\0" #endif +#endif #ifdef CONFIG_USB_HOST "usb_ignorelist=" #ifdef CONFIG_USB_KEYBOARD @@ -111,7 +112,6 @@ const char default_environment[] = { #ifdef CONFIG_ENV_IMPORT_FDT "env_fdt_path=" CONFIG_ENV_FDT_PATH "\0" #endif -#endif #if defined(CONFIG_BOOTCOUNT_BOOTLIMIT) && (CONFIG_BOOTCOUNT_BOOTLIMIT > 0) "bootlimit=" __stringify(CONFIG_BOOTCOUNT_BOOTLIMIT)"\0" #endif -- cgit v1.2.3 From 41d9ac102536a07f8561533873bb8e772e61d54a Mon Sep 17 00:00:00 2001 From: Philip Molloy Date: Fri, 5 Sep 2025 11:25:13 +0000 Subject: gpio: adp5588: Add ADP5587 as compatible The ADP5587 is a simpler version of the ADP5588. The ADP5588 can configure two pins, C8 and C9, as GPIOs or light sensors. The ADP5587 does not include the light sensors. Signed-off-by: Philip Molloy --- drivers/gpio/adp5588_gpio.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/gpio/adp5588_gpio.c b/drivers/gpio/adp5588_gpio.c index d081e169897..36304e48893 100644 --- a/drivers/gpio/adp5588_gpio.c +++ b/drivers/gpio/adp5588_gpio.c @@ -168,7 +168,7 @@ static int adp5588_ofdata_platdata(struct udevice *dev) revid = ret & ID_MASK; - printf("ADP5588 Detected: Rev %x, Rev ID %x\n", ret, revid); + printf("ADP558x Detected: Rev %x, Rev ID %x\n", ret, revid); for (i = 0, ret = 0; i <= ADP5588_BANK(ADP5588_MAXGPIO); i++) { plat->dat_out[i] = adp5588_gpio_read(dev, GPIO_DAT_OUT1 + i); @@ -194,6 +194,7 @@ static const struct dm_gpio_ops adp5588_ops = { static const struct udevice_id adp5588_of_match_list[] = { { .compatible = "adi,adp5588"}, + { .compatible = "adi,adp5587"}, { /* sentinel */ } }; -- cgit v1.2.3 From bbc9347a98c3fb32610d4324c9e0f6239f013143 Mon Sep 17 00:00:00 2001 From: Aditya Dutt Date: Fri, 5 Sep 2025 19:36:11 +0530 Subject: cmd: terminal: avoid serial_reinit_all() with DM_SERIAL enabled serial_reinit_all() is only available when CONFIG DM_SERIAL is disabled and CONFIG_SERIAL is enabled. Signed-off-by: Aditya Dutt --- cmd/terminal.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/cmd/terminal.c b/cmd/terminal.c index d803bc6c896..14610694255 100644 --- a/cmd/terminal.c +++ b/cmd/terminal.c @@ -24,7 +24,7 @@ int do_terminal(struct cmd_tbl *cmd, int flag, int argc, char *const argv[]) if (!dev) return -1; - if (IS_ENABLED(CONFIG_SERIAL)) + if (IS_ENABLED(CONFIG_SERIAL) && !IS_ENABLED(CONFIG_DM_SERIAL)) serial_reinit_all(); printf("Entering terminal mode for port %s\n", dev->name); -- cgit v1.2.3 From 56aa947c2ad6cbdf4e7a4281e83689ac3fbc8498 Mon Sep 17 00:00:00 2001 From: Greg Malysa Date: Wed, 3 Sep 2025 19:42:01 -0400 Subject: net: dwc_eth_qos_adi: Add missing header Following header dependency cleanups, an implicit dependence on env.h was exposed in dwc_eth_qos_adi. However because this driver is not (yet) enabled in any defconfigs, build tests did not identify the missing header. This adds the missing #include so that the driver builds correctly when enabled. Signed-off-by: Greg Malysa --- drivers/net/dwc_eth_qos_adi.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/net/dwc_eth_qos_adi.c b/drivers/net/dwc_eth_qos_adi.c index 0e6a901e303..fee50a88156 100644 --- a/drivers/net/dwc_eth_qos_adi.c +++ b/drivers/net/dwc_eth_qos_adi.c @@ -10,6 +10,7 @@ #include #include +#include #include #include #include -- cgit v1.2.3 From 2941e4c0476c69ef10e0900a8d9cac40a6dcc831 Mon Sep 17 00:00:00 2001 From: Greg Malysa Date: Wed, 3 Sep 2025 19:42:02 -0400 Subject: mmc: adi_sdhci: Update headers As part of the header dependency cleanup between 2025.07 and 2025.10, an implicit route to obtain SZ_128M from linux/sizes.h was removed. This adds an explicit reference to linux/sizes.h to fix build failures for this driver. Signed-off-by: Greg Malysa Reviewed-by: Peng Fan --- drivers/mmc/adi_sdhci.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/mmc/adi_sdhci.c b/drivers/mmc/adi_sdhci.c index 65a22cefb71..f58897b5218 100644 --- a/drivers/mmc/adi_sdhci.c +++ b/drivers/mmc/adi_sdhci.c @@ -15,6 +15,7 @@ #include #include #include +#include /* 400KHz is max freq for card ID etc. Use that as min */ #define EMMC_MIN_FREQ 400000 -- cgit v1.2.3 From 29f6db89add2a5484ac478ba93d4574bb65ee158 Mon Sep 17 00:00:00 2001 From: Javier Tia Date: Fri, 5 Sep 2025 14:53:44 -0600 Subject: clang-format: Add configuration file Introduce .clang-format configuration file to U-Boot, providing significant improvements over the existing scripts/Lindent approach for C code formatting. Benefits of clang-format over scripts/Lindent: - More comprehensive formatting rules: While Lindent relies on the basic 'indent' tool with limited options, clang-format provides extensive control over code formatting with 800+ configuration options - Better handling of complex code structures: clang-format understands modern C constructs and handles nested structures, macros, and complex expressions more intelligently - IDE and editor integration: Native support in major development environments (VS Code, Vim, Emacs, etc.) enables real-time formatting - Consistent results across environments: Eliminates variations between different versions of 'indent' tool and system configurations - Active maintenance: clang-format is actively developed and updated, unlike the aging 'indent' tool Alignment with Linux kernel practices: Continues U-Boot alignment with Linux kernel development practices, maintaining consistency between these closely related projects. The Linux kernel adopted clang-format to modernize its code formatting infrastructure and improve developer experience. The .clang-format file is based on the Linux kernel configuration, specifically copied from Linux kernel v6.16 tag, which itself builds upon the initial introduction in commit d4ef8d3ff005c ("clang-format: add configuration file"). Signed-off-by: Javier Tia --- .clang-format | 804 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ .gitignore | 1 + 2 files changed, 805 insertions(+) create mode 100644 .clang-format diff --git a/.clang-format b/.clang-format new file mode 100644 index 00000000000..48405c54ef2 --- /dev/null +++ b/.clang-format @@ -0,0 +1,804 @@ +# SPDX-License-Identifier: GPL-2.0 +# +# clang-format configuration file. Intended for clang-format >= 11. +# +# For more information, see: +# +# Documentation/dev-tools/clang-format.rst +# https://clang.llvm.org/docs/ClangFormat.html +# https://clang.llvm.org/docs/ClangFormatStyleOptions.html +# +--- +AccessModifierOffset: -4 +AlignAfterOpenBracket: Align +AlignConsecutiveAssignments: false +AlignConsecutiveDeclarations: false +AlignEscapedNewlines: Left +AlignOperands: true +AlignTrailingComments: false +AllowAllParametersOfDeclarationOnNextLine: false +AllowShortBlocksOnASingleLine: false +AllowShortCaseLabelsOnASingleLine: false +AllowShortFunctionsOnASingleLine: None +AllowShortIfStatementsOnASingleLine: false +AllowShortLoopsOnASingleLine: false +AlwaysBreakAfterDefinitionReturnType: None +AlwaysBreakAfterReturnType: None +AlwaysBreakBeforeMultilineStrings: false +AlwaysBreakTemplateDeclarations: false +BinPackArguments: true +BinPackParameters: true +BraceWrapping: + AfterClass: false + AfterControlStatement: false + AfterEnum: false + AfterFunction: true + AfterNamespace: true + AfterObjCDeclaration: false + AfterStruct: false + AfterUnion: false + AfterExternBlock: false + BeforeCatch: false + BeforeElse: false + IndentBraces: false + SplitEmptyFunction: true + SplitEmptyRecord: true + SplitEmptyNamespace: true +BreakBeforeBinaryOperators: None +BreakBeforeBraces: Custom +BreakBeforeInheritanceComma: false +BreakBeforeTernaryOperators: false +BreakConstructorInitializersBeforeComma: false +BreakConstructorInitializers: BeforeComma +BreakAfterJavaFieldAnnotations: false +BreakStringLiterals: false +ColumnLimit: 80 +CommentPragmas: '^ IWYU pragma:' +CompactNamespaces: false +ConstructorInitializerAllOnOneLineOrOnePerLine: false +ConstructorInitializerIndentWidth: 8 +ContinuationIndentWidth: 8 +Cpp11BracedListStyle: false +DerivePointerAlignment: false +DisableFormat: false +ExperimentalAutoDetectBinPacking: false +FixNamespaceComments: false + +# Taken from: +# git grep -h '^#define [^[:space:]]*for_each[^[:space:]]*(' include/ tools/ \ +# | sed "s,^#define \([^[:space:]]*for_each[^[:space:]]*\)(.*$, - '\1'," \ +# | LC_ALL=C sort -u +ForEachMacros: + - '__ata_qc_for_each' + - '__bio_for_each_bvec' + - '__bio_for_each_segment' + - '__evlist__for_each_entry' + - '__evlist__for_each_entry_continue' + - '__evlist__for_each_entry_from' + - '__evlist__for_each_entry_reverse' + - '__evlist__for_each_entry_safe' + - '__for_each_mem_range' + - '__for_each_mem_range_rev' + - '__for_each_thread' + - '__hlist_for_each_rcu' + - '__map__for_each_symbol_by_name' + - '__pci_bus_for_each_res0' + - '__pci_bus_for_each_res1' + - '__pci_dev_for_each_res0' + - '__pci_dev_for_each_res1' + - '__perf_evlist__for_each_entry' + - '__perf_evlist__for_each_entry_reverse' + - '__perf_evlist__for_each_entry_safe' + - '__rq_for_each_bio' + - '__shost_for_each_device' + - '__sym_for_each' + - '_for_each_counter' + - 'apei_estatus_for_each_section' + - 'ata_for_each_dev' + - 'ata_for_each_link' + - 'ata_qc_for_each' + - 'ata_qc_for_each_raw' + - 'ata_qc_for_each_with_internal' + - 'ax25_for_each' + - 'ax25_uid_for_each' + - 'bio_for_each_bvec' + - 'bio_for_each_bvec_all' + - 'bio_for_each_folio_all' + - 'bio_for_each_integrity_vec' + - 'bio_for_each_segment' + - 'bio_for_each_segment_all' + - 'bio_list_for_each' + - 'bip_for_each_vec' + - 'bond_for_each_slave' + - 'bond_for_each_slave_rcu' + - 'bpf_for_each' + - 'bpf_for_each_reg_in_vstate' + - 'bpf_for_each_reg_in_vstate_mask' + - 'bpf_for_each_spilled_reg' + - 'bpf_object__for_each_map' + - 'bpf_object__for_each_program' + - 'btree_for_each_safe128' + - 'btree_for_each_safe32' + - 'btree_for_each_safe64' + - 'btree_for_each_safel' + - 'card_for_each_dev' + - 'cgroup_taskset_for_each' + - 'cgroup_taskset_for_each_leader' + - 'cpu_aggr_map__for_each_idx' + - 'cpufreq_for_each_efficient_entry_idx' + - 'cpufreq_for_each_entry' + - 'cpufreq_for_each_entry_idx' + - 'cpufreq_for_each_valid_entry' + - 'cpufreq_for_each_valid_entry_idx' + - 'css_for_each_child' + - 'css_for_each_descendant_post' + - 'css_for_each_descendant_pre' + - 'damon_for_each_region' + - 'damon_for_each_region_from' + - 'damon_for_each_region_safe' + - 'damon_for_each_scheme' + - 'damon_for_each_scheme_safe' + - 'damon_for_each_target' + - 'damon_for_each_target_safe' + - 'damos_for_each_filter' + - 'damos_for_each_filter_safe' + - 'damos_for_each_ops_filter' + - 'damos_for_each_ops_filter_safe' + - 'damos_for_each_quota_goal' + - 'damos_for_each_quota_goal_safe' + - 'data__for_each_file' + - 'data__for_each_file_new' + - 'data__for_each_file_start' + - 'def_for_each_cpu' + - 'device_for_each_child_node' + - 'device_for_each_child_node_scoped' + - 'dma_fence_array_for_each' + - 'dma_fence_chain_for_each' + - 'dma_fence_unwrap_for_each' + - 'dma_resv_for_each_fence' + - 'dma_resv_for_each_fence_unlocked' + - 'do_for_each_ftrace_op' + - 'drm_atomic_crtc_for_each_plane' + - 'drm_atomic_crtc_state_for_each_plane' + - 'drm_atomic_crtc_state_for_each_plane_state' + - 'drm_atomic_for_each_plane_damage' + - 'drm_client_for_each_connector_iter' + - 'drm_client_for_each_modeset' + - 'drm_connector_for_each_possible_encoder' + - 'drm_exec_for_each_locked_object' + - 'drm_exec_for_each_locked_object_reverse' + - 'drm_for_each_bridge_in_chain' + - 'drm_for_each_connector_iter' + - 'drm_for_each_crtc' + - 'drm_for_each_crtc_reverse' + - 'drm_for_each_encoder' + - 'drm_for_each_encoder_mask' + - 'drm_for_each_fb' + - 'drm_for_each_legacy_plane' + - 'drm_for_each_plane' + - 'drm_for_each_plane_mask' + - 'drm_for_each_privobj' + - 'drm_gem_for_each_gpuvm_bo' + - 'drm_gem_for_each_gpuvm_bo_safe' + - 'drm_gpusvm_for_each_range' + - 'drm_gpuva_for_each_op' + - 'drm_gpuva_for_each_op_from_reverse' + - 'drm_gpuva_for_each_op_reverse' + - 'drm_gpuva_for_each_op_safe' + - 'drm_gpuvm_bo_for_each_va' + - 'drm_gpuvm_bo_for_each_va_safe' + - 'drm_gpuvm_for_each_va' + - 'drm_gpuvm_for_each_va_range' + - 'drm_gpuvm_for_each_va_range_safe' + - 'drm_gpuvm_for_each_va_safe' + - 'drm_mm_for_each_hole' + - 'drm_mm_for_each_node' + - 'drm_mm_for_each_node_in_range' + - 'drm_mm_for_each_node_safe' + - 'dsa_switch_for_each_available_port' + - 'dsa_switch_for_each_cpu_port' + - 'dsa_switch_for_each_cpu_port_continue_reverse' + - 'dsa_switch_for_each_port' + - 'dsa_switch_for_each_port_continue_reverse' + - 'dsa_switch_for_each_port_safe' + - 'dsa_switch_for_each_user_port' + - 'dsa_switch_for_each_user_port_continue_reverse' + - 'dsa_tree_for_each_cpu_port' + - 'dsa_tree_for_each_user_port' + - 'dsa_tree_for_each_user_port_continue_reverse' + - 'dso__for_each_symbol' + - 'elf_hash_for_each_possible' + - 'elf_symtab__for_each_symbol' + - 'evlist__for_each_cpu' + - 'evlist__for_each_entry' + - 'evlist__for_each_entry_continue' + - 'evlist__for_each_entry_from' + - 'evlist__for_each_entry_reverse' + - 'evlist__for_each_entry_safe' + - 'flow_action_for_each' + - 'for_each_acpi_consumer_dev' + - 'for_each_acpi_dev_match' + - 'for_each_active_dev_scope' + - 'for_each_active_drhd_unit' + - 'for_each_active_iommu' + - 'for_each_active_irq' + - 'for_each_active_route' + - 'for_each_aggr_pgid' + - 'for_each_alloc_capable_rdt_resource' + - 'for_each_and_bit' + - 'for_each_andnot_bit' + - 'for_each_available_child_of_node' + - 'for_each_available_child_of_node_scoped' + - 'for_each_bench' + - 'for_each_bio' + - 'for_each_board_func_rsrc' + - 'for_each_btf_ext_rec' + - 'for_each_btf_ext_sec' + - 'for_each_bvec' + - 'for_each_capable_rdt_resource' + - 'for_each_card_auxs' + - 'for_each_card_auxs_safe' + - 'for_each_card_components' + - 'for_each_card_dapms' + - 'for_each_card_pre_auxs' + - 'for_each_card_prelinks' + - 'for_each_card_rtds' + - 'for_each_card_rtds_safe' + - 'for_each_card_widgets' + - 'for_each_card_widgets_safe' + - 'for_each_cgroup_storage_type' + - 'for_each_child_of_node' + - 'for_each_child_of_node_scoped' + - 'for_each_child_of_node_with_prefix' + - 'for_each_clear_bit' + - 'for_each_clear_bit_from' + - 'for_each_clear_bitrange' + - 'for_each_clear_bitrange_from' + - 'for_each_cmd' + - 'for_each_cmsghdr' + - 'for_each_collection' + - 'for_each_comp_order' + - 'for_each_compatible_node' + - 'for_each_component_dais' + - 'for_each_component_dais_safe' + - 'for_each_conduit' + - 'for_each_console' + - 'for_each_console_srcu' + - 'for_each_cpu' + - 'for_each_cpu_and' + - 'for_each_cpu_andnot' + - 'for_each_cpu_from' + - 'for_each_cpu_or' + - 'for_each_cpu_wrap' + - 'for_each_dapm_widgets' + - 'for_each_dedup_cand' + - 'for_each_dev_addr' + - 'for_each_dev_scope' + - 'for_each_dma_cap_mask' + - 'for_each_dpcm_be' + - 'for_each_dpcm_be_rollback' + - 'for_each_dpcm_be_safe' + - 'for_each_dpcm_fe' + - 'for_each_drhd_unit' + - 'for_each_dss_dev' + - 'for_each_efi_memory_desc' + - 'for_each_efi_memory_desc_in_map' + - 'for_each_element' + - 'for_each_element_extid' + - 'for_each_element_id' + - 'for_each_enabled_cpu' + - 'for_each_endpoint_of_node' + - 'for_each_event' + - 'for_each_event_tps' + - 'for_each_evictable_lru' + - 'for_each_fib6_node_rt_rcu' + - 'for_each_fib6_walker_rt' + - 'for_each_file_lock' + - 'for_each_free_mem_pfn_range_in_zone_from' + - 'for_each_free_mem_range' + - 'for_each_free_mem_range_reverse' + - 'for_each_func_rsrc' + - 'for_each_gpiochip_node' + - 'for_each_group_evsel' + - 'for_each_group_evsel_head' + - 'for_each_group_member' + - 'for_each_group_member_head' + - 'for_each_hstate' + - 'for_each_hwgpio' + - 'for_each_hwgpio_in_range' + - 'for_each_if' + - 'for_each_inject_fn' + - 'for_each_insn' + - 'for_each_insn_op_loc' + - 'for_each_insn_prefix' + - 'for_each_intid' + - 'for_each_iommu' + - 'for_each_ip_tunnel_rcu' + - 'for_each_irq_desc' + - 'for_each_irq_nr' + - 'for_each_lang' + - 'for_each_link_ch_maps' + - 'for_each_link_codecs' + - 'for_each_link_cpus' + - 'for_each_link_platforms' + - 'for_each_lru' + - 'for_each_matching_node' + - 'for_each_matching_node_and_match' + - 'for_each_media_entity_data_link' + - 'for_each_mem_pfn_range' + - 'for_each_mem_range' + - 'for_each_mem_range_rev' + - 'for_each_mem_region' + - 'for_each_member' + - 'for_each_memory' + - 'for_each_migratetype_order' + - 'for_each_missing_reg' + - 'for_each_mle_subelement' + - 'for_each_mod_mem_type' + - 'for_each_mon_capable_rdt_resource' + - 'for_each_mp_bvec' + - 'for_each_net' + - 'for_each_net_continue_reverse' + - 'for_each_net_rcu' + - 'for_each_netdev' + - 'for_each_netdev_continue' + - 'for_each_netdev_continue_rcu' + - 'for_each_netdev_continue_reverse' + - 'for_each_netdev_dump' + - 'for_each_netdev_feature' + - 'for_each_netdev_in_bond_rcu' + - 'for_each_netdev_rcu' + - 'for_each_netdev_reverse' + - 'for_each_netdev_safe' + - 'for_each_new_connector_in_state' + - 'for_each_new_crtc_in_state' + - 'for_each_new_mst_mgr_in_state' + - 'for_each_new_plane_in_state' + - 'for_each_new_plane_in_state_reverse' + - 'for_each_new_private_obj_in_state' + - 'for_each_new_reg' + - 'for_each_nhlt_endpoint' + - 'for_each_nhlt_endpoint_fmtcfg' + - 'for_each_nhlt_fmtcfg' + - 'for_each_node' + - 'for_each_node_by_name' + - 'for_each_node_by_type' + - 'for_each_node_mask' + - 'for_each_node_numadist' + - 'for_each_node_state' + - 'for_each_node_with_cpus' + - 'for_each_node_with_property' + - 'for_each_nonreserved_multicast_dest_pgid' + - 'for_each_numa_hop_mask' + - 'for_each_of_allnodes' + - 'for_each_of_allnodes_from' + - 'for_each_of_cpu_node' + - 'for_each_of_graph_port' + - 'for_each_of_graph_port_endpoint' + - 'for_each_of_pci_range' + - 'for_each_old_connector_in_state' + - 'for_each_old_crtc_in_state' + - 'for_each_old_mst_mgr_in_state' + - 'for_each_old_plane_in_state' + - 'for_each_old_private_obj_in_state' + - 'for_each_oldnew_connector_in_state' + - 'for_each_oldnew_crtc_in_state' + - 'for_each_oldnew_mst_mgr_in_state' + - 'for_each_oldnew_plane_in_state' + - 'for_each_oldnew_plane_in_state_reverse' + - 'for_each_oldnew_private_obj_in_state' + - 'for_each_online_cpu' + - 'for_each_online_cpu_wrap' + - 'for_each_online_node' + - 'for_each_online_pgdat' + - 'for_each_or_bit' + - 'for_each_page_ext' + - 'for_each_path' + - 'for_each_pci_bridge' + - 'for_each_pci_dev' + - 'for_each_pcm_streams' + - 'for_each_physmem_range' + - 'for_each_populated_zone' + - 'for_each_possible_cpu' + - 'for_each_possible_cpu_wrap' + - 'for_each_present_blessed_reg' + - 'for_each_present_cpu' + - 'for_each_present_section_nr' + - 'for_each_prime_number' + - 'for_each_prime_number_from' + - 'for_each_probe_cache_entry' + - 'for_each_process' + - 'for_each_process_thread' + - 'for_each_prop_codec_conf' + - 'for_each_prop_dai_codec' + - 'for_each_prop_dai_cpu' + - 'for_each_prop_dlc_codecs' + - 'for_each_prop_dlc_cpus' + - 'for_each_prop_dlc_platforms' + - 'for_each_property_of_node' + - 'for_each_rdt_resource' + - 'for_each_reg' + - 'for_each_reg_filtered' + - 'for_each_reloc' + - 'for_each_reloc_from' + - 'for_each_requested_gpio' + - 'for_each_requested_gpio_in_range' + - 'for_each_reserved_child_of_node' + - 'for_each_reserved_mem_range' + - 'for_each_reserved_mem_region' + - 'for_each_rtd_ch_maps' + - 'for_each_rtd_codec_dais' + - 'for_each_rtd_components' + - 'for_each_rtd_cpu_dais' + - 'for_each_rtd_dais' + - 'for_each_rtd_dais_reverse' + - 'for_each_sband_iftype_data' + - 'for_each_script' + - 'for_each_sec' + - 'for_each_set_bit' + - 'for_each_set_bit_from' + - 'for_each_set_bit_wrap' + - 'for_each_set_bitrange' + - 'for_each_set_bitrange_from' + - 'for_each_set_clump8' + - 'for_each_sg' + - 'for_each_sg_dma_page' + - 'for_each_sg_page' + - 'for_each_sgtable_dma_page' + - 'for_each_sgtable_dma_sg' + - 'for_each_sgtable_page' + - 'for_each_sgtable_sg' + - 'for_each_sibling_event' + - 'for_each_sta_active_link' + - 'for_each_subelement' + - 'for_each_subelement_extid' + - 'for_each_subelement_id' + - 'for_each_sublist' + - 'for_each_subsystem' + - 'for_each_suite' + - 'for_each_supported_activate_fn' + - 'for_each_supported_inject_fn' + - 'for_each_sym' + - 'for_each_thread' + - 'for_each_token' + - 'for_each_unicast_dest_pgid' + - 'for_each_valid_link' + - 'for_each_vif_active_link' + - 'for_each_vma' + - 'for_each_vma_range' + - 'for_each_vsi' + - 'for_each_wakeup_source' + - 'for_each_zone' + - 'for_each_zone_zonelist' + - 'for_each_zone_zonelist_nodemask' + - 'func_for_each_insn' + - 'fwnode_for_each_available_child_node' + - 'fwnode_for_each_child_node' + - 'fwnode_for_each_parent_node' + - 'fwnode_graph_for_each_endpoint' + - 'gadget_for_each_ep' + - 'genradix_for_each' + - 'genradix_for_each_from' + - 'genradix_for_each_reverse' + - 'hash_for_each' + - 'hash_for_each_possible' + - 'hash_for_each_possible_rcu' + - 'hash_for_each_possible_rcu_notrace' + - 'hash_for_each_possible_safe' + - 'hash_for_each_rcu' + - 'hash_for_each_safe' + - 'hashmap__for_each_entry' + - 'hashmap__for_each_entry_safe' + - 'hashmap__for_each_key_entry' + - 'hashmap__for_each_key_entry_safe' + - 'hctx_for_each_ctx' + - 'hists__for_each_format' + - 'hists__for_each_sort_list' + - 'hlist_bl_for_each_entry' + - 'hlist_bl_for_each_entry_rcu' + - 'hlist_bl_for_each_entry_safe' + - 'hlist_for_each' + - 'hlist_for_each_entry' + - 'hlist_for_each_entry_continue' + - 'hlist_for_each_entry_continue_rcu' + - 'hlist_for_each_entry_continue_rcu_bh' + - 'hlist_for_each_entry_from' + - 'hlist_for_each_entry_from_rcu' + - 'hlist_for_each_entry_rcu' + - 'hlist_for_each_entry_rcu_bh' + - 'hlist_for_each_entry_rcu_notrace' + - 'hlist_for_each_entry_safe' + - 'hlist_for_each_entry_srcu' + - 'hlist_for_each_safe' + - 'hlist_nulls_for_each_entry' + - 'hlist_nulls_for_each_entry_from' + - 'hlist_nulls_for_each_entry_rcu' + - 'hlist_nulls_for_each_entry_safe' + - 'i3c_bus_for_each_i2cdev' + - 'i3c_bus_for_each_i3cdev' + - 'idr_for_each_entry' + - 'idr_for_each_entry_continue' + - 'idr_for_each_entry_continue_ul' + - 'idr_for_each_entry_ul' + - 'iio_for_each_active_channel' + - 'in_dev_for_each_ifa_rcu' + - 'in_dev_for_each_ifa_rtnl' + - 'in_dev_for_each_ifa_rtnl_net' + - 'inet_bind_bucket_for_each' + - 'interval_tree_for_each_span' + - 'intlist__for_each_entry' + - 'intlist__for_each_entry_safe' + - 'kcore_copy__for_each_phdr' + - 'key_for_each' + - 'key_for_each_safe' + - 'klp_for_each_func' + - 'klp_for_each_func_safe' + - 'klp_for_each_func_static' + - 'klp_for_each_object' + - 'klp_for_each_object_safe' + - 'klp_for_each_object_static' + - 'kunit_suite_for_each_test_case' + - 'kvm_for_each_memslot' + - 'kvm_for_each_memslot_in_gfn_range' + - 'kvm_for_each_vcpu' + - 'libbpf_nla_for_each_attr' + - 'list_for_each' + - 'list_for_each_codec' + - 'list_for_each_codec_safe' + - 'list_for_each_continue' + - 'list_for_each_entry' + - 'list_for_each_entry_continue' + - 'list_for_each_entry_continue_rcu' + - 'list_for_each_entry_continue_reverse' + - 'list_for_each_entry_from' + - 'list_for_each_entry_from_rcu' + - 'list_for_each_entry_from_reverse' + - 'list_for_each_entry_lockless' + - 'list_for_each_entry_rcu' + - 'list_for_each_entry_reverse' + - 'list_for_each_entry_safe' + - 'list_for_each_entry_safe_continue' + - 'list_for_each_entry_safe_from' + - 'list_for_each_entry_safe_reverse' + - 'list_for_each_entry_srcu' + - 'list_for_each_from' + - 'list_for_each_prev' + - 'list_for_each_prev_safe' + - 'list_for_each_rcu' + - 'list_for_each_safe' + - 'llist_for_each' + - 'llist_for_each_entry' + - 'llist_for_each_entry_safe' + - 'llist_for_each_safe' + - 'lwq_for_each_safe' + - 'map__for_each_symbol' + - 'map__for_each_symbol_by_name' + - 'mas_for_each' + - 'mas_for_each_rev' + - 'mci_for_each_dimm' + - 'media_device_for_each_entity' + - 'media_device_for_each_intf' + - 'media_device_for_each_link' + - 'media_device_for_each_pad' + - 'media_entity_for_each_pad' + - 'media_pipeline_for_each_entity' + - 'media_pipeline_for_each_pad' + - 'mlx5_lag_for_each_peer_mdev' + - 'mptcp_for_each_subflow' + - 'msi_domain_for_each_desc' + - 'msi_for_each_desc' + - 'mt_for_each' + - 'nanddev_io_for_each_block' + - 'nanddev_io_for_each_page' + - 'neigh_for_each_in_bucket' + - 'neigh_for_each_in_bucket_rcu' + - 'neigh_for_each_in_bucket_safe' + - 'netdev_for_each_lower_dev' + - 'netdev_for_each_lower_private' + - 'netdev_for_each_lower_private_rcu' + - 'netdev_for_each_mc_addr' + - 'netdev_for_each_synced_mc_addr' + - 'netdev_for_each_synced_uc_addr' + - 'netdev_for_each_uc_addr' + - 'netdev_for_each_upper_dev_rcu' + - 'netdev_hw_addr_list_for_each' + - 'nft_rule_for_each_expr' + - 'nla_for_each_attr' + - 'nla_for_each_attr_type' + - 'nla_for_each_nested' + - 'nla_for_each_nested_type' + - 'nlmsg_for_each_attr' + - 'nlmsg_for_each_msg' + - 'nr_neigh_for_each' + - 'nr_neigh_for_each_safe' + - 'nr_node_for_each' + - 'nr_node_for_each_safe' + - 'of_for_each_phandle' + - 'of_property_for_each_string' + - 'of_property_for_each_u32' + - 'pci_bus_for_each_resource' + - 'pci_dev_for_each_resource' + - 'pcl_for_each_chunk' + - 'pcl_for_each_segment' + - 'pcm_for_each_format' + - 'perf_config_items__for_each_entry' + - 'perf_config_sections__for_each_entry' + - 'perf_config_set__for_each_entry' + - 'perf_cpu_map__for_each_cpu' + - 'perf_cpu_map__for_each_cpu_skip_any' + - 'perf_cpu_map__for_each_idx' + - 'perf_evlist__for_each_entry' + - 'perf_evlist__for_each_entry_reverse' + - 'perf_evlist__for_each_entry_safe' + - 'perf_evlist__for_each_evsel' + - 'perf_evlist__for_each_mmap' + - 'perf_evsel_for_each_per_thread_period_safe' + - 'perf_hpp_list__for_each_format' + - 'perf_hpp_list__for_each_format_safe' + - 'perf_hpp_list__for_each_sort_list' + - 'perf_hpp_list__for_each_sort_list_safe' + - 'plist_for_each' + - 'plist_for_each_continue' + - 'plist_for_each_entry' + - 'plist_for_each_entry_continue' + - 'plist_for_each_entry_safe' + - 'plist_for_each_safe' + - 'pnp_for_each_card' + - 'pnp_for_each_dev' + - 'protocol_for_each_card' + - 'protocol_for_each_dev' + - 'queue_for_each_hw_ctx' + - 'radix_tree_for_each_slot' + - 'radix_tree_for_each_tagged' + - 'rb_for_each' + - 'rbtree_postorder_for_each_entry_safe' + - 'rdma_for_each_block' + - 'rdma_for_each_port' + - 'rdma_umem_for_each_dma_block' + - 'resource_list_for_each_entry' + - 'resource_list_for_each_entry_safe' + - 'rhl_for_each_entry_rcu' + - 'rhl_for_each_rcu' + - 'rht_for_each' + - 'rht_for_each_entry' + - 'rht_for_each_entry_from' + - 'rht_for_each_entry_rcu' + - 'rht_for_each_entry_rcu_from' + - 'rht_for_each_entry_safe' + - 'rht_for_each_from' + - 'rht_for_each_rcu' + - 'rht_for_each_rcu_from' + - 'rq_for_each_bvec' + - 'rq_for_each_segment' + - 'rq_list_for_each' + - 'rq_list_for_each_safe' + - 'sample_read_group__for_each' + - 'scsi_for_each_prot_sg' + - 'scsi_for_each_sg' + - 'sctp_for_each_hentry' + - 'sctp_skb_for_each' + - 'sec_for_each_insn' + - 'sec_for_each_insn_continue' + - 'sec_for_each_insn_from' + - 'sec_for_each_sym' + - 'shdma_for_each_chan' + - 'shost_for_each_device' + - 'sk_for_each' + - 'sk_for_each_bound' + - 'sk_for_each_bound_safe' + - 'sk_for_each_entry_offset_rcu' + - 'sk_for_each_from' + - 'sk_for_each_rcu' + - 'sk_for_each_safe' + - 'sk_nulls_for_each' + - 'sk_nulls_for_each_from' + - 'sk_nulls_for_each_rcu' + - 'snd_array_for_each' + - 'snd_pcm_group_for_each_entry' + - 'snd_soc_dapm_widget_for_each_path' + - 'snd_soc_dapm_widget_for_each_path_safe' + - 'snd_soc_dapm_widget_for_each_sink_path' + - 'snd_soc_dapm_widget_for_each_source_path' + - 'sparsebit_for_each_set_range' + - 'strlist__for_each_entry' + - 'strlist__for_each_entry_safe' + - 'sym_for_each_insn' + - 'sym_for_each_insn_continue_reverse' + - 'symbols__for_each_entry' + - 'tb_property_for_each' + - 'tcf_act_for_each_action' + - 'tcf_exts_for_each_action' + - 'test_suite__for_each_test_case' + - 'tool_pmu__for_each_event' + - 'ttm_bo_lru_for_each_reserved_guarded' + - 'ttm_resource_manager_for_each_res' + - 'udp_lrpa_for_each_entry_rcu' + - 'udp_portaddr_for_each_entry' + - 'udp_portaddr_for_each_entry_rcu' + - 'usb_hub_for_each_child' + - 'v4l2_device_for_each_subdev' + - 'v4l2_m2m_for_each_dst_buf' + - 'v4l2_m2m_for_each_dst_buf_safe' + - 'v4l2_m2m_for_each_src_buf' + - 'v4l2_m2m_for_each_src_buf_safe' + - 'virtio_device_for_each_vq' + - 'vkms_config_for_each_connector' + - 'vkms_config_for_each_crtc' + - 'vkms_config_for_each_encoder' + - 'vkms_config_for_each_plane' + - 'vkms_config_connector_for_each_possible_encoder' + - 'vkms_config_encoder_for_each_possible_crtc' + - 'vkms_config_plane_for_each_possible_crtc' + - 'while_for_each_ftrace_op' + - 'workloads__for_each' + - 'xa_for_each' + - 'xa_for_each_marked' + - 'xa_for_each_range' + - 'xa_for_each_start' + - 'xas_for_each' + - 'xas_for_each_conflict' + - 'xas_for_each_marked' + - 'xbc_array_for_each_value' + - 'xbc_for_each_key_value' + - 'xbc_node_for_each_array_value' + - 'xbc_node_for_each_child' + - 'xbc_node_for_each_key_value' + - 'xbc_node_for_each_subkey' + - 'ynl_attr_for_each' + - 'ynl_attr_for_each_nested' + - 'ynl_attr_for_each_payload' + - 'zorro_for_each_dev' + +IncludeBlocks: Preserve +IncludeCategories: + - Regex: '.*' + Priority: 1 +IncludeIsMainRegex: '(Test)?$' +IndentCaseLabels: false +IndentGotoLabels: false +IndentPPDirectives: None +IndentWidth: 8 +IndentWrappedFunctionNames: false +JavaScriptQuotes: Leave +JavaScriptWrapImports: true +KeepEmptyLinesAtTheStartOfBlocks: false +MacroBlockBegin: '' +MacroBlockEnd: '' +MaxEmptyLinesToKeep: 1 +NamespaceIndentation: None +ObjCBinPackProtocolList: Auto +ObjCBlockIndentWidth: 8 +ObjCSpaceAfterProperty: true +ObjCSpaceBeforeProtocolList: true + +# Taken from git's rules +PenaltyBreakAssignment: 10 +PenaltyBreakBeforeFirstCallParameter: 30 +PenaltyBreakComment: 10 +PenaltyBreakFirstLessLess: 0 +PenaltyBreakString: 10 +PenaltyExcessCharacter: 100 +PenaltyReturnTypeOnItsOwnLine: 60 + +PointerAlignment: Right +ReflowComments: false +SortIncludes: false +SortUsingDeclarations: false +SpaceAfterCStyleCast: false +SpaceAfterTemplateKeyword: true +SpaceBeforeAssignmentOperators: true +SpaceBeforeCtorInitializerColon: true +SpaceBeforeInheritanceColon: true +SpaceBeforeParens: ControlStatementsExceptForEachMacros +SpaceBeforeRangeBasedForLoopColon: true +SpaceInEmptyParentheses: false +SpacesBeforeTrailingComments: 1 +SpacesInAngles: false +SpacesInContainerLiterals: false +SpacesInCStyleCastParentheses: false +SpacesInParentheses: false +SpacesInSquareBrackets: false +Standard: Cpp03 +TabWidth: 8 +UseTab: Always +... diff --git a/.gitignore b/.gitignore index 6d85b3aa238..fa2db08dead 100644 --- a/.gitignore +++ b/.gitignore @@ -58,6 +58,7 @@ fit-dtb.blob* # # We don't want to ignore the following even if they are dot-files # +!.clang-format !.get_maintainer.* !.gitattributes !.gitignore -- cgit v1.2.3 From aa711ac815618bdc2c992c4b3869f6ef27b80202 Mon Sep 17 00:00:00 2001 From: Javier Tia Date: Fri, 5 Sep 2025 14:53:45 -0600 Subject: tools: zynqmp_psu_init_minimize.sh: Switch to clang-format Replace the use of scripts/Lindent with clang-format in zynqmp_psu_init_minimize.sh. This change is made to align with the rest of the codebase that uses clang-format for code formatting. This ensures consistency across all scripts in terms of code style and formatting. Tested-by: Michal Simek Signed-off-by: Javier Tia --- tools/zynqmp_psu_init_minimize.sh | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/tools/zynqmp_psu_init_minimize.sh b/tools/zynqmp_psu_init_minimize.sh index 5c8b73703bf..f8b729ebc97 100755 --- a/tools/zynqmp_psu_init_minimize.sh +++ b/tools/zynqmp_psu_init_minimize.sh @@ -82,7 +82,7 @@ for i in $FUNCS_TO_REMOVE; do sed -i "/$i/,/^}$/d" ${OUT} done -scripts/Lindent ${OUT} +clang-format -i -style=file ${OUT} # Prepend 'static' to internal functions sed -i 's/^.*data(void)$/static &/g' ${OUT} -- cgit v1.2.3 From 1b5a8ff3fdf607656097761174abe4b7473b89db Mon Sep 17 00:00:00 2001 From: Javier Tia Date: Fri, 5 Sep 2025 14:53:46 -0600 Subject: Lindent: Remove wrapper around indent tool The Linux kernel has not maintained the same script since 2017-11-01, and with clang-format included in U-Boot, it is not required anymore. Signed-off-by: Javier Tia --- scripts/Lindent | 18 ------------------ 1 file changed, 18 deletions(-) delete mode 100755 scripts/Lindent diff --git a/scripts/Lindent b/scripts/Lindent deleted file mode 100755 index 9c4b3e2b709..00000000000 --- a/scripts/Lindent +++ /dev/null @@ -1,18 +0,0 @@ -#!/bin/sh -PARAM="-npro -kr -i8 -ts8 -sob -l80 -ss -ncs -cp1" -RES=`indent --version` -V1=`echo $RES | cut -d' ' -f3 | cut -d'.' -f1` -V2=`echo $RES | cut -d' ' -f3 | cut -d'.' -f2` -V3=`echo $RES | cut -d' ' -f3 | cut -d'.' -f3` -if [ $V1 -gt 2 ]; then - PARAM="$PARAM -il0" -elif [ $V1 -eq 2 ]; then - if [ $V2 -gt 2 ]; then - PARAM="$PARAM -il0"; - elif [ $V2 -eq 2 ]; then - if [ $V3 -ge 10 ]; then - PARAM="$PARAM -il0" - fi - fi -fi -indent $PARAM "$@" -- cgit v1.2.3 From a9d997685a400e1a08d60056177aefcd159bc2af Mon Sep 17 00:00:00 2001 From: Javier Tia Date: Fri, 5 Sep 2025 14:53:47 -0600 Subject: doc: Update U-Boot coding style guide with clang-format usage The U-Boot coding style guide has been updated to include information about using the `.clang-format` configuration file for automatic code formatting. This ensures consistent formatting across the entire codebase and aligns with Linux kernel coding standards. The goal with introducing a predefined coding style is consistency rather than personal preference. The .clang-format file is copied directly from the Linux kernel without any modifications, ensuring complete compatibility with kernel coding standards. Include comprehensive best practices for using clang-format, specifically guidance on formatting only changed blocks versus entire files, creating separate formatting-only commits for better code review, and leveraging git clang-format for targeted formatting. Add examples of editor integrations. This enhancement will help maintainers and contributors to easily adhere to U-Boot coding standards. Signed-off-by: Javier Tia --- doc/develop/codingstyle.rst | 81 +++++++++++++++++++++++++++++++++++++++++++-- 1 file changed, 79 insertions(+), 2 deletions(-) diff --git a/doc/develop/codingstyle.rst b/doc/develop/codingstyle.rst index bc18b2ebb7b..10bfa747c6c 100644 --- a/doc/develop/codingstyle.rst +++ b/doc/develop/codingstyle.rst @@ -12,8 +12,9 @@ or only minimal changes. The following rules apply: * All contributions to U-Boot should conform to the `Linux kernel - coding style `_ - and the `Lindent script `_. + coding style `_. + U-Boot includes a `.clang-format` configuration file that can be used to + automatically format code according to these standards. * The exception for net files to the `multi-line comment `_ applies only to Linux, not to U-Boot. Only large hunks which are copied @@ -23,6 +24,82 @@ The following rules apply: `_. Use `pylint `_ for checking the code. +Code Formatting with clang-format +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +U-Boot provides a `.clang-format` configuration file that was copied directly +from the Linux kernel without any modifications, ensuring complete compatibility +with kernel coding standards. Here are common ways to use clang-format: + +**Basic usage for single files:** + +.. code-block:: bash + + clang-format -style=file -i + +**Format multiple files:** + +.. code-block:: bash + + find . -name '*.c' -o -name '*.h' | xargs clang-format -style=file -i + +**Integration with git (format only staged changes):** + +.. code-block:: bash + + git clang-format + +**Editor integration examples:** + +* **Vim/Neovim:** Install vim-clang-format plugin +* **Emacs:** Use clang-format.el +* **VSCode:** Install "Clang-Format" extension +* **Most IDEs:** Have built-in or plugin support for clang-format + +The `.clang-format` file in the repository root ensures consistent formatting +across the entire codebase and aligns with Linux kernel coding standards. + +**Disabling clang-format for specific code blocks:** + +In some cases, you may want to disable automatic formatting for specific code +sections, such as carefully formatted tables, assembly code, or imported code +from other projects. Use the following comments to control formatting: + +.. code-block:: c + + // clang-format off + static const struct register_config regs[] = { + { 0x1000, 0x12345678 }, // Base address register + { 0x1004, 0xabcdef00 }, // Control register + { 0x1008, 0x00000001 }, // Status register + }; + // clang-format on + +**Controversial aspects of coding style enforcement:** + +Coding style enforcement can be controversial, and it's difficult to have one +configuration that satisfies everyone's personal preferences. The goal of using +clang-format is consistency across the codebase rather than accommodating +individual preferences. While some developers may disagree with specific +formatting choices, maintaining a uniform style throughout the project makes +code more readable and maintainable for the entire development community. + +**Best practices for formatting:** + +When using clang-format to format code, consider these best practices: + +* **Format only changed blocks:** It's preferred to format only the blocks of + code that have been modified rather than entire files. This keeps diffs + focused on actual changes and makes code reviews easier. + +* **Separate formatting commits:** If you need to format entire files, create + a separate commit containing only formatting changes. This allows reviewers + to easily distinguish between functional changes and pure formatting updates. + +* **Use git clang-format:** The ``git clang-format`` command is particularly + useful as it formats only the lines that have been modified in your current + changes, avoiding unnecessary formatting of unchanged code. + * Use patman to send your patches (``tools/patman/patman -H`` for full instructions). With a few tags in your commits this will check your patches and take care of emailing them. -- cgit v1.2.3 From 7be74f63f7ebeec1665a4f0f1cf3e41c5444518d Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Sat, 6 Sep 2025 02:01:18 +0200 Subject: thermal: Sort the Makefile Sort the Makefile alphabetically. No functional change. Signed-off-by: Marek Vasut --- drivers/thermal/Makefile | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/thermal/Makefile b/drivers/thermal/Makefile index b5ab0fc221f..18ad453f9b1 100644 --- a/drivers/thermal/Makefile +++ b/drivers/thermal/Makefile @@ -4,9 +4,9 @@ # Author: Nitin Garg obj-$(CONFIG_DM_THERMAL) += thermal-uclass.o -obj-$(CONFIG_SANDBOX) += thermal_sandbox.o -obj-$(CONFIG_IMX_THERMAL) += imx_thermal.o obj-$(CONFIG_IMX_SCU_THERMAL) += imx_scu_thermal.o -obj-$(CONFIG_TI_DRA7_THERMAL) += ti-bandgap.o +obj-$(CONFIG_IMX_THERMAL) += imx_thermal.o obj-$(CONFIG_IMX_TMU) += imx_tmu.o +obj-$(CONFIG_SANDBOX) += thermal_sandbox.o +obj-$(CONFIG_TI_DRA7_THERMAL) += ti-bandgap.o obj-$(CONFIG_TI_LM74_THERMAL) += ti-lm74.o -- cgit v1.2.3 From 27fc6a67a4ca0ab565a1135a30b1e132de3bbed8 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Sat, 6 Sep 2025 02:00:53 +0200 Subject: thermal: sandbox: Staticize sandbox_thermal_get_temp() Make sandbox_thermal_get_temp() static, since this is not called outside of the driver. No functional change. Signed-off-by: Marek Vasut --- drivers/thermal/thermal_sandbox.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/thermal/thermal_sandbox.c b/drivers/thermal/thermal_sandbox.c index 9af0d0247cb..b7c567d76cd 100644 --- a/drivers/thermal/thermal_sandbox.c +++ b/drivers/thermal/thermal_sandbox.c @@ -9,7 +9,7 @@ #include #include -int sandbox_thermal_get_temp(struct udevice *dev, int *temp) +static int sandbox_thermal_get_temp(struct udevice *dev, int *temp) { /* Simply return 100 deg C */ *temp = 100; -- cgit v1.2.3 From c6a4b44cdcc11431223a9d9db17de0c587d49c72 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Sun, 7 Sep 2025 01:00:44 +0200 Subject: phy: Reset init count on phy exit failure In case the PHY exit callback reports failure, reset init_count to 0 anyway, so the next attempt at PHY initialization might try to reinitialize the PHY and restore it to normal operation. Signed-off-by: Marek Vasut Reviewed-by: Siddharth Vadapalli --- drivers/phy/phy-uclass.c | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) diff --git a/drivers/phy/phy-uclass.c b/drivers/phy/phy-uclass.c index 714be123856..f8d4fb3b41b 100644 --- a/drivers/phy/phy-uclass.c +++ b/drivers/phy/phy-uclass.c @@ -274,7 +274,7 @@ int generic_phy_exit(struct phy *phy) { struct phy_counts *counts; struct phy_ops const *ops; - int ret; + int ret = 0; if (!generic_phy_valid(phy)) return 0; @@ -292,12 +292,11 @@ int generic_phy_exit(struct phy *phy) if (ret) { dev_err(phy->dev, "PHY: Failed to exit %s: %d.\n", phy->dev->name, ret); - return ret; } } counts->init_count = 0; - return 0; + return ret; } int generic_phy_power_on(struct phy *phy) -- cgit v1.2.3 From 1c735620e19e2ae07705cc38da1552ee6a696ff0 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Sun, 7 Sep 2025 03:00:46 +0200 Subject: board: dhelectronics: Check pointer before access in dh_get_value_from_eeprom_buffer() The eip pointer in dh_get_value_from_eeprom_buffer() might be NULL. The current NULL pointer check happens too late, after the eip was accessed in variable assignment. Reorder the two, so the NULL pointer check happens first, and any access second, otherwise the access may trigger a hang or other undefined behavior. Signed-off-by: Marek Vasut Reviewed-by: Christoph Niedermaier --- board/dhelectronics/common/dh_common.c | 9 ++++++--- 1 file changed, 6 insertions(+), 3 deletions(-) diff --git a/board/dhelectronics/common/dh_common.c b/board/dhelectronics/common/dh_common.c index 8c052c45007..d3a3f0ff11f 100644 --- a/board/dhelectronics/common/dh_common.c +++ b/board/dhelectronics/common/dh_common.c @@ -131,14 +131,17 @@ int dh_read_eeprom_id_page(u8 *eeprom_buffer, const char *alias) int dh_get_value_from_eeprom_buffer(enum eip_request_values request, u8 *data, int data_len, struct eeprom_id_page *eip) { - const char fin_chr = (eip->pl.item_prefix & DH_ITEM_PREFIX_FIN_BIT) ? - DH_ITEM_PREFIX_FIN_FLASHED_CHR : DH_ITEM_PREFIX_FIN_HALF_CHR; - const u8 soc_coded = eip->pl.item_prefix & 0xf; + char fin_chr; + u8 soc_coded; char soc_chr; if (!eip) return -EINVAL; + fin_chr = (eip->pl.item_prefix & DH_ITEM_PREFIX_FIN_BIT) ? + DH_ITEM_PREFIX_FIN_FLASHED_CHR : DH_ITEM_PREFIX_FIN_HALF_CHR; + soc_coded = eip->pl.item_prefix & 0xf; + /* Copy requested data */ switch (request) { case DH_MAC0: -- cgit v1.2.3 From fd396316432ad4a0f2998ea9eee9720be0e5d5f8 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Sun, 7 Sep 2025 03:00:47 +0200 Subject: board: dhelectronics: Use isascii() before isprint() in dh_read_eeprom_id_page() The isprint() checks printability across all 256 characters, some of the upper 128 characters are printable and produce artifacts on UART. Call isascii() first to only consider the bottom 7bit ASCII characters as printable, and then check their printability using isprint(). This fixes a rare misprint in case the ID page content is uninitialized or corrupted. Signed-off-by: Marek Vasut Reviewed-by: Christoph Niedermaier --- board/dhelectronics/common/dh_common.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/board/dhelectronics/common/dh_common.c b/board/dhelectronics/common/dh_common.c index d3a3f0ff11f..6101ecc7ebc 100644 --- a/board/dhelectronics/common/dh_common.c +++ b/board/dhelectronics/common/dh_common.c @@ -88,9 +88,9 @@ int dh_read_eeprom_id_page(u8 *eeprom_buffer, const char *alias) /* Validate header ID */ if (eip->hdr.id[0] != 'D' || eip->hdr.id[1] != 'H' || eip->hdr.id[2] != 'E') { printf("%s: Error validating header ID! (got %c%c%c (0x%02x 0x%02x 0x%02x) != expected DHE)\n", - __func__, isprint(eip->hdr.id[0]) ? eip->hdr.id[0] : '.', - isprint(eip->hdr.id[1]) ? eip->hdr.id[1] : '.', - isprint(eip->hdr.id[2]) ? eip->hdr.id[2] : '.', + __func__, (isascii(eip->hdr.id[0]) && isprint(eip->hdr.id[0])) ? eip->hdr.id[0] : '.', + (isascii(eip->hdr.id[1]) && isprint(eip->hdr.id[1])) ? eip->hdr.id[1] : '.', + (isascii(eip->hdr.id[2]) && isprint(eip->hdr.id[2])) ? eip->hdr.id[2] : '.', eip->hdr.id[0], eip->hdr.id[1], eip->hdr.id[2]); return -EINVAL; } -- cgit v1.2.3 From bb947665f57629404549cb2f6955ab82e0d557b2 Mon Sep 17 00:00:00 2001 From: Gatien Chevallier Date: Fri, 8 Aug 2025 16:03:56 +0200 Subject: ARM: stm32mp: fix RIFSC semaphores acquisition Fix RIFSC semaphores acquisition by not returning an error when the current CID already possess the semaphore. Also fix an incorrect mask for the CID value in the SEMCR register. Signed-off-by: Gatien Chevallier Signed-off-by: Patrice Chotard Reviewed-by: Patrick Delaunay --- arch/arm/mach-stm32mp/stm32mp2/rifsc.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/arch/arm/mach-stm32mp/stm32mp2/rifsc.c b/arch/arm/mach-stm32mp/stm32mp2/rifsc.c index 50dececf77b..136ed68bba1 100644 --- a/arch/arm/mach-stm32mp/stm32mp2/rifsc.c +++ b/arch/arm/mach-stm32mp/stm32mp2/rifsc.c @@ -73,7 +73,8 @@ static int stm32_rif_acquire_semaphore(void *base, u32 id) void *addr = base + RIFSC_RISC_PER0_SEMCR(id); /* Check that the semaphore is available */ - if (!stm32_rif_is_semaphore_available(base, id)) + if (!stm32_rif_is_semaphore_available(base, id) && + FIELD_GET(RIFSC_RISC_SCID_MASK, (readl(addr)) != RIF_CID1)) return -EACCES; setbits_le32(addr, SEMCR_MUTEX); @@ -171,7 +172,7 @@ static int rifsc_check_access(void *base, u32 id) return -EACCES; } if (!stm32_rif_is_semaphore_available(base, id) && - !(FIELD_GET(RIFSC_RISC_SCID_MASK, sem_reg_value) & BIT(RIF_CID1))) { + !(FIELD_GET(RIFSC_RISC_SCID_MASK, sem_reg_value) & RIF_CID1)) { log_debug("Semaphore unavailable for peripheral %d\n", id); return -EACCES; } -- cgit v1.2.3 From 0b5ae33eb31aa1a31d07152f1e59ebfc6c0a5424 Mon Sep 17 00:00:00 2001 From: Gatien Chevallier Date: Fri, 8 Aug 2025 16:03:57 +0200 Subject: ARM: stm32mp: replace RIFSC check access APIs Replace RIFSC check access APIs by grant/release access ones that handle the RIF semaphores. Signed-off-by: Gatien Chevallier Signed-off-by: Patrice Chotard Reviewed-by: Patrick Delaunay --- arch/arm/mach-stm32mp/include/mach/rif.h | 48 ++++++++++-- arch/arm/mach-stm32mp/stm32mp2/rifsc.c | 127 ++++++++++++++++++------------- drivers/clk/stm32/clk-stm32mp25.c | 2 +- 3 files changed, 116 insertions(+), 61 deletions(-) diff --git a/arch/arm/mach-stm32mp/include/mach/rif.h b/arch/arm/mach-stm32mp/include/mach/rif.h index 10b22108120..4f51313980d 100644 --- a/arch/arm/mach-stm32mp/include/mach/rif.h +++ b/arch/arm/mach-stm32mp/include/mach/rif.h @@ -8,19 +8,53 @@ #include +#if IS_ENABLED(CONFIG_STM32MP21X) || IS_ENABLED(CONFIG_STM32MP23X) || IS_ENABLED(CONFIG_STM32MP25X) /** - * stm32_rifsc_check_access - Check RIF accesses for given device node + * stm32_rifsc_grant_access_by_id - Grant RIFSC access for a given peripheral using its ID * - * @device_node Node of the device for which the accesses are checked + * @device_node Node of the peripheral + * @id ID of the peripheral of which access should be granted */ -int stm32_rifsc_check_access(ofnode device_node); +int stm32_rifsc_grant_access_by_id(ofnode device_node, u32 id); /** - * stm32_rifsc_check_access - Check RIF accesses for given id + * stm32_rifsc_grant_access_by_id - Grant RIFSC access for a given peripheral using its node * - * @device_node Node of the device to get a reference on RIFSC - * @id ID of the resource to check + * @id node of the peripheral of which access should be granted */ -int stm32_rifsc_check_access_by_id(ofnode device_node, u32 id); +int stm32_rifsc_grant_access(ofnode device_node); +/** + * stm32_rifsc_release_access_by_id - Release RIFSC access for a given peripheral using its ID + * + * @device_node Node of the peripheral + * @id ID of the peripheral of which access should be released + */ +void stm32_rifsc_release_access_by_id(ofnode device_node, u32 id); + +/** + * stm32_rifsc_release_access_by_id - Release RIFSC access for a given peripheral using its node + * + * @id node of the peripheral of which access should be released + */ +void stm32_rifsc_release_access(ofnode device_node); +#else +static inline int stm32_rifsc_grant_access_by_id(ofnode device_node, u32 id) +{ + return -EACCES; +} + +static inline int stm32_rifsc_grant_access(ofnode device_node) +{ + return -EACCES; +} + +static inline void stm32_rifsc_release_access_by_id(ofnode device_node, u32 id) +{ +} + +static inline void stm32_rifsc_release_access(ofnode device_node) +{ +} +#endif #endif /* MACH_RIF_H*/ diff --git a/arch/arm/mach-stm32mp/stm32mp2/rifsc.c b/arch/arm/mach-stm32mp/stm32mp2/rifsc.c index 136ed68bba1..f8f67af4449 100644 --- a/arch/arm/mach-stm32mp/stm32mp2/rifsc.c +++ b/arch/arm/mach-stm32mp/stm32mp2/rifsc.c @@ -61,43 +61,41 @@ struct stm32_rifsc_child_plat { u32 domain_id; }; -static bool stm32_rif_is_semaphore_available(void *base, u32 id) +static bool stm32_rif_is_semaphore_available(void *addr) { - void *addr = base + RIFSC_RISC_PER0_SEMCR(id); - return !(readl(addr) & SEMCR_MUTEX); } -static int stm32_rif_acquire_semaphore(void *base, u32 id) +static int stm32_rifsc_acquire_semaphore(void *base, u32 id) { void *addr = base + RIFSC_RISC_PER0_SEMCR(id); /* Check that the semaphore is available */ - if (!stm32_rif_is_semaphore_available(base, id) && + if (!stm32_rif_is_semaphore_available(addr) && FIELD_GET(RIFSC_RISC_SCID_MASK, (readl(addr)) != RIF_CID1)) return -EACCES; setbits_le32(addr, SEMCR_MUTEX); /* Check that CID1 has the semaphore */ - if (stm32_rif_is_semaphore_available(base, id) || + if (stm32_rif_is_semaphore_available(addr) || FIELD_GET(RIFSC_RISC_SCID_MASK, (readl(addr)) != RIF_CID1)) return -EACCES; return 0; } -static int stm32_rif_release_semaphore(void *base, u32 id) +static int stm32_rifsc_release_semaphore(void *base, u32 id) { void *addr = base + RIFSC_RISC_PER0_SEMCR(id); - if (stm32_rif_is_semaphore_available(base, id)) + if (stm32_rif_is_semaphore_available(addr)) return 0; clrbits_le32(addr, SEMCR_MUTEX); /* Ok if another compartment takes the semaphore before the check */ - if (!stm32_rif_is_semaphore_available(base, id) && + if (!stm32_rif_is_semaphore_available(addr) && FIELD_GET(RIFSC_RISC_SCID_MASK, (readl(addr)) == RIF_CID1)) return -EACCES; @@ -106,11 +104,10 @@ static int stm32_rif_release_semaphore(void *base, u32 id) static int rifsc_parse_access_controller(ofnode node, struct ofnode_phandle_args *args) { - int ret; + int ret = ofnode_parse_phandle_with_args(node, "access-controllers", + "#access-controller-cells", 0, + 0, args); - ret = ofnode_parse_phandle_with_args(node, "access-controllers", - "#access-controller-cells", 0, - 0, args); if (ret) { log_debug("failed to parse access-controller (%d)\n", ret); return ret; @@ -171,7 +168,7 @@ static int rifsc_check_access(void *base, u32 id) log_debug("Not in semaphore whitelist for peripheral %d\n", id); return -EACCES; } - if (!stm32_rif_is_semaphore_available(base, id) && + if (!stm32_rif_is_semaphore_available(base + RIFSC_RISC_PER0_SEMCR(id)) && !(FIELD_GET(RIFSC_RISC_SCID_MASK, sem_reg_value) & RIF_CID1)) { log_debug("Semaphore unavailable for peripheral %d\n", id); return -EACCES; @@ -188,22 +185,44 @@ skip_cid_check: return 0; } -int stm32_rifsc_check_access_by_id(ofnode device_node, u32 id) +int stm32_rifsc_grant_access_by_id(ofnode device_node, u32 id) { struct ofnode_phandle_args args; + u32 cid_reg_value; + void *rifsc_base; int err; - if (id >= STM32MP25_RIFSC_ENTRIES) - return -EINVAL; - err = rifsc_parse_access_controller(device_node, &args); + if (err) + panic("Failed to parse access-controllers property\n"); + + rifsc_base = (void *)ofnode_get_addr(args.node); + + err = rifsc_check_access(rifsc_base, id); if (err) return err; - return rifsc_check_access((void *)ofnode_get_addr(args.node), id); + cid_reg_value = readl(rifsc_base + RIFSC_RISC_PER0_CIDCFGR(id)); + + /* + * If the peripheral is in semaphore mode, take the semaphore so that + * the CID1 has the ownership. + */ + if (cid_reg_value & CIDCFGR_SEMEN && + (FIELD_GET(RIFSC_RISC_SEMWL_MASK, cid_reg_value) & BIT(RIF_CID1))) { + err = stm32_rifsc_acquire_semaphore(rifsc_base, id); + if (err) { + pr_err("Couldn't acquire RIF semaphore for peripheral %d (%d)\n", + id, err); + return err; + } + pr_debug("Acquiring RIF semaphore for peripheral %d\n", id); + } + + return 0; } -int stm32_rifsc_check_access(ofnode device_node) +int stm32_rifsc_grant_access(ofnode device_node) { struct ofnode_phandle_args args; int err; @@ -212,58 +231,60 @@ int stm32_rifsc_check_access(ofnode device_node) if (err) return err; - return rifsc_check_access((void *)ofnode_get_addr(args.node), args.args[0]); + return stm32_rifsc_grant_access_by_id(device_node, args.args[0]); + } -static int stm32_rifsc_child_pre_probe(struct udevice *dev) +void stm32_rifsc_release_access_by_id(ofnode device_node, u32 id) { - struct stm32_rifsc_plat *plat = dev_get_plat(dev->parent); - struct stm32_rifsc_child_plat *child_plat = dev_get_parent_plat(dev); + struct ofnode_phandle_args args; u32 cid_reg_value; + void *rifsc_base; int err; - u32 id = child_plat->domain_id; - cid_reg_value = readl(plat->base + RIFSC_RISC_PER0_CIDCFGR(id)); + err = rifsc_parse_access_controller(device_node, &args); + if (err) + panic("Failed to parse access-controllers property\n"); - /* - * If the peripheral is in semaphore mode, take the semaphore so that - * the CID1 has the ownership. - */ + rifsc_base = (void *)ofnode_get_addr(args.node); + + cid_reg_value = readl(rifsc_base + RIFSC_RISC_PER0_CIDCFGR(id)); + + /* If the peripheral is in semaphore mode, release it if we have the ownership */ if (cid_reg_value & CIDCFGR_SEMEN && (FIELD_GET(RIFSC_RISC_SEMWL_MASK, cid_reg_value) & BIT(RIF_CID1))) { - err = stm32_rif_acquire_semaphore(plat->base, id); + err = stm32_rifsc_release_semaphore(rifsc_base, id); if (err) { - dev_err(dev, "Couldn't acquire RIF semaphore for peripheral %d (%d)\n", - id, err); - return err; + panic("Couldn't release RIF semaphore for peripheral %d (%d)\n", id, err); } - dev_dbg(dev, "Acquiring semaphore for peripheral %d\n", id); + pr_debug("Releasing RIF semaphore for peripheral %d\n", id); } +} - return 0; +void stm32_rifsc_release_access(ofnode device_node) +{ + struct ofnode_phandle_args args; + int err; + + err = rifsc_parse_access_controller(device_node, &args); + if (err) + panic("Failed to parse access-controllers property\n"); + + stm32_rifsc_release_access_by_id(device_node, args.args[0]); } -static int stm32_rifsc_child_post_remove(struct udevice *dev) +static int stm32_rifsc_child_pre_probe(struct udevice *dev) { - struct stm32_rifsc_plat *plat = dev_get_plat(dev->parent); struct stm32_rifsc_child_plat *child_plat = dev_get_parent_plat(dev); - u32 cid_reg_value; - int err; - u32 id = child_plat->domain_id; - cid_reg_value = readl(plat->base + RIFSC_RISC_PER0_CIDCFGR(id)); + return stm32_rifsc_grant_access_by_id(dev_ofnode(dev), child_plat->domain_id); +} - /* - * If the peripheral is in semaphore mode, release the semaphore so that - * there's no ownership. - */ - if (cid_reg_value & CIDCFGR_SEMEN && - (FIELD_GET(RIFSC_RISC_SEMWL_MASK, cid_reg_value) & BIT(RIF_CID1))) { - err = stm32_rif_release_semaphore(plat->base, id); - if (err) - dev_err(dev, "Couldn't release rif semaphore for peripheral %d (%d)\n", - id, err); - } +static int stm32_rifsc_child_post_remove(struct udevice *dev) +{ + struct stm32_rifsc_child_plat *child_plat = dev_get_parent_plat(dev); + + stm32_rifsc_release_access_by_id(dev_ofnode(dev), child_plat->domain_id); return 0; } diff --git a/drivers/clk/stm32/clk-stm32mp25.c b/drivers/clk/stm32/clk-stm32mp25.c index 18c0b1cb867..b487f33b6c7 100644 --- a/drivers/clk/stm32/clk-stm32mp25.c +++ b/drivers/clk/stm32/clk-stm32mp25.c @@ -430,7 +430,7 @@ static int stm32mp25_check_security(struct udevice *dev, void __iomem *base, u32 index = (u32)cfg->sec_id; if (index & SEC_RIFSC_FLAG) - ret = stm32_rifsc_check_access_by_id(dev_ofnode(dev), + ret = stm32_rifsc_grant_access_by_id(dev_ofnode(dev), index & ~SEC_RIFSC_FLAG); else ret = stm32_rcc_get_access(dev, index); -- cgit v1.2.3 From 08ccc1f56cc70c4116abac3d1cbe392b867d10bf Mon Sep 17 00:00:00 2001 From: Patrice Chotard Date: Thu, 11 Sep 2025 08:59:40 +0200 Subject: ioport: Add resource check helpers Add resource_overlaps() and resource_contains() helpers. Code copied from kernel source. Signed-off-by: Patrice Chotard Reviewed-by: Patrick Delaunay --- include/linux/ioport.h | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/include/linux/ioport.h b/include/linux/ioport.h index 85288c3729a..c12a7f70ad7 100644 --- a/include/linux/ioport.h +++ b/include/linux/ioport.h @@ -135,6 +135,22 @@ static inline unsigned long resource_type(const struct resource *res) return res->flags & IORESOURCE_TYPE_BITS; } +/* True iff r1 completely contains r2 */ +static inline bool resource_contains(struct resource *r1, struct resource *r2) +{ + if (resource_type(r1) != resource_type(r2)) + return false; + if (r1->flags & IORESOURCE_UNSET || r2->flags & IORESOURCE_UNSET) + return false; + return r1->start <= r2->start && r1->end >= r2->end; +} + +/* True if any part of r1 overlaps r2 */ +static inline bool resource_overlaps(struct resource *r1, struct resource *r2) +{ + return r1->start <= r2->end && r1->end >= r2->start; +} + /* Convenience shorthand with allocation */ #define request_region(start,n,name) __request_region(&ioport_resource, (start), (n), (name), 0) #define __request_mem_region(start,n,name, excl) __request_region(&iomem_resource, (start), (n), (name), excl) -- cgit v1.2.3 From b7328e2f39d946f8727d28a12df24fb8f351a0d0 Mon Sep 17 00:00:00 2001 From: Patrice Chotard Date: Thu, 11 Sep 2025 08:59:41 +0200 Subject: memory: Add STM32 Octo Memory Manager driver Octo Memory Manager driver (OMM) manages: - the muxing between 2 OSPI busses and 2 output ports. There are 4 possible muxing configurations: - direct mode (no multiplexing): OSPI1 output is on port 1 and OSPI2 output is on port 2 - OSPI1 and OSPI2 are multiplexed over the same output port 1 - swapped mode (no multiplexing), OSPI1 output is on port 2, OSPI2 output is on port 1 - OSPI1 and OSPI2 are multiplexed over the same output port 2 - the split of the memory area shared between the 2 OSPI instances. - chip select selection override. - the time between 2 transactions in multiplexed mode. - check firewall access. Signed-off-by: Patrice Chotard Reviewed-by: Patrick Delaunay --- MAINTAINERS | 1 + drivers/memory/Kconfig | 17 ++ drivers/memory/Makefile | 1 + drivers/memory/stm32_omm.c | 421 +++++++++++++++++++++++++++++++++++++++++++++ 4 files changed, 440 insertions(+) create mode 100644 drivers/memory/stm32_omm.c diff --git a/MAINTAINERS b/MAINTAINERS index 3fb163aa1db..78bce87a6ca 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -709,6 +709,7 @@ F: drivers/gpio/stm32_gpio.c F: drivers/hwspinlock/stm32_hwspinlock.c F: drivers/i2c/stm32f7_i2c.c F: drivers/mailbox/stm32-ipcc.c +F: drivers/memory/stm32-omm.c F: drivers/misc/stm32mp_fuse.c F: drivers/misc/stm32_rcc.c F: drivers/mmc/stm32_sdmmc2.c diff --git a/drivers/memory/Kconfig b/drivers/memory/Kconfig index 7c40f176987..e31c4532279 100644 --- a/drivers/memory/Kconfig +++ b/drivers/memory/Kconfig @@ -37,6 +37,23 @@ config STM32_FMC2_EBI devices (like SRAM, ethernet adapters, FPGAs, LCD displays, ...) on SOCs containing the FMC2 External Bus Interface. +config STM32_OMM + tristate "STM32 Octo Memory Manager" + depends on ARCH_STM32MP + help + This driver manages the muxing between the 2 OSPI busses and + the 2 output ports. There are 4 possible muxing configurations: + - direct mode (no multiplexing): OSPI1 output is on port 1 and OSPI2 + output is on port 2 + - OSPI1 and OSPI2 are multiplexed over the same output port 1 + - swapped mode (no multiplexing), OSPI1 output is on port 2, + OSPI2 output is on port 1 + - OSPI1 and OSPI2 are multiplexed over the same output port 2 + It also manages : + - the split of the memory area shared between the 2 OSPI instances. + - chip select selection override. + - the time between 2 transactions in multiplexed mode. + config TI_AEMIF tristate "Texas Instruments AEMIF driver" depends on ARCH_KEYSTONE || ARCH_DAVINCI diff --git a/drivers/memory/Makefile b/drivers/memory/Makefile index fdc83e4e1c8..77294fac69d 100644 --- a/drivers/memory/Makefile +++ b/drivers/memory/Makefile @@ -2,6 +2,7 @@ obj-$(CONFIG_MEMORY) += memory-uclass.o obj-$(CONFIG_SANDBOX_MEMORY) += memory-sandbox.o obj-$(CONFIG_STM32_FMC2_EBI) += stm32-fmc2-ebi.o +obj-$(CONFIG_STM32_OMM) += stm32_omm.o obj-$(CONFIG_ATMEL_EBI) += atmel_ebi.o obj-$(CONFIG_TI_AEMIF) += ti-aemif.o ti-aemif-cs.o obj-$(CONFIG_TI_GPMC) += ti-gpmc.o diff --git a/drivers/memory/stm32_omm.c b/drivers/memory/stm32_omm.c new file mode 100644 index 00000000000..d5a4e1b0683 --- /dev/null +++ b/drivers/memory/stm32_omm.c @@ -0,0 +1,421 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR BSD-3-Clause +/* + * Copyright (C) 2025, STMicroelectronics - All Rights Reserved + */ + +#define LOG_CATEGORY UCLASS_NOP + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/* OCTOSPI control register */ +#define OCTOSPIM_CR 0 +#define CR_MUXEN BIT(0) +#define CR_MUXENMODE_MASK GENMASK(1, 0) +#define CR_CSSEL_OVR_EN BIT(4) +#define CR_CSSEL_OVR_MASK GENMASK(6, 5) +#define CR_REQ2ACK_MASK GENMASK(23, 16) + +#define OMM_CHILD_NB 2 +#define OMM_CLK_NB 3 +#define OMM_RESET_NB 3 +#define NSEC_PER_SEC 1000000000L + +struct stm32_omm_plat { + phys_addr_t regs_base; + struct regmap *syscfg_regmap; + struct clk clk[OMM_CLK_NB]; + struct reset_ctl reset_ctl[OMM_RESET_NB]; + resource_size_t mm_ospi2_size; + u32 mux; + u32 cssel_ovr; + u32 req2ack; + u32 amcr_base; + u32 amcr_mask; + unsigned long clk_rate_max; + u8 nb_child; +}; + +static int stm32_omm_set_amcr(struct udevice *dev, bool set) +{ + struct stm32_omm_plat *plat = dev_get_plat(dev); + unsigned int amcr, read_amcr; + + amcr = plat->mm_ospi2_size / SZ_64M; + + if (set) + regmap_update_bits(plat->syscfg_regmap, plat->amcr_base, + plat->amcr_mask, amcr); + + /* read AMCR and check coherency with memory-map areas defined in DT */ + regmap_read(plat->syscfg_regmap, plat->amcr_base, &read_amcr); + read_amcr = read_amcr >> (ffs(plat->amcr_mask) - 1); + + if (amcr != read_amcr) { + dev_err(dev, "AMCR value not coherent with DT memory-map areas\n"); + return -EINVAL; + } + + return 0; +} + +static int stm32_omm_toggle_child_clock(struct udevice *dev, bool enable) +{ + struct stm32_omm_plat *plat = dev_get_plat(dev); + int i, ret; + + for (i = 0; i < plat->nb_child; i++) { + if (enable) { + ret = clk_enable(&plat->clk[i + 1]); + if (ret) { + dev_err(dev, "Can not enable clock\n"); + goto clk_error; + } + } else { + clk_disable(&plat->clk[i + 1]); + } + } + + return 0; + +clk_error: + while (i--) + clk_disable(&plat->clk[i + 1]); + + return ret; +} + +static int stm32_omm_disable_child(struct udevice *dev) +{ + struct stm32_omm_plat *plat = dev_get_plat(dev); + int ret; + u8 i; + + ret = stm32_omm_toggle_child_clock(dev, true); + if (ret) + return ret; + + for (i = 0; i < plat->nb_child; i++) { + /* reset OSPI to ensure CR_EN bit is set to 0 */ + reset_assert(&plat->reset_ctl[i + 1]); + udelay(2); + reset_deassert(&plat->reset_ctl[i + 1]); + } + + return stm32_omm_toggle_child_clock(dev, false); +} + +static int stm32_omm_configure(struct udevice *dev) +{ + struct stm32_omm_plat *plat = dev_get_plat(dev); + int ret; + u32 mux = 0; + u32 cssel_ovr = 0; + u32 req2ack = 0; + + /* Ensure both OSPI instance are disabled before configuring OMM */ + ret = stm32_omm_disable_child(dev); + if (ret) + return ret; + + ret = clk_enable(&plat->clk[0]); + if (ret) { + dev_err(dev, "Failed to enable OMM clock (%d)\n", ret); + return ret; + } + + reset_assert(&plat->reset_ctl[0]); + udelay(2); + reset_deassert(&plat->reset_ctl[0]); + + if (plat->mux & CR_MUXEN) { + if (plat->req2ack) { + req2ack = DIV_ROUND_UP(plat->req2ack, + NSEC_PER_SEC / plat->clk_rate_max) - 1; + if (req2ack > 256) + req2ack = 256; + } + + req2ack = FIELD_PREP(CR_REQ2ACK_MASK, req2ack); + clrsetbits_le32(plat->regs_base + OCTOSPIM_CR, CR_REQ2ACK_MASK, + req2ack); + + /* + * If the mux is enabled, the 2 OSPI clocks have to be + * always enabled + */ + ret = stm32_omm_toggle_child_clock(dev, true); + if (ret) + return ret; + } + + if (plat->cssel_ovr != 0xff) { + cssel_ovr = FIELD_PREP(CR_CSSEL_OVR_MASK, cssel_ovr); + cssel_ovr |= CR_CSSEL_OVR_EN; + clrsetbits_le32(plat->regs_base + OCTOSPIM_CR, CR_CSSEL_OVR_MASK, + cssel_ovr); + } + + mux = FIELD_PREP(CR_MUXENMODE_MASK, plat->mux); + clrsetbits_le32(plat->regs_base + OCTOSPIM_CR, CR_MUXENMODE_MASK, mux); + clk_disable(&plat->clk[0]); + + return stm32_omm_set_amcr(dev, true); +} + +static void stm32_omm_release_childs(ofnode *child_list, u8 nb_child) +{ + u8 i; + + for (i = 0; i < nb_child; i++) + stm32_rifsc_release_access(child_list[i]); +} + +static int stm32_omm_probe(struct udevice *dev) +{ + struct stm32_omm_plat *plat = dev_get_plat(dev); + ofnode child_list[OMM_CHILD_NB]; + ofnode child; + int ret; + u8 child_access_granted = 0; + bool child_access[OMM_CHILD_NB]; + + /* check child's access */ + for (child = ofnode_first_subnode(dev_ofnode(dev)); + ofnode_valid(child); + child = ofnode_next_subnode(child)) { + if (plat->nb_child > OMM_CHILD_NB) { + dev_err(dev, "Bad DT, found too much children\n"); + return -E2BIG; + } + + if (!ofnode_device_is_compatible(child, "st,stm32mp25-ospi")) + return -EINVAL; + + ret = stm32_rifsc_grant_access(child); + if (ret < 0 && ret != -EACCES) + return ret; + + child_access[plat->nb_child] = false; + if (!ret) { + child_access_granted++; + child_access[plat->nb_child] = true; + } + + child_list[plat->nb_child] = child; + plat->nb_child++; + } + + if (plat->nb_child != OMM_CHILD_NB) + return -EINVAL; + + /* check if OMM's resource access is granted */ + ret = stm32_rifsc_grant_access(dev_ofnode(dev)); + if (ret < 0 && ret != -EACCES) + goto end; + + /* All child's access are granted ? */ + if (!ret && child_access_granted == plat->nb_child) { + ret = stm32_omm_configure(dev); + if (ret) + goto end; + } else { + dev_dbg(dev, "Octo Memory Manager resource's access not granted\n"); + /* + * AMCR can't be set, so check if current value is coherent + * with memory-map areas defined in DT + */ + ret = stm32_omm_set_amcr(dev, false); + } + +end: + stm32_omm_release_childs(child_list, plat->nb_child); + stm32_rifsc_release_access(dev_ofnode(dev)); + + return ret; +} + +static int stm32_omm_of_to_plat(struct udevice *dev) +{ + struct stm32_omm_plat *plat = dev_get_plat(dev); + static const char * const clocks_name[] = {"omm", "ospi1", "ospi2"}; + static const char * const mm_name[] = { "ospi1", "ospi2" }; + static const char * const resets_name[] = {"omm", "ospi1", "ospi2"}; + struct resource res, res1, mm_res; + struct ofnode_phandle_args args; + struct udevice *child; + unsigned long clk_rate; + struct clk child_clk; + int ret, idx; + u8 i; + + plat->regs_base = dev_read_addr(dev); + if (plat->regs_base == FDT_ADDR_T_NONE) + return -EINVAL; + + ret = dev_read_resource_byname(dev, "memory_map", &mm_res); + if (ret) { + dev_err(dev, "can't get omm_mm mmap resource(ret = %d)!\n", ret); + return ret; + } + + for (i = 0; i < OMM_CLK_NB; i++) { + ret = clk_get_by_name(dev, clocks_name[i], &plat->clk[i]); + if (ret < 0) { + dev_err(dev, "Can't find I/O manager clock %s\n", clocks_name[i]); + return ret; + } + + ret = reset_get_by_name(dev, resets_name[i], &plat->reset_ctl[i]); + if (ret < 0) { + dev_err(dev, "Can't find I/O manager reset %s\n", resets_name[i]); + return ret; + } + } + + /* parse children's clock */ + plat->clk_rate_max = 0; + device_foreach_child(child, dev) { + ret = clk_get_by_index(child, 0, &child_clk); + if (ret) { + dev_err(dev, "Failed to get clock for %s\n", + dev_read_name(child)); + return ret; + } + + clk_rate = clk_get_rate(&child_clk); + if (!clk_rate) { + dev_err(dev, "Invalid clock rate\n"); + return -EINVAL; + } + + if (clk_rate > plat->clk_rate_max) + plat->clk_rate_max = clk_rate; + } + + plat->mux = dev_read_u32_default(dev, "st,omm-mux", 0); + plat->req2ack = dev_read_u32_default(dev, "st,omm-req2ack-ns", 0); + plat->cssel_ovr = dev_read_u32_default(dev, "st,omm-cssel-ovr", 0xff); + plat->mm_ospi2_size = 0; + + for (i = 0; i < 2; i++) { + idx = dev_read_stringlist_search(dev, "memory-region-names", + mm_name[i]); + if (idx < 0) + continue; + + /* res1 only used on second loop iteration */ + res1.start = res.start; + res1.end = res.end; + + dev_read_phandle_with_args(dev, "memory-region", NULL, 0, idx, + &args); + ret = ofnode_read_resource(args.node, 0, &res); + if (ret) { + dev_err(dev, "unable to resolve memory region\n"); + return ret; + } + + /* check that memory region fits inside OMM memory map area */ + if (!resource_contains(&mm_res, &res)) { + dev_err(dev, "%s doesn't fit inside OMM memory map area\n", + mm_name[i]); + dev_err(dev, "[0x%llx-0x%llx] doesn't fit inside [0x%llx-0x%llx]\n", + res.start, res.end, + mm_res.start, mm_res.end); + + return -EFAULT; + } + + if (i == 1) { + plat->mm_ospi2_size = resource_size(&res); + + /* check that OMM memory region 1 doesn't overlap memory region 2 */ + if (resource_overlaps(&res, &res1)) { + dev_err(dev, "OMM memory-region %s overlaps memory region %s\n", + mm_name[0], mm_name[1]); + dev_err(dev, "[0x%llx-0x%llx] overlaps [0x%llx-0x%llx]\n", + res1.start, res1.end, res.start, res.end); + + return -EFAULT; + } + } + } + + plat->syscfg_regmap = syscon_regmap_lookup_by_phandle(dev, "st,syscfg-amcr"); + if (IS_ERR(plat->syscfg_regmap)) { + dev_err(dev, "Failed to get st,syscfg-amcr property\n"); + ret = PTR_ERR(plat->syscfg_regmap); + return ret; + } + + ret = dev_read_u32_index(dev, "st,syscfg-amcr", 1, &plat->amcr_base); + if (ret) { + dev_err(dev, "Failed to get st,syscfg-amcr base\n"); + return ret; + } + + ret = dev_read_u32_index(dev, "st,syscfg-amcr", 2, &plat->amcr_mask); + if (ret) { + dev_err(dev, "Failed to get st,syscfg-amcr mask\n"); + return ret; + } + + return 0; +}; + +static int stm32_omm_bind(struct udevice *dev) +{ + int ret = 0, err = 0; + ofnode node; + + for (node = ofnode_first_subnode(dev_ofnode(dev)); + ofnode_valid(node); + node = ofnode_next_subnode(node)) { + const char *node_name = ofnode_get_name(node); + + if (!ofnode_is_enabled(node) || stm32_rifsc_grant_access(node)) { + dev_dbg(dev, "%s failed to bind\n", node_name); + continue; + } + + err = lists_bind_fdt(dev, node, NULL, NULL, + gd->flags & GD_FLG_RELOC ? false : true); + if (err && !ret) { + ret = err; + dev_dbg(dev, "%s: ret=%d\n", node_name, ret); + } + } + + if (ret) + dev_dbg(dev, "Some drivers failed to bind\n"); + + return ret; +} + +static const struct udevice_id stm32_omm_ids[] = { + { .compatible = "st,stm32mp25-omm", }, + {}, +}; + +U_BOOT_DRIVER(stm32_omm) = { + .name = "stm32_omm", + .id = UCLASS_NOP, + .probe = stm32_omm_probe, + .of_match = stm32_omm_ids, + .of_to_plat = stm32_omm_of_to_plat, + .plat_auto = sizeof(struct stm32_omm_plat), + .bind = stm32_omm_bind, +}; -- cgit v1.2.3 From 01eb0a583860aa8bb9960427eac3fbcdbeae1f28 Mon Sep 17 00:00:00 2001 From: Patrice Chotard Date: Thu, 11 Sep 2025 08:59:42 +0200 Subject: spi: Add STM32MP2 Octo-SPI driver support Add STM32 OSPI driver, it supports : - support sNOR / sNAND devices. - Two functional modes: indirect (read/write) and memory-mapped (read). - Single-, dual-, quad-, and octal-SPI communication. - Single data rate (SDR). Signed-off-by: Patrice Chotard Reviewed-by: Patrick Delaunay --- MAINTAINERS | 1 + drivers/spi/Kconfig | 8 + drivers/spi/Makefile | 1 + drivers/spi/stm32_ospi.c | 623 +++++++++++++++++++++++++++++++++++++++++++++++ 4 files changed, 633 insertions(+) create mode 100644 drivers/spi/stm32_ospi.c diff --git a/MAINTAINERS b/MAINTAINERS index 78bce87a6ca..af71fb02846 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -726,6 +726,7 @@ F: drivers/rng/optee_rng.c F: drivers/rng/stm32_rng.c F: drivers/rtc/stm32_rtc.c F: drivers/serial/serial_stm32.* +F: drivers/spi/stm32_ospi.c F: drivers/spi/stm32_qspi.c F: drivers/spi/stm32_spi.c F: drivers/video/stm32/stm32_ltdc.c diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig index 1ae36b5a348..2960822211a 100644 --- a/drivers/spi/Kconfig +++ b/drivers/spi/Kconfig @@ -530,6 +530,14 @@ config SPI_SUNXI Same controller driver can reuse in all Allwinner SoC variants. +config STM32_OSPI + bool "STM32MP2 OSPI driver" + depends on STM32MP25X && STM32_OMM + help + Enable the STM32MP2 Octo-SPI (OSPI) driver. This driver can be + used to access the SPI NOR flash chips on platforms embedding + this ST IP core. + config STM32_QSPI bool "STM32F7 QSPI driver" depends on STM32F4 || STM32F7 || ARCH_STM32MP diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile index da91b18b6ed..5129d649f84 100644 --- a/drivers/spi/Makefile +++ b/drivers/spi/Makefile @@ -75,6 +75,7 @@ obj-$(CONFIG_SPI_SIFIVE) += spi-sifive.o obj-$(CONFIG_SPI_SN_F_OSPI) += spi-sn-f-ospi.o obj-$(CONFIG_SPI_SUNXI) += spi-sunxi.o obj-$(CONFIG_SH_QSPI) += sh_qspi.o +obj-$(CONFIG_STM32_OSPI) += stm32_ospi.o obj-$(CONFIG_STM32_QSPI) += stm32_qspi.o obj-$(CONFIG_STM32_SPI) += stm32_spi.o obj-$(CONFIG_TEGRA114_SPI) += tegra114_spi.o diff --git a/drivers/spi/stm32_ospi.c b/drivers/spi/stm32_ospi.c new file mode 100644 index 00000000000..01b8f8e4987 --- /dev/null +++ b/drivers/spi/stm32_ospi.c @@ -0,0 +1,623 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR BSD-3-Clause +/* + * Copyright (C) 2025, STMicroelectronics - All Rights Reserved + */ + +#define LOG_CATEGORY UCLASS_SPI + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/* OCTOSPI control register */ +#define OSPI_CR 0x00 +#define OSPI_CR_EN BIT(0) +#define OSPI_CR_ABORT BIT(1) +#define OSPI_CR_TCEN BIT(3) +#define OSPI_CR_FSEL BIT(7) +#define OSPI_CR_FTHRES_MASK GENMASK(13, 8) +#define OSPI_CR_FTHRES_SHIFT 8 +#define OSPI_CR_CSSEL BIT(24) +#define OSPI_CR_FMODE_SHIFT 28 +#define OSPI_CR_FMODE_MASK GENMASK(29, 28) + +/* OCTOSPI device configuration register */ +#define OSPI_DCR1 0x08 +#define OSPI_DCR1_CKMODE BIT(0) +#define OSPI_DCR1_DLYBYP BIT(3) +#define OSPI_DCR1_CSHT_SHIFT 8 +#define OSPI_DCR1_CSHT_MASK GENMASK(13, 8) +#define OSPI_DCR1_DEVSIZE_MASK GENMASK(20, 16) +#define OSPI_DCR1_MTYP_MASK GENMASK(26, 24) + +/* OCTOSPI device configuration register 2 */ +#define OSPI_DCR2 0x0c +#define OSPI_DCR2_PRESC_SHIFT 0 +#define OSPI_DCR2_PRESC_MASK GENMASK(7, 0) + +/* OCTOSPI status register */ +#define OSPI_SR 0x20 +#define OSPI_SR_TEF BIT(0) +#define OSPI_SR_TCF BIT(1) +#define OSPI_SR_FTF BIT(2) +#define OSPI_SR_BUSY BIT(5) + +/* OCTOSPI flag clear register */ +#define OSPI_FCR 0x24 +#define OSPI_FCR_CTEF BIT(0) +#define OSPI_FCR_CTCF BIT(1) + +/* OCTOSPI data length register */ +#define OSPI_DLR 0x40 + +/* OCTOSPI address register */ +#define OSPI_AR 0x48 + +/* OCTOSPI data configuration register */ +#define OSPI_DR 0x50 + +/* OCTOSPI communication configuration register */ +#define OSPI_CCR 0x100 +#define OSPI_CCR_IMODE_SHIFT 0 +#define OSPI_CCR_IMODE_MASK GENMASK(2, 0) +#define OSPI_CCR_ADMODE_SHIFT 8 +#define OSPI_CCR_ADMODE_MASK GENMASK(10, 8) +#define OSPI_CCR_ADSIZE_SHIFT 12 +#define OSPI_CCR_DMODE_SHIFT 24 +#define OSPI_CCR_DMODE_MASK GENMASK(26, 24) +#define OSPI_CCR_IND_WRITE 0 +#define OSPI_CCR_IND_READ 1 +#define OSPI_CCR_MEM_MAP 3 + +/* OCTOSPI timing configuration register */ +#define OSPI_TCR 0x108 +#define OSPI_TCR_DCYC_SHIFT 0x0 +#define OSPI_TCR_DCYC_MASK GENMASK(4, 0) +#define OSPI_TCR_SSHIFT BIT(30) + +/* OCTOSPI instruction register */ +#define OSPI_IR 0x110 + +#define OSPI_MAX_MMAP_SZ SZ_256M +#define OSPI_MAX_CHIP 2 + +#define OSPI_FIFO_TIMEOUT_US 30000 +#define OSPI_ABT_TIMEOUT_US 100000 +#define OSPI_BUSY_TIMEOUT_US 100000 +#define OSPI_CMD_TIMEOUT_US 1000000 + +struct stm32_ospi_flash { + u32 cr; + u32 dcr; + u32 dcr2; + bool initialized; +}; + +struct stm32_ospi_priv { + struct stm32_ospi_flash flash[OSPI_MAX_CHIP]; + int cs_used; +}; + +struct stm32_ospi_plat { + phys_addr_t regs_base; /* register base address */ + phys_addr_t mm_base; /* memory map base address */ + resource_size_t mm_size; + struct clk clk; + struct reset_ctl_bulk rst_ctl; + ulong clock_rate; +}; + +static int stm32_ospi_mm(struct udevice *dev, + const struct spi_mem_op *op) +{ + struct stm32_ospi_plat *ospi_plat = dev_get_plat(dev); + + memcpy_fromio(op->data.buf.in, + (void __iomem *)ospi_plat->mm_base + op->addr.val, + op->data.nbytes); + + return 0; +} + +static void stm32_ospi_read_fifo(void *val, phys_addr_t addr, u8 len) +{ + switch (len) { + case sizeof(u32): + *((u32 *)val) = readl_relaxed(addr); + break; + case sizeof(u16): + *((u16 *)val) = readw_relaxed(addr); + break; + case sizeof(u8): + *((u8 *)val) = readb_relaxed(addr); + }; + schedule(); +} + +static void stm32_ospi_write_fifo(void *val, phys_addr_t addr, u8 len) +{ + switch (len) { + case sizeof(u32): + writel_relaxed(*((u32 *)val), addr); + break; + case sizeof(u16): + writew_relaxed(*((u16 *)val), addr); + break; + case sizeof(u8): + writeb_relaxed(*((u8 *)val), addr); + }; +} + +int stm32_ospi_tx_poll(struct udevice *dev, void *buf, u32 len, bool read) +{ + struct stm32_ospi_plat *ospi_plat = dev_get_plat(dev); + phys_addr_t regs_base = ospi_plat->regs_base; + void (*fifo)(void *val, phys_addr_t addr, u8 len); + u32 sr; + int ret; + u8 step = 1; + + if (read) + fifo = stm32_ospi_read_fifo; + else + fifo = stm32_ospi_write_fifo; + + while (len) { + ret = readl_poll_timeout(regs_base + OSPI_SR, sr, + sr & OSPI_SR_FTF, + OSPI_FIFO_TIMEOUT_US); + if (ret) { + dev_err(dev, "fifo timeout (len:%d stat:%#x)\n", + len, sr); + return ret; + } + + if (!IS_ALIGNED((uintptr_t)buf, sizeof(u32))) { + if (!IS_ALIGNED((uintptr_t)buf, sizeof(u16))) + step = sizeof(u8); + else + step = min((u32)len, (u32)sizeof(u16)); + } + /* Buf is aligned */ + else if (len >= sizeof(u32)) + step = sizeof(u32); + else if (len >= sizeof(u16)) + step = sizeof(u16); + else if (len) + step = sizeof(u8); + + fifo(buf, regs_base + OSPI_DR, step); + len -= step; + buf += step; + } + + return 0; +} + +static int stm32_ospi_tx(struct udevice *dev, + const struct spi_mem_op *op, + u8 mode) +{ + void *buf; + + if (!op->data.nbytes) + return 0; + + if (mode == OSPI_CCR_MEM_MAP) + return stm32_ospi_mm(dev, op); + + if (op->data.dir == SPI_MEM_DATA_IN) + buf = op->data.buf.in; + else + buf = (void *)op->data.buf.out; + + return stm32_ospi_tx_poll(dev, buf, op->data.nbytes, + op->data.dir == SPI_MEM_DATA_IN); +} + +static int stm32_ospi_get_mode(u8 buswidth) +{ + if (buswidth == 8) + return 4; + + if (buswidth == 4) + return 3; + + return buswidth; +} + +int stm32_ospi_wait_for_not_busy(struct udevice *dev) +{ + struct stm32_ospi_plat *ospi_plat = dev_get_plat(dev); + phys_addr_t regs_base = ospi_plat->regs_base; + u32 sr; + int ret; + + ret = readl_poll_timeout(regs_base + OSPI_SR, sr, !(sr & OSPI_SR_BUSY), + OSPI_BUSY_TIMEOUT_US); + if (ret) + dev_err(dev, "busy timeout (stat:%#x)\n", sr); + + return ret; +} + +int stm32_ospi_wait_cmd(struct udevice *dev) +{ + struct stm32_ospi_plat *ospi_plat = dev_get_plat(dev); + phys_addr_t regs_base = ospi_plat->regs_base; + u32 sr; + int ret = 0; + + ret = readl_poll_timeout(regs_base + OSPI_SR, sr, + sr & OSPI_SR_TCF, + OSPI_CMD_TIMEOUT_US); + if (ret) { + dev_err(dev, "cmd timeout (stat:%#x)\n", sr); + } else if (readl(regs_base + OSPI_SR) & OSPI_SR_TEF) { + dev_err(dev, "transfer error (stat:%#x)\n", sr); + ret = -EIO; + } + + /* clear flags */ + writel(OSPI_FCR_CTCF | OSPI_FCR_CTEF, regs_base + OSPI_FCR); + + if (!ret) + ret = stm32_ospi_wait_for_not_busy(dev); + + return ret; +} + +static int stm32_ospi_exec_op(struct spi_slave *slave, + const struct spi_mem_op *op) +{ + struct stm32_ospi_plat *ospi_plat = dev_get_plat(slave->dev->parent); + phys_addr_t regs_base = ospi_plat->regs_base; + u32 cr, ccr = 0, addr_max; + int timeout, ret; + int dmode; + u8 mode = OSPI_CCR_IND_WRITE; + u8 dcyc = 0; + + dev_dbg(slave->dev, "%s: cmd:%#x mode:%d.%d.%d.%d addr:%#llx len:%#x\n", + __func__, op->cmd.opcode, op->cmd.buswidth, op->addr.buswidth, + op->dummy.buswidth, op->data.buswidth, + op->addr.val, op->data.nbytes); + + addr_max = op->addr.val + op->data.nbytes + 1; + + if (op->data.dir == SPI_MEM_DATA_IN && op->data.nbytes) { + if (addr_max < ospi_plat->mm_size && op->addr.buswidth) + mode = OSPI_CCR_MEM_MAP; + else + mode = OSPI_CCR_IND_READ; + } + + if (op->data.nbytes) + writel(op->data.nbytes - 1, regs_base + OSPI_DLR); + + clrsetbits_le32(regs_base + OSPI_CR, OSPI_CR_FMODE_MASK, + mode << OSPI_CR_FMODE_SHIFT); + + ccr |= (stm32_ospi_get_mode(op->cmd.buswidth) << OSPI_CCR_IMODE_SHIFT) & + OSPI_CCR_IMODE_MASK; + + if (op->addr.nbytes) { + ccr |= ((op->addr.nbytes - 1) << OSPI_CCR_ADSIZE_SHIFT); + ccr |= (stm32_ospi_get_mode(op->addr.buswidth) + << OSPI_CCR_ADMODE_SHIFT) & OSPI_CCR_ADMODE_MASK; + } + + if (op->dummy.buswidth && op->dummy.nbytes) + dcyc = op->dummy.nbytes * 8 / op->dummy.buswidth; + + clrsetbits_le32(regs_base + OSPI_TCR, OSPI_TCR_DCYC_MASK, + dcyc << OSPI_TCR_DCYC_SHIFT); + + if (op->data.nbytes) { + dmode = stm32_ospi_get_mode(op->data.buswidth); + ccr |= (dmode << OSPI_CCR_DMODE_SHIFT) & OSPI_CCR_DMODE_MASK; + } + + writel(ccr, regs_base + OSPI_CCR); + + /* set instruction, must be set after ccr register update */ + writel(op->cmd.opcode, regs_base + OSPI_IR); + + if (op->addr.nbytes && mode != OSPI_CCR_MEM_MAP) + writel(op->addr.val, regs_base + OSPI_AR); + + ret = stm32_ospi_tx(slave->dev->parent, op, mode); + /* + * Abort in: + * -error case + * -read memory map: prefetching must be stopped if we read the last + * byte of device (device size - fifo size). like device size is not + * knows, the prefetching is always stop. + */ + if (ret || mode == OSPI_CCR_MEM_MAP) + goto abort; + + /* Wait end of tx in indirect mode */ + ret = stm32_ospi_wait_cmd(slave->dev->parent); + if (ret) + goto abort; + + return 0; + +abort: + setbits_le32(regs_base + OSPI_CR, OSPI_CR_ABORT); + + /* Wait clear of abort bit by hw */ + timeout = readl_poll_timeout(regs_base + OSPI_CR, cr, + !(cr & OSPI_CR_ABORT), + OSPI_ABT_TIMEOUT_US); + + writel(OSPI_FCR_CTCF, regs_base + OSPI_FCR); + + if (ret || timeout) + dev_err(slave->dev, "%s ret:%d abort timeout:%d\n", __func__, + ret, timeout); + + return ret; +} + +static int stm32_ospi_probe(struct udevice *bus) +{ + struct stm32_ospi_priv *priv = dev_get_priv(bus); + struct stm32_ospi_plat *ospi_plat; + phys_addr_t regs_base; + int ret; + + ospi_plat = dev_get_plat(bus); + regs_base = ospi_plat->regs_base; + + ret = clk_enable(&ospi_plat->clk); + if (ret) { + dev_err(bus, "failed to enable clock\n"); + return ret; + } + + /* Reset OSPI controller */ + reset_assert_bulk(&ospi_plat->rst_ctl); + udelay(2); + reset_deassert_bulk(&ospi_plat->rst_ctl); + + priv->cs_used = -1; + + setbits_le32(regs_base + OSPI_TCR, OSPI_TCR_SSHIFT); + + clrsetbits_le32(regs_base + OSPI_CR, OSPI_CR_FTHRES_MASK, + 3 << OSPI_CR_FTHRES_SHIFT); + + /* Set dcr devsize to max address */ + setbits_le32(regs_base + OSPI_DCR1, + OSPI_DCR1_DEVSIZE_MASK | OSPI_DCR1_DLYBYP); + + return 0; +} + +static int stm32_ospi_claim_bus(struct udevice *dev) +{ + struct stm32_ospi_priv *priv = dev_get_priv(dev->parent); + struct dm_spi_slave_plat *slave_plat = dev_get_parent_plat(dev); + struct stm32_ospi_plat *ospi_plat = dev_get_plat(dev->parent); + phys_addr_t regs_base = ospi_plat->regs_base; + unsigned int slave_cs = slave_plat->cs[0]; + + if (slave_cs >= OSPI_MAX_CHIP) + return -ENODEV; + + if (priv->cs_used != slave_cs) { + struct stm32_ospi_flash *flash = &priv->flash[slave_cs]; + + priv->cs_used = slave_cs; + + if (flash->initialized) { + /* Set the configuration: speed + cs */ + writel(flash->cr, regs_base + OSPI_CR); + writel(flash->dcr, regs_base + OSPI_DCR1); + writel(flash->dcr2, regs_base + OSPI_DCR2); + } else { + /* Set chip select */ + clrsetbits_le32(regs_base + OSPI_CR, + OSPI_CR_CSSEL, + priv->cs_used ? OSPI_CR_CSSEL : 0); + + /* Save the configuration: speed + cs */ + flash->cr = readl(regs_base + OSPI_CR); + flash->dcr = readl(regs_base + OSPI_DCR1); + flash->dcr2 = readl(regs_base + OSPI_DCR2); + flash->initialized = true; + } + } + + setbits_le32(regs_base + OSPI_CR, OSPI_CR_EN); + + return 0; +} + +static int stm32_ospi_release_bus(struct udevice *dev) +{ + struct stm32_ospi_plat *ospi_plat = dev_get_plat(dev->parent); + phys_addr_t regs_base = ospi_plat->regs_base; + + clrbits_le32(regs_base + OSPI_CR, OSPI_CR_EN); + + return 0; +} + +static int stm32_ospi_set_speed(struct udevice *bus, uint speed) +{ + struct stm32_ospi_plat *ospi_plat = dev_get_plat(bus); + phys_addr_t regs_base = ospi_plat->regs_base; + u32 ospi_clk = ospi_plat->clock_rate; + u32 prescaler = 255; + u32 csht; + int ret; + + if (speed > 0) { + prescaler = 0; + if (ospi_clk) { + prescaler = DIV_ROUND_UP(ospi_clk, speed) - 1; + if (prescaler > 255) + prescaler = 255; + } + } + + csht = (DIV_ROUND_UP((5 * ospi_clk) / (prescaler + 1), 100000000)) - 1; + + ret = stm32_ospi_wait_for_not_busy(bus); + if (ret) + return ret; + + clrsetbits_le32(regs_base + OSPI_DCR2, OSPI_DCR2_PRESC_MASK, + prescaler << OSPI_DCR2_PRESC_SHIFT); + + clrsetbits_le32(regs_base + OSPI_DCR1, OSPI_DCR1_CSHT_MASK, + csht << OSPI_DCR1_CSHT_SHIFT); + + return 0; +} + +static int stm32_ospi_set_mode(struct udevice *bus, uint mode) +{ + struct stm32_ospi_plat *ospi_plat = dev_get_plat(bus); + phys_addr_t regs_base = ospi_plat->regs_base; + const char *str_rx, *str_tx; + int ret; + + ret = stm32_ospi_wait_for_not_busy(bus); + if (ret) + return ret; + + if ((mode & SPI_CPHA) && (mode & SPI_CPOL)) + setbits_le32(regs_base + OSPI_DCR1, OSPI_DCR1_CKMODE); + else if (!(mode & SPI_CPHA) && !(mode & SPI_CPOL)) + clrbits_le32(regs_base + OSPI_DCR1, OSPI_DCR1_CKMODE); + else + return -ENODEV; + + if (mode & SPI_CS_HIGH) + return -ENODEV; + + if (mode & SPI_RX_OCTAL) + str_rx = "octal"; + else if (mode & SPI_RX_QUAD) + str_rx = "quad"; + else if (mode & SPI_RX_DUAL) + str_rx = "dual"; + else + str_rx = "single"; + + if (mode & SPI_TX_OCTAL) + str_tx = "octal"; + else if (mode & SPI_TX_QUAD) + str_tx = "quad"; + else if (mode & SPI_TX_DUAL) + str_tx = "dual"; + else + str_tx = "single"; + + dev_dbg(bus, "mode=%d rx: %s, tx: %s\n", mode, str_rx, str_tx); + + return 0; +} + +static const struct spi_controller_mem_ops stm32_ospi_mem_ops = { + .exec_op = stm32_ospi_exec_op, +}; + +static const struct dm_spi_ops stm32_ospi_ops = { + .claim_bus = stm32_ospi_claim_bus, + .release_bus = stm32_ospi_release_bus, + .set_speed = stm32_ospi_set_speed, + .set_mode = stm32_ospi_set_mode, + .mem_ops = &stm32_ospi_mem_ops, +}; + +static int stm32_ospi_of_to_plat(struct udevice *dev) +{ + struct stm32_ospi_plat *plat = dev_get_plat(dev); + struct resource res; + struct ofnode_phandle_args args; + const fdt32_t *reg; + int ret, len; + + reg = dev_read_prop(dev, "reg", &len); + if (!reg) { + dev_err(dev, "Can't get regs base address\n"); + return -ENOENT; + } + + plat->regs_base = (phys_addr_t)dev_translate_address(dev, reg); + + /* optional */ + ret = dev_read_phandle_with_args(dev, "memory-region", NULL, 0, 0, &args); + if (!ret) { + ret = ofnode_read_resource(args.node, 0, &res); + if (ret) { + dev_err(dev, "Can't get mmap base address(%d)\n", ret); + return ret; + } + + plat->mm_base = res.start; + plat->mm_size = resource_size(&res); + + if (plat->mm_size > OSPI_MAX_MMAP_SZ) { + dev_err(dev, "Incorrect memory-map size: %lld Bytes\n", plat->mm_size); + return -EINVAL; + } + + dev_dbg(dev, "%s: regs_base=<0x%llx> mm_base=<0x%llx> mm_size=<0x%x>\n", + __func__, plat->regs_base, plat->mm_base, (u32)plat->mm_size); + } else { + plat->mm_base = 0; + plat->mm_size = 0; + dev_info(dev, "memory-region property not found (%d)\n", ret); + } + + ret = clk_get_by_index(dev, 0, &plat->clk); + if (ret < 0) { + dev_err(dev, "Failed to get clock\n"); + return ret; + } + + ret = reset_get_bulk(dev, &plat->rst_ctl); + if (ret && ret != -ENOENT) { + dev_err(dev, "Failed to get reset\n"); + return ret; + } + + plat->clock_rate = clk_get_rate(&plat->clk); + if (!plat->clock_rate) + return -EINVAL; + + return ret; +}; + +static const struct udevice_id stm32_ospi_ids[] = { + { .compatible = "st,stm32mp25-ospi" }, + { } +}; + +U_BOOT_DRIVER(stm32_ospi) = { + .name = "stm32_ospi", + .id = UCLASS_SPI, + .of_match = stm32_ospi_ids, + .of_to_plat = stm32_ospi_of_to_plat, + .ops = &stm32_ospi_ops, + .plat_auto = sizeof(struct stm32_ospi_plat), + .priv_auto = sizeof(struct stm32_ospi_priv), + .probe = stm32_ospi_probe, +}; -- cgit v1.2.3 From df80866312b078e011cda7998cfd5e46d5b35760 Mon Sep 17 00:00:00 2001 From: Patrice Chotard Date: Thu, 11 Sep 2025 08:59:43 +0200 Subject: configs: stm32mp25: Enable configs flags related to SPI flashes. Enable configs flags related to SPI flashes. Signed-off-by: Patrice Chotard Reviewed-by: Patrick Delaunay --- configs/stm32mp25_defconfig | 15 ++++++++++++++- 1 file changed, 14 insertions(+), 1 deletion(-) diff --git a/configs/stm32mp25_defconfig b/configs/stm32mp25_defconfig index 2b02cd86d61..a5ee02a09b4 100644 --- a/configs/stm32mp25_defconfig +++ b/configs/stm32mp25_defconfig @@ -33,6 +33,7 @@ CONFIG_CMD_GPIO=y CONFIG_CMD_PWM=y # CONFIG_CMD_LOADB is not set CONFIG_CMD_MMC=y +CONFIG_CMD_MTD=y CONFIG_CMD_CACHE=y CONFIG_CMD_TIME=y CONFIG_CMD_RNG=y @@ -61,11 +62,22 @@ CONFIG_DM_I2C=y CONFIG_SYS_I2C_STM32F7=y CONFIG_LED=y CONFIG_LED_GPIO=y +CONFIG_STM32_OMM=y CONFIG_SUPPORT_EMMC_BOOT=y CONFIG_STM32_SDMMC2=y CONFIG_MTD=y +CONFIG_DM_MTD=y CONFIG_USE_SYS_MAX_FLASH_BANKS=y -CONFIG_SPI_FLASH=y +CONFIG_MTD_SPI_NAND=y +CONFIG_DM_SPI_FLASH=y +CONFIG_SPI_FLASH_SFDP_SUPPORT=y +CONFIG_SPI_FLASH_SOFT_RESET=y +CONFIG_SPI_FLASH_MACRONIX=y +CONFIG_SPI_FLASH_SPANSION=y +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_SPI_FLASH_WINBOND=y +# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set +CONFIG_SPI_FLASH_MTD=y CONFIG_PINCONF=y CONFIG_DM_REGULATOR_FIXED=y CONFIG_DM_REGULATOR_GPIO=y @@ -77,6 +89,7 @@ CONFIG_DM_RNG=y CONFIG_SERIAL_RX_BUFFER=y CONFIG_SPI=y CONFIG_DM_SPI=y +CONFIG_STM32_OSPI=y # CONFIG_OPTEE_TA_AVB is not set CONFIG_WDT=y CONFIG_WDT_STM32MP=y -- cgit v1.2.3 From b8edd54d6022e09c5b2e9a87ede34fc0f019638d Mon Sep 17 00:00:00 2001 From: Patrice Chotard Date: Thu, 11 Sep 2025 08:59:44 +0200 Subject: ARM: dts: Add flash0 partitions for stm32mp257f-ev1-u-boot Add flash0 partitions for stm32mp257f-ev1-u-boot. Signed-off-by: Patrice Chotard Reviewed-by: Patrick Delaunay --- arch/arm/dts/stm32mp257f-ev1-u-boot.dtsi | 41 ++++++++++++++++++++++++++++++++ 1 file changed, 41 insertions(+) diff --git a/arch/arm/dts/stm32mp257f-ev1-u-boot.dtsi b/arch/arm/dts/stm32mp257f-ev1-u-boot.dtsi index 9a566e18d3f..7bbb3e00351 100644 --- a/arch/arm/dts/stm32mp257f-ev1-u-boot.dtsi +++ b/arch/arm/dts/stm32mp257f-ev1-u-boot.dtsi @@ -12,6 +12,47 @@ }; }; +&flash0 { + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "fsbla1"; + reg = <0x00000000 0x00040000>; + }; + partition@40000 { + label = "fsbla2"; + reg = <0x00040000 0x00040000>; + }; + partition@80000 { + label = "metadata1"; + reg = <0x00080000 0x00040000>; + }; + partition@C0000 { + label = "metadata2"; + reg = <0x000C0000 0x00040000>; + }; + partition@100000 { + label = "fip-a"; + reg = <0x00100000 0x00400000>; + }; + partition@500000 { + label = "fip-b"; + reg = <0x00500000 0x00400000>; + }; + partition@900000 { + label = "u-boot-env"; + reg = <0x00900000 0x00080000>; + }; + partition@980000 { + label = "nor-user"; + reg = <0x00980000 0x03680000>; + }; + }; +}; + &usart2 { bootph-all; }; -- cgit v1.2.3 From 63585689686fee83b382edacad249a4ec35d7c3d Mon Sep 17 00:00:00 2001 From: Weijie Gao Date: Mon, 8 Sep 2025 16:34:02 +0800 Subject: misc: fs_loader: allow returning actual firmware data size in request_firmware_into_buf_via_script() It's important to return the actual firmware data size as some firmware files may have no checksum and need the size as the only way for firmware validation check. Signed-off-by: Weijie Gao --- drivers/misc/fs_loader.c | 6 +++++- include/fs_loader.h | 4 +++- 2 files changed, 8 insertions(+), 2 deletions(-) diff --git a/drivers/misc/fs_loader.c b/drivers/misc/fs_loader.c index 60296d55f23..87acd385e23 100644 --- a/drivers/misc/fs_loader.c +++ b/drivers/misc/fs_loader.c @@ -229,7 +229,8 @@ int request_firmware_into_buf(struct udevice *dev, } int request_firmware_into_buf_via_script(void **buf, size_t max_size, - const char *script_name) + const char *script_name, + size_t *retsize) { ulong addr, size; int ret; @@ -269,6 +270,9 @@ int request_firmware_into_buf_via_script(void **buf, size_t max_size, return -E2BIG; } + if (retsize) + *retsize = size; + memcpy(*buf, (void *)addr, size); return 0; diff --git a/include/fs_loader.h b/include/fs_loader.h index a433be1eb99..1cf6d6dd05f 100644 --- a/include/fs_loader.h +++ b/include/fs_loader.h @@ -71,6 +71,7 @@ int get_fs_loader(struct udevice **dev); * @buf: Pointer to a pointer where the firmware buffer will be stored. * @max_size: Maximum allowed size for the firmware to be loaded. * @script_name: Name of the U-Boot script to execute for firmware loading. + * @retsize: Return the actual firmware data size (optional). * * Executes a U-Boot script (@script_name) that loads firmware into * memory and sets the environment variables 'fw_addr' (address) and @@ -87,5 +88,6 @@ int get_fs_loader(struct udevice **dev); * Return: 0 on success, negative value on error. */ int request_firmware_into_buf_via_script(void **buf, size_t max_size, - const char *script_name); + const char *script_name, + size_t *retsize); #endif -- cgit v1.2.3 From 5b1d3d83d68a713c492bfad991338d47069f337e Mon Sep 17 00:00:00 2001 From: Weijie Gao Date: Mon, 8 Sep 2025 16:34:07 +0800 Subject: misc: fs_loader: allow using long script name in request_firmware_into_buf_via_script() Use cmd_process() to remove the length limit of script name used for run_command(). Signed-off-by: Weijie Gao --- drivers/misc/fs_loader.c | 9 +++------ 1 file changed, 3 insertions(+), 6 deletions(-) diff --git a/drivers/misc/fs_loader.c b/drivers/misc/fs_loader.c index 87acd385e23..6a6796c1931 100644 --- a/drivers/misc/fs_loader.c +++ b/drivers/misc/fs_loader.c @@ -232,18 +232,15 @@ int request_firmware_into_buf_via_script(void **buf, size_t max_size, const char *script_name, size_t *retsize) { + char *args[2] = { (char *)"run", (char *)script_name }; + int ret, repeatable; ulong addr, size; - int ret; - char cmd[32]; if (!buf || !script_name || !max_size) return -EINVAL; - /* Create command to run the firmware loading script */ - snprintf(cmd, sizeof(cmd), "run %s", script_name); - /* Run the firmware loading script */ - ret = run_command_list(cmd, -1, 0); + ret = cmd_process(0, 2, args, &repeatable, NULL); if (ret) { log_err("Firmware loading script '%s' not defined or failed.\n", script_name); -- cgit v1.2.3 From 465d76a0381dae83942f81329400b1fa2487185a Mon Sep 17 00:00:00 2001 From: Weijie Gao Date: Mon, 8 Sep 2025 16:34:13 +0800 Subject: net: mediatek: associate PHY device with dts node specified by phy-handle Associate PHY device with its device node specified by phy-handle property. This makes it possible for PHY drivers to read dedicated information to configure the PHY device. Signed-off-by: Weijie Gao --- drivers/net/mtk_eth/mtk_eth.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/drivers/net/mtk_eth/mtk_eth.c b/drivers/net/mtk_eth/mtk_eth.c index b172838ba3a..a35754ccd1f 100644 --- a/drivers/net/mtk_eth/mtk_eth.c +++ b/drivers/net/mtk_eth/mtk_eth.c @@ -100,6 +100,7 @@ struct mtk_eth_priv { bool pn_swap; struct phy_device *phydev; + ofnode phy_node; int phy_interface; int phy_addr; @@ -572,6 +573,7 @@ static int mtk_phy_probe(struct udevice *dev) if (!phydev) return -ENODEV; + phydev->node = priv->phy_node; phydev->supported &= PHY_GBIT_FEATURES; phydev->advertising = phydev->supported; @@ -1458,6 +1460,8 @@ static int mtk_eth_of_to_plat(struct udevice *dev) return ret; } + priv->phy_node = args.node; + priv->phy_addr = ofnode_read_s32_default(args.node, "reg", -1); if (priv->phy_addr < 0) { printf("error: phy address is not specified\n"); -- cgit v1.2.3 From b4b266fc139ad0a8856db6a7495f7e9a2cc27a6f Mon Sep 17 00:00:00 2001 From: Weijie Gao Date: Mon, 8 Sep 2025 16:34:18 +0800 Subject: net: phy: Add MediaTek built-in 2.5Gb ethernet PHY driver The MediaTek MT7987/MT7988 SoCs features a built-in 2.5Gb PHY connected to GMAC1. The PHY supports 10/100/1000/2500 Mbps full-duplex only. The PHY requires one or two firmware files. Firmware for MT7988 has already been added to upstream: mediatek/mt7988/i2p5ge-phy-pmb.bin. MT7987 has two firmware files which will be add to upstream later: i2p5ge-phy-pmb.bin and i2p5ge-phy-DSPBitTb.bin. Environment variable can be set for firmware data loading: mt7987_i2p5ge_load_pmb_firmware for i2p5ge-phy-pmb.bin mt7987_i2p5ge_load_dspbit_firmware for i2p5ge-phy-DSPBitTb.bin mt7988_i2p5ge_load_pmb_firmware for i2p5ge-phy-pmb.bin This driver allows dedicated weak functions to be overridden by board to provide the firmware data: mt7987_i2p5ge_get_fw() for MT7987 mt7988_i2p5ge_get_fw() for MT7988 To enable the PHY, add the following not to device tree: ð1 { status = "okay"; phy-mode = "xgmii"; phy-handle = <&phy15>; phy15: ethernet-phy@15 { compatible = "ethernet-phy-ieee802.3-c45"; reg = <15>; phy-mode = "xgmii"; }; }; Signed-off-by: Sky Huang Signed-off-by: Weijie Gao --- drivers/misc/fs_loader.c | 2 +- drivers/net/phy/Kconfig | 2 + drivers/net/phy/Makefile | 1 + drivers/net/phy/mediatek/Kconfig | 16 + drivers/net/phy/mediatek/Makefile | 4 + drivers/net/phy/mediatek/mtk-2p5ge.c | 627 +++++++++++++++++++++++++++++++++ drivers/net/phy/mediatek/mtk-phy-lib.c | 106 ++++++ drivers/net/phy/mediatek/mtk.h | 103 ++++++ 8 files changed, 860 insertions(+), 1 deletion(-) create mode 100644 drivers/net/phy/mediatek/Kconfig create mode 100644 drivers/net/phy/mediatek/Makefile create mode 100644 drivers/net/phy/mediatek/mtk-2p5ge.c create mode 100644 drivers/net/phy/mediatek/mtk-phy-lib.c create mode 100644 drivers/net/phy/mediatek/mtk.h diff --git a/drivers/misc/fs_loader.c b/drivers/misc/fs_loader.c index 6a6796c1931..c6c633f7c52 100644 --- a/drivers/misc/fs_loader.c +++ b/drivers/misc/fs_loader.c @@ -232,7 +232,7 @@ int request_firmware_into_buf_via_script(void **buf, size_t max_size, const char *script_name, size_t *retsize) { - char *args[2] = { (char *)"run", (char *)script_name }; + char *args[2] = { "run", (char *)script_name }; int ret, repeatable; ulong addr, size; diff --git a/drivers/net/phy/Kconfig b/drivers/net/phy/Kconfig index 21bf983056a..185c6a3156e 100644 --- a/drivers/net/phy/Kconfig +++ b/drivers/net/phy/Kconfig @@ -184,6 +184,8 @@ config PHY_MARVELL_10G help Support for the Marvell Alaska MV88X3310 and compatible PHYs. +source "drivers/net/phy/mediatek/Kconfig" + config PHY_MESON_GXL bool "Amlogic Meson GXL Internal PHY support" diff --git a/drivers/net/phy/Makefile b/drivers/net/phy/Makefile index a119eb5e177..a339b8ac29d 100644 --- a/drivers/net/phy/Makefile +++ b/drivers/net/phy/Makefile @@ -21,6 +21,7 @@ obj-$(CONFIG_PHY_ET1011C) += et1011c.o obj-$(CONFIG_PHY_LXT) += lxt.o obj-$(CONFIG_PHY_MARVELL) += marvell.o obj-$(CONFIG_PHY_MARVELL_10G) += marvell10g.o +obj-y += mediatek/ obj-$(CONFIG_PHY_MICREL_KSZ8XXX) += micrel_ksz8xxx.o obj-$(CONFIG_PHY_MICREL_KSZ90X1) += micrel_ksz90x1.o obj-$(CONFIG_PHY_MESON_GXL) += meson-gxl.o diff --git a/drivers/net/phy/mediatek/Kconfig b/drivers/net/phy/mediatek/Kconfig new file mode 100644 index 00000000000..7de7b65b4e6 --- /dev/null +++ b/drivers/net/phy/mediatek/Kconfig @@ -0,0 +1,16 @@ +# SPDX-License-Identifier: GPL-2.0-only + +config MTK_NET_PHYLIB + tristate + +config PHY_MEDIATEK_2P5GE + tristate "MediaTek built-in 2.5Gb ethernet PHYs" + depends on OF_CONTROL && (TARGET_MT7987 || TARGET_MT7988) + select MTK_NET_PHYLIB + select FS_LOADER + help + Supports MediaTek SoC built-in 2.5Gb ethernet PHYs. + + This driver requires firmware download for PHY to enable its + functionality. The board can override certian firmware downloading + function to provide the firmware data. diff --git a/drivers/net/phy/mediatek/Makefile b/drivers/net/phy/mediatek/Makefile new file mode 100644 index 00000000000..bc8dd4e878c --- /dev/null +++ b/drivers/net/phy/mediatek/Makefile @@ -0,0 +1,4 @@ +# SPDX-License-Identifier: GPL-2.0 + +obj-$(CONFIG_MTK_NET_PHYLIB) += mtk-phy-lib.o +obj-$(CONFIG_PHY_MEDIATEK_2P5GE) += mtk-2p5ge.o diff --git a/drivers/net/phy/mediatek/mtk-2p5ge.c b/drivers/net/phy/mediatek/mtk-2p5ge.c new file mode 100644 index 00000000000..ab5007389a9 --- /dev/null +++ b/drivers/net/phy/mediatek/mtk-2p5ge.c @@ -0,0 +1,627 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2025 MediaTek Inc. All Rights Reserved. + * + * Author: Sky Huang + * Author: Weijie Gao + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "mtk.h" + +#define MTK_2P5GPHY_ID_MT7987 0x00339c91 +#define MTK_2P5GPHY_ID_MT7988 0x00339c11 + +#define PBUS_BASE 0x0f000000 +#define PBUS_SIZE 0x1f0024 + +#define MTK_2P5GPHY_PMD_REG 0x010000 +#define DO_NOT_RESET (MTK_2P5GPHY_PMD_REG + 0x28) +#define DO_NOT_RESET_XBZ BIT(0) +#define DO_NOT_RESET_PMA BIT(3) +#define DO_NOT_RESET_RX BIT(5) +#define FNPLL_PWR_CTRL1 (MTK_2P5GPHY_PMD_REG + 0x208) +#define RG_SPEED_MASK GENMASK(3, 0) +#define RG_SPEED_2500 BIT(3) +#define RG_SPEED_100 BIT(0) +#define FNPLL_PWR_CTRL_STATUS (MTK_2P5GPHY_PMD_REG + 0x20c) +#define RG_STABLE_MASK GENMASK(3, 0) +#define RG_SPEED_2500_STABLE BIT(3) +#define RG_SPEED_100_STABLE BIT(0) + +#define MTK_2P5GPHY_XBZ_PCS 0x030000 +#define PHY_CTRL_CONFIG (MTK_2P5GPHY_XBZ_PCS + 0x200) +#define PMU_WP (MTK_2P5GPHY_XBZ_PCS + 0x800) +#define WRITE_PROTECT_KEY 0xCAFEF00D +#define PMU_PMA_AUTO_CFG (MTK_2P5GPHY_XBZ_PCS + 0x820) +#define POWER_ON_AUTO_MODE BIT(16) +#define PMU_AUTO_MODE_EN BIT(0) +#define PMU_PMA_STATUS (MTK_2P5GPHY_XBZ_PCS + 0x840) +#define CLK_IS_DISABLED BIT(3) + +#define MTK_2P5GPHY_XBZ_PMA_RX 0x080000 +#define SMEM_WDAT0 (MTK_2P5GPHY_XBZ_PMA_RX + 0x5000) +#define SMEM_WDAT1 (MTK_2P5GPHY_XBZ_PMA_RX + 0x5004) +#define SMEM_WDAT2 (MTK_2P5GPHY_XBZ_PMA_RX + 0x5008) +#define SMEM_WDAT3 (MTK_2P5GPHY_XBZ_PMA_RX + 0x500c) +#define SMEM_CTRL (MTK_2P5GPHY_XBZ_PMA_RX + 0x5024) +#define SMEM_HW_RDATA_ZERO BIT(24) +#define SMEM_ADDR_REF_ADDR (MTK_2P5GPHY_XBZ_PMA_RX + 0x502c) +#define CM_CTRL_P01 (MTK_2P5GPHY_XBZ_PMA_RX + 0x5100) +#define CM_CTRL_P23 (MTK_2P5GPHY_XBZ_PMA_RX + 0x5124) +#define DM_CTRL_P01 (MTK_2P5GPHY_XBZ_PMA_RX + 0x5200) +#define DM_CTRL_P23 (MTK_2P5GPHY_XBZ_PMA_RX + 0x5224) + +#define MTK_2P5GPHY_CHIP_SCU 0x0cf800 +#define SYS_SW_RESET (MTK_2P5GPHY_CHIP_SCU + 0x128) +#define RESET_RST_CNT BIT(0) + +#define MTK_2P5GPHY_MCU_CSR 0x0f0000 +#define MD32_EN_CFG (MTK_2P5GPHY_MCU_CSR + 0x18) +#define MD32_EN BIT(0) + +#define MTK_2P5GPHY_PMB_FW 0x100000 + +#define MTK_2P5GPHY_FCM_BASE 0x0e0000 +#define FC_LWM (MTK_2P5GPHY_FCM_BASE + 0x14) +#define TX_FC_LWM_MASK GENMASK(31, 16) +#define MIN_IPG_NUM (MTK_2P5GPHY_FCM_BASE + 0x2c) +#define LS_MIN_IPG_NUM_MASK GENMASK(7, 0) +#define FIFO_CTRL (MTK_2P5GPHY_FCM_BASE + 0x40) +#define TX_SFIFO_IDLE_CNT_MASK GENMASK(31, 28) +#define TX_SFIFO_DEL_IPG_WM_MASK GENMASK(23, 16) + +#define MTK_2P5GPHY_APB_BASE 0x11c30000 +#define MTK_2P5GPHY_APB_SIZE 0x9c +#define SW_RESET 0x94 +#define MD32_RESTART_EN_CLEAR BIT(9) + +/* Registers on CL22 page 0 */ +#define PHY_AUX_CTRL_STATUS 0x1d +#define PHY_AUX_DPX_MASK GENMASK(5, 5) +#define PHY_AUX_SPEED_MASK GENMASK(4, 2) + +enum { + PHY_AUX_SPD_10 = 0, + PHY_AUX_SPD_100, + PHY_AUX_SPD_1000, + PHY_AUX_SPD_2500, +}; + +/* Registers on MDIO_MMD_VEND1 */ +#define MTK_PHY_LINK_STATUS_RELATED 0x147 +#define MTK_PHY_BYPASS_LINK_STATUS_OK BIT(4) +#define MTK_PHY_FORCE_LINK_STATUS_HCD BIT(3) + +#define MTK_PHY_AN_FORCE_SPEED_REG 0x313 +#define MTK_PHY_MASTER_FORCE_SPEED_SEL_EN BIT(7) +#define MTK_PHY_MASTER_FORCE_SPEED_SEL_MASK GENMASK(6, 0) + +#define MTK_PHY_LPI_PCS_DSP_CTRL 0x121 +#define MTK_PHY_LPI_SIG_EN_LO_THRESH100_MASK GENMASK(12, 8) + +#define MTK_PHY_PMA_PMD_SPEED_ABILITY 0x300 +#define CAP_100X_HDX BIT(14) +#define CAP_10T_HDX BIT(12) + +/* Registers on MDIO_MMD_VEND2 */ +#define MT7987_OPTIONS 0x110 +#define NORMAL_RETRAIN_DISABLE BIT(0) + +/* Registers on Token Ring debug nodes */ +/* ch_addr = 0x0, node_addr = 0xf, data_addr = 0x3c */ +#define AUTO_NP_10XEN BIT(6) + +/* Firmware file size */ +#define MT7987_2P5GE_PMB_FW_SIZE 0x18000 +#define MT7988_2P5GE_PMB_FW_SIZE 0x20000 + +#define MT7987_2P5GE_DSPBITTB_SIZE 0x7000 + +struct mtk_i2p5ge_fw_info { + u8 datecode[4]; + u8 plat[2]; + u8 ver[2]; +}; + +struct mtk_i2p5ge_priv { + void __iomem *reg_base; +}; + +static inline void pbus_write(struct mtk_i2p5ge_priv *priv, u32 offset, + u32 val) +{ + writel(val, priv->reg_base + offset); +} + +static inline void pbus_rmw(struct mtk_i2p5ge_priv *priv, u32 offset, u32 clr, + u32 set) +{ + clrsetbits_le32(priv->reg_base + offset, clr, set); +} + +static int mt798x_i2p5ge_download_fw(struct mtk_i2p5ge_priv *priv, + size_t fwsize, const void *fwdata) +{ + u32 __iomem *fwmem = priv->reg_base + MTK_2P5GPHY_PMB_FW; + const u32 *fw; + u32 i; + + /* Assume fw data is 4-byte aligned */ + fw = fwdata; + + for (i = 0; i < (fwsize >> 2); i++) + writel(fw[i], &fwmem[i]); + + return 0; +} + +static int mt798x_i2p5ge_phy_probe(struct phy_device *phydev) +{ + struct mtk_i2p5ge_priv *priv; + + priv = malloc(sizeof(*priv)); + if (!priv) + return -ENOMEM; + + priv->reg_base = ioremap(PBUS_BASE, PBUS_SIZE); + if (!priv->reg_base) { + free(priv); + return -ENODEV; + } + + phydev->priv = priv; + + return 0; +} + +static int mt798x_i2p5ge_phy_config(struct phy_device *phydev) +{ + + /* Setup LED */ + phy_set_bits_mmd(phydev, MDIO_MMD_VEND2, MTK_PHY_LED0_ON_CTRL, + MTK_PHY_LED_ON_LINK10 | + MTK_PHY_LED_ON_LINK100 | + MTK_PHY_LED_ON_LINK1000 | + MTK_PHY_LED_ON_LINK2500); + phy_set_bits_mmd(phydev, MDIO_MMD_VEND2, MTK_PHY_LED1_ON_CTRL, + MTK_PHY_LED_ON_FDX | MTK_PHY_LED_ON_HDX); + + /* Switch pinctrl after setting polarity to avoid bogus blinking */ + pinctrl_select_state(phydev->dev, "i2p5gbe-led"); + + phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_LPI_PCS_DSP_CTRL, + MTK_PHY_LPI_SIG_EN_LO_THRESH100_MASK, 0); + + /* Enable 16-bit next page exchange bit if 1000-BT isn't advertising */ + mtk_tr_modify(phydev, 0x0, 0xf, 0x3c, AUTO_NP_10XEN, + FIELD_PREP(AUTO_NP_10XEN, 0x1)); + + /* Set HW auto downshift */ + mtk_phy_select_page(phydev, MTK_PHY_PAGE_EXTENDED_1); + phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, + MTK_PHY_AUX_CTRL_AND_STATUS, + MTK_PHY_ENABLE_DOWNSHIFT); + mtk_phy_restore_page(phydev); + + /* Configure parallel detction functionality */ + phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, + MTK_PHY_PMA_PMD_SPEED_ABILITY, + CAP_10T_HDX | CAP_100X_HDX); + phy_clear_bits_mmd(phydev, MDIO_DEVAD_NONE, + MII_ADVERTISE, + ADVERTISE_10HALF | ADVERTISE_100HALF); + + return 0; +} + +static void mt798x_i2p5ge_print_fw_info(const void *fwdata, size_t fwsize) +{ + const struct mtk_i2p5ge_fw_info *info; + u8 ver_minor, ver_patch; + + info = (const void *)((uintptr_t)fwdata + fwsize - sizeof(*info)); + + ver_minor = info->ver[1] >> 4; + ver_patch = info->ver[1] & 0xf; + + printf("Firmware loaded, date %02x%02x/%02x/%02x, ver %x.%u.%u\n", + info->datecode[0], info->datecode[1], info->datecode[2], + info->datecode[3], info->ver[0], ver_minor, ver_patch); +} + +int __weak mt7987_i2p5ge_get_fw(void **fw, size_t *fwsize, + void **dspfw, size_t *dspfwsize) +{ + void *pmb, *dsp; + int ret; + + pmb = malloc(MT7987_2P5GE_PMB_FW_SIZE); + if (!pmb) + return -ENOMEM; + + ret = request_firmware_into_buf_via_script( + &pmb, MT7987_2P5GE_PMB_FW_SIZE, + "mt7987_i2p5ge_load_pmb_firmware", fwsize); + if (ret) { + free(pmb); + return ret; + } + + dsp = malloc(MT7987_2P5GE_DSPBITTB_SIZE); + if (!dsp) { + free(pmb); + return -ENOMEM; + } + + ret = request_firmware_into_buf_via_script( + &dsp, MT7987_2P5GE_DSPBITTB_SIZE, + "mt7987_i2p5ge_load_dspbit_firmware", dspfwsize); + if (ret) { + free(pmb); + free(dsp); + return ret; + } + + *fw = pmb; + *dspfw = dsp; + + return 1; +} + +static int mt7987_i2p5ge_download_dspfw(struct mtk_i2p5ge_priv *priv, + const void *dspfw_data) +{ + const u32 *dspfw; + u32 i; + + pbus_rmw(priv, SMEM_CTRL, 0, SMEM_HW_RDATA_ZERO); + + pbus_rmw(priv, PHY_CTRL_CONFIG, 0, BIT(16)); + + /* Initialize data memory */ + pbus_rmw(priv, DM_CTRL_P01, 0, BIT(28)); + pbus_rmw(priv, DM_CTRL_P23, 0, BIT(28)); + + /* Initialize coefficient memory */ + pbus_rmw(priv, CM_CTRL_P01, 0, BIT(28)); + pbus_rmw(priv, CM_CTRL_P23, 0, BIT(28)); + + /* Initialize PM offset */ + pbus_write(priv, SMEM_ADDR_REF_ADDR, 0); + + /* Assume DSP bit data is 4-byte aligned */ + dspfw = dspfw_data; + + for (i = 0; i < (MT7987_2P5GE_DSPBITTB_SIZE >> 2); i += 4) { + pbus_write(priv, SMEM_WDAT0, dspfw[i]); + pbus_write(priv, SMEM_WDAT1, dspfw[i + 1]); + pbus_write(priv, SMEM_WDAT2, dspfw[i + 2]); + pbus_write(priv, SMEM_WDAT3, dspfw[i + 3]); + } + + pbus_rmw(priv, DM_CTRL_P01, BIT(28), 0); + pbus_rmw(priv, DM_CTRL_P23, BIT(28), 0); + + pbus_rmw(priv, CM_CTRL_P01, BIT(28), 0); + pbus_rmw(priv, CM_CTRL_P23, BIT(28), 0); + + return 0; +} + +static int mt7987_i2p5ge_phy_load_fw(struct phy_device *phydev) +{ + struct mtk_i2p5ge_priv *priv = phydev->priv; + size_t fw_size, dspfw_size; + void __iomem *apb_base; + void *fw, *dspfw; + int ret, fwrc; + u32 reg; + + apb_base = ioremap(MTK_2P5GPHY_APB_BASE, MTK_2P5GPHY_APB_SIZE); + if (!apb_base) + return -ENODEV; + + fwrc = mt7987_i2p5ge_get_fw(&fw, &fw_size, &dspfw, &dspfw_size); + if (fwrc < 0) { + dev_err(phydev->dev, "Failed to get firmware data\n"); + return -EINVAL; + } + + if (fw_size != MT7987_2P5GE_PMB_FW_SIZE) { + dev_err(phydev->dev, + "PMB firmware size mismatch (0x%zx != 0x%x)\n", + fw_size, MT7987_2P5GE_PMB_FW_SIZE); + ret = -EINVAL; + goto cleanup; + } + + if (dspfw_size != MT7987_2P5GE_DSPBITTB_SIZE) { + dev_err(phydev->dev, + "DSP code size mismatch (0x%zx != 0x%x)\n", + dspfw_size, MT7987_2P5GE_DSPBITTB_SIZE); + ret = -EINVAL; + goto cleanup; + } + + /* Force 2.5Gphy back to AN state */ + phy_set_bits_mmd(phydev, MDIO_DEVAD_NONE, MII_BMCR, BMCR_RESET); + mdelay(5); + phy_set_bits_mmd(phydev, MDIO_DEVAD_NONE, MII_BMCR, BMCR_PDOWN); + + clrbits_le16(apb_base + SW_RESET, MD32_RESTART_EN_CLEAR); + setbits_le16(apb_base + SW_RESET, MD32_RESTART_EN_CLEAR); + clrbits_le16(apb_base + SW_RESET, MD32_RESTART_EN_CLEAR); + + pbus_rmw(priv, MD32_EN_CFG, MD32_EN, 0); + + ret = mt798x_i2p5ge_download_fw(priv, MT7987_2P5GE_PMB_FW_SIZE, fw); + if (ret) + goto cleanup; + + /* Enable 100Mbps module clock. */ + pbus_rmw(priv, FNPLL_PWR_CTRL1, RG_SPEED_MASK, RG_SPEED_100); + + /* Check if 100Mbps module clock is ready. */ + ret = readl_poll_timeout(priv->reg_base + FNPLL_PWR_CTRL_STATUS, reg, + reg & RG_SPEED_100_STABLE, 10000); + if (ret) { + dev_err(phydev->dev, + "Timed out enabling 100Mbps module clock\n"); + } + + /* Enable 2.5Gbps module clock. */ + pbus_rmw(priv, FNPLL_PWR_CTRL1, RG_SPEED_MASK, RG_SPEED_2500); + + /* Check if 2.5Gbps module clock is ready. */ + ret = readl_poll_timeout(priv->reg_base + FNPLL_PWR_CTRL_STATUS, reg, + reg & RG_SPEED_2500_STABLE, 10000); + + if (ret) { + dev_err(phydev->dev, + "Timed out enabling 2.5Gbps module clock\n"); + } + + /* Disable AN */ + phy_clear_bits_mmd(phydev, MDIO_DEVAD_NONE, MII_BMCR, BMCR_ANENABLE); + + /* Force to run at 2.5G speed */ + phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_AN_FORCE_SPEED_REG, + MTK_PHY_MASTER_FORCE_SPEED_SEL_MASK, + MTK_PHY_MASTER_FORCE_SPEED_SEL_EN | + FIELD_PREP(MTK_PHY_MASTER_FORCE_SPEED_SEL_MASK, 0x1b)); + + phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_LINK_STATUS_RELATED, + MTK_PHY_BYPASS_LINK_STATUS_OK | + MTK_PHY_FORCE_LINK_STATUS_HCD); + + /* Set xbz, pma and rx as "do not reset" in order to input DSP code. */ + pbus_rmw(priv, DO_NOT_RESET, 0, + DO_NOT_RESET_XBZ | DO_NOT_RESET_PMA | DO_NOT_RESET_RX); + + pbus_rmw(priv, SYS_SW_RESET, RESET_RST_CNT, 0); + + pbus_write(priv, PMU_WP, WRITE_PROTECT_KEY); + + pbus_rmw(priv, PMU_PMA_AUTO_CFG, 0, + PMU_AUTO_MODE_EN | POWER_ON_AUTO_MODE); + + /* Check if clock in auto mode is disabled. */ + ret = readl_poll_timeout(priv->reg_base + PMU_PMA_STATUS, reg, + (reg & CLK_IS_DISABLED) == 0x0, 100000); + if (ret) + dev_err(phydev->dev, "Timed out enabling clock auto mode\n"); + + ret = mt7987_i2p5ge_download_dspfw(priv, dspfw); + if (ret) + goto cleanup; + + pbus_rmw(priv, MD32_EN_CFG, 0, MD32_EN); + + phy_set_bits_mmd(phydev, MDIO_DEVAD_NONE, MII_BMCR, BMCR_RESET); + + /* We need a delay here to stabilize initialization of MCU */ + mdelay(8); + + mt798x_i2p5ge_print_fw_info(fw, fw_size); + +cleanup: + if (fwrc > 0) { + free(fw); + free(dspfw); + } + + iounmap(apb_base); + + return ret; +} + +static int mt7987_i2p5ge_phy_config(struct phy_device *phydev) +{ + phy_clear_bits_mmd(phydev, MDIO_MMD_VEND2, MTK_PHY_LED0_ON_CTRL, + MTK_PHY_LED_ON_POLARITY); + + phy_clear_bits_mmd(phydev, MDIO_MMD_VEND2, MT7987_OPTIONS, + NORMAL_RETRAIN_DISABLE); + + return mt798x_i2p5ge_phy_config(phydev); +} + +static int mt7987_i2p5ge_phy_probe(struct phy_device *phydev) +{ + int ret; + + ret = mt798x_i2p5ge_phy_probe(phydev); + if (ret) + return ret; + + return mt7987_i2p5ge_phy_load_fw(phydev); +} + +int __weak mt7988_i2p5ge_get_fw(void **fw, size_t *size) +{ + void *pmb; + int ret; + + pmb = malloc(MT7988_2P5GE_PMB_FW_SIZE); + if (!pmb) + return -ENOMEM; + + ret = request_firmware_into_buf_via_script( + &pmb, MT7988_2P5GE_PMB_FW_SIZE, + "mt7988_i2p5ge_load_pmb_firmware", size); + if (ret) { + free(pmb); + return ret; + } + + *fw = pmb; + + return 1; +} + +static int mt7988_i2p5ge_phy_load_fw(struct phy_device *phydev) +{ + struct mtk_i2p5ge_priv *priv = phydev->priv; + size_t fw_size; + int ret, fwrc; + void *fw; + + fwrc = mt7988_i2p5ge_get_fw(&fw, &fw_size); + if (fwrc < 0) { + dev_err(phydev->dev, "Failed to get firmware data\n"); + return -EINVAL; + } + + if (fw_size != MT7988_2P5GE_PMB_FW_SIZE) { + dev_err(phydev->dev, "Firmware size mismatch (0x%zx != 0x%x)\n", + fw_size, MT7988_2P5GE_PMB_FW_SIZE); + ret = -EINVAL; + goto cleanup; + } + + ret = mt798x_i2p5ge_download_fw(priv, MT7988_2P5GE_PMB_FW_SIZE, fw); + if (ret) + goto cleanup; + + pbus_rmw(priv, MD32_EN_CFG, MD32_EN, 0); + pbus_rmw(priv, MD32_EN_CFG, 0, MD32_EN); + + phy_set_bits_mmd(phydev, MDIO_DEVAD_NONE, MII_BMCR, BMCR_RESET); + + /* We need a delay here to stabilize initialization of MCU */ + mdelay(8); + + mt798x_i2p5ge_print_fw_info(fw, fw_size); + +cleanup: + if (fwrc > 0) + free(fw); + + return ret; +} + +static int mt7988_i2p5ge_phy_config(struct phy_device *phydev) +{ + phy_set_bits_mmd(phydev, MDIO_MMD_VEND2, MTK_PHY_LED0_ON_CTRL, + MTK_PHY_LED_ON_POLARITY); + + return mt798x_i2p5ge_phy_config(phydev); +} + +static int mt7988_i2p5ge_phy_probe(struct phy_device *phydev) +{ + int ret; + + ret = mt798x_i2p5ge_phy_probe(phydev); + if (ret) + return ret; + + return mt7988_i2p5ge_phy_load_fw(phydev); +} + +static int mt798x_i2p5ge_phy_startup(struct phy_device *phydev) +{ + struct mtk_i2p5ge_priv *priv = phydev->priv; + int ret; + + ret = genphy_update_link(phydev); + if (ret) + return ret; + + /* Initialize speed/duplex */ + phydev->speed = SPEED_10; + phydev->duplex = DUPLEX_HALF; + + if (phydev->link) { + ret = phy_read(phydev, MDIO_DEVAD_NONE, PHY_AUX_CTRL_STATUS); + if (ret < 0) + return ret; + + switch (FIELD_GET(PHY_AUX_SPEED_MASK, ret)) { + case PHY_AUX_SPD_10: + phydev->speed = SPEED_10; + break; + + case PHY_AUX_SPD_100: + phydev->speed = SPEED_100; + break; + + case PHY_AUX_SPD_1000: + pbus_rmw(priv, FIFO_CTRL, + TX_SFIFO_IDLE_CNT_MASK | TX_SFIFO_DEL_IPG_WM_MASK, + FIELD_PREP(TX_SFIFO_IDLE_CNT_MASK, 0x1) | + FIELD_PREP(TX_SFIFO_DEL_IPG_WM_MASK, 0x10)); + pbus_rmw(priv, MIN_IPG_NUM, LS_MIN_IPG_NUM_MASK, + FIELD_PREP(LS_MIN_IPG_NUM_MASK, 0xa)); + pbus_rmw(priv, FC_LWM, TX_FC_LWM_MASK, + FIELD_PREP(TX_FC_LWM_MASK, 0x340)); + phydev->speed = SPEED_1000; + break; + + case PHY_AUX_SPD_2500: + phydev->speed = SPEED_2500; + break; + + default: + break; + } + + /* This PHY always operates in full duplex */ + phydev->duplex = DUPLEX_FULL; + } + + return 0; +} + +U_BOOT_PHY_DRIVER(mt7987_i2p5ge) = { + .name = "MediaTek MT7987 built-in 2.5GbE PHY", + .uid = MTK_2P5GPHY_ID_MT7987, + .mask = 0xfffffff0, + .features = PHY_10G_FEATURES, + .mmds = (MDIO_MMD_PCS | MDIO_MMD_AN | MDIO_MMD_VEND1 | MDIO_MMD_VEND2), + .probe = &mt7987_i2p5ge_phy_probe, + .config = &mt7987_i2p5ge_phy_config, + .startup = &mt798x_i2p5ge_phy_startup, + .shutdown = &genphy_shutdown, +}; + +U_BOOT_PHY_DRIVER(mt7988_i2p5ge) = { + .name = "MediaTek MT7988 built-in 2.5GbE PHY", + .uid = MTK_2P5GPHY_ID_MT7988, + .mask = 0xfffffff0, + .features = PHY_10G_FEATURES, + .mmds = (MDIO_MMD_PCS | MDIO_MMD_AN | MDIO_MMD_VEND1 | MDIO_MMD_VEND2), + .probe = &mt7988_i2p5ge_phy_probe, + .config = &mt7988_i2p5ge_phy_config, + .startup = &mt798x_i2p5ge_phy_startup, + .shutdown = &genphy_shutdown, +}; diff --git a/drivers/net/phy/mediatek/mtk-phy-lib.c b/drivers/net/phy/mediatek/mtk-phy-lib.c new file mode 100644 index 00000000000..55e7a6b6eec --- /dev/null +++ b/drivers/net/phy/mediatek/mtk-phy-lib.c @@ -0,0 +1,106 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2025 MediaTek Inc. All Rights Reserved. + * + * Author: Sky Huang + */ +#include +#include + +#include "mtk.h" + +void mtk_phy_select_page(struct phy_device *phydev, int page) +{ + phy_write(phydev, MDIO_DEVAD_NONE, MTK_EXT_PAGE_ACCESS, page); +} + +void mtk_phy_restore_page(struct phy_device *phydev) +{ + phy_write(phydev, MDIO_DEVAD_NONE, MTK_EXT_PAGE_ACCESS, + MTK_PHY_PAGE_STANDARD); +} + +/* Difference between functions with mtk_tr* and __mtk_tr* prefixes is + * mtk_tr* functions: wrapped by page switching operations + * __mtk_tr* functions: no page switching operations + */ +static void __mtk_tr_access(struct phy_device *phydev, bool read, u8 ch_addr, + u8 node_addr, u8 data_addr) +{ + u16 tr_cmd = BIT(15); /* bit 14 & 0 are reserved */ + + if (read) + tr_cmd |= BIT(13); + + tr_cmd |= (((ch_addr & 0x3) << 11) | + ((node_addr & 0xf) << 7) | + ((data_addr & 0x3f) << 1)); + dev_dbg(phydev->dev, "tr_cmd: 0x%x\n", tr_cmd); + phy_write(phydev, MDIO_DEVAD_NONE, 0x10, tr_cmd); +} + +static void __mtk_tr_read(struct phy_device *phydev, u8 ch_addr, u8 node_addr, + u8 data_addr, u16 *tr_high, u16 *tr_low) +{ + __mtk_tr_access(phydev, true, ch_addr, node_addr, data_addr); + *tr_low = phy_read(phydev, MDIO_DEVAD_NONE, 0x11); + *tr_high = phy_read(phydev, MDIO_DEVAD_NONE, 0x12); + dev_dbg(phydev->dev, "tr_high read: 0x%x, tr_low read: 0x%x\n", + *tr_high, *tr_low); +} + +u32 mtk_tr_read(struct phy_device *phydev, u8 ch_addr, u8 node_addr, + u8 data_addr) +{ + u16 tr_high; + u16 tr_low; + + mtk_phy_select_page(phydev, MTK_PHY_PAGE_EXTENDED_52B5); + __mtk_tr_read(phydev, ch_addr, node_addr, data_addr, &tr_high, &tr_low); + mtk_phy_restore_page(phydev); + + return (tr_high << 16) | tr_low; +} + +static void __mtk_tr_write(struct phy_device *phydev, u8 ch_addr, u8 node_addr, + u8 data_addr, u32 tr_data) +{ + phy_write(phydev, MDIO_DEVAD_NONE, 0x11, tr_data & 0xffff); + phy_write(phydev, MDIO_DEVAD_NONE, 0x12, tr_data >> 16); + dev_dbg(phydev->dev, "tr_high write: 0x%x, tr_low write: 0x%x\n", + tr_data >> 16, tr_data & 0xffff); + __mtk_tr_access(phydev, false, ch_addr, node_addr, data_addr); +} + +void __mtk_tr_modify(struct phy_device *phydev, u8 ch_addr, u8 node_addr, + u8 data_addr, u32 mask, u32 set) +{ + u32 tr_data; + u16 tr_high; + u16 tr_low; + + __mtk_tr_read(phydev, ch_addr, node_addr, data_addr, &tr_high, &tr_low); + tr_data = (tr_high << 16) | tr_low; + tr_data = (tr_data & ~mask) | set; + __mtk_tr_write(phydev, ch_addr, node_addr, data_addr, tr_data); +} + +void mtk_tr_modify(struct phy_device *phydev, u8 ch_addr, u8 node_addr, + u8 data_addr, u32 mask, u32 set) +{ + mtk_phy_select_page(phydev, MTK_PHY_PAGE_EXTENDED_52B5); + __mtk_tr_modify(phydev, ch_addr, node_addr, data_addr, mask, set); + mtk_phy_restore_page(phydev); +} + +void __mtk_tr_set_bits(struct phy_device *phydev, u8 ch_addr, u8 node_addr, + u8 data_addr, u32 set) +{ + __mtk_tr_modify(phydev, ch_addr, node_addr, data_addr, 0, set); +} + +void __mtk_tr_clr_bits(struct phy_device *phydev, u8 ch_addr, u8 node_addr, + u8 data_addr, u32 clr) +{ + __mtk_tr_modify(phydev, ch_addr, node_addr, data_addr, clr, 0); +} diff --git a/drivers/net/phy/mediatek/mtk.h b/drivers/net/phy/mediatek/mtk.h new file mode 100644 index 00000000000..68044cbdb32 --- /dev/null +++ b/drivers/net/phy/mediatek/mtk.h @@ -0,0 +1,103 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2025 MediaTek Inc. All Rights Reserved. + * + * Author: Sky Huang + * + * Common definition for Mediatek Ethernet PHYs + */ + +#ifndef _MTK_EPHY_H_ +#define _MTK_EPHY_H_ + +#define MTK_EXT_PAGE_ACCESS 0x1f +#define MTK_PHY_PAGE_STANDARD 0x0000 +#define MTK_PHY_PAGE_EXTENDED_1 0x0001 +#define MTK_PHY_AUX_CTRL_AND_STATUS 0x14 +/* suprv_media_select_RefClk */ +#define MTK_PHY_LP_DETECTED_MASK GENMASK(7, 6) +#define MTK_PHY_ENABLE_DOWNSHIFT BIT(4) + +#define MTK_PHY_PAGE_EXTENDED_52B5 0x52b5 + +/* Registers on Token Ring debug nodes */ +/* ch_addr = 0x0, node_addr = 0xf, data_addr = 0x2 */ +#define AN_STATE_MASK GENMASK(22, 19) +#define AN_STATE_SHIFT 19 +#define AN_STATE_TX_DISABLE 1 + +/* ch_addr = 0x0, node_addr = 0xf, data_addr = 0x3c */ +#define AN_NEW_LP_CNT_LIMIT_MASK GENMASK(23, 20) +#define AUTO_NP_10XEN BIT(6) + +/* Registers on MDIO_MMD_VEND1 */ +#define MTK_PHY_LINK_STATUS_MISC (0xa2) +#define MTK_PHY_FINAL_SPEED_1000 BIT(3) + +/* Registers on MDIO_MMD_VEND2 */ +#define MTK_PHY_LED0_ON_CTRL 0x24 +#define MTK_PHY_LED1_ON_CTRL 0x26 +#define MTK_GPHY_LED_ON_MASK GENMASK(6, 0) +#define MTK_2P5GPHY_LED_ON_MASK GENMASK(7, 0) +#define MTK_PHY_LED_ON_LINK1000 BIT(0) +#define MTK_PHY_LED_ON_LINK100 BIT(1) +#define MTK_PHY_LED_ON_LINK10 BIT(2) +#define MTK_PHY_LED_ON_LINKDOWN BIT(3) +#define MTK_PHY_LED_ON_FDX BIT(4) /* Full duplex */ +#define MTK_PHY_LED_ON_HDX BIT(5) /* Half duplex */ +#define MTK_PHY_LED_ON_FORCE_ON BIT(6) +#define MTK_PHY_LED_ON_LINK2500 BIT(7) +#define MTK_PHY_LED_ON_POLARITY BIT(14) +#define MTK_PHY_LED_ON_ENABLE BIT(15) + +#define MTK_PHY_LED0_BLINK_CTRL 0x25 +#define MTK_PHY_LED1_BLINK_CTRL 0x27 +#define MTK_PHY_LED_BLINK_1000TX BIT(0) +#define MTK_PHY_LED_BLINK_1000RX BIT(1) +#define MTK_PHY_LED_BLINK_100TX BIT(2) +#define MTK_PHY_LED_BLINK_100RX BIT(3) +#define MTK_PHY_LED_BLINK_10TX BIT(4) +#define MTK_PHY_LED_BLINK_10RX BIT(5) +#define MTK_PHY_LED_BLINK_COLLISION BIT(6) +#define MTK_PHY_LED_BLINK_RX_CRC_ERR BIT(7) +#define MTK_PHY_LED_BLINK_RX_IDLE_ERR BIT(8) +#define MTK_PHY_LED_BLINK_FORCE_BLINK BIT(9) +#define MTK_PHY_LED_BLINK_2500TX BIT(10) +#define MTK_PHY_LED_BLINK_2500RX BIT(11) + +#define MTK_GPHY_LED_ON_SET (MTK_PHY_LED_ON_LINK1000 | \ + MTK_PHY_LED_ON_LINK100 | \ + MTK_PHY_LED_ON_LINK10) +#define MTK_GPHY_LED_RX_BLINK_SET (MTK_PHY_LED_BLINK_1000RX | \ + MTK_PHY_LED_BLINK_100RX | \ + MTK_PHY_LED_BLINK_10RX) +#define MTK_GPHY_LED_TX_BLINK_SET (MTK_PHY_LED_BLINK_1000RX | \ + MTK_PHY_LED_BLINK_100RX | \ + MTK_PHY_LED_BLINK_10RX) + +#define MTK_2P5GPHY_LED_ON_SET (MTK_PHY_LED_ON_LINK2500 | \ + MTK_GPHY_LED_ON_SET) +#define MTK_2P5GPHY_LED_RX_BLINK_SET (MTK_PHY_LED_BLINK_2500RX | \ + MTK_GPHY_LED_RX_BLINK_SET) +#define MTK_2P5GPHY_LED_TX_BLINK_SET (MTK_PHY_LED_BLINK_2500RX | \ + MTK_GPHY_LED_TX_BLINK_SET) + +#define MTK_PHY_LED_STATE_FORCE_ON 0 +#define MTK_PHY_LED_STATE_FORCE_BLINK 1 +#define MTK_PHY_LED_STATE_NETDEV 2 + +void mtk_phy_select_page(struct phy_device *phydev, int page); +void mtk_phy_restore_page(struct phy_device *phydev); + +u32 mtk_tr_read(struct phy_device *phydev, u8 ch_addr, u8 node_addr, + u8 data_addr); +void __mtk_tr_modify(struct phy_device *phydev, u8 ch_addr, u8 node_addr, + u8 data_addr, u32 mask, u32 set); +void mtk_tr_modify(struct phy_device *phydev, u8 ch_addr, u8 node_addr, + u8 data_addr, u32 mask, u32 set); +void __mtk_tr_set_bits(struct phy_device *phydev, u8 ch_addr, u8 node_addr, + u8 data_addr, u32 set); +void __mtk_tr_clr_bits(struct phy_device *phydev, u8 ch_addr, u8 node_addr, + u8 data_addr, u32 clr); + +#endif /* _MTK_EPHY_H_ */ -- cgit v1.2.3 From 32b4c88ff2712ffafec875e22d866537d2f33dac Mon Sep 17 00:00:00 2001 From: Weijie Gao Date: Mon, 8 Sep 2025 16:34:23 +0800 Subject: MAINTAINERS: update ethernet-related file list for MediaTek ARM platform Update ethernet-related files for MediaTek ARM platform Signed-off-by: Weijie Gao --- MAINTAINERS | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/MAINTAINERS b/MAINTAINERS index 3fb163aa1db..065834246de 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -423,6 +423,8 @@ F: drivers/clk/mediatek/ F: drivers/cpu/mtk_cpu.c F: drivers/i2c/mtk_i2c.c F: drivers/mmc/mtk-sd.c +F: drivers/net/mtk_eth/ +F: drivers/net/phy/mediatek/ F: drivers/phy/phy-mtk-* F: drivers/pinctrl/mediatek/ F: drivers/power/domain/mtk-power-domain.c @@ -437,8 +439,6 @@ F: drivers/timer/mtk_timer.c F: drivers/usb/host/xhci-mtk.c F: drivers/usb/mtu3/ F: drivers/watchdog/mtk_wdt.c -F: drivers/net/mtk_eth.c -F: drivers/net/mtk_eth.h F: drivers/reset/reset-mediatek.c F: drivers/serial/serial_mtk.c F: include/dt-bindings/clock/mediatek,* -- cgit v1.2.3 From e18a0dec6e383bf903b7b577201fece58122dae8 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Mon, 8 Sep 2025 15:48:16 +0200 Subject: boot: Increase kernel size limit to 128 MiB on ARM64/PPC/RV The ARM64 kernel Image size with LOCKDEP enabled is now around 80 MiB, which makes it unbootable due to "Image too large: increase CONFIG_SYS_BOOTM_LEN". Increase the image size limit to 128 MiB to future proof the limit. Signed-off-by: Marek Vasut --- boot/Kconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/boot/Kconfig b/boot/Kconfig index 124f6db3e6e..dd047365754 100644 --- a/boot/Kconfig +++ b/boot/Kconfig @@ -1056,7 +1056,7 @@ config SYS_BOOTM_LEN hex "Maximum size of a decompresed OS image" depends on CMD_BOOTM || CMD_BOOTI || CMD_BOOTZ || \ LEGACY_IMAGE_FORMAT || SPL_LEGACY_IMAGE_FORMAT - default 0x4000000 if PPC || ARM64 || RISCV + default 0x8000000 if PPC || ARM64 || RISCV default 0x1000000 if X86 || ARCH_MX6 || ARCH_MX7 default 0x800000 help -- cgit v1.2.3 From 30fbbde2cdfaebb1db47d7c0d457a32e3c6552c3 Mon Sep 17 00:00:00 2001 From: Jim Liu Date: Wed, 10 Sep 2025 10:16:17 +0800 Subject: arm: nuvoton: remove unused parameter remove CFG_SYS_BOOTM_LEN parameter Signed-off-by: Jim Liu --- include/configs/arbel.h | 1 - 1 file changed, 1 deletion(-) diff --git a/include/configs/arbel.h b/include/configs/arbel.h index b5f684e88fe..63112baf9b2 100644 --- a/include/configs/arbel.h +++ b/include/configs/arbel.h @@ -8,7 +8,6 @@ #define CFG_SYS_SDRAM_BASE 0x0 #define CFG_SYS_BOOTMAPSZ (192 << 20) -#define CFG_SYS_BOOTM_LEN (20 << 20) #define CFG_SYS_INIT_RAM_ADDR CFG_SYS_SDRAM_BASE #define CFG_SYS_INIT_RAM_SIZE 0x8000 -- cgit v1.2.3 From 707e465cb1caab150997848d037cc6fb3f3ca861 Mon Sep 17 00:00:00 2001 From: Yao Zi Date: Wed, 13 Aug 2025 10:09:24 +0000 Subject: configs: th1520_lpi4a: Enlarge SYS_MALLOC_F_LEN to 0x10000 For TH1520, we want clock and pinctrl drivers to bind before relocation along with the UART which makes use of them, since upstream devicetree specifies pinctrl properties for the UART. This requires a large malloc pool before relocation, let's enlarge it. Signed-off-by: Yao Zi Reviewed-by: Leo Yu-Chi Liang --- configs/th1520_lpi4a_defconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/configs/th1520_lpi4a_defconfig b/configs/th1520_lpi4a_defconfig index 48cd8991591..85d7a638b86 100644 --- a/configs/th1520_lpi4a_defconfig +++ b/configs/th1520_lpi4a_defconfig @@ -1,6 +1,6 @@ CONFIG_RISCV=y CONFIG_SYS_MALLOC_LEN=0x800000 -CONFIG_SYS_MALLOC_F_LEN=0x3000 +CONFIG_SYS_MALLOC_F_LEN=0x10000 CONFIG_SPL_GPIO=y CONFIG_NR_DRAM_BANKS=1 CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y -- cgit v1.2.3 From fbcf53680be59fd8144f865f8cfd840319cb5c0d Mon Sep 17 00:00:00 2001 From: Yao Zi Date: Wed, 13 Aug 2025 10:09:25 +0000 Subject: clk: thead: th1520-ap: Mark drivers as DM_FLAG_PRE_RELOC It's common that UARTs are bound and probed before U-Boot relocation, in which case the clocks of UART and UART's pincontroller must be registered first. Let's apply DM_FLAG_PRE_RELOC to the driver, allowing it to bind before relocation. Signed-off-by: Yao Zi Reviewed-by: Leo Yu-Chi Liang --- drivers/clk/thead/clk-th1520-ap.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/clk/thead/clk-th1520-ap.c b/drivers/clk/thead/clk-th1520-ap.c index 822cf0809d5..6899e1b595a 100644 --- a/drivers/clk/thead/clk-th1520-ap.c +++ b/drivers/clk/thead/clk-th1520-ap.c @@ -235,6 +235,7 @@ U_BOOT_DRIVER(th1520_clk_div) = { .name = "th1520_clk_div", .id = UCLASS_CLK, .ops = &ccu_div_ops, + .flags = DM_FLAG_PRE_RELOC, }; static unsigned long th1520_pll_vco_recalc_rate(struct clk *clk, @@ -302,6 +303,7 @@ U_BOOT_DRIVER(th1520_clk_pll) = { .name = "th1520_clk_pll", .id = UCLASS_CLK, .ops = &clk_pll_ops, + .flags = DM_FLAG_PRE_RELOC, }; static struct ccu_pll cpu_pll0_clk = { @@ -1030,4 +1032,5 @@ U_BOOT_DRIVER(th1520_clk) = { .of_match = th1520_clk_match, .probe = th1520_clk_probe, .ops = &th1520_clk_ops, + .flags = DM_FLAG_PRE_RELOC, }; -- cgit v1.2.3 From 9d8a4728e14eb3971652c30dc262312d5a544a4e Mon Sep 17 00:00:00 2001 From: Yao Zi Date: Wed, 13 Aug 2025 10:09:26 +0000 Subject: pinctrl: th1520: Mark driver as DM_FLAG_PRE_RELOC It's common that UARTs are bound and probed before U-Boot relocation, in which case the UART's pincontroller and pinconfig must be probed first. Let's apply DM_FLAG_PRE_RELOC to the driver, allow it to bind before relocation. Signed-off-by: Yao Zi Reviewed-by: Leo Yu-Chi Liang --- drivers/pinctrl/pinctrl-th1520.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/pinctrl/pinctrl-th1520.c b/drivers/pinctrl/pinctrl-th1520.c index be7e508f8a4..4eead0875d8 100644 --- a/drivers/pinctrl/pinctrl-th1520.c +++ b/drivers/pinctrl/pinctrl-th1520.c @@ -697,4 +697,5 @@ U_BOOT_DRIVER(th1520_pinctrl) = { .probe = th1520_pinctrl_probe, .priv_auto = sizeof(struct th1520_pinctrl), .ops = &th1520_pinctrl_ops, + .flags = DM_FLAG_PRE_RELOC, }; -- cgit v1.2.3 From 0d74bbfda38816dcb9b3e1b0fd63324849948443 Mon Sep 17 00:00:00 2001 From: Yao Zi Date: Wed, 13 Aug 2025 10:09:27 +0000 Subject: dts: th1520: Switch to upstream devicetree Imply OF_UPSTREAM in platform Kconfig option and adapt existing boards to use the correct upstream devicetree paths. Signed-off-by: Yao Zi Reviewed-by: Leo Yu-Chi Liang --- arch/riscv/cpu/th1520/Kconfig | 1 + arch/riscv/dts/Makefile | 1 - arch/riscv/dts/th1520-lichee-module-4a-u-boot.dtsi | 10 + arch/riscv/dts/th1520-lichee-module-4a.dtsi | 164 ------- arch/riscv/dts/th1520-lichee-pi-4a-u-boot.dtsi | 27 ++ arch/riscv/dts/th1520-lichee-pi-4a.dts | 33 -- arch/riscv/dts/th1520-u-boot.dtsi | 44 ++ arch/riscv/dts/th1520.dtsi | 530 --------------------- configs/th1520_lpi4a_defconfig | 2 +- 9 files changed, 83 insertions(+), 729 deletions(-) create mode 100644 arch/riscv/dts/th1520-lichee-module-4a-u-boot.dtsi delete mode 100644 arch/riscv/dts/th1520-lichee-module-4a.dtsi create mode 100644 arch/riscv/dts/th1520-lichee-pi-4a-u-boot.dtsi delete mode 100644 arch/riscv/dts/th1520-lichee-pi-4a.dts create mode 100644 arch/riscv/dts/th1520-u-boot.dtsi delete mode 100644 arch/riscv/dts/th1520.dtsi diff --git a/arch/riscv/cpu/th1520/Kconfig b/arch/riscv/cpu/th1520/Kconfig index c73462c04b8..a02f5f24906 100644 --- a/arch/riscv/cpu/th1520/Kconfig +++ b/arch/riscv/cpu/th1520/Kconfig @@ -21,3 +21,4 @@ config THEAD_TH1520 imply SPL_CPU imply SPL_OPENSBI imply SPL_LOAD_FIT + imply OF_UPSTREAM diff --git a/arch/riscv/dts/Makefile b/arch/riscv/dts/Makefile index a637727b76b..9b347fc3b50 100644 --- a/arch/riscv/dts/Makefile +++ b/arch/riscv/dts/Makefile @@ -12,7 +12,6 @@ dtb-$(CONFIG_TARGET_OPENPITON_RISCV64) += openpiton-riscv64.dtb dtb-$(CONFIG_TARGET_SIFIVE_UNLEASHED) += hifive-unleashed-a00.dtb dtb-$(CONFIG_TARGET_SIFIVE_UNMATCHED) += hifive-unmatched-a00.dtb dtb-$(CONFIG_TARGET_SIPEED_MAIX) += k210-maix-bit.dtb -dtb-$(CONFIG_TARGET_TH1520_LPI4A) += th1520-lichee-pi-4a.dtb dtb-$(CONFIG_TARGET_XILINX_MBV) += xilinx-mbv32.dtb dtb-$(CONFIG_TARGET_XILINX_MBV) += xilinx-mbv64.dtb dtb-$(CONFIG_TARGET_XILINX_MBV) += xilinx-binman.dtb diff --git a/arch/riscv/dts/th1520-lichee-module-4a-u-boot.dtsi b/arch/riscv/dts/th1520-lichee-module-4a-u-boot.dtsi new file mode 100644 index 00000000000..bbfa3c499cf --- /dev/null +++ b/arch/riscv/dts/th1520-lichee-module-4a-u-boot.dtsi @@ -0,0 +1,10 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2025 Yao Zi + */ + +#include "th1520-u-boot.dtsi" + +&{/memory@0} { + bootph-pre-ram; +}; diff --git a/arch/riscv/dts/th1520-lichee-module-4a.dtsi b/arch/riscv/dts/th1520-lichee-module-4a.dtsi deleted file mode 100644 index eecd3e9832a..00000000000 --- a/arch/riscv/dts/th1520-lichee-module-4a.dtsi +++ /dev/null @@ -1,164 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Copyright (C) 2023 Jisheng Zhang - */ - -/dts-v1/; - -#include "th1520.dtsi" - -/ { - model = "Sipeed Lichee Module 4A"; - compatible = "sipeed,lichee-module-4a", "thead,th1520"; - - aliases { - ethernet0 = &gmac0; - ethernet1 = &gmac1; - }; - - memory@0 { - device_type = "memory"; - reg = <0x0 0x00000000 0x2 0x00000000>; - bootph-pre-ram; - }; -}; - -&osc { - clock-frequency = <24000000>; -}; - -&osc_32k { - clock-frequency = <32768>; -}; - -&emmc { - bus-width = <8>; - max-frequency = <198000000>; - mmc-ddr-1_8v; - mmc-hs400-1_8v; - mmc-hs400-enhanced-strobe; - non-removable; - no-sdio; - no-sd; - status = "okay"; -}; - -&gmac0 { - pinctrl-names = "default"; - pinctrl-0 = <&gmac0_pins>, <&mdio0_pins>; - phy-handle = <&phy0>; - phy-mode = "rgmii-id"; - status = "okay"; -}; - -&gmac1 { - pinctrl-names = "default"; - pinctrl-0 = <&gmac1_pins>; - phy-handle = <&phy1>; - phy-mode = "rgmii-id"; - status = "okay"; -}; - -&mdio0 { - phy0: ethernet-phy@1 { - reg = <1>; - }; - - phy1: ethernet-phy@2 { - reg = <2>; - }; -}; - -&padctrl0_apsys { - gmac0_pins: gmac0-0 { - tx-pins { - pins = "GMAC0_TX_CLK", - "GMAC0_TXEN", - "GMAC0_TXD0", - "GMAC0_TXD1", - "GMAC0_TXD2", - "GMAC0_TXD3"; - function = "gmac0"; - bias-disable; - drive-strength = <25>; - input-disable; - input-schmitt-disable; - slew-rate = <0>; - }; - - rx-pins { - pins = "GMAC0_RX_CLK", - "GMAC0_RXDV", - "GMAC0_RXD0", - "GMAC0_RXD1", - "GMAC0_RXD2", - "GMAC0_RXD3"; - function = "gmac0"; - bias-disable; - drive-strength = <1>; - input-enable; - input-schmitt-disable; - slew-rate = <0>; - }; - }; - - gmac1_pins: gmac1-0 { - tx-pins { - pins = "GPIO2_18", /* GMAC1_TX_CLK */ - "GPIO2_20", /* GMAC1_TXEN */ - "GPIO2_21", /* GMAC1_TXD0 */ - "GPIO2_22", /* GMAC1_TXD1 */ - "GPIO2_23", /* GMAC1_TXD2 */ - "GPIO2_24"; /* GMAC1_TXD3 */ - function = "gmac1"; - bias-disable; - drive-strength = <25>; - input-disable; - input-schmitt-disable; - slew-rate = <0>; - }; - - rx-pins { - pins = "GPIO2_19", /* GMAC1_RX_CLK */ - "GPIO2_25", /* GMAC1_RXDV */ - "GPIO2_30", /* GMAC1_RXD0 */ - "GPIO2_31", /* GMAC1_RXD1 */ - "GPIO3_0", /* GMAC1_RXD2 */ - "GPIO3_1"; /* GMAC1_RXD3 */ - function = "gmac1"; - bias-disable; - drive-strength = <1>; - input-enable; - input-schmitt-disable; - slew-rate = <0>; - }; - }; - - mdio0_pins: mdio0-0 { - mdc-pins { - pins = "GMAC0_MDC"; - function = "gmac0"; - bias-disable; - drive-strength = <13>; - input-disable; - input-schmitt-disable; - slew-rate = <0>; - }; - - mdio-pins { - pins = "GMAC0_MDIO"; - function = "gmac0"; - bias-disable; - drive-strength = <13>; - input-enable; - input-schmitt-enable; - slew-rate = <0>; - }; - }; -}; - -&sdio0 { - bus-width = <4>; - max-frequency = <198000000>; - status = "okay"; -}; diff --git a/arch/riscv/dts/th1520-lichee-pi-4a-u-boot.dtsi b/arch/riscv/dts/th1520-lichee-pi-4a-u-boot.dtsi new file mode 100644 index 00000000000..06d4a70d1ea --- /dev/null +++ b/arch/riscv/dts/th1520-lichee-pi-4a-u-boot.dtsi @@ -0,0 +1,27 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2025 Yao Zi + */ + +#include "th1520-lichee-module-4a-u-boot.dtsi" +#include "thead-th1520-binman.dtsi" + +&clk { + bootph-some-ram; +}; + +&padctrl0_apsys { + bootph-some-ram; +}; + +&uart0_pins { + bootph-some-ram; + + tx-pins { + bootph-some-ram; + }; + + rx-pins { + bootph-some-ram; + }; +}; diff --git a/arch/riscv/dts/th1520-lichee-pi-4a.dts b/arch/riscv/dts/th1520-lichee-pi-4a.dts deleted file mode 100644 index 49af88b7adf..00000000000 --- a/arch/riscv/dts/th1520-lichee-pi-4a.dts +++ /dev/null @@ -1,33 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Copyright (C) 2023 Jisheng Zhang - */ - -#include "th1520-lichee-module-4a.dtsi" -#include "thead-th1520-binman.dtsi" - -/ { - model = "Sipeed Lichee Pi 4A"; - compatible = "sipeed,lichee-pi-4a", "sipeed,lichee-module-4a", "thead,th1520"; - - aliases { - gpio0 = &gpio0; - gpio1 = &gpio1; - gpio2 = &gpio2; - gpio3 = &gpio3; - serial0 = &uart0; - serial1 = &uart1; - serial2 = &uart2; - serial3 = &uart3; - serial4 = &uart4; - serial5 = &uart5; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; -}; - -&uart0 { - status = "okay"; -}; diff --git a/arch/riscv/dts/th1520-u-boot.dtsi b/arch/riscv/dts/th1520-u-boot.dtsi new file mode 100644 index 00000000000..45ffccbb847 --- /dev/null +++ b/arch/riscv/dts/th1520-u-boot.dtsi @@ -0,0 +1,44 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2025 Yao Zi + */ + +&{/soc} { + ddrc: ddrc@fffd000000 { + compatible = "thead,th1520-ddrc"; + reg = <0xff 0xfd000000 0x0 0x1000000>, + <0xff 0xfe000000 0x0 0x1000000>, + <0xff 0xff000000 0x0 0x4000>, + <0xff 0xff005000 0x0 0x1000>; + reg-names = "phy-0", "phy-1", "ctrl", "sys"; + bootph-pre-ram; + }; +}; + +&cpus { + bootph-pre-ram; +}; + +&c910_0 { + bootph-pre-ram; +}; + +&c910_1 { + bootph-pre-ram; +}; + +&c910_2 { + bootph-pre-ram; +}; + +&c910_3 { + bootph-pre-ram; +}; + +&clint { + bootph-pre-ram; +}; + +&uart0 { + bootph-pre-ram; +}; diff --git a/arch/riscv/dts/th1520.dtsi b/arch/riscv/dts/th1520.dtsi deleted file mode 100644 index c46925a132a..00000000000 --- a/arch/riscv/dts/th1520.dtsi +++ /dev/null @@ -1,530 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Copyright (C) 2021 Alibaba Group Holding Limited. - * Copyright (C) 2023 Jisheng Zhang - */ - -#include -#include - -/ { - compatible = "thead,th1520"; - #address-cells = <2>; - #size-cells = <2>; - - cpus: cpus { - #address-cells = <1>; - #size-cells = <0>; - bootph-pre-ram; - timebase-frequency = <3000000>; - - c910_0: cpu@0 { - compatible = "thead,c910", "riscv"; - device_type = "cpu"; - riscv,isa = "rv64imafdc"; - reg = <0>; - bootph-pre-ram; - i-cache-block-size = <64>; - i-cache-size = <65536>; - i-cache-sets = <512>; - d-cache-block-size = <64>; - d-cache-size = <65536>; - d-cache-sets = <512>; - next-level-cache = <&l2_cache>; - mmu-type = "riscv,sv39"; - - cpu0_intc: interrupt-controller { - compatible = "riscv,cpu-intc"; - interrupt-controller; - #interrupt-cells = <1>; - }; - }; - - c910_1: cpu@1 { - compatible = "thead,c910", "riscv"; - device_type = "cpu"; - riscv,isa = "rv64imafdc"; - reg = <1>; - bootph-pre-ram; - i-cache-block-size = <64>; - i-cache-size = <65536>; - i-cache-sets = <512>; - d-cache-block-size = <64>; - d-cache-size = <65536>; - d-cache-sets = <512>; - next-level-cache = <&l2_cache>; - mmu-type = "riscv,sv39"; - - cpu1_intc: interrupt-controller { - compatible = "riscv,cpu-intc"; - interrupt-controller; - #interrupt-cells = <1>; - }; - }; - - c910_2: cpu@2 { - compatible = "thead,c910", "riscv"; - device_type = "cpu"; - riscv,isa = "rv64imafdc"; - reg = <2>; - bootph-pre-ram; - i-cache-block-size = <64>; - i-cache-size = <65536>; - i-cache-sets = <512>; - d-cache-block-size = <64>; - d-cache-size = <65536>; - d-cache-sets = <512>; - next-level-cache = <&l2_cache>; - mmu-type = "riscv,sv39"; - - cpu2_intc: interrupt-controller { - compatible = "riscv,cpu-intc"; - interrupt-controller; - #interrupt-cells = <1>; - }; - }; - - c910_3: cpu@3 { - compatible = "thead,c910", "riscv"; - device_type = "cpu"; - riscv,isa = "rv64imafdc"; - reg = <3>; - bootph-pre-ram; - i-cache-block-size = <64>; - i-cache-size = <65536>; - i-cache-sets = <512>; - d-cache-block-size = <64>; - d-cache-size = <65536>; - d-cache-sets = <512>; - next-level-cache = <&l2_cache>; - mmu-type = "riscv,sv39"; - - cpu3_intc: interrupt-controller { - compatible = "riscv,cpu-intc"; - interrupt-controller; - #interrupt-cells = <1>; - }; - }; - - l2_cache: l2-cache { - compatible = "cache"; - cache-block-size = <64>; - cache-level = <2>; - cache-size = <1048576>; - cache-sets = <1024>; - cache-unified; - }; - }; - - osc: oscillator { - compatible = "fixed-clock"; - clock-output-names = "osc_24m"; - #clock-cells = <0>; - }; - - osc_32k: 32k-oscillator { - compatible = "fixed-clock"; - clock-output-names = "osc_32k"; - #clock-cells = <0>; - }; - - aonsys_clk: clock-73728000 { - compatible = "fixed-clock"; - clock-frequency = <73728000>; - clock-output-names = "aonsys_clk"; - #clock-cells = <0>; - }; - - soc { - compatible = "simple-bus"; - interrupt-parent = <&plic>; - #address-cells = <2>; - #size-cells = <2>; - ranges; - - plic: interrupt-controller@ffd8000000 { - compatible = "thead,th1520-plic", "thead,c900-plic"; - reg = <0xff 0xd8000000 0x0 0x01000000>; - interrupts-extended = <&cpu0_intc 11>, <&cpu0_intc 9>, - <&cpu1_intc 11>, <&cpu1_intc 9>, - <&cpu2_intc 11>, <&cpu2_intc 9>, - <&cpu3_intc 11>, <&cpu3_intc 9>; - interrupt-controller; - #address-cells = <0>; - #interrupt-cells = <2>; - riscv,ndev = <240>; - }; - - clint: timer@ffdc000000 { - compatible = "thead,th1520-clint", "thead,c900-clint"; - reg = <0xff 0xdc000000 0x0 0x00010000>; - bootph-pre-ram; - interrupts-extended = <&cpu0_intc 3>, <&cpu0_intc 7>, - <&cpu1_intc 3>, <&cpu1_intc 7>, - <&cpu2_intc 3>, <&cpu2_intc 7>, - <&cpu3_intc 3>, <&cpu3_intc 7>; - }; - - uart0: serial@ffe7014000 { - compatible = "snps,dw-apb-uart"; - reg = <0xff 0xe7014000 0x0 0x100>; - bootph-pre-ram; - interrupts = <36 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clk CLK_UART_SCLK>, <&clk CLK_UART0_PCLK>; - clock-names = "buadclk", "apb_pclk"; - reg-shift = <2>; - reg-io-width = <4>; - status = "disabled"; - }; - - gmac1: ethernet@ffe7060000 { - compatible = "thead,th1520-gmac", "snps,dwmac-3.70a"; - reg = <0xff 0xe7060000 0x0 0x2000>, <0xff 0xec004000 0x0 0x1000>; - reg-names = "dwmac", "apb"; - interrupts = <67 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "macirq"; - clocks = <&clk CLK_GMAC_AXI>, <&clk CLK_GMAC1>; - clock-names = "stmmaceth", "pclk"; - snps,pbl = <32>; - snps,fixed-burst; - snps,multicast-filter-bins = <64>; - snps,perfect-filter-entries = <32>; - status = "disabled"; - - mdio1: mdio { - compatible = "snps,dwmac-mdio"; - #address-cells = <1>; - #size-cells = <0>; - }; - }; - - gmac0: ethernet@ffe7070000 { - compatible = "thead,th1520-gmac", "snps,dwmac-3.70a"; - reg = <0xff 0xe7070000 0x0 0x2000>, <0xff 0xec003000 0x0 0x1000>; - reg-names = "dwmac", "apb"; - interrupts = <66 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "macirq"; - clocks = <&clk CLK_GMAC_AXI>, <&clk CLK_GMAC0>; - clock-names = "stmmaceth", "pclk"; - snps,pbl = <32>; - snps,fixed-burst; - snps,multicast-filter-bins = <64>; - snps,perfect-filter-entries = <32>; - status = "disabled"; - - mdio0: mdio { - compatible = "snps,dwmac-mdio"; - #address-cells = <1>; - #size-cells = <0>; - }; - }; - - emmc: mmc@ffe7080000 { - compatible = "thead,th1520-dwcmshc"; - reg = <0xff 0xe7080000 0x0 0x10000>; - interrupts = <62 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clk CLK_EMMC_SDIO>; - clock-names = "core"; - status = "disabled"; - }; - - sdio0: mmc@ffe7090000 { - compatible = "thead,th1520-dwcmshc"; - reg = <0xff 0xe7090000 0x0 0x10000>; - interrupts = <64 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clk CLK_EMMC_SDIO>; - clock-names = "core"; - status = "disabled"; - }; - - sdio1: mmc@ffe70a0000 { - compatible = "thead,th1520-dwcmshc"; - reg = <0xff 0xe70a0000 0x0 0x10000>; - interrupts = <71 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clk CLK_EMMC_SDIO>; - clock-names = "core"; - status = "disabled"; - }; - - uart1: serial@ffe7f00000 { - compatible = "snps,dw-apb-uart"; - reg = <0xff 0xe7f00000 0x0 0x100>; - interrupts = <37 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clk CLK_UART_SCLK>, <&clk CLK_UART1_PCLK>; - clock-names = "buadclk", "apb_pclk"; - reg-shift = <2>; - reg-io-width = <4>; - status = "disabled"; - }; - - uart3: serial@ffe7f04000 { - compatible = "snps,dw-apb-uart"; - reg = <0xff 0xe7f04000 0x0 0x100>; - interrupts = <39 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clk CLK_UART_SCLK>, <&clk CLK_UART3_PCLK>; - clock-names = "buadclk", "apb_pclk"; - reg-shift = <2>; - reg-io-width = <4>; - status = "disabled"; - }; - - gpio2: gpio@ffe7f34000 { - compatible = "snps,dw-apb-gpio"; - reg = <0xff 0xe7f34000 0x0 0x1000>; - clocks = <&clk CLK_GPIO2>; - clock-names = "bus"; - #address-cells = <1>; - #size-cells = <0>; - - portc: gpio-controller@0 { - compatible = "snps,dw-apb-gpio-port"; - gpio-controller; - #gpio-cells = <2>; - ngpios = <32>; - reg = <0>; - interrupt-controller; - #interrupt-cells = <2>; - interrupts = <58 IRQ_TYPE_LEVEL_HIGH>; - }; - }; - - gpio3: gpio@ffe7f38000 { - compatible = "snps,dw-apb-gpio"; - reg = <0xff 0xe7f38000 0x0 0x1000>; - clocks = <&clk CLK_GPIO3>; - clock-names = "bus"; - #address-cells = <1>; - #size-cells = <0>; - - portd: gpio-controller@0 { - compatible = "snps,dw-apb-gpio-port"; - gpio-controller; - #gpio-cells = <2>; - ngpios = <32>; - reg = <0>; - interrupt-controller; - #interrupt-cells = <2>; - interrupts = <59 IRQ_TYPE_LEVEL_HIGH>; - }; - }; - - padctrl1_apsys: pinctrl@ffe7f3c000 { - compatible = "thead,th1520-pinctrl"; - reg = <0xff 0xe7f3c000 0x0 0x1000>; - clocks = <&clk CLK_PADCTRL1>; - thead,pad-group = <2>; - }; - - gpio0: gpio@ffec005000 { - compatible = "snps,dw-apb-gpio"; - reg = <0xff 0xec005000 0x0 0x1000>; - clocks = <&clk CLK_GPIO0>; - clock-names = "bus"; - #address-cells = <1>; - #size-cells = <0>; - - porta: gpio-controller@0 { - compatible = "snps,dw-apb-gpio-port"; - gpio-controller; - #gpio-cells = <2>; - ngpios = <32>; - reg = <0>; - interrupt-controller; - #interrupt-cells = <2>; - interrupts = <56 IRQ_TYPE_LEVEL_HIGH>; - }; - }; - - gpio1: gpio@ffec006000 { - compatible = "snps,dw-apb-gpio"; - reg = <0xff 0xec006000 0x0 0x1000>; - clocks = <&clk CLK_GPIO1>; - clock-names = "bus"; - #address-cells = <1>; - #size-cells = <0>; - - portb: gpio-controller@0 { - compatible = "snps,dw-apb-gpio-port"; - gpio-controller; - #gpio-cells = <2>; - ngpios = <32>; - reg = <0>; - interrupt-controller; - #interrupt-cells = <2>; - interrupts = <57 IRQ_TYPE_LEVEL_HIGH>; - }; - }; - - padctrl0_apsys: pinctrl@ffec007000 { - compatible = "thead,th1520-pinctrl"; - reg = <0xff 0xec007000 0x0 0x1000>; - clocks = <&clk CLK_PADCTRL0>; - thead,pad-group = <3>; - }; - - uart2: serial@ffec010000 { - compatible = "snps,dw-apb-uart"; - reg = <0xff 0xec010000 0x0 0x4000>; - interrupts = <38 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clk CLK_UART_SCLK>, <&clk CLK_UART2_PCLK>; - clock-names = "buadclk", "apb_pclk"; - reg-shift = <2>; - reg-io-width = <4>; - status = "disabled"; - }; - - clk: clock-controller@ffef010000 { - compatible = "thead,th1520-clk-ap"; - reg = <0xff 0xef010000 0x0 0x1000>; - clocks = <&osc>; - #clock-cells = <1>; - }; - - timer0: timer@ffefc32000 { - compatible = "snps,dw-apb-timer"; - reg = <0xff 0xefc32000 0x0 0x14>; - clocks = <&clk CLK_PERI_APB_PCLK>; - clock-names = "timer"; - interrupts = <16 IRQ_TYPE_LEVEL_HIGH>; - status = "disabled"; - }; - - timer1: timer@ffefc32014 { - compatible = "snps,dw-apb-timer"; - reg = <0xff 0xefc32014 0x0 0x14>; - clocks = <&clk CLK_PERI_APB_PCLK>; - clock-names = "timer"; - interrupts = <17 IRQ_TYPE_LEVEL_HIGH>; - status = "disabled"; - }; - - timer2: timer@ffefc32028 { - compatible = "snps,dw-apb-timer"; - reg = <0xff 0xefc32028 0x0 0x14>; - clocks = <&clk CLK_PERI_APB_PCLK>; - clock-names = "timer"; - interrupts = <18 IRQ_TYPE_LEVEL_HIGH>; - status = "disabled"; - }; - - timer3: timer@ffefc3203c { - compatible = "snps,dw-apb-timer"; - reg = <0xff 0xefc3203c 0x0 0x14>; - clocks = <&clk CLK_PERI_APB_PCLK>; - clock-names = "timer"; - interrupts = <19 IRQ_TYPE_LEVEL_HIGH>; - status = "disabled"; - }; - - uart4: serial@fff7f08000 { - compatible = "snps,dw-apb-uart"; - reg = <0xff 0xf7f08000 0x0 0x4000>; - interrupts = <40 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clk CLK_UART_SCLK>, <&clk CLK_UART4_PCLK>; - clock-names = "buadclk", "apb_pclk"; - reg-shift = <2>; - reg-io-width = <4>; - status = "disabled"; - }; - - uart5: serial@fff7f0c000 { - compatible = "snps,dw-apb-uart"; - reg = <0xff 0xf7f0c000 0x0 0x4000>; - interrupts = <41 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clk CLK_UART_SCLK>, <&clk CLK_UART5_PCLK>; - clock-names = "buadclk", "apb_pclk"; - reg-shift = <2>; - reg-io-width = <4>; - status = "disabled"; - }; - - ddrc: ddrc@fffd000000 { - compatible = "thead,th1520-ddrc"; - reg = <0xff 0xfd000000 0x0 0x1000000>, - <0xff 0xfe000000 0x0 0x1000000>, - <0xff 0xff000000 0x0 0x4000>, - <0xff 0xff005000 0x0 0x1000>; - reg-names = "phy-0", "phy-1", "ctrl", "sys"; - bootph-pre-ram; - }; - - timer4: timer@ffffc33000 { - compatible = "snps,dw-apb-timer"; - reg = <0xff 0xffc33000 0x0 0x14>; - clocks = <&clk CLK_PERI_APB_PCLK>; - clock-names = "timer"; - interrupts = <20 IRQ_TYPE_LEVEL_HIGH>; - status = "disabled"; - }; - - timer5: timer@ffffc33014 { - compatible = "snps,dw-apb-timer"; - reg = <0xff 0xffc33014 0x0 0x14>; - clocks = <&clk CLK_PERI_APB_PCLK>; - clock-names = "timer"; - interrupts = <21 IRQ_TYPE_LEVEL_HIGH>; - status = "disabled"; - }; - - timer6: timer@ffffc33028 { - compatible = "snps,dw-apb-timer"; - reg = <0xff 0xffc33028 0x0 0x14>; - clocks = <&clk CLK_PERI_APB_PCLK>; - clock-names = "timer"; - interrupts = <22 IRQ_TYPE_LEVEL_HIGH>; - status = "disabled"; - }; - - timer7: timer@ffffc3303c { - compatible = "snps,dw-apb-timer"; - reg = <0xff 0xffc3303c 0x0 0x14>; - clocks = <&clk CLK_PERI_APB_PCLK>; - clock-names = "timer"; - interrupts = <23 IRQ_TYPE_LEVEL_HIGH>; - status = "disabled"; - }; - - ao_gpio0: gpio@fffff41000 { - compatible = "snps,dw-apb-gpio"; - reg = <0xff 0xfff41000 0x0 0x1000>; - #address-cells = <1>; - #size-cells = <0>; - - porte: gpio-controller@0 { - compatible = "snps,dw-apb-gpio-port"; - gpio-controller; - #gpio-cells = <2>; - ngpios = <32>; - reg = <0>; - interrupt-controller; - #interrupt-cells = <2>; - interrupts = <76 IRQ_TYPE_LEVEL_HIGH>; - }; - }; - - padctrl_aosys: pinctrl@fffff4a000 { - compatible = "thead,th1520-pinctrl"; - reg = <0xff 0xfff4a000 0x0 0x2000>; - clocks = <&aonsys_clk>; - thead,pad-group = <1>; - }; - - ao_gpio1: gpio@fffff52000 { - compatible = "snps,dw-apb-gpio"; - reg = <0xff 0xfff52000 0x0 0x1000>; - #address-cells = <1>; - #size-cells = <0>; - - portf: gpio-controller@0 { - compatible = "snps,dw-apb-gpio-port"; - gpio-controller; - #gpio-cells = <2>; - ngpios = <32>; - reg = <0>; - interrupt-controller; - #interrupt-cells = <2>; - interrupts = <55 IRQ_TYPE_LEVEL_HIGH>; - }; - }; - }; -}; diff --git a/configs/th1520_lpi4a_defconfig b/configs/th1520_lpi4a_defconfig index 85d7a638b86..919f866d0bf 100644 --- a/configs/th1520_lpi4a_defconfig +++ b/configs/th1520_lpi4a_defconfig @@ -6,7 +6,7 @@ CONFIG_NR_DRAM_BANKS=1 CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x80200000 CONFIG_DM_GPIO=y -CONFIG_DEFAULT_DEVICE_TREE="th1520-lichee-pi-4a" +CONFIG_DEFAULT_DEVICE_TREE="thead/th1520-lichee-pi-4a" CONFIG_SPL_STACK=0xffe0170000 CONFIG_SPL_BSS_START_ADDR=0xffe0160000 CONFIG_SPL_BSS_MAX_SIZE=0x10000 -- cgit v1.2.3 From 409c73ef6368b07d4dbdf8391a0b9c7682dcf4b4 Mon Sep 17 00:00:00 2001 From: Randolph Lin Date: Thu, 21 Aug 2025 19:31:22 +0800 Subject: include: configs: andes: Remove fdt_high env variable Remove the fdt_high environment variable, as a value of all ones indicates using the FDT in place. This setting is incorrect for the current board. Signed-off-by: Randolph Lin Reviewed-by: Leo Yu-Chi Liang --- include/configs/voyager.h | 1 - 1 file changed, 1 deletion(-) diff --git a/include/configs/voyager.h b/include/configs/voyager.h index f6630b07ec9..0e5fed99dd0 100644 --- a/include/configs/voyager.h +++ b/include/configs/voyager.h @@ -26,7 +26,6 @@ #include #define CFG_EXTRA_ENV_SETTINGS \ - "fdt_high=0xffffffffffffffff\0" \ "initrd_high=0xffffffffffffffff\0" \ "kernel_addr_r=0x400600000\0" \ "kernel_comp_addr_r=0x404600000\0" \ -- cgit v1.2.3 From 686b48af6d6f4e33f10dc707e9a8c8213b682348 Mon Sep 17 00:00:00 2001 From: Heinrich Schuchardt Date: Thu, 28 Aug 2025 15:03:35 +0200 Subject: starfive: avoid NULL dereference in fdt_check_header() If the u-boot.itb read from SD-card is invalid, fdt_check_header() may be called with a NULL pointer. This was observed on an StarFive VisionFive Lite when trying to revover the board via UART. Add a missing check in the starfive board code. Signed-off-by: Heinrich Schuchardt Reviewed-by: E Shattow --- board/starfive/visionfive2/spl.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/board/starfive/visionfive2/spl.c b/board/starfive/visionfive2/spl.c index 3dfa931b655..fe14b44ce28 100644 --- a/board/starfive/visionfive2/spl.c +++ b/board/starfive/visionfive2/spl.c @@ -23,7 +23,8 @@ DECLARE_GLOBAL_DATA_PTR; void spl_perform_fixups(struct spl_image_info *spl_image) { /* Update the memory size which read from eeprom or DT */ - fdt_fixup_memory(spl_image->fdt_addr, 0x40000000, gd->ram_size); + if (spl_image->fdt_addr) + fdt_fixup_memory(spl_image->fdt_addr, 0x40000000, gd->ram_size); } static void jh7110_jtag_init(void) -- cgit v1.2.3 From cb1a70a856a53a435c7bb75d211ec51fa2855011 Mon Sep 17 00:00:00 2001 From: Hal Feng Date: Mon, 1 Sep 2025 16:24:18 +0800 Subject: pcie: starfive: Remove the redundant print of probe success The dev_err() is used incorrectly and we don't need the driver to state probe success. Signed-off-by: Hal Feng Reviewed-by: Leo Yu-Chi Liang --- drivers/pci/pcie_starfive_jh7110.c | 2 -- 1 file changed, 2 deletions(-) diff --git a/drivers/pci/pcie_starfive_jh7110.c b/drivers/pci/pcie_starfive_jh7110.c index 51aca7359ff..0908ae16b67 100644 --- a/drivers/pci/pcie_starfive_jh7110.c +++ b/drivers/pci/pcie_starfive_jh7110.c @@ -292,8 +292,6 @@ static int starfive_pcie_probe(struct udevice *dev) if (ret) return ret; - dev_err(dev, "Starfive PCIe bus probed.\n"); - return 0; } -- cgit v1.2.3 From fde7702c9b5a440fe86b4a8f35485f1920744ba7 Mon Sep 17 00:00:00 2001 From: Yao Zi Date: Tue, 2 Sep 2025 08:19:30 +0000 Subject: riscv: Add Kconfig options to distinguish Zaamo and Zalrsc Ratified on Apr. 2024, the original RISC-V "A" extension is now split into two separate extensions, "Zaamo" for atomic operations and "Zalrsc" for load-reserved/store-conditional instructions. For now, we've already seen real-world designs implement the Zalrsc extension only[2]. As U-Boot mainly runs with only one HART, we could easily support these designs by not using AMO instructions in the hard-written assembly if necessary, for which this patch introduces two new Kconfig options to indicate the availability of "Zaamo" and "Zalrsc". Note that even with this patch, "A" extension is specified in the ISA string passed to the compiler as long as one of "Zaamo" or "Zalrsc" is available, since they're only recognized with a quite recent version of GCC/Clang. The compiler usually doesn't automatically generate atomic instructions unless the source explicitly instructs it to do so, thus this should be safe. Link: https://github.com/riscv/riscv-zaamo-zalrsc/commit/d94c64c63e9120d56bdeb540caf2e5dae60a8126 # [1] Link: https://lore.kernel.org/u-boot/20250729162035.209849-9-uros.stajic@htecgroup.com/ # [2] Signed-off-by: Yao Zi Reviewed-by: Leo Yu-Chi Liang --- arch/riscv/Kconfig | 17 +++++++++++++++++ arch/riscv/Makefile | 7 ++++++- 2 files changed, 23 insertions(+), 1 deletion(-) diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig index 04eb0e6f23c..f0d2c904349 100644 --- a/arch/riscv/Kconfig +++ b/arch/riscv/Kconfig @@ -343,10 +343,27 @@ endmenu config RISCV_ISA_A bool "Standard extension for Atomic Instructions" + depends on RISCV_ISA_ZAAMO && RISCV_ISA_ZALRSC default y help Adds "A" to the ISA string passed to the compiler. +config RISCV_ISA_ZAAMO + bool "Standard extension for Atomic Memory Operations" + default y + help + Indicates the platform supports Zaamo extension for atomic memory + operations. Hand-written Assembly routines won't use AMO + instructions if set to n. + +config RISCV_ISA_ZALRSC + bool "Standard extension for LR/SC instructions" + default y + help + Indicates the platform supports Zalrsc extension for load-reserved + and store-conditional isntructions. Hand-written assembly routines + won't use LR/SC instructions if set to n. + config RISCV_ISA_ZICBOM bool "Zicbom support" depends on !SYS_DISABLE_DCACHE_OPS diff --git a/arch/riscv/Makefile b/arch/riscv/Makefile index 6f80f4a7108..fdda6da1df3 100644 --- a/arch/riscv/Makefile +++ b/arch/riscv/Makefile @@ -11,7 +11,12 @@ ifeq ($(CONFIG_ARCH_RV32I),y) ARCH_BASE = rv32im ABI_BASE = ilp32 endif -ifeq ($(CONFIG_RISCV_ISA_A),y) +# GCC starts to recognize "Zaamo" and "Zalrsc" from version 15, which is quite +# recent. We don't bother checking the exact compiler version, but pass "A" +# extension for -march as long as one of "Zaamo" or "Zalrsc" is available. +ifeq ($(findstring y,$(CONFIG_RISCV_ISA_A) \ + $(CONFIG_RISCV_ISA_ZAAMO) \ + $(CONFIG_RISCV_ISA_ZALRSC)),y) ARCH_A = a endif ifeq ($(CONFIG_RISCV_ISA_F),y) -- cgit v1.2.3 From 06b22f38af96ba9d347f2f70bc5ab8d41dd79312 Mon Sep 17 00:00:00 2001 From: Yao Zi Date: Tue, 2 Sep 2025 08:19:31 +0000 Subject: configs: ibex-ast2700: Explicitly disable Zaamo and Zalrsc extension This board supports neither Zaamo nor Zalrsc extension, thus we want to build it without "a" specified in the ISA string passed to compiler in case of misused A-extension instructions. With RISCV_ISA_ZAAMO and RISCV_ISA_ZALRSC Kconfig options introduced, we must explicitly disable both of them to achieve this. Signed-off-by: Yao Zi Reviewed-by: Leo Yu-Chi Liang --- configs/ibex-ast2700_defconfig | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/configs/ibex-ast2700_defconfig b/configs/ibex-ast2700_defconfig index 8e8259f291d..088eec1ec70 100644 --- a/configs/ibex-ast2700_defconfig +++ b/configs/ibex-ast2700_defconfig @@ -22,7 +22,8 @@ CONFIG_SYS_MEM_TOP_HIDE=0x10000000 CONFIG_BUILD_TARGET="" CONFIG_TARGET_ASPEED_AST2700_IBEX=y # CONFIG_RISCV_ISA_F is not set -# CONFIG_RISCV_ISA_A is not set +# CONFIG_RISCV_ISA_ZAAMO is not set +# CONFIG_RISCV_ISA_ZALRSC is not set # CONFIG_SPL_SMP is not set CONFIG_XIP=y CONFIG_SPL_XIP=y -- cgit v1.2.3 From a681cfecb4346107212f377e2075f6eb1bdc6a2b Mon Sep 17 00:00:00 2001 From: Yao Zi Date: Tue, 2 Sep 2025 08:19:32 +0000 Subject: riscv: Add a Zalrsc-only alternative for synchronization in start.S Add an alternative implementation that use Zalrsc extension only for HART lottery and SMP locking to support SMP on cores without "Zaamo" extension available. The Zaamo implementation is still prioritized if both of them are available, since it takes fewer instructions. Signed-off-by: Yao Zi Reviewed-by: Leo Yu-Chi Liang --- arch/riscv/cpu/start.S | 26 +++++++++++++++++++++++++- 1 file changed, 25 insertions(+), 1 deletion(-) diff --git a/arch/riscv/cpu/start.S b/arch/riscv/cpu/start.S index 7bafdfd390a..6324ff585d4 100644 --- a/arch/riscv/cpu/start.S +++ b/arch/riscv/cpu/start.S @@ -151,8 +151,15 @@ call_harts_early_init: */ la t0, hart_lottery li t1, 1 +#if CONFIG_IS_ENABLED(RISCV_ISA_ZAAMO) amoswap.w s2, t1, 0(t0) bnez s2, wait_for_gd_init +#else + lr.w s2, (t0) + bnez s2, wait_for_gd_init + sc.w s2, t1, (t0) + bnez s2, wait_for_gd_init +#endif #else /* * FIXME: gp is set before it is initialized. If an XIP U-Boot ever @@ -177,7 +184,12 @@ call_harts_early_init: #if !CONFIG_IS_ENABLED(XIP) #ifdef CONFIG_AVAILABLE_HARTS la t0, available_harts_lock +#if CONFIG_IS_ENABLED(RISCV_ISA_ZAAMO) amoswap.w.rl zero, zero, 0(t0) +#else + fence rw, w + sw zero, 0(t0) +#endif #endif wait_for_gd_init: @@ -190,7 +202,14 @@ wait_for_gd_init: #ifdef CONFIG_AVAILABLE_HARTS la t0, available_harts_lock li t1, 1 -1: amoswap.w.aq t1, t1, 0(t0) +1: +#if CONFIG_IS_ENABLED(RISCV_ISA_ZAAMO) + amoswap.w.aq t1, t1, 0(t0) +#else + lr.w.aq t1, 0(t0) + bnez t1, 1b + sc.w.rl t1, t1, 0(t0) +#endif bnez t1, 1b /* register available harts in the available_harts mask */ @@ -200,7 +219,12 @@ wait_for_gd_init: or t2, t2, t1 SREG t2, GD_AVAILABLE_HARTS(gp) +#if CONFIG_IS_ENABLED(RISCV_ISA_ZAAMO) amoswap.w.rl zero, zero, 0(t0) +#else + fence rw, w + sw zero, 0(t0) +#endif #endif /* -- cgit v1.2.3 From d141a41feb005a9f6a830006f1a4b66d1a3a3cd2 Mon Sep 17 00:00:00 2001 From: Jamie Gibbons Date: Tue, 2 Sep 2025 11:10:58 +0100 Subject: board: microchip: icicle: rename all icicle files to generic Make all Icicle Kit files generic. This supports the addition of upcoming support for other MPFS boards. Signed-off-by: Jamie Gibbons Reviewed-by: Leo Yu-Chi Liang Reviewed-by: Leo Yu-Chi Liang --- arch/riscv/Kconfig | 6 +- board/microchip/mpfs_generic/Kconfig | 67 +++++++++ board/microchip/mpfs_generic/MAINTAINERS | 7 + board/microchip/mpfs_generic/Makefile | 7 + board/microchip/mpfs_generic/mpfs_generic.c | 204 ++++++++++++++++++++++++++++ board/microchip/mpfs_icicle/Kconfig | 67 --------- board/microchip/mpfs_icicle/MAINTAINERS | 7 - board/microchip/mpfs_icicle/Makefile | 7 - board/microchip/mpfs_icicle/mpfs_icicle.c | 204 ---------------------------- configs/microchip_mpfs_generic_defconfig | 29 ++++ configs/microchip_mpfs_icicle_defconfig | 29 ---- include/configs/microchip_mpfs_generic.h | 32 +++++ include/configs/microchip_mpfs_icicle.h | 32 ----- 13 files changed, 349 insertions(+), 349 deletions(-) create mode 100644 board/microchip/mpfs_generic/Kconfig create mode 100644 board/microchip/mpfs_generic/MAINTAINERS create mode 100644 board/microchip/mpfs_generic/Makefile create mode 100644 board/microchip/mpfs_generic/mpfs_generic.c delete mode 100644 board/microchip/mpfs_icicle/Kconfig delete mode 100644 board/microchip/mpfs_icicle/MAINTAINERS delete mode 100644 board/microchip/mpfs_icicle/Makefile delete mode 100644 board/microchip/mpfs_icicle/mpfs_icicle.c create mode 100644 configs/microchip_mpfs_generic_defconfig delete mode 100644 configs/microchip_mpfs_icicle_defconfig create mode 100644 include/configs/microchip_mpfs_generic.h delete mode 100644 include/configs/microchip_mpfs_icicle.h diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig index f0d2c904349..265b5320777 100644 --- a/arch/riscv/Kconfig +++ b/arch/riscv/Kconfig @@ -23,8 +23,8 @@ config TARGET_K230_CANMV config TARGET_LICHEERV_NANO bool "Support LicheeRV Nano Board" -config TARGET_MICROCHIP_ICICLE - bool "Support Microchip PolarFire-SoC Icicle Board" +config TARGET_MICROCHIP_GENERIC + bool "Support Microchip PolarFire-SoC Boards" config TARGET_MILKV_DUO bool "Support Milk-v Duo Board" @@ -108,7 +108,7 @@ source "board/andestech/voyager/Kconfig" source "board/aspeed/ibex_ast2700/Kconfig" source "board/canaan/k230_canmv/Kconfig" source "board/emulation/qemu-riscv/Kconfig" -source "board/microchip/mpfs_icicle/Kconfig" +source "board/microchip/mpfs_generic/Kconfig" source "board/openpiton/riscv64/Kconfig" source "board/sifive/unleashed/Kconfig" source "board/sifive/unmatched/Kconfig" diff --git a/board/microchip/mpfs_generic/Kconfig b/board/microchip/mpfs_generic/Kconfig new file mode 100644 index 00000000000..8dcf55a0311 --- /dev/null +++ b/board/microchip/mpfs_generic/Kconfig @@ -0,0 +1,67 @@ +if TARGET_MICROCHIP_GENERIC + +config SYS_BOARD + default "mpfs_generic" + +config SYS_VENDOR + default "microchip" + +config SYS_CPU + default "generic" + +config SYS_CONFIG_NAME + default "microchip_mpfs_generic" + +config TEXT_BASE + default 0x80000000 if !RISCV_SMODE + default 0x80200000 if RISCV_SMODE + +config BOARD_SPECIFIC_OPTIONS # dummy + def_bool y + select GENERIC_RISCV + select BOARD_EARLY_INIT_F + select BOARD_LATE_INIT + imply SMP + imply CLK_CCF + imply CLK_MPFS + imply REGMAP + imply SYSCON + imply SYS_NS16550 + imply CMD_DHCP + imply CMD_EXT2 + imply CMD_EXT4 + imply CMD_FAT + imply CMD_FS_GENERIC + imply CMD_NET + imply CMD_PING + imply CMD_MMC + imply DOS_PARTITION + imply EFI_PARTITION + imply IP_DYN + imply ISO_PARTITION + imply MACB + imply MII + imply PHY_LIB + imply PHY_VITESSE + imply MMC + imply MMC_WRITE + imply MMC_SDHCI + imply MMC_SDHCI_CADENCE + imply MMC_SDHCI_ADMA + imply MMC_HS200_SUPPORT + imply CMD_I2C + imply DM_I2C + imply SYS_I2C_MICROCHIP + imply MTD + imply SPI + imply DM_SPI + imply MICROCHIP_COREQSPI + imply MTD_SPI_NAND + imply CMD_MTD + imply CMD_MTDPARTS + imply DM_MAILBOX + imply MPFS_MBOX + imply MISC + imply MPFS_SYSCONTROLLER + +endif diff --git a/board/microchip/mpfs_generic/MAINTAINERS b/board/microchip/mpfs_generic/MAINTAINERS new file mode 100644 index 00000000000..3de99144c41 --- /dev/null +++ b/board/microchip/mpfs_generic/MAINTAINERS @@ -0,0 +1,7 @@ +Microchip MPFS Generic +M: Conor Dooley +M: Jamie Gibbons +S: Maintained +F: board/microchip/mpfs_generic/ +F: include/configs/microchip_mpfs_generic.h +F: configs/microchip_mpfs_generic_defconfig diff --git a/board/microchip/mpfs_generic/Makefile b/board/microchip/mpfs_generic/Makefile new file mode 100644 index 00000000000..dfe4b2634e6 --- /dev/null +++ b/board/microchip/mpfs_generic/Makefile @@ -0,0 +1,7 @@ +# SPDX-License-Identifier: GPL-2.0+ +# +# Copyright (C) 2019 Microchip Technology Inc. +# Padmarao Begari +# + +obj-y += mpfs_generic.o diff --git a/board/microchip/mpfs_generic/mpfs_generic.c b/board/microchip/mpfs_generic/mpfs_generic.c new file mode 100644 index 00000000000..739a9b6cd76 --- /dev/null +++ b/board/microchip/mpfs_generic/mpfs_generic.c @@ -0,0 +1,204 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2019 Microchip Technology Inc. + * Padmarao Begari + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +#define MPFS_SYSREG_SOFT_RESET ((unsigned int *)0x20002088) +#define PERIPH_RESET_VALUE 0x1e8u + +static unsigned char mac_addr[6]; + +#if defined(CONFIG_MULTI_DTB_FIT) +int board_fit_config_name_match(const char *name) +{ + const void *fdt; + int list_len; + + /* + * If there's not a HSS provided dtb, there's no point re-selecting + * since we'd just end up re-selecting the same dtb again. + */ + if (!gd->arch.firmware_fdt_addr) + return -EINVAL; + + fdt = (void *)gd->arch.firmware_fdt_addr; + + list_len = fdt_stringlist_count(fdt, 0, "compatible"); + if (list_len < 1) + return -EINVAL; + + for (int i = 0; i < list_len; i++) { + int len, match; + const char *compat; + char copy[64]; + char *devendored; + + compat = fdt_stringlist_get(fdt, 0, "compatible", i, &len); + if (!compat) + return -EINVAL; + + /* + * The naming scheme for compatibles doesn't produce anything + * close to this long. + */ + if (len >= 64) + return -EINVAL; + + strncpy(copy, compat, 64); + strtok(copy, ","); + + devendored = strtok(NULL, ","); + if (!devendored) + return -EINVAL; + + match = strcmp(devendored, name); + if (!match) + return 0; + } + + return -EINVAL; +} +#endif + +int board_fdt_blob_setup(void **fdtp) +{ + fdtp = (void *)_end; + + /* + * The devicetree provided by the previous stage is very minimal due to + * severe space constraints. The firmware performs no fixups etc. + * U-Boot, if providing a devicetree, almost certainly has a better + * more complete one than the firmware so that provided by the firmware + * is ignored for OF_SEPARATE. + */ + if (IS_ENABLED(CONFIG_OF_BOARD) && !IS_ENABLED(CONFIG_MULTI_DTB_FIT)) { + if (gd->arch.firmware_fdt_addr) + fdtp = (void *)(uintptr_t)gd->arch.firmware_fdt_addr; + } + + return 0; +} + +int board_init(void) +{ + /* For now nothing to do here. */ + + return 0; +} + +int board_early_init_f(void) +{ + unsigned int val; + + /* Reset uart, mmc peripheral */ + val = readl(MPFS_SYSREG_SOFT_RESET); + val = (val & ~(PERIPH_RESET_VALUE)); + writel(val, MPFS_SYSREG_SOFT_RESET); + + return 0; +} + +int board_late_init(void) +{ + u32 ret; + int node; + u8 device_serial_number[16] = {0}; + void *blob = (void *)gd->fdt_blob; + struct udevice *dev; + struct mpfs_sys_serv *sys_serv_priv; + + ret = uclass_get_device_by_name(UCLASS_MISC, "syscontroller", &dev); + if (ret) { + debug("%s: system controller setup failed\n", __func__); + return ret; + } + + sys_serv_priv = kzalloc(sizeof(*sys_serv_priv), GFP_KERNEL); + if (!sys_serv_priv) + return -ENOMEM; + + sys_serv_priv->dev = dev; + + sys_serv_priv->sys_controller = mpfs_syscontroller_get(dev); + ret = IS_ERR(sys_serv_priv->sys_controller); + if (ret) { + debug("%s: Failed to register system controller sub device ret=%d\n", __func__, ret); + return -ENODEV; + } + + ret = mpfs_syscontroller_read_sernum(sys_serv_priv, device_serial_number); + if (ret) { + printf("Cannot read device serial number\n"); + return -EINVAL; + } + + /* Update MAC address with device serial number */ + mac_addr[0] = 0x00; + mac_addr[1] = 0x04; + mac_addr[2] = 0xA3; + mac_addr[3] = device_serial_number[2]; + mac_addr[4] = device_serial_number[1]; + mac_addr[5] = device_serial_number[0]; + + node = fdt_path_offset(blob, "/soc/ethernet@20112000"); + if (node >= 0) { + ret = fdt_setprop(blob, node, "local-mac-address", mac_addr, 6); + if (ret) { + printf("Error setting local-mac-address property for ethernet@20112000\n"); + return -ENODEV; + } + } + + mac_addr[5] = device_serial_number[0] + 1; + + node = fdt_path_offset(blob, "/soc/ethernet@20110000"); + if (node >= 0) { + ret = fdt_setprop(blob, node, "local-mac-address", mac_addr, 6); + if (ret) { + printf("Error setting local-mac-address property for ethernet@20110000\n"); + return -ENODEV; + } + } + + return 0; +} + +int ft_board_setup(void *blob, struct bd_info *bd) +{ + u32 ret; + int node; + + node = fdt_path_offset(blob, "/soc/ethernet@20110000"); + if (node >= 0) { + ret = fdt_setprop(blob, node, "local-mac-address", mac_addr, 6); + if (ret) { + printf("Error setting local-mac-address property for ethernet@20110000\n"); + return -ENODEV; + } + } + + mac_addr[5] -= 1; + + node = fdt_path_offset(blob, "/soc/ethernet@20112000"); + if (node >= 0) { + ret = fdt_setprop(blob, node, "local-mac-address", mac_addr, 6); + if (ret) { + printf("Error setting local-mac-address property for ethernet@20112000\n"); + return -ENODEV; + } + } + + return 0; +} diff --git a/board/microchip/mpfs_icicle/Kconfig b/board/microchip/mpfs_icicle/Kconfig deleted file mode 100644 index 760dffc488b..00000000000 --- a/board/microchip/mpfs_icicle/Kconfig +++ /dev/null @@ -1,67 +0,0 @@ -if TARGET_MICROCHIP_ICICLE - -config SYS_BOARD - default "mpfs_icicle" - -config SYS_VENDOR - default "microchip" - -config SYS_CPU - default "generic" - -config SYS_CONFIG_NAME - default "microchip_mpfs_icicle" - -config TEXT_BASE - default 0x80000000 if !RISCV_SMODE - default 0x80200000 if RISCV_SMODE - -config BOARD_SPECIFIC_OPTIONS # dummy - def_bool y - select GENERIC_RISCV - select BOARD_EARLY_INIT_F - select BOARD_LATE_INIT - imply SMP - imply CLK_CCF - imply CLK_MPFS - imply REGMAP - imply SYSCON - imply SYS_NS16550 - imply CMD_DHCP - imply CMD_EXT2 - imply CMD_EXT4 - imply CMD_FAT - imply CMD_FS_GENERIC - imply CMD_NET - imply CMD_PING - imply CMD_MMC - imply DOS_PARTITION - imply EFI_PARTITION - imply IP_DYN - imply ISO_PARTITION - imply MACB - imply MII - imply PHY_LIB - imply PHY_VITESSE - imply MMC - imply MMC_WRITE - imply MMC_SDHCI - imply MMC_SDHCI_CADENCE - imply MMC_SDHCI_ADMA - imply MMC_HS200_SUPPORT - imply CMD_I2C - imply DM_I2C - imply SYS_I2C_MICROCHIP - imply MTD - imply SPI - imply DM_SPI - imply MICROCHIP_COREQSPI - imply MTD_SPI_NAND - imply CMD_MTD - imply CMD_MTDPARTS - imply DM_MAILBOX - imply MPFS_MBOX - imply MISC - imply MPFS_SYSCONTROLLER - -endif diff --git a/board/microchip/mpfs_icicle/MAINTAINERS b/board/microchip/mpfs_icicle/MAINTAINERS deleted file mode 100644 index d092b5a8111..00000000000 --- a/board/microchip/mpfs_icicle/MAINTAINERS +++ /dev/null @@ -1,7 +0,0 @@ -Microchip MPFS icicle -M: Conor Dooley -M: Cyril Jean -S: Maintained -F: board/microchip/mpfs_icicle/ -F: include/configs/microchip_mpfs_icicle.h -F: configs/microchip_mpfs_icicle_defconfig diff --git a/board/microchip/mpfs_icicle/Makefile b/board/microchip/mpfs_icicle/Makefile deleted file mode 100644 index 72b0410dda8..00000000000 --- a/board/microchip/mpfs_icicle/Makefile +++ /dev/null @@ -1,7 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0+ -# -# Copyright (C) 2019 Microchip Technology Inc. -# Padmarao Begari -# - -obj-y += mpfs_icicle.o diff --git a/board/microchip/mpfs_icicle/mpfs_icicle.c b/board/microchip/mpfs_icicle/mpfs_icicle.c deleted file mode 100644 index 739a9b6cd76..00000000000 --- a/board/microchip/mpfs_icicle/mpfs_icicle.c +++ /dev/null @@ -1,204 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright (C) 2019 Microchip Technology Inc. - * Padmarao Begari - */ - -#include -#include -#include -#include -#include -#include -#include -#include - -DECLARE_GLOBAL_DATA_PTR; - -#define MPFS_SYSREG_SOFT_RESET ((unsigned int *)0x20002088) -#define PERIPH_RESET_VALUE 0x1e8u - -static unsigned char mac_addr[6]; - -#if defined(CONFIG_MULTI_DTB_FIT) -int board_fit_config_name_match(const char *name) -{ - const void *fdt; - int list_len; - - /* - * If there's not a HSS provided dtb, there's no point re-selecting - * since we'd just end up re-selecting the same dtb again. - */ - if (!gd->arch.firmware_fdt_addr) - return -EINVAL; - - fdt = (void *)gd->arch.firmware_fdt_addr; - - list_len = fdt_stringlist_count(fdt, 0, "compatible"); - if (list_len < 1) - return -EINVAL; - - for (int i = 0; i < list_len; i++) { - int len, match; - const char *compat; - char copy[64]; - char *devendored; - - compat = fdt_stringlist_get(fdt, 0, "compatible", i, &len); - if (!compat) - return -EINVAL; - - /* - * The naming scheme for compatibles doesn't produce anything - * close to this long. - */ - if (len >= 64) - return -EINVAL; - - strncpy(copy, compat, 64); - strtok(copy, ","); - - devendored = strtok(NULL, ","); - if (!devendored) - return -EINVAL; - - match = strcmp(devendored, name); - if (!match) - return 0; - } - - return -EINVAL; -} -#endif - -int board_fdt_blob_setup(void **fdtp) -{ - fdtp = (void *)_end; - - /* - * The devicetree provided by the previous stage is very minimal due to - * severe space constraints. The firmware performs no fixups etc. - * U-Boot, if providing a devicetree, almost certainly has a better - * more complete one than the firmware so that provided by the firmware - * is ignored for OF_SEPARATE. - */ - if (IS_ENABLED(CONFIG_OF_BOARD) && !IS_ENABLED(CONFIG_MULTI_DTB_FIT)) { - if (gd->arch.firmware_fdt_addr) - fdtp = (void *)(uintptr_t)gd->arch.firmware_fdt_addr; - } - - return 0; -} - -int board_init(void) -{ - /* For now nothing to do here. */ - - return 0; -} - -int board_early_init_f(void) -{ - unsigned int val; - - /* Reset uart, mmc peripheral */ - val = readl(MPFS_SYSREG_SOFT_RESET); - val = (val & ~(PERIPH_RESET_VALUE)); - writel(val, MPFS_SYSREG_SOFT_RESET); - - return 0; -} - -int board_late_init(void) -{ - u32 ret; - int node; - u8 device_serial_number[16] = {0}; - void *blob = (void *)gd->fdt_blob; - struct udevice *dev; - struct mpfs_sys_serv *sys_serv_priv; - - ret = uclass_get_device_by_name(UCLASS_MISC, "syscontroller", &dev); - if (ret) { - debug("%s: system controller setup failed\n", __func__); - return ret; - } - - sys_serv_priv = kzalloc(sizeof(*sys_serv_priv), GFP_KERNEL); - if (!sys_serv_priv) - return -ENOMEM; - - sys_serv_priv->dev = dev; - - sys_serv_priv->sys_controller = mpfs_syscontroller_get(dev); - ret = IS_ERR(sys_serv_priv->sys_controller); - if (ret) { - debug("%s: Failed to register system controller sub device ret=%d\n", __func__, ret); - return -ENODEV; - } - - ret = mpfs_syscontroller_read_sernum(sys_serv_priv, device_serial_number); - if (ret) { - printf("Cannot read device serial number\n"); - return -EINVAL; - } - - /* Update MAC address with device serial number */ - mac_addr[0] = 0x00; - mac_addr[1] = 0x04; - mac_addr[2] = 0xA3; - mac_addr[3] = device_serial_number[2]; - mac_addr[4] = device_serial_number[1]; - mac_addr[5] = device_serial_number[0]; - - node = fdt_path_offset(blob, "/soc/ethernet@20112000"); - if (node >= 0) { - ret = fdt_setprop(blob, node, "local-mac-address", mac_addr, 6); - if (ret) { - printf("Error setting local-mac-address property for ethernet@20112000\n"); - return -ENODEV; - } - } - - mac_addr[5] = device_serial_number[0] + 1; - - node = fdt_path_offset(blob, "/soc/ethernet@20110000"); - if (node >= 0) { - ret = fdt_setprop(blob, node, "local-mac-address", mac_addr, 6); - if (ret) { - printf("Error setting local-mac-address property for ethernet@20110000\n"); - return -ENODEV; - } - } - - return 0; -} - -int ft_board_setup(void *blob, struct bd_info *bd) -{ - u32 ret; - int node; - - node = fdt_path_offset(blob, "/soc/ethernet@20110000"); - if (node >= 0) { - ret = fdt_setprop(blob, node, "local-mac-address", mac_addr, 6); - if (ret) { - printf("Error setting local-mac-address property for ethernet@20110000\n"); - return -ENODEV; - } - } - - mac_addr[5] -= 1; - - node = fdt_path_offset(blob, "/soc/ethernet@20112000"); - if (node >= 0) { - ret = fdt_setprop(blob, node, "local-mac-address", mac_addr, 6); - if (ret) { - printf("Error setting local-mac-address property for ethernet@20112000\n"); - return -ENODEV; - } - } - - return 0; -} diff --git a/configs/microchip_mpfs_generic_defconfig b/configs/microchip_mpfs_generic_defconfig new file mode 100644 index 00000000000..0ed0cae93eb --- /dev/null +++ b/configs/microchip_mpfs_generic_defconfig @@ -0,0 +1,29 @@ +CONFIG_RISCV=y +CONFIG_SYS_MALLOC_LEN=0x800000 +CONFIG_SYS_MALLOC_F_LEN=0x2000 +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x80200000 +CONFIG_ENV_SIZE=0x2000 +CONFIG_DEFAULT_DEVICE_TREE="microchip/mpfs-icicle-kit" +CONFIG_OF_LIBFDT_OVERLAY=y +CONFIG_SYS_LOAD_ADDR=0x80200000 +CONFIG_SYS_MEM_TOP_HIDE=0x400000 +# CONFIG_DEBUG_UART is not set +CONFIG_TARGET_MICROCHIP_GENERIC=y +CONFIG_ARCH_RV64I=y +CONFIG_RISCV_SMODE=y +CONFIG_FIT=y +CONFIG_DISTRO_DEFAULTS=y +CONFIG_OF_BOARD_SETUP=y +CONFIG_DEFAULT_FDT_FILE="microchip/mpfs-icicle-kit.dtb" +CONFIG_SYS_CBSIZE=256 +CONFIG_SYS_PBSIZE=282 +CONFIG_DISPLAY_CPUINFO=y +CONFIG_DISPLAY_BOARDINFO=y +CONFIG_SYS_PROMPT="RISC-V # " +CONFIG_OF_UPSTREAM=y +CONFIG_ENV_OVERWRITE_ETHADDR_ONCE=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y +CONFIG_BOOTP_SEND_HOSTNAME=y +CONFIG_DM_MTD=y +CONFIG_SYSRESET=y diff --git a/configs/microchip_mpfs_icicle_defconfig b/configs/microchip_mpfs_icicle_defconfig deleted file mode 100644 index 9f933592c9d..00000000000 --- a/configs/microchip_mpfs_icicle_defconfig +++ /dev/null @@ -1,29 +0,0 @@ -CONFIG_RISCV=y -CONFIG_SYS_MALLOC_LEN=0x800000 -CONFIG_SYS_MALLOC_F_LEN=0x2000 -CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y -CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x80200000 -CONFIG_ENV_SIZE=0x2000 -CONFIG_DEFAULT_DEVICE_TREE="microchip/mpfs-icicle-kit" -CONFIG_OF_LIBFDT_OVERLAY=y -CONFIG_SYS_LOAD_ADDR=0x80200000 -CONFIG_SYS_MEM_TOP_HIDE=0x400000 -# CONFIG_DEBUG_UART is not set -CONFIG_TARGET_MICROCHIP_ICICLE=y -CONFIG_ARCH_RV64I=y -CONFIG_RISCV_SMODE=y -CONFIG_FIT=y -CONFIG_DISTRO_DEFAULTS=y -CONFIG_OF_BOARD_SETUP=y -CONFIG_DEFAULT_FDT_FILE="microchip/mpfs-icicle-kit.dtb" -CONFIG_SYS_CBSIZE=256 -CONFIG_SYS_PBSIZE=282 -CONFIG_DISPLAY_CPUINFO=y -CONFIG_DISPLAY_BOARDINFO=y -CONFIG_SYS_PROMPT="RISC-V # " -CONFIG_OF_UPSTREAM=y -CONFIG_ENV_OVERWRITE_ETHADDR_ONCE=y -CONFIG_ENV_RELOC_GD_ENV_ADDR=y -CONFIG_BOOTP_SEND_HOSTNAME=y -CONFIG_DM_MTD=y -CONFIG_SYSRESET=y diff --git a/include/configs/microchip_mpfs_generic.h b/include/configs/microchip_mpfs_generic.h new file mode 100644 index 00000000000..0077f6a5f95 --- /dev/null +++ b/include/configs/microchip_mpfs_generic.h @@ -0,0 +1,32 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2019 Microchip Technology Inc. + * Padmarao Begari + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#include + +#define CFG_SYS_SDRAM_BASE 0x80000000 + +/* Environment options */ + +#define BOOT_TARGET_DEVICES(func) \ + func(MMC, mmc, 0) \ + func(DHCP, dhcp, na) + +#include + +#define CFG_EXTRA_ENV_SETTINGS \ + "bootm_size=0x10000000\0" \ + "kernel_addr_r=0x84000000\0" \ + "fdt_addr_r=0x88000000\0" \ + "scriptaddr=0x88100000\0" \ + "pxefile_addr_r=0x88200000\0" \ + "ramdisk_addr_r=0x88300000\0" \ + "fdtfile=" CONFIG_DEFAULT_FDT_FILE "\0" \ + BOOTENV + +#endif /* __CONFIG_H */ diff --git a/include/configs/microchip_mpfs_icicle.h b/include/configs/microchip_mpfs_icicle.h deleted file mode 100644 index 0077f6a5f95..00000000000 --- a/include/configs/microchip_mpfs_icicle.h +++ /dev/null @@ -1,32 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2019 Microchip Technology Inc. - * Padmarao Begari - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -#include - -#define CFG_SYS_SDRAM_BASE 0x80000000 - -/* Environment options */ - -#define BOOT_TARGET_DEVICES(func) \ - func(MMC, mmc, 0) \ - func(DHCP, dhcp, na) - -#include - -#define CFG_EXTRA_ENV_SETTINGS \ - "bootm_size=0x10000000\0" \ - "kernel_addr_r=0x84000000\0" \ - "fdt_addr_r=0x88000000\0" \ - "scriptaddr=0x88100000\0" \ - "pxefile_addr_r=0x88200000\0" \ - "ramdisk_addr_r=0x88300000\0" \ - "fdtfile=" CONFIG_DEFAULT_FDT_FILE "\0" \ - BOOTENV - -#endif /* __CONFIG_H */ -- cgit v1.2.3 From 9b3a0ab138696c346bd78a064d9bfd9bc68a9a67 Mon Sep 17 00:00:00 2001 From: Jamie Gibbons Date: Tue, 2 Sep 2025 11:10:59 +0100 Subject: configs/microchip_mpfs_generic_defconfig: add board Add board support for MPFS video kit. Signed-off-by: Jamie Gibbons Reviewed-by: Leo Yu-Chi Liang --- configs/microchip_mpfs_generic_defconfig | 3 +++ 1 file changed, 3 insertions(+) diff --git a/configs/microchip_mpfs_generic_defconfig b/configs/microchip_mpfs_generic_defconfig index 0ed0cae93eb..22f67414a7c 100644 --- a/configs/microchip_mpfs_generic_defconfig +++ b/configs/microchip_mpfs_generic_defconfig @@ -22,6 +22,9 @@ CONFIG_DISPLAY_CPUINFO=y CONFIG_DISPLAY_BOARDINFO=y CONFIG_SYS_PROMPT="RISC-V # " CONFIG_OF_UPSTREAM=y +CONFIG_OF_BOARD=y +CONFIG_OF_LIST="microchip/mpfs-icicle-kit microchip/mpfs-sev-kit" +CONFIG_MULTI_DTB_FIT=y CONFIG_ENV_OVERWRITE_ETHADDR_ONCE=y CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_BOOTP_SEND_HOSTNAME=y -- cgit v1.2.3 From bd44736100a065f096d55c04577c8b011005f378 Mon Sep 17 00:00:00 2001 From: Jamie Gibbons Date: Tue, 2 Sep 2025 11:11:00 +0100 Subject: doc: microchip: introduce common sections With the upcoming additions of new MPFS boards, separate common documentation to allow this to be reused appropriately and avoid duplication. Signed-off-by: Jamie Gibbons Reviewed-by: Leo Yu-Chi Liang --- doc/board/microchip/mpfs_build_boot.rst | 29 ++ doc/board/microchip/mpfs_common.rst | 666 ++++++++++++++++++++++++++++ doc/board/microchip/mpfs_design_hss.rst | 37 ++ doc/board/microchip/mpfs_icicle.rst | 743 +------------------------------- 4 files changed, 742 insertions(+), 733 deletions(-) create mode 100644 doc/board/microchip/mpfs_build_boot.rst create mode 100644 doc/board/microchip/mpfs_common.rst create mode 100644 doc/board/microchip/mpfs_design_hss.rst diff --git a/doc/board/microchip/mpfs_build_boot.rst b/doc/board/microchip/mpfs_build_boot.rst new file mode 100644 index 00000000000..1239f675ec8 --- /dev/null +++ b/doc/board/microchip/mpfs_build_boot.rst @@ -0,0 +1,29 @@ +.. SPDX-License-Identifier: GPL-2.0+ + +Booting from eMMC using HSS +--------------------------- + +Building U-Boot +~~~~~~~~~~~~~~~ + +1. Add the RISC-V toolchain to your PATH. +2. Setup ARCH & cross compilation environment variable: + +.. code-block:: none + + export CROSS_COMPILE= + +3. make microchip_mpfs_generic_defconfig +4. make + +Flashing +~~~~~~~~ + +The current U-Boot port is supported in S-mode only and loaded from DRAM. + +A prior stage M-mode firmware/bootloader (e.g HSS with OpenSBI) is required to +boot the u-boot.bin in S-mode. + +Currently, the u-boot.bin is used as a payload of the HSS firmware (Microchip +boot-flow) and OpenSBI generic platform fw_payload.bin (with u-boot.bin embedded) +as HSS payload (Custom boot-flow) diff --git a/doc/board/microchip/mpfs_common.rst b/doc/board/microchip/mpfs_common.rst new file mode 100644 index 00000000000..edbaf043966 --- /dev/null +++ b/doc/board/microchip/mpfs_common.rst @@ -0,0 +1,666 @@ +.. SPDX-License-Identifier: GPL-2.0+ + +Creating the HSS payload - Custom boot-flow +''''''''''''''''''''''''''''''''''''''''''' + +1. You will be creating a payload from `fw_payload.bin`. + Copy this file to the HSS/tools/hss-payload-generator/test directory. +2. Go to hss-payload-generator source directory. + +.. code-block:: none + + cd hart-software-services/tools/hss-payload-generator + +3. Edit test/uboot.yaml file for hart entry points and correct name of the binary file. + + hart-entry-points: {u54_1: '0x80000000', u54_2: '0x80000000', u54_3: '0x80000000', u54_4: '0x80000000'} + + payloads: + test/fw_payload.bin: {exec-addr: '0x80000000', owner-hart: u54_1, secondary-hart: u54_2, secondary-hart: u54_3, secondary-hart: u54_4, priv-mode: prv_m} + +4. Generate payload + +.. code-block:: none + + ./hss-payload-generator -c test/uboot.yaml payload.bin + +Once the payload binary is generated, it should be copied to the eMMC. + +Please refer to HSS documenation to build the HSS firmware for payload. +(Note: HSS git repo is at https://github.com/polarfire-soc/hart-software-services/blob/master/tools/hss-payload-generator/README.md +and also refer the HSS payload generator at https://github.com/polarfire-soc/polarfire-soc-documentation/blob/master/software-development/hss-payloads.md) + +Program eMMC with HSS Payload +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +Program eMMC with payload binary is explained in the PolarFire SoC documentation. +(Note: PolarFire SoC Documentation git repo is at https://github.com/polarfire-soc/polarfire-soc-documentation/blob/master/boards/mpfs-icicle-kit-es/updating-icicle-kit/updating-icicle-kit-design-and-linux.md#eMMC) + +Once the payload image is copied to the eMMC, press CTRL+C in the HSS command +line interface, then type 'boot' and enter to boot the newly copied image. + +.. code-block:: none + + sudo dd if= of=/dev/sdX bs=512 + +GUID type with HSS Payload +~~~~~~~~~~~~~~~~~~~~~~~~~~ + +The HSS always picks up HSS payload from a GPT partition with +GUID type "21686148-6449-6E6F-744E-656564454649" or sector '0' of the eMMC if no +GPT partition. + +Booting with HSS Payload +~~~~~~~~~~~~~~~~~~~~~~~~ + +You should see the U-Boot prompt on UART1. +(Note: UART0 is reserved for HSS) + +Sample boot log from MPFS Icicle Kit +'''''''''''''''''''''''''''''''''''' + +.. code-block:: none + + U-Boot 2021.01-00314-g7303332537-dirty (Jan 14 2021 - 10:09:43 +0530) + + CPU: rv64imafdc + Model: Microchip MPFS Icicle Kit + DRAM: 1 GiB + MMC: sdhc@20008000: 0 + In: serial@20100000 + Out: serial@20100000 + Err: serial@20100000 + Net: eth0: ethernet@20112000 + Hit any key to stop autoboot: 0 + +Now you can configure your networking, tftp server and use tftp boot method to +load uImage (with initramfs). + +.. code-block:: none + + RISC-V # setenv kernel_addr_r 0x80200000 + RISC-V # setenv fdt_addr_r 0x82200000 + + RISC-V # setenv ipaddr 192.168.1.5 + RISC-V # setenv netmask 255.255.255.0 + RISC-V # setenv serverip 192.168.1.3 + RISC-V # setenv gateway 192.168.1.1 + + RISC-V # tftpboot ${kernel_addr_r} uImage + ethernet@20112000: PHY present at 9 + ethernet@20112000: Starting autonegotiation... + ethernet@20112000: Autonegotiation complete + ethernet@20112000: link up, 1000Mbps full-duplex (lpa: 0x7800) + Using ethernet@20112000 device + TFTP from server 192.168.1.3; our IP address is 192.168.1.5 + Filename 'uImage'. + Load address: 0x80200000 + Loading: ################################################################# + ################################################################# + ################################################################# + ################################################################# + ################################################################# + ################################################################# + ################################################################# + ################################################################# + ################################################################# + ################################################################# + ################################################################# + ################################################################# + ################################################################# + ################################################################# + ################################################################# + ############ + 6.4 MiB/s + done + Bytes transferred = 14482480 (dcfc30 hex) + + RISC-V # tftpboot ${fdt_addr_r} mpfs-icicle-kit.dtb + ethernet@20112000: PHY present at 9 + ethernet@20112000: Starting autonegotiation... + ethernet@20112000: Autonegotiation complete + ethernet@20112000: link up, 1000Mbps full-duplex (lpa: 0x7800) + Using ethernet@20112000 device + TFTP from server 192.168.1.3; our IP address is 192.168.1.5 + Filename 'mpfs-icicle-kit.dtb'. + Load address: 0x82200000 + Loading: # + 2.5 MiB/s + done + Bytes transferred = 10282 (282a hex) + + RISC-V # bootm ${kernel_addr_r} - ${fdt_addr_r} + ## Booting kernel from Legacy Image at 80200000 ... + Image Name: Linux + Image Type: RISC-V Linux Kernel Image (uncompressed) + Data Size: 14482416 Bytes = 13.8 MiB + Load Address: 80200000 + Entry Point: 80200000 + Verifying Checksum ... OK + ## Flattened Device Tree blob at 82200000 + Booting using the fdt blob at 0x82200000 + Loading Kernel Image + Using Device Tree in place at 000000008fffa000, end 000000008ffff829 ... OK + + Starting kernel ... + + [ 0.000000] OF: fdt: Ignoring memory range 0x80000000 - 0x80200000 + [ 0.000000] Linux version 5.6.17 (padmarao@padmarao-VirtualBox) (gcc version 7.2.0 (GCC)) #2 SMP Tue Jun 16 21:27:50 IST 2020 + [ 0.000000] initrd not found or empty - disabling initrd + [ 0.000000] Zone ranges: + [ 0.000000] DMA32 [mem 0x0000000080200000-0x00000000bfffffff] + [ 0.000000] Normal empty + [ 0.000000] Movable zone start for each node + [ 0.000000] Early memory node ranges + [ 0.000000] node 0: [mem 0x0000000080200000-0x00000000bfffffff] + [ 0.000000] Initmem setup node 0 [mem 0x0000000080200000-0x00000000bfffffff] + [ 0.000000] software IO TLB: mapped [mem 0xbb1f5000-0xbf1f5000] (64MB) + [ 0.000000] elf_hwcap is 0x112d + [ 0.000000] percpu: Embedded 14 pages/cpu s24856 r0 d32488 u57344 + [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 258055 + [ 0.000000] Kernel command line: console=ttyS0,115200n8 + [ 0.000000] Dentry cache hash table entries: 131072 (order: 8, 1048576 bytes, linear) + [ 0.000000] Inode-cache hash table entries: 65536 (order: 7, 524288 bytes, linear) + [ 0.000000] Sorting __ex_table... + [ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off + [ 0.000000] Memory: 950308K/1046528K available (3289K kernel code, 212K rwdata, 900K rodata, 9476K init, 250K bss, 96220K reserved, 0K cma-reserved) + [ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=4, Nodes=1 + [ 0.000000] rcu: Hierarchical RCU implementation. + [ 0.000000] rcu: RCU event tracing is enabled. + [ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=8 to nr_cpu_ids=4. + [ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 10 jiffies. + [ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=4 + [ 0.000000] NR_IRQS: 0, nr_irqs: 0, preallocated irqs: 0 + [ 0.000000] plic: mapped 186 interrupts with 4 handlers for 9 contexts. + [ 0.000000] riscv_timer_init_dt: Registering clocksource cpuid [0] hartid [1] + [ 0.000000] clocksource: riscv_clocksource: mask: 0xffffffffffffffff max_cycles: 0x1d854df40, max_idle_ns: 3526361616960 ns + [ 0.000015] sched_clock: 64 bits at 1000kHz, resolution 1000ns, wraps every 2199023255500ns + [ 0.000311] Calibrating delay loop (skipped), value calculated using timer frequency.. 2.00 BogoMIPS (lpj=10000) + [ 0.000349] pid_max: default: 32768 minimum: 301 + [ 0.000846] Mount-cache hash table entries: 2048 (order: 2, 16384 bytes, linear) + [ 0.000964] Mountpoint-cache hash table entries: 2048 (order: 2, 16384 bytes, linear) + [ 0.005630] rcu: Hierarchical SRCU implementation. + [ 0.006901] smp: Bringing up secondary CPUs ... + [ 0.012545] smp: Brought up 1 node, 4 CPUs + [ 0.014431] devtmpfs: initialized + [ 0.020526] random: get_random_bytes called from setup_net+0x36/0x192 with crng_init=0 + [ 0.020928] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 19112604462750000 ns + [ 0.020999] futex hash table entries: 1024 (order: 4, 65536 bytes, linear) + [ 0.022768] NET: Registered protocol family 16 + [ 0.035478] microchip-pfsoc-clkcfg 20002000.clkcfg: Registered PFSOC core clocks + [ 0.048429] SCSI subsystem initialized + [ 0.049694] pps_core: LinuxPPS API ver. 1 registered + [ 0.049719] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti + [ 0.049780] PTP clock support registered + [ 0.051781] clocksource: Switched to clocksource riscv_clocksource + [ 0.055326] NET: Registered protocol family 2 + [ 0.056922] tcp_listen_portaddr_hash hash table entries: 512 (order: 1, 8192 bytes, linear) + [ 0.057053] TCP established hash table entries: 8192 (order: 4, 65536 bytes, linear) + [ 0.057648] TCP bind hash table entries: 8192 (order: 5, 131072 bytes, linear) + [ 0.058579] TCP: Hash tables configured (established 8192 bind 8192) + [ 0.059648] UDP hash table entries: 512 (order: 2, 16384 bytes, linear) + [ 0.059837] UDP-Lite hash table entries: 512 (order: 2, 16384 bytes, linear) + [ 0.060707] NET: Registered protocol family 1 + [ 0.266229] workingset: timestamp_bits=62 max_order=18 bucket_order=0 + [ 0.287107] io scheduler mq-deadline registered + [ 0.287140] io scheduler kyber registered + [ 0.429601] Serial: 8250/16550 driver, 4 ports, IRQ sharing disabled + [ 0.433979] printk: console [ttyS0] disabled + [ 0.434154] 20000000.serial: ttyS0 at MMIO 0x20000000 (irq = 18, base_baud = 9375000) is a 16550A + [ 0.928039] printk: console [ttyS0] enabled + [ 0.939804] libphy: Fixed MDIO Bus: probed + [ 0.948702] libphy: MACB_mii_bus: probed + [ 0.993698] macb 20112000.ethernet eth0: Cadence GEM rev 0x0107010c at 0x20112000 irq 21 (56:34:12:00:fc:00) + [ 1.006751] mousedev: PS/2 mouse device common for all mice + [ 1.013803] i2c /dev entries driver + [ 1.019451] sdhci: Secure Digital Host Controller Interface driver + [ 1.027242] sdhci: Copyright(c) Pierre Ossman + [ 1.032731] sdhci-pltfm: SDHCI platform and OF driver helper + [ 1.091826] mmc0: SDHCI controller on 20008000.sdhc [20008000.sdhc] using ADMA 64-bit + [ 1.102738] NET: Registered protocol family 17 + [ 1.170326] Freeing unused kernel memory: 9476K + [ 1.176067] This architecture does not have kernel memory protection. + [ 1.184157] Run /init as init process + Starting logging: OK + Starting mdev... + /etc/init.d/S10mdev: line 21: can't create /proc/sys/kernel/hotplug: nonexiste[ 1.331981] mmc0: mmc_select_hs200 failed, error -74 + nt directory + [ 1.355011] mmc0: new MMC card at address 0001 + [ 1.363981] mmcblk0: mmc0:0001 DG4008 7.28 GiB + [ 1.372248] mmcblk0boot0: mmc0:0001 DG4008 partition 1 4.00 MiB + [ 1.382292] mmcblk0boot1: mmc0:0001 DG4008 partition 2 4.00 MiB + [ 1.390265] mmcblk0rpmb: mmc0:0001 DG4008 partition 3 4.00 MiB, chardev (251:0) + [ 1.425234] GPT:Primary header thinks Alt. header is not at the end of the disk. + [ 1.434656] GPT:2255809 != 15273599 + [ 1.439038] GPT:Alternate GPT header not at the end of the disk. + [ 1.446671] GPT:2255809 != 15273599 + [ 1.451048] GPT: Use GNU Parted to correct GPT errors. + [ 1.457755] mmcblk0: p1 p2 p3 + sort: /sys/devices/platform/Fixed: No such file or directory + modprobe: can't change directory to '/lib/modules': No such file or directory + Initializing random number generator... [ 2.830198] random: dd: uninitialized urandom read (512 bytes read) + done. + Starting network... + [ 3.061867] macb 20112000.ethernet eth0: PHY [20112000.ethernet-ffffffff:09] driver [Vitesse VSC8662] (irq=POLL) + [ 3.074674] macb 20112000.ethernet eth0: configuring for phy/sgmii link mode + [ 3.084263] pps pps0: new PPS source ptp0 + [ 3.089710] macb 20112000.ethernet: gem-ptp-timer ptp clock registered. + udhcpc (v1.24.2) started + Sending discover... + Sending discover... + [ 6.380169] macb 20112000.ethernet eth0: Link is Up - 1Gbps/Full - flow control tx + Sending discover... + Sending select for 192.168.1.2... + Lease of 192.168.1.2 obtained, lease time 86400 + deleting routers + adding dns 192.168.1.1 + Starting dropbear sshd: [ 11.385619] random: dropbear: uninitialized urandom read (32 bytes read) + OK + + Welcome to Buildroot + buildroot login: root + Password: + # + +Booting U-Boot and Linux from eMMC +'''''''''''''''''''''''''''''''''' + +FPGA design with HSS programming file and Linux Image +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +https://github.com/polarfire-soc/polarfire-soc-documentation/blob/master/boards/mpfs-icicle-kit-es/updating-icicle-kit/updating-icicle-kit-design-and-linux.md + +The HSS firmware runs from the PolarFire SoC eNVM on reset. + +Program eMMC with Payload Binary and Linux Image +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +Program eMMC with payload binary and Linux image is explained in the +PolarFire SoC documentation. +The payload binary should be copied to partition 2 of the eMMC. + +(Note: PolarFire SoC Documentation git repo is at https://github.com/polarfire-soc/polarfire-soc-documentation/blob/master/boards/mpfs-icicle-kit-es/updating-icicle-kit/updating-icicle-kit-design-and-linux.md#eMMC) + +Once the Linux image and payload binary is copied to the eMMC, press CTRL+C +in the HSS command line interface, then type 'boot' and enter to boot the newly +copied payload and Linux image. + +.. code-block:: none + + zcat .wic.gz | sudo dd of=/dev/sdX bs=4096 iflag=fullblock oflag=direct conv=fsync status=progress + + sudo dd if= of=/dev/sdX2 bs=512 + +You should see the U-Boot prompt on UART1. +(Note: UART0 is reserved for HSS) + +GUID type with Payload Binary and Linux Image +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +The HSS always picks up the HSS payload from a GPT partition with +GUID type "21686148-6449-6E6F-744E-656564454649" or sector '0' of the eMMC if no +GPT partition. + +Sample boot log from MPFS Icicle Kit 2 +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +.. code-block:: none + + U-Boot 2021.01-00314-g7303332537-dirty (Jan 14 2021 - 10:09:43 +0530) + + CPU: rv64imafdc + Model: Microchip MPFS Icicle Kit + DRAM: 1 GiB + MMC: sdhc@20008000: 0 + In: serial@20100000 + Out: serial@20100000 + Err: serial@20100000 + Net: eth0: ethernet@20112000 + Hit any key to stop autoboot: 0 + + RISC-V # mmc info + Device: sdhc@20008000 + Manufacturer ID: 45 + OEM: 100 + Name: DG400 + Bus Speed: 52000000 + Mode: MMC High Speed (52MHz) + Rd Block Len: 512 + MMC version 5.1 + High Capacity: Yes + Capacity: 7.3 GiB + Bus Width: 4-bit + Erase Group Size: 512 KiB + HC WP Group Size: 8 MiB + User Capacity: 7.3 GiB WRREL + Boot Capacity: 4 MiB ENH + RPMB Capacity: 4 MiB ENH + + RISC-V # mmc part + Partition Map for MMC device 0 -- Partition Type: EFI + + Part Start LBA End LBA Name + Attributes + Type GUID + Partition GUID + 1 0x00002000 0x0000b031 "boot" + attrs: 0x0000000000000004 + type: ebd0a0a2-b9e5-4433-87c0-68b6b72699c7 + guid: 99ff6a94-f2e7-44dd-a7df-f3a2da106ef9 + 2 0x0000b032 0x0000f031 "primary" + attrs: 0x0000000000000000 + type: 21686148-6449-6e6f-744e-656564454649 + guid: 12006052-e64b-4423-beb0-b956ea00f1ba + 3 0x00010000 0x00226b9f "root" + attrs: 0x0000000000000000 + type: 0fc63daf-8483-4772-8e79-3d69d8477de4 + guid: dd2c5619-2272-4c3c-8dc2-e21942e17ce6 + + RISC-V # load mmc 0 ${ramdisk_addr_r} fitimage + RISC-V # bootm ${ramdisk_addr_r} + ## Loading kernel from FIT Image at 88300000 ... + Using 'conf@microchip_icicle-kit-es-a000-microchip.dtb' configuration + Trying 'kernel@1' kernel subimage + Description: Linux kernel + Type: Kernel Image + Compression: gzip compressed + Data Start: 0x883000fc + Data Size: 3574555 Bytes = 3.4 MiB + Architecture: RISC-V + OS: Linux + Load Address: 0x80200000 + Entry Point: 0x80200000 + Hash algo: sha256 + Hash value: 21f18d72cf2f0a7192220abb577ad25c77c26960052d779aa02bf55dbf0a6403 + Verifying Hash Integrity ... sha256+ OK + ## Loading fdt from FIT Image at 88300000 ... + Using 'conf@microchip_icicle-kit-es-a000-microchip.dtb' configuration + Trying 'fdt@microchip_icicle-kit-es-a000-microchip.dtb' fdt subimage + Description: Flattened Device Tree blob + Type: Flat Device Tree + Compression: uncompressed + Data Start: 0x88668d44 + Data Size: 9760 Bytes = 9.5 KiB + Architecture: RISC-V + Load Address: 0x82200000 + Hash algo: sha256 + Hash value: 5c3a9f30d41b6b8e53b47916e1f339b3a4d454006554d1f7e1f552ed62409f4b + Verifying Hash Integrity ... sha256+ OK + Loading fdt from 0x88668d48 to 0x82200000 + Booting using the fdt blob at 0x82200000 + Uncompressing Kernel Image + Loading Device Tree to 000000008fffa000, end 000000008ffff61f ... OK + + Starting kernel ... + + [ 0.000000] OF: fdt: Ignoring memory range 0x80000000 - 0x80200000 + [ 0.000000] Linux version 5.6.16 (oe-user@oe-host) (gcc version 9.3.0 (GCC)) #1 SMP Fri Oct 9 11:49:47 UTC 2020 + [ 0.000000] earlycon: sbi0 at I/O port 0x0 (options '') + [ 0.000000] printk: bootconsole [sbi0] enabled + [ 0.000000] Zone ranges: + [ 0.000000] DMA32 [mem 0x0000000080200000-0x00000000bfffffff] + [ 0.000000] Normal empty + [ 0.000000] Movable zone start for each node + [ 0.000000] Early memory node ranges + [ 0.000000] node 0: [mem 0x0000000080200000-0x00000000bfffffff] + [ 0.000000] Zeroed struct page in unavailable ranges: 512 pages + [ 0.000000] Initmem setup node 0 [mem 0x0000000080200000-0x00000000bfffffff] + [ 0.000000] software IO TLB: mapped [mem 0xb9e00000-0xbde00000] (64MB) + [ 0.000000] CPU with hartid=0 is not available + [ 0.000000] CPU with hartid=0 is not available + [ 0.000000] elf_hwcap is 0x112d + [ 0.000000] percpu: Embedded 17 pages/cpu s29784 r8192 d31656 u69632 + [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 258055 + [ 0.000000] Kernel command line: earlycon=sbi root=/dev/mmcblk0p3 rootwait console=ttyS0,115200n8 uio_pdrv_genirq.of_id=generic-uio + [ 0.000000] Dentry cache hash table entries: 131072 (order: 8, 1048576 bytes, linear) + [ 0.000000] Inode-cache hash table entries: 65536 (order: 7, 524288 bytes, linear) + [ 0.000000] Sorting __ex_table... + [ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off + [ 0.000000] Memory: 941440K/1046528K available (4118K kernel code, 280K rwdata, 1687K rodata, 169K init, 273K bss, 105088K reserved, 0K cma-reserved) + [ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=4, Nodes=1 + [ 0.000000] rcu: Hierarchical RCU implementation. + [ 0.000000] rcu: RCU event tracing is enabled. + [ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=5 to nr_cpu_ids=4. + [ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 10 jiffies. + [ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=4 + [ 0.000000] NR_IRQS: 0, nr_irqs: 0, preallocated irqs: 0 + [ 0.000000] plic: mapped 53 interrupts with 4 handlers for 9 contexts. + [ 0.000000] riscv_timer_init_dt: Registering clocksource cpuid [0] hartid [1] + [ 0.000000] clocksource: riscv_clocksource: mask: 0xffffffffffffffff max_cycles: 0x1d854df40, max_idle_ns: 3526361616960 ns + [ 0.000015] sched_clock: 64 bits at 1000kHz, resolution 1000ns, wraps every 2199023255500ns + [ 0.008679] Console: colour dummy device 80x25 + [ 0.013112] Calibrating delay loop (skipped), value calculated using timer frequency.. 2.00 BogoMIPS (lpj=10000) + [ 0.023368] pid_max: default: 32768 minimum: 301 + [ 0.028314] Mount-cache hash table entries: 2048 (order: 2, 16384 bytes, linear) + [ 0.035766] Mountpoint-cache hash table entries: 2048 (order: 2, 16384 bytes, linear) + [ 0.047099] rcu: Hierarchical SRCU implementation. + [ 0.052813] smp: Bringing up secondary CPUs ... + [ 0.061581] smp: Brought up 1 node, 4 CPUs + [ 0.067069] devtmpfs: initialized + [ 0.073621] random: get_random_u32 called from bucket_table_alloc.isra.0+0x4e/0x150 with crng_init=0 + [ 0.074409] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 19112604462750000 ns + [ 0.093399] futex hash table entries: 1024 (order: 4, 65536 bytes, linear) + [ 0.101879] NET: Registered protocol family 16 + [ 0.110336] microchip-pfsoc-clkcfg 20002000.clkcfg: Registered PFSOC core clocks + [ 0.132717] usbcore: registered new interface driver usbfs + [ 0.138225] usbcore: registered new interface driver hub + [ 0.143813] usbcore: registered new device driver usb + [ 0.148939] pps_core: LinuxPPS API ver. 1 registered + [ 0.153929] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti + [ 0.163071] PTP clock support registered + [ 0.168521] clocksource: Switched to clocksource riscv_clocksource + [ 0.174927] VFS: Disk quotas dquot_6.6.0 + [ 0.179016] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes) + [ 0.205536] NET: Registered protocol family 2 + [ 0.210944] tcp_listen_portaddr_hash hash table entries: 512 (order: 1, 8192 bytes, linear) + [ 0.219393] TCP established hash table entries: 8192 (order: 4, 65536 bytes, linear) + [ 0.227497] TCP bind hash table entries: 8192 (order: 5, 131072 bytes, linear) + [ 0.235440] TCP: Hash tables configured (established 8192 bind 8192) + [ 0.242537] UDP hash table entries: 512 (order: 2, 16384 bytes, linear) + [ 0.249285] UDP-Lite hash table entries: 512 (order: 2, 16384 bytes, linear) + [ 0.256690] NET: Registered protocol family 1 + [ 0.262585] workingset: timestamp_bits=62 max_order=18 bucket_order=0 + [ 0.281036] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 249) + [ 0.288481] io scheduler mq-deadline registered + [ 0.292983] io scheduler kyber registered + [ 0.298895] microsemi,mss-gpio 20122000.gpio: Microsemi MSS GPIO registered 32 GPIOs + [ 0.453723] Serial: 8250/16550 driver, 4 ports, IRQ sharing disabled + [ 0.462911] printk: console [ttyS0] disabled + [ 0.467216] 20100000.serial: ttyS0 at MMIO 0x20100000 (irq = 12, base_baud = 9375000) is a 16550A + [ 0.476201] printk: console [ttyS0] enabled + [ 0.476201] printk: console [ttyS0] enabled + [ 0.484576] printk: bootconsole [sbi0] disabled + [ 0.484576] printk: bootconsole [sbi0] disabled + [ 0.494920] 20102000.serial: ttyS1 at MMIO 0x20102000 (irq = 13, base_baud = 9375000) is a 16550A + [ 0.505068] 20104000.serial: ttyS2 at MMIO 0x20104000 (irq = 14, base_baud = 9375000) is a 16550A + [ 0.533336] loop: module loaded + [ 0.572284] Rounding down aligned max_sectors from 4294967295 to 4294967288 + [ 0.580000] db_root: cannot open: /etc/target + [ 0.585413] libphy: Fixed MDIO Bus: probed + [ 0.591526] libphy: MACB_mii_bus: probed + [ 0.598060] macb 20112000.ethernet eth0: Cadence GEM rev 0x0107010c at 0x20112000 irq 17 (56:34:12:00:fc:00) + [ 0.608352] ehci_hcd: USB 2.0 'Enhanced' Host Controller (EHCI) Driver + [ 0.615001] ehci-platform: EHCI generic platform driver + [ 0.620446] ohci_hcd: USB 1.1 'Open' Host Controller (OHCI) Driver + [ 0.626632] ohci-platform: OHCI generic platform driver + [ 0.632326] usbcore: registered new interface driver cdc_acm + [ 0.637996] cdc_acm: USB Abstract Control Model driver for USB modems and ISDN adapters + [ 0.646459] i2c /dev entries driver + [ 0.650852] microsemi-mss-i2c 2010b000.i2c: Microsemi I2C Probe Complete + [ 0.658010] sdhci: Secure Digital Host Controller Interface driver + [ 0.664326] sdhci: Copyright(c) Pierre Ossman + [ 0.668754] sdhci-pltfm: SDHCI platform and OF driver helper + [ 0.706845] mmc0: SDHCI controller on 20008000.sdhc [20008000.sdhc] using ADMA 64-bit + [ 0.715052] usbcore: registered new interface driver usbhid + [ 0.720722] usbhid: USB HID core driver + [ 0.725174] pac193x 0-0010: Chip revision: 0x03 + [ 0.733339] pac193x 0-0010: :pac193x_prep_iio_channels: Channel 0 active + [ 0.740127] pac193x 0-0010: :pac193x_prep_iio_channels: Channel 1 active + [ 0.746881] pac193x 0-0010: :pac193x_prep_iio_channels: Channel 2 active + [ 0.753686] pac193x 0-0010: :pac193x_prep_iio_channels: Channel 3 active + [ 0.760495] pac193x 0-0010: :pac193x_prep_iio_channels: Active chip channels: 25 + [ 0.778006] NET: Registered protocol family 10 + [ 0.784929] Segment Routing with IPv6 + [ 0.788875] sit: IPv6, IPv4 and MPLS over IPv4 tunneling driver + [ 0.795743] NET: Registered protocol family 17 + [ 0.801191] hctosys: unable to open rtc device (rtc0) + [ 0.807774] Waiting for root device /dev/mmcblk0p3... + [ 0.858506] mmc0: mmc_select_hs200 failed, error -74 + [ 0.865764] mmc0: new MMC card at address 0001 + [ 0.872564] mmcblk0: mmc0:0001 DG4008 7.28 GiB + [ 0.878777] mmcblk0boot0: mmc0:0001 DG4008 partition 1 4.00 MiB + [ 0.886182] mmcblk0boot1: mmc0:0001 DG4008 partition 2 4.00 MiB + [ 0.892633] mmcblk0rpmb: mmc0:0001 DG4008 partition 3 4.00 MiB, chardev (247:0) + [ 0.919029] GPT:Primary header thinks Alt. header is not at the end of the disk. + [ 0.926448] GPT:2255841 != 15273599 + [ 0.930019] GPT:Alternate GPT header not at the end of the disk. + [ 0.936029] GPT:2255841 != 15273599 + [ 0.939583] GPT: Use GNU Parted to correct GPT errors. + [ 0.944800] mmcblk0: p1 p2 p3 + [ 0.966696] EXT4-fs (mmcblk0p3): INFO: recovery required on readonly filesystem + [ 0.974105] EXT4-fs (mmcblk0p3): write access will be enabled during recovery + [ 1.052362] random: fast init done + [ 1.057961] EXT4-fs (mmcblk0p3): recovery complete + [ 1.065734] EXT4-fs (mmcblk0p3): mounted filesystem with ordered data mode. Opts: (null) + [ 1.074002] VFS: Mounted root (ext4 filesystem) readonly on device 179:3. + [ 1.081654] Freeing unused kernel memory: 168K + [ 1.086108] This architecture does not have kernel memory protection. + [ 1.092629] Run /sbin/init as init process + [ 1.702217] systemd[1]: System time before build time, advancing clock. + [ 1.754192] systemd[1]: systemd 244.3+ running in system mode. (+PAM -AUDIT -SELINUX +IMA -APPARMOR -SMACK +SYSVINIT +UTMP -LIBCRYPTSETUP -GCRYPT -GNUTLS +ACL +XZ -LZ4 -SECCOMP +BLKID -ELFUTILS +KMOD -IDN2 -IDN -PCRE2 default-hierarchy=hybrid) + [ 1.776361] systemd[1]: Detected architecture riscv64. + + Welcome to OpenEmbedded nodistro.0! + + [ 1.829651] systemd[1]: Set hostname to . + [ 2.648597] random: systemd: uninitialized urandom read (16 bytes read) + [ 2.657485] systemd[1]: Created slice system-getty.slice. + [ OK ] Created slice system-getty.slice. + [ 2.698779] random: systemd: uninitialized urandom read (16 bytes read) + [ 2.706317] systemd[1]: Created slice system-serial\x2dgetty.slice. + [ OK ] Created slice system-serial\x2dgetty.slice. + [ 2.748716] random: systemd: uninitialized urandom read (16 bytes read) + [ 2.756098] systemd[1]: Created slice User and Session Slice. + [ OK ] Created slice User and Session Slice. + [ 2.789065] systemd[1]: Started Dispatch Password Requests to Console Directory Watch. + [ OK ] Started Dispatch Password …ts to Console Directory Watch. + [ 2.828974] systemd[1]: Started Forward Password Requests to Wall Directory Watch. + [ OK ] Started Forward Password R…uests to Wall Directory Watch. + [ 2.869009] systemd[1]: Reached target Paths. + [ OK ] Reached target Paths. + [ 2.898808] systemd[1]: Reached target Remote File Systems. + [ OK ] Reached target Remote File Systems. + [ 2.938771] systemd[1]: Reached target Slices. + [ OK ] Reached target Slices. + [ 2.968754] systemd[1]: Reached target Swap. + [ OK ] Reached target Swap. + [ 2.999283] systemd[1]: Listening on initctl Compatibility Named Pipe. + [ OK ] Listening on initctl Compatibility Named Pipe. + [ 3.060458] systemd[1]: Condition check resulted in Journal Audit Socket being skipped. + [ 3.069826] systemd[1]: Listening on Journal Socket (/dev/log). + [ OK ] Listening on Journal Socket (/dev/log). + [ 3.109601] systemd[1]: Listening on Journal Socket. + [ OK ] Listening on Journal Socket. + [ 3.149868] systemd[1]: Listening on Network Service Netlink Socket. + [ OK ] Listening on Network Service Netlink Socket. + [ 3.189419] systemd[1]: Listening on udev Control Socket. + [ OK ] Listening on udev Control Socket. + [ 3.229179] systemd[1]: Listening on udev Kernel Socket. + [ OK ] Listening on udev Kernel Socket. + [ 3.269520] systemd[1]: Condition check resulted in Huge Pages File System being skipped. + [ 3.278477] systemd[1]: Condition check resulted in POSIX Message Queue File System being skipped. + [ 3.288200] systemd[1]: Condition check resulted in Kernel Debug File System being skipped. + [ 3.302570] systemd[1]: Mounting Temporary Directory (/tmp)... + Mounting Temporary Directory (/tmp)... + [ 3.339226] systemd[1]: Condition check resulted in Create list of static device nodes for the current kernel being skipped. + [ 3.355883] systemd[1]: Starting File System Check on Root Device... + Starting File System Check on Root Device... + [ 3.407220] systemd[1]: Starting Journal Service... + Starting Journal Service... + [ 3.422441] systemd[1]: Condition check resulted in Load Kernel Modules being skipped. + [ 3.431770] systemd[1]: Condition check resulted in FUSE Control File System being skipped. + [ 3.446415] systemd[1]: Mounting Kernel Configuration File System... + Mounting Kernel Configuration File System... + [ 3.458983] systemd[1]: Starting Apply Kernel Variables... + Starting Apply Kernel Variables... + [ 3.471368] systemd[1]: Starting udev Coldplug all Devices... + Starting udev Coldplug all Devices... + [ 3.491071] systemd[1]: Mounted Temporary Directory (/tmp). + [ OK 3.498114] systemd[1]: Mounted Kernel Configuration File System. + 0m] Mounted Temporary Directory (/tmp). + [ OK ] Mounted Kernel Configuration File System. + [ 3.550853] systemd[1]: Started Apply Kernel Variables. + [ OK 3.557535] systemd[1]: Started Journal Service. + 0m] Started Apply Kernel Variables. + [ OK ] Started Journal Service. + [ OK ] Started udev Coldplug all Devices. + [ OK ] Started File System Check on Root Device. + Starting Remount Root and Kernel File Systems... + [ 8.133469] EXT4-fs (mmcblk0p3): re-mounted. Opts: (null) + [ OK ] Started Remount Root and Kernel File Systems. + Starting Flush Journal to Persistent Storage... + [ 8.215327] systemd-journald[77]: Received client request to flush runtime journal. + Starting Create Static Device Nodes in /dev... + [ OK ] Started Flush Journal to Persistent Storage. + [ OK ] Started Create Static Device Nodes in /dev. + [ OK ] Reached target Local File Systems (Pre). + Mounting /var/volatile... + Starting udev Kernel Device Manager... + [ OK ] Mounted /var/volatile. + Starting Load/Save Random Seed... + [ OK ] Reached target Local File Systems. + Starting Create Volatile Files and Directories... + [ OK ] Started udev Kernel Device Manager. + [ OK ] Started Create Volatile Files and Directories. + Starting Network Time Synchronization... + Starting Update UTMP about System Boot/Shutdown... + [ OK ] Started Update UTMP about System Boot/Shutdown. + [ OK ] Started Network Time Synchronization. + [ 11.618575] random: crng init done + [ 11.622007] random: 7 urandom warning(s) missed due to ratelimiting + [ OK ] Started Load/Save Random Seed. + [ OK ] Reached target System Initialization. + [ OK ] Started Daily Cleanup of Temporary Directories. + [ OK ] Reached target System Time Set. + [ OK ] Reached target System Time Synchronized. + [ OK ] Reached target Timers. + [ OK ] Listening on D-Bus System Message Bus Socket. + [ OK ] Listening on dropbear.socket. + [ OK ] Reached target Sockets. + [ OK ] Reached target Basic System. + [ OK ] Started D-Bus System Message Bus. + Starting IPv6 Packet Filtering Framework... + Starting IPv4 Packet Filtering Framework... + Starting Login Service... + [ OK ] Started IPv6 Packet Filtering Framework. + [ OK ] Started IPv4 Packet Filtering Framework. + [ OK ] Reached target Network (Pre). + Starting Network Service... + [ OK ] Started Login Service. + [ 12.602455] macb 20112000.ethernet eth0: PHY [20112000.ethernet-ffffffff:09] driver [Vitesse VSC8662] (irq=POLL) + [ 12.612795] macb 20112000.ethernet eth0: configuring for phy/sgmii link mode + [ 12.622153] pps pps0: new PPS source ptp0 + [ OK 12.626725] macb 20112000.ethernet: gem-ptp-timer ptp clock registered. + 0m] Started Network Service. + Starting Network Name Resolution... + [ OK ] Started Network Name Resolution. + [ OK ] Reached target Network. + [ OK ] Reached target Host and Network Name Lookups. + [ OK ] Started Collectd. + [ OK ] Started Collectd. + Starting Permit User Sessions... + [ OK ] Started Permit User Sessions. + [ OK ] Started Getty on tty1. + [ OK ] Started Serial Getty on ttyS0. + [ OK ] Reached target Login Prompts. + [ OK ] Reached target Multi-User System. + Starting Update UTMP about System Runlevel Changes... + [ OK ] Started Update UTMP about System Runlevel Changes. + + OpenEmbedded nodistro.0 icicle-kit-es ttyS0 + + icicle-kit-es login: [ 15.795564] macb 20112000.ethernet eth0: Link is Up - 1Gbps/Full - flow control tx + [ 15.803306] IPv6: ADDRCONF(NETDEV_CHANGE): eth0: link becomes ready + + icicle-kit-es login: root + root@icicle-kit-es:~# diff --git a/doc/board/microchip/mpfs_design_hss.rst b/doc/board/microchip/mpfs_design_hss.rst new file mode 100644 index 00000000000..d4100470758 --- /dev/null +++ b/doc/board/microchip/mpfs_design_hss.rst @@ -0,0 +1,37 @@ +.. SPDX-License-Identifier: GPL-2.0+ + +FPGA design with HSS programming file +''''''''''''''''''''''''''''''''''''' + +https://github.com/polarfire-soc/polarfire-soc-documentation/blob/master/reference-designs-fpga-and-development-kits/updating-linux-in-mpfs-kit.md + +The HSS firmware runs from the PolarFire SoC eNVM on reset. + +Creating the HSS payload - Microchip boot-flow +'''''''''''''''''''''''''''''''''''''''''''''' + +1. You will be creating a payload from `u-boot-dtb.bin`. + Copy this file to the HSS/tools/hss-payload-generator/test directory. +2. Go to hss-payload-generator source directory. + +.. code-block:: none + + cd hart-software-services/tools/hss-payload-generator + +3. Edit test/uboot.yaml file for hart entry points and correct name of the binary file. + + hart-entry-points: {u54_1: '0x80200000', u54_2: '0x80200000', u54_3: '0x80200000', u54_4: '0x80200000'} + + payloads: + test/u-boot-dtb.bin: {exec-addr: '0x80200000', owner-hart: u54_1, secondary-hart: u54_2, secondary-hart: u54_3, secondary-hart: u54_4, priv-mode: prv_s} + +4. Generate payload + +.. code-block:: none + + ./hss-payload-generator -c test/uboot.yaml payload.bin + +Once the payload binary is generated, it should be copied to the eMMC. + +Please refer to HSS documenation to build the HSS firmware for payload. +(Note: HSS git repo is at https://github.com/polarfire-soc/hart-software-services/blob/master/tools/hss-payload-generator/README.md) \ No newline at end of file diff --git a/doc/board/microchip/mpfs_icicle.rst b/doc/board/microchip/mpfs_icicle.rst index 1464e536e94..5af7125bde0 100644 --- a/doc/board/microchip/mpfs_icicle.rst +++ b/doc/board/microchip/mpfs_icicle.rst @@ -22,33 +22,7 @@ The support for following drivers are already enabled: 4. Cadence MMC Driver for eMMC/SD support. 5. Microchip I2C Driver. -Booting from eMMC using HSS ---------------------------- - -Building U-Boot -~~~~~~~~~~~~~~~ - -1. Add the RISC-V toolchain to your PATH. -2. Setup ARCH & cross compilation environment variable: - -.. code-block:: none - - export CROSS_COMPILE= - -3. make microchip_mpfs_icicle_defconfig -4. make - -Flashing -~~~~~~~~ - -The current U-Boot port is supported in S-mode only and loaded from DRAM. - -A prior stage M-mode firmware/bootloader (e.g HSS with OpenSBI) is required to -boot the u-boot.bin in S-mode. - -Currently, the u-boot.bin is used as a payload of the HSS firmware (Microchip -boot-flow) and OpenSBI generic platform fw_payload.bin (with u-boot.bin embedded) -as HSS payload (Custom boot-flow) +.. include:: mpfs_build_boot.rst Microchip boot-flow ~~~~~~~~~~~~~~~~~~~ @@ -64,55 +38,21 @@ Build the HSS (Hart Software Services) - Microchip boot-flow .. code-block:: none - make BOARD=icicle-kit-es config + make BOARD=mpfs-icicle-kit-es config Alternatively, copy the default config for Microchip boot-flow. .. code-block:: none - cp boards/icicle-kit-es/def_config .config + cp boards/mpfs-icicle-kit-es/def_config .config -2. make BOARD=icicle-kit-es +2. make BOARD=mpfs-icicle-kit-es 3. In the Default subdirectory, the standard build will create hss.elf and various binary formats (hss.hex and hss.bin). The FPGA design will use the hss.hex or hss.bin. -FPGA design with HSS programming file -''''''''''''''''''''''''''''''''''''' - -https://github.com/polarfire-soc/polarfire-soc-documentation/blob/master/boards/mpfs-icicle-kit-es/updating-icicle-kit/updating-icicle-kit-design-and-linux.md - -The HSS firmware runs from the PolarFire SoC eNVM on reset. - -Creating the HSS payload - Microchip boot-flow -'''''''''''''''''''''''''''''''''''''''''''''' - -1. You will be creating a payload from `u-boot-dtb.bin`. - Copy this file to the HSS/tools/hss-payload-generator/test directory. -2. Go to hss-payload-generator source directory. - -.. code-block:: none - - cd hart-software-services/tools/hss-payload-generator - -3. Edit test/uboot.yaml file for hart entry points and correct name of the binary file. - - hart-entry-points: {u54_1: '0x80200000', u54_2: '0x80200000', u54_3: '0x80200000', u54_4: '0x80200000'} - - payloads: - test/u-boot-dtb.bin: {exec-addr: '0x80200000', owner-hart: u54_1, secondary-hart: u54_2, secondary-hart: u54_3, secondary-hart: u54_4, priv-mode: prv_s} - -4. Generate payload - -.. code-block:: none - - ./hss-payload-generator -c test/uboot.yaml payload.bin - -Once the payload binary is generated, it should be copied to the eMMC. - -Please refer to HSS documenation to build the HSS firmware for payload. -(Note: HSS git repo is at https://github.com/polarfire-soc/hart-software-services/blob/master/tools/hss-payload-generator/README.md) +.. include:: mpfs_design_hss.rst Custom boot-flow ~~~~~~~~~~~~~~~~ @@ -134,7 +74,7 @@ Build OpenSBI .. code-block:: none make PLATFORM=generic FW_PAYLOAD_PATH=/u-boot.bin - FW_FDT_PATH=/arch/riscv/dts/mpfs-icicle-kit-.dtb + FW_FDT_PATH=/dts/upstream/src/riscv/microchip/mpfs-icicle-kit-.dtb 3. Output "fw_payload.bin" file available at "/build/platform/generic/firmware/fw_payload.bin" @@ -148,681 +88,18 @@ Build the HSS (Hart Software Services)- Custom boot-flow .. code-block:: none - make BOARD=icicle-kit-es config + make BOARD=mpfs-icicle-kit-es config Alternatively, copy the default custom config for Custom boot-flow. .. code-block:: none - cp boards/icicle-kit-es/def_config_custom .config + cp boards/mpfs-icicle-kit-es/def_config_custom .config -2. make BOARD=icicle-kit-es +2. make BOARD=mpfs-icicle-kit-es 3. In the Default subdirectory, the standard build will create hss.elf and various binary formats (hss.hex and hss.bin). The FPGA design will use the hss.hex or hss.bin. -Creating the HSS payload - Custom boot-flow -''''''''''''''''''''''''''''''''''''''''''' - -1. You will be creating a payload from `fw_payload.bin`. - Copy this file to the HSS/tools/hss-payload-generator/test directory. -2. Go to hss-payload-generator source directory. - -.. code-block:: none - - cd hart-software-services/tools/hss-payload-generator - -3. Edit test/uboot.yaml file for hart entry points and correct name of the binary file. - - hart-entry-points: {u54_1: '0x80000000', u54_2: '0x80000000', u54_3: '0x80000000', u54_4: '0x80000000'} - - payloads: - test/fw_payload.bin: {exec-addr: '0x80000000', owner-hart: u54_1, secondary-hart: u54_2, secondary-hart: u54_3, secondary-hart: u54_4, priv-mode: prv_m} - -4. Generate payload - -.. code-block:: none - - ./hss-payload-generator -c test/uboot.yaml payload.bin - -Once the payload binary is generated, it should be copied to the eMMC. - -Please refer to HSS documenation to build the HSS firmware for payload. -(Note: HSS git repo is at https://github.com/polarfire-soc/hart-software-services/blob/master/tools/hss-payload-generator/README.md -and also refer the HSS payload generator at https://github.com/polarfire-soc/polarfire-soc-documentation/blob/master/software-development/hss-payloads.md) - -eMMC -~~~~ - -Program eMMC with payload binary is explained in the PolarFire SoC documentation. -(Note: PolarFire SoC Documentation git repo is at https://github.com/polarfire-soc/polarfire-soc-documentation/blob/master/boards/mpfs-icicle-kit-es/updating-icicle-kit/updating-icicle-kit-design-and-linux.md#eMMC) - -Once the payload image is copied to the eMMC, press CTRL+C in the HSS command -line interface, then type 'boot' and enter to boot the newly copied image. - -.. code-block:: none - - sudo dd if= of=/dev/sdX bs=512 - -GUID type -~~~~~~~~~ - -The HSS always picks up HSS payload from a GPT partition with -GUID type "21686148-6449-6E6F-744E-656564454649" or sector '0' of the eMMC if no -GPT partition. - -Booting -~~~~~~~ - -You should see the U-Boot prompt on UART1. -(Note: UART0 is reserved for HSS) - -Sample boot log from MPFS Icicle Kit -'''''''''''''''''''''''''''''''''''' - -.. code-block:: none - - U-Boot 2021.01-00314-g7303332537-dirty (Jan 14 2021 - 10:09:43 +0530) - - CPU: rv64imafdc - Model: Microchip MPFS Icicle Kit - DRAM: 1 GiB - MMC: sdhc@20008000: 0 - In: serial@20100000 - Out: serial@20100000 - Err: serial@20100000 - Net: eth0: ethernet@20112000 - Hit any key to stop autoboot: 0 - -Now you can configure your networking, tftp server and use tftp boot method to -load uImage (with initramfs). - -.. code-block:: none - - RISC-V # setenv kernel_addr_r 0x80200000 - RISC-V # setenv fdt_addr_r 0x82200000 - - RISC-V # setenv ipaddr 192.168.1.5 - RISC-V # setenv netmask 255.255.255.0 - RISC-V # setenv serverip 192.168.1.3 - RISC-V # setenv gateway 192.168.1.1 - - RISC-V # tftpboot ${kernel_addr_r} uImage - ethernet@20112000: PHY present at 9 - ethernet@20112000: Starting autonegotiation... - ethernet@20112000: Autonegotiation complete - ethernet@20112000: link up, 1000Mbps full-duplex (lpa: 0x7800) - Using ethernet@20112000 device - TFTP from server 192.168.1.3; our IP address is 192.168.1.5 - Filename 'uImage'. - Load address: 0x80200000 - Loading: ################################################################# - ################################################################# - ################################################################# - ################################################################# - ################################################################# - ################################################################# - ################################################################# - ################################################################# - ################################################################# - ################################################################# - ################################################################# - ################################################################# - ################################################################# - ################################################################# - ################################################################# - ############ - 6.4 MiB/s - done - Bytes transferred = 14482480 (dcfc30 hex) - - RISC-V # tftpboot ${fdt_addr_r} mpfs-icicle-kit.dtb - ethernet@20112000: PHY present at 9 - ethernet@20112000: Starting autonegotiation... - ethernet@20112000: Autonegotiation complete - ethernet@20112000: link up, 1000Mbps full-duplex (lpa: 0x7800) - Using ethernet@20112000 device - TFTP from server 192.168.1.3; our IP address is 192.168.1.5 - Filename 'mpfs-icicle-kit.dtb'. - Load address: 0x82200000 - Loading: # - 2.5 MiB/s - done - Bytes transferred = 10282 (282a hex) - - RISC-V # bootm ${kernel_addr_r} - ${fdt_addr_r} - ## Booting kernel from Legacy Image at 80200000 ... - Image Name: Linux - Image Type: RISC-V Linux Kernel Image (uncompressed) - Data Size: 14482416 Bytes = 13.8 MiB - Load Address: 80200000 - Entry Point: 80200000 - Verifying Checksum ... OK - ## Flattened Device Tree blob at 82200000 - Booting using the fdt blob at 0x82200000 - Loading Kernel Image - Using Device Tree in place at 000000008fffa000, end 000000008ffff829 ... OK - - Starting kernel ... - - [ 0.000000] OF: fdt: Ignoring memory range 0x80000000 - 0x80200000 - [ 0.000000] Linux version 5.6.17 (padmarao@padmarao-VirtualBox) (gcc version 7.2.0 (GCC)) #2 SMP Tue Jun 16 21:27:50 IST 2020 - [ 0.000000] initrd not found or empty - disabling initrd - [ 0.000000] Zone ranges: - [ 0.000000] DMA32 [mem 0x0000000080200000-0x00000000bfffffff] - [ 0.000000] Normal empty - [ 0.000000] Movable zone start for each node - [ 0.000000] Early memory node ranges - [ 0.000000] node 0: [mem 0x0000000080200000-0x00000000bfffffff] - [ 0.000000] Initmem setup node 0 [mem 0x0000000080200000-0x00000000bfffffff] - [ 0.000000] software IO TLB: mapped [mem 0xbb1f5000-0xbf1f5000] (64MB) - [ 0.000000] elf_hwcap is 0x112d - [ 0.000000] percpu: Embedded 14 pages/cpu s24856 r0 d32488 u57344 - [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 258055 - [ 0.000000] Kernel command line: console=ttyS0,115200n8 - [ 0.000000] Dentry cache hash table entries: 131072 (order: 8, 1048576 bytes, linear) - [ 0.000000] Inode-cache hash table entries: 65536 (order: 7, 524288 bytes, linear) - [ 0.000000] Sorting __ex_table... - [ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off - [ 0.000000] Memory: 950308K/1046528K available (3289K kernel code, 212K rwdata, 900K rodata, 9476K init, 250K bss, 96220K reserved, 0K cma-reserved) - [ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=4, Nodes=1 - [ 0.000000] rcu: Hierarchical RCU implementation. - [ 0.000000] rcu: RCU event tracing is enabled. - [ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=8 to nr_cpu_ids=4. - [ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 10 jiffies. - [ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=4 - [ 0.000000] NR_IRQS: 0, nr_irqs: 0, preallocated irqs: 0 - [ 0.000000] plic: mapped 186 interrupts with 4 handlers for 9 contexts. - [ 0.000000] riscv_timer_init_dt: Registering clocksource cpuid [0] hartid [1] - [ 0.000000] clocksource: riscv_clocksource: mask: 0xffffffffffffffff max_cycles: 0x1d854df40, max_idle_ns: 3526361616960 ns - [ 0.000015] sched_clock: 64 bits at 1000kHz, resolution 1000ns, wraps every 2199023255500ns - [ 0.000311] Calibrating delay loop (skipped), value calculated using timer frequency.. 2.00 BogoMIPS (lpj=10000) - [ 0.000349] pid_max: default: 32768 minimum: 301 - [ 0.000846] Mount-cache hash table entries: 2048 (order: 2, 16384 bytes, linear) - [ 0.000964] Mountpoint-cache hash table entries: 2048 (order: 2, 16384 bytes, linear) - [ 0.005630] rcu: Hierarchical SRCU implementation. - [ 0.006901] smp: Bringing up secondary CPUs ... - [ 0.012545] smp: Brought up 1 node, 4 CPUs - [ 0.014431] devtmpfs: initialized - [ 0.020526] random: get_random_bytes called from setup_net+0x36/0x192 with crng_init=0 - [ 0.020928] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 19112604462750000 ns - [ 0.020999] futex hash table entries: 1024 (order: 4, 65536 bytes, linear) - [ 0.022768] NET: Registered protocol family 16 - [ 0.035478] microchip-pfsoc-clkcfg 20002000.clkcfg: Registered PFSOC core clocks - [ 0.048429] SCSI subsystem initialized - [ 0.049694] pps_core: LinuxPPS API ver. 1 registered - [ 0.049719] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti - [ 0.049780] PTP clock support registered - [ 0.051781] clocksource: Switched to clocksource riscv_clocksource - [ 0.055326] NET: Registered protocol family 2 - [ 0.056922] tcp_listen_portaddr_hash hash table entries: 512 (order: 1, 8192 bytes, linear) - [ 0.057053] TCP established hash table entries: 8192 (order: 4, 65536 bytes, linear) - [ 0.057648] TCP bind hash table entries: 8192 (order: 5, 131072 bytes, linear) - [ 0.058579] TCP: Hash tables configured (established 8192 bind 8192) - [ 0.059648] UDP hash table entries: 512 (order: 2, 16384 bytes, linear) - [ 0.059837] UDP-Lite hash table entries: 512 (order: 2, 16384 bytes, linear) - [ 0.060707] NET: Registered protocol family 1 - [ 0.266229] workingset: timestamp_bits=62 max_order=18 bucket_order=0 - [ 0.287107] io scheduler mq-deadline registered - [ 0.287140] io scheduler kyber registered - [ 0.429601] Serial: 8250/16550 driver, 4 ports, IRQ sharing disabled - [ 0.433979] printk: console [ttyS0] disabled - [ 0.434154] 20000000.serial: ttyS0 at MMIO 0x20000000 (irq = 18, base_baud = 9375000) is a 16550A - [ 0.928039] printk: console [ttyS0] enabled - [ 0.939804] libphy: Fixed MDIO Bus: probed - [ 0.948702] libphy: MACB_mii_bus: probed - [ 0.993698] macb 20112000.ethernet eth0: Cadence GEM rev 0x0107010c at 0x20112000 irq 21 (56:34:12:00:fc:00) - [ 1.006751] mousedev: PS/2 mouse device common for all mice - [ 1.013803] i2c /dev entries driver - [ 1.019451] sdhci: Secure Digital Host Controller Interface driver - [ 1.027242] sdhci: Copyright(c) Pierre Ossman - [ 1.032731] sdhci-pltfm: SDHCI platform and OF driver helper - [ 1.091826] mmc0: SDHCI controller on 20008000.sdhc [20008000.sdhc] using ADMA 64-bit - [ 1.102738] NET: Registered protocol family 17 - [ 1.170326] Freeing unused kernel memory: 9476K - [ 1.176067] This architecture does not have kernel memory protection. - [ 1.184157] Run /init as init process - Starting logging: OK - Starting mdev... - /etc/init.d/S10mdev: line 21: can't create /proc/sys/kernel/hotplug: nonexiste[ 1.331981] mmc0: mmc_select_hs200 failed, error -74 - nt directory - [ 1.355011] mmc0: new MMC card at address 0001 - [ 1.363981] mmcblk0: mmc0:0001 DG4008 7.28 GiB - [ 1.372248] mmcblk0boot0: mmc0:0001 DG4008 partition 1 4.00 MiB - [ 1.382292] mmcblk0boot1: mmc0:0001 DG4008 partition 2 4.00 MiB - [ 1.390265] mmcblk0rpmb: mmc0:0001 DG4008 partition 3 4.00 MiB, chardev (251:0) - [ 1.425234] GPT:Primary header thinks Alt. header is not at the end of the disk. - [ 1.434656] GPT:2255809 != 15273599 - [ 1.439038] GPT:Alternate GPT header not at the end of the disk. - [ 1.446671] GPT:2255809 != 15273599 - [ 1.451048] GPT: Use GNU Parted to correct GPT errors. - [ 1.457755] mmcblk0: p1 p2 p3 - sort: /sys/devices/platform/Fixed: No such file or directory - modprobe: can't change directory to '/lib/modules': No such file or directory - Initializing random number generator... [ 2.830198] random: dd: uninitialized urandom read (512 bytes read) - done. - Starting network... - [ 3.061867] macb 20112000.ethernet eth0: PHY [20112000.ethernet-ffffffff:09] driver [Vitesse VSC8662] (irq=POLL) - [ 3.074674] macb 20112000.ethernet eth0: configuring for phy/sgmii link mode - [ 3.084263] pps pps0: new PPS source ptp0 - [ 3.089710] macb 20112000.ethernet: gem-ptp-timer ptp clock registered. - udhcpc (v1.24.2) started - Sending discover... - Sending discover... - [ 6.380169] macb 20112000.ethernet eth0: Link is Up - 1Gbps/Full - flow control tx - Sending discover... - Sending select for 192.168.1.2... - Lease of 192.168.1.2 obtained, lease time 86400 - deleting routers - adding dns 192.168.1.1 - Starting dropbear sshd: [ 11.385619] random: dropbear: uninitialized urandom read (32 bytes read) - OK - - Welcome to Buildroot - buildroot login: root - Password: - # - -Booting U-Boot and Linux from eMMC ----------------------------------- - -FPGA design with HSS programming file and Linux Image -~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ - -https://github.com/polarfire-soc/polarfire-soc-documentation/blob/master/boards/mpfs-icicle-kit-es/updating-icicle-kit/updating-icicle-kit-design-and-linux.md - -The HSS firmware runs from the PolarFire SoC eNVM on reset. - -eMMC -~~~~ - -Program eMMC with payload binary and Linux image is explained in the -PolarFire SoC documentation. -The payload binary should be copied to partition 2 of the eMMC. - -(Note: PolarFire SoC Documentation git repo is at https://github.com/polarfire-soc/polarfire-soc-documentation/blob/master/boards/mpfs-icicle-kit-es/updating-icicle-kit/updating-icicle-kit-design-and-linux.md#eMMC) - -Once the Linux image and payload binary is copied to the eMMC, press CTRL+C -in the HSS command line interface, then type 'boot' and enter to boot the newly -copied payload and Linux image. - -.. code-block:: none - - zcat .wic.gz | sudo dd of=/dev/sdX bs=4096 iflag=fullblock oflag=direct conv=fsync status=progress - - sudo dd if= of=/dev/sdX2 bs=512 - -You should see the U-Boot prompt on UART1. -(Note: UART0 is reserved for HSS) - -GUID type -~~~~~~~~~ - -The HSS always picks up the HSS payload from a GPT partition with -GUID type "21686148-6449-6E6F-744E-656564454649" or sector '0' of the eMMC if no -GPT partition. - -Sample boot log from MPFS Icicle Kit -~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ - -.. code-block:: none - - U-Boot 2021.01-00314-g7303332537-dirty (Jan 14 2021 - 10:09:43 +0530) - - CPU: rv64imafdc - Model: Microchip MPFS Icicle Kit - DRAM: 1 GiB - MMC: sdhc@20008000: 0 - In: serial@20100000 - Out: serial@20100000 - Err: serial@20100000 - Net: eth0: ethernet@20112000 - Hit any key to stop autoboot: 0 - - RISC-V # mmc info - Device: sdhc@20008000 - Manufacturer ID: 45 - OEM: 100 - Name: DG400 - Bus Speed: 52000000 - Mode: MMC High Speed (52MHz) - Rd Block Len: 512 - MMC version 5.1 - High Capacity: Yes - Capacity: 7.3 GiB - Bus Width: 4-bit - Erase Group Size: 512 KiB - HC WP Group Size: 8 MiB - User Capacity: 7.3 GiB WRREL - Boot Capacity: 4 MiB ENH - RPMB Capacity: 4 MiB ENH - - RISC-V # mmc part - Partition Map for MMC device 0 -- Partition Type: EFI - - Part Start LBA End LBA Name - Attributes - Type GUID - Partition GUID - 1 0x00002000 0x0000b031 "boot" - attrs: 0x0000000000000004 - type: ebd0a0a2-b9e5-4433-87c0-68b6b72699c7 - guid: 99ff6a94-f2e7-44dd-a7df-f3a2da106ef9 - 2 0x0000b032 0x0000f031 "primary" - attrs: 0x0000000000000000 - type: 21686148-6449-6e6f-744e-656564454649 - guid: 12006052-e64b-4423-beb0-b956ea00f1ba - 3 0x00010000 0x00226b9f "root" - attrs: 0x0000000000000000 - type: 0fc63daf-8483-4772-8e79-3d69d8477de4 - guid: dd2c5619-2272-4c3c-8dc2-e21942e17ce6 - - RISC-V # load mmc 0 ${ramdisk_addr_r} fitimage - RISC-V # bootm ${ramdisk_addr_r} - ## Loading kernel from FIT Image at 88300000 ... - Using 'conf@microchip_icicle-kit-es-a000-microchip.dtb' configuration - Trying 'kernel@1' kernel subimage - Description: Linux kernel - Type: Kernel Image - Compression: gzip compressed - Data Start: 0x883000fc - Data Size: 3574555 Bytes = 3.4 MiB - Architecture: RISC-V - OS: Linux - Load Address: 0x80200000 - Entry Point: 0x80200000 - Hash algo: sha256 - Hash value: 21f18d72cf2f0a7192220abb577ad25c77c26960052d779aa02bf55dbf0a6403 - Verifying Hash Integrity ... sha256+ OK - ## Loading fdt from FIT Image at 88300000 ... - Using 'conf@microchip_icicle-kit-es-a000-microchip.dtb' configuration - Trying 'fdt@microchip_icicle-kit-es-a000-microchip.dtb' fdt subimage - Description: Flattened Device Tree blob - Type: Flat Device Tree - Compression: uncompressed - Data Start: 0x88668d44 - Data Size: 9760 Bytes = 9.5 KiB - Architecture: RISC-V - Load Address: 0x82200000 - Hash algo: sha256 - Hash value: 5c3a9f30d41b6b8e53b47916e1f339b3a4d454006554d1f7e1f552ed62409f4b - Verifying Hash Integrity ... sha256+ OK - Loading fdt from 0x88668d48 to 0x82200000 - Booting using the fdt blob at 0x82200000 - Uncompressing Kernel Image - Loading Device Tree to 000000008fffa000, end 000000008ffff61f ... OK - - Starting kernel ... - - [ 0.000000] OF: fdt: Ignoring memory range 0x80000000 - 0x80200000 - [ 0.000000] Linux version 5.6.16 (oe-user@oe-host) (gcc version 9.3.0 (GCC)) #1 SMP Fri Oct 9 11:49:47 UTC 2020 - [ 0.000000] earlycon: sbi0 at I/O port 0x0 (options '') - [ 0.000000] printk: bootconsole [sbi0] enabled - [ 0.000000] Zone ranges: - [ 0.000000] DMA32 [mem 0x0000000080200000-0x00000000bfffffff] - [ 0.000000] Normal empty - [ 0.000000] Movable zone start for each node - [ 0.000000] Early memory node ranges - [ 0.000000] node 0: [mem 0x0000000080200000-0x00000000bfffffff] - [ 0.000000] Zeroed struct page in unavailable ranges: 512 pages - [ 0.000000] Initmem setup node 0 [mem 0x0000000080200000-0x00000000bfffffff] - [ 0.000000] software IO TLB: mapped [mem 0xb9e00000-0xbde00000] (64MB) - [ 0.000000] CPU with hartid=0 is not available - [ 0.000000] CPU with hartid=0 is not available - [ 0.000000] elf_hwcap is 0x112d - [ 0.000000] percpu: Embedded 17 pages/cpu s29784 r8192 d31656 u69632 - [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 258055 - [ 0.000000] Kernel command line: earlycon=sbi root=/dev/mmcblk0p3 rootwait console=ttyS0,115200n8 uio_pdrv_genirq.of_id=generic-uio - [ 0.000000] Dentry cache hash table entries: 131072 (order: 8, 1048576 bytes, linear) - [ 0.000000] Inode-cache hash table entries: 65536 (order: 7, 524288 bytes, linear) - [ 0.000000] Sorting __ex_table... - [ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off - [ 0.000000] Memory: 941440K/1046528K available (4118K kernel code, 280K rwdata, 1687K rodata, 169K init, 273K bss, 105088K reserved, 0K cma-reserved) - [ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=4, Nodes=1 - [ 0.000000] rcu: Hierarchical RCU implementation. - [ 0.000000] rcu: RCU event tracing is enabled. - [ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=5 to nr_cpu_ids=4. - [ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 10 jiffies. - [ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=4 - [ 0.000000] NR_IRQS: 0, nr_irqs: 0, preallocated irqs: 0 - [ 0.000000] plic: mapped 53 interrupts with 4 handlers for 9 contexts. - [ 0.000000] riscv_timer_init_dt: Registering clocksource cpuid [0] hartid [1] - [ 0.000000] clocksource: riscv_clocksource: mask: 0xffffffffffffffff max_cycles: 0x1d854df40, max_idle_ns: 3526361616960 ns - [ 0.000015] sched_clock: 64 bits at 1000kHz, resolution 1000ns, wraps every 2199023255500ns - [ 0.008679] Console: colour dummy device 80x25 - [ 0.013112] Calibrating delay loop (skipped), value calculated using timer frequency.. 2.00 BogoMIPS (lpj=10000) - [ 0.023368] pid_max: default: 32768 minimum: 301 - [ 0.028314] Mount-cache hash table entries: 2048 (order: 2, 16384 bytes, linear) - [ 0.035766] Mountpoint-cache hash table entries: 2048 (order: 2, 16384 bytes, linear) - [ 0.047099] rcu: Hierarchical SRCU implementation. - [ 0.052813] smp: Bringing up secondary CPUs ... - [ 0.061581] smp: Brought up 1 node, 4 CPUs - [ 0.067069] devtmpfs: initialized - [ 0.073621] random: get_random_u32 called from bucket_table_alloc.isra.0+0x4e/0x150 with crng_init=0 - [ 0.074409] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 19112604462750000 ns - [ 0.093399] futex hash table entries: 1024 (order: 4, 65536 bytes, linear) - [ 0.101879] NET: Registered protocol family 16 - [ 0.110336] microchip-pfsoc-clkcfg 20002000.clkcfg: Registered PFSOC core clocks - [ 0.132717] usbcore: registered new interface driver usbfs - [ 0.138225] usbcore: registered new interface driver hub - [ 0.143813] usbcore: registered new device driver usb - [ 0.148939] pps_core: LinuxPPS API ver. 1 registered - [ 0.153929] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti - [ 0.163071] PTP clock support registered - [ 0.168521] clocksource: Switched to clocksource riscv_clocksource - [ 0.174927] VFS: Disk quotas dquot_6.6.0 - [ 0.179016] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes) - [ 0.205536] NET: Registered protocol family 2 - [ 0.210944] tcp_listen_portaddr_hash hash table entries: 512 (order: 1, 8192 bytes, linear) - [ 0.219393] TCP established hash table entries: 8192 (order: 4, 65536 bytes, linear) - [ 0.227497] TCP bind hash table entries: 8192 (order: 5, 131072 bytes, linear) - [ 0.235440] TCP: Hash tables configured (established 8192 bind 8192) - [ 0.242537] UDP hash table entries: 512 (order: 2, 16384 bytes, linear) - [ 0.249285] UDP-Lite hash table entries: 512 (order: 2, 16384 bytes, linear) - [ 0.256690] NET: Registered protocol family 1 - [ 0.262585] workingset: timestamp_bits=62 max_order=18 bucket_order=0 - [ 0.281036] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 249) - [ 0.288481] io scheduler mq-deadline registered - [ 0.292983] io scheduler kyber registered - [ 0.298895] microsemi,mss-gpio 20122000.gpio: Microsemi MSS GPIO registered 32 GPIOs - [ 0.453723] Serial: 8250/16550 driver, 4 ports, IRQ sharing disabled - [ 0.462911] printk: console [ttyS0] disabled - [ 0.467216] 20100000.serial: ttyS0 at MMIO 0x20100000 (irq = 12, base_baud = 9375000) is a 16550A - [ 0.476201] printk: console [ttyS0] enabled - [ 0.476201] printk: console [ttyS0] enabled - [ 0.484576] printk: bootconsole [sbi0] disabled - [ 0.484576] printk: bootconsole [sbi0] disabled - [ 0.494920] 20102000.serial: ttyS1 at MMIO 0x20102000 (irq = 13, base_baud = 9375000) is a 16550A - [ 0.505068] 20104000.serial: ttyS2 at MMIO 0x20104000 (irq = 14, base_baud = 9375000) is a 16550A - [ 0.533336] loop: module loaded - [ 0.572284] Rounding down aligned max_sectors from 4294967295 to 4294967288 - [ 0.580000] db_root: cannot open: /etc/target - [ 0.585413] libphy: Fixed MDIO Bus: probed - [ 0.591526] libphy: MACB_mii_bus: probed - [ 0.598060] macb 20112000.ethernet eth0: Cadence GEM rev 0x0107010c at 0x20112000 irq 17 (56:34:12:00:fc:00) - [ 0.608352] ehci_hcd: USB 2.0 'Enhanced' Host Controller (EHCI) Driver - [ 0.615001] ehci-platform: EHCI generic platform driver - [ 0.620446] ohci_hcd: USB 1.1 'Open' Host Controller (OHCI) Driver - [ 0.626632] ohci-platform: OHCI generic platform driver - [ 0.632326] usbcore: registered new interface driver cdc_acm - [ 0.637996] cdc_acm: USB Abstract Control Model driver for USB modems and ISDN adapters - [ 0.646459] i2c /dev entries driver - [ 0.650852] microsemi-mss-i2c 2010b000.i2c: Microsemi I2C Probe Complete - [ 0.658010] sdhci: Secure Digital Host Controller Interface driver - [ 0.664326] sdhci: Copyright(c) Pierre Ossman - [ 0.668754] sdhci-pltfm: SDHCI platform and OF driver helper - [ 0.706845] mmc0: SDHCI controller on 20008000.sdhc [20008000.sdhc] using ADMA 64-bit - [ 0.715052] usbcore: registered new interface driver usbhid - [ 0.720722] usbhid: USB HID core driver - [ 0.725174] pac193x 0-0010: Chip revision: 0x03 - [ 0.733339] pac193x 0-0010: :pac193x_prep_iio_channels: Channel 0 active - [ 0.740127] pac193x 0-0010: :pac193x_prep_iio_channels: Channel 1 active - [ 0.746881] pac193x 0-0010: :pac193x_prep_iio_channels: Channel 2 active - [ 0.753686] pac193x 0-0010: :pac193x_prep_iio_channels: Channel 3 active - [ 0.760495] pac193x 0-0010: :pac193x_prep_iio_channels: Active chip channels: 25 - [ 0.778006] NET: Registered protocol family 10 - [ 0.784929] Segment Routing with IPv6 - [ 0.788875] sit: IPv6, IPv4 and MPLS over IPv4 tunneling driver - [ 0.795743] NET: Registered protocol family 17 - [ 0.801191] hctosys: unable to open rtc device (rtc0) - [ 0.807774] Waiting for root device /dev/mmcblk0p3... - [ 0.858506] mmc0: mmc_select_hs200 failed, error -74 - [ 0.865764] mmc0: new MMC card at address 0001 - [ 0.872564] mmcblk0: mmc0:0001 DG4008 7.28 GiB - [ 0.878777] mmcblk0boot0: mmc0:0001 DG4008 partition 1 4.00 MiB - [ 0.886182] mmcblk0boot1: mmc0:0001 DG4008 partition 2 4.00 MiB - [ 0.892633] mmcblk0rpmb: mmc0:0001 DG4008 partition 3 4.00 MiB, chardev (247:0) - [ 0.919029] GPT:Primary header thinks Alt. header is not at the end of the disk. - [ 0.926448] GPT:2255841 != 15273599 - [ 0.930019] GPT:Alternate GPT header not at the end of the disk. - [ 0.936029] GPT:2255841 != 15273599 - [ 0.939583] GPT: Use GNU Parted to correct GPT errors. - [ 0.944800] mmcblk0: p1 p2 p3 - [ 0.966696] EXT4-fs (mmcblk0p3): INFO: recovery required on readonly filesystem - [ 0.974105] EXT4-fs (mmcblk0p3): write access will be enabled during recovery - [ 1.052362] random: fast init done - [ 1.057961] EXT4-fs (mmcblk0p3): recovery complete - [ 1.065734] EXT4-fs (mmcblk0p3): mounted filesystem with ordered data mode. Opts: (null) - [ 1.074002] VFS: Mounted root (ext4 filesystem) readonly on device 179:3. - [ 1.081654] Freeing unused kernel memory: 168K - [ 1.086108] This architecture does not have kernel memory protection. - [ 1.092629] Run /sbin/init as init process - [ 1.702217] systemd[1]: System time before build time, advancing clock. - [ 1.754192] systemd[1]: systemd 244.3+ running in system mode. (+PAM -AUDIT -SELINUX +IMA -APPARMOR -SMACK +SYSVINIT +UTMP -LIBCRYPTSETUP -GCRYPT -GNUTLS +ACL +XZ -LZ4 -SECCOMP +BLKID -ELFUTILS +KMOD -IDN2 -IDN -PCRE2 default-hierarchy=hybrid) - [ 1.776361] systemd[1]: Detected architecture riscv64. - - Welcome to OpenEmbedded nodistro.0! - - [ 1.829651] systemd[1]: Set hostname to . - [ 2.648597] random: systemd: uninitialized urandom read (16 bytes read) - [ 2.657485] systemd[1]: Created slice system-getty.slice. - [ OK ] Created slice system-getty.slice. - [ 2.698779] random: systemd: uninitialized urandom read (16 bytes read) - [ 2.706317] systemd[1]: Created slice system-serial\x2dgetty.slice. - [ OK ] Created slice system-serial\x2dgetty.slice. - [ 2.748716] random: systemd: uninitialized urandom read (16 bytes read) - [ 2.756098] systemd[1]: Created slice User and Session Slice. - [ OK ] Created slice User and Session Slice. - [ 2.789065] systemd[1]: Started Dispatch Password Requests to Console Directory Watch. - [ OK ] Started Dispatch Password …ts to Console Directory Watch. - [ 2.828974] systemd[1]: Started Forward Password Requests to Wall Directory Watch. - [ OK ] Started Forward Password R…uests to Wall Directory Watch. - [ 2.869009] systemd[1]: Reached target Paths. - [ OK ] Reached target Paths. - [ 2.898808] systemd[1]: Reached target Remote File Systems. - [ OK ] Reached target Remote File Systems. - [ 2.938771] systemd[1]: Reached target Slices. - [ OK ] Reached target Slices. - [ 2.968754] systemd[1]: Reached target Swap. - [ OK ] Reached target Swap. - [ 2.999283] systemd[1]: Listening on initctl Compatibility Named Pipe. - [ OK ] Listening on initctl Compatibility Named Pipe. - [ 3.060458] systemd[1]: Condition check resulted in Journal Audit Socket being skipped. - [ 3.069826] systemd[1]: Listening on Journal Socket (/dev/log). - [ OK ] Listening on Journal Socket (/dev/log). - [ 3.109601] systemd[1]: Listening on Journal Socket. - [ OK ] Listening on Journal Socket. - [ 3.149868] systemd[1]: Listening on Network Service Netlink Socket. - [ OK ] Listening on Network Service Netlink Socket. - [ 3.189419] systemd[1]: Listening on udev Control Socket. - [ OK ] Listening on udev Control Socket. - [ 3.229179] systemd[1]: Listening on udev Kernel Socket. - [ OK ] Listening on udev Kernel Socket. - [ 3.269520] systemd[1]: Condition check resulted in Huge Pages File System being skipped. - [ 3.278477] systemd[1]: Condition check resulted in POSIX Message Queue File System being skipped. - [ 3.288200] systemd[1]: Condition check resulted in Kernel Debug File System being skipped. - [ 3.302570] systemd[1]: Mounting Temporary Directory (/tmp)... - Mounting Temporary Directory (/tmp)... - [ 3.339226] systemd[1]: Condition check resulted in Create list of static device nodes for the current kernel being skipped. - [ 3.355883] systemd[1]: Starting File System Check on Root Device... - Starting File System Check on Root Device... - [ 3.407220] systemd[1]: Starting Journal Service... - Starting Journal Service... - [ 3.422441] systemd[1]: Condition check resulted in Load Kernel Modules being skipped. - [ 3.431770] systemd[1]: Condition check resulted in FUSE Control File System being skipped. - [ 3.446415] systemd[1]: Mounting Kernel Configuration File System... - Mounting Kernel Configuration File System... - [ 3.458983] systemd[1]: Starting Apply Kernel Variables... - Starting Apply Kernel Variables... - [ 3.471368] systemd[1]: Starting udev Coldplug all Devices... - Starting udev Coldplug all Devices... - [ 3.491071] systemd[1]: Mounted Temporary Directory (/tmp). - [ OK 3.498114] systemd[1]: Mounted Kernel Configuration File System. - 0m] Mounted Temporary Directory (/tmp). - [ OK ] Mounted Kernel Configuration File System. - [ 3.550853] systemd[1]: Started Apply Kernel Variables. - [ OK 3.557535] systemd[1]: Started Journal Service. - 0m] Started Apply Kernel Variables. - [ OK ] Started Journal Service. - [ OK ] Started udev Coldplug all Devices. - [ OK ] Started File System Check on Root Device. - Starting Remount Root and Kernel File Systems... - [ 8.133469] EXT4-fs (mmcblk0p3): re-mounted. Opts: (null) - [ OK ] Started Remount Root and Kernel File Systems. - Starting Flush Journal to Persistent Storage... - [ 8.215327] systemd-journald[77]: Received client request to flush runtime journal. - Starting Create Static Device Nodes in /dev... - [ OK ] Started Flush Journal to Persistent Storage. - [ OK ] Started Create Static Device Nodes in /dev. - [ OK ] Reached target Local File Systems (Pre). - Mounting /var/volatile... - Starting udev Kernel Device Manager... - [ OK ] Mounted /var/volatile. - Starting Load/Save Random Seed... - [ OK ] Reached target Local File Systems. - Starting Create Volatile Files and Directories... - [ OK ] Started udev Kernel Device Manager. - [ OK ] Started Create Volatile Files and Directories. - Starting Network Time Synchronization... - Starting Update UTMP about System Boot/Shutdown... - [ OK ] Started Update UTMP about System Boot/Shutdown. - [ OK ] Started Network Time Synchronization. - [ 11.618575] random: crng init done - [ 11.622007] random: 7 urandom warning(s) missed due to ratelimiting - [ OK ] Started Load/Save Random Seed. - [ OK ] Reached target System Initialization. - [ OK ] Started Daily Cleanup of Temporary Directories. - [ OK ] Reached target System Time Set. - [ OK ] Reached target System Time Synchronized. - [ OK ] Reached target Timers. - [ OK ] Listening on D-Bus System Message Bus Socket. - [ OK ] Listening on dropbear.socket. - [ OK ] Reached target Sockets. - [ OK ] Reached target Basic System. - [ OK ] Started D-Bus System Message Bus. - Starting IPv6 Packet Filtering Framework... - Starting IPv4 Packet Filtering Framework... - Starting Login Service... - [ OK ] Started IPv6 Packet Filtering Framework. - [ OK ] Started IPv4 Packet Filtering Framework. - [ OK ] Reached target Network (Pre). - Starting Network Service... - [ OK ] Started Login Service. - [ 12.602455] macb 20112000.ethernet eth0: PHY [20112000.ethernet-ffffffff:09] driver [Vitesse VSC8662] (irq=POLL) - [ 12.612795] macb 20112000.ethernet eth0: configuring for phy/sgmii link mode - [ 12.622153] pps pps0: new PPS source ptp0 - [ OK 12.626725] macb 20112000.ethernet: gem-ptp-timer ptp clock registered. - 0m] Started Network Service. - Starting Network Name Resolution... - [ OK ] Started Network Name Resolution. - [ OK ] Reached target Network. - [ OK ] Reached target Host and Network Name Lookups. - [ OK ] Started Collectd. - [ OK ] Started Collectd. - Starting Permit User Sessions... - [ OK ] Started Permit User Sessions. - [ OK ] Started Getty on tty1. - [ OK ] Started Serial Getty on ttyS0. - [ OK ] Reached target Login Prompts. - [ OK ] Reached target Multi-User System. - Starting Update UTMP about System Runlevel Changes... - [ OK ] Started Update UTMP about System Runlevel Changes. - - OpenEmbedded nodistro.0 icicle-kit-es ttyS0 - - icicle-kit-es login: [ 15.795564] macb 20112000.ethernet eth0: Link is Up - 1Gbps/Full - flow control tx - [ 15.803306] IPv6: ADDRCONF(NETDEV_CHANGE): eth0: link becomes ready - - icicle-kit-es login: root - root@icicle-kit-es:~# +.. include:: mpfs_common.rst -- cgit v1.2.3 From 39eda3f037d8551511dedee33caa3347a1dd0269 Mon Sep 17 00:00:00 2001 From: Jamie Gibbons Date: Tue, 2 Sep 2025 11:11:01 +0100 Subject: doc: microchip: add mpfs_video.rst Add documentation to support the addition of the MPFS Video Kit. Signed-off-by: Jamie Gibbons Reviewed-by: Leo Yu-Chi Liang --- doc/board/microchip/index.rst | 1 + doc/board/microchip/mpfs_video.rst | 105 +++++++++++++++++++++++++++++++++++++ 2 files changed, 106 insertions(+) create mode 100644 doc/board/microchip/mpfs_video.rst diff --git a/doc/board/microchip/index.rst b/doc/board/microchip/index.rst index affc5a9e014..571b8877f08 100644 --- a/doc/board/microchip/index.rst +++ b/doc/board/microchip/index.rst @@ -7,3 +7,4 @@ Microchip :maxdepth: 2 mpfs_icicle + mpfs_video diff --git a/doc/board/microchip/mpfs_video.rst b/doc/board/microchip/mpfs_video.rst new file mode 100644 index 00000000000..25df63ff14b --- /dev/null +++ b/doc/board/microchip/mpfs_video.rst @@ -0,0 +1,105 @@ +.. SPDX-License-Identifier: GPL-2.0+ + +Microchip PolarFire SoC Video Kit +================================== + +RISC-V PolarFire SoC +-------------------- + +The PolarFire SoC is the 4+1 64-bit RISC-V SoC from Microchip. + +The Video Kit development platform is based on PolarFire SoC and capable +of running Linux. + +Mainline support +---------------- + +The support for following drivers are already enabled: + +1. NS16550 UART Driver. +2. Microchip Clock Driver. +3. Cadence MACB ethernet driver for networking support. +4. Cadence MMC Driver for eMMC/SD support. +5. Microchip I2C Driver. + +.. include:: mpfs_build_boot.rst + +Microchip boot-flow +~~~~~~~~~~~~~~~~~~~ + +HSS with OpenSBI (M-Mode) -> U-Boot (S-Mode) -> Linux (S-Mode) + +Build the HSS (Hart Software Services) - Microchip boot-flow +'''''''''''''''''''''''''''''''''''''''''''''''''''''''''''' + +(Note: HSS git repo is at https://github.com/polarfire-soc/hart-software-services) + +1. Configure + +.. code-block:: none + + make BOARD=mpfs-video-kit config + +Alternatively, copy the default config for Microchip boot-flow. + +.. code-block:: none + + cp boards/mpfs-video-kit/def_config .config + +2. make BOARD=mpfs-video-kit +3. In the Default subdirectory, the standard build will create hss.elf and + various binary formats (hss.hex and hss.bin). + +The FPGA design will use the hss.hex or hss.bin. + +.. include:: mpfs_design_hss.rst + +Custom boot-flow +~~~~~~~~~~~~~~~~ + +HSS without OpenSBI (M-Mode) -> OpenSBI (M-Mode) -> U-Boot (S-Mode) -> Linux (S-Mode) + +Build OpenSBI +''''''''''''' + +1. Get the OpenSBI source + +.. code-block:: none + + git clone https://github.com/riscv/opensbi.git + cd opensbi + +2. Build + +.. code-block:: none + + make PLATFORM=generic FW_PAYLOAD_PATH=/u-boot.bin + FW_FDT_PATH=/dts/upstream/src/riscv/microchip/mpfs-sev-kit-.dtb + +3. Output "fw_payload.bin" file available at + "/build/platform/generic/firmware/fw_payload.bin" + +Build the HSS (Hart Software Services)- Custom boot-flow +'''''''''''''''''''''''''''''''''''''''''''''''''''''''' + +(Note: HSS git repo is at https://github.com/polarfire-soc/hart-software-services) + +1. Configure + +.. code-block:: none + + make BOARD=mpfs-video-kit config + +Alternatively, copy the default custom config for Custom boot-flow. + +.. code-block:: none + + cp boards/mpfs-video-kit/def_config_custom .config + +2. make BOARD=mpfs-video-kit +3. In the Default subdirectory, the standard build will create hss.elf and + various binary formats (hss.hex and hss.bin). + +The FPGA design will use the hss.hex or hss.bin. + +.. include:: mpfs_common.rst -- cgit v1.2.3 From 7fa1ee7fb99fe36ba512dc221ce77fef9d01cc98 Mon Sep 17 00:00:00 2001 From: Jamie Gibbons Date: Tue, 2 Sep 2025 11:11:02 +0100 Subject: misc: mpfs_syscontroller: add functions to read device tree overlays Include functions to use the system controller to read the device tree overlays which supports auto update functionality. Signed-off-by: Jamie Gibbons Reviewed-by: Leo Yu-Chi Liang --- drivers/misc/mpfs_syscontroller.c | 200 ++++++++++++++++++++++++++++++++++++++ 1 file changed, 200 insertions(+) diff --git a/drivers/misc/mpfs_syscontroller.c b/drivers/misc/mpfs_syscontroller.c index 41e80815ab5..f608d5518b0 100644 --- a/drivers/misc/mpfs_syscontroller.c +++ b/drivers/misc/mpfs_syscontroller.c @@ -22,7 +22,27 @@ #include #include +#define SYS_SPI_CMD 0x50 +#define SYS_SPI_MAILBOX_DATA_LEN 17 +#define SYS_SPI_MAILBOX_SRC_OFFSET 8 +#define SYS_SPI_MAILBOX_LENGTH_OFFSET 12 +#define SYS_SPI_MAILBOX_FREQ_OFFSET 16 +#define SYS_SPI_MAILBOX_FREQ 3 +#define SPI_FLASH_ADDR 0x400 + /* Descriptor table */ +#define START_OFFSET 4 +#define END_OFFSET 8 +#define SIZE_OFFSET 12 +#define DESC_NEXT 12 +#define DESC_RESERVED_SIZE 0 +#define DESC_SIZE 16 + +#define DESIGN_MAGIC_0 0x4d /* 'M' */ +#define DESIGN_MAGIC_1 0x43 /* 'C'*/ +#define DESIGN_MAGIC_2 0x48 /* 'H'*/ +#define DESIGN_MAGIC_3 0x50 /* 'P'*/ + #define CMD_OPCODE 0x0u #define CMD_DATA_SIZE 0U #define CMD_DATA NULL @@ -109,6 +129,186 @@ int mpfs_syscontroller_read_sernum(struct mpfs_sys_serv *sys_serv_priv, u8 *devi } EXPORT_SYMBOL(mpfs_syscontroller_read_sernum); +static u16 mpfs_syscontroller_service_spi_copy(struct mpfs_sys_serv *sys_serv_priv, u64 dst_addr, u32 src_addr, u32 length) +{ + int ret; + u32 mailbox_format[SYS_SPI_MAILBOX_DATA_LEN]; + + *(u64 *)mailbox_format = dst_addr; + mailbox_format[SYS_SPI_MAILBOX_SRC_OFFSET/4] = src_addr; + mailbox_format[SYS_SPI_MAILBOX_LENGTH_OFFSET/4] = length; + mailbox_format[SYS_SPI_MAILBOX_FREQ_OFFSET/4] = SYS_SPI_MAILBOX_FREQ; + + struct mpfs_mss_response response = { + .resp_status = 0U, + .resp_msg = mailbox_format, + .resp_size = RESP_BYTES}; + struct mpfs_mss_msg msg = { + .cmd_opcode = SYS_SPI_CMD, + .cmd_data_size = SYS_SPI_MAILBOX_DATA_LEN, + .response = &response, + .cmd_data = (u8 *)mailbox_format, + .mbox_offset = MBOX_OFFSET, + .resp_offset = RESP_OFFSET}; + + ret = mpfs_syscontroller_run_service(sys_serv_priv->sys_controller, &msg); + if (ret) { + dev_err(sys_serv_priv->sys_controller->chan.dev, "Service failed: %d, abort. Failure: %u\n", ret, msg.response->resp_status); + } + + return ret; +} + +static u16 mpfs_syscontroller_get_dtbo_desc_header(struct mpfs_sys_serv *sys_serv_priv, u8 *desc_data, u32 desc_addr) +{ + u32 length, no_of_descs; + int ret = -ENOENT; + + /* Get first four bytes to calculate length */ + ret = mpfs_syscontroller_service_spi_copy(sys_serv_priv, (u64)desc_data, desc_addr, BYTES_4); + if (!ret) { + no_of_descs = *((u32 *)desc_data); + if (no_of_descs) { + length = DESC_SIZE + ((no_of_descs - 1) * DESC_SIZE); + ret = mpfs_syscontroller_service_spi_copy(sys_serv_priv, (u64)desc_data, desc_addr, + length); + } + } + + return ret; +} + +static u8 *mpfs_syscontroller_get_dtbo(struct mpfs_sys_serv *sys_serv_priv, u32 start_addr, u32 size) +{ + int ret; + u8 *dtbo; + + /* Intentionally never freed, even on success so that u-boot "userspace" can access it. */ + dtbo = (u8 *)malloc(size); + + ret = mpfs_syscontroller_service_spi_copy(sys_serv_priv, (u64)dtbo, start_addr, size); + if (ret) { + free(dtbo); + dtbo = NULL; + } + + return dtbo; +} + +static void mpfs_syscontroller_parse_desc_header(struct mpfs_sys_serv *sys_serv_priv, u8 *desc_header, u8 *no_of_dtbo, u32 *dtbos_size) +{ + u32 dtbo_desc_start_addr; + u32 dtbo_desc_size; + u32 no_of_descs; + u16 i; + u8 dtbo_name[16]; + u8 dtbo_addr[20]; + u8 *desc; + u8 *dtbo; + + no_of_descs = *((u32 *)desc_header); + + for (i = 0; i < no_of_descs; i++) { + desc = &desc_header[START_OFFSET + (DESC_NEXT * i)]; + /* + * The dtbo info structure contains addresses that are relative + * to the start of structure, so the offset of the structure in + * flash must be added to get the actual start address. + */ + dtbo_desc_start_addr = *((u32 *)desc) + SPI_FLASH_ADDR; + + desc = &desc_header[SIZE_OFFSET + (DESC_NEXT * i)]; + dtbo_desc_size = *((u32 *)desc); + + dtbo = mpfs_syscontroller_get_dtbo(sys_serv_priv, dtbo_desc_start_addr, dtbo_desc_size); + if (dtbo) { + sprintf(dtbo_name, "dtbo_image%d", *no_of_dtbo); + sprintf(dtbo_addr, "0x%llx", (u64)dtbo); + env_set(dtbo_name, dtbo_addr); + ++*no_of_dtbo; + *dtbos_size += dtbo_desc_size; + } + } +} + +void mpfs_syscontroller_process_dtbo(struct mpfs_sys_serv *sys_serv_priv) +{ + u32 desc_length; + u32 dtbo_desc_addr; + u32 dtbo_addr[5]; + u16 i, hart, no_of_harts; + u8 design_info_desc[256]; + u8 dtbo_desc_data[256]; + u8 no_of_dtbos[8]; + u8 dtbo_size[8]; + u8 *desc; + u8 no_of_dtbo = 0; + u32 dtbos_size = 0; + int ret; + + /* Read first 10 bytes to verify the descriptor is found or not */ + ret = mpfs_syscontroller_service_spi_copy(sys_serv_priv, (u64)design_info_desc, SPI_FLASH_ADDR, 10); + if (ret) { + sprintf(no_of_dtbos, "%d", no_of_dtbo); + env_set("no_of_overlays", no_of_dtbos); + sprintf(dtbo_size, "%d", dtbos_size); + env_set("dtbo_size", dtbo_size); + return; + } + + if (design_info_desc[0] != DESIGN_MAGIC_0 || + design_info_desc[1] != DESIGN_MAGIC_1 || + design_info_desc[2] != DESIGN_MAGIC_2 || + design_info_desc[3] != DESIGN_MAGIC_3) { + dev_dbg(sys_serv_priv->dev, "magic not found in desc structure.\n"); + sprintf(no_of_dtbos, "%d", no_of_dtbo); + env_set("no_of_overlays", no_of_dtbos); + sprintf(dtbo_size, "%d", dtbos_size); + env_set("dtbo_size", dtbo_size); + return; + } + desc_length = *((u32 *)&design_info_desc[4]); + /* Read Design descriptor */ + ret = mpfs_syscontroller_service_spi_copy(sys_serv_priv, (u64)design_info_desc, + SPI_FLASH_ADDR, desc_length); + if (ret) + return; + + no_of_harts = *((u16 *)&design_info_desc[10]); + + for (hart = 0; hart < no_of_harts; hart++) { + /* Start address of DTBO descriptor */ + desc = &design_info_desc[(0x4 * hart) + 0xc]; + + dtbo_desc_addr = *((u32 *)desc); + dtbo_addr[hart] = dtbo_desc_addr; + + if (!dtbo_addr[hart]) + continue; + + for (i = 0; i < hart; i++) { + if (dtbo_addr[hart] == dtbo_addr[i]) + continue; + } + + if (hart && hart == i) + continue; + + dtbo_desc_addr += SPI_FLASH_ADDR; + ret = mpfs_syscontroller_get_dtbo_desc_header(sys_serv_priv, dtbo_desc_data, + dtbo_desc_addr); + if (ret) + continue; + else + mpfs_syscontroller_parse_desc_header(sys_serv_priv, dtbo_desc_data, &no_of_dtbo, &dtbos_size); + } + sprintf(no_of_dtbos, "%d", no_of_dtbo); + env_set("no_of_overlays", no_of_dtbos); + sprintf(dtbo_size, "%d", dtbos_size); + env_set("dtbo_size", dtbo_size); +} +EXPORT_SYMBOL(mpfs_syscontroller_process_dtbo); + static int mpfs_syscontroller_probe(struct udevice *dev) { struct mpfs_syscontroller_priv *sys_controller = dev_get_priv(dev); -- cgit v1.2.3 From 41e5a6520b125265f8010f958bb6eef050c08c92 Mon Sep 17 00:00:00 2001 From: Jamie Gibbons Date: Tue, 2 Sep 2025 11:11:03 +0100 Subject: board: microchip: mpfs_generic: include processing of dtbos Include the use of the process dtbo functionality added in the MPFS system controller driver. Signed-off-by: Jamie Gibbons Reviewed-by: Leo Yu-Chi Liang --- board/microchip/mpfs_generic/mpfs_generic.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/board/microchip/mpfs_generic/mpfs_generic.c b/board/microchip/mpfs_generic/mpfs_generic.c index 739a9b6cd76..fac4b6aecba 100644 --- a/board/microchip/mpfs_generic/mpfs_generic.c +++ b/board/microchip/mpfs_generic/mpfs_generic.c @@ -172,6 +172,8 @@ int board_late_init(void) } } + mpfs_syscontroller_process_dtbo(sys_serv_priv); + return 0; } -- cgit v1.2.3 From 133c6acdaca4d2cfc142600e34f7390a179b4f30 Mon Sep 17 00:00:00 2001 From: Eoin Dickson Date: Tue, 9 Sep 2025 18:23:47 +0530 Subject: gpio: mpfs_gpio: fix compilation warnings mchp_gpio_get_value() should return int instead of bool, and some casts are needed. Signed-off-by: Eoin Dickson Reviewed-by: Leo Yu-Chi Liang --- drivers/gpio/mpfs_gpio.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/drivers/gpio/mpfs_gpio.c b/drivers/gpio/mpfs_gpio.c index 9bbeada4ef5..35eed596c10 100644 --- a/drivers/gpio/mpfs_gpio.c +++ b/drivers/gpio/mpfs_gpio.c @@ -75,7 +75,7 @@ static int mchp_gpio_direction_output(struct udevice *dev, u32 offset, int value return 0; } -static bool mchp_gpio_get_value(struct udevice *dev, u32 offset) +static int mchp_gpio_get_value(struct udevice *dev, u32 offset) { struct mchp_gpio_plat *plat = dev_get_plat(dev); struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev); @@ -136,7 +136,7 @@ static int mchp_gpio_probe(struct udevice *dev) struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev); char name[18], *str; - plat->regs = dev_get_driver_data(dev); + plat->regs = (struct mpfs_gpio_reg_offsets *)dev_get_driver_data(dev); sprintf(name, "gpio@%4lx_", (uintptr_t)plat->base); str = strdup(name); if (!str) @@ -160,10 +160,10 @@ static const struct mpfs_gpio_reg_offsets coregpio_reg_offsets = { static const struct udevice_id mchp_gpio_match[] = { { .compatible = "microchip,mpfs-gpio", - .data = &mpfs_reg_offsets, + .data = (unsigned long)&mpfs_reg_offsets, }, { .compatible = "microchip,coregpio-rtl-v3", - .data = &coregpio_reg_offsets, + .data = (unsigned long)&coregpio_reg_offsets, }, { /* end of list */ } }; -- cgit v1.2.3 From 62f1afbe7a8ae8f8b9e85c5ea4eb446b97892a7c Mon Sep 17 00:00:00 2001 From: Vivian Wang Date: Mon, 15 Sep 2025 07:45:49 +0800 Subject: riscv: qemu: Remove fdt_high default Setting fdt_high to all ones is discouraged and does not appear to be useful for RISC-V QEMU. Moreover, it causes a boot failure when the FDT generated internally by QEMU is used while booting. Remove it to allow U-Boot to pick a suitable address and relocate the FDT. Closes: https://lore.kernel.org/u-boot/8397369a-9b0b-4798-9c30-3a81165657d6@iscas.ac.cn Signed-off-by: Vivian Wang Reviewed-by: Tom Rini Reviewed-by: Lukas Auer Reviewed-by: Leo Yu-Chi Liang --- include/configs/qemu-riscv.h | 1 - 1 file changed, 1 deletion(-) diff --git a/include/configs/qemu-riscv.h b/include/configs/qemu-riscv.h index cf4fcb90b04..dad59cc0d58 100644 --- a/include/configs/qemu-riscv.h +++ b/include/configs/qemu-riscv.h @@ -32,7 +32,6 @@ #define CFG_EXTRA_ENV_SETTINGS \ CFG_STD_DEVICES_SETTINGS \ - "fdt_high=0xffffffffffffffff\0" \ "initrd_high=0xffffffffffffffff\0" \ "kernel_addr_r=0x84000000\0" \ "kernel_comp_addr_r=0x88000000\0" \ -- cgit v1.2.3 From 36d9587fa8b3590ae07ca16a2fe2aa6c905fc102 Mon Sep 17 00:00:00 2001 From: Greentime Hu Date: Mon, 15 Sep 2025 15:44:27 +0800 Subject: arch/riscv: Remove unused macro in encoding.h This patch remove the unused macro DRAM_BASE. Signed-off-by: Greentime Hu Reviewed-by: Leo Yu-Chi Liang --- arch/riscv/include/asm/encoding.h | 1 - 1 file changed, 1 deletion(-) diff --git a/arch/riscv/include/asm/encoding.h b/arch/riscv/include/asm/encoding.h index 56c5da86e86..ae3e5bce5c1 100644 --- a/arch/riscv/include/asm/encoding.h +++ b/arch/riscv/include/asm/encoding.h @@ -95,7 +95,6 @@ #define DEFAULT_MTVEC 0x00001010 #define CFG_STRING_ADDR 0x0000100C #define EXT_IO_BASE 0x40000000 -#define DRAM_BASE 0x80000000 // page table entry (PTE) fields #define PTE_V 0x001 // Valid -- cgit v1.2.3 From 27f617019dd070cb61f220c67244be834065aa30 Mon Sep 17 00:00:00 2001 From: E Shattow Date: Tue, 16 Sep 2025 17:02:22 -0700 Subject: riscv: dts: starfive: prune redundant jh7110-common overrides Prune jh7110-common-u-boot.dtsi (clocks, qspi flash, eeprom, and bootph-pre-ram hints now upstream since devicetree-rebasing v6.16). In preparation for removal of per-dts jh7110-*-u-boot.dtsi replace include by next dependency jh7110-u-boot.dtsi in automatic dtsi inclusion order. Signed-off-by: E Shattow Reviewed-by: Leo Yu-Chi Liang --- arch/riscv/dts/jh7110-common-u-boot.dtsi | 99 ---------------------- .../dts/jh7110-deepcomputing-fml13v01-u-boot.dtsi | 2 +- arch/riscv/dts/jh7110-milkv-mars-u-boot.dtsi | 2 +- arch/riscv/dts/jh7110-pine64-star64-u-boot.dtsi | 2 +- .../jh7110-starfive-visionfive-2-v1.2a-u-boot.dtsi | 2 +- .../jh7110-starfive-visionfive-2-v1.3b-u-boot.dtsi | 2 +- 6 files changed, 5 insertions(+), 104 deletions(-) delete mode 100644 arch/riscv/dts/jh7110-common-u-boot.dtsi diff --git a/arch/riscv/dts/jh7110-common-u-boot.dtsi b/arch/riscv/dts/jh7110-common-u-boot.dtsi deleted file mode 100644 index 049b0a7ce28..00000000000 --- a/arch/riscv/dts/jh7110-common-u-boot.dtsi +++ /dev/null @@ -1,99 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 OR MIT -/* - * Copyright (C) 2023 StarFive Technology Co., Ltd. - */ - -#include "jh7110-u-boot.dtsi" -/ { - aliases { - spi0 = &qspi; - }; - - chosen { - bootph-pre-ram; - }; - - firmware { - spi0 = &qspi; - bootph-pre-ram; - }; - - memory@40000000 { - bootph-pre-ram; - }; -}; - -&uart0 { - bootph-pre-ram; - reg-offset = <0>; - current-speed = <115200>; -}; - -&mmc0 { - bootph-pre-ram; -}; - -&mmc1 { - bootph-pre-ram; -}; - -&qspi { - bootph-pre-ram; - - flash@0 { - bootph-pre-ram; - cdns,read-delay = <2>; - spi-max-frequency = <100000000>; - }; -}; - -&syscrg { - assigned-clocks = <&syscrg JH7110_SYSCLK_CPU_ROOT>, - <&syscrg JH7110_SYSCLK_BUS_ROOT>, - <&syscrg JH7110_SYSCLK_PERH_ROOT>, - <&syscrg JH7110_SYSCLK_QSPI_REF>; - assigned-clock-parents = <&pllclk JH7110_PLLCLK_PLL0_OUT>, - <&pllclk JH7110_PLLCLK_PLL2_OUT>, - <&pllclk JH7110_PLLCLK_PLL2_OUT>, - <&syscrg JH7110_SYSCLK_QSPI_REF_SRC>; - assigned-clock-rates = <0>, <0>, <0>, <0>; -}; - -&sysgpio { - bootph-pre-ram; -}; - -&mmc0_pins { - bootph-pre-ram; - rst-pins { - bootph-pre-ram; - }; -}; - -&mmc1_pins { - bootph-pre-ram; - clk-pins { - bootph-pre-ram; - }; - - mmc-pins { - bootph-pre-ram; - }; -}; - -&i2c5_pins { - bootph-pre-ram; - i2c-pins { - bootph-pre-ram; - }; -}; - -&i2c5 { - bootph-pre-ram; - eeprom@50 { - bootph-pre-ram; - compatible = "atmel,24c04"; - reg = <0x50>; - pagesize = <16>; - }; -}; diff --git a/arch/riscv/dts/jh7110-deepcomputing-fml13v01-u-boot.dtsi b/arch/riscv/dts/jh7110-deepcomputing-fml13v01-u-boot.dtsi index ab882d07f6f..b9202f2acce 100644 --- a/arch/riscv/dts/jh7110-deepcomputing-fml13v01-u-boot.dtsi +++ b/arch/riscv/dts/jh7110-deepcomputing-fml13v01-u-boot.dtsi @@ -3,5 +3,5 @@ * Copyright (C) 2024 StarFive Technology Co., Ltd. */ -#include "jh7110-common-u-boot.dtsi" +#include "jh7110-u-boot.dtsi" #include "starfive-visionfive2-binman.dtsi" diff --git a/arch/riscv/dts/jh7110-milkv-mars-u-boot.dtsi b/arch/riscv/dts/jh7110-milkv-mars-u-boot.dtsi index ab882d07f6f..b9202f2acce 100644 --- a/arch/riscv/dts/jh7110-milkv-mars-u-boot.dtsi +++ b/arch/riscv/dts/jh7110-milkv-mars-u-boot.dtsi @@ -3,5 +3,5 @@ * Copyright (C) 2024 StarFive Technology Co., Ltd. */ -#include "jh7110-common-u-boot.dtsi" +#include "jh7110-u-boot.dtsi" #include "starfive-visionfive2-binman.dtsi" diff --git a/arch/riscv/dts/jh7110-pine64-star64-u-boot.dtsi b/arch/riscv/dts/jh7110-pine64-star64-u-boot.dtsi index ab882d07f6f..b9202f2acce 100644 --- a/arch/riscv/dts/jh7110-pine64-star64-u-boot.dtsi +++ b/arch/riscv/dts/jh7110-pine64-star64-u-boot.dtsi @@ -3,5 +3,5 @@ * Copyright (C) 2024 StarFive Technology Co., Ltd. */ -#include "jh7110-common-u-boot.dtsi" +#include "jh7110-u-boot.dtsi" #include "starfive-visionfive2-binman.dtsi" diff --git a/arch/riscv/dts/jh7110-starfive-visionfive-2-v1.2a-u-boot.dtsi b/arch/riscv/dts/jh7110-starfive-visionfive-2-v1.2a-u-boot.dtsi index ab882d07f6f..b9202f2acce 100644 --- a/arch/riscv/dts/jh7110-starfive-visionfive-2-v1.2a-u-boot.dtsi +++ b/arch/riscv/dts/jh7110-starfive-visionfive-2-v1.2a-u-boot.dtsi @@ -3,5 +3,5 @@ * Copyright (C) 2024 StarFive Technology Co., Ltd. */ -#include "jh7110-common-u-boot.dtsi" +#include "jh7110-u-boot.dtsi" #include "starfive-visionfive2-binman.dtsi" diff --git a/arch/riscv/dts/jh7110-starfive-visionfive-2-v1.3b-u-boot.dtsi b/arch/riscv/dts/jh7110-starfive-visionfive-2-v1.3b-u-boot.dtsi index 874074174ff..848ed8225ac 100644 --- a/arch/riscv/dts/jh7110-starfive-visionfive-2-v1.3b-u-boot.dtsi +++ b/arch/riscv/dts/jh7110-starfive-visionfive-2-v1.3b-u-boot.dtsi @@ -3,5 +3,5 @@ * Copyright (C) 2023 StarFive Technology Co., Ltd. */ -#include "jh7110-common-u-boot.dtsi" +#include "jh7110-u-boot.dtsi" #include "starfive-visionfive2-binman.dtsi" -- cgit v1.2.3 From 3e6d5b205d11eae088945c7aed838f281621e353 Mon Sep 17 00:00:00 2001 From: E Shattow Date: Tue, 16 Sep 2025 17:02:23 -0700 Subject: riscv: dts: starfive: sync visionfive2 overrides with upstream Linux for-next Sync automatic dtsi inclusion overrides for JH7110 CPU with upstream "riscv: dts: starfive: jh7110: bootph-pre-ram hinting needed by boot loader" from upstream Linux conor/riscv-dt-for-next commit 8181cc2f3f21 Signed-off-by: E Shattow Reviewed-by: Leo Yu-Chi Liang --- arch/riscv/dts/jh7110-u-boot.dtsi | 81 +++++++++++++++------------------------ 1 file changed, 31 insertions(+), 50 deletions(-) diff --git a/arch/riscv/dts/jh7110-u-boot.dtsi b/arch/riscv/dts/jh7110-u-boot.dtsi index f8d13277d24..cc27dd648f8 100644 --- a/arch/riscv/dts/jh7110-u-boot.dtsi +++ b/arch/riscv/dts/jh7110-u-boot.dtsi @@ -3,36 +3,10 @@ * Copyright (C) 2022 StarFive Technology Co., Ltd. */ -#include - -/ { - timer { - compatible = "riscv,timer"; - interrupts-extended = <&cpu0_intc 5>, - <&cpu1_intc 5>, - <&cpu2_intc 5>, - <&cpu3_intc 5>, - <&cpu4_intc 5>; - }; +// BEGIN "riscv: dts: starfive: jh7110: bootph-pre-ram hinting needed by boot loader" +// From upstream Linux conor/riscv-dt-for-next commit 8181cc2f3f21 - soc { - bootph-pre-ram; - - dmc: dmc@15700000 { - bootph-pre-ram; - compatible = "starfive,jh7110-dmc"; - reg = <0x0 0x15700000 0x0 0x10000>, - <0x0 0x13000000 0x0 0x10000>; - resets = <&syscrg JH7110_SYSRST_DDR_AXI>, - <&syscrg JH7110_SYSRST_DDR_OSC>, - <&syscrg JH7110_SYSRST_DDR_APB>; - reset-names = "axi", "osc", "apb"; - clocks = <&syscrg JH7110_PLLCLK_PLL1_OUT>; - clock-names = "pll1_out"; - clock-frequency = <2133>; - }; - }; -}; +#include &clint { bootph-pre-ram; @@ -58,22 +32,10 @@ bootph-pre-ram; }; -&cpus { - bootph-pre-ram; -}; - &osc { bootph-pre-ram; }; -&gmac0_rgmii_rxin { - bootph-pre-ram; -}; - -&gmac0_rmii_refin { - bootph-pre-ram; -}; - &gmac1_rgmii_rxin { bootph-pre-ram; }; @@ -82,23 +44,42 @@ bootph-pre-ram; }; -&aoncrg { - bootph-pre-ram; +/ { + soc { + memory-controller@15700000 { + compatible = "starfive,jh7110-dmc"; + reg = <0x0 0x15700000 0x0 0x10000>, + <0x0 0x13000000 0x0 0x10000>; + bootph-pre-ram; + clocks = <&syscrg JH7110_PLLCLK_PLL1_OUT>; + clock-names = "pll"; + resets = <&syscrg JH7110_SYSRST_DDR_AXI>, + <&syscrg JH7110_SYSRST_DDR_OSC>, + <&syscrg JH7110_SYSRST_DDR_APB>; + reset-names = "axi", "osc", "apb"; + }; + }; }; -&pllclk { +&syscrg { bootph-pre-ram; }; -&syscrg { - assigned-clock-rates = <0>; /* cpufreq not implemented, use defaults */ +&pllclk { bootph-pre-ram; }; -&stgcrg { - bootph-pre-ram; +// END "riscv: dts: starfive: jh7110: bootph-pre-ram hinting needed by boot loader" + +/ { + soc { + memory-controller@15700000 { + clock-frequency = <2133>; /* FIXME: delete property and implement CCF */ + }; + }; }; -&sys_syscon { - bootph-pre-ram; +&syscrg { + assigned-clock-rates = <0>; /* FIXME: delete property and implement cpufreq */ }; + -- cgit v1.2.3 From b8732d30a44412a346e2ef8c8c541fce8b00b364 Mon Sep 17 00:00:00 2001 From: E Shattow Date: Tue, 16 Sep 2025 17:02:24 -0700 Subject: riscv: dts: starfive: visionfive2 depend on SYS_CPU automatic dtsi inclusion Drop visionfive2 per-board -u-boot.dtsi stubs and instead rely on automatic inclusion of jh7110-u-boot.dtsi Signed-off-by: E Shattow Reviewed-by: Leo Yu-Chi Liang --- arch/riscv/dts/jh7110-deepcomputing-fml13v01-u-boot.dtsi | 7 ------- arch/riscv/dts/jh7110-milkv-mars-u-boot.dtsi | 7 ------- arch/riscv/dts/jh7110-pine64-star64-u-boot.dtsi | 7 ------- arch/riscv/dts/jh7110-starfive-visionfive-2-v1.2a-u-boot.dtsi | 7 ------- arch/riscv/dts/jh7110-starfive-visionfive-2-v1.3b-u-boot.dtsi | 7 ------- arch/riscv/dts/jh7110-u-boot.dtsi | 1 + 6 files changed, 1 insertion(+), 35 deletions(-) delete mode 100644 arch/riscv/dts/jh7110-deepcomputing-fml13v01-u-boot.dtsi delete mode 100644 arch/riscv/dts/jh7110-milkv-mars-u-boot.dtsi delete mode 100644 arch/riscv/dts/jh7110-pine64-star64-u-boot.dtsi delete mode 100644 arch/riscv/dts/jh7110-starfive-visionfive-2-v1.2a-u-boot.dtsi delete mode 100644 arch/riscv/dts/jh7110-starfive-visionfive-2-v1.3b-u-boot.dtsi diff --git a/arch/riscv/dts/jh7110-deepcomputing-fml13v01-u-boot.dtsi b/arch/riscv/dts/jh7110-deepcomputing-fml13v01-u-boot.dtsi deleted file mode 100644 index b9202f2acce..00000000000 --- a/arch/riscv/dts/jh7110-deepcomputing-fml13v01-u-boot.dtsi +++ /dev/null @@ -1,7 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 OR MIT -/* - * Copyright (C) 2024 StarFive Technology Co., Ltd. - */ - -#include "jh7110-u-boot.dtsi" -#include "starfive-visionfive2-binman.dtsi" diff --git a/arch/riscv/dts/jh7110-milkv-mars-u-boot.dtsi b/arch/riscv/dts/jh7110-milkv-mars-u-boot.dtsi deleted file mode 100644 index b9202f2acce..00000000000 --- a/arch/riscv/dts/jh7110-milkv-mars-u-boot.dtsi +++ /dev/null @@ -1,7 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 OR MIT -/* - * Copyright (C) 2024 StarFive Technology Co., Ltd. - */ - -#include "jh7110-u-boot.dtsi" -#include "starfive-visionfive2-binman.dtsi" diff --git a/arch/riscv/dts/jh7110-pine64-star64-u-boot.dtsi b/arch/riscv/dts/jh7110-pine64-star64-u-boot.dtsi deleted file mode 100644 index b9202f2acce..00000000000 --- a/arch/riscv/dts/jh7110-pine64-star64-u-boot.dtsi +++ /dev/null @@ -1,7 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 OR MIT -/* - * Copyright (C) 2024 StarFive Technology Co., Ltd. - */ - -#include "jh7110-u-boot.dtsi" -#include "starfive-visionfive2-binman.dtsi" diff --git a/arch/riscv/dts/jh7110-starfive-visionfive-2-v1.2a-u-boot.dtsi b/arch/riscv/dts/jh7110-starfive-visionfive-2-v1.2a-u-boot.dtsi deleted file mode 100644 index b9202f2acce..00000000000 --- a/arch/riscv/dts/jh7110-starfive-visionfive-2-v1.2a-u-boot.dtsi +++ /dev/null @@ -1,7 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 OR MIT -/* - * Copyright (C) 2024 StarFive Technology Co., Ltd. - */ - -#include "jh7110-u-boot.dtsi" -#include "starfive-visionfive2-binman.dtsi" diff --git a/arch/riscv/dts/jh7110-starfive-visionfive-2-v1.3b-u-boot.dtsi b/arch/riscv/dts/jh7110-starfive-visionfive-2-v1.3b-u-boot.dtsi deleted file mode 100644 index 848ed8225ac..00000000000 --- a/arch/riscv/dts/jh7110-starfive-visionfive-2-v1.3b-u-boot.dtsi +++ /dev/null @@ -1,7 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 OR MIT -/* - * Copyright (C) 2023 StarFive Technology Co., Ltd. - */ - -#include "jh7110-u-boot.dtsi" -#include "starfive-visionfive2-binman.dtsi" diff --git a/arch/riscv/dts/jh7110-u-boot.dtsi b/arch/riscv/dts/jh7110-u-boot.dtsi index cc27dd648f8..0e5dc3685b2 100644 --- a/arch/riscv/dts/jh7110-u-boot.dtsi +++ b/arch/riscv/dts/jh7110-u-boot.dtsi @@ -83,3 +83,4 @@ assigned-clock-rates = <0>; /* FIXME: delete property and implement cpufreq */ }; +#include "starfive-visionfive2-binman.dtsi" -- cgit v1.2.3 From 10fdc2735da3a4825a5172056090eaf41e061627 Mon Sep 17 00:00:00 2001 From: E Shattow Date: Tue, 16 Sep 2025 17:02:25 -0700 Subject: configs: starfive: Use visionfive2 DEVICE_TREE_INCLUDES dtsi named similar to defconfig Add SYS_CPU automatic inclusion jh7110-u-boot.dtsi to item of config list DEVICE_TREE_INCLUDES as starfive-visionfive2-u-boot.dtsi and rename file. Signed-off-by: E Shattow Reviewed-by: Leo Yu-Chi Liang --- arch/riscv/dts/jh7110-u-boot.dtsi | 86 ------------------------- arch/riscv/dts/starfive-visionfive2-u-boot.dtsi | 86 +++++++++++++++++++++++++ configs/starfive_visionfive2_defconfig | 1 + 3 files changed, 87 insertions(+), 86 deletions(-) delete mode 100644 arch/riscv/dts/jh7110-u-boot.dtsi create mode 100644 arch/riscv/dts/starfive-visionfive2-u-boot.dtsi diff --git a/arch/riscv/dts/jh7110-u-boot.dtsi b/arch/riscv/dts/jh7110-u-boot.dtsi deleted file mode 100644 index 0e5dc3685b2..00000000000 --- a/arch/riscv/dts/jh7110-u-boot.dtsi +++ /dev/null @@ -1,86 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 OR MIT -/* - * Copyright (C) 2022 StarFive Technology Co., Ltd. - */ - -// BEGIN "riscv: dts: starfive: jh7110: bootph-pre-ram hinting needed by boot loader" -// From upstream Linux conor/riscv-dt-for-next commit 8181cc2f3f21 - -#include - -&clint { - bootph-pre-ram; -}; - -&cpu0_intc { - bootph-pre-ram; -}; - -&cpu1_intc { - bootph-pre-ram; -}; - -&cpu2_intc { - bootph-pre-ram; -}; - -&cpu3_intc { - bootph-pre-ram; -}; - -&cpu4_intc { - bootph-pre-ram; -}; - -&osc { - bootph-pre-ram; -}; - -&gmac1_rgmii_rxin { - bootph-pre-ram; -}; - -&gmac1_rmii_refin { - bootph-pre-ram; -}; - -/ { - soc { - memory-controller@15700000 { - compatible = "starfive,jh7110-dmc"; - reg = <0x0 0x15700000 0x0 0x10000>, - <0x0 0x13000000 0x0 0x10000>; - bootph-pre-ram; - clocks = <&syscrg JH7110_PLLCLK_PLL1_OUT>; - clock-names = "pll"; - resets = <&syscrg JH7110_SYSRST_DDR_AXI>, - <&syscrg JH7110_SYSRST_DDR_OSC>, - <&syscrg JH7110_SYSRST_DDR_APB>; - reset-names = "axi", "osc", "apb"; - }; - }; -}; - -&syscrg { - bootph-pre-ram; -}; - -&pllclk { - bootph-pre-ram; -}; - -// END "riscv: dts: starfive: jh7110: bootph-pre-ram hinting needed by boot loader" - -/ { - soc { - memory-controller@15700000 { - clock-frequency = <2133>; /* FIXME: delete property and implement CCF */ - }; - }; -}; - -&syscrg { - assigned-clock-rates = <0>; /* FIXME: delete property and implement cpufreq */ -}; - -#include "starfive-visionfive2-binman.dtsi" diff --git a/arch/riscv/dts/starfive-visionfive2-u-boot.dtsi b/arch/riscv/dts/starfive-visionfive2-u-boot.dtsi new file mode 100644 index 00000000000..0e5dc3685b2 --- /dev/null +++ b/arch/riscv/dts/starfive-visionfive2-u-boot.dtsi @@ -0,0 +1,86 @@ +// SPDX-License-Identifier: GPL-2.0 OR MIT +/* + * Copyright (C) 2022 StarFive Technology Co., Ltd. + */ + +// BEGIN "riscv: dts: starfive: jh7110: bootph-pre-ram hinting needed by boot loader" +// From upstream Linux conor/riscv-dt-for-next commit 8181cc2f3f21 + +#include + +&clint { + bootph-pre-ram; +}; + +&cpu0_intc { + bootph-pre-ram; +}; + +&cpu1_intc { + bootph-pre-ram; +}; + +&cpu2_intc { + bootph-pre-ram; +}; + +&cpu3_intc { + bootph-pre-ram; +}; + +&cpu4_intc { + bootph-pre-ram; +}; + +&osc { + bootph-pre-ram; +}; + +&gmac1_rgmii_rxin { + bootph-pre-ram; +}; + +&gmac1_rmii_refin { + bootph-pre-ram; +}; + +/ { + soc { + memory-controller@15700000 { + compatible = "starfive,jh7110-dmc"; + reg = <0x0 0x15700000 0x0 0x10000>, + <0x0 0x13000000 0x0 0x10000>; + bootph-pre-ram; + clocks = <&syscrg JH7110_PLLCLK_PLL1_OUT>; + clock-names = "pll"; + resets = <&syscrg JH7110_SYSRST_DDR_AXI>, + <&syscrg JH7110_SYSRST_DDR_OSC>, + <&syscrg JH7110_SYSRST_DDR_APB>; + reset-names = "axi", "osc", "apb"; + }; + }; +}; + +&syscrg { + bootph-pre-ram; +}; + +&pllclk { + bootph-pre-ram; +}; + +// END "riscv: dts: starfive: jh7110: bootph-pre-ram hinting needed by boot loader" + +/ { + soc { + memory-controller@15700000 { + clock-frequency = <2133>; /* FIXME: delete property and implement CCF */ + }; + }; +}; + +&syscrg { + assigned-clock-rates = <0>; /* FIXME: delete property and implement cpufreq */ +}; + +#include "starfive-visionfive2-binman.dtsi" diff --git a/configs/starfive_visionfive2_defconfig b/configs/starfive_visionfive2_defconfig index 544140c03f7..03fcec7f121 100644 --- a/configs/starfive_visionfive2_defconfig +++ b/configs/starfive_visionfive2_defconfig @@ -78,6 +78,7 @@ CONFIG_CMD_WDT=y CONFIG_CMD_WGET=y CONFIG_CMD_BOOTSTAGE=y CONFIG_OF_BOARD=y +CONFIG_DEVICE_TREE_INCLUDES="starfive-visionfive2-u-boot.dtsi" CONFIG_OF_LIST="starfive/jh7110-deepcomputing-fml13v01 starfive/jh7110-milkv-mars starfive/jh7110-pine64-star64 starfive/jh7110-starfive-visionfive-2-v1.2a starfive/jh7110-starfive-visionfive-2-v1.3b" CONFIG_MULTI_DTB_FIT=y CONFIG_ENV_OVERWRITE=y -- cgit v1.2.3 From ecced05f679e1920ffd3e1bd57334bd6442194c4 Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Wed, 10 Sep 2025 09:12:39 +0200 Subject: lib: Tidy up comments for vsprintf functions Some of the functions in this file do not follow the normal style. Fix this so that things are more consistent. Signed-off-by: Simon Glass Signed-off-by: Heinrich Schuchardt --- include/vsprintf.h | 25 +++++++++++++------------ 1 file changed, 13 insertions(+), 12 deletions(-) diff --git a/include/vsprintf.h b/include/vsprintf.h index 9da6ce7cc4d..3cb335515e4 100644 --- a/include/vsprintf.h +++ b/include/vsprintf.h @@ -11,7 +11,7 @@ #include /** - * simple_strtoul - convert a string to an unsigned long + * simple_strtoul() - convert a string to an unsigned long * * @cp: The string to be converted * @endp: Updated to point to the first character not converted @@ -32,7 +32,7 @@ ulong simple_strtoul(const char *cp, char **endp, unsigned int base); /** - * hex_strtoul - convert a string in hex to an unsigned long + * hex_strtoul() - convert a string in hex to an unsigned long * * @cp: The string to be converted * @endp: Updated to point to the first character not converted @@ -45,7 +45,7 @@ ulong simple_strtoul(const char *cp, char **endp, unsigned int base); unsigned long hextoul(const char *cp, char **endp); /** - * hex_strtoull - convert a string in hex to an unsigned long long + * hex_strtoull() - convert a string in hex to an unsigned long long * * @cp: The string to be converted * @endp: Updated to point to the first character not converted @@ -58,7 +58,7 @@ unsigned long hextoul(const char *cp, char **endp); unsigned long long hextoull(const char *cp, char **endp); /** - * dec_strtoul - convert a string in decimal to an unsigned long + * dec_strtoul() - convert a string in decimal to an unsigned long * * @cp: The string to be converted * @endp: Updated to point to the first character not converted @@ -71,7 +71,7 @@ unsigned long long hextoull(const char *cp, char **endp); unsigned long dectoul(const char *cp, char **endp); /** - * strict_strtoul - convert a string to an unsigned long strictly + * strict_strtoul() - convert a string to an unsigned long strictly * @cp: The string to be converted * @base: The number base to use (0 for the default) * @res: The converted result value @@ -100,6 +100,7 @@ unsigned long dectoul(const char *cp, char **endp); * */ int strict_strtoul(const char *cp, unsigned int base, unsigned long *res); + unsigned long long simple_strtoull(const char *cp, char **endp, unsigned int base); long simple_strtol(const char *cp, char **endp, unsigned int base); @@ -178,7 +179,7 @@ void panic(const char *fmt, ...) void panic_str(const char *str) __attribute__ ((noreturn)); /** - * Format a string and place it in a buffer + * sprintf() - Format a string and place it in a buffer * * @buf: The buffer to place the result into * @fmt: The format string to use @@ -193,7 +194,7 @@ int sprintf(char *buf, const char *fmt, ...) __attribute__ ((format (__printf__, 2, 3))); /** - * Format a string and place it in a buffer (va_list version) + * vsprintf() - Format a string and place it in a buffer (va_list version) * * @buf: The buffer to place the result into * @fmt: The format string to use @@ -232,7 +233,7 @@ char *simple_itoa(ulong val); char *simple_xtoa(ulong num); /** - * Format a string and place it in a buffer + * scnprintf() - Format a string and place it in a buffer * * @buf: The buffer to place the result into * @size: The size of the buffer, including the trailing null space @@ -248,7 +249,7 @@ int scnprintf(char *buf, size_t size, const char *fmt, ...) __attribute__ ((format (__printf__, 3, 4))); /** - * Format a string and place it in a buffer (base function) + * vsnprintf() - Format a string and place it in a buffer (base function) * * @buf: The buffer to place the result into * @size: The size of the buffer, including the trailing null space @@ -273,7 +274,7 @@ int scnprintf(char *buf, size_t size, const char *fmt, ...) int vsnprintf(char *buf, size_t size, const char *fmt, va_list args); /** - * Format a string and place it in a buffer (va_list version) + * vscnprintf() - Format a string and place it in a buffer (va_list version) * * @buf: The buffer to place the result into * @size: The size of the buffer, including the trailing null space @@ -349,7 +350,7 @@ const char **str_to_list(const char *instr); void str_free_list(const char **ptr); /** - * vsscanf - Unformat a buffer into a list of arguments + * vsscanf() - Unformat a buffer into a list of arguments * @inp: input buffer * @fmt0: format of buffer * @ap: arguments @@ -357,7 +358,7 @@ void str_free_list(const char **ptr); int vsscanf(const char *inp, char const *fmt0, va_list ap); /** - * sscanf - Unformat a buffer into a list of arguments + * sscanf() - Unformat a buffer into a list of arguments * @buf: input buffer * @fmt: formatting of buffer * @...: resulting arguments -- cgit v1.2.3 From e246e2b65885e6d5fd052ec2acdf2b07a53171f0 Mon Sep 17 00:00:00 2001 From: Kunihiko Hayashi Date: Wed, 10 Sep 2025 18:23:26 +0900 Subject: configs: qemu-sbsa: Define GIC register base address If GICV3 is enabled, GICD_BASE and GICR_BASE are needed at arch/arm/cpu/armv8/start.S. Signed-off-by: Kunihiko Hayashi --- include/configs/qemu-sbsa.h | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/include/configs/qemu-sbsa.h b/include/configs/qemu-sbsa.h index aff78160e12..669d0fe7c58 100644 --- a/include/configs/qemu-sbsa.h +++ b/include/configs/qemu-sbsa.h @@ -86,4 +86,8 @@ #define CFG_SYS_INIT_RAM_ADDR SBSA_MEM_BASE_ADDR #define CFG_SYS_INIT_RAM_SIZE 0x1000000 +/* Generic Interrupt Controller Definitions */ +#define GICD_BASE SBSA_GIC_DIST_BASE_ADDR +#define GICR_BASE SBSA_GIC_REDIST_BASE_ADDR + #endif /* __CONFIG_H */ -- cgit v1.2.3 From edaaedb5dd0fee9fcdfe41d92659914dc9d1d44d Mon Sep 17 00:00:00 2001 From: Kunihiko Hayashi Date: Wed, 10 Sep 2025 18:23:27 +0900 Subject: board: qemu-sbsa: Fix mistyped GICV3 definition The config "GIC_V3" seems to be typo, and currently "GICV3" remains disabled. Since "GIC_V3_ITS" is enabled in qemu-sbsa, "GICV3" should also be enabled. Fixes: 6d722894fd48 ("board: emulation: Add QEMU sbsa support") Signed-off-by: Kunihiko Hayashi --- board/emulation/qemu-sbsa/Kconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/board/emulation/qemu-sbsa/Kconfig b/board/emulation/qemu-sbsa/Kconfig index 9ea6303ec9c..1f058a43932 100644 --- a/board/emulation/qemu-sbsa/Kconfig +++ b/board/emulation/qemu-sbsa/Kconfig @@ -34,7 +34,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select PCIE_ECAM_GENERIC select SYS_PCI_64BIT select USB - select GIC_V3 + select GICV3 select GIC_V3_ITS select SYS_FLASH_CFI_WIDTH_16BIT imply AHCI_GENERIC -- cgit v1.2.3 From 6f79e80079aae24d2fbcc73185a5a35fdeaed3bb Mon Sep 17 00:00:00 2001 From: Daniel Schultz Date: Tue, 9 Sep 2025 12:36:53 +0200 Subject: configs: phycore_am62ax_r5_defconfig: eMMC boot from raw offsets Enable CONFIG_SPL_SYS_MMCSD_RAW_MODE and set the offset address to boot from raw addresses instead of a FAT partition. Signed-off-by: Daniel Schultz Signed-off-by: Wadim Egorov Acked-by: Anshul Dalal --- configs/phycore_am62ax_r5_defconfig | 2 ++ 1 file changed, 2 insertions(+) diff --git a/configs/phycore_am62ax_r5_defconfig b/configs/phycore_am62ax_r5_defconfig index 01d100842de..584a6415ca5 100644 --- a/configs/phycore_am62ax_r5_defconfig +++ b/configs/phycore_am62ax_r5_defconfig @@ -42,6 +42,8 @@ CONFIG_SPL_SYS_MALLOC=y CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x84000000 CONFIG_SPL_EARLY_BSS=y +CONFIG_SPL_SYS_MMCSD_RAW_MODE=y +CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x400 CONFIG_SPL_DMA=y CONFIG_SPL_DM_MAILBOX=y CONFIG_SPL_MTD=y -- cgit v1.2.3 From be5715f9aa93341fb01f870af596bfa37e137b91 Mon Sep 17 00:00:00 2001 From: Daniel Schultz Date: Tue, 9 Sep 2025 12:36:54 +0200 Subject: configs: phycore_am62ax_a53_defconfig: eMMC boot from raw offsets Enable CONFIG_SPL_SYS_MMCSD_RAW_MODE and set the offset address to boot from raw addresses instead of a FAT partition. Signed-off-by: Daniel Schultz Signed-off-by: Wadim Egorov Acked-by: Anshul Dalal --- configs/phycore_am62ax_a53_defconfig | 2 ++ 1 file changed, 2 insertions(+) diff --git a/configs/phycore_am62ax_a53_defconfig b/configs/phycore_am62ax_a53_defconfig index 05849d05be4..27fa4386a21 100644 --- a/configs/phycore_am62ax_a53_defconfig +++ b/configs/phycore_am62ax_a53_defconfig @@ -48,6 +48,8 @@ CONFIG_SPL_MAX_SIZE=0x58000 CONFIG_SPL_PAD_TO=0x0 CONFIG_SPL_BOARD_INIT=y CONFIG_SPL_SYS_MALLOC_SIMPLE=y +CONFIG_SPL_SYS_MMCSD_RAW_MODE=y +CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x1400 CONFIG_SPL_DMA=y CONFIG_SPL_ENV_SUPPORT=y CONFIG_SPL_ETH=y -- cgit v1.2.3 From b717a4090fb0fda4814bbc9d9a91396710294cfb Mon Sep 17 00:00:00 2001 From: John Ripple Date: Tue, 9 Sep 2025 13:53:22 -0600 Subject: imx8: Add ahab_commit command The ahab_commit command allows the user to commit into the SECO fuses that control the SRK key revocation information. This is used to Revoke compromised SRK keys. To use ahab_commit, the boot container must be built with an SRK revocation bit mask that is not 0x0. For the SPSDK provided by NXP, this means setting the 'srk_revoke_mask' option in the config file used to sign the boot container. The 'ahab_commit 0x10' can then be used to commit the SRK revocation information into the SECO fuses. Signed-off-by: John Ripple --- arch/arm/mach-imx/imx8/ahab.c | 29 +++++++++++++++++++++++++++++ drivers/misc/imx8/scu_api.c | 31 +++++++++++++++++++++++++++++++ include/firmware/imx/sci/sci.h | 6 ++++++ 3 files changed, 66 insertions(+) diff --git a/arch/arm/mach-imx/imx8/ahab.c b/arch/arm/mach-imx/imx8/ahab.c index 324e010bb2c..f13baa871cc 100644 --- a/arch/arm/mach-imx/imx8/ahab.c +++ b/arch/arm/mach-imx/imx8/ahab.c @@ -401,6 +401,29 @@ static int do_ahab_close(struct cmd_tbl *cmdtp, int flag, int argc, return 0; } +static int do_ahab_commit(struct cmd_tbl *cmdtp, int flag, int argc, + char *const argv[]) +{ + u32 info; + int ret; + + if (argc < 2) + return CMD_RET_USAGE; + + info = simple_strtoul(argv[1], NULL, 16); + printf("Commit index is 0x%x\n", info); + + ret = sc_seco_commit(-1, &info); + if (ret) { + printf("Error in AHAB commit\n"); + return ret; + } + + printf("AHAB commit succeeded.\n"); + + return CMD_RET_SUCCESS; +} + U_BOOT_CMD(auth_cntr, CONFIG_SYS_MAXARGS, 1, do_authenticate, "autenticate OS container via AHAB", "addr\n" @@ -416,3 +439,9 @@ U_BOOT_CMD(ahab_close, CONFIG_SYS_MAXARGS, 1, do_ahab_close, "Change AHAB lifecycle to OEM closed", "" ); + +U_BOOT_CMD(ahab_commit, CONFIG_SYS_MAXARGS, 1, do_ahab_commit, + "commit into the fuses any new SRK revocation information that have been found\n" + "into the NXP (SECO FW) and OEM containers. For SRK revocation use 0x10 for the value.", + "" +); diff --git a/drivers/misc/imx8/scu_api.c b/drivers/misc/imx8/scu_api.c index 8985ab6584d..d9cc7acb970 100644 --- a/drivers/misc/imx8/scu_api.c +++ b/drivers/misc/imx8/scu_api.c @@ -1286,3 +1286,34 @@ int sc_seco_secvio_dgo_config(sc_ipc_t ipc, u8 id, u8 access, u32 *data) return ret; } + +int sc_seco_commit(sc_ipc_t ipc, u32 *info) +{ + struct udevice *dev = gd->arch.scu_dev; + struct sc_rpc_msg_s msg; + int size = sizeof(struct sc_rpc_msg_s); + int ret; + + /* Fill in header */ + RPC_VER(&msg) = SC_RPC_VERSION; + RPC_SIZE(&msg) = 2U; + RPC_SVC(&msg) = (u8)SC_RPC_SVC_SECO; + RPC_FUNC(&msg) = (u8)SECO_FUNC_COMMIT; + + /* Fill in send message */ + RPC_U32(&msg, 0U) = *info; + + /* Call RPC */ + ret = misc_call(dev, SC_FALSE, &msg, size, &msg, size); + if (ret) + return ret; + + /* Copy out result */ + ret = (int)RPC_R8(&msg); + + /* Copy out receive message */ + if (!ret) + *info = RPC_U32(&msg, 0U); + + return ret; +} diff --git a/include/firmware/imx/sci/sci.h b/include/firmware/imx/sci/sci.h index 588f3671103..876d52cac35 100644 --- a/include/firmware/imx/sci/sci.h +++ b/include/firmware/imx/sci/sci.h @@ -144,6 +144,7 @@ int sc_seco_secvio_dgo_config(sc_ipc_t ipc, u8 id, u8 access, u32 *data); int sc_seco_secvio_config(sc_ipc_t ipc, u8 id, u8 access, u32 *data0, u32 *data1, u32 *data2, u32 *data3, u32 *data4, u8 size); +int sc_seco_commit(sc_ipc_t ipc, u32 *info); #else /* PM API*/ static inline int sc_pm_set_resource_power_mode(sc_ipc_t ipc, sc_rsrc_t resource, @@ -383,6 +384,11 @@ static inline int sc_seco_secvio_config(sc_ipc_t ipc, u8 id, u8 access, u32 *dat return -EOPNOTSUPP; } +static inline int sc_seco_commit(sc_ipc_t ipc, u32 *info) +{ + return -EOPNOTSUPP; +} + static inline void sc_pm_reboot(sc_ipc_t ipc, sc_pm_reset_type_t type) { } -- cgit v1.2.3 From 00ef795981d0c2df52e7fdd91d57a924b941dbfb Mon Sep 17 00:00:00 2001 From: Ye Li Date: Thu, 11 Sep 2025 18:56:04 +0800 Subject: pci: dw: Fix wrong register used for PCI_COMMAND Wirting to command register should use PCI_COMMAND not PCI_PRIMARY_BUS Signed-off-by: Ye Li --- drivers/pci/pcie_dw_common.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/drivers/pci/pcie_dw_common.c b/drivers/pci/pcie_dw_common.c index c4cad019373..4113a9f03cf 100644 --- a/drivers/pci/pcie_dw_common.c +++ b/drivers/pci/pcie_dw_common.c @@ -7,7 +7,6 @@ * * Copyright (C) 2018 Texas Instruments, Inc */ - #include #include #include @@ -385,7 +384,7 @@ void pcie_dw_setup_host(struct pcie_dw *pci) 0xffffff, 0x00ff0100); /* setup command register */ - clrsetbits_le32(pci->dbi_base + PCI_PRIMARY_BUS, + clrsetbits_le32(pci->dbi_base + PCI_COMMAND, 0xffff, PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER | PCI_COMMAND_SERR); -- cgit v1.2.3 From f8b188350815df2e0436eb113e7c9300ca9cd02e Mon Sep 17 00:00:00 2001 From: Ye Li Date: Thu, 11 Sep 2025 18:56:05 +0800 Subject: pci: pcie_dw_imx: Add iMX9 support to the driver Adding iMX95/iMX94 support to the dw driver. Follow kernel driver stype to use flags to distinguish the characteristic of different platforms. Signed-off-by: Ye Li --- drivers/pci/Kconfig | 2 +- drivers/pci/pcie_dw_imx.c | 420 +++++++++++++++++++++++++++++++++++++++++----- 2 files changed, 377 insertions(+), 45 deletions(-) diff --git a/drivers/pci/Kconfig b/drivers/pci/Kconfig index b8568267ff8..6c2cda1a966 100644 --- a/drivers/pci/Kconfig +++ b/drivers/pci/Kconfig @@ -461,7 +461,7 @@ config PCIE_STARFIVE_JH7110 config PCIE_DW_IMX bool "i.MX DW PCIe controller support" - depends on ARCH_IMX8M + depends on ARCH_IMX8M || ARCH_IMX9 select PCIE_DW_COMMON select DM_REGULATOR select REGMAP diff --git a/drivers/pci/pcie_dw_imx.c b/drivers/pci/pcie_dw_imx.c index fdb463710ba..f84c7180560 100644 --- a/drivers/pci/pcie_dw_imx.c +++ b/drivers/pci/pcie_dw_imx.c @@ -1,6 +1,7 @@ // SPDX-License-Identifier: GPL-2.0+ /* * Copyright (C) 2024 Linaro Ltd. + * Copyright 2025 NXP * * Author: Sumit Garg */ @@ -45,6 +46,47 @@ #define IMX8M_GPR_PCIE_CLK_REQ_OVERRIDE_EN BIT(10) #define IMX8M_GPR_PCIE_CLK_REQ_OVERRIDE BIT(11) +#define IMX95_PCIE_PHY_GEN_CTRL 0x0 +#define IMX95_PCIE_REF_USE_PAD BIT(17) + +#define IMX95_PCIE_PHY_MPLLA_CTRL 0x10 +#define IMX95_PCIE_PHY_MPLL_STATE BIT(30) + +#define IMX95_PCIE_SS_RW_REG_0 0xf0 +#define IMX95_PCIE_REF_CLKEN BIT(23) +#define IMX95_PCIE_PHY_CR_PARA_SEL BIT(9) +#define IMX95_PCIE_SS_RW_REG_1 0xf4 +#define IMX95_PCIE_CLKREQ_OVERRIDE_EN BIT(8) +#define IMX95_PCIE_CLKREQ_OVERRIDE_VAL BIT(9) +#define IMX95_PCIE_SYS_AUX_PWR_DET BIT(31) + +#define IMX95_PE0_GEN_CTRL_1 0x1050 +#define IMX95_PCIE_DEVICE_TYPE GENMASK(3, 0) + +#define IMX95_PE0_GEN_CTRL_3 0x1058 +#define IMX95_PCIE_LTSSM_EN BIT(0) + +#define IMX95_PCIE_RST_CTRL 0x3010 +#define IMX95_PCIE_COLD_RST BIT(0) + +#define GEN3_RELATED_OFF 0x890 +#define GEN3_RELATED_OFF_GEN3_ZRXDC_NONCOMPL BIT(0) +#define GEN3_RELATED_OFF_RXEQ_RGRDLESS_RXTS BIT(13) +#define GEN3_RELATED_OFF_GEN3_EQ_DISABLE BIT(16) +#define GEN3_RELATED_OFF_RATE_SHADOW_SEL_SHIFT 24 +#define GEN3_RELATED_OFF_RATE_SHADOW_SEL_MASK GENMASK(25, 24) +#define GEN3_RELATED_OFF_RATE_SHADOW_SEL_16_0GT 0x1 + +#define IMX_PCIE_FLAG_HAS_PHYDRV BIT(3) +#define IMX_PCIE_FLAG_HAS_APP_RESET BIT(4) +#define IMX_PCIE_FLAG_HAS_SERDES BIT(6) + +#define IMX_PCIE_MAX_INSTANCES 2 + +/* Parameters for the waiting for PCIe PHY PLL to lock s*/ +#define PHY_PLL_LOCK_WAIT_USLEEP_MAX 200 +#define PHY_PLL_LOCK_WAIT_TIMEOUT (2000 * PHY_PLL_LOCK_WAIT_USLEEP_MAX / 1000) + struct pcie_dw_imx { /* Must be first member of the struct */ struct pcie_dw dw; @@ -54,20 +96,203 @@ struct pcie_dw_imx { struct reset_ctl apps_reset; struct phy phy; struct udevice *vpcie; + void *info; + u32 max_link_speed; + bool enable_ext_refclk; + bool supports_clkreq; }; struct pcie_chip_info { + u32 flags; + const u32 ltssm_off; + const u32 ltssm_mask; + const u32 mode_off[IMX_PCIE_MAX_INSTANCES]; + const u32 mode_mask[IMX_PCIE_MAX_INSTANCES]; const char *gpr; + void (*init_phy)(struct pcie_dw_imx *priv); + int (*enable_ref_clk)(struct pcie_dw_imx *priv, bool enable); + int (*core_reset)(struct pcie_dw_imx *priv, bool assert); + int (*wait_pll_lock)(struct pcie_dw_imx *priv); + void (*post_config)(struct pcie_dw_imx *priv); }; +static void imx95_pcie_init_phy(struct pcie_dw_imx *priv) +{ +/* + * Workaround for ERR051624: The Controller Without Vaux Cannot + * Exit L23 Ready Through Beacon or PERST# De-assertion + * + * When the auxiliary power is not available the controller + * cannot exit from L23 Ready with beacon or PERST# de-assertion + * when main power is not removed. + * + * Workaround: Set SS_RW_REG_1[SYS_AUX_PWR_DET] to 1. + */ + regmap_update_bits(priv->iomuxc_gpr, IMX95_PCIE_SS_RW_REG_1, + IMX95_PCIE_SYS_AUX_PWR_DET, IMX95_PCIE_SYS_AUX_PWR_DET); + + regmap_update_bits(priv->iomuxc_gpr, + IMX95_PCIE_SS_RW_REG_0, + IMX95_PCIE_PHY_CR_PARA_SEL, + IMX95_PCIE_PHY_CR_PARA_SEL); + + if (priv->enable_ext_refclk) { + /* External clock is used as reference clock */ + regmap_update_bits(priv->iomuxc_gpr, + IMX95_PCIE_PHY_GEN_CTRL, + IMX95_PCIE_REF_USE_PAD, + IMX95_PCIE_REF_USE_PAD); + regmap_update_bits(priv->iomuxc_gpr, + IMX95_PCIE_SS_RW_REG_0, + IMX95_PCIE_REF_CLKEN, 0); + } else { + regmap_update_bits(priv->iomuxc_gpr, + IMX95_PCIE_PHY_GEN_CTRL, + IMX95_PCIE_REF_USE_PAD, 0); + + regmap_update_bits(priv->iomuxc_gpr, + IMX95_PCIE_SS_RW_REG_0, + IMX95_PCIE_REF_CLKEN, + IMX95_PCIE_REF_CLKEN); + } + + /* Force CLKREQ# low by override */ + if (!priv->supports_clkreq) + regmap_update_bits(priv->iomuxc_gpr, + IMX95_PCIE_SS_RW_REG_1, + IMX95_PCIE_CLKREQ_OVERRIDE_EN | + IMX95_PCIE_CLKREQ_OVERRIDE_VAL, + IMX95_PCIE_CLKREQ_OVERRIDE_EN | + IMX95_PCIE_CLKREQ_OVERRIDE_VAL); +} + +static int imx95_pcie_wait_for_phy_pll_lock(struct pcie_dw_imx *priv) +{ + u32 val; + + if (regmap_read_poll_timeout(priv->iomuxc_gpr, + IMX95_PCIE_PHY_MPLLA_CTRL, val, + val & IMX95_PCIE_PHY_MPLL_STATE, + PHY_PLL_LOCK_WAIT_USLEEP_MAX, + PHY_PLL_LOCK_WAIT_TIMEOUT)) { + printf("PCIe PLL lock timeout\n"); + return -ETIMEDOUT; + } + + return 0; +} + +static int imx95_pcie_core_reset(struct pcie_dw_imx *priv, bool assert) +{ + u32 val; + + if (assert) { + /* + * From i.MX95 PCIe PHY perspective, the COLD reset toggle + * should be complete after power-up by the following sequence. + * > 10us(at power-up) + * > 10ns(warm reset) + * |<------------>| + * ______________ + * phy_reset ____/ \________________ + * ____________ + * ref_clk_en_______________________/ + * Toggle COLD reset aligned with this sequence for i.MX95 PCIe. + */ + regmap_update_bits(priv->iomuxc_gpr, IMX95_PCIE_RST_CTRL, + IMX95_PCIE_COLD_RST, IMX95_PCIE_COLD_RST); + /* + * Make sure the write to IMX95_PCIE_RST_CTRL is flushed to the + * hardware by doing a read. Otherwise, there is no guarantee + * that the write has reached the hardware before udelay(). + */ + regmap_read(priv->iomuxc_gpr, IMX95_PCIE_RST_CTRL, + &val); + udelay(15); + regmap_update_bits(priv->iomuxc_gpr, IMX95_PCIE_RST_CTRL, + IMX95_PCIE_COLD_RST, 0); + regmap_read(priv->iomuxc_gpr, IMX95_PCIE_RST_CTRL, + &val); + udelay(10); + } + + return 0; +} + +static void imx95_pcie_post_config(struct pcie_dw_imx *priv) +{ + u32 val; + + /* + * Workaround for ERR051586: Compliance with 8GT/s Receiver + * Impedance ECN + * + * The default value of GEN3_RELATED_OFF[GEN3_ZRXDC_NONCOMPL] is + * 1 which makes receiver non-compliant with the ZRX-DC + * parameter for 2.5 GT/s when operating at 8 GT/s or higher. It + * causes unnecessary timeout in L1. + * + * Workaround: Program GEN3_RELATED_OFF[GEN3_ZRXDC_NONCOMPL] to 0. + */ + dw_pcie_dbi_write_enable(&priv->dw, true); + val = readl(priv->dw.dbi_base + GEN3_RELATED_OFF); + val &= ~GEN3_RELATED_OFF_GEN3_ZRXDC_NONCOMPL; + writel(val, priv->dw.dbi_base + GEN3_RELATED_OFF); + dw_pcie_dbi_write_enable(&priv->dw, false); +} + +static int imx8mm_pcie_enable_ref_clk(struct pcie_dw_imx *priv, bool enable) +{ + regmap_update_bits(priv->iomuxc_gpr, IOMUXC_GPR14_OFFSET, + IMX8M_GPR_PCIE_CLK_REQ_OVERRIDE, + enable ? 0 : IMX8M_GPR_PCIE_CLK_REQ_OVERRIDE); + regmap_update_bits(priv->iomuxc_gpr, IOMUXC_GPR14_OFFSET, + IMX8M_GPR_PCIE_CLK_REQ_OVERRIDE_EN, + enable ? IMX8M_GPR_PCIE_CLK_REQ_OVERRIDE_EN : 0); + return 0; +} + static const struct pcie_chip_info imx8mm_chip_info = { + .flags = IMX_PCIE_FLAG_HAS_APP_RESET | IMX_PCIE_FLAG_HAS_PHYDRV, .gpr = "fsl,imx8mm-iomuxc-gpr", + .enable_ref_clk = imx8mm_pcie_enable_ref_clk, }; static const struct pcie_chip_info imx8mp_chip_info = { + .flags = IMX_PCIE_FLAG_HAS_APP_RESET | IMX_PCIE_FLAG_HAS_PHYDRV, .gpr = "fsl,imx8mp-iomuxc-gpr", + .enable_ref_clk = imx8mm_pcie_enable_ref_clk, +}; + +static const struct pcie_chip_info imx95_chip_info = { + .flags = IMX_PCIE_FLAG_HAS_SERDES, + .ltssm_off = IMX95_PE0_GEN_CTRL_3, + .ltssm_mask = IMX95_PCIE_LTSSM_EN, + .mode_off[0] = IMX95_PE0_GEN_CTRL_1, + .mode_mask[0] = IMX95_PCIE_DEVICE_TYPE, + .init_phy = imx95_pcie_init_phy, + .core_reset = imx95_pcie_core_reset, + .wait_pll_lock = imx95_pcie_wait_for_phy_pll_lock, + .post_config = imx95_pcie_post_config, }; +static void imx_pcie_configure_type(struct pcie_dw_imx *priv) +{ + struct pcie_chip_info *info = (struct pcie_chip_info *)(priv->info); + unsigned int mask, val, mode; + + mode = PCI_EXP_TYPE_ROOT_PORT; + + /* If mode_mask is 0, then generic PHY driver is used to set the mode */ + if (!info->mode_mask[0]) + return; + + mask = info->mode_mask[0]; + val = mode << (ffs(mask) - 1); + + regmap_update_bits(priv->iomuxc_gpr, info->mode_off[0], mask, val); +} + static void pcie_dw_configure(struct pcie_dw_imx *priv, u32 cap_speed) { dw_pcie_dbi_write_enable(&priv->dw, true); @@ -75,17 +300,34 @@ static void pcie_dw_configure(struct pcie_dw_imx *priv, u32 cap_speed) clrsetbits_le32(priv->dw.dbi_base + PCIE_LINK_CAPABILITY, TARGET_LINK_SPEED_MASK, cap_speed); + clrsetbits_le32(priv->dw.dbi_base + PCIE_LINK_CTL_2, + TARGET_LINK_SPEED_MASK, cap_speed); + dw_pcie_dbi_write_enable(&priv->dw, false); } static void imx_pcie_ltssm_enable(struct pcie_dw_imx *priv) { - reset_deassert(&priv->apps_reset); + struct pcie_chip_info *info = (struct pcie_chip_info *)(priv->info); + + if (info->ltssm_mask) + regmap_update_bits(priv->iomuxc_gpr, info->ltssm_off, info->ltssm_mask, + info->ltssm_mask); + + if (info->flags & IMX_PCIE_FLAG_HAS_APP_RESET) + reset_deassert(&priv->apps_reset); } static void imx_pcie_ltssm_disable(struct pcie_dw_imx *priv) { - reset_assert(&priv->apps_reset); + struct pcie_chip_info *info = (struct pcie_chip_info *)(priv->info); + + if (info->ltssm_mask) + regmap_update_bits(priv->iomuxc_gpr, info->ltssm_off, + info->ltssm_mask, 0); + + if (info->flags & IMX_PCIE_FLAG_HAS_APP_RESET) + reset_assert(&priv->apps_reset); } static bool is_link_up(u32 val) @@ -122,6 +364,11 @@ static int pcie_link_up(struct pcie_dw_imx *priv, u32 cap_speed) static int imx_pcie_assert_core_reset(struct pcie_dw_imx *priv) { + struct pcie_chip_info *info = (struct pcie_chip_info *)(priv->info); + + if (info->core_reset) + info->core_reset(priv, true); + if (dm_gpio_is_valid(&priv->reset_gpio)) { dm_gpio_set_value(&priv->reset_gpio, 1); mdelay(20); @@ -133,6 +380,7 @@ static int imx_pcie_assert_core_reset(struct pcie_dw_imx *priv) static int imx_pcie_clk_enable(struct pcie_dw_imx *priv) { int ret; + struct pcie_chip_info *info = (struct pcie_chip_info *)(priv->info); ret = clk_enable_bulk(&priv->clks); if (ret) @@ -142,11 +390,8 @@ static int imx_pcie_clk_enable(struct pcie_dw_imx *priv) * Set the over ride low and enabled make sure that * REF_CLK is turned on. */ - regmap_update_bits(priv->iomuxc_gpr, IOMUXC_GPR14_OFFSET, - IMX8M_GPR_PCIE_CLK_REQ_OVERRIDE, 0); - regmap_update_bits(priv->iomuxc_gpr, IOMUXC_GPR14_OFFSET, - IMX8M_GPR_PCIE_CLK_REQ_OVERRIDE_EN, - IMX8M_GPR_PCIE_CLK_REQ_OVERRIDE_EN); + if (info->enable_ref_clk) + info->enable_ref_clk(priv, true); /* allow the clocks to stabilize */ udelay(500); @@ -156,6 +401,11 @@ static int imx_pcie_clk_enable(struct pcie_dw_imx *priv) static void imx_pcie_deassert_core_reset(struct pcie_dw_imx *priv) { + struct pcie_chip_info *info = (struct pcie_chip_info *)(priv->info); + + if (info->core_reset) + info->core_reset(priv, false); + if (!dm_gpio_is_valid(&priv->reset_gpio)) return; @@ -170,10 +420,11 @@ static int pcie_dw_imx_probe(struct udevice *dev) struct pcie_dw_imx *priv = dev_get_priv(dev); struct udevice *ctlr = pci_get_controller(dev); struct pci_controller *hose = dev_get_uclass_priv(ctlr); + struct pcie_chip_info *info = (void *)dev_get_driver_data(dev); int ret; if (priv->vpcie) { - ret = regulator_set_enable(priv->vpcie, true); + ret = regulator_set_enable_if_allowed(priv->vpcie, true); if (ret) { dev_err(dev, "failed to enable vpcie regulator\n"); return ret; @@ -186,31 +437,49 @@ static int pcie_dw_imx_probe(struct udevice *dev) return ret; } + if (info->init_phy) + info->init_phy(priv); + + imx_pcie_configure_type(priv); + ret = imx_pcie_clk_enable(priv); if (ret) { dev_err(dev, "failed to enable clocks\n"); goto err_clk; } - ret = generic_phy_init(&priv->phy); - if (ret) { - dev_err(dev, "failed to initialize PHY\n"); - goto err_phy_init; - } + if (info->flags & IMX_PCIE_FLAG_HAS_PHYDRV) { + ret = generic_phy_init(&priv->phy); + if (ret) { + dev_err(dev, "failed to initialize PHY\n"); + goto err_phy_init; + } - ret = generic_phy_power_on(&priv->phy); - if (ret) { - dev_err(dev, "failed to power on PHY\n"); - goto err_phy_power; + ret = generic_phy_power_on(&priv->phy); + if (ret) { + dev_err(dev, "failed to power on PHY\n"); + goto err_phy_power; + } } imx_pcie_deassert_core_reset(priv); + if (info->wait_pll_lock) { + ret = info->wait_pll_lock(priv); + if (ret) { + dev_err(dev, "failed to wait pll lock\n"); + goto err_link; + } + } + + if (info->post_config) + info->post_config(priv); + priv->dw.first_busno = dev_seq(dev); priv->dw.dev = dev; pcie_dw_setup_host(&priv->dw); - if (pcie_link_up(priv, LINK_SPEED_GEN_1)) { + if (pcie_link_up(priv, priv->max_link_speed)) { printf("PCIE-%d: Link down\n", dev_seq(dev)); ret = -ENODEV; goto err_link; @@ -229,26 +498,41 @@ static int pcie_dw_imx_probe(struct udevice *dev) return 0; err_link: - generic_shutdown_phy(&priv->phy); + if (info->flags & IMX_PCIE_FLAG_HAS_PHYDRV) + generic_shutdown_phy(&priv->phy); err_phy_power: - generic_phy_exit(&priv->phy); + if (info->flags & IMX_PCIE_FLAG_HAS_PHYDRV) + generic_phy_exit(&priv->phy); err_phy_init: - clk_disable_bulk(&priv->clks); + clk_release_bulk(&priv->clks); err_clk: imx_pcie_deassert_core_reset(priv); + dm_gpio_free(dev, &priv->reset_gpio); + + if (priv->vpcie) + regulator_set_enable_if_allowed(priv->vpcie, false); + return ret; } static int pcie_dw_imx_remove(struct udevice *dev) { struct pcie_dw_imx *priv = dev_get_priv(dev); + struct pcie_chip_info *info = (void *)dev_get_driver_data(dev); + + if (info->flags & IMX_PCIE_FLAG_HAS_PHYDRV) + generic_shutdown_phy(&priv->phy); - generic_shutdown_phy(&priv->phy); dm_gpio_free(dev, &priv->reset_gpio); - reset_free(&priv->apps_reset); + if (info->flags & IMX_PCIE_FLAG_HAS_APP_RESET) + reset_free(&priv->apps_reset); + clk_release_bulk(&priv->clks); + if (priv->vpcie) + regulator_set_enable_if_allowed(priv->vpcie, false); + return 0; } @@ -257,7 +541,9 @@ static int pcie_dw_imx_of_to_plat(struct udevice *dev) struct pcie_chip_info *info = (void *)dev_get_driver_data(dev); struct pcie_dw_imx *priv = dev_get_priv(dev); ofnode gpr; - int ret; + int ret, index; + + priv->info = info; /* Get the controller base address */ priv->dw.dbi_base = (void *)dev_read_addr_name(dev, "dbi"); @@ -274,17 +560,29 @@ static int pcie_dw_imx_of_to_plat(struct udevice *dev) return -EINVAL; } + priv->dw.atu_base = (void *)dev_read_addr_name_ptr(dev, "atu"); + if (!priv->dw.atu_base) + dev_dbg(dev, "failed to get atu address from dtb\n"); + ret = clk_get_bulk(dev, &priv->clks); if (ret) { dev_err(dev, "failed to get PCIe clks\n"); return ret; } - ret = reset_get_by_name(dev, "apps", &priv->apps_reset); - if (ret) { - dev_err(dev, - "Failed to get PCIe apps reset control\n"); - goto err_reset; + index = ofnode_stringlist_search(dev_ofnode(dev), "clock-names", "ext-ref"); + if (index < 0) + priv->enable_ext_refclk = false; + else + priv->enable_ext_refclk = true; + + if (info->flags & IMX_PCIE_FLAG_HAS_APP_RESET) { + ret = reset_get_by_name(dev, "apps", &priv->apps_reset); + if (ret) { + dev_err(dev, + "Failed to get PCIe apps reset control\n"); + goto err_reset; + } } ret = gpio_request_by_name(dev, "reset-gpio", 0, &priv->reset_gpio, @@ -294,26 +592,58 @@ static int pcie_dw_imx_of_to_plat(struct udevice *dev) goto err_gpio; } - ret = generic_phy_get_by_name(dev, "pcie-phy", &priv->phy); - if (ret) { - dev_err(dev, "failed to get pcie phy\n"); - goto err_phy; + if (info->flags & IMX_PCIE_FLAG_HAS_PHYDRV) { + ret = generic_phy_get_by_name(dev, "pcie-phy", &priv->phy); + if (ret) { + dev_err(dev, "failed to get pcie phy\n"); + goto err_phy; + } } - gpr = ofnode_by_compatible(ofnode_null(), info->gpr); - if (ofnode_equal(gpr, ofnode_null())) { - dev_err(dev, "unable to find GPR node\n"); - ret = -ENODEV; - goto err_phy; + if (info->flags & IMX_PCIE_FLAG_HAS_SERDES) { + void __iomem *app_base; + fdt_size_t app_size; + struct regmap_config config; + + app_base = (void *)dev_read_addr_size_name(dev, "app", &app_size); + if ((fdt_addr_t)app_base == FDT_ADDR_T_NONE) { + dev_err(dev, "failed to get app_base address\n"); + return -EINVAL; + } + + config.r_start = (ulong)app_base; + config.r_size = (ulong)app_size; + config.reg_offset_shift = 0; + config.width = REGMAP_SIZE_32; + + priv->iomuxc_gpr = devm_regmap_init(dev, NULL, NULL, &config); + if (IS_ERR(priv->iomuxc_gpr)) { + dev_err(dev, "unable to remap gpr\n"); + ret = PTR_ERR(priv->iomuxc_gpr); + goto err_phy; + } } - priv->iomuxc_gpr = syscon_node_to_regmap(gpr); - if (IS_ERR(priv->iomuxc_gpr)) { - dev_err(dev, "unable to find iomuxc registers\n"); - ret = PTR_ERR(priv->iomuxc_gpr); - goto err_phy; + if (info->gpr) { + gpr = ofnode_by_compatible(ofnode_null(), info->gpr); + if (ofnode_equal(gpr, ofnode_null())) { + dev_err(dev, "unable to find GPR node\n"); + ret = -ENODEV; + goto err_phy; + } + + priv->iomuxc_gpr = syscon_node_to_regmap(gpr); + if (IS_ERR(priv->iomuxc_gpr)) { + dev_err(dev, "unable to find iomuxc registers\n"); + ret = PTR_ERR(priv->iomuxc_gpr); + goto err_phy; + } } + priv->max_link_speed = dev_read_u32_default(dev, "fsl,max-link-speed", LINK_SPEED_GEN_1); + + priv->supports_clkreq = dev_read_bool(dev, "supports-clkreq"); + /* vpcie-supply regulator is optional */ device_get_supply_regulator(dev, "vpcie-supply", &priv->vpcie); @@ -322,7 +652,8 @@ static int pcie_dw_imx_of_to_plat(struct udevice *dev) err_phy: dm_gpio_free(dev, &priv->reset_gpio); err_gpio: - reset_free(&priv->apps_reset); + if (info->flags & IMX_PCIE_FLAG_HAS_APP_RESET) + reset_free(&priv->apps_reset); err_reset: clk_release_bulk(&priv->clks); @@ -337,6 +668,7 @@ static const struct dm_pci_ops pcie_dw_imx_ops = { static const struct udevice_id pcie_dw_imx_ids[] = { { .compatible = "fsl,imx8mm-pcie", .data = (ulong)&imx8mm_chip_info, }, { .compatible = "fsl,imx8mp-pcie", .data = (ulong)&imx8mp_chip_info, }, + { .compatible = "fsl,imx95-pcie", .data = (ulong)&imx95_chip_info, }, { } }; -- cgit v1.2.3 From d680ac6cfd052ced54f51d7cfe081ad291550e44 Mon Sep 17 00:00:00 2001 From: Ye Li Date: Thu, 11 Sep 2025 18:56:06 +0800 Subject: clk: imx: Add imx95 blkctrl clock driver Add iMX95 blkctrl clock driver which implements clocks for HSIOMIX blkctrl and LVDS blkctrl. Since multiple blkctrl device for different blkctrl may be enabled, and each has dedicated clock id from 0. We must enable CLK_AUTO_ID to avoid conflict on clock id. Signed-off-by: Ye Li --- drivers/clk/imx/Kconfig | 9 ++ drivers/clk/imx/Makefile | 1 + drivers/clk/imx/clk-imx95-blkctrl.c | 170 ++++++++++++++++++++++++++++++++++++ 3 files changed, 180 insertions(+) create mode 100644 drivers/clk/imx/clk-imx95-blkctrl.c diff --git a/drivers/clk/imx/Kconfig b/drivers/clk/imx/Kconfig index 74d5fe73f94..644ab162af4 100644 --- a/drivers/clk/imx/Kconfig +++ b/drivers/clk/imx/Kconfig @@ -167,3 +167,12 @@ config CLK_IMXRT1170 select CLK_CCF help This enables support clock driver for i.MXRT1170 platforms. + +config CLK_IMX95_BLKCTRL + bool "Enable i.MX95 blkctrl clock driver" + depends on IMX95 || IMX94 + select CLK + select CLK_CCF + select CLK_AUTO_ID + help + Enable support for clocks in i.MX95 MIX blkctrl like HSIO and LVDS. diff --git a/drivers/clk/imx/Makefile b/drivers/clk/imx/Makefile index b10221a195c..f2fd6ff8ca0 100644 --- a/drivers/clk/imx/Makefile +++ b/drivers/clk/imx/Makefile @@ -25,3 +25,4 @@ obj-$(CONFIG_$(PHASE_)CLK_IMX93) += clk-imx93.o clk-fracn-gppll.o \ obj-$(CONFIG_$(PHASE_)CLK_IMXRT1020) += clk-imxrt1020.o obj-$(CONFIG_$(PHASE_)CLK_IMXRT1050) += clk-imxrt1050.o obj-$(CONFIG_$(PHASE_)CLK_IMXRT1170) += clk-imxrt1170.o +obj-$(CONFIG_CLK_IMX95_BLKCTRL) += clk-imx95-blkctrl.o diff --git a/drivers/clk/imx/clk-imx95-blkctrl.c b/drivers/clk/imx/clk-imx95-blkctrl.c new file mode 100644 index 00000000000..3bf6f9415e2 --- /dev/null +++ b/drivers/clk/imx/clk-imx95-blkctrl.c @@ -0,0 +1,170 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2023-2025 NXP + * + */ + +#include +#include +#include +#include +#include +#include + +#include "clk.h" + +enum { + CLK_GATE, + CLK_DIVIDER, + CLK_MUX, +}; + +struct imx95_blk_ctl_clk_dev_data { + const char *name; + const char * const *parent_names; + u32 num_parents; + u32 reg; + u32 bit_idx; + u32 clk_type; + u32 flags; + u32 flags2; + u32 type; +}; + +struct imx95_blk_ctl_dev_data { + const struct imx95_blk_ctl_clk_dev_data *clk_dev_data; + u32 num_clks; + u32 clk_reg_offset; +}; + +static const struct imx95_blk_ctl_clk_dev_data hsio_blk_ctl_clk_dev_data[] = { + [0] = { + .name = "hsio_blk_ctl_clk", + .parent_names = (const char *[]){ "hsiopll", }, + .num_parents = 1, + .reg = 0, + .bit_idx = 6, + .type = CLK_GATE, + .flags = CLK_SET_RATE_PARENT, + } +}; + +static const struct imx95_blk_ctl_dev_data hsio_blk_ctl_dev_data = { + .num_clks = 1, + .clk_dev_data = hsio_blk_ctl_clk_dev_data, + .clk_reg_offset = 0, +}; + +static const struct imx95_blk_ctl_clk_dev_data imx95_lvds_clk_dev_data[] = { + [IMX95_CLK_DISPMIX_LVDS_PHY_DIV] = { + .name = "ldb_phy_div", + .parent_names = (const char *[]){ "ldbpll", }, + .num_parents = 1, + .reg = 0, + .bit_idx = 0, + .type = CLK_DIVIDER, + .flags2 = CLK_DIVIDER_POWER_OF_TWO, + }, + + [IMX95_CLK_DISPMIX_LVDS_CH0_GATE] = { + .name = "lvds_ch0_gate", + .parent_names = (const char *[]){ "ldb_phy_div", }, + .num_parents = 1, + .reg = 0, + .bit_idx = 1, + .type = CLK_GATE, + .flags = CLK_SET_RATE_PARENT, + .flags2 = CLK_GATE_SET_TO_DISABLE, + }, + [IMX95_CLK_DISPMIX_LVDS_CH1_GATE] = { + .name = "lvds_ch1_gate", + .parent_names = (const char *[]){ "ldb_phy_div", }, + .num_parents = 1, + .reg = 0, + .bit_idx = 2, + .type = CLK_GATE, + .flags = CLK_SET_RATE_PARENT, + .flags2 = CLK_GATE_SET_TO_DISABLE, + }, + [IMX95_CLK_DISPMIX_PIX_DI0_GATE] = { + .name = "lvds_di0_gate", + .parent_names = (const char *[]){ "ldb_pll_div7", }, + .num_parents = 1, + .reg = 0, + .bit_idx = 3, + .type = CLK_GATE, + .flags = CLK_SET_RATE_PARENT, + .flags2 = CLK_GATE_SET_TO_DISABLE, + }, + [IMX95_CLK_DISPMIX_PIX_DI1_GATE] = { + .name = "lvds_di1_gate", + .parent_names = (const char *[]){ "ldb_pll_div7", }, + .num_parents = 1, + .reg = 0, + .bit_idx = 4, + .type = CLK_GATE, + .flags = CLK_SET_RATE_PARENT, + .flags2 = CLK_GATE_SET_TO_DISABLE, + }, +}; + +static const struct imx95_blk_ctl_dev_data imx95_lvds_csr_dev_data = { + .num_clks = ARRAY_SIZE(imx95_lvds_clk_dev_data), + .clk_dev_data = imx95_lvds_clk_dev_data, + .clk_reg_offset = 0, +}; + +static int imx95_blkctrl_clk_probe(struct udevice *dev) +{ + int i; + void __iomem *addr; + struct imx95_blk_ctl_dev_data *dev_data = (void *)dev_get_driver_data(dev); + const struct imx95_blk_ctl_clk_dev_data *clk_dev_data; + + addr = dev_read_addr_ptr(dev); + if (addr == (void *)FDT_ADDR_T_NONE) { + dev_err(dev, "No blkctrl register base address\n"); + return -EINVAL; + } + + if (!dev_data) { + dev_err(dev, "driver data is NULL\n"); + return -EINVAL; + } + + clk_dev_data = dev_data->clk_dev_data; + for (i = 0; i < dev_data->num_clks; i++) { + if (clk_dev_data[i].clk_type == CLK_GATE) { + dev_clk_dm(dev, i, clk_register_gate(dev, clk_dev_data[i].name, clk_dev_data[i].parent_names[0], + clk_dev_data[i].flags, addr + dev_data->clk_reg_offset, clk_dev_data[i].bit_idx, + clk_dev_data[i].flags2, NULL)); + } else if (clk_dev_data[i].clk_type == CLK_DIVIDER) { + dev_clk_dm(dev, i, + clk_register_divider(dev, clk_dev_data[i].name, clk_dev_data[i].parent_names[0], + clk_dev_data[i].flags, addr + dev_data->clk_reg_offset, clk_dev_data[i].bit_idx, 1, + clk_dev_data[i].flags2)); + } else if (clk_dev_data[i].clk_type == CLK_MUX) { + dev_clk_dm(dev, i, + clk_register_mux(dev, clk_dev_data[i].name, clk_dev_data[i].parent_names, + clk_dev_data[i].num_parents, clk_dev_data[i].flags, addr + dev_data->clk_reg_offset, + clk_dev_data[i].bit_idx, 1, clk_dev_data[i].flags2)); + } + } + + return 0; +} + +static const struct udevice_id imx95_blkctrl_clk_ids[] = { + { .compatible = "nxp,imx95-lvds-csr", .data = (ulong)&imx95_lvds_csr_dev_data, }, + { .compatible = "nxp,imx95-hsio-blk-ctl", .data = (ulong)&hsio_blk_ctl_dev_data, }, + { }, +}; + +U_BOOT_DRIVER(imx95_blkctrl_clk) = { + .name = "imx95_blkctrl_clk", + .id = UCLASS_CLK, + .of_match = imx95_blkctrl_clk_ids, + .ops = &ccf_clk_ops, + .probe = imx95_blkctrl_clk_probe, + .flags = DM_FLAG_PRE_RELOC, +}; -- cgit v1.2.3 From f98d812e5353408ef77a46bad1f1cdc793ff8a03 Mon Sep 17 00:00:00 2001 From: Ye Li Date: Thu, 11 Sep 2025 18:56:07 +0800 Subject: power: regulator: Add vin-supply for GPIO and Fixed regulators Enable the vin-supply when probing the regulator device. Signed-off-by: Ye Li --- drivers/power/regulator/regulator_common.c | 10 ++++++++++ drivers/power/regulator/regulator_common.h | 1 + 2 files changed, 11 insertions(+) diff --git a/drivers/power/regulator/regulator_common.c b/drivers/power/regulator/regulator_common.c index e3565d32a01..c80f10c3aa3 100644 --- a/drivers/power/regulator/regulator_common.c +++ b/drivers/power/regulator/regulator_common.c @@ -45,6 +45,16 @@ int regulator_common_of_to_plat(struct udevice *dev, dev_read_u32_default(dev, "u-boot,off-on-delay-us", 0); } + ret = device_get_supply_regulator(dev, "vin-supply", &plat->vin_supply); + if (ret) { + debug("Regulator vin regulator not defined: %d\n", ret); + if (ret != -ENOENT) + return ret; + } + + if (plat->vin_supply) + regulator_set_enable_if_allowed(plat->vin_supply, true); + return 0; } diff --git a/drivers/power/regulator/regulator_common.h b/drivers/power/regulator/regulator_common.h index d4962899d83..799c968d0b6 100644 --- a/drivers/power/regulator/regulator_common.h +++ b/drivers/power/regulator/regulator_common.h @@ -14,6 +14,7 @@ struct regulator_common_plat { unsigned int startup_delay_us; unsigned int off_on_delay_us; unsigned int enable_count; + struct udevice *vin_supply; }; int regulator_common_of_to_plat(struct udevice *dev, -- cgit v1.2.3 From 87119e0f793d55bc540ac98fea9d75c3cb5ac8be Mon Sep 17 00:00:00 2001 From: Ye Li Date: Thu, 11 Sep 2025 18:56:08 +0800 Subject: clk: clk-uclass: Fix clk_set_default_rates issue clk_set_rate returns the actual clock rate, When assigned clock rate is higher than 0x7FFFFFFF, the return value will be recognized as error. Change to IS_ERR_VALUE to check the return value. Signed-off-by: Ye Li --- drivers/clk/clk-uclass.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/clk/clk-uclass.c b/drivers/clk/clk-uclass.c index 7262e89b512..3dbe1ce9441 100644 --- a/drivers/clk/clk-uclass.c +++ b/drivers/clk/clk-uclass.c @@ -358,7 +358,7 @@ static int clk_set_default_rates(struct udevice *dev, ret = clk_set_rate(c, rates[index]); - if (ret < 0) { + if (IS_ERR_VALUE(ret)) { dev_warn(dev, "failed to set rate on clock index %d (%ld) (error = %d)\n", index, clk.id, ret); -- cgit v1.2.3 From 749f6762b40859c24db6f13ba491300c1d22508c Mon Sep 17 00:00:00 2001 From: Ye Li Date: Thu, 11 Sep 2025 18:56:09 +0800 Subject: arm: dts: imx95: Assign HSIOPLL_VCO as HSIOPLL parent clock We have to explicitly assign HSIOPLL_VCO as HSIOPLL parent. So when enabling HSIOPLL, its parent HSIOPLL_VCO will be enabled firstly. Signed-off-by: Ye Li --- arch/arm/dts/imx95-u-boot.dtsi | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/arch/arm/dts/imx95-u-boot.dtsi b/arch/arm/dts/imx95-u-boot.dtsi index 9bf8f9834c9..27f8209b19c 100644 --- a/arch/arm/dts/imx95-u-boot.dtsi +++ b/arch/arm/dts/imx95-u-boot.dtsi @@ -170,6 +170,22 @@ bootph-all; }; +&pcie0 { + assigned-clocks =<&scmi_clk IMX95_CLK_HSIOPLL_VCO>, + <&scmi_clk IMX95_CLK_HSIOPLL>, + <&scmi_clk IMX95_CLK_HSIOPCIEAUX>; + assigned-clock-parents = <0>, <&scmi_clk IMX95_CLK_HSIOPLL_VCO>, + <&scmi_clk IMX95_CLK_SYSPLL1_PFD1_DIV2>; +}; + +&pcie1 { + assigned-clocks =<&scmi_clk IMX95_CLK_HSIOPLL_VCO>, + <&scmi_clk IMX95_CLK_HSIOPLL>, + <&scmi_clk IMX95_CLK_HSIOPCIEAUX>; + assigned-clock-parents = <0>, <&scmi_clk IMX95_CLK_HSIOPLL_VCO>, + <&scmi_clk IMX95_CLK_SYSPLL1_PFD1_DIV2>; +}; + &{/soc} { bootph-all; }; -- cgit v1.2.3 From 5c4e28e52f247bfc4fca4e5f61246e510602ad9e Mon Sep 17 00:00:00 2001 From: Ye Li Date: Thu, 11 Sep 2025 18:56:10 +0800 Subject: arm: dts: imx95-evk: set alias for enetc PCI buses Use fixed seq 0 and 1 for enetc PCI buses, then the seq for PCI controllers could start after them. Signed-off-by: Ye Li --- arch/arm/dts/imx95-19x19-evk-u-boot.dtsi | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/arch/arm/dts/imx95-19x19-evk-u-boot.dtsi b/arch/arm/dts/imx95-19x19-evk-u-boot.dtsi index 2d1f02baa5f..8b59831b7ca 100644 --- a/arch/arm/dts/imx95-19x19-evk-u-boot.dtsi +++ b/arch/arm/dts/imx95-19x19-evk-u-boot.dtsi @@ -5,6 +5,13 @@ #include "imx95-u-boot.dtsi" +/ { + aliases { + pci0 = &netc_bus0; + pci1 = &netc_bus1; + }; +}; + &lpuart1 { bootph-pre-ram; }; -- cgit v1.2.3 From 9f90e39d1cc458e2955c1edbe8a018c0c6c08b32 Mon Sep 17 00:00:00 2001 From: Ye Li Date: Thu, 11 Sep 2025 18:56:11 +0800 Subject: imx95_evk: Enable PCI host controller on iMX95 19x19 EVK Enable DW IMX PCI driver and iMX95 BLKCTRL clock driver in defconfig, so PCI controller can work. Signed-off-by: Ye Li --- configs/imx95_19x19_evk_defconfig | 7 ++----- 1 file changed, 2 insertions(+), 5 deletions(-) diff --git a/configs/imx95_19x19_evk_defconfig b/configs/imx95_19x19_evk_defconfig index 73818a82627..f0a31dbda7b 100644 --- a/configs/imx95_19x19_evk_defconfig +++ b/configs/imx95_19x19_evk_defconfig @@ -94,15 +94,12 @@ CONFIG_ETHPRIME="eth0" CONFIG_NET_RANDOM_ETHADDR=y CONFIG_SYS_RX_ETH_BUFFER=8 CONFIG_SPL_DM=y -CONFIG_REGMAP=y -CONFIG_SYSCON=y CONFIG_SPL_OF_TRANSLATE=y -CONFIG_CLK=y CONFIG_SPL_CLK=y CONFIG_SPL_CLK_CCF=y -CONFIG_CLK_CCF=y CONFIG_CLK_SCMI=y CONFIG_SPL_CLK_SCMI=y +CONFIG_CLK_IMX95_BLKCTRL=y CONFIG_DFU_MMC=y CONFIG_DFU_RAM=y CONFIG_SPL_FIRMWARE=y @@ -130,13 +127,13 @@ CONFIG_DM_MDIO=y CONFIG_MII=y CONFIG_FSL_ENETC=y CONFIG_PCIE_ECAM_GENERIC=y +CONFIG_PCIE_DW_IMX=y CONFIG_PHY=y CONFIG_PINCTRL=y CONFIG_SPL_PINCTRL=y CONFIG_PINCTRL_IMX_SCMI=y CONFIG_POWER_DOMAIN=y CONFIG_SCMI_POWER_DOMAIN=y -CONFIG_DM_REGULATOR=y CONFIG_SPL_DM_REGULATOR=y CONFIG_DM_REGULATOR_FIXED=y CONFIG_SPL_DM_REGULATOR_FIXED=y -- cgit v1.2.3 From 8918b60e33157dd6abaaf11ea24437da133eed0a Mon Sep 17 00:00:00 2001 From: Mathieu Dubois-Briand Date: Mon, 15 Sep 2025 14:57:02 +0200 Subject: imx93_frdm: Add support for flashing board with UUU Allow to flash a board using NXP UUU utility: - Enable fastboot support on USB. - Add fastboot partition aliases with names used by UUU. Also add extra environment variables used by UUU. - Set 'dofastboot' environment variable based on boot device configuration, allowing to automatically enter fastboot when booting from USB. Signed-off-by: Mathieu Dubois-Briand --- board/freescale/imx93_frdm/imx93_frdm.c | 6 ++++++ board/freescale/imx93_frdm/imx93_frdm.env | 8 ++++++++ configs/imx93_frdm_defconfig | 14 ++++++++++++++ doc/board/nxp/imx93_frdm.rst | 22 ++++++++++++++++++++++ 4 files changed, 50 insertions(+) diff --git a/board/freescale/imx93_frdm/imx93_frdm.c b/board/freescale/imx93_frdm/imx93_frdm.c index c74fd85712f..c436ac6aa47 100644 --- a/board/freescale/imx93_frdm/imx93_frdm.c +++ b/board/freescale/imx93_frdm/imx93_frdm.c @@ -10,6 +10,7 @@ #include #include #include +#include #include #include @@ -55,5 +56,10 @@ int board_late_init(void) env_set("board_rev", "iMX93"); } + if (get_boot_device() == USB_BOOT) { + printf("USB boot detected. Will enter fasboot mode\n"); + env_set_ulong("dofastboot", 1); + } + return 0; } diff --git a/board/freescale/imx93_frdm/imx93_frdm.env b/board/freescale/imx93_frdm/imx93_frdm.env index 528a953c8df..111f38ed72a 100644 --- a/board/freescale/imx93_frdm/imx93_frdm.env +++ b/board/freescale/imx93_frdm/imx93_frdm.env @@ -19,8 +19,16 @@ kernel_addr_r=CONFIG_SYS_LOAD_ADDR loadimage=load mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image} loadfdt=load mmc ${mmcdev}:${mmcpart} ${fdt_addr_r} ${fdtfile} boot_os=booti ${loadaddr} - ${fdt_addr_r} +fastboot_partition_alias_all=0:0 +fastboot_partition_alias_bootloader=0.1 +emmc_dev=0 +sd_dev=1 +dofastboot=0 bsp_bootcmd= + if test ${dofastboot} = 1; then + fastboot 0; + fi; echo Running BSP bootcmd ...; mmc dev ${mmcdev}; run mmcargs; diff --git a/configs/imx93_frdm_defconfig b/configs/imx93_frdm_defconfig index 4f837ca9282..eddd36c618d 100644 --- a/configs/imx93_frdm_defconfig +++ b/configs/imx93_frdm_defconfig @@ -30,6 +30,7 @@ CONFIG_EFI_VAR_BUF_SIZE=139264 CONFIG_EFI_RUNTIME_UPDATE_CAPSULE=y CONFIG_EFI_CAPSULE_ON_DISK=y CONFIG_EFI_CAPSULE_FIRMWARE_RAW=y +# CONFIG_ANDROID_BOOT_IMAGE is not set CONFIG_BOOTCOMMAND="bootflow scan -lb; run bsp_bootcmd" CONFIG_DEFAULT_FDT_FILE="imx93-11x11-frdm.dtb" CONFIG_SYS_CBSIZE=2048 @@ -58,6 +59,7 @@ CONFIG_CMD_ERASEENV=y CONFIG_CMD_NVEDIT_EFI=y # CONFIG_CMD_CRC32 is not set CONFIG_CMD_MEMTEST=y +# CONFIG_CMD_BIND is not set CONFIG_CMD_CLK=y CONFIG_CMD_DFU=y CONFIG_CMD_FUSE=y @@ -91,6 +93,11 @@ CONFIG_ADC_IMX93=y CONFIG_SPL_CLK_IMX93=y CONFIG_CLK_IMX93=y CONFIG_DFU_MMC=y +CONFIG_USB_FUNCTION_FASTBOOT=y +CONFIG_FASTBOOT_BUF_ADDR=0x82800000 +CONFIG_FASTBOOT_FLASH=y +CONFIG_FASTBOOT_UUU_SUPPORT=y +CONFIG_FASTBOOT_FLASH_MMC_DEV=0 CONFIG_IMX_RGPIO2P=y CONFIG_DM_PCA953X=y CONFIG_DM_I2C=y @@ -116,6 +123,13 @@ CONFIG_SYSRESET=y CONFIG_SYSRESET_CMD_POWEROFF=y CONFIG_SYSRESET_PSCI=y CONFIG_DM_THERMAL=y +CONFIG_USB=y +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_GADGET=y +CONFIG_USB_GADGET_MANUFACTURER="FSL" +CONFIG_USB_GADGET_VENDOR_NUM=0x0525 +CONFIG_USB_GADGET_PRODUCT_NUM=0x0152 +CONFIG_CI_UDC=y CONFIG_ULP_WATCHDOG=y CONFIG_WDT=y CONFIG_SHA384=y diff --git a/doc/board/nxp/imx93_frdm.rst b/doc/board/nxp/imx93_frdm.rst index a1f526fd4cc..3c3e5f49b04 100644 --- a/doc/board/nxp/imx93_frdm.rst +++ b/doc/board/nxp/imx93_frdm.rst @@ -13,6 +13,7 @@ Quick Start - Get ahab-container.img - Build U-Boot - Boot from the SD card +- Boot using USB serial download (uuu) Get and Build the ARM Trusted firmware -------------------------------------- @@ -73,3 +74,24 @@ Boot from the SD card at /dev/ttyACM0. - Power on the board by connecting a USB Type-C cable into the P1 Power USB Port. + +Boot using USB serial download (uuu) +------------------------------------ + +- Configure SW1 boot switches to serial download boot mode: + 0001 SW1[3:0] - ("Serial downloader (USB)" Boot Mode) +- Plug USB Type-C cable into the P2 device port. +- Connect a USB Type-C cable into the P16 Debug USB Port and connect + using a terminal emulator at 115200 bps, 8n1. The console will show up + at /dev/ttyACM0. +- Power on the board by connecting a USB Type-C cable into the P1 + Power USB Port. +- Use NXP Universal Update Utility `NXP Universal Update Utility`_ to boot or + flash the device. E.g. following command can be used to flash an image onto + the eMMC storage: + +.. code-block:: bash + + $ uuu -V -b emmc_all + +.. _`NXP Universal Update Utility`: https://github.com/nxp-imx/mfgtools -- cgit v1.2.3 From 2727de799a644f4db15e8682503f783a62fa4af2 Mon Sep 17 00:00:00 2001 From: Peng Fan Date: Tue, 16 Sep 2025 10:57:35 +0800 Subject: power: regulator: pfuze100: Fix accessing the regulator desc se_desc loop check is wrong, it relies on the desc always has the expected name to end of the loop. It works because the device tree has the expected name as of now, but this may not be always true. Drop se_desc by moving the check into probe and fix the loop check. Reported-by: Andrew Goodbody Cc: Tom Rini Cc: Fabio Estevam Signed-off-by: Peng Fan --- drivers/power/regulator/pfuze100.c | 44 +++++++++++++++----------------------- 1 file changed, 17 insertions(+), 27 deletions(-) diff --git a/drivers/power/regulator/pfuze100.c b/drivers/power/regulator/pfuze100.c index bf3a7019411..f864b1d8834 100644 --- a/drivers/power/regulator/pfuze100.c +++ b/drivers/power/regulator/pfuze100.c @@ -241,56 +241,46 @@ static struct dm_regulator_mode pfuze_ldo_modes[] = { MODE(LDO_MODE_ON, LDO_MODE_ON, "LDO_MODE_ON"), }; -static struct pfuze100_regulator_desc *se_desc(struct pfuze100_regulator_desc *desc, - int size, - const char *name) -{ - int i; - - for (i = 0; i < size; desc++) { - if (!strcmp(desc->name, name)) - return desc; - continue; - } - - return NULL; -} - static int pfuze100_regulator_probe(struct udevice *dev) { struct dm_regulator_uclass_plat *uc_pdata; struct pfuze100_regulator_plat *plat = dev_get_plat(dev); struct pfuze100_regulator_desc *desc; + int i, size; switch (dev_get_driver_data(dev_get_parent(dev))) { case PFUZE100: - desc = se_desc(pfuze100_regulators, - ARRAY_SIZE(pfuze100_regulators), - dev->name); + desc = pfuze100_regulators; + size = ARRAY_SIZE(pfuze100_regulators); break; case PFUZE200: - desc = se_desc(pfuze200_regulators, - ARRAY_SIZE(pfuze200_regulators), - dev->name); + desc = pfuze200_regulators; + size = ARRAY_SIZE(pfuze200_regulators); break; case PFUZE3000: - desc = se_desc(pfuze3000_regulators, - ARRAY_SIZE(pfuze3000_regulators), - dev->name); + desc = pfuze3000_regulators; + size = ARRAY_SIZE(pfuze3000_regulators); break; default: debug("Unsupported PFUZE\n"); return -EINVAL; } - if (!desc) { + + for (i = 0; i < size; i++) { + if (strcmp(desc[i].name, dev->name)) + continue; + break; + } + + if (i == size) { debug("Do not support regulator %s\n", dev->name); return -EINVAL; } - plat->desc = desc; + plat->desc = &desc[i]; uc_pdata = dev_get_uclass_plat(dev); - uc_pdata->type = desc->type; + uc_pdata->type = desc[i].type; if (uc_pdata->type == REGULATOR_TYPE_BUCK) { if (!strcmp(dev->name, "swbst")) { uc_pdata->mode = pfuze_swbst_modes; -- cgit v1.2.3 From edc666f1cf721c12ebc2fc096d362f8b14004d3a Mon Sep 17 00:00:00 2001 From: Ricardo Simoes Date: Wed, 17 Sep 2025 17:59:32 +0200 Subject: clk: imx6q: Add definition for missing PWM clocks Following the work done in commit 7f39ad5a ("clk: imx6q: Add definition for IMX6QDL_CLK_PWM1"), this commit adds definitions for PWM2, PWM3, and PWM4 clocks. Allowing one to use these PWM modules together with DM_CLK. Note that the solution was verified only against PWM3. Signed-off-by: Ricardo Simoes Signed-off-by: Mark Jonas --- drivers/clk/imx/clk-imx6q.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/drivers/clk/imx/clk-imx6q.c b/drivers/clk/imx/clk-imx6q.c index 13239f2f64d..b69355cefc7 100644 --- a/drivers/clk/imx/clk-imx6q.c +++ b/drivers/clk/imx/clk-imx6q.c @@ -156,6 +156,12 @@ static int imx6q_clk_probe(struct udevice *dev) imx_clk_gate2(dev, "i2c3", "ipg_per", base + 0x70, 10)); clk_dm(IMX6QDL_CLK_PWM1, imx_clk_gate2(dev, "pwm1", "ipg_per", base + 0x78, 16)); + clk_dm(IMX6QDL_CLK_PWM2, + imx_clk_gate2(dev, "pwm2", "ipg_per", base + 0x78, 18)); + clk_dm(IMX6QDL_CLK_PWM3, + imx_clk_gate2(dev, "pwm3", "ipg_per", base + 0x78, 20)); + clk_dm(IMX6QDL_CLK_PWM4, + imx_clk_gate2(dev, "pwm4", "ipg_per", base + 0x78, 22)); clk_dm(IMX6QDL_CLK_ENET, imx_clk_gate2(dev, "enet", "ipg", base + 0x6c, 10)); clk_dm(IMX6QDL_CLK_ENET_REF, -- cgit v1.2.3 From f7857695c914756f7c62dca23b3a675e779ae0f1 Mon Sep 17 00:00:00 2001 From: Yannic Moog Date: Thu, 18 Sep 2025 08:13:55 +0200 Subject: phytec-imx8m boards: enable OP-TEE for KASLR Enable OP-TEE config and RNG by default. Set OP-TEE load address to end of 1GiB RAM for phycore-imx8mp and phycore-imx8mm as the boards support a 1GiB RAM variant (although not yet upstreamed for phycore-imx8mm). The imx8mm-phygate-tauri-l board only supports 2GiB, so the default at the end of 2GiB is sufficient. Reviewed-by: Teresa Remmet Signed-off-by: Yannic Moog --- configs/imx8mm-phygate-tauri-l_defconfig | 5 ++++- configs/phycore-imx8mm_defconfig | 5 ++++- configs/phycore-imx8mp_defconfig | 4 ++++ 3 files changed, 12 insertions(+), 2 deletions(-) diff --git a/configs/imx8mm-phygate-tauri-l_defconfig b/configs/imx8mm-phygate-tauri-l_defconfig index 7369c0a05ac..6dc95d6d3ed 100644 --- a/configs/imx8mm-phygate-tauri-l_defconfig +++ b/configs/imx8mm-phygate-tauri-l_defconfig @@ -73,9 +73,9 @@ CONFIG_SPL_CLK_COMPOSITE_CCF=y CONFIG_CLK_COMPOSITE_CCF=y CONFIG_SPL_CLK_IMX8MM=y CONFIG_CLK_IMX8MM=y +CONFIG_FSL_CAAM=y CONFIG_MXC_GPIO=y CONFIG_DM_I2C=y -CONFIG_MISC=y CONFIG_I2C_EEPROM=y CONFIG_SYS_I2C_EEPROM_ADDR=0x51 CONFIG_SUPPORT_EMMC_BOOT=y @@ -97,11 +97,14 @@ CONFIG_IMX8M_POWER_DOMAIN=y CONFIG_DM_REGULATOR=y CONFIG_DM_REGULATOR_FIXED=y CONFIG_DM_REGULATOR_GPIO=y +CONFIG_DM_RNG=y CONFIG_DM_SERIAL=y CONFIG_MXC_UART=y CONFIG_SYSRESET=y CONFIG_SPL_SYSRESET=y CONFIG_SYSRESET_PSCI=y CONFIG_SYSRESET_WATCHDOG=y +CONFIG_TEE=y +CONFIG_OPTEE=y CONFIG_DM_THERMAL=y CONFIG_IMX_WATCHDOG=y diff --git a/configs/phycore-imx8mm_defconfig b/configs/phycore-imx8mm_defconfig index 4d6bce26f07..4cf4d397256 100644 --- a/configs/phycore-imx8mm_defconfig +++ b/configs/phycore-imx8mm_defconfig @@ -82,9 +82,9 @@ CONFIG_SPL_CLK_COMPOSITE_CCF=y CONFIG_CLK_COMPOSITE_CCF=y CONFIG_SPL_CLK_IMX8MM=y CONFIG_CLK_IMX8MM=y +CONFIG_FSL_CAAM=y CONFIG_MXC_GPIO=y CONFIG_DM_I2C=y -CONFIG_MISC=y CONFIG_I2C_EEPROM=y CONFIG_SYS_I2C_EEPROM_ADDR=0x51 CONFIG_SUPPORT_EMMC_BOOT=y @@ -120,6 +120,7 @@ CONFIG_POWER_DOMAIN=y CONFIG_IMX8M_POWER_DOMAIN=y CONFIG_DM_REGULATOR_FIXED=y CONFIG_DM_REGULATOR_GPIO=y +CONFIG_DM_RNG=y CONFIG_DM_SERIAL=y CONFIG_MXC_UART=y CONFIG_SPI=y @@ -129,5 +130,7 @@ CONFIG_SYSRESET=y CONFIG_SPL_SYSRESET=y CONFIG_SYSRESET_PSCI=y CONFIG_SYSRESET_WATCHDOG=y +CONFIG_TEE=y +CONFIG_OPTEE=y CONFIG_DM_THERMAL=y CONFIG_IMX_WATCHDOG=y diff --git a/configs/phycore-imx8mp_defconfig b/configs/phycore-imx8mp_defconfig index 6bd8bcf15da..c497f0bcd91 100644 --- a/configs/phycore-imx8mp_defconfig +++ b/configs/phycore-imx8mp_defconfig @@ -13,6 +13,7 @@ CONFIG_ENV_SECT_SIZE=0x10000 CONFIG_SYS_I2C_MXC_I2C1=y CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="freescale/imx8mp-phyboard-pollux-rdk" +CONFIG_IMX8M_OPTEE_LOAD_ADDR=0x7e000000 CONFIG_TARGET_PHYCORE_IMX8MP=y CONFIG_OF_LIBFDT_OVERLAY=y CONFIG_SYS_MONITOR_LEN=524288 @@ -153,6 +154,7 @@ CONFIG_DM_REGULATOR=y CONFIG_DM_REGULATOR_FIXED=y CONFIG_DM_REGULATOR_GPIO=y CONFIG_SPL_POWER_I2C=y +CONFIG_DM_RNG=y CONFIG_DM_SERIAL=y CONFIG_MXC_UART=y CONFIG_SPI=y @@ -162,6 +164,8 @@ CONFIG_SYSRESET=y CONFIG_SPL_SYSRESET=y CONFIG_SYSRESET_PSCI=y CONFIG_SYSRESET_WATCHDOG=y +CONFIG_TEE=y +CONFIG_OPTEE=y CONFIG_DM_THERMAL=y CONFIG_USB=y CONFIG_DM_USB_GADGET=y -- cgit v1.2.3 From cb1292450d89391b56e83e00e4520935f95d403e Mon Sep 17 00:00:00 2001 From: Yannic Moog Date: Thu, 18 Sep 2025 08:13:56 +0200 Subject: doc: phytec: update imx8m docs for optee builds OP-TEE configs are enabled by default, change the doc to no longer declare OP-TEE as optional. Also remove CFG_TEE_BENCHMARK as it is no longer present in optee_os. Further, phycore-imx8mm and imx8mm-phygate-tauri-l use different build instructions, so dissolve the common file for building OP-TEE. Reviewed-by: Teresa Remmet Signed-off-by: Yannic Moog --- board/phytec/phycore_imx8mm/MAINTAINERS | 1 - doc/board/phytec/imx8mm-optee-build.rsti | 14 -------------- doc/board/phytec/imx8mm-phygate-tauri-l.rst | 18 ++++++++++++------ doc/board/phytec/imx8mp-libra-fpsc.rst | 1 - doc/board/phytec/phycore-imx8mm.rst | 18 ++++++++++++------ doc/board/phytec/phycore-imx8mp.rst | 16 ++++++---------- 6 files changed, 30 insertions(+), 38 deletions(-) delete mode 100644 doc/board/phytec/imx8mm-optee-build.rsti diff --git a/board/phytec/phycore_imx8mm/MAINTAINERS b/board/phytec/phycore_imx8mm/MAINTAINERS index 7631e1cb331..58c5e2d0af9 100644 --- a/board/phytec/phycore_imx8mm/MAINTAINERS +++ b/board/phytec/phycore_imx8mm/MAINTAINERS @@ -9,6 +9,5 @@ F: configs/imx8mm-phygate-tauri-l_defconfig F: configs/phycore-imx8mm_defconfig F: doc/board/phytec/imx8mm-phygate-tauri-l.rst F: doc/board/phytec/index.rst -F: doc/board/phytec/imx8mm-optee-build.rsti F: doc/board/phytec/phycore_imx8mm.rst F: include/configs/phycore_imx8mm.h diff --git a/doc/board/phytec/imx8mm-optee-build.rsti b/doc/board/phytec/imx8mm-optee-build.rsti deleted file mode 100644 index c83de5cc7cf..00000000000 --- a/doc/board/phytec/imx8mm-optee-build.rsti +++ /dev/null @@ -1,14 +0,0 @@ -Build the OP-TEE binary (optional) ----------------------------------- - -.. code-block:: bash - - $ git clone https://github.com/OP-TEE/optee_os.git - $ cd optee_os - $ make CFG_TEE_BENCHMARK=n \ - CROSS_COMPILE=aarch64-linux-gnu- \ - O=out/arm \ - PLATFORM=imx-mx8mmevk \ - CFG_TZDRAM_START=0x56000000 \ - CFG_DDR_SIZE=0x80000000 \ - CFG_UART_BASE=UART3_BASE diff --git a/doc/board/phytec/imx8mm-phygate-tauri-l.rst b/doc/board/phytec/imx8mm-phygate-tauri-l.rst index 0d9e1024f8c..bc58a141e4f 100644 --- a/doc/board/phytec/imx8mm-phygate-tauri-l.rst +++ b/doc/board/phytec/imx8mm-phygate-tauri-l.rst @@ -9,7 +9,7 @@ Quick Start ----------- - Build the ARM Trusted firmware binary -- Build the OP-TEE binary (optional) +- Build the OP-TEE binary - Get ddr firmware - Build U-Boot - Boot @@ -23,12 +23,18 @@ Build the ARM Trusted firmware binary $ cd trusted-firmware-a $ export CROSS_COMPILE=aarch64-linux-gnu- $ export IMX_BOOT_UART_BASE=0x30880000 - $ # with optee - $ make PLAT=imx8mm BL32_BASE=0x56000000 SPD=opteed bl31 - $ # without optee - $ make PLAT=imx8mm bl31 + $ make PLAT=imx8mm BL32_BASE=0xbe000000 SPD=opteed bl31 -.. include:: imx8mm-optee-build.rsti +Build the OP-TEE binary +----------------------- + +.. code-block:: bash + + $ git clone https://github.com/OP-TEE/optee_os.git + $ cd optee_os + $ make CROSS_COMPILE=aarch64-linux-gnu- \ + O=out/arm \ + PLATFORM=imx-mx8mm_phygate_tauri_l Get the ddr firmware -------------------- diff --git a/doc/board/phytec/imx8mp-libra-fpsc.rst b/doc/board/phytec/imx8mp-libra-fpsc.rst index 26752ac1882..87b7a99ee71 100644 --- a/doc/board/phytec/imx8mp-libra-fpsc.rst +++ b/doc/board/phytec/imx8mp-libra-fpsc.rst @@ -40,7 +40,6 @@ Build the OP-TEE binary $ cd optee_os $ make -j $(nproc) \ CROSS_COMPILE=aarch64-linux-gnu- \ - CFG_TEE_BENCHMARK=n \ O=out/arm \ PLATFORM=imx-mx8mp_libra_fpsc diff --git a/doc/board/phytec/phycore-imx8mm.rst b/doc/board/phytec/phycore-imx8mm.rst index 08f5949e02d..f8fa420019c 100644 --- a/doc/board/phytec/phycore-imx8mm.rst +++ b/doc/board/phytec/phycore-imx8mm.rst @@ -9,7 +9,7 @@ Quick Start ----------- - Build the ARM Trusted firmware binary -- Build the OP-TEE binary (optional) +- Build the OP-TEE binary - Get ddr firmware - Build U-Boot - Boot @@ -23,12 +23,18 @@ Build the ARM Trusted firmware binary $ cd trusted-firmware-a $ export CROSS_COMPILE=aarch64-linux-gnu- $ export IMX_BOOT_UART_BASE=0x30880000 - $ # with optee - $ make PLAT=imx8mm BL32_BASE=0x56000000 SPD=opteed bl31 - $ # without optee - $ make PLAT=imx8mm bl31 + $ make PLAT=imx8mm BL32_BASE=0x7e000000 SPD=opteed bl31 -.. include:: imx8mm-optee-build.rsti +Build the OP-TEE binary +----------------------- + +.. code-block:: bash + + $ git clone https://github.com/OP-TEE/optee_os.git + $ cd optee_os + $ make CROSS_COMPILE=aarch64-linux-gnu- \ + O=out/arm \ + PLATFORM=imx-mx8mm_phyboard_polis Get the ddr firmware -------------------- diff --git a/doc/board/phytec/phycore-imx8mp.rst b/doc/board/phytec/phycore-imx8mp.rst index 50be9912653..df087072062 100644 --- a/doc/board/phytec/phycore-imx8mp.rst +++ b/doc/board/phytec/phycore-imx8mp.rst @@ -9,7 +9,7 @@ Quick Start ----------- - Build the ARM Trusted firmware binary -- Build the OP-TEE binary (optional) +- Build the OP-TEE binary - Get ddr firmware - Build U-Boot - Boot @@ -23,23 +23,19 @@ Build the ARM Trusted firmware binary $ cd trusted-firmware-a $ export CROSS_COMPILE=aarch64-linux-gnu- $ export IMX_BOOT_UART_BASE=0x30860000 - $ # with optee - $ make PLAT=imx8mp SPD=opteed bl31 - $ # without optee - $ make PLAT=imx8mp bl31 + $ make PLAT=imx8mp BL32_BASE=0x7e000000 SPD=opteed bl31 -Build the OP-TEE binary (optional) ----------------------------------- +Build the OP-TEE binary +----------------------- .. code-block:: bash $ git clone https://github.com/OP-TEE/optee_os.git $ cd optee_os - $ make CFG_TEE_BENCHMARK=n \ - CROSS_COMPILE=aarch64-linux-gnu- \ + $ make CROSS_COMPILE=aarch64-linux-gnu- \ O=out/arm \ PLATFORM=imx-mx8mp_phyboard_pollux \ - CFG_TZDRAM_START=0x56000000 + CFG_TZDRAM_START=0x7e000000 Get the ddr firmware -------------------- -- cgit v1.2.3 From db6487861ae87e07db97b6e5ad0de901c483084c Mon Sep 17 00:00:00 2001 From: Yannic Moog Date: Thu, 18 Sep 2025 08:13:57 +0200 Subject: doc: phytec: imx8m: Style and firmware update Use single make command for compiling blobs and U-Boot. Update the imx firmware version. Signed-off-by: Yannic Moog --- doc/board/phytec/imx8mm-phygate-tauri-l.rst | 27 ++++++++++++++--------- doc/board/phytec/phycore-imx8mm.rst | 28 +++++++++++++++--------- doc/board/phytec/phycore-imx8mp.rst | 34 +++++++++++++++++------------ 3 files changed, 55 insertions(+), 34 deletions(-) diff --git a/doc/board/phytec/imx8mm-phygate-tauri-l.rst b/doc/board/phytec/imx8mm-phygate-tauri-l.rst index bc58a141e4f..3a09be7075a 100644 --- a/doc/board/phytec/imx8mm-phygate-tauri-l.rst +++ b/doc/board/phytec/imx8mm-phygate-tauri-l.rst @@ -21,9 +21,13 @@ Build the ARM Trusted firmware binary $ git clone https://git.trustedfirmware.org/TF-A/trusted-firmware-a.git $ cd trusted-firmware-a - $ export CROSS_COMPILE=aarch64-linux-gnu- - $ export IMX_BOOT_UART_BASE=0x30880000 - $ make PLAT=imx8mm BL32_BASE=0xbe000000 SPD=opteed bl31 + $ make -j $(nproc) \ + CROSS_COMPILE=aarch64-linux-gnu- \ + PLAT=imx8mm \ + IMX_BOOT_UART_BASE=0x30880000 \ + BL32_BASE=0xbe000000 \ + SPD=opteed \ + bl31 Build the OP-TEE binary ----------------------- @@ -32,7 +36,8 @@ Build the OP-TEE binary $ git clone https://github.com/OP-TEE/optee_os.git $ cd optee_os - $ make CROSS_COMPILE=aarch64-linux-gnu- \ + $ make -j $(nproc) \ + CROSS_COMPILE=aarch64-linux-gnu- \ O=out/arm \ PLATFORM=imx-mx8mm_phygate_tauri_l @@ -41,9 +46,9 @@ Get the ddr firmware .. code-block:: bash - $ wget https://www.nxp.com/lgfiles/NMG/MAD/YOCTO/firmware-imx-8.23.bin - $ chmod +x firmware-imx-8.23.bin - $ ./firmware-imx-8.23.bin + $ wget https://www.nxp.com/lgfiles/NMG/MAD/YOCTO/firmware-imx-8.28-994fa14.bin + $ chmod +x firmware-imx-8.28-994fa14.bin + $ ./firmware-imx-8.28-994fa14.bin Build U-Boot for SD card ------------------------ @@ -55,15 +60,17 @@ Copy binaries $ cp /build/imx8mm/release/bl31.bin . $ cp /out/arm/core/tee-raw.bin tee.bin - $ cp firmware-imx-8.23/firmware/ddr/synopsys/lpddr4*.bin . + $ cp firmware-imx-8.28-994fa14/firmware/ddr/synopsys/lpddr4*.bin . Build U-Boot ^^^^^^^^^^^^ .. code-block:: bash - $ make imx8mm-phygate-tauri-l_defconfig - $ make flash.bin + $ make -j $(nproc) + CROSS_COMPILE=aarch64-linux-gnu- \ + imx8mm-phygate-tauri-l_defconfig \ + flash.bin Flash SD card ^^^^^^^^^^^^^ diff --git a/doc/board/phytec/phycore-imx8mm.rst b/doc/board/phytec/phycore-imx8mm.rst index f8fa420019c..0784154e710 100644 --- a/doc/board/phytec/phycore-imx8mm.rst +++ b/doc/board/phytec/phycore-imx8mm.rst @@ -21,9 +21,13 @@ Build the ARM Trusted firmware binary $ git clone https://git.trustedfirmware.org/TF-A/trusted-firmware-a.git $ cd trusted-firmware-a - $ export CROSS_COMPILE=aarch64-linux-gnu- - $ export IMX_BOOT_UART_BASE=0x30880000 - $ make PLAT=imx8mm BL32_BASE=0x7e000000 SPD=opteed bl31 + $ make -j $(nproc) \ + CROSS_COMPILE=aarch64-linux-gnu- \ + PLAT=imx8mm \ + IMX_BOOT_UART_BASE=0x30880000 \ + BL32_BASE=0x7e000000 \ + SPD=opteed \ + bl31 Build the OP-TEE binary ----------------------- @@ -32,7 +36,8 @@ Build the OP-TEE binary $ git clone https://github.com/OP-TEE/optee_os.git $ cd optee_os - $ make CROSS_COMPILE=aarch64-linux-gnu- \ + $ make -j $(nproc) \ + CROSS_COMPILE=aarch64-linux-gnu- \ O=out/arm \ PLATFORM=imx-mx8mm_phyboard_polis @@ -41,9 +46,9 @@ Get the ddr firmware .. code-block:: bash - $ wget https://www.nxp.com/lgfiles/NMG/MAD/YOCTO/firmware-imx-8.19.bin - $ chmod +x firmware-imx-8.19.bin - $ ./firmware-imx-8.19.bin + $ wget https://www.nxp.com/lgfiles/NMG/MAD/YOCTO/firmware-imx-8.28-994fa14.bin + $ chmod +x firmware-imx-8.28-994fa14.bin + $ ./firmware-imx-8.28-994fa14.bin Build U-Boot for SD card ------------------------ @@ -54,15 +59,18 @@ Copy binaries .. code-block:: bash $ cp /build/imx8mm/release/bl31.bin . - $ cp firmware-imx-8.19/firmware/ddr/synopsys/lpddr4*.bin . + $ cp /out/arm/core/tee-raw.bin tee.bin + $ cp firmware-imx-8.28-994fa14/firmware/ddr/synopsys/lpddr4*.bin . Build U-Boot ^^^^^^^^^^^^ .. code-block:: bash - $ make phycore-imx8mm_defconfig - $ make flash.bin + $ make -j $(nproc) \ + CROSS_COMPILE=aarch64-linux-gnu- \ + phycore-imx8mm_defconfig \ + flash.bin Flash SD card ^^^^^^^^^^^^^ diff --git a/doc/board/phytec/phycore-imx8mp.rst b/doc/board/phytec/phycore-imx8mp.rst index df087072062..0252cbd0824 100644 --- a/doc/board/phytec/phycore-imx8mp.rst +++ b/doc/board/phytec/phycore-imx8mp.rst @@ -3,7 +3,7 @@ phyCORE-i.MX 8M Plus ==================== -The phyCORE-i.MX 8M Plus with 2GB of main memory is supported. +The phyCORE-i.MX 8M Plus with 1,2,4GB of main memory is supported. Quick Start ----------- @@ -21,9 +21,13 @@ Build the ARM Trusted firmware binary $ git clone https://git.trustedfirmware.org/TF-A/trusted-firmware-a.git $ cd trusted-firmware-a - $ export CROSS_COMPILE=aarch64-linux-gnu- - $ export IMX_BOOT_UART_BASE=0x30860000 - $ make PLAT=imx8mp BL32_BASE=0x7e000000 SPD=opteed bl31 + $ make -j $(nproc) \ + CROSS_COMPILE=aarch64-linux-gnu- \ + PLAT=imx8mp \ + IMX_BOOT_UART_BASE=0x30860000 \ + BL32_BASE=0x7e000000 \ + SPD=opteed \ + bl31 Build the OP-TEE binary ----------------------- @@ -32,19 +36,19 @@ Build the OP-TEE binary $ git clone https://github.com/OP-TEE/optee_os.git $ cd optee_os - $ make CROSS_COMPILE=aarch64-linux-gnu- \ - O=out/arm \ - PLATFORM=imx-mx8mp_phyboard_pollux \ - CFG_TZDRAM_START=0x7e000000 + $ make -j $(nproc) \ + CROSS_COMPILE=aarch64-linux-gnu- \ + O=out/arm \ + PLATFORM=imx-mx8mp_phyboard_pollux Get the ddr firmware -------------------- .. code-block:: bash - $ wget https://www.nxp.com/lgfiles/NMG/MAD/YOCTO/firmware-imx-8.19.bin - $ chmod +x firmware-imx-8.19.bin - $ ./firmware-imx-8.19.bin + $ wget https://www.nxp.com/lgfiles/NMG/MAD/YOCTO/firmware-imx-8.28-994fa14.bin + $ chmod +x firmware-imx-8.28-994fa14.bin + $ ./firmware-imx-8.28-994fa14.bin Build U-Boot for SD card ------------------------ @@ -56,15 +60,17 @@ Copy binaries $ cp /build/imx8mp/release/bl31.bin . $ cp /out/arm/core/tee-raw.bin tee.bin - $ cp firmware-imx-8.19/firmware/ddr/synopsys/lpddr4*.bin . + $ cp firmware-imx-8.28-994fa14/firmware/ddr/synopsys/lpddr4*.bin . Build U-Boot ^^^^^^^^^^^^ .. code-block:: bash - $ make phycore-imx8mp_defconfig - $ make flash.bin + $ make -j $(nproc) \ + CROSS_COMPILE=aarch64-linux-gnu- \ + phycore-imx8mp_defconfig \ + flash.bin Flash SD card ^^^^^^^^^^^^^ -- cgit v1.2.3 From 88392a59bf87bf2c1c5aedc0b76f459d702f71a7 Mon Sep 17 00:00:00 2001 From: Aristo Chen Date: Sun, 14 Sep 2025 10:59:26 +0000 Subject: binman: Fix typo for the test case name Fix typo from `Singature` to `Signature` Signed-off-by: Aristo Chen Reviewed-by: Dhruva Gole --- tools/binman/ftest.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/tools/binman/ftest.py b/tools/binman/ftest.py index a90db3c9351..6ed8b8637cd 100644 --- a/tools/binman/ftest.py +++ b/tools/binman/ftest.py @@ -7986,7 +7986,7 @@ fdt fdtmap Extract the devicetree blob from the fdtmap 'Node \'/binman/fit\': multiple key paths found', str(e.exception)) - def testFitSignNoSingatureNodes(self): + def testFitSignNoSignatureNodes(self): """Test that fit,sign doens't raise error if no signature nodes found""" if not elf.ELF_TOOLS: self.skipTest('Python elftools not available') -- cgit v1.2.3 From dade54edaff659c4ed6fc40db0b2dd446714c573 Mon Sep 17 00:00:00 2001 From: Aristo Chen Date: Sun, 14 Sep 2025 10:59:27 +0000 Subject: binman: Fix FIT image overlap issues Fix three binman tests that has memory region overlap issue, the test cases needed to be updated to use non-overlapping memory layouts. * Tests fixed: - testFitFirmwareLoadables - testFitSignSimple - testFitSignNoSignatureNodes * Changes made: Updated DTB test files to change U-Boot load addresses from 0x0 to 0x2000 to avoid overlapping with ATF in the 0x10-0xfc range: - 276_fit_firmware_loadables.dts - 340_fit_signature.dts - 342_fit_signature.dts An upcoming commit will validate if the memory region is overlapped Signed-off-by: Aristo Chen Reviewed-by: Neha Malcom Francis --- tools/binman/test/276_fit_firmware_loadables.dts | 4 ++-- tools/binman/test/340_fit_signature.dts | 4 ++-- tools/binman/test/342_fit_signature.dts | 4 ++-- 3 files changed, 6 insertions(+), 6 deletions(-) diff --git a/tools/binman/test/276_fit_firmware_loadables.dts b/tools/binman/test/276_fit_firmware_loadables.dts index 2f79cdc9bb8..d344036a11a 100644 --- a/tools/binman/test/276_fit_firmware_loadables.dts +++ b/tools/binman/test/276_fit_firmware_loadables.dts @@ -19,8 +19,8 @@ arch = "arm64"; os = "u-boot"; compression = "none"; - load = <0x00000000>; - entry = <0x00000000>; + load = <0x00002000>; + entry = <0x00002000>; u-boot-nodtb { }; diff --git a/tools/binman/test/340_fit_signature.dts b/tools/binman/test/340_fit_signature.dts index 9dce62e52de..1c25d52cba4 100644 --- a/tools/binman/test/340_fit_signature.dts +++ b/tools/binman/test/340_fit_signature.dts @@ -20,8 +20,8 @@ arch = "arm64"; os = "u-boot"; compression = "none"; - load = <0x00000000>; - entry = <0x00000000>; + load = <0x00002000>; + entry = <0x00002000>; u-boot-nodtb { }; diff --git a/tools/binman/test/342_fit_signature.dts b/tools/binman/test/342_fit_signature.dts index 267105d0f68..2ac600b1c70 100644 --- a/tools/binman/test/342_fit_signature.dts +++ b/tools/binman/test/342_fit_signature.dts @@ -20,8 +20,8 @@ arch = "arm64"; os = "u-boot"; compression = "none"; - load = <0x00000000>; - entry = <0x00000000>; + load = <0x00002000>; + entry = <0x00002000>; u-boot-nodtb { }; -- cgit v1.2.3 From a06733fc83f07dd975a9e220a44392f3455c7c21 Mon Sep 17 00:00:00 2001 From: Aristo Chen Date: Sun, 14 Sep 2025 10:59:28 +0000 Subject: binman: Fix FIT image overlap issues for testFitSplitElf Fix one binman test that has memory region overlap issue, the test case needed to be updated to use non-overlapping memory layouts. * Tests fixed: - testFitSplitElf * Changes made: 1. ELF section layouts: added elf_sections_tee.lds with different address for TEE to avoid overlap with ATF address defined in elf_sections.lds 2. Makefile to properly build elf_sections_tee binary 3. Updat ftest.py to use separate ELF files for TEE vs ATF components in split-elf operations. An upcoming commit will validate if the memory region is overlapped Signed-off-by: Aristo Chen --- tools/binman/ftest.py | 2 +- tools/binman/test/Makefile | 6 +++++- tools/binman/test/elf_sections_tee.c | 1 + tools/binman/test/elf_sections_tee.lds | 32 ++++++++++++++++++++++++++++++++ 4 files changed, 39 insertions(+), 2 deletions(-) create mode 120000 tools/binman/test/elf_sections_tee.c create mode 100644 tools/binman/test/elf_sections_tee.lds diff --git a/tools/binman/ftest.py b/tools/binman/ftest.py index 6ed8b8637cd..0252b175242 100644 --- a/tools/binman/ftest.py +++ b/tools/binman/ftest.py @@ -252,7 +252,7 @@ class TestFunctional(unittest.TestCase): TestFunctional._MakeInputFile('bl31.elf', tools.read_file(cls.ElfTestFile('elf_sections'))) TestFunctional.tee_elf_path = TestFunctional._MakeInputFile('tee.elf', - tools.read_file(cls.ElfTestFile('elf_sections'))) + tools.read_file(cls.ElfTestFile('elf_sections_tee'))) # Newer OP_TEE file in v1 binary format cls.make_tee_bin('tee.bin') diff --git a/tools/binman/test/Makefile b/tools/binman/test/Makefile index 4d152eee9c0..66279e0e207 100644 --- a/tools/binman/test/Makefile +++ b/tools/binman/test/Makefile @@ -30,12 +30,13 @@ LDS_BINMAN_BAD := -T $(SRC)u_boot_binman_syms_bad.lds LDS_BINMAN_X86 := -T $(SRC)u_boot_binman_syms_x86.lds LDS_BINMAN_EMBED := -T $(SRC)u_boot_binman_embed.lds LDS_EFL_SECTIONS := -T $(SRC)elf_sections.lds +LDS_EFL_SECTIONS_TEE := -T $(SRC)elf_sections_tee.lds LDS_BLOB := -T $(SRC)blob_syms.lds TARGETS = u_boot_ucode_ptr u_boot_no_ucode_ptr bss_data bss_data_zero \ u_boot_binman_syms u_boot_binman_syms.bin u_boot_binman_syms_bad \ u_boot_binman_syms_size u_boot_binman_syms_x86 embed_data \ - u_boot_binman_embed u_boot_binman_embed_sm elf_sections blob_syms.bin + u_boot_binman_embed u_boot_binman_embed_sm elf_sections elf_sections_tee blob_syms.bin all: $(TARGETS) @@ -84,6 +85,9 @@ blob_syms: blob_syms.c elf_sections: CFLAGS += $(LDS_EFL_SECTIONS) elf_sections: elf_sections.c +elf_sections_tee: CFLAGS += $(LDS_EFL_SECTIONS_TEE) +elf_sections_tee: elf_sections_tee.c + clean: rm -f $(TARGETS) diff --git a/tools/binman/test/elf_sections_tee.c b/tools/binman/test/elf_sections_tee.c new file mode 120000 index 00000000000..01b200a365e --- /dev/null +++ b/tools/binman/test/elf_sections_tee.c @@ -0,0 +1 @@ +elf_sections.c \ No newline at end of file diff --git a/tools/binman/test/elf_sections_tee.lds b/tools/binman/test/elf_sections_tee.lds new file mode 100644 index 00000000000..97e5e5f5d94 --- /dev/null +++ b/tools/binman/test/elf_sections_tee.lds @@ -0,0 +1,32 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (c) 2016 Google, Inc + * Copyright (c) 2025 Canonical Ltd. + */ + +OUTPUT_FORMAT("elf32-i386", "elf32-i386", "elf32-i386") +OUTPUT_ARCH(i386) +ENTRY(_start) + +SECTIONS +{ + . = 0x00100010; + _start = .; + + . = ALIGN(4); + .text : + { + *(.text*) + } + + . = 0x00101000; + .sram : + { + *(.sram*) + } + + /DISCARD/ : { + *(.comment) + *(.dyn*) + } +} -- cgit v1.2.3 From cbc4da1dce3f8dd828a2e613676fdceefd87e1ea Mon Sep 17 00:00:00 2001 From: Aristo Chen Date: Sun, 14 Sep 2025 10:59:29 +0000 Subject: arm: dts: k3-am6xx: Fix FIT image memory overlap in binman configurations Fix memory overlaps in FIT image configurations for TI AM62x and AM64x PHYCore and SK boards. The overlaps occurred in two categories: 1. TI firmware stub images (tifsstub-hs, tifsstub-fs, tifsstub-gp): These mutually exclusive firmware variants were incorrectly assigned the same load address within FIT configurations, causing overlap detection to fail. Adjust addresses with 64KB spacing: - tifsstub-hs: Keep original address - tifsstub-fs: Move to +64KB offset - tifsstub-gp: Move to +128KB offset 2. Device tree overlay images (som-no-rtc, som-no-spi, som-no-eth): These overlay files had insufficient spacing between load addresses, causing actual memory overlaps. Increase spacing to 8KB boundaries to accommodate overlay sizes safely. An upcoming commit will validate if the memory region is overlapped Signed-off-by: Aristo Chen --- arch/arm/dts/k3-am625-phycore-som-binman.dtsi | 22 +++++++++++----------- arch/arm/dts/k3-am625-sk-binman.dtsi | 16 ++++++++-------- arch/arm/dts/k3-am625-verdin-wifi-dev-binman.dtsi | 16 ++++++++-------- arch/arm/dts/k3-am62a-phycore-som-binman.dtsi | 10 +++++----- arch/arm/dts/k3-am62a-sk-binman.dtsi | 4 ++-- arch/arm/dts/k3-am642-phycore-som-binman.dtsi | 6 +++--- 6 files changed, 37 insertions(+), 37 deletions(-) diff --git a/arch/arm/dts/k3-am625-phycore-som-binman.dtsi b/arch/arm/dts/k3-am625-phycore-som-binman.dtsi index a9bd5a2be84..4344cefeba3 100644 --- a/arch/arm/dts/k3-am625-phycore-som-binman.dtsi +++ b/arch/arm/dts/k3-am625-phycore-som-binman.dtsi @@ -234,8 +234,8 @@ arch = "arm32"; compression = "none"; os = "tifsstub-fs"; - load = <0x9dc00000>; - entry = <0x9dc00000>; + load = <0x9dc10000>; + entry = <0x9dc10000>; blob-ext { filename = "tifsstub.bin_fs"; }; @@ -247,8 +247,8 @@ arch = "arm32"; compression = "none"; os = "tifsstub-gp"; - load = <0x9dc00000>; - entry = <0x9dc00000>; + load = <0x9dc20000>; + entry = <0x9dc20000>; blob-ext { filename = "tifsstub.bin_gp"; }; @@ -322,7 +322,7 @@ description = "k3-am6xx-phycore-disable-spi-nor"; type = "flat_dt"; compression = "none"; - load = <0x8F001000>; + load = <0x8F002000>; arch = "arm"; ti-secure { content = <&am6xx_phycore_disable_spi_not_dtbo>; @@ -337,7 +337,7 @@ description = "k3-am6xx-phycore-disable-eth-phy"; type = "flat_dt"; compression = "none"; - load = <0x8F002000>; + load = <0x8F004000>; arch = "arm"; ti-secure { content = <&am6xx_phycore_disable_eth_phy_dtbo>; @@ -352,7 +352,7 @@ description = "k3-am6xx-phycore-qspi-nor"; type = "flat_dt"; compression = "none"; - load = <0x8F003000>; + load = <0x8F006000>; arch = "arm"; ti-secure { content = <&am6xx_phycore_disable_qspi_nor_dtbo>; @@ -479,8 +479,8 @@ arch = "arm32"; compression = "none"; os = "tifsstub-fs"; - load = <0x9dc00000>; - entry = <0x9dc00000>; + load = <0x9dc10000>; + entry = <0x9dc10000>; blob-ext { filename = "tifsstub.bin_fs"; }; @@ -492,8 +492,8 @@ arch = "arm32"; compression = "none"; os = "tifsstub-gp"; - load = <0x9dc00000>; - entry = <0x9dc00000>; + load = <0x9dc20000>; + entry = <0x9dc20000>; blob-ext { filename = "tifsstub.bin_gp"; }; diff --git a/arch/arm/dts/k3-am625-sk-binman.dtsi b/arch/arm/dts/k3-am625-sk-binman.dtsi index f743c4353b4..1619f733a0d 100644 --- a/arch/arm/dts/k3-am625-sk-binman.dtsi +++ b/arch/arm/dts/k3-am625-sk-binman.dtsi @@ -231,8 +231,8 @@ arch = "arm32"; compression = "none"; os = "tifsstub-fs"; - load = <0x9dc00000>; - entry = <0x9dc00000>; + load = <0x9dc10000>; + entry = <0x9dc10000>; blob-ext { filename = "tifsstub.bin_fs"; }; @@ -244,8 +244,8 @@ arch = "arm32"; compression = "none"; os = "tifsstub-gp"; - load = <0x9dc00000>; - entry = <0x9dc00000>; + load = <0x9dc20000>; + entry = <0x9dc20000>; blob-ext { filename = "tifsstub.bin_gp"; }; @@ -362,8 +362,8 @@ arch = "arm32"; compression = "none"; os = "tifsstub-fs"; - load = <0x9dc00000>; - entry = <0x9dc00000>; + load = <0x9dc10000>; + entry = <0x9dc10000>; blob-ext { filename = "tifsstub.bin_fs"; }; @@ -375,8 +375,8 @@ arch = "arm32"; compression = "none"; os = "tifsstub-gp"; - load = <0x9dc00000>; - entry = <0x9dc00000>; + load = <0x9dc20000>; + entry = <0x9dc20000>; blob-ext { filename = "tifsstub.bin_gp"; }; diff --git a/arch/arm/dts/k3-am625-verdin-wifi-dev-binman.dtsi b/arch/arm/dts/k3-am625-verdin-wifi-dev-binman.dtsi index 65fef6e4790..6c4ad72d936 100644 --- a/arch/arm/dts/k3-am625-verdin-wifi-dev-binman.dtsi +++ b/arch/arm/dts/k3-am625-verdin-wifi-dev-binman.dtsi @@ -219,8 +219,8 @@ arch = "arm32"; compression = "none"; os = "tifsstub-fs"; - load = <0x9dc00000>; - entry = <0x9dc00000>; + load = <0x9dc10000>; + entry = <0x9dc10000>; blob-ext { filename = "tifsstub.bin_fs"; }; @@ -232,8 +232,8 @@ arch = "arm32"; compression = "none"; os = "tifsstub-gp"; - load = <0x9dc00000>; - entry = <0x9dc00000>; + load = <0x9dc20000>; + entry = <0x9dc20000>; blob-ext { filename = "tifsstub.bin_gp"; }; @@ -346,8 +346,8 @@ arch = "arm32"; compression = "none"; os = "tifsstub-fs"; - load = <0x9dc00000>; - entry = <0x9dc00000>; + load = <0x9dc10000>; + entry = <0x9dc10000>; blob-ext { filename = "tifsstub.bin_fs"; }; @@ -359,8 +359,8 @@ arch = "arm32"; compression = "none"; os = "tifsstub-gp"; - load = <0x9dc00000>; - entry = <0x9dc00000>; + load = <0x9dc20000>; + entry = <0x9dc20000>; blob-ext { filename = "tifsstub.bin_gp"; }; diff --git a/arch/arm/dts/k3-am62a-phycore-som-binman.dtsi b/arch/arm/dts/k3-am62a-phycore-som-binman.dtsi index a284226320c..786c7a2d458 100644 --- a/arch/arm/dts/k3-am62a-phycore-som-binman.dtsi +++ b/arch/arm/dts/k3-am62a-phycore-som-binman.dtsi @@ -184,8 +184,8 @@ arch = "arm32"; compression = "none"; os = "tifsstub-fs"; - load = <0x9ca00000>; - entry = <0x9ca00000>; + load = <0x9ca10000>; + entry = <0x9ca10000>; blob-ext { filename = "tifsstub.bin_fs"; }; @@ -260,7 +260,7 @@ description = "k3-am6xx-phycore-disable-spi-nor"; type = "flat_dt"; compression = "none"; - load = <0x8F001000>; + load = <0x8F002000>; arch = "arm"; ti-secure { content = <&am6xx_phycore_disable_spi_not_dtbo>; @@ -275,7 +275,7 @@ description = "k3-am6xx-phycore-disable-eth-phy"; type = "flat_dt"; compression = "none"; - load = <0x8F002000>; + load = <0x8F004000>; arch = "arm"; ti-secure { content = <&am6xx_phycore_disable_eth_phy_dtbo>; @@ -290,7 +290,7 @@ description = "k3-am6xx-phycore-qspi-nor"; type = "flat_dt"; compression = "none"; - load = <0x8F003000>; + load = <0x8F006000>; arch = "arm"; ti-secure { content = <&am6xx_phycore_disable_qspi_nor_dtbo>; diff --git a/arch/arm/dts/k3-am62a-sk-binman.dtsi b/arch/arm/dts/k3-am62a-sk-binman.dtsi index e64c165ecbf..214acd7f0f7 100644 --- a/arch/arm/dts/k3-am62a-sk-binman.dtsi +++ b/arch/arm/dts/k3-am62a-sk-binman.dtsi @@ -168,8 +168,8 @@ arch = "arm32"; compression = "none"; os = "tifsstub-fs"; - load = <0x9ca00000>; - entry = <0x9ca00000>; + load = <0x9ca10000>; + entry = <0x9ca10000>; blob-ext { filename = "tifsstub.bin_fs"; }; diff --git a/arch/arm/dts/k3-am642-phycore-som-binman.dtsi b/arch/arm/dts/k3-am642-phycore-som-binman.dtsi index 966905bd64d..59d8902bf48 100644 --- a/arch/arm/dts/k3-am642-phycore-som-binman.dtsi +++ b/arch/arm/dts/k3-am642-phycore-som-binman.dtsi @@ -371,7 +371,7 @@ description = "k3-am6xx-phycore-disable-spi-nor"; type = "flat_dt"; compression = "none"; - load = <0x8F001000>; + load = <0x8F002000>; arch = "arm"; ti-secure { content = <&am6xx_phycore_disable_spi_not_dtbo>; @@ -386,7 +386,7 @@ description = "k3-am6xx-phycore-disable-eth-phy"; type = "flat_dt"; compression = "none"; - load = <0x8F002000>; + load = <0x8F004000>; arch = "arm"; ti-secure { content = <&am6xx_phycore_disable_eth_phy_dtbo>; @@ -401,7 +401,7 @@ description = "k3-am6xx-phycore-qspi-nor"; type = "flat_dt"; compression = "none"; - load = <0x8F003000>; + load = <0x8F006000>; arch = "arm"; ti-secure { content = <&am6xx_phycore_disable_qspi_nor_dtbo>; -- cgit v1.2.3 From 588094f2c8ec9a4f7d2dcda11ffae8db8462149c Mon Sep 17 00:00:00 2001 From: Aristo Chen Date: Sun, 14 Sep 2025 10:59:30 +0000 Subject: tools: mkimage: detect overlapping load regions in FIT configurations This patch adds a validation step in mkimage to detect memory region overlaps between images specified in the same configuration of a FIT image. If any overlaps are found, the tool prints an error and aborts the build. This helps prevent runtime memory corruption caused by conflicting load addresses between images. Signed-off-by: Aristo Chen --- tools/fit_image.c | 90 ++++++++++++++++++++++++++++++++++++++++++++++++++++++- tools/mkimage.c | 3 +- 2 files changed, 91 insertions(+), 2 deletions(-) diff --git a/tools/fit_image.c b/tools/fit_image.c index 331be5ae71d..bd849110646 100644 --- a/tools/fit_image.c +++ b/tools/fit_image.c @@ -22,6 +22,20 @@ #include #include +struct fit_region { + ulong load; + ulong size; + const char *name; +}; + +static int regions_overlap(const struct fit_region *a, const struct fit_region *b) +{ + ulong a_end = a->load + a->size; + ulong b_end = b->load + b->size; + + return !(a_end <= b->load || b_end <= a->load); +} + static struct legacy_img_hdr header; static int fit_estimate_hash_sig_size(struct image_tool_params *params, const char *fname) @@ -775,9 +789,12 @@ static int fit_import_data(struct image_tool_params *params, const char *fname) } fdt_for_each_subnode(node, fdt, confs) { + struct fit_region *regions = NULL; + unsigned int img_count = 0; + unsigned int regions_allocated = 0; const char *conf_name = fdt_get_name(fdt, node, NULL); - for (int i = 0; i < ARRAY_SIZE(props); i++) { + for (unsigned int i = 0; i < ARRAY_SIZE(props); i++) { int count = fdt_stringlist_count(fdt, node, props[i]); if (count < 0) @@ -798,8 +815,79 @@ static int fit_import_data(struct image_tool_params *params, const char *fname) ret = FDT_ERR_NOTFOUND; goto err_munmap; } + + ulong img_load = 0; + int img_size = 0; + + if (fit_image_get_load(fdt, img, &img_load)) { + fprintf(stderr, + "Warning: not able to get `load` of node '%s'\n", + img_name); + // Skip checking the components that do not have a + // definition for `load` + continue; + } + const char *img_data = fdt_getprop(fdt, img, + FIT_DATA_PROP, + &img_size); + + if (!img_data || !img_size) + continue; + + // Check if we've already added this image to avoid duplicates + for (unsigned int k = 0; k < img_count; k++) { + if (!strcmp(regions[k].name, img_name)) + goto next_node; + } + + // Expand regions array if needed + if (img_count >= regions_allocated) { + unsigned int new_size = regions_allocated ? + regions_allocated * 2 : 8; + struct fit_region *new_regions = realloc(regions, + new_size * sizeof(struct fit_region)); + if (!new_regions) { + fprintf(stderr, + "Failed to allocate memory for regions in config %s\n", + fdt_get_name(fdt, node, NULL)); + free(regions); + ret = -ENOMEM; + goto err_munmap; + } + regions = new_regions; + regions_allocated = new_size; + } + + regions[img_count].load = img_load; + regions[img_count].size = img_size; + regions[img_count].name = img_name; + img_count++; +next_node:; + } + } + + // Check for overlap within this config only + for (unsigned int i = 0; i < img_count; i++) { + for (unsigned int j = i + 1; j < img_count; j++) { + if (regions_overlap(®ions[i], ®ions[j])) { + fprintf(stderr, + "[Config: %s] Error: Overlap detected:\n" + " - %s: [0x%lx - 0x%lx]\n" + " - %s: [0x%lx - 0x%lx]\n", + fdt_get_name(fdt, node, NULL), + regions[i].name, regions[i].load, + regions[i].load + regions[i].size, + regions[j].name, regions[j].load, + regions[j].load + regions[j].size); + ret = FDT_ERR_BADSTRUCTURE; + free(regions); + goto err_munmap; + } } } + + // Clean up allocated memory for this configuration + free(regions); } munmap(old_fdt, sbuf.st_size); diff --git a/tools/mkimage.c b/tools/mkimage.c index 361711c53b2..3f28918f5cf 100644 --- a/tools/mkimage.c +++ b/tools/mkimage.c @@ -520,7 +520,8 @@ int main(int argc, char **argv) retval = tparams->fflag_handle(¶ms); if (retval != EXIT_SUCCESS) { - if (retval == FDT_ERR_NOTFOUND) { + if (retval == FDT_ERR_NOTFOUND || + retval == FDT_ERR_BADSTRUCTURE) { // Already printed error, exit cleanly exit(EXIT_FAILURE); } -- cgit v1.2.3 From 8f3d3510e31ebc7b2057f431322a7174b6b60ea6 Mon Sep 17 00:00:00 2001 From: Aristo Chen Date: Sun, 14 Sep 2025 10:59:31 +0000 Subject: test: Add test case for FIT image load address overlap detection Add a new test case to verify that mkimage properly detects and reports memory region overlaps in FIT image configurations. The test creates a FIT image with kernel and FDT components that have the same load address (0x40000), which should trigger the overlap detection logic and cause mkimage to fail with an appropriate error message. Test verifies: - mkimage returns non-zero exit code when overlap is detected - Error message contains "Error: Overlap detected:" - Error message identifies the specific overlapping components (kernel@1 and fdt@1) This test ensures the overlap detection feature works correctly and prevents deployment of FIT images with conflicting memory layouts that could cause runtime failures. Signed-off-by: Aristo Chen --- test/py/tests/test_fit_mkimage_validate.py | 65 ++++++++++++++++++++++++++++++ 1 file changed, 65 insertions(+) diff --git a/test/py/tests/test_fit_mkimage_validate.py b/test/py/tests/test_fit_mkimage_validate.py index 170b2a8cbbb..27299a58f33 100644 --- a/test/py/tests/test_fit_mkimage_validate.py +++ b/test/py/tests/test_fit_mkimage_validate.py @@ -103,3 +103,68 @@ def test_fit_invalid_default_config(ubman): assert result.returncode != 0, "mkimage should fail due to missing default config" assert re.search(r"Default configuration '.*' not found under /configurations", result.stderr) + +def test_fit_load_addr_overlap(ubman): + """Test that mkimage fails when load address overlap""" + + its_fname = fit_util.make_fname(ubman, "invalid.its") + itb_fname = fit_util.make_fname(ubman, "invalid.itb") + kernel = fit_util.make_kernel(ubman, 'kernel.bin', 'kernel') + fdt = fit_util.make_dtb(ubman, ''' +/dts-v1/; +/ { + model = "Test FDT"; + compatible = "test"; +}; +''', 'test') + + # Write ITS with an invalid reference to a nonexistent default config + its_text = ''' +/dts-v1/; + +/ { + images { + kernel@1 { + description = "Test Kernel"; + data = /incbin/("kernel.bin"); + type = "kernel"; + arch = "sandbox"; + os = "linux"; + compression = "none"; + load = <0x40000>; + entry = <0x40000>; + }; + fdt@1 { + description = "Test FDT"; + data = /incbin/("test.dtb"); + type = "flat_dt"; + arch = "sandbox"; + os = "linux"; + compression = "none"; + load = <0x40000>; + entry = <0x40000>; + }; + }; + + configurations { + default = "conf@1"; + conf@1 { + kernel = "kernel@1"; + fdt = "fdt@1"; + }; + }; +}; +''' + + with open(its_fname, 'w') as f: + f.write(its_text) + + mkimage = os.path.join(ubman.config.build_dir, 'tools/mkimage') + cmd = [mkimage, '-f', its_fname, itb_fname] + + result = subprocess.run(cmd, capture_output=True, text=True) + + assert result.returncode != 0, "mkimage should fail due to memory overlap" + assert "Error: Overlap detected:" in result.stderr + # Check that it identifies the specific overlapping components + assert "kernel@1" in result.stderr and "fdt@1" in result.stderr -- cgit v1.2.3 From 4907a920e8292e9e38ddab4d211dfd5499097a8c Mon Sep 17 00:00:00 2001 From: Aristo Chen Date: Sun, 14 Sep 2025 10:59:32 +0000 Subject: doc: binman: Add guidance for determining ELF load addresses Add documentation to help users understand how to determine where ELF files will be loaded when using binman's 'fit,load' property. This addresses the common confusion about how load addresses are determined from ELF files. The documentation explains three methods: 1. Using readelf to examine program headers 2. Checking the linker script (.lds file) 3. Using objdump to see section addresses Also includes a specific example from binman tests showing how elf_sections.lds sets ATF load address to 0x00000010 and elf_sections_tee.lds sets TEE load address to 0x00100010 to avoid memory overlap conflicts. This helps users debug memory layout conflicts more efficiently when working with FIT images containing multiple ELF components. Signed-off-by: Aristo Chen --- tools/binman/entries.rst | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) diff --git a/tools/binman/entries.rst b/tools/binman/entries.rst index 12a39d070e4..f6a5465ca44 100644 --- a/tools/binman/entries.rst +++ b/tools/binman/entries.rst @@ -1050,6 +1050,24 @@ split-elf Generates a `load = <...>` property with the load address of the segment + Note: The load address comes from the ELF file's program header or + linker script. To determine where an ELF file will be loaded, you can: + + 1. Use readelf to examine the program headers: + ``readelf -l your_elf_file.elf`` + Look for the LOAD segments and their VirtAddr (Virtual Address) + + 2. Check the linker script (.lds file) used to build the ELF: + Look for the `. =
;` statements which set the location + counter and determine load addresses for different sections + + 3. Use objdump to see section addresses: + ``objdump -h your_elf_file.elf`` + + For example, in binman tests, elf_sections.lds sets ATF load address + to 0x00000010, while elf_sections_tee.lds sets TEE load address to + 0x00100010 to avoid memory overlap conflicts. + fit,entry Generates a `entry = <...>` property with the entry address of the ELF. This is only produced for the first entry -- cgit v1.2.3 From e482fdbbca935de32400054eb532de45b1cc01cb Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Wed, 24 Sep 2025 07:50:44 -0600 Subject: Revert "Merge patch series "mkimage: Detect FIT image load address overlaps and fix related test/DTS issues"" This reverts commit 4d84fa1261eb27d57687f2e4c404a78b8653c183, reversing changes made to b82a1fa7ddc7f3be2f3b75898d5dc44c34420bdd. I had missed some feedback on this series from earlier, and we have since had reports of regressions due to this as well. For now, revert this. Signed-off-by: Tom Rini --- arch/arm/dts/k3-am625-phycore-som-binman.dtsi | 22 +++--- arch/arm/dts/k3-am625-sk-binman.dtsi | 16 ++-- arch/arm/dts/k3-am625-verdin-wifi-dev-binman.dtsi | 16 ++-- arch/arm/dts/k3-am62a-phycore-som-binman.dtsi | 10 +-- arch/arm/dts/k3-am62a-sk-binman.dtsi | 4 +- arch/arm/dts/k3-am642-phycore-som-binman.dtsi | 6 +- test/py/tests/test_fit_mkimage_validate.py | 65 ---------------- tools/binman/entries.rst | 18 ----- tools/binman/ftest.py | 4 +- tools/binman/test/276_fit_firmware_loadables.dts | 4 +- tools/binman/test/340_fit_signature.dts | 4 +- tools/binman/test/342_fit_signature.dts | 4 +- tools/binman/test/Makefile | 6 +- tools/binman/test/elf_sections_tee.c | 1 - tools/binman/test/elf_sections_tee.lds | 32 -------- tools/fit_image.c | 90 +---------------------- tools/mkimage.c | 3 +- 17 files changed, 48 insertions(+), 257 deletions(-) delete mode 120000 tools/binman/test/elf_sections_tee.c delete mode 100644 tools/binman/test/elf_sections_tee.lds diff --git a/arch/arm/dts/k3-am625-phycore-som-binman.dtsi b/arch/arm/dts/k3-am625-phycore-som-binman.dtsi index 4344cefeba3..a9bd5a2be84 100644 --- a/arch/arm/dts/k3-am625-phycore-som-binman.dtsi +++ b/arch/arm/dts/k3-am625-phycore-som-binman.dtsi @@ -234,8 +234,8 @@ arch = "arm32"; compression = "none"; os = "tifsstub-fs"; - load = <0x9dc10000>; - entry = <0x9dc10000>; + load = <0x9dc00000>; + entry = <0x9dc00000>; blob-ext { filename = "tifsstub.bin_fs"; }; @@ -247,8 +247,8 @@ arch = "arm32"; compression = "none"; os = "tifsstub-gp"; - load = <0x9dc20000>; - entry = <0x9dc20000>; + load = <0x9dc00000>; + entry = <0x9dc00000>; blob-ext { filename = "tifsstub.bin_gp"; }; @@ -322,7 +322,7 @@ description = "k3-am6xx-phycore-disable-spi-nor"; type = "flat_dt"; compression = "none"; - load = <0x8F002000>; + load = <0x8F001000>; arch = "arm"; ti-secure { content = <&am6xx_phycore_disable_spi_not_dtbo>; @@ -337,7 +337,7 @@ description = "k3-am6xx-phycore-disable-eth-phy"; type = "flat_dt"; compression = "none"; - load = <0x8F004000>; + load = <0x8F002000>; arch = "arm"; ti-secure { content = <&am6xx_phycore_disable_eth_phy_dtbo>; @@ -352,7 +352,7 @@ description = "k3-am6xx-phycore-qspi-nor"; type = "flat_dt"; compression = "none"; - load = <0x8F006000>; + load = <0x8F003000>; arch = "arm"; ti-secure { content = <&am6xx_phycore_disable_qspi_nor_dtbo>; @@ -479,8 +479,8 @@ arch = "arm32"; compression = "none"; os = "tifsstub-fs"; - load = <0x9dc10000>; - entry = <0x9dc10000>; + load = <0x9dc00000>; + entry = <0x9dc00000>; blob-ext { filename = "tifsstub.bin_fs"; }; @@ -492,8 +492,8 @@ arch = "arm32"; compression = "none"; os = "tifsstub-gp"; - load = <0x9dc20000>; - entry = <0x9dc20000>; + load = <0x9dc00000>; + entry = <0x9dc00000>; blob-ext { filename = "tifsstub.bin_gp"; }; diff --git a/arch/arm/dts/k3-am625-sk-binman.dtsi b/arch/arm/dts/k3-am625-sk-binman.dtsi index 1619f733a0d..f743c4353b4 100644 --- a/arch/arm/dts/k3-am625-sk-binman.dtsi +++ b/arch/arm/dts/k3-am625-sk-binman.dtsi @@ -231,8 +231,8 @@ arch = "arm32"; compression = "none"; os = "tifsstub-fs"; - load = <0x9dc10000>; - entry = <0x9dc10000>; + load = <0x9dc00000>; + entry = <0x9dc00000>; blob-ext { filename = "tifsstub.bin_fs"; }; @@ -244,8 +244,8 @@ arch = "arm32"; compression = "none"; os = "tifsstub-gp"; - load = <0x9dc20000>; - entry = <0x9dc20000>; + load = <0x9dc00000>; + entry = <0x9dc00000>; blob-ext { filename = "tifsstub.bin_gp"; }; @@ -362,8 +362,8 @@ arch = "arm32"; compression = "none"; os = "tifsstub-fs"; - load = <0x9dc10000>; - entry = <0x9dc10000>; + load = <0x9dc00000>; + entry = <0x9dc00000>; blob-ext { filename = "tifsstub.bin_fs"; }; @@ -375,8 +375,8 @@ arch = "arm32"; compression = "none"; os = "tifsstub-gp"; - load = <0x9dc20000>; - entry = <0x9dc20000>; + load = <0x9dc00000>; + entry = <0x9dc00000>; blob-ext { filename = "tifsstub.bin_gp"; }; diff --git a/arch/arm/dts/k3-am625-verdin-wifi-dev-binman.dtsi b/arch/arm/dts/k3-am625-verdin-wifi-dev-binman.dtsi index 6c4ad72d936..65fef6e4790 100644 --- a/arch/arm/dts/k3-am625-verdin-wifi-dev-binman.dtsi +++ b/arch/arm/dts/k3-am625-verdin-wifi-dev-binman.dtsi @@ -219,8 +219,8 @@ arch = "arm32"; compression = "none"; os = "tifsstub-fs"; - load = <0x9dc10000>; - entry = <0x9dc10000>; + load = <0x9dc00000>; + entry = <0x9dc00000>; blob-ext { filename = "tifsstub.bin_fs"; }; @@ -232,8 +232,8 @@ arch = "arm32"; compression = "none"; os = "tifsstub-gp"; - load = <0x9dc20000>; - entry = <0x9dc20000>; + load = <0x9dc00000>; + entry = <0x9dc00000>; blob-ext { filename = "tifsstub.bin_gp"; }; @@ -346,8 +346,8 @@ arch = "arm32"; compression = "none"; os = "tifsstub-fs"; - load = <0x9dc10000>; - entry = <0x9dc10000>; + load = <0x9dc00000>; + entry = <0x9dc00000>; blob-ext { filename = "tifsstub.bin_fs"; }; @@ -359,8 +359,8 @@ arch = "arm32"; compression = "none"; os = "tifsstub-gp"; - load = <0x9dc20000>; - entry = <0x9dc20000>; + load = <0x9dc00000>; + entry = <0x9dc00000>; blob-ext { filename = "tifsstub.bin_gp"; }; diff --git a/arch/arm/dts/k3-am62a-phycore-som-binman.dtsi b/arch/arm/dts/k3-am62a-phycore-som-binman.dtsi index 786c7a2d458..a284226320c 100644 --- a/arch/arm/dts/k3-am62a-phycore-som-binman.dtsi +++ b/arch/arm/dts/k3-am62a-phycore-som-binman.dtsi @@ -184,8 +184,8 @@ arch = "arm32"; compression = "none"; os = "tifsstub-fs"; - load = <0x9ca10000>; - entry = <0x9ca10000>; + load = <0x9ca00000>; + entry = <0x9ca00000>; blob-ext { filename = "tifsstub.bin_fs"; }; @@ -260,7 +260,7 @@ description = "k3-am6xx-phycore-disable-spi-nor"; type = "flat_dt"; compression = "none"; - load = <0x8F002000>; + load = <0x8F001000>; arch = "arm"; ti-secure { content = <&am6xx_phycore_disable_spi_not_dtbo>; @@ -275,7 +275,7 @@ description = "k3-am6xx-phycore-disable-eth-phy"; type = "flat_dt"; compression = "none"; - load = <0x8F004000>; + load = <0x8F002000>; arch = "arm"; ti-secure { content = <&am6xx_phycore_disable_eth_phy_dtbo>; @@ -290,7 +290,7 @@ description = "k3-am6xx-phycore-qspi-nor"; type = "flat_dt"; compression = "none"; - load = <0x8F006000>; + load = <0x8F003000>; arch = "arm"; ti-secure { content = <&am6xx_phycore_disable_qspi_nor_dtbo>; diff --git a/arch/arm/dts/k3-am62a-sk-binman.dtsi b/arch/arm/dts/k3-am62a-sk-binman.dtsi index 214acd7f0f7..e64c165ecbf 100644 --- a/arch/arm/dts/k3-am62a-sk-binman.dtsi +++ b/arch/arm/dts/k3-am62a-sk-binman.dtsi @@ -168,8 +168,8 @@ arch = "arm32"; compression = "none"; os = "tifsstub-fs"; - load = <0x9ca10000>; - entry = <0x9ca10000>; + load = <0x9ca00000>; + entry = <0x9ca00000>; blob-ext { filename = "tifsstub.bin_fs"; }; diff --git a/arch/arm/dts/k3-am642-phycore-som-binman.dtsi b/arch/arm/dts/k3-am642-phycore-som-binman.dtsi index 59d8902bf48..966905bd64d 100644 --- a/arch/arm/dts/k3-am642-phycore-som-binman.dtsi +++ b/arch/arm/dts/k3-am642-phycore-som-binman.dtsi @@ -371,7 +371,7 @@ description = "k3-am6xx-phycore-disable-spi-nor"; type = "flat_dt"; compression = "none"; - load = <0x8F002000>; + load = <0x8F001000>; arch = "arm"; ti-secure { content = <&am6xx_phycore_disable_spi_not_dtbo>; @@ -386,7 +386,7 @@ description = "k3-am6xx-phycore-disable-eth-phy"; type = "flat_dt"; compression = "none"; - load = <0x8F004000>; + load = <0x8F002000>; arch = "arm"; ti-secure { content = <&am6xx_phycore_disable_eth_phy_dtbo>; @@ -401,7 +401,7 @@ description = "k3-am6xx-phycore-qspi-nor"; type = "flat_dt"; compression = "none"; - load = <0x8F006000>; + load = <0x8F003000>; arch = "arm"; ti-secure { content = <&am6xx_phycore_disable_qspi_nor_dtbo>; diff --git a/test/py/tests/test_fit_mkimage_validate.py b/test/py/tests/test_fit_mkimage_validate.py index 27299a58f33..170b2a8cbbb 100644 --- a/test/py/tests/test_fit_mkimage_validate.py +++ b/test/py/tests/test_fit_mkimage_validate.py @@ -103,68 +103,3 @@ def test_fit_invalid_default_config(ubman): assert result.returncode != 0, "mkimage should fail due to missing default config" assert re.search(r"Default configuration '.*' not found under /configurations", result.stderr) - -def test_fit_load_addr_overlap(ubman): - """Test that mkimage fails when load address overlap""" - - its_fname = fit_util.make_fname(ubman, "invalid.its") - itb_fname = fit_util.make_fname(ubman, "invalid.itb") - kernel = fit_util.make_kernel(ubman, 'kernel.bin', 'kernel') - fdt = fit_util.make_dtb(ubman, ''' -/dts-v1/; -/ { - model = "Test FDT"; - compatible = "test"; -}; -''', 'test') - - # Write ITS with an invalid reference to a nonexistent default config - its_text = ''' -/dts-v1/; - -/ { - images { - kernel@1 { - description = "Test Kernel"; - data = /incbin/("kernel.bin"); - type = "kernel"; - arch = "sandbox"; - os = "linux"; - compression = "none"; - load = <0x40000>; - entry = <0x40000>; - }; - fdt@1 { - description = "Test FDT"; - data = /incbin/("test.dtb"); - type = "flat_dt"; - arch = "sandbox"; - os = "linux"; - compression = "none"; - load = <0x40000>; - entry = <0x40000>; - }; - }; - - configurations { - default = "conf@1"; - conf@1 { - kernel = "kernel@1"; - fdt = "fdt@1"; - }; - }; -}; -''' - - with open(its_fname, 'w') as f: - f.write(its_text) - - mkimage = os.path.join(ubman.config.build_dir, 'tools/mkimage') - cmd = [mkimage, '-f', its_fname, itb_fname] - - result = subprocess.run(cmd, capture_output=True, text=True) - - assert result.returncode != 0, "mkimage should fail due to memory overlap" - assert "Error: Overlap detected:" in result.stderr - # Check that it identifies the specific overlapping components - assert "kernel@1" in result.stderr and "fdt@1" in result.stderr diff --git a/tools/binman/entries.rst b/tools/binman/entries.rst index 173b7eef6cc..8922d6cd070 100644 --- a/tools/binman/entries.rst +++ b/tools/binman/entries.rst @@ -1050,24 +1050,6 @@ split-elf Generates a `load = <...>` property with the load address of the segment - Note: The load address comes from the ELF file's program header or - linker script. To determine where an ELF file will be loaded, you can: - - 1. Use readelf to examine the program headers: - ``readelf -l your_elf_file.elf`` - Look for the LOAD segments and their VirtAddr (Virtual Address) - - 2. Check the linker script (.lds file) used to build the ELF: - Look for the `. =
;` statements which set the location - counter and determine load addresses for different sections - - 3. Use objdump to see section addresses: - ``objdump -h your_elf_file.elf`` - - For example, in binman tests, elf_sections.lds sets ATF load address - to 0x00000010, while elf_sections_tee.lds sets TEE load address to - 0x00100010 to avoid memory overlap conflicts. - fit,entry Generates a `entry = <...>` property with the entry address of the ELF. This is only produced for the first entry diff --git a/tools/binman/ftest.py b/tools/binman/ftest.py index 0c2dbf333c0..925c39a530e 100644 --- a/tools/binman/ftest.py +++ b/tools/binman/ftest.py @@ -252,7 +252,7 @@ class TestFunctional(unittest.TestCase): TestFunctional._MakeInputFile('bl31.elf', tools.read_file(cls.ElfTestFile('elf_sections'))) TestFunctional.tee_elf_path = TestFunctional._MakeInputFile('tee.elf', - tools.read_file(cls.ElfTestFile('elf_sections_tee'))) + tools.read_file(cls.ElfTestFile('elf_sections'))) # Newer OP_TEE file in v1 binary format cls.make_tee_bin('tee.bin') @@ -7997,7 +7997,7 @@ fdt fdtmap Extract the devicetree blob from the fdtmap 'Node \'/binman/fit\': multiple key paths found', str(e.exception)) - def testFitSignNoSignatureNodes(self): + def testFitSignNoSingatureNodes(self): """Test that fit,sign doens't raise error if no signature nodes found""" if not elf.ELF_TOOLS: self.skipTest('Python elftools not available') diff --git a/tools/binman/test/276_fit_firmware_loadables.dts b/tools/binman/test/276_fit_firmware_loadables.dts index d344036a11a..2f79cdc9bb8 100644 --- a/tools/binman/test/276_fit_firmware_loadables.dts +++ b/tools/binman/test/276_fit_firmware_loadables.dts @@ -19,8 +19,8 @@ arch = "arm64"; os = "u-boot"; compression = "none"; - load = <0x00002000>; - entry = <0x00002000>; + load = <0x00000000>; + entry = <0x00000000>; u-boot-nodtb { }; diff --git a/tools/binman/test/340_fit_signature.dts b/tools/binman/test/340_fit_signature.dts index 1c25d52cba4..9dce62e52de 100644 --- a/tools/binman/test/340_fit_signature.dts +++ b/tools/binman/test/340_fit_signature.dts @@ -20,8 +20,8 @@ arch = "arm64"; os = "u-boot"; compression = "none"; - load = <0x00002000>; - entry = <0x00002000>; + load = <0x00000000>; + entry = <0x00000000>; u-boot-nodtb { }; diff --git a/tools/binman/test/342_fit_signature.dts b/tools/binman/test/342_fit_signature.dts index 2ac600b1c70..267105d0f68 100644 --- a/tools/binman/test/342_fit_signature.dts +++ b/tools/binman/test/342_fit_signature.dts @@ -20,8 +20,8 @@ arch = "arm64"; os = "u-boot"; compression = "none"; - load = <0x00002000>; - entry = <0x00002000>; + load = <0x00000000>; + entry = <0x00000000>; u-boot-nodtb { }; diff --git a/tools/binman/test/Makefile b/tools/binman/test/Makefile index 66279e0e207..4d152eee9c0 100644 --- a/tools/binman/test/Makefile +++ b/tools/binman/test/Makefile @@ -30,13 +30,12 @@ LDS_BINMAN_BAD := -T $(SRC)u_boot_binman_syms_bad.lds LDS_BINMAN_X86 := -T $(SRC)u_boot_binman_syms_x86.lds LDS_BINMAN_EMBED := -T $(SRC)u_boot_binman_embed.lds LDS_EFL_SECTIONS := -T $(SRC)elf_sections.lds -LDS_EFL_SECTIONS_TEE := -T $(SRC)elf_sections_tee.lds LDS_BLOB := -T $(SRC)blob_syms.lds TARGETS = u_boot_ucode_ptr u_boot_no_ucode_ptr bss_data bss_data_zero \ u_boot_binman_syms u_boot_binman_syms.bin u_boot_binman_syms_bad \ u_boot_binman_syms_size u_boot_binman_syms_x86 embed_data \ - u_boot_binman_embed u_boot_binman_embed_sm elf_sections elf_sections_tee blob_syms.bin + u_boot_binman_embed u_boot_binman_embed_sm elf_sections blob_syms.bin all: $(TARGETS) @@ -85,9 +84,6 @@ blob_syms: blob_syms.c elf_sections: CFLAGS += $(LDS_EFL_SECTIONS) elf_sections: elf_sections.c -elf_sections_tee: CFLAGS += $(LDS_EFL_SECTIONS_TEE) -elf_sections_tee: elf_sections_tee.c - clean: rm -f $(TARGETS) diff --git a/tools/binman/test/elf_sections_tee.c b/tools/binman/test/elf_sections_tee.c deleted file mode 120000 index 01b200a365e..00000000000 --- a/tools/binman/test/elf_sections_tee.c +++ /dev/null @@ -1 +0,0 @@ -elf_sections.c \ No newline at end of file diff --git a/tools/binman/test/elf_sections_tee.lds b/tools/binman/test/elf_sections_tee.lds deleted file mode 100644 index 97e5e5f5d94..00000000000 --- a/tools/binman/test/elf_sections_tee.lds +++ /dev/null @@ -1,32 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (c) 2016 Google, Inc - * Copyright (c) 2025 Canonical Ltd. - */ - -OUTPUT_FORMAT("elf32-i386", "elf32-i386", "elf32-i386") -OUTPUT_ARCH(i386) -ENTRY(_start) - -SECTIONS -{ - . = 0x00100010; - _start = .; - - . = ALIGN(4); - .text : - { - *(.text*) - } - - . = 0x00101000; - .sram : - { - *(.sram*) - } - - /DISCARD/ : { - *(.comment) - *(.dyn*) - } -} diff --git a/tools/fit_image.c b/tools/fit_image.c index 12f4cdb2875..10849733816 100644 --- a/tools/fit_image.c +++ b/tools/fit_image.c @@ -22,20 +22,6 @@ #include #include -struct fit_region { - ulong load; - ulong size; - const char *name; -}; - -static int regions_overlap(const struct fit_region *a, const struct fit_region *b) -{ - ulong a_end = a->load + a->size; - ulong b_end = b->load + b->size; - - return !(a_end <= b->load || b_end <= a->load); -} - static struct legacy_img_hdr header; static int fit_estimate_hash_sig_size(struct image_tool_params *params, const char *fname) @@ -837,12 +823,9 @@ static int fit_import_data(struct image_tool_params *params, const char *fname) } fdt_for_each_subnode(node, fdt, confs) { - struct fit_region *regions = NULL; - unsigned int img_count = 0; - unsigned int regions_allocated = 0; const char *conf_name = fdt_get_name(fdt, node, NULL); - for (unsigned int i = 0; i < ARRAY_SIZE(props); i++) { + for (int i = 0; i < ARRAY_SIZE(props); i++) { int count = fdt_stringlist_count(fdt, node, props[i]); if (count < 0) @@ -863,79 +846,8 @@ static int fit_import_data(struct image_tool_params *params, const char *fname) ret = FDT_ERR_NOTFOUND; goto err_munmap; } - - ulong img_load = 0; - int img_size = 0; - - if (fit_image_get_load(fdt, img, &img_load)) { - fprintf(stderr, - "Warning: not able to get `load` of node '%s'\n", - img_name); - // Skip checking the components that do not have a - // definition for `load` - continue; - } - const char *img_data = fdt_getprop(fdt, img, - FIT_DATA_PROP, - &img_size); - - if (!img_data || !img_size) - continue; - - // Check if we've already added this image to avoid duplicates - for (unsigned int k = 0; k < img_count; k++) { - if (!strcmp(regions[k].name, img_name)) - goto next_node; - } - - // Expand regions array if needed - if (img_count >= regions_allocated) { - unsigned int new_size = regions_allocated ? - regions_allocated * 2 : 8; - struct fit_region *new_regions = realloc(regions, - new_size * sizeof(struct fit_region)); - if (!new_regions) { - fprintf(stderr, - "Failed to allocate memory for regions in config %s\n", - fdt_get_name(fdt, node, NULL)); - free(regions); - ret = -ENOMEM; - goto err_munmap; - } - regions = new_regions; - regions_allocated = new_size; - } - - regions[img_count].load = img_load; - regions[img_count].size = img_size; - regions[img_count].name = img_name; - img_count++; -next_node:; - } - } - - // Check for overlap within this config only - for (unsigned int i = 0; i < img_count; i++) { - for (unsigned int j = i + 1; j < img_count; j++) { - if (regions_overlap(®ions[i], ®ions[j])) { - fprintf(stderr, - "[Config: %s] Error: Overlap detected:\n" - " - %s: [0x%lx - 0x%lx]\n" - " - %s: [0x%lx - 0x%lx]\n", - fdt_get_name(fdt, node, NULL), - regions[i].name, regions[i].load, - regions[i].load + regions[i].size, - regions[j].name, regions[j].load, - regions[j].load + regions[j].size); - ret = FDT_ERR_BADSTRUCTURE; - free(regions); - goto err_munmap; - } } } - - // Clean up allocated memory for this configuration - free(regions); } munmap(old_fdt, sbuf.st_size); diff --git a/tools/mkimage.c b/tools/mkimage.c index e96fb7e42db..12183270776 100644 --- a/tools/mkimage.c +++ b/tools/mkimage.c @@ -533,8 +533,7 @@ int main(int argc, char **argv) retval = tparams->fflag_handle(¶ms); if (retval != EXIT_SUCCESS) { - if (retval == FDT_ERR_NOTFOUND || - retval == FDT_ERR_BADSTRUCTURE) { + if (retval == FDT_ERR_NOTFOUND) { // Already printed error, exit cleanly exit(EXIT_FAILURE); } -- cgit v1.2.3 From 6c98e6014b3a36933860d02cb757565ec2fc80a4 Mon Sep 17 00:00:00 2001 From: Andrew Goodbody Date: Mon, 1 Sep 2025 16:00:46 +0100 Subject: power: regulator: Fix incorrect use of binary and In regulator_list_autoset there is a test for ret being non-zero and error being zero but it uses the binary '&' instead of the logical '&&' which could well lead to unexpected results. Correct this to use the logical '&&' instead. This issue found by Smatch. Signed-off-by: Andrew Goodbody Reviewed-by: Peng Fan Signed-off-by: Peng Fan --- drivers/power/regulator/regulator-uclass.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/power/regulator/regulator-uclass.c b/drivers/power/regulator/regulator-uclass.c index 2a59a1b79c2..94c52cf555b 100644 --- a/drivers/power/regulator/regulator-uclass.c +++ b/drivers/power/regulator/regulator-uclass.c @@ -389,7 +389,7 @@ int regulator_list_autoset(const char *list_platname[], ret = regulator_autoset_by_name(list_platname[i], &dev); if (ret != -EMEDIUMTYPE && verbose) regulator_show(dev, ret); - if (ret & !error) + if (ret && ret != -EALREADY && !error) error = ret; if (list_devp) -- cgit v1.2.3 From 3cabc6bf7e16c7e2a1156392c31e40f678cc7026 Mon Sep 17 00:00:00 2001 From: Bhimeswararao Matsa Date: Mon, 1 Sep 2025 19:14:10 +0530 Subject: mmc: core: style fixes in mmc.c Fix a couple of style issues reported by checkpatch.pl: - Replace `#ifdef CONFIG_MMC_TRACE` with `#if IS_ENABLED(CONFIG_MMC_TRACE)` to follow the preferred kernel style for config-dependent branches. - Drop explicit zero initialization of a static variable. No functional change intended. Signed-off-by: Bhimeswararao Matsa Signed-off-by: Peng Fan --- drivers/mmc/mmc.c | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) diff --git a/drivers/mmc/mmc.c b/drivers/mmc/mmc.c index 20afcffde3d..b1cfa3cd7c2 100644 --- a/drivers/mmc/mmc.c +++ b/drivers/mmc/mmc.c @@ -104,8 +104,7 @@ __weak int board_mmc_getcd(struct mmc *mmc) return -1; } #endif - -#ifdef CONFIG_MMC_TRACE +#if IS_ENABLED(CONFIG_MMC_TRACE) void mmmc_trace_before_send(struct mmc *mmc, struct mmc_cmd *cmd) { printf("CMD_SEND:%d\n", cmd->cmdidx); @@ -3190,7 +3189,7 @@ static int mmc_probe(struct bd_info *bis) int mmc_initialize(struct bd_info *bis) { - static int initialized = 0; + static int initialized; int ret; if (initialized) /* Avoid initializing mmc multiple times */ return 0; -- cgit v1.2.3 From 5289b6e5540e571afd81482305e5623e9124ea66 Mon Sep 17 00:00:00 2001 From: Guillaume Ranquet Date: Thu, 11 Sep 2025 15:50:26 +0200 Subject: android: boot: fix wrong end of header in v3/v4 parsing The android boot header is page aligned but the current code made the assumption that the header was always smaller than the current header format. When the page_size is defined as 2048, as this is the case with the cuttlefish target, the current code sets the end of the header in the middle of it as the v3 and v4 headers are respectively 2112 and 2128 bytes long. Fix that by aligning to page_size Fixes: 1115027d2f75 ("android: boot: update android_image_get_data to support v3, v4") Signed-off-by: Guillaume Ranquet --- boot/image-android.c | 7 ++++++- include/android_image.h | 2 ++ 2 files changed, 8 insertions(+), 1 deletion(-) diff --git a/boot/image-android.c b/boot/image-android.c index 1cd2060bb3f..e46dee0d9b3 100644 --- a/boot/image-android.c +++ b/boot/image-android.c @@ -107,7 +107,12 @@ static void android_vendor_boot_image_v3_v4_parse_hdr(const struct andr_vnd_boot data->dtb_load_addr = hdr->dtb_addr; data->bootconfig_size = hdr->bootconfig_size; end = (ulong)hdr; - end += hdr->page_size; + + if (hdr->header_version > 3) + end += ALIGN(ANDR_VENDOR_BOOT_V4_SIZE, hdr->page_size); + else + end += ALIGN(ANDR_VENDOR_BOOT_V3_SIZE, hdr->page_size); + if (hdr->vendor_ramdisk_size) { data->vendor_ramdisk_ptr = end; data->vendor_ramdisk_size = hdr->vendor_ramdisk_size; diff --git a/include/android_image.h b/include/android_image.h index 96820709b42..a2d80499ba3 100644 --- a/include/android_image.h +++ b/include/android_image.h @@ -21,6 +21,8 @@ #define ANDR_BOOT_ARGS_SIZE 512 #define ANDR_BOOT_EXTRA_ARGS_SIZE 1024 #define VENDOR_BOOT_MAGIC "VNDRBOOT" +#define ANDR_VENDOR_BOOT_V3_SIZE 2112 /* sz(andr_vnd_boot_img_hdr) - sz(vendor_ramdisk_table*) */ +#define ANDR_VENDOR_BOOT_V4_SIZE 2128 /* sz(andr_vnd_boot_img_hdr) */ #define ANDR_VENDOR_BOOT_MAGIC_SIZE 8 #define ANDR_VENDOR_BOOT_ARGS_SIZE 2048 #define ANDR_VENDOR_BOOT_NAME_SIZE 16 -- cgit v1.2.3 From 8558aaa3cf9065ab5ec9a0b241ce567e7393dbc3 Mon Sep 17 00:00:00 2001 From: Osama Abdelkader Date: Sun, 14 Sep 2025 17:27:27 +0200 Subject: sandbox: use env_get() for time offset instead of getenv() The sandbox time offset is intended to be controlled via the U-Boot environment, not the host process environment. Update os_get_time_offset() to use env_get() instead of the libc getenv(). Leave other getenv() uses (e.g. U_BOOT_PERSISTENT_DATA_DIR, UBOOT_SB_FUZZ_TEST) unchanged, since those refer to host environment variables needed by sandbox tests. Signed-off-by: Osama Abdelkader --- arch/sandbox/cpu/os.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/arch/sandbox/cpu/os.c b/arch/sandbox/cpu/os.c index f5c9a8aecf2..e48eb23cdc0 100644 --- a/arch/sandbox/cpu/os.c +++ b/arch/sandbox/cpu/os.c @@ -35,6 +35,7 @@ #include #include #include +#include /* Environment variable for time offset */ #define ENV_TIME_OFFSET "UBOOT_SB_TIME_OFFSET" @@ -1014,7 +1015,7 @@ long os_get_time_offset(void) { const char *offset; - offset = getenv(ENV_TIME_OFFSET); + offset = env_get(ENV_TIME_OFFSET); if (offset) return strtol(offset, NULL, 0); return 0; -- cgit v1.2.3 From 5d0b813d6e4749da2cc8672216ea0f5b9b1b350f Mon Sep 17 00:00:00 2001 From: Osama Abdelkader Date: Sun, 14 Sep 2025 17:27:51 +0200 Subject: imls: remove return parentheses return is not a function, parentheses are not required Signed-off-by: Osama Abdelkader --- cmd/bootm.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/cmd/bootm.c b/cmd/bootm.c index bee683d0580..2c5aea26d98 100644 --- a/cmd/bootm.c +++ b/cmd/bootm.c @@ -572,7 +572,7 @@ static int do_imls(struct cmd_tbl *cmdtp, int flag, int argc, if (ret_nand) return ret_nand; - return (0); + return 0; } U_BOOT_CMD( -- cgit v1.2.3 From 7cae89bac47cd8e79c91034865e5a671334f73fd Mon Sep 17 00:00:00 2001 From: Jan Kiszka Date: Mon, 15 Sep 2025 15:41:46 +0200 Subject: lib: optee: Add line ending to debug() outputs Signed-off-by: Jan Kiszka --- lib/optee/optee.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/lib/optee/optee.c b/lib/optee/optee.c index 393f2715a9c..c643fd8fea0 100644 --- a/lib/optee/optee.c +++ b/lib/optee/optee.c @@ -87,7 +87,7 @@ static int optee_copy_firmware_node(ofnode node, void *fdt_blob) /* copy the compatible property */ prop = ofnode_get_property(node, "compatible", &len); if (!prop) { - debug("missing OP-TEE compatible property"); + debug("missing OP-TEE compatible property\n"); return -EINVAL; } @@ -98,7 +98,7 @@ static int optee_copy_firmware_node(ofnode node, void *fdt_blob) /* copy the method property */ prop = ofnode_get_property(node, "method", &len); if (!prop) { - debug("missing OP-TEE method property"); + debug("missing OP-TEE method property\n"); return -EINVAL; } @@ -121,7 +121,7 @@ int optee_copy_fdt_nodes(void *new_blob) /* only proceed if there is an /firmware/optee node */ node = ofnode_path("/firmware/optee"); if (!ofnode_valid(node)) { - debug("No OP-TEE firmware node in old fdt, nothing to do"); + debug("No OP-TEE firmware node in old fdt, nothing to do\n"); return 0; } @@ -131,7 +131,7 @@ int optee_copy_fdt_nodes(void *new_blob) * so do not interfere. */ if (fdt_path_offset(new_blob, "/firmware/optee") >= 0) { - debug("OP-TEE Device Tree node already exists in target"); + debug("OP-TEE Device Tree node already exists in target\n"); return 0; } -- cgit v1.2.3 From 44c4919e9dd6c162b237633ba689441eca9a149c Mon Sep 17 00:00:00 2001 From: Jan Kiszka Date: Mon, 15 Sep 2025 15:41:55 +0200 Subject: test: Fix optee unit test This was apparently not built for several years: Since a2535243e011, optee_copy_fdt_nodes implicitly works against the U-Boot dt. We therefore have to tweak its reference before using the function and restore things afterwards. If it had been built, actually trying it out would have failed next: We need CONFIG_OPTEE_LIB to actually build the function that is primarily being tested here. And we need to re-initialize target fdt, now that the tests may run in random order. Fixes: a2535243e011 ("lib: optee: migration optee_copy_fdt_nodes for OF_LIVE support") Fixes: ba2feaf41435 ("test: Split optee tests into three functions") Signed-off-by: Jan Kiszka --- test/optee/Kconfig | 1 + test/optee/optee.c | 42 +++++++++++++++++++++++++++++++----------- 2 files changed, 32 insertions(+), 11 deletions(-) diff --git a/test/optee/Kconfig b/test/optee/Kconfig index 63e2cbf79c7..ebf8d07c41c 100644 --- a/test/optee/Kconfig +++ b/test/optee/Kconfig @@ -1,6 +1,7 @@ config UT_OPTEE bool "Enable OP-TEE Unit Tests" depends on OF_CONTROL && OPTEE + select OPTEE_LIB default y help This enables the 'ut optee' command which runs a series of unit diff --git a/test/optee/optee.c b/test/optee/optee.c index 658621fa2fa..7e1c8d04a11 100644 --- a/test/optee/optee.c +++ b/test/optee/optee.c @@ -5,16 +5,20 @@ #include #include +#include #include #include #include #include +#include #include #include #include +DECLARE_GLOBAL_DATA_PTR; + /* 4k ought to be enough for anybody */ #define FDT_COPY_SIZE (4 * SZ_1K) @@ -40,14 +44,6 @@ static int optee_test_init(struct unit_test_state *uts) if (!fdt) return ret; - /* - * Resize the FDT to 4k so that we have room to operate on - * - * (and relocate it since the memory might be mapped - * read-only) - */ - ut_assertok(fdt_open_into(fdt_base, fdt, FDT_COPY_SIZE)); - return 0; } OPTEE_TEST_INIT(optee_test_init, 0); @@ -127,9 +123,21 @@ static int optee_fdt_protected_memory(struct unit_test_state *uts) static int optee_fdt_copy_empty(struct unit_test_state *uts) { void *fdt_no_optee = &__dtb_test_optee_no_optee_begin; + const void *fdt_blob = gd->fdt_blob; + + /* + * Resize the FDT to 4k so that we have room to operate on + * + * (and relocate it since the memory might be mapped + * read-only) + */ + ut_assertok(fdt_open_into(&__dtb_test_optee_base_begin, fdt, + FDT_COPY_SIZE)); /* This should still run successfully */ - ut_assertok(optee_copy_fdt_nodes(fdt_no_optee, fdt)); + gd->fdt_blob = fdt_no_optee; + ut_assertok(optee_copy_fdt_nodes(fdt)); + gd->fdt_blob = fdt_blob; expect_success = false; ut_assertok(optee_fdt_firmware(uts)); @@ -143,8 +151,14 @@ OPTEE_TEST(optee_fdt_copy_empty, 0); static int optee_fdt_copy_prefilled(struct unit_test_state *uts) { void *fdt_optee = &__dtb_test_optee_optee_begin; + const void *fdt_blob = gd->fdt_blob; - ut_assertok(optee_copy_fdt_nodes(fdt_optee, fdt)); + ut_assertok(fdt_open_into(&__dtb_test_optee_base_begin, fdt, + FDT_COPY_SIZE)); + + gd->fdt_blob = fdt_optee; + ut_assertok(optee_copy_fdt_nodes(fdt)); + gd->fdt_blob = fdt_blob; expect_success = true; ut_assertok(optee_fdt_firmware(uts)); @@ -158,9 +172,15 @@ OPTEE_TEST(optee_fdt_copy_prefilled, 0); static int optee_fdt_copy_already_filled(struct unit_test_state *uts) { void *fdt_optee = &__dtb_test_optee_optee_begin; + const void *fdt_blob = gd->fdt_blob; + + ut_assertok(fdt_open_into(&__dtb_test_optee_base_begin, fdt, + FDT_COPY_SIZE)); ut_assertok(fdt_open_into(fdt_optee, fdt, FDT_COPY_SIZE)); - ut_assertok(optee_copy_fdt_nodes(fdt_optee, fdt)); + gd->fdt_blob = fdt_optee; + ut_assertok(optee_copy_fdt_nodes(fdt)); + gd->fdt_blob = fdt_blob; expect_success = true; ut_assertok(optee_fdt_firmware(uts)); -- cgit v1.2.3 From f83a9e5df4cbb792e4b1c3f826b05f3fe8249dcc Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Thu, 11 Sep 2025 15:50:18 -0600 Subject: usb: dwc3: Tighten driver glue dependencies A few of the platform specific DWC3 host glue drivers cannot build without access to some platform specific header files. Express those requirements in Kconfig as well. Reviewed-by: Marek Vasut Signed-off-by: Tom Rini --- drivers/usb/dwc3/Kconfig | 9 ++++++--- 1 file changed, 6 insertions(+), 3 deletions(-) diff --git a/drivers/usb/dwc3/Kconfig b/drivers/usb/dwc3/Kconfig index 682a6910655..744dfa90463 100644 --- a/drivers/usb/dwc3/Kconfig +++ b/drivers/usb/dwc3/Kconfig @@ -17,6 +17,7 @@ comment "Platform Glue Driver Support" config USB_DWC3_OMAP bool "Texas Instruments OMAP5 and similar Platforms" + depends on ARCH_OMAP2PLUS help Some platforms from Texas Instruments like OMAP5, DRA7xxx and AM437x use this IP for USB2/3 functionality. @@ -39,14 +40,14 @@ config SPL_USB_DWC3_GENERIC config SPL_USB_DWC3_AM62 bool "TI AM62 USB wrapper" - depends on SPL_DM_USB && SPL_USB_DWC3_GENERIC && SPL_SYSCON + depends on SPL_DM_USB && SPL_USB_DWC3_GENERIC && SPL_SYSCON && ARCH_K3 help Select this for TI AM62 Platforms. This wrapper supports Host and Peripheral operation modes. config USB_DWC3_AM62 bool "TI AM62 USB wrapper" - depends on DM_USB && USB_DWC3_GENERIC && SYSCON + depends on DM_USB && USB_DWC3_GENERIC && SYSCON && ARCH_K3 help Select this for TI AM62 Platforms. This wrapper supports Host and Peripheral operation modes. @@ -80,7 +81,7 @@ config USB_DWC3_UNIPHIER config USB_DWC3_LAYERSCAPE bool "Freescale Layerscape platform support" depends on DM_USB && USB_DWC3 - depends on !USB_XHCI_FSL + depends on !USB_XHCI_FSL && ARM help Select this for Freescale Layerscape Platforms. @@ -99,12 +100,14 @@ menu "PHY Subsystem" config USB_DWC3_PHY_OMAP bool "TI OMAP SoC series USB DRD PHY driver" + depends on ARCH_OMAP2PLUS help Enable single driver for both USB2 PHY programming and USB3 PHY programming for TI SoCs. config USB_DWC3_PHY_SAMSUNG bool "Exynos5 SoC series USB DRD PHY driver" + depends on ARCH_EXYNOS help Enable USB DRD PHY support for Exynos 5 SoC series. This driver provides PHY interface for USB 3.0 DRD controller -- cgit v1.2.3 From 70553ec85f0002900e817ba64f84ff818bc28755 Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Thu, 11 Sep 2025 15:50:19 -0600 Subject: usb: gadget: Tighten requirements on USB_GADGET_ATMEL_USBA This driver requires some mach-at91 specific header files in order to build. Express that requirement in Kconfig as well. Reviewed-by: Marek Vasut Signed-off-by: Tom Rini --- drivers/usb/gadget/Kconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/usb/gadget/Kconfig b/drivers/usb/gadget/Kconfig index 0121f9872ae..29c2f27fa05 100644 --- a/drivers/usb/gadget/Kconfig +++ b/drivers/usb/gadget/Kconfig @@ -93,6 +93,7 @@ config USB_GADGET_PRODUCT_NUM config USB_GADGET_ATMEL_USBA bool "Atmel USBA" + depends on ARCH_AT91 select USB_GADGET_DUALSPEED help USBA is the integrated high-speed USB Device controller on -- cgit v1.2.3 From 219751e8c7259cb6e86a564e70fdf6c967862d55 Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Thu, 11 Sep 2025 15:50:20 -0600 Subject: usb: gadget: bcm_udc_otg: Remove unused driver This driver is unused since the removal of the bcm28155_ap board in commit 0f6807e77b07 ("arm: Remove bcm28155_ap board"). Remove it. Fixes: 0f6807e77b07 ("arm: Remove bcm28155_ap board") Signed-off-by: Tom Rini Reviewed-by: Marek Vasut --- drivers/usb/gadget/Kconfig | 5 ---- drivers/usb/gadget/Makefile | 1 - drivers/usb/gadget/bcm_udc_otg.h | 19 ------------- drivers/usb/gadget/bcm_udc_otg_phy.c | 54 ------------------------------------ 4 files changed, 79 deletions(-) delete mode 100644 drivers/usb/gadget/bcm_udc_otg.h delete mode 100644 drivers/usb/gadget/bcm_udc_otg_phy.c diff --git a/drivers/usb/gadget/Kconfig b/drivers/usb/gadget/Kconfig index 29c2f27fa05..c59d1d6252c 100644 --- a/drivers/usb/gadget/Kconfig +++ b/drivers/usb/gadget/Kconfig @@ -99,11 +99,6 @@ config USB_GADGET_ATMEL_USBA USBA is the integrated high-speed USB Device controller on the AT32AP700x, some AT91SAM9 and AT91CAP9 processors from Atmel. -config USB_GADGET_BCM_UDC_OTG_PHY - bool "Broadcom UDC OTG PHY" - help - Enable the Broadcom UDC OTG physical device interface. - config USB_GADGET_AT91 bool "Atmel AT91 USB Gadget Controller" depends on ARCH_AT91 diff --git a/drivers/usb/gadget/Makefile b/drivers/usb/gadget/Makefile index db5f8895a33..7af5f6e6d63 100644 --- a/drivers/usb/gadget/Makefile +++ b/drivers/usb/gadget/Makefile @@ -17,7 +17,6 @@ endif ifdef CONFIG_USB_GADGET obj-$(CONFIG_USB_GADGET_AT91) += at91_udc.o obj-$(CONFIG_USB_GADGET_ATMEL_USBA) += atmel_usba_udc.o -obj-$(CONFIG_USB_GADGET_BCM_UDC_OTG_PHY) += bcm_udc_otg_phy.o obj-$(CONFIG_USB_GADGET_DWC2_OTG) += dwc2_udc_otg.o obj-$(CONFIG_USB_GADGET_DWC2_OTG_PHY) += dwc2_udc_otg_phy.o obj-$(CONFIG_USB_GADGET_MAX3420) += max3420_udc.o diff --git a/drivers/usb/gadget/bcm_udc_otg.h b/drivers/usb/gadget/bcm_udc_otg.h deleted file mode 100644 index 48370f37d8a..00000000000 --- a/drivers/usb/gadget/bcm_udc_otg.h +++ /dev/null @@ -1,19 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright 2015 Broadcom Corporation. - */ - -#ifndef __BCM_UDC_OTG_H -#define __BCM_UDC_OTG_H - -static inline void wfld_set(uintptr_t addr, uint32_t fld_val, uint32_t fld_mask) -{ - writel(((readl(addr) & ~(fld_mask)) | (fld_val)), (addr)); -} - -static inline void wfld_clear(uintptr_t addr, uint32_t fld_mask) -{ - writel((readl(addr) & ~(fld_mask)), (addr)); -} - -#endif diff --git a/drivers/usb/gadget/bcm_udc_otg_phy.c b/drivers/usb/gadget/bcm_udc_otg_phy.c deleted file mode 100644 index 9875191091c..00000000000 --- a/drivers/usb/gadget/bcm_udc_otg_phy.c +++ /dev/null @@ -1,54 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright 2015 Broadcom Corporation. - */ - -#include -#include -#include -#include -#include - -#include "dwc2_udc_otg_priv.h" -#include "bcm_udc_otg.h" - -void otg_phy_init(struct dwc2_udc *dev) -{ - /* turn on the USB OTG clocks */ - clk_usb_otg_enable((void *)HSOTG_BASE_ADDR); - - /* set Phy to driving mode */ - wfld_clear(HSOTG_CTRL_BASE_ADDR + HSOTG_CTRL_PHY_P1CTL_OFFSET, - HSOTG_CTRL_PHY_P1CTL_NON_DRIVING_MASK); - - udelay(100); - - /* clear Soft Disconnect */ - wfld_clear(HSOTG_BASE_ADDR + HSOTG_DCTL_OFFSET, - HSOTG_DCTL_SFTDISCON_MASK); - - /* invoke Reset (active low) */ - wfld_clear(HSOTG_CTRL_BASE_ADDR + HSOTG_CTRL_PHY_P1CTL_OFFSET, - HSOTG_CTRL_PHY_P1CTL_SOFT_RESET_MASK); - - /* Reset needs to be asserted for 2ms */ - udelay(2000); - - /* release Reset */ - wfld_set(HSOTG_CTRL_BASE_ADDR + HSOTG_CTRL_PHY_P1CTL_OFFSET, - HSOTG_CTRL_PHY_P1CTL_SOFT_RESET_MASK, - HSOTG_CTRL_PHY_P1CTL_SOFT_RESET_MASK); -} - -void otg_phy_off(struct dwc2_udc *dev) -{ - /* Soft Disconnect */ - wfld_set(HSOTG_BASE_ADDR + HSOTG_DCTL_OFFSET, - HSOTG_DCTL_SFTDISCON_MASK, - HSOTG_DCTL_SFTDISCON_MASK); - - /* set Phy to non-driving (reset) mode */ - wfld_set(HSOTG_CTRL_BASE_ADDR + HSOTG_CTRL_PHY_P1CTL_OFFSET, - HSOTG_CTRL_PHY_P1CTL_NON_DRIVING_MASK, - HSOTG_CTRL_PHY_P1CTL_NON_DRIVING_MASK); -} -- cgit v1.2.3 From 56edb1cc76c1de79b852d51fa79fb64142f1e901 Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Thu, 11 Sep 2025 15:50:21 -0600 Subject: usb: gadget: max3420_udc: Remove unused driver This driver was never enabled by any platforms after being added to the tree over 5 years ago. Remove it. Signed-off-by: Tom Rini Reviewed-by: Marek Vasut --- drivers/usb/gadget/Kconfig | 6 - drivers/usb/gadget/Makefile | 1 - drivers/usb/gadget/max3420_udc.c | 879 --------------------------------------- 3 files changed, 886 deletions(-) delete mode 100644 drivers/usb/gadget/max3420_udc.c diff --git a/drivers/usb/gadget/Kconfig b/drivers/usb/gadget/Kconfig index c59d1d6252c..e845e46e0b7 100644 --- a/drivers/usb/gadget/Kconfig +++ b/drivers/usb/gadget/Kconfig @@ -152,12 +152,6 @@ config CI_UDC Say Y here to enable device controller functionality of the ChipIdea driver. -config USB_GADGET_MAX3420 - bool "MAX3420 USB Over SPI" - depends on DM_SPI - help - MAX3420, from MAXIM, implements USB-over-SPI Full-Speed device controller. - config USB_GADGET_VBUS_DRAW int "Maximum VBUS Power usage (2-500 mA)" range 2 500 diff --git a/drivers/usb/gadget/Makefile b/drivers/usb/gadget/Makefile index 7af5f6e6d63..f2aebf4e480 100644 --- a/drivers/usb/gadget/Makefile +++ b/drivers/usb/gadget/Makefile @@ -19,7 +19,6 @@ obj-$(CONFIG_USB_GADGET_AT91) += at91_udc.o obj-$(CONFIG_USB_GADGET_ATMEL_USBA) += atmel_usba_udc.o obj-$(CONFIG_USB_GADGET_DWC2_OTG) += dwc2_udc_otg.o obj-$(CONFIG_USB_GADGET_DWC2_OTG_PHY) += dwc2_udc_otg_phy.o -obj-$(CONFIG_USB_GADGET_MAX3420) += max3420_udc.o obj-$(CONFIG_USB_RENESAS_USBHS) += rcar/ ifndef CONFIG_XPL_BUILD obj-$(CONFIG_USB_GADGET_DOWNLOAD) += g_dnl.o diff --git a/drivers/usb/gadget/max3420_udc.c b/drivers/usb/gadget/max3420_udc.c deleted file mode 100644 index 557a1f0644e..00000000000 --- a/drivers/usb/gadget/max3420_udc.c +++ /dev/null @@ -1,879 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#define MAX3420_MAX_EPS 4 -#define EP_MAX_PACKET 64 /* Same for all Endpoints */ -#define EPNAME_SIZE 16 /* Buffer size for endpoint name */ - -#define MAX3420_SPI_DIR_RD 0 /* read register from MAX3420 */ -#define MAX3420_SPI_DIR_WR 1 /* write register to MAX3420 */ - -/* SPI commands: */ -#define MAX3420_SPI_ACK_MASK BIT(0) -#define MAX3420_SPI_DIR_MASK BIT(1) -#define MAX3420_SPI_REG_MASK GENMASK(7, 3) - -#define MAX3420_REG_EP0FIFO 0 -#define MAX3420_REG_EP1FIFO 1 -#define MAX3420_REG_EP2FIFO 2 -#define MAX3420_REG_EP3FIFO 3 -#define MAX3420_REG_SUDFIFO 4 -#define MAX3420_REG_EP0BC 5 -#define MAX3420_REG_EP1BC 6 -#define MAX3420_REG_EP2BC 7 -#define MAX3420_REG_EP3BC 8 - -#define MAX3420_REG_EPSTALLS 9 - #define bACKSTAT BIT(6) - #define bSTLSTAT BIT(5) - #define bSTLEP3IN BIT(4) - #define bSTLEP2IN BIT(3) - #define bSTLEP1OUT BIT(2) - #define bSTLEP0OUT BIT(1) - #define bSTLEP0IN BIT(0) - -#define MAX3420_REG_CLRTOGS 10 - #define bEP3DISAB BIT(7) - #define bEP2DISAB BIT(6) - #define bEP1DISAB BIT(5) - #define bCTGEP3IN BIT(4) - #define bCTGEP2IN BIT(3) - #define bCTGEP1OUT BIT(2) - -#define MAX3420_REG_EPIRQ 11 -#define MAX3420_REG_EPIEN 12 - #define bSUDAVIRQ BIT(5) - #define bIN3BAVIRQ BIT(4) - #define bIN2BAVIRQ BIT(3) - #define bOUT1DAVIRQ BIT(2) - #define bOUT0DAVIRQ BIT(1) - #define bIN0BAVIRQ BIT(0) - -#define MAX3420_REG_USBIRQ 13 -#define MAX3420_REG_USBIEN 14 - #define bOSCOKIRQ BIT(0) - #define bRWUDNIRQ BIT(1) - #define bBUSACTIRQ BIT(2) - #define bURESIRQ BIT(3) - #define bSUSPIRQ BIT(4) - #define bNOVBUSIRQ BIT(5) - #define bVBUSIRQ BIT(6) - #define bURESDNIRQ BIT(7) - -#define MAX3420_REG_USBCTL 15 - #define bHOSCSTEN BIT(7) - #define bVBGATE BIT(6) - #define bCHIPRES BIT(5) - #define bPWRDOWN BIT(4) - #define bCONNECT BIT(3) - #define bSIGRWU BIT(2) - -#define MAX3420_REG_CPUCTL 16 - #define bIE BIT(0) - -#define MAX3420_REG_PINCTL 17 - #define bEP3INAK BIT(7) - #define bEP2INAK BIT(6) - #define bEP0INAK BIT(5) - #define bFDUPSPI BIT(4) - #define bINTLEVEL BIT(3) - #define bPOSINT BIT(2) - #define bGPXB BIT(1) - #define bGPXA BIT(0) - -#define MAX3420_REG_REVISION 18 - -#define MAX3420_REG_FNADDR 19 - #define FNADDR_MASK 0x7f - -#define MAX3420_REG_IOPINS 20 -#define MAX3420_REG_IOPINS2 21 -#define MAX3420_REG_GPINIRQ 22 -#define MAX3420_REG_GPINIEN 23 -#define MAX3420_REG_GPINPOL 24 -#define MAX3420_REG_HIRQ 25 -#define MAX3420_REG_HIEN 26 -#define MAX3420_REG_MODE 27 -#define MAX3420_REG_PERADDR 28 -#define MAX3420_REG_HCTL 29 -#define MAX3420_REG_HXFR 30 -#define MAX3420_REG_HRSL 31 - -struct max3420_req { - struct usb_request usb_req; - struct list_head queue; - struct max3420_ep *ep; -}; - -struct max3420_ep { - struct max3420_udc *udc; - struct list_head queue; - char name[EPNAME_SIZE]; - unsigned int maxpacket; - struct usb_ep ep_usb; - int halted; - int id; -}; - -struct max3420_udc { - struct max3420_ep ep[MAX3420_MAX_EPS]; - struct usb_gadget_driver *driver; - bool softconnect; - struct usb_ctrlrequest setup; - struct max3420_req ep0req; - struct usb_gadget gadget; - struct spi_slave *slave; - struct udevice *dev; - u8 ep0buf[64]; - int remote_wkp; - bool suspended; -}; - -#define to_max3420_req(r) container_of((r), struct max3420_req, usb_req) -#define to_max3420_ep(e) container_of((e), struct max3420_ep, ep_usb) -#define to_udc(g) container_of((g), struct max3420_udc, gadget) - -static void spi_ack_ctrl(struct max3420_udc *udc) -{ - struct spi_slave *slave = udc->slave; - u8 txdata[1]; - - txdata[0] = FIELD_PREP(MAX3420_SPI_ACK_MASK, 1); - spi_xfer(slave, sizeof(txdata), txdata, NULL, SPI_XFER_ONCE); -} - -static u8 spi_rd8_ack(struct max3420_udc *udc, u8 reg, int ackstat) -{ - struct spi_slave *slave = udc->slave; - u8 txdata[2], rxdata[2]; - - txdata[0] = FIELD_PREP(MAX3420_SPI_REG_MASK, reg) | - FIELD_PREP(MAX3420_SPI_DIR_MASK, MAX3420_SPI_DIR_RD) | - FIELD_PREP(MAX3420_SPI_ACK_MASK, ackstat ? 1 : 0); - - rxdata[0] = 0; - rxdata[1] = 0; - spi_xfer(slave, sizeof(txdata), txdata, rxdata, SPI_XFER_ONCE); - - return rxdata[1]; -} - -static u8 spi_rd8(struct max3420_udc *udc, u8 reg) -{ - return spi_rd8_ack(udc, reg, 0); -} - -static void spi_wr8_ack(struct max3420_udc *udc, u8 reg, u8 val, int ackstat) -{ - struct spi_slave *slave = udc->slave; - u8 txdata[2]; - - txdata[0] = FIELD_PREP(MAX3420_SPI_REG_MASK, reg) | - FIELD_PREP(MAX3420_SPI_DIR_MASK, MAX3420_SPI_DIR_WR) | - FIELD_PREP(MAX3420_SPI_ACK_MASK, ackstat ? 1 : 0); - txdata[1] = val; - - spi_xfer(slave, sizeof(txdata), txdata, NULL, SPI_XFER_ONCE); -} - -static void spi_wr8(struct max3420_udc *udc, u8 reg, u8 val) -{ - spi_wr8_ack(udc, reg, val, 0); -} - -static void spi_rd_buf(struct max3420_udc *udc, u8 reg, void *buf, u8 len) -{ - struct spi_slave *slave = udc->slave; - u8 txdata[1]; - - txdata[0] = FIELD_PREP(MAX3420_SPI_REG_MASK, reg) | - FIELD_PREP(MAX3420_SPI_DIR_MASK, MAX3420_SPI_DIR_RD); - - spi_xfer(slave, sizeof(txdata), txdata, NULL, SPI_XFER_BEGIN); - spi_xfer(slave, len * 8, NULL, buf, SPI_XFER_END); -} - -static void spi_wr_buf(struct max3420_udc *udc, u8 reg, void *buf, u8 len) -{ - struct spi_slave *slave = udc->slave; - u8 txdata[1]; - - txdata[0] = FIELD_PREP(MAX3420_SPI_REG_MASK, reg) | - FIELD_PREP(MAX3420_SPI_DIR_MASK, MAX3420_SPI_DIR_WR); - - spi_xfer(slave, sizeof(txdata), txdata, NULL, SPI_XFER_BEGIN); - spi_xfer(slave, len * 8, buf, NULL, SPI_XFER_END); -} - -/* 0 if not-connected */ -int g_dnl_board_usb_cable_connected(void) -{ - return 1; -} - -static void spi_max3420_enable(struct max3420_ep *ep, int enable) -{ - struct max3420_udc *udc = ep->udc; - u8 epdis, epien; - - if (ep->id == 0) - return; - - epien = spi_rd8(udc, MAX3420_REG_EPIEN); - epdis = spi_rd8(udc, MAX3420_REG_CLRTOGS); - - if (enable) { - epdis &= ~BIT(ep->id + 4); - epien |= BIT(ep->id + 1); - } else { - epdis |= BIT(ep->id + 4); - epien &= ~BIT(ep->id + 1); - } - - spi_wr8(udc, MAX3420_REG_CLRTOGS, epdis); - spi_wr8(udc, MAX3420_REG_EPIEN, epien); -} - -static int -max3420_ep_enable(struct usb_ep *_ep, - const struct usb_endpoint_descriptor *desc) -{ - struct max3420_ep *ep = to_max3420_ep(_ep); - - _ep->desc = desc; - _ep->maxpacket = usb_endpoint_maxp(desc) & 0x7ff; - - spi_max3420_enable(ep, 1); - - return 0; -} - -static void max3420_req_done(struct max3420_req *req, int status) -{ - struct max3420_ep *ep = req->ep; - - if (req->usb_req.status == -EINPROGRESS) - req->usb_req.status = status; - else - status = req->usb_req.status; - - if (status && status != -ESHUTDOWN) - dev_err(ep->udc->dev, "%s done %p, status %d\n", - ep->ep_usb.name, req, status); - - if (req->usb_req.complete) - req->usb_req.complete(&ep->ep_usb, &req->usb_req); -} - -static void max3420_ep_nuke(struct max3420_ep *ep, int status) -{ - struct max3420_req *req, *r; - - list_for_each_entry_safe(req, r, &ep->queue, queue) { - list_del_init(&req->queue); - max3420_req_done(req, status); - } -} - -static int max3420_ep_disable(struct usb_ep *_ep) -{ - struct max3420_ep *ep = to_max3420_ep(_ep); - - _ep->desc = NULL; - max3420_ep_nuke(ep, -ESHUTDOWN); - spi_max3420_enable(ep, 0); - - return 0; -} - -static struct usb_request * -max3420_ep_alloc_request(struct usb_ep *_ep, gfp_t gfp_flags) -{ - struct max3420_ep *ep = to_max3420_ep(_ep); - struct max3420_req *req = kzalloc(sizeof(*req), gfp_flags); - - if (!req) - return NULL; - - req->ep = ep; - INIT_LIST_HEAD(&req->queue); - - return &req->usb_req; -} - -static void -max3420_ep_free_request(struct usb_ep *_ep, struct usb_request *_req) -{ - kfree(to_max3420_req(_req)); -} - -static int -max3420_ep_queue(struct usb_ep *_ep, struct usb_request *_req, gfp_t gfp_flags) -{ - struct max3420_req *req = to_max3420_req(_req); - struct max3420_ep *ep = to_max3420_ep(_ep); - - _req->status = -EINPROGRESS; - _req->actual = 0; - list_add_tail(&req->queue, &ep->queue); - - return 0; -} - -static int max3420_ep_dequeue(struct usb_ep *_ep, struct usb_request *_req) -{ - struct max3420_req *req = to_max3420_req(_req); - - list_del_init(&req->queue); - max3420_req_done(req, -ECONNRESET); - - return 0; -} - -static int max3420_ep_set_halt(struct usb_ep *_ep, int halt) -{ - struct max3420_ep *ep = to_max3420_ep(_ep); - struct max3420_udc *udc = ep->udc; - u8 epstalls; - - if (ep->id == 0) /* can't stall EP0 */ - return 0; - - epstalls = spi_rd8(udc, MAX3420_REG_EPSTALLS); - if (halt) { - ep->halted = 1; - epstalls |= BIT(ep->id + 1); - } else { - u8 clrtogs; - - ep->halted = 0; - epstalls &= ~BIT(ep->id + 1); - clrtogs = spi_rd8(udc, MAX3420_REG_CLRTOGS); - clrtogs |= BIT(ep->id + 1); - spi_wr8(udc, MAX3420_REG_CLRTOGS, clrtogs); - } - spi_wr8(udc, MAX3420_REG_EPSTALLS, epstalls | bACKSTAT); - - return 0; -} - -static const struct usb_ep_ops max3420_ep_ops = { - .enable = max3420_ep_enable, - .disable = max3420_ep_disable, - .alloc_request = max3420_ep_alloc_request, - .free_request = max3420_ep_free_request, - .queue = max3420_ep_queue, - .dequeue = max3420_ep_dequeue, - .set_halt = max3420_ep_set_halt, -}; - -static void __max3420_stop(struct max3420_udc *udc) -{ - u8 val; - - /* Disable IRQ to CPU */ - spi_wr8(udc, MAX3420_REG_CPUCTL, 0); - - val = spi_rd8(udc, MAX3420_REG_USBCTL); - val |= bPWRDOWN; - val |= bHOSCSTEN; - spi_wr8(udc, MAX3420_REG_USBCTL, val); -} - -static void __max3420_start(struct max3420_udc *udc) -{ - u8 val; - - /* configure SPI */ - spi_wr8(udc, MAX3420_REG_PINCTL, bFDUPSPI); - - /* Chip Reset */ - spi_wr8(udc, MAX3420_REG_USBCTL, bCHIPRES); - mdelay(5); - spi_wr8(udc, MAX3420_REG_USBCTL, 0); - - /* Poll for OSC to stabilize */ - while (1) { - val = spi_rd8(udc, MAX3420_REG_USBIRQ); - if (val & bOSCOKIRQ) - break; - cond_resched(); - } - - /* Enable PULL-UP only when Vbus detected */ - val = spi_rd8(udc, MAX3420_REG_USBCTL); - val |= bVBGATE | bCONNECT; - spi_wr8(udc, MAX3420_REG_USBCTL, val); - - val = bURESDNIRQ | bURESIRQ; - spi_wr8(udc, MAX3420_REG_USBIEN, val); - - /* Enable only EP0 interrupts */ - val = bIN0BAVIRQ | bOUT0DAVIRQ | bSUDAVIRQ; - spi_wr8(udc, MAX3420_REG_EPIEN, val); - - /* Enable IRQ to CPU */ - spi_wr8(udc, MAX3420_REG_CPUCTL, bIE); -} - -static int max3420_udc_start(struct usb_gadget *gadget, - struct usb_gadget_driver *driver) -{ - struct max3420_udc *udc = to_udc(gadget); - - udc->driver = driver; - udc->remote_wkp = 0; - udc->softconnect = true; - - __max3420_start(udc); - - return 0; -} - -static int max3420_udc_stop(struct usb_gadget *gadget) -{ - struct max3420_udc *udc = to_udc(gadget); - - udc->driver = NULL; - udc->softconnect = false; - - __max3420_stop(udc); - - return 0; -} - -static int max3420_wakeup(struct usb_gadget *gadget) -{ - struct max3420_udc *udc = to_udc(gadget); - u8 usbctl; - - /* Only if wakeup allowed by host */ - if (!udc->remote_wkp || !udc->suspended) - return 0; - - /* Set Remote-Wakeup Signal*/ - usbctl = spi_rd8(udc, MAX3420_REG_USBCTL); - usbctl |= bSIGRWU; - spi_wr8(udc, MAX3420_REG_USBCTL, usbctl); - - mdelay(5); - - /* Clear Remote-WkUp Signal*/ - usbctl = spi_rd8(udc, MAX3420_REG_USBCTL); - usbctl &= ~bSIGRWU; - spi_wr8(udc, MAX3420_REG_USBCTL, usbctl); - - udc->suspended = false; - - return 0; -} - -static const struct usb_gadget_ops max3420_udc_ops = { - .udc_start = max3420_udc_start, - .udc_stop = max3420_udc_stop, - .wakeup = max3420_wakeup, -}; - -static struct usb_endpoint_descriptor ep0_desc = { - .bLength = USB_DT_ENDPOINT_SIZE, - .bDescriptorType = USB_DT_ENDPOINT, - .bEndpointAddress = USB_DIR_OUT, - .bmAttributes = USB_ENDPOINT_XFER_CONTROL, - .wMaxPacketSize = cpu_to_le16(EP_MAX_PACKET), -}; - -static void max3420_getstatus(struct max3420_udc *udc) -{ - struct max3420_ep *ep; - u16 status = 0; - - switch (udc->setup.bRequestType & USB_RECIP_MASK) { - case USB_RECIP_DEVICE: - /* Get device status */ - status = 0 << USB_DEVICE_SELF_POWERED; - status |= (udc->remote_wkp << USB_DEVICE_REMOTE_WAKEUP); - break; - case USB_RECIP_INTERFACE: - if (udc->driver->setup(&udc->gadget, &udc->setup) < 0) - goto stall; - break; - case USB_RECIP_ENDPOINT: - ep = &udc->ep[udc->setup.wIndex & USB_ENDPOINT_NUMBER_MASK]; - if (ep->halted) - status = 1 << USB_ENDPOINT_HALT; - break; - default: - goto stall; - } - - status = cpu_to_le16(status); - spi_wr_buf(udc, MAX3420_REG_EP0FIFO, &status, 2); - spi_wr8_ack(udc, MAX3420_REG_EP0BC, 2, 1); - return; -stall: - dev_err(udc->dev, "Can't respond to getstatus request\n"); - spi_wr8(udc, MAX3420_REG_EPSTALLS, bSTLEP0IN | bSTLEP0OUT | bSTLSTAT); -} - -static void max3420_set_clear_feature(struct max3420_udc *udc) -{ - int set = udc->setup.bRequest == USB_REQ_SET_FEATURE; - struct max3420_ep *ep; - int id; - - switch (udc->setup.bRequestType) { - case USB_RECIP_DEVICE: - if (udc->setup.wValue != USB_DEVICE_REMOTE_WAKEUP) - break; - - if (udc->setup.bRequest == USB_REQ_SET_FEATURE) - udc->remote_wkp = 1; - else - udc->remote_wkp = 0; - - return spi_ack_ctrl(udc); - - case USB_RECIP_ENDPOINT: - if (udc->setup.wValue != USB_ENDPOINT_HALT) - break; - - id = udc->setup.wIndex & USB_ENDPOINT_NUMBER_MASK; - ep = &udc->ep[id]; - - max3420_ep_set_halt(&ep->ep_usb, set); - return; - default: - break; - } - - dev_err(udc->dev, "Can't respond to SET/CLEAR FEATURE\n"); - spi_wr8(udc, MAX3420_REG_EPSTALLS, bSTLEP0IN | bSTLEP0OUT | bSTLSTAT); -} - -static void max3420_handle_setup(struct max3420_udc *udc) -{ - struct usb_ctrlrequest setup; - u8 addr; - - spi_rd_buf(udc, MAX3420_REG_SUDFIFO, (void *)&setup, 8); - - udc->setup = setup; - udc->setup.wValue = cpu_to_le16(setup.wValue); - udc->setup.wIndex = cpu_to_le16(setup.wIndex); - udc->setup.wLength = cpu_to_le16(setup.wLength); - - switch (udc->setup.bRequest) { - case USB_REQ_GET_STATUS: - /* Data+Status phase form udc */ - if ((udc->setup.bRequestType & - (USB_DIR_IN | USB_TYPE_MASK)) != - (USB_DIR_IN | USB_TYPE_STANDARD)) { - break; - } - return max3420_getstatus(udc); - case USB_REQ_SET_ADDRESS: - /* Status phase from udc */ - if (udc->setup.bRequestType != (USB_DIR_OUT | - USB_TYPE_STANDARD | USB_RECIP_DEVICE)) - break; - addr = spi_rd8_ack(udc, MAX3420_REG_FNADDR, 1); - dev_dbg(udc->dev, "Assigned Address=%d/%d\n", - udc->setup.wValue, addr); - return; - case USB_REQ_CLEAR_FEATURE: - case USB_REQ_SET_FEATURE: - /* Requests with no data phase, status phase from udc */ - if ((udc->setup.bRequestType & USB_TYPE_MASK) - != USB_TYPE_STANDARD) - break; - return max3420_set_clear_feature(udc); - default: - break; - } - - if (udc->driver->setup(&udc->gadget, &setup) < 0) { - /* Stall EP0 */ - spi_wr8(udc, MAX3420_REG_EPSTALLS, - bSTLEP0IN | bSTLEP0OUT | bSTLSTAT); - } -} - -static int do_data(struct max3420_udc *udc, int ep_id, int in) -{ - struct max3420_ep *ep = &udc->ep[ep_id]; - struct max3420_req *req; - int done, length, psz; - void *buf; - - if (list_empty(&ep->queue)) - return 0; - - req = list_first_entry(&ep->queue, struct max3420_req, queue); - buf = req->usb_req.buf + req->usb_req.actual; - - psz = ep->ep_usb.maxpacket; - length = req->usb_req.length - req->usb_req.actual; - length = min(length, psz); - - if (length == 0) { - done = 1; - goto xfer_done; - } - - done = 0; - if (in) { - spi_wr_buf(udc, MAX3420_REG_EP0FIFO + ep_id, buf, length); - spi_wr8(udc, MAX3420_REG_EP0BC + ep_id, length); - if (length < psz) - done = 1; - } else { - psz = spi_rd8(udc, MAX3420_REG_EP0BC + ep_id); - length = min(length, psz); - spi_rd_buf(udc, MAX3420_REG_EP0FIFO + ep_id, buf, length); - if (length < ep->ep_usb.maxpacket) - done = 1; - } - - req->usb_req.actual += length; - - if (req->usb_req.actual == req->usb_req.length) - done = 1; - -xfer_done: - if (done) { - list_del_init(&req->queue); - - if (ep_id == 0) - spi_ack_ctrl(udc); - - max3420_req_done(req, 0); - } - - return 1; -} - -static int max3420_handle_irqs(struct max3420_udc *udc) -{ - u8 epien, epirq, usbirq, usbien, reg[4]; - int ret = 0; - - spi_rd_buf(udc, MAX3420_REG_EPIRQ, reg, 4); - epirq = reg[0]; - epien = reg[1]; - usbirq = reg[2]; - usbien = reg[3]; - - usbirq &= usbien; - epirq &= epien; - - if (epirq & bSUDAVIRQ) { - spi_wr8(udc, MAX3420_REG_EPIRQ, bSUDAVIRQ); - max3420_handle_setup(udc); - return 1; - } - - if (usbirq & bVBUSIRQ) { - spi_wr8(udc, MAX3420_REG_USBIRQ, bVBUSIRQ); - dev_dbg(udc->dev, "Cable plugged in\n"); - g_dnl_clear_detach(); - return 1; - } - - if (usbirq & bNOVBUSIRQ) { - spi_wr8(udc, MAX3420_REG_USBIRQ, bNOVBUSIRQ); - dev_dbg(udc->dev, "Cable pulled out\n"); - g_dnl_trigger_detach(); - return 1; - } - - if (usbirq & bURESIRQ) { - spi_wr8(udc, MAX3420_REG_USBIRQ, bURESIRQ); - return 1; - } - - if (usbirq & bURESDNIRQ) { - spi_wr8(udc, MAX3420_REG_USBIRQ, bURESDNIRQ); - spi_wr8(udc, MAX3420_REG_USBIEN, bURESDNIRQ | bURESIRQ); - spi_wr8(udc, MAX3420_REG_EPIEN, bSUDAVIRQ - | bIN0BAVIRQ | bOUT0DAVIRQ); - return 1; - } - - if (usbirq & bSUSPIRQ) { - spi_wr8(udc, MAX3420_REG_USBIRQ, bSUSPIRQ); - dev_dbg(udc->dev, "USB Suspend - Enter\n"); - udc->suspended = true; - return 1; - } - - if (usbirq & bBUSACTIRQ) { - spi_wr8(udc, MAX3420_REG_USBIRQ, bBUSACTIRQ); - dev_dbg(udc->dev, "USB Suspend - Exit\n"); - udc->suspended = false; - return 1; - } - - if (usbirq & bRWUDNIRQ) { - spi_wr8(udc, MAX3420_REG_USBIRQ, bRWUDNIRQ); - dev_dbg(udc->dev, "Asked Host to wakeup\n"); - return 1; - } - - if (usbirq & bOSCOKIRQ) { - spi_wr8(udc, MAX3420_REG_USBIRQ, bOSCOKIRQ); - dev_dbg(udc->dev, "Osc stabilized, start work\n"); - return 1; - } - - if (epirq & bOUT0DAVIRQ && do_data(udc, 0, 0)) { - spi_wr8_ack(udc, MAX3420_REG_EPIRQ, bOUT0DAVIRQ, 1); - ret = 1; - } - - if (epirq & bIN0BAVIRQ && do_data(udc, 0, 1)) - ret = 1; - - if (epirq & bOUT1DAVIRQ && do_data(udc, 1, 0)) { - spi_wr8_ack(udc, MAX3420_REG_EPIRQ, bOUT1DAVIRQ, 1); - ret = 1; - } - - if (epirq & bIN2BAVIRQ && do_data(udc, 2, 1)) - ret = 1; - - if (epirq & bIN3BAVIRQ && do_data(udc, 3, 1)) - ret = 1; - - return ret; -} - -static int max3420_irq(struct max3420_udc *udc) -{ - do_data(udc, 0, 1); /* get done with the EP0 ZLP */ - - return max3420_handle_irqs(udc); -} - -static void max3420_setup_eps(struct max3420_udc *udc) -{ - int i; - - INIT_LIST_HEAD(&udc->gadget.ep_list); - INIT_LIST_HEAD(&udc->ep[0].ep_usb.ep_list); - - for (i = 0; i < MAX3420_MAX_EPS; i++) { - struct max3420_ep *ep = &udc->ep[i]; - - INIT_LIST_HEAD(&ep->queue); - - ep->id = i; - ep->udc = udc; - ep->ep_usb.ops = &max3420_ep_ops; - ep->ep_usb.name = ep->name; - ep->ep_usb.maxpacket = EP_MAX_PACKET; - - if (i == 0) { - ep->ep_usb.desc = &ep0_desc; - snprintf(ep->name, EPNAME_SIZE, "ep0"); - continue; - } - - list_add_tail(&ep->ep_usb.ep_list, &udc->gadget.ep_list); - - if (i == 1) - snprintf(ep->name, EPNAME_SIZE, "ep1out-bulk"); - else - snprintf(ep->name, EPNAME_SIZE, "ep%din-bulk", i); - }; -} - -static void max3420_setup_spi(struct max3420_udc *udc) -{ - u8 reg[8]; - - spi_claim_bus(udc->slave); - spi_rd_buf(udc, MAX3420_REG_EPIRQ, reg, 8); - /* configure SPI */ - spi_wr8(udc, MAX3420_REG_PINCTL, bFDUPSPI); -} - -static int max3420_udc_probe(struct udevice *dev) -{ - struct max3420_udc *udc = dev_get_priv(dev); - struct dm_spi_slave_plat *slave_pdata; - struct udevice *bus = dev->parent; - int busnum = dev_seq(bus); - unsigned int cs; - uint speed, mode; - struct udevice *spid; - - slave_pdata = dev_get_parent_plat(dev); - cs = slave_pdata->cs; - speed = slave_pdata->max_hz; - mode = slave_pdata->mode; - _spi_get_bus_and_cs(busnum, cs, speed, mode, false, "spi_generic_drv", - NULL, &spid, &udc->slave); - - udc->dev = dev; - udc->gadget.ep0 = &udc->ep[0].ep_usb; - udc->gadget.max_speed = USB_SPEED_FULL; - udc->gadget.speed = USB_SPEED_FULL; - udc->gadget.is_dualspeed = 0; - udc->gadget.ops = &max3420_udc_ops; - udc->gadget.name = "max3420-udc"; - - max3420_setup_eps(udc); - max3420_setup_spi(udc); - - usb_add_gadget_udc((struct device *)dev, &udc->gadget); - - return 0; -} - -static int max3420_udc_remove(struct udevice *dev) -{ - struct max3420_udc *udc = dev_get_priv(dev); - - usb_del_gadget_udc(&udc->gadget); - - spi_release_bus(udc->slave); - - return 0; -} - -static int max3420_gadget_handle_interrupts(struct udevice *dev) -{ - struct max3420_udc *udc = dev_get_priv(dev); - - return max3420_irq(udc); -} - -static const struct usb_gadget_generic_ops max3420_gadget_ops = { - .handle_interrupts = max3420_gadget_handle_interrupts, -}; - -static const struct udevice_id max3420_ids[] = { - { .compatible = "maxim,max3421-udc" }, - { } -}; - -U_BOOT_DRIVER(max3420_generic_udc) = { - .name = "max3420-udc", - .id = UCLASS_USB_GADGET_GENERIC, - .of_match = max3420_ids, - .ops = &max3420_gadget_ops, - .probe = max3420_udc_probe, - .remove = max3420_udc_remove, - .priv_auto = sizeof(struct max3420_udc), -}; -- cgit v1.2.3 From be8c07b606b84b5500971d8e518e80152588bd54 Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Thu, 11 Sep 2025 15:50:22 -0600 Subject: usb: host: Tighten USB host driver dependencies A few of the USB host drivers cannot build without access to some platform specific header files. Express those requirements in Kconfig as well. Reviewed-by: Marek Vasut Signed-off-by: Tom Rini --- drivers/usb/host/Kconfig | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) diff --git a/drivers/usb/host/Kconfig b/drivers/usb/host/Kconfig index 5c9e8fc9d15..2cf687fc4f3 100644 --- a/drivers/usb/host/Kconfig +++ b/drivers/usb/host/Kconfig @@ -121,8 +121,9 @@ config USB_XHCI_DRA7XX_INDEX config USB_XHCI_FSL bool "Support for NXP Layerscape on-chip xHCI USB controller" - default y if ARCH_LS1021A || FSL_LSCH3 || FSL_LSCH2 + depends on ARCH_LS1021A || FSL_LSCH3 || FSL_LSCH2 depends on !SPL_NO_USB + default y help Enables support for the on-chip xHCI controller on NXP Layerscape SoCs. @@ -286,7 +287,8 @@ config USB_EHCI_TEGRA config USB_EHCI_ZYNQ bool "Support for Xilinx Zynq on-chip EHCI USB controller" - default y if ARCH_ZYNQ + depends on ARCH_ZYNQ + default y select USB_EHCI_IS_TDI ---help--- Enable support for Zynq on-chip EHCI USB controller @@ -303,6 +305,7 @@ config EHCI_HCD_INIT_AFTER_RESET config USB_EHCI_FSL bool "Support for FSL on-chip EHCI USB controller" + depends on PPC select EHCI_HCD_INIT_AFTER_RESET select SYS_FSL_USB_INTERNAL_UTMI_PHY if MPC85xx && \ !(ARCH_B4860 || ARCH_B4420 || ARCH_P4080 || ARCH_P1020 || ARCH_P2020) @@ -362,6 +365,7 @@ config USB_OHCI_GENERIC config USB_OHCI_DA8XX bool "Support for da850 OHCI USB controller" + depends on ARCH_DAVINCI help Enable support for the da850 USB controller. -- cgit v1.2.3 From 3285584429ba09df602011784f40e2c2d59a26b9 Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Thu, 11 Sep 2025 15:50:23 -0600 Subject: usb: host: Tighten USB musb-new host glue driver dependencies A few of the USB musb-new host glue drivers cannot build without access to some platform specific header files. Express those requirements in Kconfig as well. Reviewed-by: Marek Vasut Signed-off-by: Tom Rini --- drivers/usb/musb-new/Kconfig | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/usb/musb-new/Kconfig b/drivers/usb/musb-new/Kconfig index ad9072a5327..0e2b2b5fb85 100644 --- a/drivers/usb/musb-new/Kconfig +++ b/drivers/usb/musb-new/Kconfig @@ -52,9 +52,11 @@ config USB_MUSB_OMAP2PLUS config USB_MUSB_AM35X bool "AM35x" + depends on ARCH_OMAP2PLUS config USB_MUSB_DSPS bool "TI DSPS platforms" + depends on ARCH_OMAP2PLUS config USB_MUSB_MT85XX bool "Enable Mediatek MT85XX DRC USB controller" -- cgit v1.2.3 From a87b9283266344ac31ef76a3a3ccf2da65429818 Mon Sep 17 00:00:00 2001 From: Ye Li Date: Tue, 23 Sep 2025 10:14:53 +0800 Subject: imx9: Add i.MX94 CPU type and SoC-level Kconfig Introduce support for the new i.MX94 processor, including its CPU type and SoC-level Kconfig entry. The i.MX94 is a new member of the i.MX9 family. It uses a System Manager to handle system-level functions such as power, clock, sensor and pin control. The System Manager runs on a Cortex-M processor, while the Cortex-A processor communicates with it via the ARM SCMI protocol and a messaging unit. Signed-off-by: Ye Li Signed-off-by: Alice Guo Acked-by: Peng Fan Reviewed-by: Jacky Bai --- arch/arm/include/asm/arch-imx/cpu.h | 2 ++ arch/arm/include/asm/mach-imx/sys_proto.h | 1 + arch/arm/mach-imx/imx9/Kconfig | 9 +++++++++ 3 files changed, 12 insertions(+) diff --git a/arch/arm/include/asm/arch-imx/cpu.h b/arch/arm/include/asm/arch-imx/cpu.h index 1f669c72d00..1af9778f8ce 100644 --- a/arch/arm/include/asm/arch-imx/cpu.h +++ b/arch/arm/include/asm/arch-imx/cpu.h @@ -78,6 +78,8 @@ #define MXC_CPU_IMX95 0x1C1 /* dummy ID */ +#define MXC_CPU_IMX94 0x1C2 /* dummy ID */ + #define MXC_SOC_MX6 0x60 #define MXC_SOC_MX7 0x70 #define MXC_SOC_IMX8M 0x80 diff --git a/arch/arm/include/asm/mach-imx/sys_proto.h b/arch/arm/include/asm/mach-imx/sys_proto.h index 0780f99b49a..46da7a1eff5 100644 --- a/arch/arm/include/asm/mach-imx/sys_proto.h +++ b/arch/arm/include/asm/mach-imx/sys_proto.h @@ -97,6 +97,7 @@ struct bd_info; #define is_imx9302() (is_cpu_type(MXC_CPU_IMX9302)) #define is_imx9301() (is_cpu_type(MXC_CPU_IMX9301)) +#define is_imx94() (is_cpu_type(MXC_CPU_IMX94)) #define is_imx95() (is_cpu_type(MXC_CPU_IMX95)) #define is_imx9121() (is_cpu_type(MXC_CPU_IMX9121)) diff --git a/arch/arm/mach-imx/imx9/Kconfig b/arch/arm/mach-imx/imx9/Kconfig index b6acbb20ff0..f2011448c23 100644 --- a/arch/arm/mach-imx/imx9/Kconfig +++ b/arch/arm/mach-imx/imx9/Kconfig @@ -38,6 +38,15 @@ config IMX95 select SPL_IMX_CONTAINER_USE_TRAMPOLINE select IMX_PQC_SUPPORT if !IMX95_A0 +config IMX94 + bool + select ARMV8_SPL_EXCEPTION_VECTORS + select DM_MAILBOX + select IMX9 + select IMX_PQC_SUPPORT + select SCMI_FIRMWARE + select SPL_IMX_CONTAINER_USE_TRAMPOLINE + config SYS_SOC default "imx9" -- cgit v1.2.3 From a2d62d3b1d357dccc2e9ed56a4e7bdbb030ca06f Mon Sep 17 00:00:00 2001 From: Alice Guo Date: Tue, 23 Sep 2025 10:14:54 +0800 Subject: cpu: imx94: Add support for i.MX94 in get_imx_type_str() Add a case for i.MX94 to return the correct string identifier in the get_imx_type_str() function. This ensures proper CPU type reporting for i.MX94 platforms. Signed-off-by: Alice Guo --- drivers/cpu/imx8_cpu.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/cpu/imx8_cpu.c b/drivers/cpu/imx8_cpu.c index 950630453f9..630919a3642 100644 --- a/drivers/cpu/imx8_cpu.c +++ b/drivers/cpu/imx8_cpu.c @@ -113,6 +113,8 @@ static const char *get_imx_type_str(u32 imxtype) return "91(01)";/* iMX91 9x9 Specific feature */ case MXC_CPU_IMX95: return "95"; + case MXC_CPU_IMX94: + return "94"; default: return "??"; } -- cgit v1.2.3 From 998c6cc450e61152b6d0e800989d2d19358e25c2 Mon Sep 17 00:00:00 2001 From: Peng Fan Date: Tue, 23 Sep 2025 10:14:55 +0800 Subject: imx95: Add get_reset_reason() to retrieve the LM/system last booted/shutdown reasons System Manager provides the last booted and shutdown reasons of the logical machines (LM) and system using the SCMI misc protocol (Protocol ID: 0x84, Message ID: 0xA). This path adds get_reset_reason() to query and print these reasons in SPL and U-Boot. Signed-off-by: Peng Fan Signed-off-by: Alice Guo Reviewed-by: Ye Li --- arch/arm/include/asm/arch-imx9/sys_proto.h | 1 + arch/arm/mach-imx/imx9/scmi/soc.c | 110 +++++++++++++++++++++++++++++ board/freescale/imx95_evk/spl.c | 3 + include/scmi_nxp_protocols.h | 55 +++++++++++++++ 4 files changed, 169 insertions(+) create mode 100644 include/scmi_nxp_protocols.h diff --git a/arch/arm/include/asm/arch-imx9/sys_proto.h b/arch/arm/include/asm/arch-imx9/sys_proto.h index 455aa95339e..dead7a99a66 100644 --- a/arch/arm/include/asm/arch-imx9/sys_proto.h +++ b/arch/arm/include/asm/arch-imx9/sys_proto.h @@ -21,6 +21,7 @@ int m33_prepare(void); int low_drive_freq_update(void *blob); enum imx9_soc_voltage_mode soc_target_voltage_mode(void); +int get_reset_reason(bool sys, bool lm); #define is_voltage_mode(mode) (soc_target_voltage_mode() == (mode)) diff --git a/arch/arm/mach-imx/imx9/scmi/soc.c b/arch/arm/mach-imx/imx9/scmi/soc.c index f973652d0cb..f04b9255cdb 100644 --- a/arch/arm/mach-imx/imx9/scmi/soc.c +++ b/arch/arm/mach-imx/imx9/scmi/soc.c @@ -17,8 +17,10 @@ #include #include #include +#include #include #include +#include DECLARE_GLOBAL_DATA_PTR; @@ -468,6 +470,114 @@ err: printf("%s: fuse read err: %d\n", __func__, ret); } +static char *rst_string[32] = { + "cm33_lockup", + "cm33_swreq", + "cm7_lockup", + "cm7_swreq", + "fccu", + "jtag_sw", + "ele", + "tempsense", + "wdog1", + "wdog2", + "wdog3", + "wdog4", + "wdog5", + "jtag", + "cm33_exc", + "bbm", + "sw", + "sm_err", "fusa_sreco", "pmic", "unused", "unused", "unused", + "unused", "unused", "unused", "unused", "unused", "unused", + "unused", "unused", + "por" +}; + +int get_reset_reason(bool sys, bool lm) +{ + struct scmi_imx_misc_reset_reason_in in = { + .flags = MISC_REASON_FLAG_SYSTEM, + }; + + struct scmi_imx_misc_reset_reason_out out = { 0 }; + struct scmi_msg msg = { + .protocol_id = SCMI_PROTOCOL_ID_IMX_MISC, + .message_id = SCMI_IMX_MISC_RESET_REASON, + .in_msg = (u8 *)&in, + .in_msg_sz = sizeof(in), + .out_msg = (u8 *)&out, + .out_msg_sz = sizeof(out), + }; + int ret; + + struct udevice *dev; + + ret = uclass_get_device_by_name(UCLASS_CLK, "protocol@14", &dev); + if (ret) + return ret; + + if (sys) { + ret = devm_scmi_process_msg(dev, &msg); + if (out.status) { + printf("%s:%d for SYS\n", __func__, out.status); + return ret; + } + + if (out.bootflags & MISC_BOOT_FLAG_VLD) { + printf("SYS Boot reason: %s, origin: %ld, errid: %ld\n", + rst_string[out.bootflags & MISC_BOOT_FLAG_REASON], + out.bootflags & MISC_BOOT_FLAG_ORG_VLD ? + FIELD_GET(MISC_BOOT_FLAG_ORIGIN, out.bootflags) : -1, + out.bootflags & MISC_BOOT_FLAG_ERR_VLD ? + FIELD_GET(MISC_BOOT_FLAG_ERR_ID, out.bootflags) : -1 + ); + } + if (out.shutdownflags & MISC_SHUTDOWN_FLAG_VLD) { + printf("SYS shutdown reason: %s, origin: %ld, errid: %ld\n", + rst_string[out.bootflags & MISC_SHUTDOWN_FLAG_REASON], + out.bootflags & MISC_SHUTDOWN_FLAG_ORG_VLD ? + FIELD_GET(MISC_SHUTDOWN_FLAG_ORIGIN, out.bootflags) : -1, + out.bootflags & MISC_SHUTDOWN_FLAG_ERR_VLD ? + FIELD_GET(MISC_SHUTDOWN_FLAG_ERR_ID, out.bootflags) : -1 + ); + } + } + + if (lm) { + in.flags = 0; + memset(&out, 0, sizeof(struct scmi_imx_misc_reset_reason_out)); + + ret = devm_scmi_process_msg(dev, &msg); + if (out.status) { + printf("%s:%d for LM\n", __func__, out.status); + return ret; + } + + if (out.bootflags & MISC_BOOT_FLAG_VLD) { + printf("LM Boot reason: %s, origin: %ld, errid: %ld\n", + rst_string[out.bootflags & MISC_BOOT_FLAG_REASON], + out.bootflags & MISC_BOOT_FLAG_ORG_VLD ? + FIELD_GET(MISC_BOOT_FLAG_ORIGIN, out.bootflags) : -1, + out.bootflags & MISC_BOOT_FLAG_ERR_VLD ? + FIELD_GET(MISC_BOOT_FLAG_ERR_ID, out.bootflags) : -1 + ); + } + + if (out.shutdownflags & MISC_SHUTDOWN_FLAG_VLD) { + printf("LM shutdown reason: %s, origin: %ld, errid: %ld\n", + rst_string[out.bootflags & MISC_SHUTDOWN_FLAG_REASON], + out.bootflags & MISC_SHUTDOWN_FLAG_ORG_VLD ? + FIELD_GET(MISC_SHUTDOWN_FLAG_ORIGIN, out.bootflags) : -1, + out.bootflags & MISC_SHUTDOWN_FLAG_ERR_VLD ? + FIELD_GET(MISC_SHUTDOWN_FLAG_ERR_ID, out.bootflags) : -1 + ); + } + } + + return 0; +} + const char *get_imx_type(u32 imxtype) { switch (imxtype) { diff --git a/board/freescale/imx95_evk/spl.c b/board/freescale/imx95_evk/spl.c index 08f4da0bb73..3d64097b4c7 100644 --- a/board/freescale/imx95_evk/spl.c +++ b/board/freescale/imx95_evk/spl.c @@ -5,6 +5,7 @@ #include #include +#include #include #include #include @@ -65,5 +66,7 @@ void board_init_f(ulong dummy) debug("SOC: 0x%x\n", gd->arch.soc_rev); debug("LC: 0x%x\n", gd->arch.lifecycle); + get_reset_reason(true, false); + board_init_r(NULL, 0); } diff --git a/include/scmi_nxp_protocols.h b/include/scmi_nxp_protocols.h new file mode 100644 index 00000000000..fe6ecd6a7cf --- /dev/null +++ b/include/scmi_nxp_protocols.h @@ -0,0 +1,55 @@ +/* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */ +/* + * Copyright 2025 NXP + */ + +#ifndef _SCMI_NXP_PROTOCOLS_H +#define _SCMI_NXP_PROTOCOLS_H + +#include +#include + +enum scmi_imx_protocol { + SCMI_IMX_PROTOCOL_ID_MISC = 0x84, +}; + +#define SCMI_PAYLOAD_LEN 100 + +#define SCMI_ARRAY(X, Y) ((SCMI_PAYLOAD_LEN - (X)) / sizeof(Y)) + +#define SCMI_IMX_MISC_RESET_REASON 0xA + +struct scmi_imx_misc_reset_reason_in { +#define MISC_REASON_FLAG_SYSTEM BIT(0) + u32 flags; +}; + +struct scmi_imx_misc_reset_reason_out { + s32 status; + /* Boot reason flags */ +#define MISC_BOOT_FLAG_VLD BIT(31) +#define MISC_BOOT_FLAG_ORG_VLD BIT(28) +#define MISC_BOOT_FLAG_ORIGIN GENMASK(27, 24) +#define MISC_BOOT_FLAG_O_SHIFT 24 +#define MISC_BOOT_FLAG_ERR_VLD BIT(23) +#define MISC_BOOT_FLAG_ERR_ID GENMASK(22, 8) +#define MISC_BOOT_FLAG_E_SHIFT 8 +#define MISC_BOOT_FLAG_REASON GENMASK(7, 0) + u32 bootflags; + /* Shutdown reason flags */ +#define MISC_SHUTDOWN_FLAG_VLD BIT(31) +#define MISC_SHUTDOWN_FLAG_EXT_LEN GENMASK(30, 29) +#define MISC_SHUTDOWN_FLAG_ORG_VLD BIT(28) +#define MISC_SHUTDOWN_FLAG_ORIGIN GENMASK(27, 24) +#define MISC_SHUTDOWN_FLAG_O_SHIFT 24 +#define MISC_SHUTDOWN_FLAG_ERR_VLD BIT(23) +#define MISC_SHUTDOWN_FLAG_ERR_ID GENMASK(22, 8) +#define MISC_SHUTDOWN_FLAG_E_SHIFT 8 +#define MISC_SHUTDOWN_FLAG_REASON GENMASK(7, 0) + u32 shutdownflags; + /* Array of extended info words */ +#define MISC_MAX_EXTINFO SCMI_ARRAY(16, u32) + u32 extInfo[MISC_MAX_EXTINFO]; +}; + +#endif -- cgit v1.2.3 From 1588c243b972eee7086cfbb98e04fc680f7fae13 Mon Sep 17 00:00:00 2001 From: Ye Li Date: Tue, 23 Sep 2025 10:14:56 +0800 Subject: imx9: scmi: Add i.MX94 support to get_reset_reason() Update get_reset_reason() to support i.MX94 to send message to the System Manager to retrieve the LM/system last booted/shutdown reasons. Signed-off-by: Ye Li Signed-off-by: Alice Guo Reviewed-by: Peng Fan --- arch/arm/mach-imx/imx9/scmi/soc.c | 39 +++++++++++++++++++++++++++++++++++---- 1 file changed, 35 insertions(+), 4 deletions(-) diff --git a/arch/arm/mach-imx/imx9/scmi/soc.c b/arch/arm/mach-imx/imx9/scmi/soc.c index f04b9255cdb..07022c65b88 100644 --- a/arch/arm/mach-imx/imx9/scmi/soc.c +++ b/arch/arm/mach-imx/imx9/scmi/soc.c @@ -494,6 +494,31 @@ static char *rst_string[32] = { "por" }; +static char *rst_string_imx94[32] = { + "cm33_lockup", + "cm33_swreq", + "cm70_lockup", + "cm70_swreq", + "fccu", + "jtag_sw", + "ele", + "tempsense", + "wdog1", + "wdog2", + "wdog3", + "wdog4", + "wdog5", + "jtag", + "wdog6", + "wdog7", + "wdog8", + "wo_netc", "cm33s_lockup", "cm33s_swreq", "cm71_lockup", "cm71_swreq", "cm33_exc", + "bbm", "sw", "sm_err", "fusa_sreco", "pmic", "unused", + "unused", "unused", + "por" +}; + + int get_reset_reason(bool sys, bool lm) { struct scmi_imx_misc_reset_reason_in in = { @@ -512,6 +537,12 @@ int get_reset_reason(bool sys, bool lm) int ret; struct udevice *dev; + char **rst; + + if (is_imx94()) + rst = rst_string_imx94; + else + rst = rst_string; ret = uclass_get_device_by_name(UCLASS_CLK, "protocol@14", &dev); if (ret) @@ -526,7 +557,7 @@ int get_reset_reason(bool sys, bool lm) if (out.bootflags & MISC_BOOT_FLAG_VLD) { printf("SYS Boot reason: %s, origin: %ld, errid: %ld\n", - rst_string[out.bootflags & MISC_BOOT_FLAG_REASON], + rst[out.bootflags & MISC_BOOT_FLAG_REASON], out.bootflags & MISC_BOOT_FLAG_ORG_VLD ? FIELD_GET(MISC_BOOT_FLAG_ORIGIN, out.bootflags) : -1, out.bootflags & MISC_BOOT_FLAG_ERR_VLD ? @@ -535,7 +566,7 @@ int get_reset_reason(bool sys, bool lm) } if (out.shutdownflags & MISC_SHUTDOWN_FLAG_VLD) { printf("SYS shutdown reason: %s, origin: %ld, errid: %ld\n", - rst_string[out.bootflags & MISC_SHUTDOWN_FLAG_REASON], + rst[out.bootflags & MISC_SHUTDOWN_FLAG_REASON], out.bootflags & MISC_SHUTDOWN_FLAG_ORG_VLD ? FIELD_GET(MISC_SHUTDOWN_FLAG_ORIGIN, out.bootflags) : -1, out.bootflags & MISC_SHUTDOWN_FLAG_ERR_VLD ? @@ -556,7 +587,7 @@ int get_reset_reason(bool sys, bool lm) if (out.bootflags & MISC_BOOT_FLAG_VLD) { printf("LM Boot reason: %s, origin: %ld, errid: %ld\n", - rst_string[out.bootflags & MISC_BOOT_FLAG_REASON], + rst[out.bootflags & MISC_BOOT_FLAG_REASON], out.bootflags & MISC_BOOT_FLAG_ORG_VLD ? FIELD_GET(MISC_BOOT_FLAG_ORIGIN, out.bootflags) : -1, out.bootflags & MISC_BOOT_FLAG_ERR_VLD ? @@ -566,7 +597,7 @@ int get_reset_reason(bool sys, bool lm) if (out.shutdownflags & MISC_SHUTDOWN_FLAG_VLD) { printf("LM shutdown reason: %s, origin: %ld, errid: %ld\n", - rst_string[out.bootflags & MISC_SHUTDOWN_FLAG_REASON], + rst[out.bootflags & MISC_SHUTDOWN_FLAG_REASON], out.bootflags & MISC_SHUTDOWN_FLAG_ORG_VLD ? FIELD_GET(MISC_SHUTDOWN_FLAG_ORIGIN, out.bootflags) : -1, out.bootflags & MISC_SHUTDOWN_FLAG_ERR_VLD ? -- cgit v1.2.3 From f9c4fd387179187dd81a34f6f78df448f1e8cbfa Mon Sep 17 00:00:00 2001 From: Ye Li Date: Tue, 23 Sep 2025 10:14:57 +0800 Subject: imx9: scmi: Update the files under arch/arm/mach-imx/imx9/scmi/ to support i.MX94 - Add base addresses for WDG3, WDG4, GPIO6, and GPIO7 for i.MX94. - Introduce common.h with macros of clock IDs, power domains, and CPU types for platform-specific replacement (e.g., i.MX94, i.MX95). - Extend imx_get_mac_from_fuse() to support i.MX94. Signed-off-by: Ye Li Signed-off-by: Alice Guo Acked-by: Peng Fan Reviewed-by: Jacky Bai --- arch/arm/include/asm/arch-imx9/imx-regs.h | 9 ++++++ arch/arm/mach-imx/imx9/scmi/Makefile | 3 ++ arch/arm/mach-imx/imx9/scmi/clock.c | 29 +++++++++--------- arch/arm/mach-imx/imx9/scmi/common.h | 41 +++++++++++++++++++++++++ arch/arm/mach-imx/imx9/scmi/soc.c | 50 ++++++++++++++++++++++++------- 5 files changed, 108 insertions(+), 24 deletions(-) create mode 100644 arch/arm/mach-imx/imx9/scmi/common.h diff --git a/arch/arm/include/asm/arch-imx9/imx-regs.h b/arch/arm/include/asm/arch-imx9/imx-regs.h index 5127fe8f286..a44fa6663c3 100644 --- a/arch/arm/include/asm/arch-imx9/imx-regs.h +++ b/arch/arm/include/asm/arch-imx9/imx-regs.h @@ -17,14 +17,23 @@ #define ANATOP_BASE_ADDR 0x44480000UL +#ifdef CONFIG_IMX94 +#define WDG3_BASE_ADDR 0x49220000UL +#define WDG4_BASE_ADDR 0x49230000UL +#else #define WDG3_BASE_ADDR 0x42490000UL #define WDG4_BASE_ADDR 0x424a0000UL +#endif #define WDG5_BASE_ADDR 0x424b0000UL #define GPIO2_BASE_ADDR 0x43810000UL #define GPIO3_BASE_ADDR 0x43820000UL #define GPIO4_BASE_ADDR 0x43840000UL #define GPIO5_BASE_ADDR 0x43850000UL +#ifdef CONFIG_IMX94 +#define GPIO6_BASE_ADDR 0x43860000UL +#define GPIO7_BASE_ADDR 0x43870000UL +#endif #define FSB_BASE_ADDR 0x47510000UL diff --git a/arch/arm/mach-imx/imx9/scmi/Makefile b/arch/arm/mach-imx/imx9/scmi/Makefile index 4534db08d28..b98744e1ecb 100644 --- a/arch/arm/mach-imx/imx9/scmi/Makefile +++ b/arch/arm/mach-imx/imx9/scmi/Makefile @@ -2,5 +2,8 @@ # # Copyright 2025 NXP +# Add include path for NXP device tree header files from Linux. +ccflags-y += -I$(srctree)/dts/upstream/src/arm64/freescale/ + obj-y += soc.o obj-y += clock_scmi.o clock.o diff --git a/arch/arm/mach-imx/imx9/scmi/clock.c b/arch/arm/mach-imx/imx9/scmi/clock.c index 6e6541eaa31..951d47bd9d7 100644 --- a/arch/arm/mach-imx/imx9/scmi/clock.c +++ b/arch/arm/mach-imx/imx9/scmi/clock.c @@ -6,16 +6,17 @@ #include #include #include -#include "../../../../../dts/upstream/src/arm64/freescale/imx95-clock.h" +#include +#include "common.h" u32 get_arm_core_clk(void) { u32 val; - val = imx_clk_scmi_get_rate(IMX95_CLK_SEL_A55C0); + val = imx_clk_scmi_get_rate(SCMI_CLK(SEL_A55C0)); if (val) return val; - return imx_clk_scmi_get_rate(IMX95_CLK_A55); + return imx_clk_scmi_get_rate(SCMI_CLK(A55)); } void init_uart_clk(u32 index) @@ -24,13 +25,13 @@ void init_uart_clk(u32 index) switch (index) { case 0: - clock_id = IMX95_CLK_LPUART1; + clock_id = SCMI_CLK(LPUART1); break; case 1: - clock_id = IMX95_CLK_LPUART2; + clock_id = SCMI_CLK(LPUART2); break; case 2: - clock_id = IMX95_CLK_LPUART3; + clock_id = SCMI_CLK(LPUART3); break; default: return; @@ -38,7 +39,7 @@ void init_uart_clk(u32 index) /* 24MHz */ imx_clk_scmi_enable(clock_id, false); - imx_clk_scmi_set_parent(clock_id, IMX95_CLK_24M); + imx_clk_scmi_set_parent(clock_id, SCMI_CLK(24M)); imx_clk_scmi_set_rate(clock_id, 24000000); imx_clk_scmi_enable(clock_id, true); } @@ -49,19 +50,19 @@ unsigned int mxc_get_clock(enum mxc_clock clk) case MXC_ARM_CLK: return get_arm_core_clk(); case MXC_IPG_CLK: - return imx_clk_scmi_get_rate(IMX95_CLK_BUSWAKEUP); + return imx_clk_scmi_get_rate(SCMI_CLK(BUSWAKEUP)); case MXC_CSPI_CLK: - return imx_clk_scmi_get_rate(IMX95_CLK_LPSPI1); + return imx_clk_scmi_get_rate(SCMI_CLK(LPSPI1)); case MXC_ESDHC_CLK: - return imx_clk_scmi_get_rate(IMX95_CLK_USDHC1); + return imx_clk_scmi_get_rate(SCMI_CLK(USDHC1)); case MXC_ESDHC2_CLK: - return imx_clk_scmi_get_rate(IMX95_CLK_USDHC2); + return imx_clk_scmi_get_rate(SCMI_CLK(USDHC2)); case MXC_ESDHC3_CLK: - return imx_clk_scmi_get_rate(IMX95_CLK_USDHC3); + return imx_clk_scmi_get_rate(SCMI_CLK(USDHC3)); case MXC_UART_CLK: - return imx_clk_scmi_get_rate(IMX95_CLK_LPUART1); + return imx_clk_scmi_get_rate(SCMI_CLK(LPUART1)); case MXC_FLEXSPI_CLK: - return imx_clk_scmi_get_rate(IMX95_CLK_FLEXSPI1); + return imx_clk_scmi_get_rate(SCMI_CLK(FLEXSPI1)); default: return -1; }; diff --git a/arch/arm/mach-imx/imx9/scmi/common.h b/arch/arm/mach-imx/imx9/scmi/common.h new file mode 100644 index 00000000000..dd4675402c7 --- /dev/null +++ b/arch/arm/mach-imx/imx9/scmi/common.h @@ -0,0 +1,41 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2025 NXP + */ + +#ifndef _SCMI_CLOCK_COMMON_H_ +#define _SCMI_CLOCK_COMMON_H_ + +#ifdef CONFIG_IMX94 +#define IMX_PLAT 94 +#include +#include + +#define IMX94_CLK_FLEXSPI1 IMX94_CLK_XSPI1 +#endif + +#ifdef CONFIG_IMX95 +#define IMX_PLAT 95 +#include +#include + +#define IMX95_PD_M70 IMX95_PD_M7 +#endif + +#define IMX_PLAT_STR__(plat) # plat +#define IMX_PLAT_STR_(IMX_PLAT) IMX_PLAT_STR__(IMX_PLAT) +#define IMX_PLAT_STR IMX_PLAT_STR_(IMX_PLAT) + +#define SCMI_CLK__(plat, clk) IMX ## plat ## _CLK_ ## clk +#define SCMI_CLK_(plat, clk) SCMI_CLK__(plat, clk) +#define SCMI_CLK(clk) SCMI_CLK_(IMX_PLAT, clk) + +#define SCMI_PD__(plat, pd) IMX ## plat ## _PD_ ## pd +#define SCMI_PD_(plat, pd) SCMI_PD__(plat, pd) +#define SCMI_PD(pd) SCMI_PD_(IMX_PLAT, pd) + +#define SCMI_CPU__(plat) MXC_CPU_IMX ## plat +#define SCMI_CPU_(plat) SCMI_CPU__(plat) +#define SCMI_CPU SCMI_CPU_(IMX_PLAT) + +#endif diff --git a/arch/arm/mach-imx/imx9/scmi/soc.c b/arch/arm/mach-imx/imx9/scmi/soc.c index 07022c65b88..5c1e13c9842 100644 --- a/arch/arm/mach-imx/imx9/scmi/soc.c +++ b/arch/arm/mach-imx/imx9/scmi/soc.c @@ -21,6 +21,7 @@ #include #include #include +#include "common.h" DECLARE_GLOBAL_DATA_PTR; @@ -176,7 +177,7 @@ u32 get_cpu_rev(void) { u32 rev = (gd->arch.soc_rev >> 24) - 0xa0; - return (MXC_CPU_IMX95 << 12) | (CHIP_REV_1_0 + rev); + return (SCMI_CPU << 12) | (CHIP_REV_1_0 + rev); } #define UNLOCK_WORD 0xD928C520 @@ -437,12 +438,16 @@ void imx_get_mac_from_fuse(int dev_id, unsigned char *mac) { u32 val[2] = {}; int ret, num_of_macs; + u32 bank = 40; - ret = fuse_read(40, 5, &val[0]); + if (is_imx94()) + bank = 66; + + ret = fuse_read(bank, 5, &val[0]); if (ret) goto err; - ret = fuse_read(40, 6, &val[1]); + ret = fuse_read(bank, 6, &val[1]); if (ret) goto err; @@ -458,10 +463,32 @@ void imx_get_mac_from_fuse(int dev_id, unsigned char *mac) mac[3] = (val[0] >> 24) & 0xff; mac[4] = val[1] & 0xff; mac[5] = (val[1] >> 8) & 0xff; - if (dev_id == 1) - mac[5] = mac[5] + 3; - if (dev_id == 2) - mac[5] = mac[5] + 6; + + if (is_imx94()) { + /* + * i.MX94 uses the following mac address offset list: + * | No. | Module | Mac address user | + * |--------|-------------|---------------------------| + * | 0 ~ 1 | ethercat | port0/port1 | + * | 2 | netc switch | internal enetc3 mac/swp0 | + * | 3 ~ 6 | | enetc3 vf1~3/swp1 | + * | 7 | enetc mac | enetc0 pf | + * | 8 | | enetc1 pf | + * | 9 | | enetc2 pf | + * | 10 | netc switch | swp2 | + */ + if (dev_id == 0) + mac[5] = mac[5] + 2; /* enetc3 mac/swp0 */ + if (dev_id == 1) + mac[5] = mac[5] + 8; /* enetc1 */ + if (dev_id == 2) + mac[5] = mac[5] + 9; /* enetc2 */ + } else { + if (dev_id == 1) + mac[5] = mac[5] + 3; + if (dev_id == 2) + mac[5] = mac[5] + 6; + } debug("%s: MAC%d: %pM\n", __func__, dev_id, mac); return; @@ -518,7 +545,6 @@ static char *rst_string_imx94[32] = { "por" }; - int get_reset_reason(bool sys, bool lm) { struct scmi_imx_misc_reset_reason_in in = { @@ -612,8 +638,8 @@ int get_reset_reason(bool sys, bool lm) const char *get_imx_type(u32 imxtype) { switch (imxtype) { - case MXC_CPU_IMX95: - return "95";/* iMX95 FULL */ + case SCMI_CPU: + return IMX_PLAT_STR; default: return "??"; } @@ -694,6 +720,10 @@ int arch_cpu_init(void) gpio_reset(GPIO3_BASE_ADDR); gpio_reset(GPIO4_BASE_ADDR); gpio_reset(GPIO5_BASE_ADDR); +#ifdef CONFIG_IMX94 + gpio_reset(GPIO6_BASE_ADDR); + gpio_reset(GPIO7_BASE_ADDR); +#endif } return 0; -- cgit v1.2.3 From 6fc3934db567c3f78f1a3ff29644f3d5285d0e80 Mon Sep 17 00:00:00 2001 From: Ye Li Date: Tue, 23 Sep 2025 10:14:58 +0800 Subject: imx: container: Add i.MX94 support to get_imageset_end() Extend get_imageset_end() to handle i.MX94 family. Signed-off-by: Ye Li Signed-off-by: Jacky Bai Signed-off-by: Alice Guo Acked-by: Peng Fan --- arch/arm/mach-imx/image-container.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm/mach-imx/image-container.c b/arch/arm/mach-imx/image-container.c index 3a9e6dcf225..78f2488cf6d 100644 --- a/arch/arm/mach-imx/image-container.c +++ b/arch/arm/mach-imx/image-container.c @@ -297,7 +297,7 @@ static ulong get_imageset_end(void *dev, int dev_type) debug("seco container size 0x%x\n", value_container[0]); - if (is_imx95()) { + if (is_imx95() || is_imx94()) { offset[1] = ALIGN(hdr_length, CONTAINER_HDR_ALIGNMENT) + offset[0]; value_container[1] = get_dev_container_size(dev, dev_type, offset[1], &hdr_length, &v2x_fw); @@ -321,7 +321,7 @@ static ulong get_imageset_end(void *dev, int dev_type) value_container[2] = get_dev_container_size(dev, dev_type, offset[2], &hdr_length, NULL); if (value_container[2] < 0) { debug("Parse scu container image failed %d, only seco container\n", value_container[2]); - if (is_imx95()) + if (is_imx95() || is_imx94()) return value_container[1] + offset[1]; /* return seco + v2x container total size */ else return value_container[0] + offset[0]; /* return seco container total size */ -- cgit v1.2.3 From 3661d4dc6d81bcf27887c553f400fd4bcdeb2ad2 Mon Sep 17 00:00:00 2001 From: Alice Guo Date: Tue, 23 Sep 2025 10:14:59 +0800 Subject: pinctrl: nxp: Add i.MX94 daisy register offset Define the daisy register offset for i.MX94 at 0x608 within the iomuxc register space. This enables correct pad selection for daisy chain configuration on i.MX94 platforms. Signed-off-by: Jacky Bai Signed-off-by: Alice Guo Acked-by: Peng Fan --- drivers/pinctrl/nxp/pinctrl-imx-scmi.c | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/drivers/pinctrl/nxp/pinctrl-imx-scmi.c b/drivers/pinctrl/nxp/pinctrl-imx-scmi.c index aed47be337d..781835c6852 100644 --- a/drivers/pinctrl/nxp/pinctrl-imx-scmi.c +++ b/drivers/pinctrl/nxp/pinctrl-imx-scmi.c @@ -16,6 +16,7 @@ #include "pinctrl-imx.h" #define DAISY_OFFSET_IMX95 0x408 +#define DAISY_OFFSET_IMX94 0x608 /* SCMI pin control types */ #define PINCTRL_TYPE_MUX 192 @@ -133,6 +134,8 @@ static int imx_scmi_pinctrl_probe(struct udevice *dev) if (IS_ENABLED(CONFIG_IMX95)) priv->daisy_offset = DAISY_OFFSET_IMX95; + else if (IS_ENABLED(CONFIG_IMX94)) + priv->daisy_offset = DAISY_OFFSET_IMX94; else return -EINVAL; @@ -141,7 +144,7 @@ static int imx_scmi_pinctrl_probe(struct udevice *dev) static int imx_scmi_pinctrl_bind(struct udevice *dev) { - if (IS_ENABLED(CONFIG_IMX95)) + if (IS_ENABLED(CONFIG_IMX95) || IS_ENABLED(CONFIG_IMX94)) return 0; return -ENODEV; -- cgit v1.2.3 From 54e4b1c36bc8ca85fd35dae917dcb34cf1fce057 Mon Sep 17 00:00:00 2001 From: Ye Li Date: Tue, 23 Sep 2025 10:15:00 +0800 Subject: imx9: Change container header temp buffer address Due to i.MX95 has reserved first 256MB DDR, change to use the DDR start address in u-boot as the container header buffer. Signed-off-by: Ye Li Signed-off-by: Alice Guo Reviewed-by: Peng Fan --- arch/arm/include/asm/arch-imx9/imx-regs.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/include/asm/arch-imx9/imx-regs.h b/arch/arm/include/asm/arch-imx9/imx-regs.h index a44fa6663c3..e641ed299c0 100644 --- a/arch/arm/include/asm/arch-imx9/imx-regs.h +++ b/arch/arm/include/asm/arch-imx9/imx-regs.h @@ -57,7 +57,7 @@ #define SRC_MIX_SLICE_FUNC_STAT_SSAR_STAT BIT(8) #define SRC_MIX_SLICE_FUNC_STAT_MEM_STAT BIT(12) -#define IMG_CONTAINER_BASE (0x80000000UL) +#define IMG_CONTAINER_BASE CFG_SYS_SDRAM_BASE #define BCTRL_GPR_ENET_QOS_INTF_MODE_MASK GENMASK(3, 1) #define BCTRL_GPR_ENET_QOS_INTF_SEL_MII (0x0 << 1) -- cgit v1.2.3 From 226a606c10de005d6fbffa07531ef2817ff6e933 Mon Sep 17 00:00:00 2001 From: Ye Li Date: Tue, 23 Sep 2025 10:15:01 +0800 Subject: imx: ele_ahab: Implement display_life_cycle() for i.MX95 The register reflects lifecycle and some lifecycle-derived state of i.MX95 has new offset address and layout, so display_life_cycle() is added specifically for it. Signed-off-by: Ye Li Signed-off-by: Alice Guo Reviewed-by: Peng Fan --- arch/arm/mach-imx/ele_ahab.c | 55 +++++++++++++++++++++++++++++++++++++++++--- 1 file changed, 52 insertions(+), 3 deletions(-) diff --git a/arch/arm/mach-imx/ele_ahab.c b/arch/arm/mach-imx/ele_ahab.c index 647daeb6562..39aba65d29e 100644 --- a/arch/arm/mach-imx/ele_ahab.c +++ b/arch/arm/mach-imx/ele_ahab.c @@ -411,6 +411,54 @@ static int do_authenticate(struct cmd_tbl *cmdtp, int flag, int argc, return CMD_RET_SUCCESS; } +#if IS_ENABLED(CONFIG_IMX95) +#define FSB_LC_OFFSET 0x414 +#define LC_OEM_OPEN 0x10 +static void display_life_cycle(u32 lc) +{ + printf("Lifecycle: 0x%08X, ", lc); + switch (lc) { + case 0x1: + printf("BLANK\n\n"); + break; + case 0x2: + printf("FAB Default\n\n"); + break; + case 0x4: + printf("FAB\n\n"); + break; + case 0x8: + printf("NXP Provisioned\n\n"); + break; + case 0x10: + printf("OEM Open\n\n"); + break; + case 0x20: + printf("OEM secure world closed\n\n"); + break; + case 0x40: + printf("OEM closed\n\n"); + break; + case 0x80: + printf("OEM Locked\n\n"); + break; + case 0x100: + printf("Field Return OEM\n\n"); + break; + case 0x200: + printf("Field Return NXP\n\n"); + break; + case 0x400: + printf("BRICKED\n\n"); + break; + default: + printf("Unknown\n\n"); + break; + } +} +#else +#define FSB_LC_OFFSET 0x41c +#define LC_OEM_OPEN 0x8 static void display_life_cycle(u32 lc) { printf("Lifecycle: 0x%08X, ", lc); @@ -447,6 +495,7 @@ static void display_life_cycle(u32 lc) break; } } +#endif static int confirm_close(void) { @@ -474,10 +523,10 @@ static int do_ahab_close(struct cmd_tbl *cmdtp, int flag, int argc, if (!confirm_close()) return -EACCES; - lc = readl(FSB_BASE_ADDR + 0x41c); + lc = readl(FSB_BASE_ADDR + FSB_LC_OFFSET); lc &= 0x3ff; - if (lc != 0x8) { + if (lc != LC_OEM_OPEN) { puts("Current lifecycle is NOT OEM open, can't move to OEM closed\n"); display_life_cycle(lc); return -EPERM; @@ -540,7 +589,7 @@ static int do_ahab_status(struct cmd_tbl *cmdtp, int flag, int argc, char *const u32 cnt = AHAB_MAX_EVENTS; int ret; - lc = readl(FSB_BASE_ADDR + 0x41c); + lc = readl(FSB_BASE_ADDR + FSB_LC_OFFSET); lc &= 0x3ff; display_life_cycle(lc); -- cgit v1.2.3 From 8824aa432ca561eed81d053eedbc0cbea0664d80 Mon Sep 17 00:00:00 2001 From: Ye Li Date: Tue, 23 Sep 2025 10:15:02 +0800 Subject: imx: ele_ahab: Add i.MX94 support to display_life_cycle() Extend display_life_cycle() to support i.MX94. Signed-off-by: Ye Li Signed-off-by: Jacky Bai Signed-off-by: Alice Guo Acked-by: Peng Fan --- arch/arm/mach-imx/ele_ahab.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/mach-imx/ele_ahab.c b/arch/arm/mach-imx/ele_ahab.c index 39aba65d29e..38e671e3935 100644 --- a/arch/arm/mach-imx/ele_ahab.c +++ b/arch/arm/mach-imx/ele_ahab.c @@ -411,7 +411,7 @@ static int do_authenticate(struct cmd_tbl *cmdtp, int flag, int argc, return CMD_RET_SUCCESS; } -#if IS_ENABLED(CONFIG_IMX95) +#if IS_ENABLED(CONFIG_IMX95) || IS_ENABLED(CONFIG_IMX94) #define FSB_LC_OFFSET 0x414 #define LC_OEM_OPEN 0x10 static void display_life_cycle(u32 lc) -- cgit v1.2.3 From 88c5ed4aa00d222f353ae7b0efd2554a8f060a70 Mon Sep 17 00:00:00 2001 From: Ye Li Date: Tue, 23 Sep 2025 10:15:03 +0800 Subject: arm: dts: Add i.MX943 EVK board dtsi files Introduce the base dtsi files for the i.MX943 EVK board. These files define the essential components such as messaging units, uSDHC, GPIOs and lpuart for board bring-up. Signed-off-by: Ye Li Signed-off-by: Alice Guo Acked-by: Peng Fan Reviewed-by: Jacky Bai --- arch/arm/dts/imx943-evk-u-boot.dtsi | 62 +++++++++++ arch/arm/dts/imx943-u-boot.dtsi | 212 ++++++++++++++++++++++++++++++++++++ 2 files changed, 274 insertions(+) create mode 100644 arch/arm/dts/imx943-evk-u-boot.dtsi create mode 100644 arch/arm/dts/imx943-u-boot.dtsi diff --git a/arch/arm/dts/imx943-evk-u-boot.dtsi b/arch/arm/dts/imx943-evk-u-boot.dtsi new file mode 100644 index 00000000000..5496385dc4d --- /dev/null +++ b/arch/arm/dts/imx943-evk-u-boot.dtsi @@ -0,0 +1,62 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2025 NXP + */ + +#include "imx943-u-boot.dtsi" + +&lpuart1 { + bootph-pre-ram; +}; + +®_usdhc2_vmmc { + bootph-pre-ram; +}; + +&usdhc1 { + bootph-pre-ram; +}; + +&usdhc2 { + bootph-pre-ram; +}; + +&wdog3 { + status = "disabled"; +}; + +&pinctrl_reg_usdhc2_vmmc { + bootph-pre-ram; +}; + +&pinctrl_uart1 { + bootph-pre-ram; +}; + +&pinctrl_usdhc1 { + bootph-pre-ram; +}; + +&pinctrl_usdhc1_100mhz { + bootph-pre-ram; +}; + +&pinctrl_usdhc1_200mhz { + bootph-pre-ram; +}; + +&pinctrl_usdhc2 { + bootph-pre-ram; +}; + +&pinctrl_usdhc2_100mhz { + bootph-pre-ram; +}; + +&pinctrl_usdhc2_200mhz { + bootph-pre-ram; +}; + +&pinctrl_usdhc2_gpio { + bootph-pre-ram; +}; diff --git a/arch/arm/dts/imx943-u-boot.dtsi b/arch/arm/dts/imx943-u-boot.dtsi new file mode 100644 index 00000000000..9c4882f7d79 --- /dev/null +++ b/arch/arm/dts/imx943-u-boot.dtsi @@ -0,0 +1,212 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2025 NXP + */ + +/ { + binman { + multiple-images; + + m33-oei-ddrfw { + pad-byte = <0x00>; + align-size = <0x8>; + filename = "m33-oei-ddrfw.bin"; + + oei-m33-ddr { + align-size = <0x4>; + filename = "oei-m33-ddr.bin"; + type = "blob-ext"; + }; + + imx-lpddr { + type = "nxp-header-ddrfw"; + + imx-lpddr-imem { + filename = "lpddr5_imem_v202409.bin"; + type = "blob-ext"; + }; + + imx-lpddr-dmem { + filename = "lpddr5_dmem_v202409.bin"; + type = "blob-ext"; + }; + }; + + imx-lpddr-qb { + type = "nxp-header-ddrfw"; + + imx-lpddr-imem-qb { + filename = "lpddr5_imem_qb_v202409.bin"; + type = "blob-ext"; + }; + + imx-lpddr-dmem-qb { + filename = "lpddr5_dmem_qb_v202409.bin"; + type = "blob-ext"; + }; + }; + }; + + imx-boot { + filename = "flash.bin"; + pad-byte = <0x00>; + + spl { + type = "nxp-imx9image"; + cfg-path = "spl/u-boot-spl.cfgout"; + args; + + cntr-version = <2>; + boot-from = "sd"; + soc-type = "IMX9"; + append = "mx943a0-ahab-container.img"; + container; + dummy-ddr; + image0 = "oei", "m33-oei-ddrfw.bin", "0x1ffc0000"; + hold = <0x10000>; + image1 = "m33", "m33_image.bin", "0x1ffc0000"; + image2 = "a55", "spl/u-boot-spl.bin", "0x20480000"; + dummy-v2x = <0x8b000000>; + }; + + u-boot { + type = "nxp-imx9image"; + cfg-path = "u-boot-container.cfgout"; + args; + + cntr-version = <2>; + boot-from = "sd"; + soc-type = "IMX9"; + container; + image0 = "a55", "bl31.bin", "0x8a200000"; + image1 = "a55", "u-boot.bin", "0x90200000"; + }; + }; + }; +}; + +&cpu0 { + clocks = <&scmi_clk IMX94_CLK_ARMPLL_PFD0>; + /delete-property/ power-domains; +}; + +&cpu1 { + clocks = <&scmi_clk IMX94_CLK_ARMPLL_PFD0>; + /delete-property/ power-domains; +}; + +&cpu2 { + clocks = <&scmi_clk IMX94_CLK_ARMPLL_PFD0>; + /delete-property/ power-domains; +}; + +&cpu3 { + clocks = <&scmi_clk IMX94_CLK_ARMPLL_PFD0>; + /delete-property/ power-domains; +}; + +&aips1 { + bootph-all; +}; + +&aips2 { + bootph-all; +}; + +&aips3 { + bootph-all; +}; + +&clk_ext1 { + bootph-all; +}; + +&dummy { + bootph-all; +}; + +&{/firmware} { + bootph-all; +}; + +&{/firmware/scmi} { + bootph-all; +}; + +&{/firmware/scmi/protocol@11} { + bootph-all; +}; + +&{/firmware/scmi/protocol@13} { + bootph-all; +}; + +&{/firmware/scmi/protocol@14} { + bootph-all; +}; + +&{/firmware/scmi/protocol@19} { + bootph-all; +}; + +&gpio2 { + bootph-pre-ram; +}; + +&gpio3 { + bootph-pre-ram; +}; + +&gpio4 { + bootph-pre-ram; +}; + +&gpio5 { + bootph-pre-ram; +}; + +&gpio6 { + bootph-pre-ram; +}; + +&gpio7 { + bootph-pre-ram; +}; + +&mu2 { + bootph-all; +}; + +&osc_24m { + bootph-all; +}; + +&scmi_buf0 { + bootph-all; +}; + +&scmi_buf1 { + bootph-all; +}; + +&{/soc} { + bootph-all; + + elemu1: mailbox@47530000 { + compatible = "fsl,imx93-mu-s4"; + reg = <0x0 0x47530000 0x0 0x10000>; + bootph-all; + status = "okay"; + }; + + elemu3: mailbox@47550000 { + compatible = "fsl,imx93-mu-s4"; + reg = <0x0 0x47550000 0x0 0x10000>; + bootph-all; + status = "okay"; + }; +}; + +&sram0 { + bootph-all; +}; -- cgit v1.2.3 From 3d4e14f4c903819b15ec7e83a29d175692557b3f Mon Sep 17 00:00:00 2001 From: Ye Li Date: Tue, 23 Sep 2025 10:15:04 +0800 Subject: imx94_evk: Add i.MX943 EVK board support Add board-level code and defconfig for the i.MX943 EVK board, supporting multiple SOM variants: 19x19 LPDDR5, 19x19 LPDDR4 and 15x15 LPDDR4. Signed-off-by: Ye Li Signed-off-by: Alice Guo Acked-by: Peng Fan Reviewed-by: Jacky Bai --- arch/arm/mach-imx/Makefile | 2 +- arch/arm/mach-imx/imx9/Kconfig | 8 +++ board/freescale/imx94_evk/Kconfig | 12 ++++ board/freescale/imx94_evk/MAINTAINERS | 6 ++ board/freescale/imx94_evk/Makefile | 11 +++ board/freescale/imx94_evk/imx94_evk.c | 41 ++++++++++++ board/freescale/imx94_evk/imx94_evk.env | 100 +++++++++++++++++++++++++++ board/freescale/imx94_evk/spl.c | 81 ++++++++++++++++++++++ configs/imx943_evk_defconfig | 115 ++++++++++++++++++++++++++++++++ doc/board/nxp/imx943_evk.rst | 112 +++++++++++++++++++++++++++++++ doc/board/nxp/index.rst | 1 + include/configs/imx94_evk.h | 24 +++++++ 12 files changed, 512 insertions(+), 1 deletion(-) create mode 100644 board/freescale/imx94_evk/Kconfig create mode 100644 board/freescale/imx94_evk/MAINTAINERS create mode 100644 board/freescale/imx94_evk/Makefile create mode 100644 board/freescale/imx94_evk/imx94_evk.c create mode 100644 board/freescale/imx94_evk/imx94_evk.env create mode 100644 board/freescale/imx94_evk/spl.c create mode 100644 configs/imx943_evk_defconfig create mode 100644 doc/board/nxp/imx943_evk.rst create mode 100644 include/configs/imx94_evk.h diff --git a/arch/arm/mach-imx/Makefile b/arch/arm/mach-imx/Makefile index fa2cdaba144..1efe690e876 100644 --- a/arch/arm/mach-imx/Makefile +++ b/arch/arm/mach-imx/Makefile @@ -223,7 +223,7 @@ endif ifeq ($(CONFIG_ARCH_IMX9)$(CONFIG_ARCH_IMX8ULP), y) -ifneq ($(and $(CONFIG_IMX95),$(CONFIG_BINMAN)),) +ifneq ($(and $(CONFIG_BINMAN),$(or $(CONFIG_IMX95),$(CONFIG_IMX94))),) SPL: spl/u-boot-spl.bin FORCE $(call if_changed,mkimage) else diff --git a/arch/arm/mach-imx/imx9/Kconfig b/arch/arm/mach-imx/imx9/Kconfig index f2011448c23..48f458fa55c 100644 --- a/arch/arm/mach-imx/imx9/Kconfig +++ b/arch/arm/mach-imx/imx9/Kconfig @@ -106,6 +106,13 @@ config TARGET_IMX95_19X19_EVK imply BOOTSTD_FULL imply OF_UPSTREAM +config TARGET_IMX943_EVK + bool "imx943_evk" + select IMX94 + imply BOOTSTD_BOOTCOMMAND + imply BOOTSTD_FULL + imply OF_UPSTREAM + endchoice source "board/freescale/imx91_evk/Kconfig" @@ -114,6 +121,7 @@ source "board/freescale/imx93_frdm/Kconfig" source "board/freescale/imx93_qsb/Kconfig" source "board/phytec/phycore_imx93/Kconfig" source "board/variscite/imx93_var_som/Kconfig" +source "board/freescale/imx94_evk/Kconfig" source "board/freescale/imx95_evk/Kconfig" endif diff --git a/board/freescale/imx94_evk/Kconfig b/board/freescale/imx94_evk/Kconfig new file mode 100644 index 00000000000..a4237244ace --- /dev/null +++ b/board/freescale/imx94_evk/Kconfig @@ -0,0 +1,12 @@ +if TARGET_IMX943_EVK + +config SYS_BOARD + default "imx94_evk" + +config SYS_VENDOR + default "freescale" + +config SYS_CONFIG_NAME + default "imx94_evk" + +endif diff --git a/board/freescale/imx94_evk/MAINTAINERS b/board/freescale/imx94_evk/MAINTAINERS new file mode 100644 index 00000000000..95309430734 --- /dev/null +++ b/board/freescale/imx94_evk/MAINTAINERS @@ -0,0 +1,6 @@ +i.MX94 EVK BOARD +M: Alice Guo +S: Maintained +F: board/freescale/imx94_evk/ +F: include/configs/imx94_evk.h +F: configs/imx943_evk_defconfig diff --git a/board/freescale/imx94_evk/Makefile b/board/freescale/imx94_evk/Makefile new file mode 100644 index 00000000000..ca31602f6ba --- /dev/null +++ b/board/freescale/imx94_evk/Makefile @@ -0,0 +1,11 @@ +# +# Copyright 2025 NXP +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y += imx94_evk.o + +ifdef CONFIG_SPL_BUILD +obj-y += spl.o +endif diff --git a/board/freescale/imx94_evk/imx94_evk.c b/board/freescale/imx94_evk/imx94_evk.c new file mode 100644 index 00000000000..28d512ac5f3 --- /dev/null +++ b/board/freescale/imx94_evk/imx94_evk.c @@ -0,0 +1,41 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2025 NXP + */ + +#include +#include +#include +#include +#include + +int board_early_init_f(void) +{ + init_uart_clk(0); + return 0; +} + +int board_init(void) +{ + return 0; +} + +int board_late_init(void) +{ + if (IS_ENABLED(CONFIG_ENV_IS_IN_MMC)) + board_late_mmc_env_init(); + + env_set("sec_boot", "no"); + + if (IS_ENABLED(CONFIG_AHAB_BOOT)) + env_set("sec_boot", "yes"); + + return 0; +} + +int board_phys_sdram_size(phys_size_t *size) +{ + *size = PHYS_SDRAM_SIZE + PHYS_SDRAM_2_SIZE; + + return 0; +} diff --git a/board/freescale/imx94_evk/imx94_evk.env b/board/freescale/imx94_evk/imx94_evk.env new file mode 100644 index 00000000000..2baf1bbadcb --- /dev/null +++ b/board/freescale/imx94_evk/imx94_evk.env @@ -0,0 +1,100 @@ +#ifdef CONFIG_AHAB_BOOT +sec_boot=yes +#else +sec_boot=no +#endif + +jh_root_dtb=imx943-evk-root.dtb +jh_mmcboot=setenv fdtfile ${jh_root_dtb}; + setenv jh_clk kvm.enable_virt_at_load=false cpuidle.off=1 clk_ignore_unused kvm-arm.mode=nvhe; + setenv jh_root_mem 0x60000000@0x90000000,0x100000000@0x100000000; + if run loadimage; then + run mmcboot; + else run jh_netboot; fi; +jh_netboot=setenv fdtfile ${jh_root_dtb}; + setenv jh_root_mem 0x60000000@0x90000000,0x100000000@0x100000000; + setenv jh_clk kvm.enable_virt_at_load=false cpuidle.off=1 clk_ignore_unused kvm-arm.mode=nvhe; run netboot; + +initrd_addr=0x93800000 +emmc_dev=0 +sd_dev=1 +scriptaddr=0x93500000 +kernel_addr_r=CONFIG_SYS_LOAD_ADDR +image=Image +splashimage=0xA0000000 +console=ttyLP0,115200 earlycon +fdt_addr_r=0x93000000 +fdt_addr=0x93000000 +cntr_addr=0xA8000000 +cntr_file=os_cntr_signed.bin +boot_fit=no +fdtfile=CONFIG_DEFAULT_FDT_FILE +bootm_size=0x10000000 +mmcdev=CONFIG_SYS_MMC_ENV_DEV +mmcautodetect=yes +mmcargs=setenv bootargs ${jh_clk} ${mcore_args} console=${console} root=${mmcroot} +prepare_mcore=setenv mcore_args pd_ignore_unused; +loadbootscript=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script}; +bootscript=echo Running bootscript from mmc ...; source +loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image} +loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr_r} ${fdtfile} +loadcntr=fatload mmc ${mmcdev}:${mmcpart} ${cntr_addr} ${cntr_file} +auth_os=booti ${cntr_addr} +boot_os=booti ${loadaddr} - ${fdt_addr_r}; +mmcboot=echo Booting from mmc ...; + run mmcargs; + if test ${sec_boot} = yes; then + run auth_os; + else + if test ${boot_fit} = yes || test ${boot_fit} = try; then + bootm ${loadaddr}; + else + if run loadfdt; then + run boot_os; + else + echo WARN: Cannot load the DT; + fi; + fi; + fi; +netargs=setenv bootargs ${jh_clk} ${mcore_args} console=${console} root=/dev/nfs + ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp +netboot=echo Booting from net ...; + run netargs; + if test ${ip_dyn} = yes; then + setenv get_cmd dhcp; + else + setenv get_cmd tftp; + fi; + if test ${sec_boot} = yes; then + ${get_cmd} ${cntr_addr} ${cntr_file}; + run auth_os; + else + ${get_cmd} ${loadaddr} ${image}; + if test ${boot_fit} = yes || test ${boot_fit} = try; then + bootm ${loadaddr}; + else + if ${get_cmd} ${fdt_addr_r} ${fdtfile}; then + run boot_os; + else + echo WARN: Cannot load the DT; + fi; + fi; + fi; +bsp_bootcmd=echo Running BSP bootcmd ...; + mmc dev ${mmcdev}; if mmc rescan; then + if run loadbootscript; then + run bootscript; + else + if test ${sec_boot} = yes; then + if run loadcntr; then + run mmcboot; + else run netboot; + fi; + else + if run loadimage; then + run mmcboot; + else run netboot; + fi; + fi; + fi; + fi; diff --git a/board/freescale/imx94_evk/spl.c b/board/freescale/imx94_evk/spl.c new file mode 100644 index 00000000000..341b165b3c8 --- /dev/null +++ b/board/freescale/imx94_evk/spl.c @@ -0,0 +1,81 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2025 NXP + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +int spl_board_boot_device(enum boot_device boot_dev_spl) +{ + switch (boot_dev_spl) { + case SD1_BOOT: + case MMC1_BOOT: + return BOOT_DEVICE_MMC1; + case SD2_BOOT: + case MMC2_BOOT: + return BOOT_DEVICE_MMC2; + case USB_BOOT: + return BOOT_DEVICE_BOARD; + case QSPI_BOOT: + return BOOT_DEVICE_SPI; + default: + return BOOT_DEVICE_NONE; + } +} + +void spl_board_init(void) +{ + int ret; + + puts("Normal Boot\n"); + + ret = ele_start_rng(); + if (ret) + printf("Fail to start RNG: %d\n", ret); +} + +/* SCMI support by default */ +void board_init_f(ulong dummy) +{ + int ret; + + /* Clear the BSS. */ + memset(__bss_start, 0, __bss_end - __bss_start); + + if (IS_ENABLED(CONFIG_SPL_RECOVER_DATA_SECTION) && + IS_ENABLED(CONFIG_SPL_BUILD)) + spl_save_restore_data(); + + timer_init(); + + spl_early_init(); + + /* Need enable SCMI drivers and ELE driver before enabling console */ + ret = imx9_probe_mu(); + if (ret) + hang(); /* if MU not probed, nothing can output, just hang here */ + + arch_cpu_init(); + + board_early_init_f(); + + preloader_console_init(); + + debug("SOC: 0x%x\n", gd->arch.soc_rev); + debug("LC: 0x%x\n", gd->arch.lifecycle); + + get_reset_reason(true, false); + + board_init_r(NULL, 0); +} diff --git a/configs/imx943_evk_defconfig b/configs/imx943_evk_defconfig new file mode 100644 index 00000000000..27230ed3207 --- /dev/null +++ b/configs/imx943_evk_defconfig @@ -0,0 +1,115 @@ +CONFIG_ARM=y +CONFIG_ARCH_IMX9=y +CONFIG_TEXT_BASE=0x90200000 +CONFIG_SYS_MALLOC_LEN=0x2000000 +CONFIG_SYS_MALLOC_F_LEN=0x10000 +CONFIG_SPL_GPIO=y +CONFIG_SPL_LIBCOMMON_SUPPORT=y +CONFIG_SPL_LIBGENERIC_SUPPORT=y +CONFIG_NR_DRAM_BANKS=2 +CONFIG_ENV_SOURCE_FILE="imx94_evk" +CONFIG_ENV_SIZE=0x4000 +CONFIG_ENV_OFFSET=0x700000 +CONFIG_DM_GPIO=y +CONFIG_DEFAULT_DEVICE_TREE="freescale/imx943-evk" +CONFIG_TARGET_IMX943_EVK=y +CONFIG_OF_LIBFDT_OVERLAY=y +CONFIG_SYS_MONITOR_LEN=524288 +CONFIG_SPL_MMC=y +CONFIG_SPL_SERIAL=y +CONFIG_SPL_DRIVERS_MISC=y +CONFIG_SPL_TEXT_BASE=0x20480000 +CONFIG_SPL_HAS_BSS_LINKER_SECTION=y +CONFIG_SPL_BSS_START_ADDR=0x204d6000 +CONFIG_SPL_BSS_MAX_SIZE=0x2000 +CONFIG_SYS_LOAD_ADDR=0x90400000 +CONFIG_SPL=y +CONFIG_SPL_RECOVER_DATA_SECTION=y +CONFIG_PCI=y +CONFIG_OF_BOARD_FIXUP=y +CONFIG_SYS_MEMTEST_START=0x90000000 +CONFIG_SYS_MEMTEST_END=0xA0000000 +CONFIG_REMAKE_ELF=y +CONFIG_FIT=y +CONFIG_FIT_VERBOSE=y +CONFIG_OF_SYSTEM_SETUP=y +CONFIG_BOOTCOMMAND="bootflow scan -l; run bsp_bootcmd" +CONFIG_DEFAULT_FDT_FILE="imx943-evk.dtb" +CONFIG_SYS_CBSIZE=2048 +CONFIG_SYS_PBSIZE=2074 +CONFIG_BOARD_EARLY_INIT_F=y +CONFIG_BOARD_LATE_INIT=y +CONFIG_SPL_MAX_SIZE=0x30000 +CONFIG_SPL_BOARD_INIT=y +CONFIG_SPL_LOAD_IMX_CONTAINER=y +# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set +CONFIG_SPL_SYS_MALLOC=y +CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y +CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x93200000 +CONFIG_SPL_SYS_MALLOC_SIZE=0x80000 +CONFIG_SPL_SYS_MMCSD_RAW_MODE=y +CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x1040 +CONFIG_SPL_DM_MAILBOX=y +CONFIG_SPL_POWER_DOMAIN=y +CONFIG_SPL_THERMAL=y +CONFIG_SPL_WATCHDOG=y +CONFIG_SYS_PROMPT="u-boot=> " +CONFIG_CMD_ERASEENV=y +CONFIG_CMD_NVEDIT_EFI=y +CONFIG_CRC32_VERIFY=y +CONFIG_CMD_MEMTEST=y +CONFIG_CMD_CLK=y +CONFIG_CMD_DFU=y +CONFIG_CMD_FUSE=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_GPT=y +CONFIG_CMD_MMC=y +CONFIG_CMD_PCI=y +CONFIG_CMD_POWEROFF=y +CONFIG_CMD_SNTP=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_EFIDEBUG=y +CONFIG_CMD_RTC=y +CONFIG_CMD_TIME=y +CONFIG_CMD_GETTIME=y +CONFIG_CMD_TIMER=y +CONFIG_CMD_REGULATOR=y +CONFIG_CMD_HASH=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_OF_CONTROL=y +CONFIG_SPL_OF_CONTROL=y +CONFIG_ENV_OVERWRITE=y +CONFIG_ENV_IS_NOWHERE=y +CONFIG_ENV_IS_IN_MMC=y +CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y +CONFIG_SPL_DM=y +CONFIG_SPL_DM_SEQ_ALIAS=y +CONFIG_REGMAP=y +CONFIG_SYSCON=y +CONFIG_SPL_OF_TRANSLATE=y +CONFIG_CLK=y +CONFIG_SPL_CLK=y +CONFIG_SPL_CLK_CCF=y +CONFIG_CLK_CCF=y +CONFIG_CLK_SCMI=y +CONFIG_SPL_CLK_SCMI=y +CONFIG_SPL_FIRMWARE=y +# CONFIG_SCMI_AGENT_SMCCC is not set +CONFIG_IMX_RGPIO2P=y +CONFIG_IMX_MU_MBOX=y +CONFIG_SUPPORT_EMMC_BOOT=y +CONFIG_FSL_USDHC=y +CONFIG_PINCTRL=y +CONFIG_SPL_PINCTRL=y +CONFIG_PINCTRL_IMX_SCMI=y +CONFIG_POWER_DOMAIN=y +CONFIG_SCMI_POWER_DOMAIN=y +CONFIG_DM_REGULATOR=y +CONFIG_SPL_DM_REGULATOR=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_SPL_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_DM_RTC=y +CONFIG_DM_SERIAL=y +CONFIG_FSL_LPUART=y +CONFIG_ULP_WATCHDOG=y diff --git a/doc/board/nxp/imx943_evk.rst b/doc/board/nxp/imx943_evk.rst new file mode 100644 index 00000000000..651db08a0f7 --- /dev/null +++ b/doc/board/nxp/imx943_evk.rst @@ -0,0 +1,112 @@ +.. SPDX-License-Identifier: GPL-2.0+ + +imx943_evk +======================= + +U-Boot for the NXP i.MX943 19x19 EVK board + +Quick Start +----------- + +- Get ahab-container.img +- Get DDR PHY Firmware Images +- Get and Build OEI Images +- Get and Build System Manager Image +- Get and Build the ARM Trusted Firmware +- Build the Bootloader Image +- Boot + +Get ahab-container.img +-------------------------------------- + +Note: srctree is U-Boot source directory + +.. code-block:: bash + + $ wget https://www.nxp.com/lgfiles/NMG/MAD/YOCTO/firmware-ele-imx-2.0.2-89161a8.bin + $ sh firmware-ele-imx-2.0.2-89161a8.bin --auto-accept + $ cp firmware-ele-imx-2.0.2-89161a8/mx943a0-ahab-container.img $(srctree) + +Get DDR PHY Firmware Images +-------------------------------------- + +Note: srctree is U-Boot source directory + +.. code-block:: bash + + $ wget https://www.nxp.com/lgfiles/NMG/MAD/YOCTO/firmware-imx-8.28-994fa14.bin + $ sh firmware-imx-8.28-994fa14.bin --auto-accept + $ cp firmware-imx-8.28-994fa14/firmware/ddr/synopsys/lpddr5*v202409.bin $(srctree) + +Get and Build OEI Images +-------------------------------------- + +Note: srctree is U-Boot source directory +Get OEI from: https://github.com/nxp-imx/imx-oei +branch: master + +.. code-block:: bash + + $ sudo apt -y install make gcc g++-multilib srecord + $ wget https://developer.arm.com/-/media/Files/downloads/gnu/13.3.rel1/binrel/arm-gnu-toolchain-13.3.rel1-x86_64-arm-none-eabi.tar.xz + $ tar xvf arm-gnu-toolchain-13.3.rel1-x86_64-arm-none-eabi.tar.xz + $ export TOOLS=$PWD + $ git clone -b master https://github.com/nxp-imx/imx-oei.git + $ cd imx-oei + $ make board=mx943lp5-19 oei=ddr DEBUG=1 all + $ cp build/mx943lp5-19/ddr/oei-m33-ddr.bin $(srctree) + +Get and Build System Manager Image +-------------------------------------- + +Note: srctree is U-Boot source directory +Get System Manager from: https://github.com/nxp-imx/imx-sm +branch: master + +.. code-block:: bash + + $ sudo apt -y install make gcc g++-multilib srecord + $ wget https://developer.arm.com/-/media/Files/downloads/gnu/13.3.rel1/binrel/arm-gnu-toolchain-13.3.rel1-x86_64-arm-none-eabi.tar.xz + $ tar xvf arm-gnu-toolchain-13.3.rel1-x86_64-arm-none-eabi.tar.xz + $ export TOOLS=$PWD + $ git clone -b master https://github.com/nxp-imx/imx-sm.git + $ cd imx-sm + $ make config=mx94evk all + $ cp build/mx94evk/m33_image.bin $(srctree) + +Get and Build the ARM Trusted Firmware +-------------------------------------- + +Note: srctree is U-Boot source directory +Get ATF from: https://github.com/nxp-imx/imx-atf/ +branch: lf_v2.12 + +.. code-block:: bash + + $ export CROSS_COMPILE=aarch64-poky-linux- + $ unset LDFLAGS + $ unset AS + $ git clone -b lf_v2.12 https://github.com/nxp-imx/imx-atf.git + $ cd imx-atf + $ make PLAT=imx94 bl31 + $ cp build/imx94/release/bl31.bin $(srctree) + +Build the Bootloader Image +-------------------------- + +.. code-block:: bash + + $ export CROSS_COMPILE=aarch64-poky-linux- + $ make imx943_evk_defconfig + $ make + +Copy flash.bin to the MicroSD card: + +.. code-block:: bash + + $ sudo dd if=flash.bin of=/dev/sd[x] bs=1k seek=32 conv=fsync + +Boot +---- + +Set i.MX943 boot device to MicroSD card diff --git a/doc/board/nxp/index.rst b/doc/board/nxp/index.rst index aa7d857346d..670501164b5 100644 --- a/doc/board/nxp/index.rst +++ b/doc/board/nxp/index.rst @@ -16,6 +16,7 @@ NXP Semiconductors imx93_9x9_qsb imx93_11x11_evk imx93_frdm + imx943_evk imx95_evk imxrt1020-evk imxrt1050-evk diff --git a/include/configs/imx94_evk.h b/include/configs/imx94_evk.h new file mode 100644 index 00000000000..f93c3c4e4a8 --- /dev/null +++ b/include/configs/imx94_evk.h @@ -0,0 +1,24 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2025 NXP + */ + +#ifndef __IMX94_EVK_H +#define __IMX94_EVK_H + +#include +#include +#include + +#define CFG_SYS_INIT_RAM_ADDR 0x90000000 +#define CFG_SYS_INIT_RAM_SIZE 0x200000 + +#define CFG_SYS_SDRAM_BASE 0x90000000 +#define PHYS_SDRAM 0x90000000 +#define PHYS_SDRAM_SIZE 0x70000000UL /* 2GB - 256MB DDR */ +#define PHYS_SDRAM_2_SIZE 0x180000000 /* 8GB */ + +/* Using ULP WDOG for reset */ +#define WDOG_BASE_ADDR WDG3_BASE_ADDR + +#endif -- cgit v1.2.3 From 89bae6ea2d46e642339842caab49917bf6d9f4ec Mon Sep 17 00:00:00 2001 From: Primoz Fiser Date: Tue, 23 Sep 2025 12:49:07 +0200 Subject: board: phytec: phycore-imx93: Set CONFIG_ETHPRIME to eth0 Set ethprime to eth0 since FEC interface is considered the primary IF on phyCORE-i.MX93 SoM based boards. This comes from the fact that the same bootloader is reused for both carrier boards, that is phyBOARD-Segin and phyBOARD-Nash which both use different Ethernet PHYs on the EQOS (eth1) interface and thus eth1 cannot be used as a prime. Signed-off-by: Primoz Fiser --- configs/imx93-phycore_defconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/configs/imx93-phycore_defconfig b/configs/imx93-phycore_defconfig index 0acdfd2bf53..4c952e966d1 100644 --- a/configs/imx93-phycore_defconfig +++ b/configs/imx93-phycore_defconfig @@ -89,7 +89,7 @@ CONFIG_ENV_REDUNDANT=y CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_ENV_MMC_DEVICE_INDEX=1 CONFIG_USE_ETHPRIME=y -CONFIG_ETHPRIME="eth1" +CONFIG_ETHPRIME="eth0" CONFIG_NET_RANDOM_ETHADDR=y CONFIG_SPL_DM=y CONFIG_SPL_DM_SEQ_ALIAS=y -- cgit v1.2.3 From c320edc9c09a46db5a7815d157ff412f444274b8 Mon Sep 17 00:00:00 2001 From: Ye Li Date: Wed, 24 Sep 2025 10:11:24 +0800 Subject: spi: nxp_fspi: Use second last LUT entry for AHB read Use a dedicated LUT (second last) for AHB read command, so we can directly read from the AHB memory-mapped address and booting M core for XIP on Flexspi NOR. Signed-off-by: Ye Li --- drivers/spi/nxp_fspi.c | 14 ++++++++++++-- 1 file changed, 12 insertions(+), 2 deletions(-) diff --git a/drivers/spi/nxp_fspi.c b/drivers/spi/nxp_fspi.c index 6d97b8eefc9..2f9abdc7795 100644 --- a/drivers/spi/nxp_fspi.c +++ b/drivers/spi/nxp_fspi.c @@ -539,6 +539,15 @@ static void nxp_fspi_prepare_lut(struct nxp_fspi *f, fspi_writel(f, lutval[i], base + target_lut_reg); } + if (op->data.nbytes && op->data.dir == SPI_MEM_DATA_IN && + op->addr.nbytes) { + lut_offset = (f->devtype_data->lut_num - 2) * 4 * 4; + for (i = 0; i < ARRAY_SIZE(lutval); i++) { + target_lut_reg = FSPI_LUT_BASE + lut_offset + i * 4; + fspi_writel(f, lutval[i], base + target_lut_reg); + } + } + dev_dbg(f->dev, "CMD[%x] lutval[0:%x \t 1:%x \t 2:%x \t 3:%x], size: 0x%08x\n", op->cmd.opcode, lutval[0], lutval[1], lutval[2], lutval[3], op->data.nbytes); @@ -943,9 +952,10 @@ static int nxp_fspi_default_setup(struct nxp_fspi *f) /* * The driver only uses one single LUT entry, that is updated on * each call of exec_op(). Index 0 is preset at boot with a basic - * read operation, so let's use the last entry. + * read operation, last entry is used for dynamic lut, the second + * last entry is used for AHB read. */ - seqid_lut = f->devtype_data->lut_num - 1; + seqid_lut = f->devtype_data->lut_num - 2; /* AHB Read - Set lut sequence ID for all CS. */ fspi_writel(f, seqid_lut, base + FSPI_FLSHA1CR2); fspi_writel(f, seqid_lut, base + FSPI_FLSHA2CR2); -- cgit v1.2.3 From 2866c332180fa8f36a03c41943b45d80c6992f15 Mon Sep 17 00:00:00 2001 From: Ye Li Date: Wed, 24 Sep 2025 10:11:25 +0800 Subject: spi: nxp_fspi: Support i.MX8QXP flexspi Add the compatible string and driver data for i.MX8QXP. Signed-off-by: Ye Li --- drivers/spi/nxp_fspi.c | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/drivers/spi/nxp_fspi.c b/drivers/spi/nxp_fspi.c index 2f9abdc7795..6e2aee4672b 100644 --- a/drivers/spi/nxp_fspi.c +++ b/drivers/spi/nxp_fspi.c @@ -337,6 +337,15 @@ static struct nxp_fspi_devtype_data imxrt1170_data = { .little_endian = true, }; +static const struct nxp_fspi_devtype_data imx8qxp_data = { + .rxfifo = SZ_512, /* (64 * 64 bits) */ + .txfifo = SZ_1K, /* (128 * 64 bits) */ + .ahb_buf_size = SZ_2K, /* (256 * 64 bits) */ + .quirks = 0, + .lut_num = 32, + .little_endian = true, /* little-endian */ +}; + struct nxp_fspi { struct udevice *dev; void __iomem *iobase; @@ -1081,6 +1090,7 @@ static const struct udevice_id nxp_fspi_ids[] = { { .compatible = "nxp,lx2160a-fspi", .data = (ulong)&lx2160a_data, }, { .compatible = "nxp,imx8mm-fspi", .data = (ulong)&imx8mm_data, }, { .compatible = "nxp,imx8mp-fspi", .data = (ulong)&imx8mm_data, }, + { .compatible = "nxp,imx8qxp-fspi", .data = (ulong)&imx8qxp_data, }, { .compatible = "nxp,imxrt1170-fspi", .data = (ulong)&imxrt1170_data, }, { } }; -- cgit v1.2.3 From 8e8fdb6681b916b9db769fb8e082e1160e2801f4 Mon Sep 17 00:00:00 2001 From: Ye Li Date: Wed, 24 Sep 2025 10:11:26 +0800 Subject: spi: nxp_fspi: Support i.MX8DXL flexspi MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit According to i.MX8DXL A1 errata ERR050601, concurrent read accesses from the A35 cores to the peripherals within the LSIO subsystem (region 0_5DXX_XXXX) and address spaces in the regions [0_0000_0000 – 0_1BFF_FFFF] and [4_0000_0000 – 4_3FFF_FFFF] can collide and cause data corruption in the returned data, with no failure report. Even a single A35 core accessing both these regions can trigger the issue because an A35 core can have more than one parallel read operation in progress. The flexspi0 AHB memory is in LSIO region mentioned in above errata. So we can't use AHB read, only can read data from FIFO. Add the compatible string for 8DXL and use a flag for the IPS read. Signed-off-by: Ye Li --- drivers/spi/nxp_fspi.c | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/drivers/spi/nxp_fspi.c b/drivers/spi/nxp_fspi.c index 6e2aee4672b..3dfb54b1968 100644 --- a/drivers/spi/nxp_fspi.c +++ b/drivers/spi/nxp_fspi.c @@ -346,6 +346,15 @@ static const struct nxp_fspi_devtype_data imx8qxp_data = { .little_endian = true, /* little-endian */ }; +static const struct nxp_fspi_devtype_data imx8dxl_data = { + .rxfifo = SZ_512, /* (64 * 64 bits) */ + .txfifo = SZ_1K, /* (128 * 64 bits) */ + .ahb_buf_size = SZ_2K, /* (256 * 64 bits) */ + .quirks = FSPI_QUIRK_USE_IP_ONLY, + .lut_num = 32, + .little_endian = true, /* little-endian */ +}; + struct nxp_fspi { struct udevice *dev; void __iomem *iobase; @@ -1091,6 +1100,7 @@ static const struct udevice_id nxp_fspi_ids[] = { { .compatible = "nxp,imx8mm-fspi", .data = (ulong)&imx8mm_data, }, { .compatible = "nxp,imx8mp-fspi", .data = (ulong)&imx8mm_data, }, { .compatible = "nxp,imx8qxp-fspi", .data = (ulong)&imx8qxp_data, }, + { .compatible = "nxp,imx8dxl-fspi", .data = (ulong)&imx8dxl_data, }, { .compatible = "nxp,imxrt1170-fspi", .data = (ulong)&imxrt1170_data, }, { } }; -- cgit v1.2.3 From 320b191ec820705f24ab7f7981dc3b60ab9e0ee8 Mon Sep 17 00:00:00 2001 From: Ye Li Date: Wed, 24 Sep 2025 10:11:27 +0800 Subject: spi: nxp_fspi: Support i.MX8ULP flexspi Add i.MX8ULP flexspi compatible string and driver data. The flexspi on i.MX8ULP only has 16 LUT sequences and uses 1KB RX FIFO. Signed-off-by: Ye Li --- drivers/spi/nxp_fspi.c | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/drivers/spi/nxp_fspi.c b/drivers/spi/nxp_fspi.c index 3dfb54b1968..7086a2a264a 100644 --- a/drivers/spi/nxp_fspi.c +++ b/drivers/spi/nxp_fspi.c @@ -355,6 +355,15 @@ static const struct nxp_fspi_devtype_data imx8dxl_data = { .little_endian = true, /* little-endian */ }; +static const struct nxp_fspi_devtype_data imx8ulp_data = { + .rxfifo = SZ_1K, /* (128 * 64 bits) */ + .txfifo = SZ_1K, /* (128 * 64 bits) */ + .ahb_buf_size = SZ_2K, /* (256 * 64 bits) */ + .quirks = 0, + .lut_num = 16, + .little_endian = true, /* little-endian */ +}; + struct nxp_fspi { struct udevice *dev; void __iomem *iobase; @@ -1101,6 +1110,7 @@ static const struct udevice_id nxp_fspi_ids[] = { { .compatible = "nxp,imx8mp-fspi", .data = (ulong)&imx8mm_data, }, { .compatible = "nxp,imx8qxp-fspi", .data = (ulong)&imx8qxp_data, }, { .compatible = "nxp,imx8dxl-fspi", .data = (ulong)&imx8dxl_data, }, + { .compatible = "nxp,imx8ulp-fspi", .data = (ulong)&imx8ulp_data, }, { .compatible = "nxp,imxrt1170-fspi", .data = (ulong)&imxrt1170_data, }, { } }; -- cgit v1.2.3 From 1566f803bff58f472c38e2e34204753529d01136 Mon Sep 17 00:00:00 2001 From: Ye Li Date: Fri, 26 Sep 2025 20:24:18 +0800 Subject: imx9: scmi: Add PCIE ECAM and outbound space to MMU Add PCIE1 and PCIE2 ECAM space and outbound space to MMU pagetable, so A55 can access them. Signed-off-by: Ye Li Reviewed-by: Peng Fan --- arch/arm/mach-imx/imx9/scmi/soc.c | 24 ++++++++++++++++++++++++ 1 file changed, 24 insertions(+) diff --git a/arch/arm/mach-imx/imx9/scmi/soc.c b/arch/arm/mach-imx/imx9/scmi/soc.c index 5c1e13c9842..dbaa19a9e6e 100644 --- a/arch/arm/mach-imx/imx9/scmi/soc.c +++ b/arch/arm/mach-imx/imx9/scmi/soc.c @@ -257,6 +257,30 @@ static struct mm_region imx9_mem_map[] = { PTE_BLOCK_OUTER_SHARE }, { #endif + /* PCIE2 ECAM */ + .virt = 0x880000000UL, + .phys = 0x880000000UL, + .size = 0x10000000UL, + .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | + PTE_BLOCK_NON_SHARE | + PTE_BLOCK_PXN | PTE_BLOCK_UXN + }, { + /* PCIE1 Outbound */ + .virt = 0x900000000UL, + .phys = 0x900000000UL, + .size = 0x100000000UL, + .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | + PTE_BLOCK_NON_SHARE | + PTE_BLOCK_PXN | PTE_BLOCK_UXN + }, { + /* PCIE2 Outbound */ + .virt = 0xA00000000UL, + .phys = 0xA00000000UL, + .size = 0x100000000UL, + .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | + PTE_BLOCK_NON_SHARE | + PTE_BLOCK_PXN | PTE_BLOCK_UXN + }, { /* empty entry to split table entry 5 if needed when TEEs are used */ 0, }, { -- cgit v1.2.3 From e54bf98c3afc6dc6e6ce9496c217cb1c660aac4d Mon Sep 17 00:00:00 2001 From: Rasmus Villemoes Date: Fri, 19 Sep 2025 12:09:54 +0200 Subject: malloc.h: be a bit more consistent with macro definitions Currrently, malloc and free are function-like macros, while calloc, realloc and memalign are object-like macros. Usually, this doesn't matter, but it does when the identifiers appear without a following open parenthesis, such as when their address is taken for building the export table. Adding calloc or realloc to that table breaks the build on sandbox due to this inconsistency. Signed-off-by: Rasmus Villemoes Reviewed-by: Tom Rini --- include/malloc.h | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/include/malloc.h b/include/malloc.h index 9e0be482416..3979fc62830 100644 --- a/include/malloc.h +++ b/include/malloc.h @@ -904,11 +904,11 @@ void *realloc_simple(void *ptr, size_t size); # define mALLOPt dlmallopt /* Ensure that U-Boot actually uses these too */ -#define calloc dlcalloc +#define calloc(x,y) dlcalloc(x,y) #define free(ptr) dlfree(ptr) #define malloc(x) dlmalloc(x) -#define memalign dlmemalign -#define realloc dlrealloc +#define memalign(a,x) dlmemalign(a,x) +#define realloc(p,x) dlrealloc(p,x) #define valloc dlvalloc #define pvalloc dlpvalloc #define mallinfo() dlmallinfo() -- cgit v1.2.3 From 0933358163a3c0ef13577853194769504cfb39ea Mon Sep 17 00:00:00 2001 From: Rasmus Villemoes Date: Fri, 19 Sep 2025 12:09:55 +0200 Subject: _exports.h: drop creating dummy i2c entries and fixup config dependency There's really no good reason to create stub entries that would call a function that doesn't even return anything sensible. The existence of these two i2c_* functions depends on CONFIG_IS_ENABLED(SYS_I2C_LEGACY), which does depend on !DM_I2C, but is not equivalent to it. They are probably rather hard to use unless CMD_I2C and something in U-Boot has called "i2c dev foo" to set the current i2c bus before calling the standalone app, so keep that dependency. Signed-off-by: Rasmus Villemoes Reviewed-by: Tom Rini --- include/_exports.h | 6 +----- 1 file changed, 1 insertion(+), 5 deletions(-) diff --git a/include/_exports.h b/include/_exports.h index 1af946fac32..39278a34942 100644 --- a/include/_exports.h +++ b/include/_exports.h @@ -1,7 +1,6 @@ /* * You need to use #ifdef around functions that may not exist * in the final configuration (such as i2c). - * use a dummyfunction as first parameter to EXPORT_FUNC. * As an example see the CONFIG_CMD_I2C section below */ #ifndef EXPORT_FUNC @@ -43,12 +42,9 @@ EXPORT_FUNC(simple_strtol, long, simple_strtol, const char *, char **, unsigned int) EXPORT_FUNC(strcmp, int, strcmp, const char *cs, const char *ct) -#if defined(CONFIG_CMD_I2C) && !CONFIG_IS_ENABLED(DM_I2C) +#if defined(CONFIG_CMD_I2C) && CONFIG_IS_ENABLED(SYS_I2C_LEGACY) EXPORT_FUNC(i2c_write, int, i2c_write, uchar, uint, int , uchar * , int) EXPORT_FUNC(i2c_read, int, i2c_read, uchar, uint, int , uchar * , int) -#else - EXPORT_FUNC(dummy, void, i2c_write, void) - EXPORT_FUNC(dummy, void, i2c_read, void) #endif #if !defined(CONFIG_CMD_SPI) || defined(CONFIG_DM_SPI) -- cgit v1.2.3 From 475a72f6471194633fd85a813547bebe846611e0 Mon Sep 17 00:00:00 2001 From: Rasmus Villemoes Date: Fri, 19 Sep 2025 12:09:56 +0200 Subject: _exports.h: simplify condition for including spi functions As for the i2c functions, drop the dummy entries that, if ever used, would just have the standalone app get some random content in the return register. While deprecated, the spi_{setup,free}_slave functions do exist even with CONFIG_DM_SPI - and a standalone app can't really do anything but refer to a spi device via a (bus, cs) pair. Eventually, one should probably export some function that could allow a standalone app to get a struct udevice* corresponding to either a full DT path, an alias, or perhaps a label (provided one builds with -@), and then export functions that can operate on that. Signed-off-by: Rasmus Villemoes Reviewed-by: Tom Rini --- include/_exports.h | 11 +---------- 1 file changed, 1 insertion(+), 10 deletions(-) diff --git a/include/_exports.h b/include/_exports.h index 39278a34942..c1511903088 100644 --- a/include/_exports.h +++ b/include/_exports.h @@ -47,19 +47,10 @@ EXPORT_FUNC(i2c_read, int, i2c_read, uchar, uint, int , uchar * , int) #endif -#if !defined(CONFIG_CMD_SPI) || defined(CONFIG_DM_SPI) - EXPORT_FUNC(dummy, void, spi_setup_slave, void) - EXPORT_FUNC(dummy, void, spi_free_slave, void) -#else +#if defined(CONFIG_CMD_SPI) EXPORT_FUNC(spi_setup_slave, struct spi_slave *, spi_setup_slave, unsigned int, unsigned int, unsigned int, unsigned int) EXPORT_FUNC(spi_free_slave, void, spi_free_slave, struct spi_slave *) -#endif -#ifndef CONFIG_CMD_SPI - EXPORT_FUNC(dummy, void, spi_claim_bus, void) - EXPORT_FUNC(dummy, void, spi_release_bus, void) - EXPORT_FUNC(dummy, void, spi_xfer, void) -#else EXPORT_FUNC(spi_claim_bus, int, spi_claim_bus, struct spi_slave *) EXPORT_FUNC(spi_release_bus, void, spi_release_bus, struct spi_slave *) EXPORT_FUNC(spi_xfer, int, spi_xfer, struct spi_slave *, -- cgit v1.2.3 From eb178c849c25024225941db79c1c3b9681a46a80 Mon Sep 17 00:00:00 2001 From: Rasmus Villemoes Date: Fri, 19 Sep 2025 12:09:57 +0200 Subject: _exports.h: drop the last dummy entries Signed-off-by: Rasmus Villemoes Reviewed-by: Tom Rini --- include/_exports.h | 3 --- 1 file changed, 3 deletions(-) diff --git a/include/_exports.h b/include/_exports.h index c1511903088..21afb8d37f8 100644 --- a/include/_exports.h +++ b/include/_exports.h @@ -20,9 +20,6 @@ int, interrupt_handler_t, void*) EXPORT_FUNC(irq_free_handler, void, free_hdlr, int) -#else - EXPORT_FUNC(dummy, void, install_hdlr, void) - EXPORT_FUNC(dummy, void, free_hdlr, void) #endif EXPORT_FUNC(malloc, void *, malloc, size_t) #if !CONFIG_IS_ENABLED(SYS_MALLOC_SIMPLE) -- cgit v1.2.3 From a78941bc7ff72ab3b67197d53216306429e6a831 Mon Sep 17 00:00:00 2001 From: Rasmus Villemoes Date: Fri, 19 Sep 2025 12:09:58 +0200 Subject: exports.c: drop unused dummy function The !CONFIG_PHY_AQUANTIA defines were already superfluous since _exports.h does have a CONFIG_PHY_AQUANTIA, so the entries never existed. In fact, it couldn't have worked, because the defines would affect both occurences of the mdio_get_current_dev identifier in the EXPORT_FUNC(mdio_get_current_dev, struct mii_dev *, mdio_get_current_dev, void) so the C code would end up containing four copies of gd->jt->dummy = dummy but struct jt_funcs would not and does not have any 'dummy' member. Now that nothing in _exports.h refers to dummy(), remove the empty function. Signed-off-by: Rasmus Villemoes Reviewed-by: Tom Rini --- common/exports.c | 11 ----------- 1 file changed, 11 deletions(-) diff --git a/common/exports.c b/common/exports.c index 48b084c3861..1b7fec685b1 100644 --- a/common/exports.c +++ b/common/exports.c @@ -7,10 +7,6 @@ DECLARE_GLOBAL_DATA_PTR; -__attribute__((unused)) static void dummy(void) -{ -} - unsigned long get_version(void) { return XF_VERSION; @@ -18,13 +14,6 @@ unsigned long get_version(void) #define EXPORT_FUNC(f, a, x, ...) gd->jt->x = f; -#ifndef CONFIG_PHY_AQUANTIA -# define mdio_get_current_dev dummy -# define phy_find_by_mask dummy -# define mdio_phydev_for_ethname dummy -# define miiphy_set_current_dev dummy -#endif - int jumptable_init(void) { gd->jt = malloc(sizeof(struct jt_funcs)); -- cgit v1.2.3 From bdbaaee65c69eebe1ee47296fa2fb12a4677697c Mon Sep 17 00:00:00 2001 From: Rasmus Villemoes Date: Fri, 19 Sep 2025 12:09:59 +0200 Subject: exports.h: make sure declarations are in sync with the actual exports After finishing a later patch in this series, I discovered I had neglected to update the list of declarations in exports.h to match. But then I realized I wasn't the first to do that. Use the existing mechanism and DRY it out. Signed-off-by: Rasmus Villemoes Reviewed-by: Tom Rini --- include/exports.h | 36 +++--------------------------------- 1 file changed, 3 insertions(+), 33 deletions(-) diff --git a/include/exports.h b/include/exports.h index 23cc3a66c20..bcf170dca87 100644 --- a/include/exports.h +++ b/include/exports.h @@ -26,39 +26,9 @@ struct spi_slave; int jumptable_init(void); /* These are declarations of exported functions available in C code */ -unsigned long get_version(void); -int getc(void); -int tstc(void); -void putc(const char); -void puts(const char*); -int printf(const char* fmt, ...); -void install_hdlr(int, interrupt_handler_t, void*); -void free_hdlr(int); -void *malloc(size_t); -#if !CONFIG_IS_ENABLED(SYS_MALLOC_SIMPLE) -void free(void*); -#endif -void __udelay(unsigned long); -unsigned long get_timer(unsigned long); -int vprintf(const char *, va_list); -unsigned long simple_strtoul(const char *cp, char **endp, unsigned int base); -int strict_strtoul(const char *cp, unsigned int base, unsigned long *res); -char *env_get(const char *name); -int env_set(const char *varname, const char *value); -long simple_strtol(const char *cp, char **endp, unsigned int base); -int strcmp(const char *cs, const char *ct); -unsigned long ustrtoul(const char *cp, char **endp, unsigned int base); -unsigned long long ustrtoull(const char *cp, char **endp, unsigned int base); -#if defined(CONFIG_CMD_I2C) && !CONFIG_IS_ENABLED(DM_I2C) -int i2c_write (uchar, uint, int , uchar* , int); -int i2c_read (uchar, uint, int , uchar* , int); -#endif -#ifdef CONFIG_PHY_AQUANTIA -struct mii_dev *mdio_get_current_dev(void); -struct phy_device *phy_find_by_mask(struct mii_dev *bus, unsigned phy_mask); -struct phy_device *mdio_phydev_for_ethname(const char *ethname); -int miiphy_set_current_dev(const char *devname); -#endif +#define EXPORT_FUNC(impl, res, func, ...) res func(__VA_ARGS__); +#include <_exports.h> +#undef EXPORT_FUNC void app_startup(char * const *); -- cgit v1.2.3 From 2ef6c17f7f46a908e99e24de53d2c153dc1972ab Mon Sep 17 00:00:00 2001 From: Rasmus Villemoes Date: Fri, 19 Sep 2025 12:10:00 +0200 Subject: _exports.h: reorganize a bit The current list of exported functions is somewhat of a mess. Reorganize them so that related functionality is kept together: - console I/O: move vprintf next to printf and the getc/putc functions - integer parsing: move the *strto* functions together - standard string.h stuff: move memset() and strcpy() next to strcmp() - time: move mdelay() next to udelay() and get_timer() Signed-off-by: Rasmus Villemoes Reviewed-by: Tom Rini --- include/_exports.h | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) diff --git a/include/_exports.h b/include/_exports.h index 21afb8d37f8..f1b11c1e380 100644 --- a/include/_exports.h +++ b/include/_exports.h @@ -15,6 +15,7 @@ EXPORT_FUNC(flush, void, flush, void) #endif EXPORT_FUNC(printf, int, printf, const char*, ...) + EXPORT_FUNC(vprintf, int, vprintf, const char *, va_list) #if (defined(CONFIG_X86) && !defined(CONFIG_X86_64)) || defined(CONFIG_PPC) EXPORT_FUNC(irq_install_handler, void, install_hdlr, int, interrupt_handler_t, void*) @@ -25,9 +26,9 @@ #if !CONFIG_IS_ENABLED(SYS_MALLOC_SIMPLE) EXPORT_FUNC(free, void, free, void *) #endif + EXPORT_FUNC(mdelay, void, mdelay, unsigned long msec) EXPORT_FUNC(udelay, void, udelay, unsigned long) EXPORT_FUNC(get_timer, unsigned long, get_timer, unsigned long) - EXPORT_FUNC(vprintf, int, vprintf, const char *, va_list) EXPORT_FUNC(do_reset, int, do_reset, struct cmd_tbl *, int , int , char * const []) EXPORT_FUNC(env_get, char *, env_get, const char*) @@ -38,7 +39,13 @@ const char *, unsigned int , unsigned long *) EXPORT_FUNC(simple_strtol, long, simple_strtol, const char *, char **, unsigned int) + EXPORT_FUNC(ustrtoul, unsigned long, ustrtoul, + const char *, char **, unsigned int) + EXPORT_FUNC(ustrtoull, unsigned long long, ustrtoull, + const char *, char **, unsigned int) + EXPORT_FUNC(memset, void *, memset, void *, int, size_t) EXPORT_FUNC(strcmp, int, strcmp, const char *cs, const char *ct) + EXPORT_FUNC(strcpy, char *, strcpy, char *dest, const char *src) #if defined(CONFIG_CMD_I2C) && CONFIG_IS_ENABLED(SYS_I2C_LEGACY) EXPORT_FUNC(i2c_write, int, i2c_write, uchar, uint, int , uchar * , int) EXPORT_FUNC(i2c_read, int, i2c_read, uchar, uint, int , uchar * , int) @@ -53,13 +60,6 @@ EXPORT_FUNC(spi_xfer, int, spi_xfer, struct spi_slave *, unsigned int, const void *, void *, unsigned long) #endif - EXPORT_FUNC(ustrtoul, unsigned long, ustrtoul, - const char *, char **, unsigned int) - EXPORT_FUNC(ustrtoull, unsigned long long, ustrtoull, - const char *, char **, unsigned int) - EXPORT_FUNC(strcpy, char *, strcpy, char *dest, const char *src) - EXPORT_FUNC(mdelay, void, mdelay, unsigned long msec) - EXPORT_FUNC(memset, void *, memset, void *, int, size_t) #ifdef CONFIG_PHY_AQUANTIA EXPORT_FUNC(mdio_get_current_dev, struct mii_dev *, mdio_get_current_dev, void) -- cgit v1.2.3 From d95706158203db0b2281e134e8dfbad87e3d668c Mon Sep 17 00:00:00 2001 From: Rasmus Villemoes Date: Fri, 19 Sep 2025 12:10:01 +0200 Subject: _exports.h: export standard memory/string handling functions The current list of exported functions lacks quite a few bog-standard C library functions that we might as well expose, since U-Boot certainly has them implemented anyway. There's no reason a standalone application should have its own strlen() implementation or link in a copy from some tiny libc. For a customer's standalone app, this means it goes from 95K to 10K. More importantly, we can ditch the custom toolchain including a newlibc used to build the standalone app and just use the same toolchain as used to build u-boot itself. Signed-off-by: Rasmus Villemoes Reviewed-by: Tom Rini --- include/_exports.h | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/include/_exports.h b/include/_exports.h index f1b11c1e380..a23fc001421 100644 --- a/include/_exports.h +++ b/include/_exports.h @@ -23,6 +23,8 @@ EXPORT_FUNC(irq_free_handler, void, free_hdlr, int) #endif EXPORT_FUNC(malloc, void *, malloc, size_t) + EXPORT_FUNC(realloc, void *, realloc, void *, size_t) + EXPORT_FUNC(calloc, void *, calloc, size_t, size_t) #if !CONFIG_IS_ENABLED(SYS_MALLOC_SIMPLE) EXPORT_FUNC(free, void, free, void *) #endif @@ -43,9 +45,21 @@ const char *, char **, unsigned int) EXPORT_FUNC(ustrtoull, unsigned long long, ustrtoull, const char *, char **, unsigned int) + EXPORT_FUNC(memcmp, int, memcmp, const void *, const void *, size_t) + EXPORT_FUNC(memcpy, void *, memcpy, void *, const void *, size_t) + EXPORT_FUNC(memmove, void *, memmove, void *, const void *, size_t) EXPORT_FUNC(memset, void *, memset, void *, int, size_t) + EXPORT_FUNC(strchr, char *, strchr, const char *cs, int c) + EXPORT_FUNC(strlen, size_t, strlen, const char *s) + EXPORT_FUNC(strncmp, int, strncmp, const char *cs, const char *ct, size_t n) + EXPORT_FUNC(strncpy, char *, strncpy, char *dest, const char *src, size_t n) + EXPORT_FUNC(strnlen, size_t, strnlen, const char *s, size_t n) EXPORT_FUNC(strcmp, int, strcmp, const char *cs, const char *ct) EXPORT_FUNC(strcpy, char *, strcpy, char *dest, const char *src) + EXPORT_FUNC(sprintf, int, sprintf, char *, const char *, ...) + EXPORT_FUNC(snprintf, int, snprintf, char *, size_t, const char *, ...) + EXPORT_FUNC(vsprintf, int, vsprintf, char *, const char *, va_list) + EXPORT_FUNC(vsnprintf, int, vsnprintf, char *, size_t, const char *, va_list) #if defined(CONFIG_CMD_I2C) && CONFIG_IS_ENABLED(SYS_I2C_LEGACY) EXPORT_FUNC(i2c_write, int, i2c_write, uchar, uint, int , uchar * , int) EXPORT_FUNC(i2c_read, int, i2c_read, uchar, uint, int , uchar * , int) -- cgit v1.2.3 From 07588f4ad9b80e73726fd7ecb8e17e21785322a0 Mon Sep 17 00:00:00 2001 From: Rasmus Villemoes Date: Fri, 19 Sep 2025 12:10:02 +0200 Subject: exports.h: bump XF_VERSION There have been quite a few changes to _exports.h since the last update of XF_VERSION, also before the previous patches in this series. I doubt the mechanism is actually being used in practice, it is simply too fragile: Not only does the list of exported functions depend on .config, so with the same XF_VERSION the jump table entries could have different offsets. But getting to the jump table itself from gd to even call the ->get_version() is fragile, since offsetof(gd_t, jt) can, and does, change. For example, as recently as commit d9902107027 ("global_data: Remove jump table in SPL"). One really must build one's standalone app against the proper U-Boot version and config.h. But for good measure, do bump it now. Signed-off-by: Rasmus Villemoes Reviewed-by: Tom Rini --- include/exports.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/include/exports.h b/include/exports.h index bcf170dca87..12abb35643e 100644 --- a/include/exports.h +++ b/include/exports.h @@ -40,7 +40,7 @@ struct jt_funcs { #undef EXPORT_FUNC }; -#define XF_VERSION 9 +#define XF_VERSION 10 #if defined(CONFIG_X86) extern gd_t *global_data; -- cgit v1.2.3 From c8a74db0cd2ae90720e81b55795cf2809762a995 Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Wed, 17 Sep 2025 09:54:06 +0200 Subject: arm: Change SYS_INIT_SP_BSS_OFFSET from int to hex The most of OFFSET values are in hex instead of int which is easier for layout description. Signed-off-by: Michal Simek --- arch/arm/Kconfig | 4 ++-- configs/amd_versal2_virt_defconfig | 2 +- configs/qcom_defconfig | 2 +- configs/qcom_ipq5424_mmc_defconfig | 2 +- configs/qcom_ipq9574_mmc_defconfig | 2 +- configs/renesas_rzg2l_smarc_defconfig | 2 +- configs/xilinx_versal_net_virt_defconfig | 2 +- configs/xilinx_versal_virt_defconfig | 2 +- 8 files changed, 9 insertions(+), 9 deletions(-) diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 625d2e995d2..4c2885fc981 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -68,10 +68,10 @@ config INIT_SP_RELATIVE SYS_INIT_SP_BSS_OFFSET. config SYS_INIT_SP_BSS_OFFSET - int "Early stack offset from the .bss base address" + hex "Early stack offset from the .bss base address" depends on ARM64 depends on INIT_SP_RELATIVE - default 524288 + default 0x80000 help This option's value is the offset added to &_bss_start in order to calculate the stack pointer. This offset should be large enough so diff --git a/configs/amd_versal2_virt_defconfig b/configs/amd_versal2_virt_defconfig index 062cae70eb0..5791f0415c9 100644 --- a/configs/amd_versal2_virt_defconfig +++ b/configs/amd_versal2_virt_defconfig @@ -1,7 +1,7 @@ CONFIG_ARM=y CONFIG_COUNTER_FREQUENCY=100000000 CONFIG_POSITION_INDEPENDENT=y -CONFIG_SYS_INIT_SP_BSS_OFFSET=1572864 +CONFIG_SYS_INIT_SP_BSS_OFFSET=0x180000 CONFIG_ARCH_VERSAL2=y CONFIG_TEXT_BASE=0x40000000 CONFIG_SYS_MALLOC_F_LEN=0x100000 diff --git a/configs/qcom_defconfig b/configs/qcom_defconfig index 86d7de89e77..8d1269b4634 100644 --- a/configs/qcom_defconfig +++ b/configs/qcom_defconfig @@ -1,7 +1,7 @@ CONFIG_ARM=y CONFIG_SKIP_LOWLEVEL_INIT=y CONFIG_POSITION_INDEPENDENT=y -CONFIG_SYS_INIT_SP_BSS_OFFSET=1572864 +CONFIG_SYS_INIT_SP_BSS_OFFSET=0x180000 CONFIG_ARCH_SNAPDRAGON=y CONFIG_NR_DRAM_BANKS=24 CONFIG_DEFAULT_DEVICE_TREE="qcom/sdm845-db845c" diff --git a/configs/qcom_ipq5424_mmc_defconfig b/configs/qcom_ipq5424_mmc_defconfig index e508c0cf508..3c03e367b7d 100644 --- a/configs/qcom_ipq5424_mmc_defconfig +++ b/configs/qcom_ipq5424_mmc_defconfig @@ -1,7 +1,7 @@ CONFIG_ARM=y CONFIG_SKIP_LOWLEVEL_INIT=y CONFIG_POSITION_INDEPENDENT=y -CONFIG_SYS_INIT_SP_BSS_OFFSET=1572864 +CONFIG_SYS_INIT_SP_BSS_OFFSET=0x180000 CONFIG_ARCH_SNAPDRAGON=y CONFIG_TEXT_BASE=0x8a380000 CONFIG_NR_DRAM_BANKS=24 diff --git a/configs/qcom_ipq9574_mmc_defconfig b/configs/qcom_ipq9574_mmc_defconfig index 720220dc98a..b45ef504155 100644 --- a/configs/qcom_ipq9574_mmc_defconfig +++ b/configs/qcom_ipq9574_mmc_defconfig @@ -1,7 +1,7 @@ CONFIG_ARM=y CONFIG_SKIP_LOWLEVEL_INIT=y CONFIG_POSITION_INDEPENDENT=y -CONFIG_SYS_INIT_SP_BSS_OFFSET=1572864 +CONFIG_SYS_INIT_SP_BSS_OFFSET=0x180000 CONFIG_ARCH_SNAPDRAGON=y CONFIG_TEXT_BASE=0x4A240000 CONFIG_NR_DRAM_BANKS=24 diff --git a/configs/renesas_rzg2l_smarc_defconfig b/configs/renesas_rzg2l_smarc_defconfig index 401e237a816..e5b560cf237 100644 --- a/configs/renesas_rzg2l_smarc_defconfig +++ b/configs/renesas_rzg2l_smarc_defconfig @@ -1,6 +1,6 @@ CONFIG_ARM=y CONFIG_COUNTER_FREQUENCY=16666666 -CONFIG_SYS_INIT_SP_BSS_OFFSET=1048576 +CONFIG_SYS_INIT_SP_BSS_OFFSET=0x100000 CONFIG_ARCH_CPU_INIT=y CONFIG_ARCH_RENESAS=y CONFIG_SYS_MALLOC_LEN=0x4000000 diff --git a/configs/xilinx_versal_net_virt_defconfig b/configs/xilinx_versal_net_virt_defconfig index c13bdb2e545..13d89c47339 100644 --- a/configs/xilinx_versal_net_virt_defconfig +++ b/configs/xilinx_versal_net_virt_defconfig @@ -1,7 +1,7 @@ CONFIG_ARM=y CONFIG_COUNTER_FREQUENCY=100000000 CONFIG_POSITION_INDEPENDENT=y -CONFIG_SYS_INIT_SP_BSS_OFFSET=1572864 +CONFIG_SYS_INIT_SP_BSS_OFFSET=0x180000 CONFIG_ARCH_VERSAL_NET=y CONFIG_TEXT_BASE=0x8000000 CONFIG_SYS_MALLOC_F_LEN=0x100000 diff --git a/configs/xilinx_versal_virt_defconfig b/configs/xilinx_versal_virt_defconfig index d8f4b884e76..52142bcc7b2 100644 --- a/configs/xilinx_versal_virt_defconfig +++ b/configs/xilinx_versal_virt_defconfig @@ -1,7 +1,7 @@ CONFIG_ARM=y CONFIG_COUNTER_FREQUENCY=100000000 CONFIG_POSITION_INDEPENDENT=y -CONFIG_SYS_INIT_SP_BSS_OFFSET=1572864 +CONFIG_SYS_INIT_SP_BSS_OFFSET=0x180000 CONFIG_ARCH_VERSAL=y CONFIG_TEXT_BASE=0x8000000 CONFIG_SYS_MALLOC_LEN=0x4000000 -- cgit v1.2.3 From 40888b1e4cc81404493a2df263af1ca20ccd08d6 Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Tue, 16 Sep 2025 10:14:45 -0600 Subject: scripts: checkpatch.pl: Extend some checks to "env" files In order for the U-Boot specific tests we've added (along with the long line test) to be run on ".env" files as well, we need to update the line in the process function that starts to limit the file extensions that we test on. Signed-off-by: Tom Rini --- scripts/checkpatch.pl | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/scripts/checkpatch.pl b/scripts/checkpatch.pl index 414019c5b89..763287e02b1 100755 --- a/scripts/checkpatch.pl +++ b/scripts/checkpatch.pl @@ -3791,7 +3791,7 @@ sub process { } # check we are in a valid source file if not then ignore this hunk - next if ($realfile !~ /\.(h|c|s|S|sh|dtsi|dts)$/); + next if ($realfile !~ /\.(h|c|s|S|sh|dtsi|dts|env)$/); # check for using SPDX-License-Identifier on the wrong line number if ($realline != $checklicenseline && -- cgit v1.2.3 From 7c0f1c46f885db62c86d035814c1bb282af43c8c Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Thu, 18 Sep 2025 18:49:19 +0200 Subject: arm64: Add MIDR entry for Cortex-A720 Add MIDR entry for Cortex-A720 core. Signed-off-by: Marek Vasut --- arch/arm/include/asm/armv8/cpu.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm/include/asm/armv8/cpu.h b/arch/arm/include/asm/armv8/cpu.h index e906fdf1bf1..d8f0e16dadd 100644 --- a/arch/arm/include/asm/armv8/cpu.h +++ b/arch/arm/include/asm/armv8/cpu.h @@ -11,6 +11,7 @@ #define MIDR_PARTNUM_CORTEX_A73 0xD09 #define MIDR_PARTNUM_CORTEX_A75 0xD0A #define MIDR_PARTNUM_CORTEX_A76 0xD0B +#define MIDR_PARTNUM_CORTEX_A720 0xD81 #define MIDR_PARTNUM_SHIFT 0x4 #define MIDR_PARTNUM_MASK (0xFFF << MIDR_PARTNUM_SHIFT) @@ -40,3 +41,4 @@ is_cortex_a(72) is_cortex_a(73) is_cortex_a(75) is_cortex_a(76) +is_cortex_a(720) -- cgit v1.2.3 From b6d9aa6aafc0ae2f551de301e1f371c4814cef68 Mon Sep 17 00:00:00 2001 From: Vishnu Singh Date: Tue, 16 Sep 2025 12:55:15 +0530 Subject: bootstage: stash boot records to reserved mem before kernel handoff MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit U-Boot now stashes its bootstage buffer into a reserved memory region whenever CONFIG_BOOTSTAGE_STASH is enabled, just before exiting to the kernel. This allows a post boot parser to read a unified timeline (SPL→U-Boot→Kernel→MCU/DSP) directly from DDR, enabling standardized and repeatable boot-time profiling across releases and SoCs. Change summary: Call bootstage_stash_default() in announce_and_cleanup() when CONFIG_BOOTSTAGE_STASH is set. Reference boot-time parser utility: https://github.com/v-singh1/boot-time-parser Sample boot time report: +--------------------------------------------------------------------+ am62xx-evm Boot Time Report +--------------------------------------------------------------------+ Device Power On : 0 ms SPL Time : 843 ms U-Boot Time : 2173 ms Kernel handoff time : 462 ms Kernel Time : 2522 ms Total Boot Time : 6000 ms +--------------------------------------------------------------------+ +--------------------------------------------------------------------+ Bootloader and Kernel Boot Records +--------------------------------------------------------------------+ BOOTSTAGE_AWAKE = 0 ms (+ 0 ms) BOOTSTAGE_START_UBOOT_F = 843 ms (+ 0 ms) BOOTSTAGE_ACCUM_DM_F = 843 ms (+ 0 ms) BOOTSTAGE_START_UBOOT_R = 1951 ms (+1108 ms) BOOTSTAGE_ACCUM_DM_R = 1951 ms (+ 0 ms) BOOTSTAGE_NET_ETH_START = 2032 ms (+ 81 ms) BOOTSTAGE_NET_ETH_INIT = 2053 ms (+ 21 ms) BOOTSTAGE_MAIN_LOOP = 2055 ms (+ 2 ms) BOOTSTAGE_START_MCU = 2661 ms (+606 ms) BOOTSTAGE_BOOTM_START = 2959 ms (+298 ms) BOOTSTAGE_RUN_OS = 3016 ms (+ 57 ms) BOOTSTAGE_BOOTM_HANDOFF = 3016 ms (+ 0 ms) BOOTSTAGE_KERNEL_START = 3478 ms (+462 ms) BOOTSTAGE_KERNEL_END = 6000 ms (+2522 ms) +--------------------------------------------------------------------+ +--------------------------------------------------------------------+ MCU Boot Records +--------------------------------------------------------------------+ MCU_AWAKE = 2661 ms (+ 0 ms) BOARD_PERIPHERALS_INIT = 2661 ms (+ 0 ms) MAIN_TASK_CREATE = 2661 ms (+ 0 ms) FIRST_TASK = 2662 ms (+ 1 ms) DRIVERS_OPEN = 2662 ms (+ 0 ms) BOARD_DRIVERS_OPEN = 2662 ms (+ 0 ms) IPC_SYNC_FOR_LINUX = 6636 ms (+3974 ms) IPC_REGISTER_CLIENT = 6636 ms (+ 0 ms) IPC_SUSPEND_TASK = 6636 ms (+ 0 ms) IPC_RECEIVE_TASK = 6636 ms (+ 0 ms) IPC_SYNC_ALL = 6787 ms (+151 ms) +--------------------------------------------------------------------+ Signed-off-by: Vishnu Singh --- arch/arm/lib/bootm.c | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/lib/bootm.c b/arch/arm/lib/bootm.c index ca4cec61f22..b874aa252c6 100644 --- a/arch/arm/lib/bootm.c +++ b/arch/arm/lib/bootm.c @@ -57,6 +57,7 @@ static void announce_and_cleanup(int fake) #ifdef CONFIG_BOOTSTAGE_FDT bootstage_fdt_add_report(); #endif + bootstage_stash_default(); #ifdef CONFIG_BOOTSTAGE_REPORT bootstage_report(); #endif -- cgit v1.2.3 From 2767386806c254820ea22a812bb02e5405495a29 Mon Sep 17 00:00:00 2001 From: Debbie Horsfall Date: Wed, 17 Sep 2025 17:22:21 +0100 Subject: vexpress64: Set the DM_RNG property Enable the DM_RNG virtio random number generator driver in order to consume entropy within U-Boot. This allows U-Boot to inject entropy to the kernel via UEFI, so the kernel can use that early, for instance for address layout randomisation, or when the kernel does not provide an entropy driver itself. Signed-off-by: Debbie Horsfall Reviewed-by: Andre Przywara --- board/armltd/vexpress64/Kconfig | 2 ++ 1 file changed, 2 insertions(+) diff --git a/board/armltd/vexpress64/Kconfig b/board/armltd/vexpress64/Kconfig index 7e8709444fe..610ab0ac37d 100644 --- a/board/armltd/vexpress64/Kconfig +++ b/board/armltd/vexpress64/Kconfig @@ -21,6 +21,8 @@ config VEXPRESS64_BASE_MODEL imply EFI_SET_TIME if DM_RTC select LINUX_KERNEL_IMAGE_HEADER select POSITION_INDEPENDENT + imply DM_RNG + imply RNG_ARM_RNDR choice prompt "VExpress64 board variant" -- cgit v1.2.3 From 1f3f1e090a2695e0b17cbf9dc50ccb59d100458f Mon Sep 17 00:00:00 2001 From: Debbie Horsfall Date: Wed, 17 Sep 2025 17:22:22 +0100 Subject: arm: vexpress64: Enable SYSRESET and SYSRESET_PSCI Select SYSRESET on Vexpress64 to enable system reset to support other features, such as capsule-on-disk. Select SYSRESET_PSCI if PSCI is inferred from the firmware (via ARM_PSCI_FW). Select ARM_SMCCC for Vexpress64 boards which in turn selects ARM_PSCI_FW. The sysreset uclass unconditionally implements a reset_cpu() function. Remove the empty reset_cpu() in vexpress64 board code. Signed-off-by: Debbie Horsfall --- arch/arm/Kconfig | 2 ++ board/armltd/vexpress64/Kconfig | 2 ++ board/armltd/vexpress64/vexpress64.c | 5 ----- 3 files changed, 4 insertions(+), 5 deletions(-) diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 16db046f4b8..0a1bd6958fe 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -1418,6 +1418,8 @@ config ARCH_VEXPRESS64 select MTD_NOR_FLASH if MTD select FLASH_CFI_DRIVER if MTD select ENV_IS_IN_FLASH if MTD + select SYSRESET + select SYSRESET_PSCI if ARM_PSCI_FW imply DISTRO_DEFAULTS config TARGET_CORSTONE1000 diff --git a/board/armltd/vexpress64/Kconfig b/board/armltd/vexpress64/Kconfig index 610ab0ac37d..9ef3fa1b379 100644 --- a/board/armltd/vexpress64/Kconfig +++ b/board/armltd/vexpress64/Kconfig @@ -23,6 +23,7 @@ config VEXPRESS64_BASE_MODEL select POSITION_INDEPENDENT imply DM_RNG imply RNG_ARM_RNDR + select ARM_SMCCC choice prompt "VExpress64 board variant" @@ -48,6 +49,7 @@ config TARGET_VEXPRESS64_JUNO select USB_EHCI_GENERIC if USB select USB_OHCI_HCD if USB select USB_OHCI_GENERIC if USB + select ARM_SMCCC imply OF_HAS_PRIOR_STAGE endchoice diff --git a/board/armltd/vexpress64/vexpress64.c b/board/armltd/vexpress64/vexpress64.c index 0b75c1358f0..e8f1c2fe9fe 100644 --- a/board/armltd/vexpress64/vexpress64.c +++ b/board/armltd/vexpress64/vexpress64.c @@ -206,11 +206,6 @@ int board_fdt_blob_setup(void **fdtp) #endif #endif -/* Actual reset is done via PSCI. */ -void reset_cpu(void) -{ -} - /* * Board specific ethernet initialization routine. */ -- cgit v1.2.3 From 6578475a9669ea74b9e9e3df2b275309862cb27f Mon Sep 17 00:00:00 2001 From: Tony Dinh Date: Wed, 10 Sep 2025 14:56:03 -0700 Subject: doc: ext4fs: update documentation for Ext4 Write configuration Update documentation for how to configure Ext4 Write when using large partitions. Signed-off-by: Tony Dinh --- doc/README.ext4 | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/doc/README.ext4 b/doc/README.ext4 index 8ecd21eee3b..ca9f19953d2 100644 --- a/doc/README.ext4 +++ b/doc/README.ext4 @@ -40,6 +40,17 @@ Also relevant are the generic filesystem commands, selected by: This does not automatically enable EXT4 support for you, you still need to do that yourself. +Lastly, the current u-boot implementation for Ext4 write requires a lot +of memory to run successfully. The following enable support for +large Ext4 partitions: + + CONFIG_EXT4_MAX_JOURNAL_ENTRIES + CONFIG_SYS_MALLOC_LEN + +The number of journal entries and dynamic memory allocation are proportional +to the partition capacity. For example, an ext4 4TB HDD partition could +require approximately 500 entries and more than 128 MB heap space. + Some sample commands to test ext4 support: 1. Check that the commands can be seen in the output of U-Boot help: -- cgit v1.2.3 From 1998334d5afe2a036ba4a85b8ee35e46bdedb611 Mon Sep 17 00:00:00 2001 From: Tony Dinh Date: Sun, 14 Sep 2025 13:56:28 -0700 Subject: doc: usage: Add File System section and Ext4 documentation Create doc/usage/filesystems/ section. Convert doc/README.ext4 to rST format and move it to the new section. Update documentation to add configuration instruction for Ext4 Write when using large partitions. Note that this patch depends on this previous patch: https://patchwork.ozlabs.org/project/uboot/patch/20250910215702.15576-1-mibodhi@gmail.com/ Signed-off-by: Tony Dinh Reviewed-by: Anshul Dalal --- doc/README.ext4 | 94 ---------------------------- doc/usage/filesystems/ext4.rst | 137 +++++++++++++++++++++++++++++++++++++++++ doc/usage/index.rst | 8 +++ 3 files changed, 145 insertions(+), 94 deletions(-) delete mode 100644 doc/README.ext4 create mode 100644 doc/usage/filesystems/ext4.rst diff --git a/doc/README.ext4 b/doc/README.ext4 deleted file mode 100644 index ca9f19953d2..00000000000 --- a/doc/README.ext4 +++ /dev/null @@ -1,94 +0,0 @@ -U-Boot supports access of both ext2 and ext4 filesystems, either in read-only -mode or in read-write mode. - -First, to enable support for both ext4 (and, automatically, ext2 as well), -but without selecting the corresponding commands, enable one of the following: - - CONFIG_FS_EXT4 (for read-only) - CONFIG_EXT4_WRITE (for read-write) - -Next, to select the ext2-related commands: - - * ext2ls - * ext2load - -or ext4-related commands: - - * ext4size - * ext4ls - * ext4load - -use one or both of: - - CONFIG_CMD_EXT2 - CONFIG_CMD_EXT4 - -Selecting either of the above automatically selects CONFIG_FS_EXT4 if it -wasn't enabled already. - -In addition, to get the write access command "ext4write", enable: - - CONFIG_CMD_EXT4_WRITE - -which automatically selects CONFIG_EXT4_WRITE if it wasn't defined -already. - -Also relevant are the generic filesystem commands, selected by: - - CONFIG_CMD_FS_GENERIC - -This does not automatically enable EXT4 support for you, you still need -to do that yourself. - -Lastly, the current u-boot implementation for Ext4 write requires a lot -of memory to run successfully. The following enable support for -large Ext4 partitions: - - CONFIG_EXT4_MAX_JOURNAL_ENTRIES - CONFIG_SYS_MALLOC_LEN - -The number of journal entries and dynamic memory allocation are proportional -to the partition capacity. For example, an ext4 4TB HDD partition could -require approximately 500 entries and more than 128 MB heap space. - -Some sample commands to test ext4 support: - -1. Check that the commands can be seen in the output of U-Boot help: - - UBOOT #help - ... - ext4load- load binary file from a Ext4 file system - ext4ls - list files in a directory (default /) - ext4size - determine a file's size - ext4write- create a file in ext4 formatted partition - ... - -2. To list the files in an ext4-formatted partition, run: - - ext4ls [directory] - - For example: - UBOOT #ext4ls mmc 0:5 /usr/lib - -3. To read and load a file from an ext4-formatted partition to RAM, run: - - ext4load [addr] [filename] [bytes] - - For example: - UBOOT #ext4load mmc 2:2 0x30007fc0 uImage - -4. To write a file to an ext4-formatted partition. - - a) First load a file to RAM at a particular address for example 0x30007fc0. - Now execute ext4write command: - ext4write [filename] [Address] [sizebytes] - - For example: - UBOOT #ext4write mmc 2:2 /boot/uImage 0x30007fc0 6183120 - (here 6183120 is the size of the file to be written) - Note: Absolute path is required for the file to be written - -References : - -- ext4 implementation in Linux Kernel - -- Uboot existing ext2 load and ls implementation - -- Journaling block device JBD2 implementation in linux Kernel diff --git a/doc/usage/filesystems/ext4.rst b/doc/usage/filesystems/ext4.rst new file mode 100644 index 00000000000..c6cdaf57fac --- /dev/null +++ b/doc/usage/filesystems/ext4.rst @@ -0,0 +1,137 @@ +.. SPDX-License-Identifier: GPL-2.0+ + +Ext4 File System +================ + +Overview +-------- + +U-Boot supports access of both ext2 and ext4 filesystems, either in read-only +mode or in read-write mode. + +Configuration +------------- + +First, to enable support for both ext4 (and, automatically, ext2 as well), +but without selecting the corresponding commands, enable one of the following: + +:: + + CONFIG_FS_EXT4 (for read-only) + CONFIG_EXT4_WRITE (for read-write) + +Next, to select the ext2-related commands: + + * ext2ls + * ext2load + +or ext4-related commands: + + * ext4size + * ext4ls + * ext4load + +use one or both of: + +:: + + CONFIG_CMD_EXT2 + CONFIG_CMD_EXT4 + +Selecting either of the above automatically selects CONFIG_FS_EXT4 if it +wasn't enabled already. + +In addition, to get the write access command ``ext4write``, enable: + +:: + + CONFIG_CMD_EXT4_WRITE + +which automatically selects CONFIG_EXT4_WRITE if it wasn't defined +already. + +Also relevant are the generic filesystem commands, selected by: + +:: + + CONFIG_CMD_FS_GENERIC + +This does not automatically enable EXT4 support for you, you still need +to do that yourself. + +Lastly, the current u-boot implementation for Ext4 write requires a lot +of memory to run successfully. The following enable support for +large Ext4 partitions: + +:: + + CONFIG_EXT4_MAX_JOURNAL_ENTRIES + CONFIG_SYS_MALLOC_LEN + +The number of journal entries and dynamic memory allocation are proportional +to the partition capacity. For example, an ext4 4TB HDD partition could +require approximately 500 entries and more than 128 MB heap space. + +Examples +-------- + +Some sample commands to test ext4 support: + +1. Check that the ext4 commands can be seen in the output of U-Boot help: + +:: + + => help + ... + ext4load- load binary file from a Ext4 file system + ext4ls - list files in a directory (default /) + ext4size - determine a file's size + ext4write- create a file in ext4 formatted partition + ... + +2. The ``ext4ls`` command can be used to list the files in an ext4-formatted partition: + +:: + + ext4ls [directory] + +For example, to list files in ext4-formatted partition directory /usr/lib: + +:: + + => ext4ls mmc 0:5 /usr/lib + +3. The ``ext4load`` command can be used to read and load a file from an +ext4-formatted partition to RAM: + +:: + + ext4load [ [addr [filename [bytes [pos]]]]] + +For example, to load file /uImage from an ext4-formatted partition: + +:: + + => ext4load mmc 2:2 0x30007fc0 uImage + +4. The ``ext4write`` command can be used to write to an ext4 partition: + +:: + + ext4write [sizebytes] [file offset] + +For example, to write a file loaded at 0x8200000 of size 256 bytes to an +ext4-formatted partition with the filename ``/boot/sample_file.hex``: + +:: + + => ext4write mmc 2:2 0x82000000 /boot/sample_file.hex 0x100 + 256 bytes written in 138 ms (1000 Bytes/s) + + +References +---------- + + * ext4 implementation in Linux Kernel + * Uboot existing ext2 load and ls implementation + * Journaling block device JBD2 implementation in linux Kernel diff --git a/doc/usage/index.rst b/doc/usage/index.rst index 3a48521d5d5..4b0533c8e69 100644 --- a/doc/usage/index.rst +++ b/doc/usage/index.rst @@ -147,3 +147,11 @@ Booting OS os/plan9 os/vxworks + +File Systems +------------ + +.. toctree:: + :maxdepth: 1 + + filesystems/ext4 -- cgit v1.2.3 From f0e722def6c7b33f5918603e4f5f275d05cc4319 Mon Sep 17 00:00:00 2001 From: Naresh Kumar Ravulapalli Date: Fri, 8 Aug 2025 02:40:03 -0700 Subject: arch: arm: dts: agilex5: Disable cache allocation for reads In order to circumvent CCU NOC issue in Agilex5, it is recommended to disable cache allocation for reads. This prevents hang issues caused by CCP (Common Cache Pipe) Fill Done FIFO overflow. Signed-off-by: Naresh Kumar Ravulapalli Reviewed-by: Tien Fong Chee --- arch/arm/dts/socfpga_agilex5-u-boot.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm/dts/socfpga_agilex5-u-boot.dtsi b/arch/arm/dts/socfpga_agilex5-u-boot.dtsi index 402f0bec173..d51a9e2ff7f 100644 --- a/arch/arm/dts/socfpga_agilex5-u-boot.dtsi +++ b/arch/arm/dts/socfpga_agilex5-u-boot.dtsi @@ -209,7 +209,7 @@ /* DMIUSMCTCR */ <0x00000300 0x00000001 0x00000003>, <0x00000300 0x00000003 0x00000003>, - <0x00000308 0x00000004 0x0000001F>; + <0x00000308 0x0000000C 0x0000001F>; bootph-all; }; @@ -220,7 +220,7 @@ /* DMIUSMCTCR */ <0x00000300 0x00000001 0x00000003>, <0x00000300 0x00000003 0x00000003>, - <0x00000308 0x00000004 0x0000001F>; + <0x00000308 0x0000000C 0x0000001F>; bootph-all; }; }; -- cgit v1.2.3 From f6dbe41638be6de0071d84073483dc9aaefbdadd Mon Sep 17 00:00:00 2001 From: Naresh Kumar Ravulapalli Date: Mon, 18 Aug 2025 21:17:44 -0700 Subject: arch: arm: dts: stratix10: Add NAND IP to base dtsi Add NAND node to the base stratix10 dtsi file. Signed-off-by: Naresh Kumar Ravulapalli Reviewed-by: Tien Fong Chee --- arch/arm/dts/socfpga_stratix10.dtsi | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/arch/arm/dts/socfpga_stratix10.dtsi b/arch/arm/dts/socfpga_stratix10.dtsi index eb82d663204..ea80d1bed15 100644 --- a/arch/arm/dts/socfpga_stratix10.dtsi +++ b/arch/arm/dts/socfpga_stratix10.dtsi @@ -232,6 +232,18 @@ status = "disabled"; }; + nand: nand@ffb90000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "altr,socfpga-denali-nand"; + reg = <0xffb90000 0x10000>, + <0xffb80000 0x1000>; + reg-names = "nand_data", "denali_reg"; + interrupts = <0 97 4>; + resets = <&rst NAND_RESET>, <&rst NAND_OCP_RESET>; + status = "disabled"; + }; + ocram: sram@ffe00000 { compatible = "mmio-sram"; reg = <0xffe00000 0x100000>; -- cgit v1.2.3 From 27e13c9c8d07e6dc626a7f553e7690c6fe4e1cd0 Mon Sep 17 00:00:00 2001 From: Naresh Kumar Ravulapalli Date: Mon, 18 Aug 2025 21:25:55 -0700 Subject: arch: arm: socfpga: Remove speed and mode from flash probe Change is to allow the user to choose speed and mode values from dts or the default ones. Signed-off-by: Naresh Kumar Ravulapalli Reviewed-by: Tien Fong Chee --- arch/arm/mach-socfpga/misc_arria10.c | 3 --- 1 file changed, 3 deletions(-) diff --git a/arch/arm/mach-socfpga/misc_arria10.c b/arch/arm/mach-socfpga/misc_arria10.c index c442af02888..7e0f3875b7c 100644 --- a/arch/arm/mach-socfpga/misc_arria10.c +++ b/arch/arm/mach-socfpga/misc_arria10.c @@ -214,10 +214,7 @@ int qspi_flash_software_reset(void) /* Get the flash info */ ret = spi_flash_probe_bus_cs(CONFIG_SF_DEFAULT_BUS, CONFIG_SF_DEFAULT_CS, - CONFIG_SF_DEFAULT_SPEED, - CONFIG_SF_DEFAULT_MODE, &flash); - if (ret) { debug("Failed to initialize SPI flash at "); debug("%u:%u (error %d)\n", CONFIG_SF_DEFAULT_BUS, -- cgit v1.2.3 From 26ffc37787e6107878ac2ec9d46a8c01bb731e89 Mon Sep 17 00:00:00 2001 From: Naresh Kumar Ravulapalli Date: Mon, 18 Aug 2025 21:16:04 -0700 Subject: arm: dts: socfpga: Enable driver model for watchdog timer All SoCFPGA platforms are switching to CONFIG_WDT (driver model for watchdog timer drivers) from CONFIG_HW_WATCHDOG. Status of watchdog is enabled to assist with this switching. Signed-off-by: Naresh Kumar Ravulapalli Reviewed-by: Tien Fong Chee --- arch/arm/dts/socfpga_stratix10_socdk.dts | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm/dts/socfpga_stratix10_socdk.dts b/arch/arm/dts/socfpga_stratix10_socdk.dts index e6d8fe6a907..864f4093ef8 100644 --- a/arch/arm/dts/socfpga_stratix10_socdk.dts +++ b/arch/arm/dts/socfpga_stratix10_socdk.dts @@ -137,3 +137,7 @@ &usb0 { status = "okay"; }; + +&watchdog0 { + status = "okay"; +}; -- cgit v1.2.3 From 2a7771166ea903726c8d9d919ddcd5526c882459 Mon Sep 17 00:00:00 2001 From: Naresh Kumar Ravulapalli Date: Fri, 8 Aug 2025 02:30:41 -0700 Subject: configs: Simplify Agilex7 VAB defconfig To ensure unintentional bugs occurring because of config changes in master defconfig and its VAB variants, VAB defconfig files now include the master defconfig and enable config values specific to VAB functionality only. Signed-off-by: Naresh Kumar Ravulapalli Reviewed-by: Tien Fong Chee --- configs/socfpga_agilex_vab_defconfig | 94 +----------------------------------- 1 file changed, 2 insertions(+), 92 deletions(-) diff --git a/configs/socfpga_agilex_vab_defconfig b/configs/socfpga_agilex_vab_defconfig index edce692ecd1..4607dc73343 100644 --- a/configs/socfpga_agilex_vab_defconfig +++ b/configs/socfpga_agilex_vab_defconfig @@ -1,93 +1,3 @@ -CONFIG_ARM=y -CONFIG_COUNTER_FREQUENCY=400000000 -CONFIG_ARCH_SOCFPGA=y -CONFIG_TEXT_BASE=0x200000 -CONFIG_SYS_MALLOC_LEN=0x500000 -CONFIG_NR_DRAM_BANKS=2 -CONFIG_SPL_LDSCRIPT="arch/arm/mach-socfpga/u-boot-spl-soc64.lds" -CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y -CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x300000 -CONFIG_SF_DEFAULT_MODE=0x2003 -CONFIG_ENV_SIZE=0x1000 -CONFIG_ENV_OFFSET=0x200 -CONFIG_DM_GPIO=y -CONFIG_DEFAULT_DEVICE_TREE="intel/socfpga_agilex_socdk" -CONFIG_DM_RESET=y -CONFIG_SPL_STACK=0xffe3f000 -CONFIG_SPL_TEXT_BASE=0xFFE00000 -CONFIG_SPL_HAS_BSS_LINKER_SECTION=y -CONFIG_SPL_BSS_START_ADDR=0x3ff00000 -CONFIG_SPL_BSS_MAX_SIZE=0x100000 -CONFIG_SYS_BOOTM_LEN=0x2000000 -CONFIG_SYS_LOAD_ADDR=0x02000000 +#include + CONFIG_SOCFPGA_SECURE_VAB_AUTH=y -CONFIG_TARGET_SOCFPGA_AGILEX_SOCDK=y -CONFIG_IDENT_STRING="socfpga_agilex" -CONFIG_SPL_FS_FAT=y -CONFIG_REMAKE_ELF=y -CONFIG_FIT=y -CONFIG_SPL_FIT_SIGNATURE=y -CONFIG_SPL_LOAD_FIT=y -CONFIG_SPL_LOAD_FIT_ADDRESS=0x02000000 -CONFIG_BOOTDELAY=5 -CONFIG_USE_BOOTARGS=y -CONFIG_BOOTARGS="earlycon" -CONFIG_USE_BOOTCOMMAND=y -CONFIG_BOOTCOMMAND="run fatscript; run mmcfitload; run mmcfitboot" -CONFIG_SYS_PBSIZE=2082 -CONFIG_SPL_MAX_SIZE=0x40000 -# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set -CONFIG_SPL_HAVE_INIT_STACK=y -CONFIG_SPL_SYS_MALLOC=y -CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y -CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x3fa00000 -CONFIG_SPL_SYS_MALLOC_SIZE=0x500000 -CONFIG_SPL_CACHE=y -CONFIG_SPL_SPI_LOAD=y -CONFIG_SYS_SPI_U_BOOT_OFFS=0x02000000 -CONFIG_SPL_ATF=y -CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y -CONFIG_SPL_TARGET="spl/u-boot-spl-dtb.hex" -CONFIG_HUSH_PARSER=y -CONFIG_SYS_PROMPT="SOCFPGA_AGILEX # " -CONFIG_CMD_MEMTEST=y -CONFIG_CMD_GPIO=y -CONFIG_CMD_I2C=y -CONFIG_CMD_MMC=y -CONFIG_CMD_SPI=y -CONFIG_CMD_USB=y -CONFIG_CMD_DHCP=y -CONFIG_CMD_MII=y -CONFIG_CMD_PING=y -CONFIG_CMD_CACHE=y -CONFIG_CMD_EXT4=y -CONFIG_CMD_FAT=y -CONFIG_CMD_FS_GENERIC=y -CONFIG_OF_UPSTREAM=y -CONFIG_ENV_IS_IN_MMC=y -CONFIG_NET_RANDOM_ETHADDR=y -CONFIG_SPL_DM_SEQ_ALIAS=y -CONFIG_SPL_ALTERA_SDRAM=y -CONFIG_DWAPB_GPIO=y -CONFIG_DM_I2C=y -CONFIG_SYS_I2C_DW=y -CONFIG_SYS_MMC_MAX_BLK_COUNT=256 -CONFIG_MMC_DW=y -CONFIG_SPI_FLASH_SPANSION=y -CONFIG_SPI_FLASH_STMICRO=y -CONFIG_PHY_MICREL=y -CONFIG_PHY_MICREL_KSZ90X1=y -CONFIG_ETH_DESIGNWARE=y -CONFIG_MII=y -CONFIG_SYS_NS16550_MEM32=y -CONFIG_SPI=y -CONFIG_CADENCE_QSPI=y -CONFIG_DESIGNWARE_SPI=y -CONFIG_USB=y -CONFIG_USB_DWC2=y -CONFIG_USB_STORAGE=y -CONFIG_DESIGNWARE_WATCHDOG=y -CONFIG_WDT=y -# CONFIG_SPL_USE_TINY_PRINTF is not set -CONFIG_PANIC_HANG=y -CONFIG_SPL_CRC32=y -- cgit v1.2.3 From 65261e83f3b1fd5e17ff361d167ae035e2954502 Mon Sep 17 00:00:00 2001 From: Naresh Kumar Ravulapalli Date: Mon, 18 Aug 2025 21:24:04 -0700 Subject: configs: socfpga: Add CRC32 support CRC32 support for SoC64 devices is added. Signed-off-by: Naresh Kumar Ravulapalli Reviewed-by: Tien Fong Chee --- configs/socfpga_agilex_defconfig | 1 + configs/socfpga_n5x_defconfig | 1 + configs/socfpga_stratix10_defconfig | 1 + 3 files changed, 3 insertions(+) diff --git a/configs/socfpga_agilex_defconfig b/configs/socfpga_agilex_defconfig index 1c3664bc0d7..44c12db08b5 100644 --- a/configs/socfpga_agilex_defconfig +++ b/configs/socfpga_agilex_defconfig @@ -38,6 +38,7 @@ CONFIG_SPL_SYS_MALLOC=y CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x3fa00000 CONFIG_SPL_SYS_MALLOC_SIZE=0x500000 +CONFIG_SPL_CRC32=y CONFIG_SPL_CACHE=y CONFIG_SPL_MTD=y CONFIG_SPL_SPI_FLASH_MTD=y diff --git a/configs/socfpga_n5x_defconfig b/configs/socfpga_n5x_defconfig index 879556614f6..d501fcddf3d 100644 --- a/configs/socfpga_n5x_defconfig +++ b/configs/socfpga_n5x_defconfig @@ -37,6 +37,7 @@ CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x3fa00000 CONFIG_SPL_SYS_MALLOC_SIZE=0x500000 CONFIG_SPL_CACHE=y +CONFIG_SPL_CRC32=y CONFIG_SPL_SPI_LOAD=y CONFIG_SYS_SPI_U_BOOT_OFFS=0x3c00000 CONFIG_SPL_TARGET="spl/u-boot-spl-dtb.hex" diff --git a/configs/socfpga_stratix10_defconfig b/configs/socfpga_stratix10_defconfig index 90134d8f3f3..fe191d09714 100644 --- a/configs/socfpga_stratix10_defconfig +++ b/configs/socfpga_stratix10_defconfig @@ -41,6 +41,7 @@ CONFIG_SPL_SYS_MALLOC=y CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x3fa00000 CONFIG_SPL_SYS_MALLOC_SIZE=0x500000 +CONFIG_SPL_CRC32=y CONFIG_SPL_SPI_LOAD=y CONFIG_SYS_SPI_U_BOOT_OFFS=0x3C00000 CONFIG_SPL_TARGET="spl/u-boot-spl-dtb.hex" -- cgit v1.2.3 From 3d084d91eda63fde4a159bc866816c9c6b1ae6ce Mon Sep 17 00:00:00 2001 From: Naresh Kumar Ravulapalli Date: Mon, 18 Aug 2025 21:34:40 -0700 Subject: configs: socfpga: Remove SYS_BOOTM_LEN from N5X VAB config Remove the current CONFIG_SYS_BOOTM_LEN in N5X VAB defconfig. Previously, the size was set to 32MB, but due to larger kernel image, 64MB size is required. This 64MB configuration has been set as default in the Kconfig. Signed-off-by: Naresh Kumar Ravulapalli Reviewed-by: Tien Fong Chee --- configs/socfpga_n5x_vab_defconfig | 1 - 1 file changed, 1 deletion(-) diff --git a/configs/socfpga_n5x_vab_defconfig b/configs/socfpga_n5x_vab_defconfig index 5d51c4786c0..a4798e2f953 100644 --- a/configs/socfpga_n5x_vab_defconfig +++ b/configs/socfpga_n5x_vab_defconfig @@ -18,7 +18,6 @@ CONFIG_SPL_TEXT_BASE=0xFFE00000 CONFIG_SPL_HAS_BSS_LINKER_SECTION=y CONFIG_SPL_BSS_START_ADDR=0x3ff00000 CONFIG_SPL_BSS_MAX_SIZE=0x100000 -CONFIG_SYS_BOOTM_LEN=0x2000000 CONFIG_SOCFPGA_SECURE_VAB_AUTH=y CONFIG_TARGET_SOCFPGA_N5X_SOCDK=y CONFIG_IDENT_STRING="socfpga_n5x" -- cgit v1.2.3 From 5d2ef97c66f0a432c859cfdf64ef696017619ad6 Mon Sep 17 00:00:00 2001 From: Naresh Kumar Ravulapalli Date: Fri, 8 Aug 2025 02:36:59 -0700 Subject: drivers: ddr: altera: Check IOSSM mailbox compatibility Compatibility check of IOSSM mailbox with U-Boot is performed by verifying the mailbox specification version. If check fails, appropriate error message is displayed. Signed-off-by: Naresh Kumar Ravulapalli Reviewed-by: Tien Fong Chee --- drivers/ddr/altera/iossm_mailbox.c | 24 ++++++++++++++++++++++++ 1 file changed, 24 insertions(+) diff --git a/drivers/ddr/altera/iossm_mailbox.c b/drivers/ddr/altera/iossm_mailbox.c index 21f94959a04..2a2f86a650e 100644 --- a/drivers/ddr/altera/iossm_mailbox.c +++ b/drivers/ddr/altera/iossm_mailbox.c @@ -38,6 +38,8 @@ #define IOSSM_STATUS_CMD_RESPONSE_ERROR(n) FIELD_GET(IOSSM_STATUS_CMD_RESPONSE_ERROR_MASK, n) #define IOSSM_STATUS_GENERAL_ERROR_MASK GENMASK(4, 1) #define IOSSM_STATUS_GENERAL_ERROR(n) FIELD_GET(IOSSM_STATUS_GENERAL_ERROR_MASK, n) +#define IOSSM_MAILBOX_SPEC_VERSION_MASK GENMASK(2, 0) +#define IOSSM_MAILBOX_SPEC_VERSION(n) FIELD_GET(IOSSM_MAILBOX_SPEC_VERSION_MASK, n) /* Offset of Mailbox Read-only Registers */ #define IOSSM_MAILBOX_HEADER_OFFSET 0x0 @@ -383,6 +385,23 @@ err: return ret; } +static bool is_mailbox_spec_compatible(struct io96b_info *io96b_ctrl) +{ + u32 mailbox_header; + u8 mailbox_spec_ver; + + mailbox_header = readl(io96b_ctrl->io96b[0].io96b_csr_addr + + IOSSM_MAILBOX_HEADER_OFFSET); + mailbox_spec_ver = IOSSM_MAILBOX_SPEC_VERSION(mailbox_header); + printf("%s: IOSSM mailbox version: %d\n", __func__, mailbox_spec_ver); + + /* for now there are two mailbox spec versions, 0 and 1; only version 1 is compatible */ + if (!mailbox_spec_ver) + return false; + + return true; +} + /* * Initial function to be called to set memory interface IP type and instance ID * IP type and instance ID need to be determined before sending mailbox command @@ -392,6 +411,11 @@ void io96b_mb_init(struct io96b_info *io96b_ctrl) int i, j; u32 mem_intf_info_0, mem_intf_info_1; + if (!is_mailbox_spec_compatible(io96b_ctrl)) { + printf("DDR: Failed to get compatible mailbox version\n"); + hang(); + } + debug("%s: num_instance %d\n", __func__, io96b_ctrl->num_instance); for (i = 0; i < io96b_ctrl->num_instance; i++) { -- cgit v1.2.3 From 63ef1c7a7391e7440bdfbffedd2cc5d9007707cd Mon Sep 17 00:00:00 2001 From: Naresh Kumar Ravulapalli Date: Fri, 8 Aug 2025 02:42:42 -0700 Subject: drivers: ddr: altera: Correct DDR calibration status check Bit 3 of the seq2core register is no longer set to indicate calibration completion. Instead, added polling of the seq2core register until it reads 0b00000111, signaling that the Nios processor has started the calibration process. Signed-off-by: Naresh Kumar Ravulapalli Reviewed-by: Tien Fong Chee --- drivers/ddr/altera/sdram_soc64.c | 6 +++--- drivers/ddr/altera/sdram_soc64.h | 2 +- 2 files changed, 4 insertions(+), 4 deletions(-) diff --git a/drivers/ddr/altera/sdram_soc64.c b/drivers/ddr/altera/sdram_soc64.c index f8fc92060db..2d0093c591c 100644 --- a/drivers/ddr/altera/sdram_soc64.c +++ b/drivers/ddr/altera/sdram_soc64.c @@ -85,11 +85,11 @@ int emif_reset(struct altera_sdram_plat *plat) debug("DDR: Triggerring emif reset\n"); hmc_ecc_writel(plat, DDR_HMC_CORE2SEQ_INT_REQ, RSTHANDSHAKECTRL); - /* if seq2core[3] = 0, we are good */ + /* if seq2core[2:0] = 0b0000_0111, we are good */ ret = wait_for_bit_le32((const void *)(plat->hmc + RSTHANDSHAKESTAT), - DDR_HMC_SEQ2CORE_INT_RESP_MASK, - false, 1000, false); + DDR_HMC_SEQ2CORE_INT_REQ_ACK_MASK, + true, 1000, false); if (ret) { printf("DDR: failed to get ack from EMIF\n"); return ret; diff --git a/drivers/ddr/altera/sdram_soc64.h b/drivers/ddr/altera/sdram_soc64.h index 6031cef560e..6fe0653922c 100644 --- a/drivers/ddr/altera/sdram_soc64.h +++ b/drivers/ddr/altera/sdram_soc64.h @@ -77,7 +77,7 @@ struct altera_sdram_plat { #define DDR_HMC_INTMODE_INTMODE_SET_MSK BIT(0) #define DDR_HMC_RSTHANDSHAKE_MASK 0x0000000f #define DDR_HMC_CORE2SEQ_INT_REQ 0x0000000f -#define DDR_HMC_SEQ2CORE_INT_RESP_MASK BIT(3) +#define DDR_HMC_SEQ2CORE_INT_REQ_ACK_MASK GENMASK(2, 0) #define DDR_HMC_HPSINTFCSEL_ENABLE_MASK 0x001f1f1f #define DDR_HMC_ERRINTEN_INTMASK \ -- cgit v1.2.3 From fb7aa75561b7d05c37dfc9f3d7f73d1838622517 Mon Sep 17 00:00:00 2001 From: Alif Zakuan Yuslaimi Date: Thu, 28 Aug 2025 20:42:59 -0700 Subject: arm: socfpga: Define Use FPGA switch handoff section size for Agilex5 Agilex5 FPGA switch section in the handoff data is larger by 32 bytes than the default value as these extra sections contains I3C0 and I3C1 register offsets and values with 4 bytes each. This requires 4 more times of reading the FPGA switch section of the handoff data to fully populate the handoff data table in the memory during runtime. Signed-off-by: Alif Zakuan Yuslaimi Reviewed-by: Tien Fong Chee --- arch/arm/mach-socfpga/include/mach/handoff_soc64.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm/mach-socfpga/include/mach/handoff_soc64.h b/arch/arm/mach-socfpga/include/mach/handoff_soc64.h index 9ef82cf46c0..b8f2f73e283 100644 --- a/arch/arm/mach-socfpga/include/mach/handoff_soc64.h +++ b/arch/arm/mach-socfpga/include/mach/handoff_soc64.h @@ -98,6 +98,8 @@ #define SOC64_HANDOFF_IOCTL_LEN 96 #if IS_ENABLED(CONFIG_TARGET_SOCFPGA_STRATIX10) #define SOC64_HANDOFF_FPGA_LEN 42 +#elif IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX5) +#define SOC64_HANDOFF_FPGA_LEN 44 #else #define SOC64_HANDOFF_FPGA_LEN 40 #endif -- cgit v1.2.3 From f4db066455119d944adda481b5d3415fe79ba858 Mon Sep 17 00:00:00 2001 From: Alif Zakuan Yuslaimi Date: Mon, 22 Sep 2025 18:31:47 -0700 Subject: arm: socfpga: mailbox: Remove CONFIG_CADENCE_QSPI guard from QSPI mailbox API declarations The QSPI mailbox API function declarations (mbox_qspi_close and mbox_qspi_open) in mailbox_s10.h were guarded by CONFIG_CADENCE_QSPI preprocessor conditional. This prevented their prototypes from being visible to code that may use the stub implementations when CONFIG_CADENCE_QSPI is disabled. Remove the CONFIG_CADENCE_QSPI preprocessor conditional so these functions are always declared, regardless of the configuration. This avoids potential build or linkage errors when stubs are used. Signed-off-by: Alif Zakuan Yuslaimi Reviewed-by: Tien Fong Chee --- arch/arm/mach-socfpga/include/mach/mailbox_s10.h | 2 -- 1 file changed, 2 deletions(-) diff --git a/arch/arm/mach-socfpga/include/mach/mailbox_s10.h b/arch/arm/mach-socfpga/include/mach/mailbox_s10.h index 2099c51b682..1a461de4819 100644 --- a/arch/arm/mach-socfpga/include/mach/mailbox_s10.h +++ b/arch/arm/mach-socfpga/include/mach/mailbox_s10.h @@ -398,10 +398,8 @@ int mbox_rcv_resp(u32 *resp_buf, u32 resp_buf_max_len); int mbox_rcv_resp_psci(u32 *resp_buf, u32 resp_buf_max_len); int mbox_init(void); -#ifdef CONFIG_CADENCE_QSPI int mbox_qspi_close(void); int mbox_qspi_open(void); -#endif int mbox_reset_cold(void); int mbox_hps_stage_notify(u32 execution_stage); -- cgit v1.2.3 From 36e013490ed40af227f206b2906e30ad877a7854 Mon Sep 17 00:00:00 2001 From: Alif Zakuan Yuslaimi Date: Thu, 14 Aug 2025 20:40:22 -0700 Subject: configs: agilex5: Increase watchdog timeout Linux kernel will fail to boot due to exceeding timeout trying to probe I3C device. Increasing the watchdog timeout 30 seconds will give enough time for Linux to probe the I3C device and will be able to boot up successfully. User is expected to fine tune the watchdog timeout for the complete boot in production. Signed-off-by: Alif Zakuan Yuslaimi Reviewed-by: Tien Fong Chee --- configs/socfpga_agilex5_defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/configs/socfpga_agilex5_defconfig b/configs/socfpga_agilex5_defconfig index b373201dbaa..846c18eed27 100644 --- a/configs/socfpga_agilex5_defconfig +++ b/configs/socfpga_agilex5_defconfig @@ -15,6 +15,7 @@ CONFIG_SPL_HAS_BSS_LINKER_SECTION=y CONFIG_SPL_BSS_START_ADDR=0x9ff00000 CONFIG_SPL_BSS_MAX_SIZE=0x100000 CONFIG_SYS_LOAD_ADDR=0x82000000 +CONFIG_WATCHDOG_TIMEOUT_MSECS=30000 CONFIG_TARGET_SOCFPGA_AGILEX5_SOCDK=y CONFIG_IDENT_STRING="socfpga_agilex5" CONFIG_SPL_FS_FAT=y -- cgit v1.2.3 From 8d28f121d3794613a2ab6799d54f743e439763ab Mon Sep 17 00:00:00 2001 From: Boon Khai Ng Date: Thu, 14 Aug 2025 11:17:39 +0800 Subject: arch: arm: mach-socfpga: smc: Add dcache flushing and invalidation in smc_send_mailbox() Adding the dcache flushing and invalidation in the smc_send_mailbox() At the same time replace the use of u64 with uintptr_t to ensure compatibility across different architectures and correct the pointer arithmetic for buffer end address calculation. Signed-off-by: Mahesh Rao Signed-off-by: Boon Khai Ng Reviewed-by: Tien Fong Chee Reviewed-by: Tien Fong Chee --- arch/arm/mach-socfpga/smc_api.c | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/mach-socfpga/smc_api.c b/arch/arm/mach-socfpga/smc_api.c index b212a94b321..a531030f5be 100644 --- a/arch/arm/mach-socfpga/smc_api.c +++ b/arch/arm/mach-socfpga/smc_api.c @@ -57,6 +57,7 @@ int smc_send_mailbox(u32 cmd, u32 len, u32 *arg, u8 urgent, u32 *resp_buf_len, resp, ARRAY_SIZE(resp)); if (ret == INTEL_SIP_SMC_STATUS_OK && resp_buf && resp_buf_len) { + invalidate_dcache_range((uintptr_t)resp_buf, (uintptr_t)(resp_buf + *resp_buf_len)); if (!resp[0]) *resp_buf_len = resp[1]; } -- cgit v1.2.3 From c4e9554015ebe919a480a54e508461af7a3e9fc8 Mon Sep 17 00:00:00 2001 From: Alif Zakuan Yuslaimi Date: Mon, 8 Sep 2025 19:11:14 -0700 Subject: include: dt-bindings: clk: agilex: Add Agilex clock definitions header file Introduce header file to define the clock indexes for the Agilex platform. Signed-off-by: Alif Zakuan Yuslaimi Reviewed-by: Tien Fong Chee --- include/dt-bindings/clock/agilex-clock.h | 71 ++++++++++++++++++++++++++++++++ 1 file changed, 71 insertions(+) create mode 100644 include/dt-bindings/clock/agilex-clock.h diff --git a/include/dt-bindings/clock/agilex-clock.h b/include/dt-bindings/clock/agilex-clock.h new file mode 100644 index 00000000000..a6252180516 --- /dev/null +++ b/include/dt-bindings/clock/agilex-clock.h @@ -0,0 +1,71 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2025 Altera Corporation + */ + +#ifndef __AGILEX_CLOCK_H +#define __AGILEX_CLOCK_H + +/* fixed rate clocks */ +#define AGILEX_OSC1 0 +#define AGILEX_CB_INTOSC_HS_DIV2_CLK 1 +#define AGILEX_CB_INTOSC_LS_CLK 2 +#define AGILEX_L4_SYS_FREE_CLK 3 +#define AGILEX_F2S_FREE_CLK 4 + +/* PLL clocks */ +#define AGILEX_MAIN_PLL_CLK 5 +#define AGILEX_MAIN_PLL_C0_CLK 6 +#define AGILEX_MAIN_PLL_C1_CLK 7 +#define AGILEX_MAIN_PLL_C2_CLK 8 +#define AGILEX_MAIN_PLL_C3_CLK 9 +#define AGILEX_PERIPH_PLL_CLK 10 +#define AGILEX_PERIPH_PLL_C0_CLK 11 +#define AGILEX_PERIPH_PLL_C1_CLK 12 +#define AGILEX_PERIPH_PLL_C2_CLK 13 +#define AGILEX_PERIPH_PLL_C3_CLK 14 +#define AGILEX_MPU_FREE_CLK 15 +#define AGILEX_MPU_CCU_CLK 16 +#define AGILEX_BOOT_CLK 17 + +/* fixed factor clocks */ +#define AGILEX_L3_MAIN_FREE_CLK 18 +#define AGILEX_NOC_FREE_CLK 19 +#define AGILEX_S2F_USR0_CLK 20 +#define AGILEX_NOC_CLK 21 +#define AGILEX_EMAC_A_FREE_CLK 22 +#define AGILEX_EMAC_B_FREE_CLK 23 +#define AGILEX_EMAC_PTP_FREE_CLK 24 +#define AGILEX_GPIO_DB_FREE_CLK 25 +#define AGILEX_SDMMC_FREE_CLK 26 +#define AGILEX_S2F_USER0_FREE_CLK 27 +#define AGILEX_S2F_USER1_FREE_CLK 28 +#define AGILEX_PSI_REF_FREE_CLK 29 + +/* Gate clocks */ +#define AGILEX_MPU_CLK 30 +#define AGILEX_MPU_PERIPH_CLK 31 +#define AGILEX_L4_MAIN_CLK 32 +#define AGILEX_L4_MP_CLK 33 +#define AGILEX_L4_SP_CLK 34 +#define AGILEX_CS_AT_CLK 35 +#define AGILEX_CS_TRACE_CLK 36 +#define AGILEX_CS_PDBG_CLK 37 +#define AGILEX_CS_TIMER_CLK 38 +#define AGILEX_S2F_USER0_CLK 39 +#define AGILEX_EMAC0_CLK 40 +#define AGILEX_EMAC1_CLK 41 +#define AGILEX_EMAC2_CLK 42 +#define AGILEX_EMAC_PTP_CLK 43 +#define AGILEX_GPIO_DB_CLK 44 +#define AGILEX_NAND_CLK 45 +#define AGILEX_PSI_REF_CLK 46 +#define AGILEX_S2F_USER1_CLK 47 +#define AGILEX_SDMMC_CLK 48 +#define AGILEX_SPI_M_CLK 49 +#define AGILEX_USB_CLK 50 +#define AGILEX_NAND_X_CLK 51 +#define AGILEX_NAND_ECC_CLK 52 +#define AGILEX_NUM_CLKS 53 + +#endif /* __AGILEX_CLOCK_H */ -- cgit v1.2.3 From 38d49808d4cd51e8972bfe7478db03325118d553 Mon Sep 17 00:00:00 2001 From: Boon Khai Ng Date: Thu, 14 Aug 2025 11:17:40 +0800 Subject: cache: Check dcache availability before calling cache functions When the data cache (dcache) is disabled, calling related status functions can lead to compilation errors due to undefined references. Adding a !CONFIG_IS_ENABLED(SYS_DCACHE_OFF) check before invoking dcache_status() (used in common/memsize.c:get_ram_size()) and mmu_status() (from arch/arm/include/asm/io.h). Without this check, builds with dcache disabled will fail to compile. Signed-off-by: Boon Khai Ng Reviewed-by: Tom Rini --- arch/arm/include/asm/io.h | 28 ++++++++++++++++------------ common/memsize.c | 5 ++++- 2 files changed, 20 insertions(+), 13 deletions(-) diff --git a/arch/arm/include/asm/io.h b/arch/arm/include/asm/io.h index 85ec0e6937e..cebed7397d4 100644 --- a/arch/arm/include/asm/io.h +++ b/arch/arm/include/asm/io.h @@ -386,12 +386,14 @@ void __memcpy_fromio(void *to, const volatile void __iomem *from, size_t count) count--; } - if (mmu_status()) { - while (count >= 8) { - *(u64 *)to = __raw_readq(from); - from += 8; - to += 8; - count -= 8; + if (!CONFIG_IS_ENABLED(SYS_DCACHE_OFF)) { + if (mmu_status()) { + while (count >= 8) { + *(u64 *)to = __raw_readq(from); + from += 8; + to += 8; + count -= 8; + } } } @@ -416,12 +418,14 @@ void __memcpy_toio(volatile void __iomem *to, const void *from, size_t count) count--; } - if (mmu_status()) { - while (count >= 8) { - __raw_writeq(*(u64 *)from, to); - from += 8; - to += 8; - count -= 8; + if (!CONFIG_IS_ENABLED(SYS_DCACHE_OFF)) { + if (mmu_status()) { + while (count >= 8) { + __raw_writeq(*(u64 *)from, to); + from += 8; + to += 8; + count -= 8; + } } } diff --git a/common/memsize.c b/common/memsize.c index 86109579c95..3c3ae6f1eba 100644 --- a/common/memsize.c +++ b/common/memsize.c @@ -52,7 +52,10 @@ long get_ram_size(long *base, long maxsize) long val; long size; int i = 0; - int dcache_en = dcache_status(); + int dcache_en = 0; + + if (!CONFIG_IS_ENABLED(SYS_DCACHE_OFF)) + dcache_en = dcache_status(); for (cnt = (maxsize / sizeof(long)) >> 1; cnt > 0; cnt >>= 1) { addr = base + cnt; /* pointer arith! */ -- cgit v1.2.3 From 022b2159b5d24556b7623906de147260fe46e0f2 Mon Sep 17 00:00:00 2001 From: Alif Zakuan Yuslaimi Date: Mon, 8 Sep 2025 19:11:15 -0700 Subject: drivers: clk: agilex: Support for enable/disable API Update Agilex clock driver to support enabling or disabling the peripheral clocks via clock driver model APIs. The caller will pass the clock ID to this driver and the driver will then proceed to manipulate the desired bit in the Agilex clock manager peripheral PLL register based on the given clock ID. Signed-off-by: Alif Zakuan Yuslaimi Reviewed-by: Tien Fong Chee --- drivers/clk/altera/clk-agilex.c | 120 ++++++++++++++++++++++++++++++++++++++++ drivers/clk/altera/clk-agilex.h | 20 +++++++ 2 files changed, 140 insertions(+) diff --git a/drivers/clk/altera/clk-agilex.c b/drivers/clk/altera/clk-agilex.c index 242740a4b00..46b04895cc5 100644 --- a/drivers/clk/altera/clk-agilex.c +++ b/drivers/clk/altera/clk-agilex.c @@ -22,6 +22,8 @@ DECLARE_GLOBAL_DATA_PTR; struct socfpga_clk_plat { void __iomem *regs; + int pllgrp; + int bitmask; }; /* @@ -643,8 +645,125 @@ static ulong socfpga_clk_get_rate(struct clk *clk) } } +static int bitmask_from_clk_id(struct clk *clk) +{ + struct socfpga_clk_plat *plat = dev_get_plat(clk->dev); + + switch (clk->id) { + case AGILEX_MPU_CLK: + plat->pllgrp = CLKMGR_MAINPLL_EN; + plat->bitmask = CLKMGR_MAINPLLGRP_EN_MPUCLK_MASK; + break; + case AGILEX_L4_MAIN_CLK: + plat->pllgrp = CLKMGR_MAINPLL_EN; + plat->bitmask = CLKMGR_MAINPLLGRP_EN_L4MAINCLK_MASK; + break; + case AGILEX_L4_MP_CLK: + plat->pllgrp = CLKMGR_MAINPLL_EN; + plat->bitmask = CLKMGR_MAINPLLGRP_EN_L4MPCLK_MASK; + break; + case AGILEX_L4_SP_CLK: + plat->pllgrp = CLKMGR_MAINPLL_EN; + plat->bitmask = CLKMGR_MAINPLLGRP_EN_L4SPCLK_MASK; + break; + case AGILEX_CS_AT_CLK: + plat->pllgrp = CLKMGR_MAINPLL_EN; + plat->bitmask = CLKMGR_MAINPLLGRP_EN_CSCLK_MASK; + break; + case AGILEX_CS_TRACE_CLK: + plat->pllgrp = CLKMGR_MAINPLL_EN; + plat->bitmask = CLKMGR_MAINPLLGRP_EN_CSCLK_MASK; + break; + case AGILEX_CS_PDBG_CLK: + plat->pllgrp = CLKMGR_MAINPLL_EN; + plat->bitmask = CLKMGR_MAINPLLGRP_EN_CSCLK_MASK; + break; + case AGILEX_CS_TIMER_CLK: + plat->pllgrp = CLKMGR_MAINPLL_EN; + plat->bitmask = CLKMGR_MAINPLLGRP_EN_CSTIMERCLK_MASK; + break; + case AGILEX_S2F_USER0_CLK: + plat->pllgrp = CLKMGR_MAINPLL_EN; + plat->bitmask = CLKMGR_MAINPLLGRP_EN_S2FUSER0CLK_MASK; + break; + case AGILEX_EMAC0_CLK: + plat->pllgrp = CLKMGR_PERPLL_EN; + plat->bitmask = CLKMGR_PERPLLGRP_EN_EMAC0CLK_MASK; + break; + case AGILEX_EMAC1_CLK: + plat->pllgrp = CLKMGR_PERPLL_EN; + plat->bitmask = CLKMGR_PERPLLGRP_EN_EMAC1CLK_MASK; + break; + case AGILEX_EMAC2_CLK: + plat->pllgrp = CLKMGR_PERPLL_EN; + plat->bitmask = CLKMGR_PERPLLGRP_EN_EMAC2CLK_MASK; + break; + case AGILEX_EMAC_PTP_CLK: + plat->pllgrp = CLKMGR_PERPLL_EN; + plat->bitmask = CLKMGR_PERPLLGRP_EN_EMACPTPCLK_MASK; + break; + case AGILEX_GPIO_DB_CLK: + plat->pllgrp = CLKMGR_PERPLL_EN; + plat->bitmask = CLKMGR_PERPLLGRP_EN_GPIODBCLK_MASK; + break; + case AGILEX_SDMMC_CLK: + plat->pllgrp = CLKMGR_PERPLL_EN; + plat->bitmask = CLKMGR_PERPLLGRP_EN_SDMMCCLK_MASK; + break; + case AGILEX_S2F_USER1_CLK: + plat->pllgrp = CLKMGR_PERPLL_EN; + plat->bitmask = CLKMGR_PERPLLGRP_EN_S2FUSER1CLK_MASK; + break; + case AGILEX_PSI_REF_CLK: + plat->pllgrp = CLKMGR_PERPLL_EN; + plat->bitmask = CLKMGR_PERPLLGRP_EN_PSIREFCLK_MASK; + break; + case AGILEX_USB_CLK: + plat->pllgrp = CLKMGR_PERPLL_EN; + plat->bitmask = CLKMGR_PERPLLGRP_EN_USBCLK_MASK; + break; + case AGILEX_SPI_M_CLK: + plat->pllgrp = CLKMGR_PERPLL_EN; + plat->bitmask = CLKMGR_PERPLLGRP_EN_SPIMCLK_MASK; + break; + case AGILEX_NAND_CLK: + plat->pllgrp = CLKMGR_PERPLL_EN; + plat->bitmask = CLKMGR_PERPLLGRP_EN_NANDCLK_MASK; + break; + default: + return -ENXIO; + } + + return 0; +} + static int socfpga_clk_enable(struct clk *clk) { + struct socfpga_clk_plat *plat = dev_get_plat(clk->dev); + uintptr_t base_addr = (uintptr_t)plat->regs; + int ret; + + ret = bitmask_from_clk_id(clk); + if (ret) + return ret; + + setbits_le32(base_addr + plat->pllgrp, plat->bitmask); + + return 0; +} + +static int socfpga_clk_disable(struct clk *clk) +{ + struct socfpga_clk_plat *plat = dev_get_plat(clk->dev); + uintptr_t base_addr = (uintptr_t)plat->regs; + int ret; + + ret = bitmask_from_clk_id(clk); + if (ret) + return ret; + + clrbits_le32(base_addr + plat->pllgrp, plat->bitmask); + return 0; } @@ -672,6 +791,7 @@ static int socfpga_clk_of_to_plat(struct udevice *dev) static struct clk_ops socfpga_clk_ops = { .enable = socfpga_clk_enable, + .disable = socfpga_clk_disable, .get_rate = socfpga_clk_get_rate, }; diff --git a/drivers/clk/altera/clk-agilex.h b/drivers/clk/altera/clk-agilex.h index b3e8841a512..be639957940 100644 --- a/drivers/clk/altera/clk-agilex.h +++ b/drivers/clk/altera/clk-agilex.h @@ -1,6 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0 */ /* * Copyright (C) 2019 Intel Corporation + * Copyright (C) 2025 Altera Corporation */ #ifndef _CLK_AGILEX_ @@ -210,7 +211,26 @@ struct cm_config { #define CLKMGR_LOSTLOCK_SET_MASK BIT(0) +#define CLKMGR_MAINPLLGRP_EN_MPUCLK_MASK BIT(0) +#define CLKMGR_MAINPLLGRP_EN_L4MAINCLK_MASK BIT(1) +#define CLKMGR_MAINPLLGRP_EN_L4MPCLK_MASK BIT(2) +#define CLKMGR_MAINPLLGRP_EN_L4SPCLK_MASK BIT(3) +#define CLKMGR_MAINPLLGRP_EN_CSCLK_MASK BIT(4) +#define CLKMGR_MAINPLLGRP_EN_CSTIMERCLK_MASK BIT(5) +#define CLKMGR_MAINPLLGRP_EN_S2FUSER0CLK_MASK BIT(6) + +#define CLKMGR_PERPLLGRP_EN_EMAC0CLK_MASK BIT(0) +#define CLKMGR_PERPLLGRP_EN_EMAC1CLK_MASK BIT(1) +#define CLKMGR_PERPLLGRP_EN_EMAC2CLK_MASK BIT(2) +#define CLKMGR_PERPLLGRP_EN_EMACPTPCLK_MASK BIT(3) +#define CLKMGR_PERPLLGRP_EN_GPIODBCLK_MASK BIT(4) #define CLKMGR_PERPLLGRP_EN_SDMMCCLK_MASK BIT(5) +#define CLKMGR_PERPLLGRP_EN_S2FUSER1CLK_MASK BIT(6) +#define CLKMGR_PERPLLGRP_EN_PSIREFCLK_MASK BIT(7) +#define CLKMGR_PERPLLGRP_EN_USBCLK_MASK BIT(8) +#define CLKMGR_PERPLLGRP_EN_SPIMCLK_MASK BIT(9) +#define CLKMGR_PERPLLGRP_EN_NANDCLK_MASK BIT(10) + #define CLKMGR_PERPLLGRP_EMACCTL_EMAC0SELB_OFFSET 26 #define CLKMGR_PERPLLGRP_EMACCTL_EMAC0SELB_MASK BIT(26) #define CLKMGR_PERPLLGRP_EMACCTL_EMAC1SELB_OFFSET 27 -- cgit v1.2.3 From 190a339ae345c5653aca5557e713af6a9227f29e Mon Sep 17 00:00:00 2001 From: Boon Khai Ng Date: Thu, 14 Aug 2025 11:17:41 +0800 Subject: configs: agilex5: Enable config SPL_SYS_DCACHE_OFF Add SPL_SYS_DCACHE_OFF to Agilex5 defconfig to disable data cache for SPL Signed-off-by: Tanmay Kathpalia Signed-off-by: Boon Khai Ng Reviewed-by: Tien Fong Chee --- configs/socfpga_agilex5_defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/configs/socfpga_agilex5_defconfig b/configs/socfpga_agilex5_defconfig index 846c18eed27..24c95eb39d5 100644 --- a/configs/socfpga_agilex5_defconfig +++ b/configs/socfpga_agilex5_defconfig @@ -46,6 +46,7 @@ CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x9fa00000 CONFIG_SPL_SYS_MALLOC_SIZE=0x500000 CONFIG_SPL_CACHE=y +CONFIG_SPL_SYS_DCACHE_OFF=y CONFIG_SPL_MTD=y CONFIG_SPL_POWER_DOMAIN=y CONFIG_SPL_SPI_FLASH_MTD=y -- cgit v1.2.3 From ab27182cac8ff14621c73c6609aaf3036fab1c0a Mon Sep 17 00:00:00 2001 From: Alif Zakuan Yuslaimi Date: Mon, 8 Sep 2025 19:11:16 -0700 Subject: mmc: socfpga_dw_mmc: Enable/disable SDMMC clock via API Update the driver to enable or disable the SDMMC clock via clock driver model API instead of doing it in the driver itself. This allows for scalability of the driver for various SoCFPGA devices. Signed-off-by: Alif Zakuan Yuslaimi Reviewed-by: Tien Fong Chee --- drivers/mmc/socfpga_dw_mmc.c | 33 +++++++++++++++++---------------- 1 file changed, 17 insertions(+), 16 deletions(-) diff --git a/drivers/mmc/socfpga_dw_mmc.c b/drivers/mmc/socfpga_dw_mmc.c index 3b86bc9b18c..db4e0129c2e 100644 --- a/drivers/mmc/socfpga_dw_mmc.c +++ b/drivers/mmc/socfpga_dw_mmc.c @@ -29,7 +29,9 @@ struct socfpga_dwmci_plat { /* socfpga implmentation specific driver private data */ struct dwmci_socfpga_priv_data { + struct udevice *dev; struct dwmci_host host; + struct clk mmc_clk_ciu; unsigned int drvsel; unsigned int smplsel; }; @@ -51,28 +53,23 @@ static void socfpga_dwmci_reset(struct udevice *dev) static int socfpga_dwmci_clksel(struct dwmci_host *host) { struct dwmci_socfpga_priv_data *priv = host->priv; + int ret; + u32 sdmmc_mask = ((priv->smplsel & 0x7) << SYSMGR_SDMMC_SMPLSEL_SHIFT) | ((priv->drvsel & 0x7) << SYSMGR_SDMMC_DRVSEL_SHIFT); - /* Get clock manager base address */ - struct udevice *clkmgr_dev; - int ret = uclass_get_device_by_name(UCLASS_CLK, "clock-controller@ffd10000", &clkmgr_dev); - + ret = clk_get_by_name(priv->dev, "ciu", &priv->mmc_clk_ciu); if (ret) { - printf("Failed to get clkmgr device: %d\n", ret); + debug("%s: Failed to get SDMMC clock from dts\n", __func__); return ret; } - fdt_addr_t clkmgr_base = dev_read_addr(clkmgr_dev); - - if (clkmgr_base == FDT_ADDR_T_NONE) { - printf("Failed to read base address from clkmgr DT node\n"); - return -EINVAL; - } - /* Disable SDMMC clock. */ - clrbits_le32(clkmgr_base + CLKMGR_PERPLL_EN, - CLKMGR_PERPLLGRP_EN_SDMMCCLK_MASK); + ret = clk_disable(&priv->mmc_clk_ciu); + if (ret) { + printf("%s: Failed to disable SDMMC clock\n", __func__); + return ret; + } debug("%s: drvsel %d smplsel %d\n", __func__, priv->drvsel, priv->smplsel); @@ -92,8 +89,11 @@ static int socfpga_dwmci_clksel(struct dwmci_host *host) #endif /* Enable SDMMC clock */ - setbits_le32(clkmgr_base + CLKMGR_PERPLL_EN, - CLKMGR_PERPLLGRP_EN_SDMMCCLK_MASK); + ret = clk_enable(&priv->mmc_clk_ciu); + if (ret) { + printf("%s: Failed to enable SDMMC clock\n", __func__); + return ret; + } return 0; } @@ -169,6 +169,7 @@ static int socfpga_dwmmc_probe(struct udevice *dev) struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev); struct dwmci_socfpga_priv_data *priv = dev_get_priv(dev); struct dwmci_host *host = &priv->host; + priv->dev = dev; int ret; ret = socfpga_dwmmc_get_clk_rate(dev); -- cgit v1.2.3 From 924a9fc4021cf4899c6b1e26d28336f412aa296f Mon Sep 17 00:00:00 2001 From: Naresh Kumar Ravulapalli Date: Wed, 10 Sep 2025 22:21:11 -0700 Subject: drivers: clk: agilex: Fix EMAC clock source selection Fix the incorrect bit masking and bit shift used to compute EMAC control which in turn is used to select EMAC clock from EMAC source A or B. Signed-off-by: Naresh Kumar Ravulapalli Reviewed-by: Tien Fong Chee --- drivers/clk/altera/clk-agilex.c | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/drivers/clk/altera/clk-agilex.c b/drivers/clk/altera/clk-agilex.c index 46b04895cc5..19c4e8220db 100644 --- a/drivers/clk/altera/clk-agilex.c +++ b/drivers/clk/altera/clk-agilex.c @@ -546,14 +546,14 @@ static u32 clk_get_emac_clk_hz(struct socfpga_clk_plat *plat, u32 emac_id) /* Get EMAC clock source */ ctl = CM_REG_READL(plat, CLKMGR_PERPLL_EMACCTL); if (emac_id == AGILEX_EMAC0_CLK) - ctl = (ctl >> CLKMGR_PERPLLGRP_EMACCTL_EMAC0SELB_OFFSET) & - CLKMGR_PERPLLGRP_EMACCTL_EMAC0SELB_MASK; + ctl = (ctl & CLKMGR_PERPLLGRP_EMACCTL_EMAC0SELB_MASK) >> + CLKMGR_PERPLLGRP_EMACCTL_EMAC0SELB_OFFSET; else if (emac_id == AGILEX_EMAC1_CLK) - ctl = (ctl >> CLKMGR_PERPLLGRP_EMACCTL_EMAC1SELB_OFFSET) & - CLKMGR_PERPLLGRP_EMACCTL_EMAC1SELB_MASK; + ctl = (ctl & CLKMGR_PERPLLGRP_EMACCTL_EMAC1SELB_MASK) >> + CLKMGR_PERPLLGRP_EMACCTL_EMAC1SELB_OFFSET; else if (emac_id == AGILEX_EMAC2_CLK) - ctl = (ctl >> CLKMGR_PERPLLGRP_EMACCTL_EMAC2SELB_OFFSET) & - CLKMGR_PERPLLGRP_EMACCTL_EMAC2SELB_MASK; + ctl = (ctl & CLKMGR_PERPLLGRP_EMACCTL_EMAC2SELB_MASK) >> + CLKMGR_PERPLLGRP_EMACCTL_EMAC2SELB_OFFSET; else return 0; -- cgit v1.2.3 From 2ff686bcfd14689de3d6a6da9c35340449025ef5 Mon Sep 17 00:00:00 2001 From: Naresh Kumar Ravulapalli Date: Wed, 10 Sep 2025 22:21:12 -0700 Subject: drivers: clk: agilex: Use FIELD_GET during EMAC clock selection FIELD_GET() macro is used during EMAC clock source selection for better code readability and maintainability. Signed-off-by: Naresh Kumar Ravulapalli Reviewed-by: Tien Fong Chee --- drivers/clk/altera/clk-agilex.c | 10 ++++------ 1 file changed, 4 insertions(+), 6 deletions(-) diff --git a/drivers/clk/altera/clk-agilex.c b/drivers/clk/altera/clk-agilex.c index 19c4e8220db..fdbf834bb2f 100644 --- a/drivers/clk/altera/clk-agilex.c +++ b/drivers/clk/altera/clk-agilex.c @@ -14,6 +14,7 @@ #include #include #include +#include #include #include @@ -546,14 +547,11 @@ static u32 clk_get_emac_clk_hz(struct socfpga_clk_plat *plat, u32 emac_id) /* Get EMAC clock source */ ctl = CM_REG_READL(plat, CLKMGR_PERPLL_EMACCTL); if (emac_id == AGILEX_EMAC0_CLK) - ctl = (ctl & CLKMGR_PERPLLGRP_EMACCTL_EMAC0SELB_MASK) >> - CLKMGR_PERPLLGRP_EMACCTL_EMAC0SELB_OFFSET; + ctl = FIELD_GET(CLKMGR_PERPLLGRP_EMACCTL_EMAC0SELB_MASK, ctl); else if (emac_id == AGILEX_EMAC1_CLK) - ctl = (ctl & CLKMGR_PERPLLGRP_EMACCTL_EMAC1SELB_MASK) >> - CLKMGR_PERPLLGRP_EMACCTL_EMAC1SELB_OFFSET; + ctl = FIELD_GET(CLKMGR_PERPLLGRP_EMACCTL_EMAC1SELB_MASK, ctl); else if (emac_id == AGILEX_EMAC2_CLK) - ctl = (ctl & CLKMGR_PERPLLGRP_EMACCTL_EMAC2SELB_MASK) >> - CLKMGR_PERPLLGRP_EMACCTL_EMAC2SELB_OFFSET; + ctl = FIELD_GET(CLKMGR_PERPLLGRP_EMACCTL_EMAC2SELB_MASK, ctl); else return 0; -- cgit v1.2.3 From e3a11a240add752f092092fd514af68f441aab31 Mon Sep 17 00:00:00 2001 From: Naresh Kumar Ravulapalli Date: Wed, 24 Sep 2025 00:49:08 -0700 Subject: arch: arm: dts: Enable USB3.1 for Agilex5 USB 3.1 node is enabled for Agilex5. Signed-off-by: Naresh Kumar Ravulapalli Reviewed-by: Tien Fong Chee --- arch/arm/dts/socfpga_agilex5_socdk.dts | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm/dts/socfpga_agilex5_socdk.dts b/arch/arm/dts/socfpga_agilex5_socdk.dts index 2ab143e38f8..886cc89fdb6 100644 --- a/arch/arm/dts/socfpga_agilex5_socdk.dts +++ b/arch/arm/dts/socfpga_agilex5_socdk.dts @@ -87,6 +87,10 @@ disable-over-current; }; +&usb31 { + status = "okay"; +}; + &watchdog0 { status = "okay"; }; -- cgit v1.2.3 From 61c4768d83fc3f7ce21b151a6e1b02397d788926 Mon Sep 17 00:00:00 2001 From: Naresh Kumar Ravulapalli Date: Wed, 24 Sep 2025 00:49:09 -0700 Subject: configs: Enable USB DWC3 host drivers for Agilex5 Required USB DWC3 host driver configurations are enabled for Agilex5. Signed-off-by: Naresh Kumar Ravulapalli Reviewed-by: Tien Fong Chee --- configs/socfpga_agilex5_defconfig | 2 ++ 1 file changed, 2 insertions(+) diff --git a/configs/socfpga_agilex5_defconfig b/configs/socfpga_agilex5_defconfig index 24c95eb39d5..da9241b765a 100644 --- a/configs/socfpga_agilex5_defconfig +++ b/configs/socfpga_agilex5_defconfig @@ -103,7 +103,9 @@ CONFIG_TIMER=y CONFIG_DESIGNWARE_APB_TIMER=y CONFIG_USB=y CONFIG_USB_XHCI_HCD=y +CONFIG_USB_XHCI_DWC3=y CONFIG_USB_DWC2=y +CONFIG_USB_DWC3=y CONFIG_DESIGNWARE_WATCHDOG=y CONFIG_WDT=y # CONFIG_SPL_USE_TINY_PRINTF is not set -- cgit v1.2.3 From 060ed1bbbe0fd1a8583d09d7766cf3f194b23edc Mon Sep 17 00:00:00 2001 From: Naresh Kumar Ravulapalli Date: Wed, 24 Sep 2025 00:49:10 -0700 Subject: configs: Increase USB Hub debounce timeout in Agilex5 Some legacy USB mass storage devices during connection were observed to have debounce issues. Hence, increasing the default USB Hub debounce timeout value to handle this issue for devices connected to Agilex5 boards. Signed-off-by: Naresh Kumar Ravulapalli Reviewed-by: Tien Fong Chee --- configs/socfpga_agilex5_defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/configs/socfpga_agilex5_defconfig b/configs/socfpga_agilex5_defconfig index da9241b765a..9ca1910d53f 100644 --- a/configs/socfpga_agilex5_defconfig +++ b/configs/socfpga_agilex5_defconfig @@ -106,6 +106,7 @@ CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y CONFIG_USB_DWC2=y CONFIG_USB_DWC3=y +CONFIG_USB_HUB_DEBOUNCE_TIMEOUT=3000 CONFIG_DESIGNWARE_WATCHDOG=y CONFIG_WDT=y # CONFIG_SPL_USE_TINY_PRINTF is not set -- cgit v1.2.3 From da57acb4c396cfc978c0652fec9dfb17a4f67ad8 Mon Sep 17 00:00:00 2001 From: Naresh Kumar Ravulapalli Date: Wed, 24 Sep 2025 00:49:11 -0700 Subject: arch: arm: socfpga: Configure USB3 System Manager registers For successful reset staggering pulse operation, reset pulse override bit is set. Port overcurrent bit 1, which in reality reflects PIPE power present signal is set to avoid giving false information of Vbus status to HPS controller. Signed-off-by: Naresh Kumar Ravulapalli Reviewed-by: Tien Fong Chee --- .../include/mach/system_manager_soc64.h | 12 +++++++++++ arch/arm/mach-socfpga/system_manager_soc64.c | 24 ++++++++++++++++++++++ 2 files changed, 36 insertions(+) diff --git a/arch/arm/mach-socfpga/include/mach/system_manager_soc64.h b/arch/arm/mach-socfpga/include/mach/system_manager_soc64.h index 054a28d845d..f768a3a55cb 100644 --- a/arch/arm/mach-socfpga/include/mach/system_manager_soc64.h +++ b/arch/arm/mach-socfpga/include/mach/system_manager_soc64.h @@ -33,6 +33,7 @@ void populate_sysmgr_pinmux(void); #define SYSMGR_SOC64_ECC_INTMASK_CLR 0x98 #define SYSMGR_SOC64_ECC_INTMASK_SERR 0x9C #define SYSMGR_SOC64_ECC_INTMASK_DERR 0xA0 +#define SYSMGR_SOC64_USB3_MISC_CTRL_REG0 0x1F0 #define SYSMGR_SOC64_MPFE_CONFIG 0x228 #define SYSMGR_SOC64_BOOT_SCRATCH_POR0 0x258 #define SYSMGR_SOC64_BOOT_SCRATCH_POR1 0x25C @@ -47,6 +48,17 @@ void populate_sysmgr_pinmux(void); #define ALT_SYSMGR_SCRATCH_REG_POR_0_DDR_PROGRESS_MASK BIT(0) #define ALT_SYSMGR_SCRATCH_REG_POR_1_REVA_WORKAROUND_USER_MODE_MASK BIT(0) #define ALT_SYSMGR_SCRATCH_REG_POR_1_REVA_WORKAROUND_MASK BIT(1) + +/* + * Bits for SYSMGR_SOC64_USB3_MISC_CTRL_REG0 + * Bits[14:13] Port Overcurrent + * Bit[12] Reset Pulse Override + */ +#define SYSMGR_SOC64_USB3_MISC_CTRL_REG0_PORT_OVR_CURR GENMASK(14, 13) +#define SYSMGR_SOC64_USB3_MISC_CTRL_REG0_RESET_PUL_OVR BIT(12) +#define SET_USB3_MISC_CTRL_REG0_PORT_RESET_PUL_OVR 1 +/* BIT 1 actually reflects PIPE power present signal */ +#define SET_USB3_MISC_CTRL_REG0_PORT_OVR_CURR_BIT_1 2 #else #define SYSMGR_SOC64_NAND_AXUSER 0x5c #define SYSMGR_SOC64_DMA_L3MASTER 0x74 diff --git a/arch/arm/mach-socfpga/system_manager_soc64.c b/arch/arm/mach-socfpga/system_manager_soc64.c index 4b42158be9d..913f93c8f94 100644 --- a/arch/arm/mach-socfpga/system_manager_soc64.c +++ b/arch/arm/mach-socfpga/system_manager_soc64.c @@ -8,9 +8,29 @@ #include #include #include +#include DECLARE_GLOBAL_DATA_PTR; +#if IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX5) +/* + * Setting RESET_PULSE_OVERRIDE bit for successful reset staggering pulse + * generation and setting PORT_OVERCURRENT bit so that until we turn on the + * Vbus, it doesn't give false information about Vbus to the HPS controller. + */ +static void sysmgr_config_usb3(void) +{ + u32 reg_val = 0; + + reg_val = readl(socfpga_get_sysmgr_addr() + SYSMGR_SOC64_USB3_MISC_CTRL_REG0); + reg_val |= FIELD_PREP(SYSMGR_SOC64_USB3_MISC_CTRL_REG0_RESET_PUL_OVR, + SET_USB3_MISC_CTRL_REG0_PORT_RESET_PUL_OVR); + reg_val |= FIELD_PREP(SYSMGR_SOC64_USB3_MISC_CTRL_REG0_PORT_OVR_CURR, + SET_USB3_MISC_CTRL_REG0_PORT_OVR_CURR_BIT_1); + writel(reg_val, socfpga_get_sysmgr_addr() + SYSMGR_SOC64_USB3_MISC_CTRL_REG0); +} +#endif + /* * Configure all the pin muxes */ @@ -18,6 +38,10 @@ void sysmgr_pinmux_init(void) { populate_sysmgr_pinmux(); populate_sysmgr_fpgaintf_module(); + +#if IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX5) + sysmgr_config_usb3(); +#endif } /* -- cgit v1.2.3 From 3ce8a0e9115eaa0cdfc142459814b2283cf01785 Mon Sep 17 00:00:00 2001 From: Chance Yang Date: Tue, 26 Aug 2025 11:36:17 +0800 Subject: fastboot: Fix has-slot command always returning yes for fb_nand The issue was a mismatch in return value conventions between functions: - getvar_get_part_info() expects >= 0 for success - fb_nand_lookup() returns 0 on success, 1 on failure (from mtdparts_init and find_dev_and_part) When partition didn't exist, fb_nand_lookup returned 1, but fastboot_nand_get_part_info passed it directly to getvar_get_part_info, which treated 1 >= 0 as success, causing has-slot to always return yes. Fix by converting positive return values to -ENOENT in fastboot_nand_get_part_info to match the expected error convention. Signed-off-by: Chance Yang Reviewed-by: Mattijs Korpershoek Link: https://lore.kernel.org/r/20250826-master-v2-1-30b787a2f9fd@kneron.us Signed-off-by: Mattijs Korpershoek --- drivers/fastboot/fb_nand.c | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/drivers/fastboot/fb_nand.c b/drivers/fastboot/fb_nand.c index afc64fd5280..6df3917e129 100644 --- a/drivers/fastboot/fb_nand.c +++ b/drivers/fastboot/fb_nand.c @@ -157,8 +157,13 @@ int fastboot_nand_get_part_info(const char *part_name, struct part_info **part_info, char *response) { struct mtd_info *mtd = NULL; + int ret; + + ret = fb_nand_lookup(part_name, &mtd, part_info, response); + if (ret) + return -ENOENT; - return fb_nand_lookup(part_name, &mtd, part_info, response); + return ret; } /** -- cgit v1.2.3 From f58667587243ce652aaa7d0dd6557a2fb2da5020 Mon Sep 17 00:00:00 2001 From: Andrew Goodbody Date: Mon, 29 Sep 2025 17:25:23 +0100 Subject: usb: gadget: atmel: Add missing null check Add in the missing null check for udc->driver that is present at other points in the function before it is dereferenced. This issue was found by Smatch. Signed-off-by: Andrew Goodbody Reviewed-by: Mattijs Korpershoek Reviewed-by: Marek Vasut Link: https://lore.kernel.org/r/20250929-atmel_usba_udc-v1-1-e1426271e12a@linaro.org Signed-off-by: Mattijs Korpershoek --- drivers/usb/gadget/atmel_usba_udc.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/usb/gadget/atmel_usba_udc.c b/drivers/usb/gadget/atmel_usba_udc.c index 72f68dba3a7..f7a92ded6da 100644 --- a/drivers/usb/gadget/atmel_usba_udc.c +++ b/drivers/usb/gadget/atmel_usba_udc.c @@ -1147,7 +1147,7 @@ static int usba_udc_irq(struct usba_udc *udc) reset_all_endpoints(udc); if (udc->gadget.speed != USB_SPEED_UNKNOWN && - udc->driver->disconnect) { + udc->driver && udc->driver->disconnect) { udc->gadget.speed = USB_SPEED_UNKNOWN; spin_unlock(&udc->lock); udc->driver->disconnect(&udc->gadget); -- cgit v1.2.3 From 5ac61383b2db15b037e87bd353f726eafc49e181 Mon Sep 17 00:00:00 2001 From: Andrew Goodbody Date: Mon, 29 Sep 2025 17:40:43 +0100 Subject: usb: dwc2: Add missing null check Add in the missing null check for dev->driver that is present at other points in the function before it is dereferenced. This issue was found by Smatch. Signed-off-by: Andrew Goodbody Reviewed-by: Mattijs Korpershoek Reviewed-by: Marek Vasut Link: https://lore.kernel.org/r/20250929-usb_dwc2-v1-1-863133dcbcde@linaro.org Signed-off-by: Mattijs Korpershoek --- drivers/usb/gadget/dwc2_udc_otg_xfer_dma.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/usb/gadget/dwc2_udc_otg_xfer_dma.c b/drivers/usb/gadget/dwc2_udc_otg_xfer_dma.c index fca052b4556..5a7f50ebaa5 100644 --- a/drivers/usb/gadget/dwc2_udc_otg_xfer_dma.c +++ b/drivers/usb/gadget/dwc2_udc_otg_xfer_dma.c @@ -526,7 +526,7 @@ static int dwc2_udc_irq(int irq, void *_dev) if (gotgint & GOTGINT_SES_END_DET) { debug_cond(DEBUG_ISR, "\t\tSession End Detected\n"); /* Let gadget detect disconnected state */ - if (dev->driver->disconnect) { + if (dev->driver && dev->driver->disconnect) { spin_unlock_irqrestore(&dev->lock, flags); dev->driver->disconnect(&dev->gadget); spin_lock_irqsave(&dev->lock, flags); -- cgit v1.2.3 From 8cd4a5e94ba2ab73fde3301d6314549dd5a25cb4 Mon Sep 17 00:00:00 2001 From: Andrew Goodbody Date: Mon, 29 Sep 2025 10:11:57 +0100 Subject: usb: dwc3: Remove redundant test In dwc3_ep0_complete_data there is a test for 'r' being null and the code will return at that point if so. After that point 'r' is guaranteed to not be null and testing for that is redundant. Remove the test for 'r' being non-null. This issue was found by Smatch. Signed-off-by: Andrew Goodbody Reviewed-by: Mattijs Korpershoek Reviewed-by: Marek Vasut Link: https://lore.kernel.org/r/20250929-dwc3_ep0-v1-1-1d5c58933bde@linaro.org Signed-off-by: Mattijs Korpershoek --- drivers/usb/dwc3/ep0.c | 5 +---- 1 file changed, 1 insertion(+), 4 deletions(-) diff --git a/drivers/usb/dwc3/ep0.c b/drivers/usb/dwc3/ep0.c index c656cbe25ce..680756532f0 100644 --- a/drivers/usb/dwc3/ep0.c +++ b/drivers/usb/dwc3/ep0.c @@ -799,10 +799,7 @@ static void dwc3_ep0_complete_data(struct dwc3 *dwc, status = DWC3_TRB_SIZE_TRBSTS(trb->size); if (status == DWC3_TRBSTS_SETUP_PENDING) { dev_dbg(dwc->dev, "Setup Pending received"); - - if (r) - dwc3_gadget_giveback(ep0, r, -ECONNRESET); - + dwc3_gadget_giveback(ep0, r, -ECONNRESET); return; } -- cgit v1.2.3 From 1a367adfd66c28d8d2fdb2957dfba5434b987de1 Mon Sep 17 00:00:00 2001 From: Neil Armstrong Date: Fri, 2 May 2025 08:51:45 +0200 Subject: net: mdio: mux-meson-gxl: set reversed bit when using internal phy This bit is necessary to receive packets from the internal PHY. Without this bit set, no activity occurs on the interface. Normally u-boot sets this bit, but if u-boot is compiled without net support, the interface will be up but without any activity. The vendor SDK sets this bit along with the PHY_ID bits. Ported from the Linux change at [1] from Da Xu merged in commit [2]. [1] https://lore.kernel.org/all/20250425192009.1439508-1-da@libre.computer/ [2] b23285e93bef ("net: mdio: mux-meson-gxl: set reversed bit when using internal phy") Suggested-by: Da Xue Link: https://lore.kernel.org/r/20250502-u-boot-topic-mdio-mux-gxl-bit28-v1-1-399f6c3db154@linaro.org Signed-off-by: Neil Armstrong --- drivers/net/mdio_mux_meson_gxl.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/net/mdio_mux_meson_gxl.c b/drivers/net/mdio_mux_meson_gxl.c index 8ef3ae598b7..31898ed437e 100644 --- a/drivers/net/mdio_mux_meson_gxl.c +++ b/drivers/net/mdio_mux_meson_gxl.c @@ -19,6 +19,7 @@ #define REG2_LEDACT GENMASK(23, 22) #define REG2_LEDLINK GENMASK(25, 24) #define REG2_DIV4SEL BIT(27) +#define REG2_REVERSED BIT(28) #define REG2_ADCBYPASS BIT(30) #define REG2_CLKINSEL BIT(31) #define ETH_REG3 0x4 @@ -66,7 +67,7 @@ static int meson_gxl_enable_internal_mdio(struct mdio_mux_meson_gxl_priv *priv) * The only constraint is that it must match the one in * drivers/net/phy/meson-gxl.c to properly match the PHY. */ - writel(FIELD_PREP(REG2_PHYID, EPHY_GXL_ID), + writel(REG2_REVERSED | FIELD_PREP(REG2_PHYID, EPHY_GXL_ID), priv->regs + ETH_REG2); /* Enable the internal phy */ -- cgit v1.2.3 From 033dbc7f9ec969168a2f48766cb16aa26fa381d8 Mon Sep 17 00:00:00 2001 From: Yang Xiwen Date: Tue, 17 Jun 2025 01:01:17 +0800 Subject: pinctrl: meson: support gpio toggle command meson_gpio_get() always assumes gpio is configured to input mode. This is incorrect and breaks `gpio toggle` command: gpio: pin aobus-banks2 (gpio 2) value is 0 Warning: value of pin is still 1 Fix it by adding the logic to handle both input and output mode. Fixes: 2009a8d03fe5 ("pinctrl: meson: add GPIO support") Signed-off-by: Yang Xiwen Reviewed-by: Neil Armstrong Link: https://lore.kernel.org/r/20250617-meson_ppinctrl-v3-1-218d9321a8d2@outlook.com Signed-off-by: Neil Armstrong --- drivers/pinctrl/meson/pinctrl-meson.c | 20 +++++++++++++++++++- 1 file changed, 19 insertions(+), 1 deletion(-) diff --git a/drivers/pinctrl/meson/pinctrl-meson.c b/drivers/pinctrl/meson/pinctrl-meson.c index babf1bccc96..7dbaf966f93 100644 --- a/drivers/pinctrl/meson/pinctrl-meson.c +++ b/drivers/pinctrl/meson/pinctrl-meson.c @@ -117,8 +117,26 @@ int meson_gpio_get(struct udevice *dev, unsigned int offset) struct meson_pinctrl *priv = dev_get_priv(dev->parent); unsigned int reg, bit; int ret; + enum gpio_func_t direction; + enum meson_reg_type reg_type; - ret = meson_gpio_calc_reg_and_bit(dev->parent, offset, REG_IN, ®, + direction = meson_gpio_get_direction(dev, offset); + + switch (direction) { + case GPIOF_INPUT: + reg_type = REG_IN; + break; + + case GPIOF_OUTPUT: + reg_type = REG_OUT; + break; + + default: + dev_warn(dev, "Failed to get current direction of Pin %u\n", offset); + return -EINVAL; + } + + ret = meson_gpio_calc_reg_and_bit(dev->parent, offset, reg_type, ®, &bit); if (ret) return ret; -- cgit v1.2.3 From b332723882f82f6feff027fb733c4b7e43bdef80 Mon Sep 17 00:00:00 2001 From: Andrew Goodbody Date: Tue, 22 Jul 2025 15:06:14 +0100 Subject: adc: meson-saradc: uint cannot be less than zero timeout is declared as a uint but then tested for being less than zero which must always fail. Change the while loop for a pre-decrement on timeout and test timeout for being zero. This issue was found by Smatch. Signed-off-by: Andrew Goodbody Reviewed-by: Neil Armstrong Link: https://lore.kernel.org/r/20250722-meson_saradc-v1-1-1ab45d53da9d@linaro.org Signed-off-by: Neil Armstrong --- drivers/adc/meson-saradc.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/drivers/adc/meson-saradc.c b/drivers/adc/meson-saradc.c index 60e348968fb..0144ff828c5 100644 --- a/drivers/adc/meson-saradc.c +++ b/drivers/adc/meson-saradc.c @@ -205,9 +205,9 @@ static int meson_saradc_lock(struct meson_saradc_priv *priv) do { udelay(1); regmap_read(priv->regmap, MESON_SAR_ADC_DELAY, &val); - } while (val & MESON_SAR_ADC_DELAY_BL30_BUSY && timeout--); + } while (val & MESON_SAR_ADC_DELAY_BL30_BUSY && --timeout); - if (timeout < 0) { + if (!timeout) { printf("Timeout while waiting for BL30 unlock\n"); return -ETIMEDOUT; } @@ -256,9 +256,9 @@ static int meson_saradc_wait_busy_clear(struct meson_saradc_priv *priv) do { udelay(1); regmap_read(priv->regmap, MESON_SAR_ADC_REG0, ®val); - } while (FIELD_GET(MESON_SAR_ADC_REG0_BUSY_MASK, regval) && timeout--); + } while (FIELD_GET(MESON_SAR_ADC_REG0_BUSY_MASK, regval) && --timeout); - if (timeout < 0) + if (!timeout) return -ETIMEDOUT; return 0; -- cgit v1.2.3 From bb2d7ea6f2a8b9539f9daf526b5f87c29ce413b4 Mon Sep 17 00:00:00 2001 From: Andrew Goodbody Date: Wed, 23 Jul 2025 17:37:24 +0100 Subject: clk: meson: Remove unreachable code A second return following the first return is unreachable code so remove it. This issue was found by Smatch. Signed-off-by: Andrew Goodbody Reviewed-by: Neil Armstrong Link: https://lore.kernel.org/r/20250723-clk_meson-v1-1-8cd6e73145a4@linaro.org Signed-off-by: Neil Armstrong --- drivers/clk/meson/g12a.c | 2 -- 1 file changed, 2 deletions(-) diff --git a/drivers/clk/meson/g12a.c b/drivers/clk/meson/g12a.c index 5d7faaa3eab..a7a42b2edb6 100644 --- a/drivers/clk/meson/g12a.c +++ b/drivers/clk/meson/g12a.c @@ -916,8 +916,6 @@ static ulong meson_clk_set_rate_by_id(struct clk *clk, unsigned long id, return -EINVAL; case CLKID_PCIE_PLL: return meson_pcie_pll_set_rate(clk, rate); - - return 0; case CLKID_VPU: return meson_clk_set_rate_by_id(clk, meson_mux_get_parent(clk, CLKID_VPU), rate, -- cgit v1.2.3 From b1e2cbd65cdfbc32c222eccedac11f53390694cf Mon Sep 17 00:00:00 2001 From: Andrew Goodbody Date: Fri, 8 Aug 2025 10:34:43 +0100 Subject: pwm: meson: Stop premature exit from for loop In meson_pwm_probe the for loop attempts to get the name of a clock but the following if..else statements only perform useful work if -ENODATA is returned from clk_get_by_name. If clk_get_by_name simply succeeds then this results in a premature exit from the for loop and the following code can never be reached. Make the else clause only apply for an error return from clk_get_by_name. This issue was found by Smatch. Signed-off-by: Andrew Goodbody Reviewed-by: Neil Armstrong Link: https://lore.kernel.org/r/20250808-pwm_meson-v1-1-cddb7e5f76bd@linaro.org Signed-off-by: Neil Armstrong --- drivers/pwm/pwm-meson.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/pwm/pwm-meson.c b/drivers/pwm/pwm-meson.c index c2597d8b669..caa7af085fa 100644 --- a/drivers/pwm/pwm-meson.c +++ b/drivers/pwm/pwm-meson.c @@ -359,8 +359,9 @@ static int meson_pwm_probe(struct udevice *dev) /* We have our source clock, do not alter HW clock mux */ continue; - } else + } else if (err) { return err; + } /* Get id in list */ for (p = 0 ; p < data->num_parents ; ++p) { -- cgit v1.2.3 From d521fa32cc692a44c7c11d4b2a86f371d614e727 Mon Sep 17 00:00:00 2001 From: Viacheslav Bocharov Date: Wed, 3 Sep 2025 14:06:03 +0300 Subject: ARM: amlogic: fix JetHub D1 eth mac fallback generation JetHome has allocated a special range for MAC fallback on JetHub D1/D1+ devices. Signed-off-by: Viacheslav Bocharov Link: https://lore.kernel.org/r/20250903110726.546083-1-adeep@lexina.in Signed-off-by: Neil Armstrong --- board/amlogic/jethub-j100/jethub-j100.c | 22 +++++++++------------- 1 file changed, 9 insertions(+), 13 deletions(-) diff --git a/board/amlogic/jethub-j100/jethub-j100.c b/board/amlogic/jethub-j100/jethub-j100.c index 9e87fb9f9d7..79732864d03 100644 --- a/board/amlogic/jethub-j100/jethub-j100.c +++ b/board/amlogic/jethub-j100/jethub-j100.c @@ -19,21 +19,17 @@ int misc_init_r(void) { u8 mac_addr[ARP_HLEN + 1]; char serial[SM_SERIAL_SIZE]; - u32 sid; + u16 sid; if (!meson_sm_get_serial(serial, SM_SERIAL_SIZE)) { - sid = crc32(0, (unsigned char *)serial, SM_SERIAL_SIZE); - /* Ensure the NIC specific bytes of the mac are not all 0 */ - if ((sid & 0xffff) == 0) - sid |= 0x800000; - - /* OUI registered MAC address */ - mac_addr[0] = 0x10; - mac_addr[1] = 0x27; - mac_addr[2] = 0xBE; - mac_addr[3] = (sid >> 16) & 0xff; - mac_addr[4] = (sid >> 8) & 0xff; - mac_addr[5] = (sid >> 0) & 0xff; + sid = crc32(0, (unsigned char *)serial, SM_SERIAL_SIZE) & 0xFFFF; + /* OUI registered fallback MAC address */ + mac_addr[0] = 0xF0; + mac_addr[1] = 0x57; + mac_addr[2] = 0x8D; + mac_addr[3] = 0x00; + mac_addr[4] = (sid >> 8) & 0xFF; + mac_addr[5] = sid & 0xFF; mac_addr[ARP_HLEN] = '\0'; eth_env_set_enetaddr("ethaddr", mac_addr); -- cgit v1.2.3 From e589d5822cac10915ec04e8d9044d2460aec8924 Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Mon, 22 Sep 2025 18:03:39 +0200 Subject: env: spi: Fix gd->env_valid for the first write When both SPI environment locations are invalid (gd->env_valid == ENV_INVALID), the first call to saveenv writes to the primary location and sets the active flag. However, the logic for updating gd->env_valid incorrectly sets it to ENV_REDUND, which does not match the actual location written. This causes the first two writes to target the same location, and alternation only begins after the second write. Update the logic to alternate gd->env_valid based on whether the last write was to the primary or redundant location, ensuring the first write sets ENV_VALID and subsequent writes alternate as expected. This aligns env_valid with the actual storage location and fixes the alternation sequence from the first write. With this change, the "Valid environment" printout correctly reflects the active location after each save, and the alternation between primary and redundant locations works as intended from the start. Signed-off-by: Michal Simek Reviewed-by: Marek Vasut Acked-by: E Shattow --- env/sf.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/env/sf.c b/env/sf.c index 0b70e18b9af..0e27a020643 100644 --- a/env/sf.c +++ b/env/sf.c @@ -148,7 +148,7 @@ static int env_sf_save(void) puts("done\n"); - gd->env_valid = gd->env_valid == ENV_REDUND ? ENV_VALID : ENV_REDUND; + gd->env_valid = gd->env_valid == ENV_VALID ? ENV_REDUND : ENV_VALID; printf("Valid environment: %d\n", (int)gd->env_valid); -- cgit v1.2.3 From 8fd3768ca1683b45aeb5662094de6bcffdb7735b Mon Sep 17 00:00:00 2001 From: Anshul Dalal Date: Tue, 16 Sep 2025 16:52:05 +0530 Subject: arm: armv8: remove redundant definition of mmu_status mmu_status is used in io memcpy functions to prevent accesses to non 8-byte aligned addresses when the mmu is disabled. Though there is a redundant definition enabled when icaches is turned off by setting SYS_ICACHE_OFF. This patch removes the redundant definition, allowing mmu_status to properly report the status regardless of config settings. This shouldn't be a problem since access to non 8-byte aligned data can be done irrespective of icache state. Fixes: 268f6ac1f95c ("arm64: Update memcpy_{from, to}io() helpers") Signed-off-by: Anshul Dalal Reviewed-by: Patrice Chotard Reviewed-by: Dhruva Gole Acked-by: Ilias Apalodimas --- arch/arm/cpu/armv8/cache_v8.c | 15 +++++---------- 1 file changed, 5 insertions(+), 10 deletions(-) diff --git a/arch/arm/cpu/armv8/cache_v8.c b/arch/arm/cpu/armv8/cache_v8.c index 1c1e33bec24..a7899857658 100644 --- a/arch/arm/cpu/armv8/cache_v8.c +++ b/arch/arm/cpu/armv8/cache_v8.c @@ -1134,11 +1134,6 @@ int icache_status(void) return (get_sctlr() & CR_I) != 0; } -int mmu_status(void) -{ - return (get_sctlr() & CR_M) != 0; -} - void invalidate_icache_all(void) { __asm_invalidate_icache_all(); @@ -1160,17 +1155,17 @@ int icache_status(void) return 0; } -int mmu_status(void) -{ - return 0; -} - void invalidate_icache_all(void) { } #endif /* !CONFIG_IS_ENABLED(SYS_ICACHE_OFF) */ +int mmu_status(void) +{ + return (get_sctlr() & CR_M) != 0; +} + /* * Enable dCache & iCache, whether cache is actually enabled * depend on CONFIG_SYS_DCACHE_OFF and CONFIG_SYS_ICACHE_OFF -- cgit v1.2.3 From 5c9dffa40525e86d3b511a53bde0f43b72cf0719 Mon Sep 17 00:00:00 2001 From: Wolfgang Wallner Date: Fri, 19 Sep 2025 15:43:00 +0200 Subject: configs: brcp1: Drop CONFIG_SUPPORT_PASSING_ATAGS CONFIG_SUPPORT_PASSING_ATAGS is not needed for these boards. Signed-off-by: Wolfgang Wallner --- configs/brcp1_1r_defconfig | 2 -- configs/brcp1_1r_switch_defconfig | 2 -- configs/brcp1_2r_defconfig | 2 -- 3 files changed, 6 deletions(-) diff --git a/configs/brcp1_1r_defconfig b/configs/brcp1_1r_defconfig index 684800228ef..568313d4860 100644 --- a/configs/brcp1_1r_defconfig +++ b/configs/brcp1_1r_defconfig @@ -3,8 +3,6 @@ CONFIG_SYS_VENDOR="BuR" CONFIG_SYS_CONFIG_NAME="brzynq" CONFIG_SYS_L2CACHE_OFF=y CONFIG_ARCH_ZYNQ=y -CONFIG_SUPPORT_PASSING_ATAGS=y -CONFIG_INITRD_TAG=y CONFIG_TEXT_BASE=0x4000000 CONFIG_SYS_MALLOC_F_LEN=0x1000 CONFIG_SPL_GPIO=y diff --git a/configs/brcp1_1r_switch_defconfig b/configs/brcp1_1r_switch_defconfig index 9b45961ef8e..805de796df6 100644 --- a/configs/brcp1_1r_switch_defconfig +++ b/configs/brcp1_1r_switch_defconfig @@ -3,8 +3,6 @@ CONFIG_SYS_VENDOR="BuR" CONFIG_SYS_CONFIG_NAME="brzynq" CONFIG_SYS_L2CACHE_OFF=y CONFIG_ARCH_ZYNQ=y -CONFIG_SUPPORT_PASSING_ATAGS=y -CONFIG_INITRD_TAG=y CONFIG_TEXT_BASE=0x4000000 CONFIG_SYS_MALLOC_F_LEN=0x1000 CONFIG_SPL_GPIO=y diff --git a/configs/brcp1_2r_defconfig b/configs/brcp1_2r_defconfig index 357eef38601..e92d8381bbb 100644 --- a/configs/brcp1_2r_defconfig +++ b/configs/brcp1_2r_defconfig @@ -3,8 +3,6 @@ CONFIG_SYS_VENDOR="BuR" CONFIG_SYS_CONFIG_NAME="brzynq" CONFIG_SYS_L2CACHE_OFF=y CONFIG_ARCH_ZYNQ=y -CONFIG_SUPPORT_PASSING_ATAGS=y -CONFIG_INITRD_TAG=y CONFIG_TEXT_BASE=0x4000000 CONFIG_SYS_MALLOC_F_LEN=0x1000 CONFIG_SPL_GPIO=y -- cgit v1.2.3 From 92c2effbbfb7b03f93f988273550f6b6079fecdc Mon Sep 17 00:00:00 2001 From: Wolfgang Wallner Date: Fri, 19 Sep 2025 15:43:01 +0200 Subject: configs: brcp150: Drop CONFIG_SUPPORT_PASSING_ATAGS CONFIG_SUPPORT_PASSING_ATAGS is not needed for this board. Signed-off-by: Wolfgang Wallner --- configs/brcp150_defconfig | 2 -- 1 file changed, 2 deletions(-) diff --git a/configs/brcp150_defconfig b/configs/brcp150_defconfig index 6d2b92e1ec3..bae185e8126 100644 --- a/configs/brcp150_defconfig +++ b/configs/brcp150_defconfig @@ -3,8 +3,6 @@ CONFIG_SYS_VENDOR="BuR" CONFIG_SYS_CONFIG_NAME="brzynq" CONFIG_SYS_L2CACHE_OFF=y CONFIG_ARCH_ZYNQ=y -CONFIG_SUPPORT_PASSING_ATAGS=y -CONFIG_INITRD_TAG=y CONFIG_TEXT_BASE=0x4000000 CONFIG_SYS_MALLOC_F_LEN=0x1000 CONFIG_SPL_GPIO=y -- cgit v1.2.3 From de8f3868102e420eb229b090597101d5f46dea2e Mon Sep 17 00:00:00 2001 From: Wolfgang Wallner Date: Fri, 19 Sep 2025 15:43:02 +0200 Subject: configs: brcp170: Drop CONFIG_SUPPORT_PASSING_ATAGS CONFIG_SUPPORT_PASSING_ATAGS is not needed for this board. Signed-off-by: Wolfgang Wallner --- configs/brcp170_defconfig | 2 -- 1 file changed, 2 deletions(-) diff --git a/configs/brcp170_defconfig b/configs/brcp170_defconfig index 44460c510f1..f8e17ece276 100644 --- a/configs/brcp170_defconfig +++ b/configs/brcp170_defconfig @@ -3,8 +3,6 @@ CONFIG_SYS_VENDOR="BuR" CONFIG_SYS_CONFIG_NAME="brzynq" CONFIG_SYS_L2CACHE_OFF=y CONFIG_ARCH_ZYNQ=y -CONFIG_SUPPORT_PASSING_ATAGS=y -CONFIG_INITRD_TAG=y CONFIG_TEXT_BASE=0x4000000 CONFIG_SYS_MALLOC_F_LEN=0x1000 CONFIG_SPL_GPIO=y -- cgit v1.2.3 From 70ae44f3713427be5368d0829b97cafbd01ef1f5 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Mon, 22 Sep 2025 14:29:22 +0200 Subject: linux/kernel.h: Update upper_NN_bits() and lower_NN_bits() macros Synchronize upper_NN_bits() and lower_NN_bits() macros with Linux 6.16 commit 118d777c4cb4 ("wordpart.h: Add REPEAT_BYTE_U32()"). This fixes the lower_32_bits() macros and assures it works with 64bit systems correctly. This also adds 16bit variants of these macros, which will be used by the Airoha PHY driver. Signed-off-by: Marek Vasut Reviewed-by: Tom Rini --- include/linux/kernel.h | 14 +++++++++++++- 1 file changed, 13 insertions(+), 1 deletion(-) diff --git a/include/linux/kernel.h b/include/linux/kernel.h index e0443ecac84..44a639a5e4e 100644 --- a/include/linux/kernel.h +++ b/include/linux/kernel.h @@ -111,7 +111,19 @@ * lower_32_bits - return bits 0-31 of a number * @n: the number we're accessing */ -#define lower_32_bits(n) ((u32)(n)) +#define lower_32_bits(n) ((u32)((n) & 0xffffffff)) + +/** + * upper_16_bits - return bits 16-31 of a number + * @n: the number we're accessing + */ +#define upper_16_bits(n) ((u16)((n) >> 16)) + +/** + * lower_16_bits - return bits 0-15 of a number + * @n: the number we're accessing + */ +#define lower_16_bits(n) ((u16)((n) & 0xffff)) /* * abs() handles unsigned and signed longs, ints, shorts and chars. For all -- cgit v1.2.3 From 601cebc29d2a41846bbad36453b97b065db656dd Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Mon, 15 Sep 2025 13:05:48 -0600 Subject: cmd: spl: Remove ATAG support from this command While we continue to have some systems which support extremely legacy OS booting methods, we do not have use cases for supporting this in Falcon mode anymore. Remove this support and references from the documentation. Co-developed-by: Anshul Dalal Signed-off-by: Tom Rini --- arch/arm/lib/spl.c | 3 +- arch/powerpc/lib/spl.c | 3 +- cmd/spl.c | 23 ++------------ doc/README.commands.spl | 14 ++------- doc/develop/falcon.rst | 84 +++++-------------------------------------------- include/cmd_spl.h | 3 +- 6 files changed, 15 insertions(+), 115 deletions(-) diff --git a/arch/arm/lib/spl.c b/arch/arm/lib/spl.c index c43a63f1819..6c7d1fb5629 100644 --- a/arch/arm/lib/spl.c +++ b/arch/arm/lib/spl.c @@ -46,8 +46,7 @@ void __weak board_init_f(ulong dummy) } /* - * This function jumps to an image with argument. Normally an FDT or ATAGS - * image. + * This function jumps to an image with argument, usually an FDT. */ #if CONFIG_IS_ENABLED(OS_BOOT) #ifdef CONFIG_ARM64 diff --git a/arch/powerpc/lib/spl.c b/arch/powerpc/lib/spl.c index 3a24cbfff3b..a2bf52c5adc 100644 --- a/arch/powerpc/lib/spl.c +++ b/arch/powerpc/lib/spl.c @@ -9,8 +9,7 @@ #include /* - * This function jumps to an image with argument. Normally an FDT or ATAGS - * image. + * This function jumps to an image with argument, usually an FDT. */ #ifdef CONFIG_SPL_OS_BOOT void __noreturn jump_to_image_linux(struct spl_image_info *spl_image) diff --git a/cmd/spl.c b/cmd/spl.c index 379b512f1ff..f591dc07fb6 100644 --- a/cmd/spl.c +++ b/cmd/spl.c @@ -27,19 +27,6 @@ static const char **subcmd_list[] = { "cmdline", "bdt", "prep", -#endif - NULL, - }, - [SPL_EXPORT_ATAGS] = (const char * []) { -#ifdef CONFIG_SUPPORT_PASSING_ATAGS - "start", - "loados", -#ifdef CONFIG_SYS_BOOT_RAMDISK_HIGH - "ramdisk", -#endif - "cmdline", - "bdt", - "prep", #endif NULL, }, @@ -96,7 +83,6 @@ static int call_bootm(int argc, char *const argv[], const char *subcommand[]) static struct cmd_tbl cmd_spl_export_sub[] = { U_BOOT_CMD_MKENT(fdt, 0, 1, (void *)SPL_EXPORT_FDT, "", ""), - U_BOOT_CMD_MKENT(atags, 0, 1, (void *)SPL_EXPORT_ATAGS, "", ""), }; static int spl_export(struct cmd_tbl *cmdtp, int flag, int argc, @@ -128,10 +114,6 @@ static int spl_export(struct cmd_tbl *cmdtp, int flag, int argc, #endif break; #endif - case SPL_EXPORT_ATAGS: - printf("Argument image is now in RAM at: 0x%p\n", - (void *)gd->bd->bi_boot_params); - break; } } else { /* Unrecognized command */ @@ -176,11 +158,10 @@ static int do_spl(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]) U_BOOT_CMD( spl, 6 , 1, do_spl, "SPL configuration", - "export [kernel_addr] [initrd_addr] [fdt_addr]\n" - "\timg\t\t\"atags\" or \"fdt\"\n" + "export fdt [kernel_addr] [initrd_addr] [fdt_addr]\n" "\tkernel_addr\taddress where a kernel image is stored.\n" "\t\t\tkernel is loaded as part of the boot process, but it is not started.\n" "\tinitrd_addr\taddress of initial ramdisk\n" "\t\t\tcan be set to \"-\" if fdt_addr without initrd_addr is used.\n" - "\tfdt_addr\tin case of fdt, the address of the device tree.\n" + "\tfdt_addr\tthe address of the device tree.\n" ); diff --git a/doc/README.commands.spl b/doc/README.commands.spl index ecfd3ca9ee5..54cc5b1ec42 100644 --- a/doc/README.commands.spl +++ b/doc/README.commands.spl @@ -5,24 +5,16 @@ SUBCOMMAND EXPORT To execute the command everything has to be in place as if bootm should be used. (kernel image, initrd-image, fdt-image etc.) -export has two subcommands: - atags: exports the ATAGS +export has one subcommand: fdt: exports the FDT Call is: -spl export [kernel_addr] [initrd_addr] [fdt_addr if fdt] +spl export fdt [kernel_addr] [initrd_addr] [fdt_addr if fdt] TYPICAL CALL -on OMAP3: -nandecc hw -nand read 0x82000000 0x280000 0x400000 /* Read kernel image from NAND*/ -spl export atags /* export ATAGS */ -nand erase 0x680000 0x20000 /* erase - one page */ -nand write 0x80000100 0x680000 0x20000 /* write the image - one page */ - -call with FDT: +on OMAP3 with FDT: nandecc hw nand read 0x82000000 0x280000 0x400000 /* Read kernel image from NAND*/ tftpboot 0x80000100 devkit8000.dtb /* Read fdt */ diff --git a/doc/develop/falcon.rst b/doc/develop/falcon.rst index 244b4ccb5c2..5689d5b93a7 100644 --- a/doc/develop/falcon.rst +++ b/doc/develop/falcon.rst @@ -22,7 +22,7 @@ copies U-Boot image into the memory. The Falcon Mode extends this way allowing to start the Linux kernel directly from SPL. A new command is added to U-Boot to prepare the parameters that SPL -must pass to the kernel, using ATAGS or Device Tree. +must pass to the kernel using a Device Tree. In normal mode, these parameters are generated each time before loading the kernel, passing to Linux the address in memory where @@ -117,10 +117,7 @@ spl - SPL configuration Usage:: - spl export [kernel_addr] [initrd_addr] [fdt_addr ] - -img - "atags" or "fdt" + spl export fdt [kernel_addr] [initrd_addr] [fdt_addr ] kernel_addr kernel is loaded as part of the boot process, but it is not started. @@ -134,11 +131,11 @@ fdt_addr in case of fdt, the address of the device tree. The *spl export* command does not write to a storage media. The user is -responsible to transfer the gathered information (assembled ATAGS list -or prepared FDT) from temporary storage in RAM into persistent storage -after each run of *spl export*. Unfortunately the position of temporary -storage can not be predicted nor provided at command line, it depends -highly on your system setup and your provided data (ATAGS or FDT). +responsible to transfer the gathered information (prepared FDT) from temporary +storage in RAM into persistent storage after each run of *spl export*. +Unfortunately the position of temporary storage can not be predicted nor +provided at command line, it depends highly on your system setup and your +provided device tree. However at the end of an successful *spl export* run it will print the RAM address of temporary storage. The RAM address of FDT will also be set in the environment variable *fdtargsaddr*, the new length of the @@ -152,73 +149,6 @@ to the pre-defined address in persistent storage The following example shows how to prepare the data for Falcon Mode on twister board with ATAGS BLOB. -The *spl export* command is prepared to work with ATAGS and FDT. However, -using FDT is at the moment untested. The ppc port (see a3m071 example -later) prepares the fdt blob with the fdt command instead. - - -Usage on the twister board --------------------------- - -Using mtd names with the following (default) configuration -for mtdparts:: - - device nand0 , # parts = 9 - #: name size offset mask_flags - 0: MLO 0x00080000 0x00000000 0 - 1: u-boot 0x00100000 0x00080000 0 - 2: env1 0x00040000 0x00180000 0 - 3: env2 0x00040000 0x001c0000 0 - 4: kernel 0x00600000 0x00200000 0 - 5: bootparms 0x00040000 0x00800000 0 - 6: splashimg 0x00200000 0x00840000 0 - 7: mini 0x02800000 0x00a40000 0 - 8: rootfs 0x1cdc0000 0x03240000 0 - -:: - - twister => nand read 82000000 kernel - - NAND read: device 0 offset 0x200000, size 0x600000 - 6291456 bytes read: OK - -Now the kernel is in RAM at address 0x82000000:: - - twister => spl export atags 0x82000000 - ## Booting kernel from Legacy Image at 82000000 ... - Image Name: Linux-3.5.0-rc4-14089-gda0b7f4 - Image Type: ARM Linux Kernel Image (uncompressed) - Data Size: 3654808 Bytes = 3.5 MiB - Load Address: 80008000 - Entry Point: 80008000 - Verifying Checksum ... OK - Loading Kernel Image ... OK - OK - cmdline subcommand not supported - bdt subcommand not supported - Argument image is now in RAM at: 0x80000100 - -The result can be checked at address 0x80000100:: - - twister => md 0x80000100 - 80000100: 00000005 54410001 00000000 00000000 ......AT........ - 80000110: 00000000 00000067 54410009 746f6f72 ....g.....ATroot - 80000120: 65642f3d 666e2f76 77722073 73666e20 =/dev/nfs rw nfs - -The parameters generated with this step can be saved into NAND at the offset -0x800000 (value for twister for CONFIG_CMD_SPL_NAND_OFS):: - - nand erase.part bootparms - nand write 0x80000100 bootparms 0x4000 - -Now the parameters are stored into the NAND flash at the address -CONFIG_CMD_SPL_NAND_OFS (=0x800000). - -Next time, the board can be started into Falcon Mode moving the -setting the GPIO (on twister GPIO 55 is used) to kernel mode. - -The kernel is loaded directly by the SPL without passing through U-Boot. - Example with FDT: a3m071 board ------------------------------ diff --git a/include/cmd_spl.h b/include/cmd_spl.h index 51ec12edb90..45ea91e9bce 100644 --- a/include/cmd_spl.h +++ b/include/cmd_spl.h @@ -8,7 +8,6 @@ #define SPL_EXPORT (0x00000001) #define SPL_EXPORT_FDT (0x00000001) -#define SPL_EXPORT_ATAGS (0x00000002) -#define SPL_EXPORT_LAST SPL_EXPORT_ATAGS +#define SPL_EXPORT_LAST SPL_EXPORT_FDT #endif /* _NAND_SPL_H_ */ -- cgit v1.2.3 From f4dd112a3822c86175d091362f5cce1029f0523b Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Wed, 1 Oct 2025 08:20:07 +0200 Subject: usb: onboard-hub: Make i2c-bus optional DT binding doesn't mandate i2c-bus as required property because hub itself doesn't need to have i2c connected. It can be in standalone mode that only power regulator and reset should be handled. Or hub should be configured via spi interface. Signed-off-by: Michal Simek Reviewed-by: Marek Vasut --- common/usb_onboard_hub.c | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/common/usb_onboard_hub.c b/common/usb_onboard_hub.c index 805b2ccbc00..6fc34489a98 100644 --- a/common/usb_onboard_hub.c +++ b/common/usb_onboard_hub.c @@ -61,8 +61,13 @@ static int usb5744_i2c_init(struct udevice *dev) int ret, slave_addr; ret = dev_read_phandle_with_args(dev, "i2c-bus", NULL, 0, 0, &phandle); + if (ret == -ENOENT) { + dev_dbg(dev, "i2c-bus not specified\n"); + return 0; + } + if (ret) { - dev_err(dev, "i2c-bus not specified\n"); + dev_err(dev, "i2c-bus read failed\n"); return ret; } -- cgit v1.2.3