From b614ddb5d33556cfeefa874811484b98e05bc461 Mon Sep 17 00:00:00 2001 From: Shawn Guo Date: Mon, 2 Jan 2023 20:20:34 +0800 Subject: ddr: imx: Save the FW loading if it hasn't changed Function ddr_load_train_firmware() is called 4 times in a loop by ddr_cfg_phy(). The first 3 calls are all '1D' type and just loading the same FWs. Let's add a type check and save 2 of them. This helps to reduce DDRPHY training time from 269 ms down to 212 ms, and thus speed up boot time ~ 50 ms. Signed-off-by: Shawn Guo Reviewed-by: Fabio Estevam --- drivers/ddr/imx/phy/helper.c | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/drivers/ddr/imx/phy/helper.c b/drivers/ddr/imx/phy/helper.c index 855a874ac1e..b9b2403012d 100644 --- a/drivers/ddr/imx/phy/helper.c +++ b/drivers/ddr/imx/phy/helper.c @@ -49,6 +49,13 @@ void ddr_load_train_firmware(enum fw_type type) unsigned long imem_start = (unsigned long)_end + fw_offset; unsigned long dmem_start; unsigned long imem_len = IMEM_LEN, dmem_len = DMEM_LEN; + static enum fw_type last_type = -1; + + /* If FW doesn't change, we can save the loading. */ + if (last_type == type) + return; + + last_type = type; #ifdef CONFIG_SPL_OF_CONTROL if (gd->fdt_blob && !fdt_check_header(gd->fdt_blob)) { -- cgit v1.3.1 From 595b8be3afe54520432e1f8be8e01e3610228d42 Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Wed, 13 Dec 2023 09:16:12 -0300 Subject: imx8qm_dmsse20a1: Improve SPL memory configuration Currently, building imx8qm_dmsse20a1_defconfig leads to the following warning: aarch64-linux-ld.bfd: invalid origin for memory region .sdram Fix it by using the same SPL memory layout as done in the imx8mq_evk. Reported-by: Tom Rini Signed-off-by: Fabio Estevam Tested-by: Oliver Graute --- configs/imx8qm_dmsse20a1_defconfig | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/configs/imx8qm_dmsse20a1_defconfig b/configs/imx8qm_dmsse20a1_defconfig index 01eabc43fb3..017a5419134 100644 --- a/configs/imx8qm_dmsse20a1_defconfig +++ b/configs/imx8qm_dmsse20a1_defconfig @@ -20,6 +20,7 @@ CONFIG_TARGET_IMX8QM_DMSSE20_A1=y CONFIG_SPL_MMC=y CONFIG_SPL_SERIAL=y CONFIG_SPL_DRIVERS_MISC=y +CONFIG_SPL_STACK=0x13e000 CONFIG_SPL=y CONFIG_SYS_LOAD_ADDR=0x80280000 CONFIG_REMAKE_ELF=y @@ -32,8 +33,16 @@ CONFIG_USE_BOOTCOMMAND=y CONFIG_BOOTCOMMAND="mmc dev ${mmcdev}; if mmc rescan; then if run loadbootscript; then run bootscript; else if run loadimage; then run mmcboot; else run netboot; fi; fi; else booti ${loadaddr} - ${fdt_addr}; fi" CONFIG_LOG=y # CONFIG_DISPLAY_CPUINFO is not set +CONFIG_SPL_SYS_MALLOC_SIMPLE=y +# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set +CONFIG_SPL_SYS_MALLOC=y +CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y +CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x120000 +CONFIG_SPL_SYS_MALLOC_SIZE=0x3000 CONFIG_BOARD_EARLY_INIT_F=y CONFIG_SPL_MAX_SIZE=0x1f000 +CONFIG_SPL_HAS_BSS_LINKER_SECTION=y +CONFIG_SPL_BSS_START_ADDR=0x128000 CONFIG_SPL_BSS_MAX_SIZE=0x1000 CONFIG_SPL_BOARD_INIT=y CONFIG_SPL_POWER_DOMAIN=y -- cgit v1.3.1 From 994a51d9ac73c4672880bdcbea59d5eec8058686 Mon Sep 17 00:00:00 2001 From: Gilles Talis Date: Wed, 13 Dec 2023 09:29:40 -0300 Subject: imx: imx8mp: Add support for Polyhex Debix Model A SBC Add support for the Polyhex Debix Model A SBC board. It is an industrial grade single board computer based on NXP's i.MX 8M Plus. Currently supported interfaces are: - Serial console - Micro SD - eQOS and FEC Ethernet imx8mp-debix-model-a.dts is taken from Linux 6.3. Signed-off-by: Gilles Talis Reviewed-by: Peng Fan --- arch/arm/dts/Makefile | 1 + arch/arm/dts/imx8mp-debix-model-a-u-boot.dtsi | 141 ++ arch/arm/dts/imx8mp-debix-model-a.dts | 507 ++++++ arch/arm/mach-imx/imx8m/Kconfig | 8 + board/polyhex/imx8mp_debix_model_a/Kconfig | 15 + board/polyhex/imx8mp_debix_model_a/MAINTAINERS | 8 + board/polyhex/imx8mp_debix_model_a/Makefile | 13 + .../imx8mp_debix_model_a/imx8mp_debix_model_a.c | 55 + .../imx8mp_debix_model_a/imximage-8mp-lpddr4.cfg | 9 + board/polyhex/imx8mp_debix_model_a/lpddr4_timing.c | 1843 ++++++++++++++++++++ board/polyhex/imx8mp_debix_model_a/spl.c | 129 ++ configs/imx8mp_debix_model_a_defconfig | 110 ++ include/configs/imx8mp_debix_model_a.h | 54 + 13 files changed, 2893 insertions(+) create mode 100644 arch/arm/dts/imx8mp-debix-model-a-u-boot.dtsi create mode 100644 arch/arm/dts/imx8mp-debix-model-a.dts create mode 100644 board/polyhex/imx8mp_debix_model_a/Kconfig create mode 100644 board/polyhex/imx8mp_debix_model_a/MAINTAINERS create mode 100644 board/polyhex/imx8mp_debix_model_a/Makefile create mode 100644 board/polyhex/imx8mp_debix_model_a/imx8mp_debix_model_a.c create mode 100644 board/polyhex/imx8mp_debix_model_a/imximage-8mp-lpddr4.cfg create mode 100644 board/polyhex/imx8mp_debix_model_a/lpddr4_timing.c create mode 100644 board/polyhex/imx8mp_debix_model_a/spl.c create mode 100644 configs/imx8mp_debix_model_a_defconfig create mode 100644 include/configs/imx8mp_debix_model_a.h diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index ea420db1b80..b415613740c 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -1104,6 +1104,7 @@ dtb-$(CONFIG_ARCH_IMX8M) += \ imx8mp-dhcom-som-overlay-eth1xfast.dtbo \ imx8mp-dhcom-som-overlay-eth2xfast.dtbo \ imx8mp-dhcom-pdk-overlay-eth2xfast.dtbo \ + imx8mp-debix-model-a.dtb \ imx8mp-dhcom-pdk2.dtb \ imx8mp-dhcom-pdk3.dtb \ imx8mp-dhcom-pdk3-overlay-rev100.dtbo \ diff --git a/arch/arm/dts/imx8mp-debix-model-a-u-boot.dtsi b/arch/arm/dts/imx8mp-debix-model-a-u-boot.dtsi new file mode 100644 index 00000000000..33bd89a8434 --- /dev/null +++ b/arch/arm/dts/imx8mp-debix-model-a-u-boot.dtsi @@ -0,0 +1,141 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2019, 2021 NXP + * Copyright 2023 Gilles Talis + */ + +#include "imx8mp-u-boot.dtsi" + +/ { + wdt-reboot { + compatible = "wdt-reboot"; + wdt = <&wdog1>; + bootph-pre-ram; + }; + firmware { + optee { + compatible = "linaro,optee-tz"; + method = "smc"; + }; + }; +}; + +&crypto { + bootph-pre-ram; +}; + +ðphy0 { + reset-gpios = <&gpio4 18 GPIO_ACTIVE_LOW>; + reset-delay-us = <15000>; + reset-post-delay-us = <100000>; +}; + +&fec { + phy-reset-gpios = <&gpio4 19 GPIO_ACTIVE_LOW>; + phy-reset-duration = <15>; + phy-reset-post-delay = <100>; +}; + +&gpio1 { + bootph-pre-ram; +}; + +&gpio2 { + bootph-pre-ram; +}; + +&gpio3 { + bootph-pre-ram; +}; + +&gpio4 { + bootph-pre-ram; +}; + +&gpio5 { + bootph-pre-ram; +}; + +&i2c1 { + bootph-pre-ram; +}; + +&pinctrl_i2c1 { + bootph-pre-ram; +}; + +&pinctrl_pmic { + bootph-pre-ram; +}; + +&pinctrl_uart2 { + bootph-pre-ram; +}; + +&pinctrl_usdhc2_gpio { + bootph-pre-ram; +}; + +&pinctrl_usdhc2 { + bootph-pre-ram; +}; + +&pinctrl_usdhc3 { + bootph-pre-ram; +}; + +&pinctrl_wdog { + bootph-pre-ram; +}; + +&pmic { + bootph-pre-ram; + + regulators { + bootph-pre-ram; + }; +}; + +®_usdhc2_vmmc { + u-boot,off-on-delay-us = <20000>; +}; + +®_usdhc2_vmmc { + bootph-pre-ram; +}; + +&uart2 { + bootph-pre-ram; +}; + +&sec_jr0 { + bootph-pre-ram; +}; + +&sec_jr1 { + bootph-pre-ram; +}; + +&sec_jr2 { + bootph-pre-ram; +}; + +&usdhc1 { + bootph-pre-ram; +}; + +&usdhc2 { + bootph-pre-ram; + sd-uhs-sdr104; + sd-uhs-ddr50; +}; + +&usdhc3 { + bootph-pre-ram; + mmc-hs400-1_8v; + mmc-hs400-enhanced-strobe; +}; + +&wdog1 { + bootph-pre-ram; +}; diff --git a/arch/arm/dts/imx8mp-debix-model-a.dts b/arch/arm/dts/imx8mp-debix-model-a.dts new file mode 100644 index 00000000000..58dae612b4b --- /dev/null +++ b/arch/arm/dts/imx8mp-debix-model-a.dts @@ -0,0 +1,507 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2019 NXP + * Copyright 2022 Ideas on Board Oy + */ + +/dts-v1/; + +#include +#include +#include + +#include "imx8mp.dtsi" + +/ { + model = "Polyhex Debix Model A i.MX8MPlus board"; + compatible = "polyhex,imx8mp-debix-model-a", "polyhex,imx8mp-debix", "fsl,imx8mp"; + + chosen { + stdout-path = &uart2; + }; + + leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio_led>; + + led-0 { + function = LED_FUNCTION_POWER; + color = ; + gpios = <&gpio3 16 GPIO_ACTIVE_HIGH>; + default-state = "on"; + }; + }; + + reg_usdhc2_vmmc: regulator-usdhc2 { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>; + regulator-name = "VSD_3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; +}; + +&A53_0 { + cpu-supply = <&buck2>; +}; + +&A53_1 { + cpu-supply = <&buck2>; +}; + +&A53_2 { + cpu-supply = <&buck2>; +}; + +&A53_3 { + cpu-supply = <&buck2>; +}; + +&eqos { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_eqos>; + phy-connection-type = "rgmii-id"; + phy-handle = <ðphy0>; + status = "okay"; + + mdio { + compatible = "snps,dwmac-mdio"; + #address-cells = <1>; + #size-cells = <0>; + + ethphy0: ethernet-phy@0 { /* RTL8211E */ + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0>; + reset-gpios = <&gpio4 18 GPIO_ACTIVE_LOW>; + reset-assert-us = <20>; + reset-deassert-us = <200000>; + }; + }; +}; + +&i2c1 { + clock-frequency = <400000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1>; + status = "okay"; + + pmic: pmic@25 { + compatible = "nxp,pca9450c"; + reg = <0x25>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pmic>; + interrupt-parent = <&gpio1>; + interrupts = <3 IRQ_TYPE_EDGE_RISING>; + + regulators { + buck1: BUCK1 { + regulator-name = "BUCK1"; + regulator-min-microvolt = <600000>; + regulator-max-microvolt = <2187500>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay = <3125>; + }; + + buck2: BUCK2 { + regulator-name = "BUCK2"; + regulator-min-microvolt = <600000>; + regulator-max-microvolt = <2187500>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay = <3125>; + nxp,dvs-run-voltage = <950000>; + nxp,dvs-standby-voltage = <850000>; + }; + + buck4: BUCK4{ + regulator-name = "BUCK4"; + regulator-min-microvolt = <600000>; + regulator-max-microvolt = <3400000>; + regulator-boot-on; + regulator-always-on; + }; + + buck5: BUCK5{ + regulator-name = "BUCK5"; + regulator-min-microvolt = <600000>; + regulator-max-microvolt = <3400000>; + regulator-boot-on; + regulator-always-on; + }; + + buck6: BUCK6 { + regulator-name = "BUCK6"; + regulator-min-microvolt = <600000>; + regulator-max-microvolt = <3400000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo1: LDO1 { + regulator-name = "LDO1"; + regulator-min-microvolt = <1600000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo2: LDO2 { + regulator-name = "LDO2"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1150000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo3: LDO3 { + regulator-name = "LDO3"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo4: LDO4 { + regulator-name = "LDO4"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo5: LDO5 { + regulator-name = "LDO5"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + }; + }; +}; + +&i2c2 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c2>; + status = "okay"; +}; + +&i2c3 { + clock-frequency = <400000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c3>; + status = "okay"; +}; + +&i2c4 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c4>; + status = "okay"; + + eeprom@50 { + compatible = "atmel,24c02"; + reg = <0x50>; + pagesize = <16>; + }; + + rtc@51 { + compatible = "haoyu,hym8563"; + reg = <0x51>; + #clock-cells = <0>; + clock-frequency = <32768>; + clock-output-names = "xin32k"; + interrupt-parent = <&gpio2>; + interrupts = <11 IRQ_TYPE_EDGE_FALLING>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_rtc_int>; + }; +}; + +&i2c6 { + clock-frequency = <400000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c6>; + status = "okay"; +}; + +&snvs_pwrkey { + status = "okay"; +}; + +&uart2 { + /* console */ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2>; + status = "okay"; +}; + +&uart3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart3>; + status = "okay"; +}; + +&uart4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart4>; + status = "okay"; +}; + +/* SD Card */ +&usdhc2 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; + pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>; + pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>; + cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>; + vmmc-supply = <®_usdhc2_vmmc>; + bus-width = <4>; + status = "okay"; +}; + +/* eMMC */ +&usdhc3 { + assigned-clocks = <&clk IMX8MP_CLK_USDHC3>; + assigned-clock-rates = <400000000>; + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc3>; + pinctrl-1 = <&pinctrl_usdhc3_100mhz>; + pinctrl-2 = <&pinctrl_usdhc3_200mhz>; + bus-width = <8>; + non-removable; + status = "okay"; +}; + +&wdog1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_wdog>; + fsl,ext-reset-output; + status = "okay"; +}; + +&iomuxc { + pinctrl_eqos: eqosgrp { + fsl,pins = < + MX8MP_IOMUXC_ENET_MDC__ENET_QOS_MDC 0x3 + MX8MP_IOMUXC_ENET_MDIO__ENET_QOS_MDIO 0x3 + MX8MP_IOMUXC_ENET_RD0__ENET_QOS_RGMII_RD0 0x91 + MX8MP_IOMUXC_ENET_RD1__ENET_QOS_RGMII_RD1 0x91 + MX8MP_IOMUXC_ENET_RD2__ENET_QOS_RGMII_RD2 0x91 + MX8MP_IOMUXC_ENET_RD3__ENET_QOS_RGMII_RD3 0x91 + MX8MP_IOMUXC_ENET_RXC__CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK 0x91 + MX8MP_IOMUXC_ENET_RX_CTL__ENET_QOS_RGMII_RX_CTL 0x91 + MX8MP_IOMUXC_ENET_TD0__ENET_QOS_RGMII_TD0 0x1f + MX8MP_IOMUXC_ENET_TD1__ENET_QOS_RGMII_TD1 0x1f + MX8MP_IOMUXC_ENET_TD2__ENET_QOS_RGMII_TD2 0x1f + MX8MP_IOMUXC_ENET_TD3__ENET_QOS_RGMII_TD3 0x1f + MX8MP_IOMUXC_ENET_TX_CTL__ENET_QOS_RGMII_TX_CTL 0x1f + MX8MP_IOMUXC_ENET_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK 0x1f + MX8MP_IOMUXC_SAI1_RXFS__ENET1_1588_EVENT0_IN 0x1f + MX8MP_IOMUXC_SAI1_RXC__ENET1_1588_EVENT0_OUT 0x1f + MX8MP_IOMUXC_SAI1_TXD6__GPIO4_IO18 0x19 + >; + }; + + pinctrl_fec: fecgrp { + fsl,pins = < + MX8MP_IOMUXC_SAI1_RXD2__ENET1_MDC 0x3 + MX8MP_IOMUXC_SAI1_RXD3__ENET1_MDIO 0x3 + MX8MP_IOMUXC_SAI1_RXD4__ENET1_RGMII_RD0 0x91 + MX8MP_IOMUXC_SAI1_RXD5__ENET1_RGMII_RD1 0x91 + MX8MP_IOMUXC_SAI1_RXD6__ENET1_RGMII_RD2 0x91 + MX8MP_IOMUXC_SAI1_RXD7__ENET1_RGMII_RD3 0x91 + MX8MP_IOMUXC_SAI1_TXC__ENET1_RGMII_RXC 0x91 + MX8MP_IOMUXC_SAI1_TXFS__ENET1_RGMII_RX_CTL 0x91 + MX8MP_IOMUXC_SAI1_TXD0__ENET1_RGMII_TD0 0x1f + MX8MP_IOMUXC_SAI1_TXD1__ENET1_RGMII_TD1 0x1f + MX8MP_IOMUXC_SAI1_TXD2__ENET1_RGMII_TD2 0x1f + MX8MP_IOMUXC_SAI1_TXD3__ENET1_RGMII_TD3 0x1f + MX8MP_IOMUXC_SAI1_TXD4__ENET1_RGMII_TX_CTL 0x1f + MX8MP_IOMUXC_SAI1_TXD5__ENET1_RGMII_TXC 0x1f + MX8MP_IOMUXC_SAI1_RXD1__ENET1_1588_EVENT1_OUT 0x1f + MX8MP_IOMUXC_SAI1_RXD0__ENET1_1588_EVENT1_IN 0x1f + MX8MP_IOMUXC_SAI1_TXD7__GPIO4_IO19 0x19 + >; + }; + + pinctrl_gpio_led: gpioledgrp { + fsl,pins = < + MX8MP_IOMUXC_NAND_READY_B__GPIO3_IO16 0x19 + >; + }; + + pinctrl_i2c1: i2c1grp { + fsl,pins = < + MX8MP_IOMUXC_I2C1_SCL__I2C1_SCL 0x400001c2 + MX8MP_IOMUXC_I2C1_SDA__I2C1_SDA 0x400001c2 + >; + }; + + pinctrl_i2c2: i2c2grp { + fsl,pins = < + MX8MP_IOMUXC_I2C2_SCL__I2C2_SCL 0x400001c2 + MX8MP_IOMUXC_I2C2_SDA__I2C2_SDA 0x400001c2 + >; + }; + + pinctrl_i2c3: i2c3grp { + fsl,pins = < + MX8MP_IOMUXC_I2C3_SCL__I2C3_SCL 0x400001c2 + MX8MP_IOMUXC_I2C3_SDA__I2C3_SDA 0x400001c2 + >; + }; + + pinctrl_i2c4: i2c4grp { + fsl,pins = < + MX8MP_IOMUXC_I2C4_SCL__I2C4_SCL 0x400001c3 + MX8MP_IOMUXC_I2C4_SDA__I2C4_SDA 0x400001c3 + >; + }; + + pinctrl_i2c6: i2c6grp { + fsl,pins = < + MX8MP_IOMUXC_SAI5_RXFS__I2C6_SCL 0x400001c3 + MX8MP_IOMUXC_SAI5_RXC__I2C6_SDA 0x400001c3 + >; + }; + + pinctrl_pmic: pmicirqgrp { + fsl,pins = < + MX8MP_IOMUXC_GPIO1_IO03__GPIO1_IO03 0x41 + >; + }; + + pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp { + fsl,pins = < + MX8MP_IOMUXC_SD2_RESET_B__GPIO2_IO19 0x41 + >; + }; + + pinctrl_rtc_int: rtcintgrp { + fsl,pins = < + MX8MP_IOMUXC_SD1_STROBE__GPIO2_IO11 0x140 + >; + }; + + pinctrl_uart2: uart2grp { + fsl,pins = < + MX8MP_IOMUXC_UART2_RXD__UART2_DCE_RX 0x14f + MX8MP_IOMUXC_UART2_TXD__UART2_DCE_TX 0x14f + >; + }; + + pinctrl_uart3: uart3grp { + fsl,pins = < + MX8MP_IOMUXC_UART3_RXD__UART3_DCE_RX 0x49 + MX8MP_IOMUXC_UART3_TXD__UART3_DCE_TX 0x49 + >; + }; + + pinctrl_uart4: uart4grp { + fsl,pins = < + MX8MP_IOMUXC_UART4_RXD__UART4_DCE_RX 0x49 + MX8MP_IOMUXC_UART4_TXD__UART4_DCE_TX 0x49 + >; + }; + + pinctrl_usdhc2: usdhc2grp { + fsl,pins = < + MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x190 + MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d0 + MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d0 + MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d0 + MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d0 + MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d0 + >; + }; + + pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp { + fsl,pins = < + MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x194 + MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d4 + MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d4 + MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d4 + MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d4 + MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d4 + >; + }; + + pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp { + fsl,pins = < + MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x196 + MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d6 + MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d6 + MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d6 + MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d6 + MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d6 + >; + }; + + pinctrl_usdhc2_gpio: usdhc2gpiogrp { + fsl,pins = < + MX8MP_IOMUXC_SD2_CD_B__GPIO2_IO12 0x1c4 + >; + }; + + pinctrl_usdhc3: usdhc3grp { + fsl,pins = < + MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x190 + MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d0 + MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d0 + MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d0 + MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d0 + MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d0 + MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d0 + MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d0 + MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d0 + MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d0 + MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x190 + >; + }; + + pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp { + fsl,pins = < + MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x194 + MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d4 + MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d4 + MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d4 + MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d4 + MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d4 + MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d4 + MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d4 + MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d4 + MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d4 + MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x194 + >; + }; + + pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp { + fsl,pins = < + MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x196 + MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d6 + MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d6 + MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d6 + MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d6 + MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d6 + MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d6 + MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d6 + MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d6 + MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d6 + MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x196 + >; + }; + + pinctrl_wdog: wdoggrp { + fsl,pins = < + MX8MP_IOMUXC_GPIO1_IO02__WDOG1_WDOG_B 0xc6 + >; + }; +}; + diff --git a/arch/arm/mach-imx/imx8m/Kconfig b/arch/arm/mach-imx/imx8m/Kconfig index 3d62d7052e7..b802d5cf280 100644 --- a/arch/arm/mach-imx/imx8m/Kconfig +++ b/arch/arm/mach-imx/imx8m/Kconfig @@ -199,6 +199,13 @@ config TARGET_IMX8MP_BEACON select ARCH_MISC_INIT select SPL_CRYPTO if SPL +config TARGET_IMX8MP_DEBIX_MODEL_A + bool "Polyhex i.MX8M Plus Debix Model A SBC" + select BINMAN + select IMX8MP + select IMX8M_LPDDR4 + select SUPPORT_SPL + config TARGET_IMX8MP_DH_DHCOM_PDK2 bool "DH electronics DHCOM Premium Developer Kit (2) i.MX8M Plus" select BINMAN @@ -384,6 +391,7 @@ source "board/msc/sm2s_imx8mp/Kconfig" source "board/mntre/imx8mq_reform2/Kconfig" source "board/phytec/phycore_imx8mm/Kconfig" source "board/phytec/phycore_imx8mp/Kconfig" +source "board/polyhex/imx8mp_debix_model_a/Kconfig" source "board/purism/librem5/Kconfig" source "board/ronetix/imx8mq-cm/Kconfig" source "board/technexion/pico-imx8mq/Kconfig" diff --git a/board/polyhex/imx8mp_debix_model_a/Kconfig b/board/polyhex/imx8mp_debix_model_a/Kconfig new file mode 100644 index 00000000000..3ebb6bc5557 --- /dev/null +++ b/board/polyhex/imx8mp_debix_model_a/Kconfig @@ -0,0 +1,15 @@ +if TARGET_IMX8MP_DEBIX_MODEL_A + +config SYS_BOARD + default "imx8mp_debix_model_a" + +config SYS_VENDOR + default "polyhex" + +config SYS_CONFIG_NAME + default "imx8mp_debix_model_a" + +config IMX_CONFIG + default "board/polyhex/imx8mp_debix_model_a/imximage-8mp-lpddr4.cfg" + +endif diff --git a/board/polyhex/imx8mp_debix_model_a/MAINTAINERS b/board/polyhex/imx8mp_debix_model_a/MAINTAINERS new file mode 100644 index 00000000000..d3afa91c118 --- /dev/null +++ b/board/polyhex/imx8mp_debix_model_a/MAINTAINERS @@ -0,0 +1,8 @@ +DEBIX MODEL A BOARD (i.MX8M Plus) +M: Gilles Talis +S: Maintained +F: arch/arm/dts/imx8mp-debix-model-a.dts +F: arch/arm/dts/imx8mp-debix-model-a-u-boot.dtsi +F: board/polyhex/imx8mp_debix_model_a/ +F: include/configs/imx8mp_debix_model_a.h +F: configs/imx8mp_debix_model_a_defconfig diff --git a/board/polyhex/imx8mp_debix_model_a/Makefile b/board/polyhex/imx8mp_debix_model_a/Makefile new file mode 100644 index 00000000000..e5cdc850878 --- /dev/null +++ b/board/polyhex/imx8mp_debix_model_a/Makefile @@ -0,0 +1,13 @@ +# +# Copyright 2019 NXP +# Copyright 2023 Gilles Talis +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y += imx8mp_debix_model_a.o + +ifdef CONFIG_SPL_BUILD +obj-y += spl.o +obj-$(CONFIG_IMX8M_LPDDR4) += lpddr4_timing.o +endif diff --git a/board/polyhex/imx8mp_debix_model_a/imx8mp_debix_model_a.c b/board/polyhex/imx8mp_debix_model_a/imx8mp_debix_model_a.c new file mode 100644 index 00000000000..14b94c9e33c --- /dev/null +++ b/board/polyhex/imx8mp_debix_model_a/imx8mp_debix_model_a.c @@ -0,0 +1,55 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2019 NXP + * Copyright 2023 Gilles Talis + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +static void setup_fec(void) +{ + struct iomuxc_gpr_base_regs *gpr = + (struct iomuxc_gpr_base_regs *)IOMUXC_GPR_BASE_ADDR; + + /* Enable RGMII TX clk output */ + setbits_le32(&gpr->gpr[1], BIT(22)); +} + +#if CONFIG_IS_ENABLED(NET) +int board_phy_config(struct phy_device *phydev) +{ + if (phydev->drv->config) + phydev->drv->config(phydev); + return 0; +} +#endif + +int board_init(void) +{ + int ret = 0; + + if (IS_ENABLED(CONFIG_FEC_MXC)) + setup_fec(); + + return ret; +} + +int board_late_init(void) +{ + return 0; +} diff --git a/board/polyhex/imx8mp_debix_model_a/imximage-8mp-lpddr4.cfg b/board/polyhex/imx8mp_debix_model_a/imximage-8mp-lpddr4.cfg new file mode 100644 index 00000000000..23fd05204a6 --- /dev/null +++ b/board/polyhex/imx8mp_debix_model_a/imximage-8mp-lpddr4.cfg @@ -0,0 +1,9 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2021, 2023 NXP + */ + + +ROM_VERSION v2 +BOOT_FROM sd +LOADER u-boot-spl-ddr.bin 0x920000 diff --git a/board/polyhex/imx8mp_debix_model_a/lpddr4_timing.c b/board/polyhex/imx8mp_debix_model_a/lpddr4_timing.c new file mode 100644 index 00000000000..518daa39f94 --- /dev/null +++ b/board/polyhex/imx8mp_debix_model_a/lpddr4_timing.c @@ -0,0 +1,1843 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2019, 2023 NXP + */ + +#include +#include + +struct dram_cfg_param ddr_ddrc_cfg[] = { + /** Initialize DDRC registers **/ + { 0x3d400304, 0x1 }, + { 0x3d400030, 0x1 }, + { 0x3d400000, 0xa1080020 }, + { 0x3d400020, 0x1323 }, + { 0x3d400024, 0x1c61a00 }, + { 0x3d400064, 0x710105 }, + { 0x3d400070, 0x61027f10 }, + { 0x3d400074, 0x7b0 }, + { 0x3d4000d0, 0xc003071a }, + { 0x3d4000d4, 0xb70000 }, + { 0x3d4000dc, 0xe40036 }, + { 0x3d4000e0, 0x330000 }, + { 0x3d4000e8, 0x660048 }, + { 0x3d4000ec, 0x160048 }, + { 0x3d400100, 0x1e261f28 }, + { 0x3d400104, 0x7073b }, + { 0x3d40010c, 0xe0e000 }, + { 0x3d400110, 0x11040a11 }, + { 0x3d400114, 0x2050e0e }, + { 0x3d400118, 0x1010008 }, + { 0x3d40011c, 0x501 }, + { 0x3d400130, 0x20700 }, + { 0x3d400134, 0xe100002 }, + { 0x3d400138, 0x10c }, + { 0x3d400144, 0xba005d }, + { 0x3d400180, 0x3a2001c }, + { 0x3d400184, 0x2f07187 }, + { 0x3d400188, 0x0 }, + { 0x3d400190, 0x49b820c }, + { 0x3d400194, 0x80303 }, + { 0x3d4001b4, 0x1b0c }, + { 0x3d4001a0, 0xe0400018 }, + { 0x3d4001a4, 0xdf00e4 }, + { 0x3d4001a8, 0x80000000 }, + { 0x3d4001b0, 0x11 }, + { 0x3d4001c0, 0x1 }, + { 0x3d4001c4, 0x1 }, + { 0x3d4000f4, 0xc99 }, + { 0x3d400108, 0x810191a }, + { 0x3d400200, 0x1f }, + { 0x3d40020c, 0x0 }, + { 0x3d400210, 0x1f1f }, + { 0x3d400204, 0x80808 }, + { 0x3d400214, 0x7070707 }, + { 0x3d400218, 0x7070707 }, + { 0x3d40021c, 0xf0f }, + { 0x3d400250, 0x1705 }, + { 0x3d400254, 0x2c }, + { 0x3d40025c, 0x4000030 }, + { 0x3d400264, 0x900093e7 }, + { 0x3d40026c, 0x2005574 }, + { 0x3d400400, 0x111 }, + { 0x3d400404, 0x72ff }, + { 0x3d400408, 0x72ff }, + { 0x3d400494, 0x2100e07 }, + { 0x3d400498, 0x620096 }, + { 0x3d40049c, 0x1100e07 }, + { 0x3d4004a0, 0xc8012c }, + { 0x3d402020, 0x1021 }, + { 0x3d402024, 0x30d400 }, + { 0x3d402050, 0x20d000 }, + { 0x3d402064, 0xc001c }, + { 0x3d4020dc, 0x840000 }, + { 0x3d4020e0, 0x330000 }, + { 0x3d4020e8, 0x660048 }, + { 0x3d4020ec, 0x160048 }, + { 0x3d402100, 0xa040305 }, + { 0x3d402104, 0x30407 }, + { 0x3d402108, 0x203060b }, + { 0x3d40210c, 0x505000 }, + { 0x3d402110, 0x2040202 }, + { 0x3d402114, 0x2030202 }, + { 0x3d402118, 0x1010004 }, + { 0x3d40211c, 0x301 }, + { 0x3d402130, 0x20300 }, + { 0x3d402134, 0xa100002 }, + { 0x3d402138, 0x1d }, + { 0x3d402144, 0x14000a }, + { 0x3d402180, 0x640004 }, + { 0x3d402190, 0x3818200 }, + { 0x3d402194, 0x80303 }, + { 0x3d4021b4, 0x100 }, + { 0x3d4020f4, 0xc99 }, + { 0x3d403020, 0x1021 }, + { 0x3d403024, 0xc3500 }, + { 0x3d403050, 0x20d000 }, + { 0x3d403064, 0x30007 }, + { 0x3d4030dc, 0x840000 }, + { 0x3d4030e0, 0x330000 }, + { 0x3d4030e8, 0x660048 }, + { 0x3d4030ec, 0x160048 }, + { 0x3d403100, 0xa010102 }, + { 0x3d403104, 0x30404 }, + { 0x3d403108, 0x203060b }, + { 0x3d40310c, 0x505000 }, + { 0x3d403110, 0x2040202 }, + { 0x3d403114, 0x2030202 }, + { 0x3d403118, 0x1010004 }, + { 0x3d40311c, 0x301 }, + { 0x3d403130, 0x20300 }, + { 0x3d403134, 0xa100002 }, + { 0x3d403138, 0x8 }, + { 0x3d403144, 0x50003 }, + { 0x3d403180, 0x190004 }, + { 0x3d403190, 0x3818200 }, + { 0x3d403194, 0x80303 }, + { 0x3d4031b4, 0x100 }, + { 0x3d4030f4, 0xc99 }, + { 0x3d400028, 0x0 }, +}; + +/* PHY Initialize Configuration */ +struct dram_cfg_param ddr_ddrphy_cfg[] = { + { 0x100a0, 0x0 }, + { 0x100a1, 0x1 }, + { 0x100a2, 0x2 }, + { 0x100a3, 0x3 }, + { 0x100a4, 0x4 }, + { 0x100a5, 0x5 }, + { 0x100a6, 0x6 }, + { 0x100a7, 0x7 }, + { 0x110a0, 0x0 }, + { 0x110a1, 0x1 }, + { 0x110a2, 0x3 }, + { 0x110a3, 0x4 }, + { 0x110a4, 0x5 }, + { 0x110a5, 0x2 }, + { 0x110a6, 0x7 }, + { 0x110a7, 0x6 }, + { 0x120a0, 0x0 }, + { 0x120a1, 0x1 }, + { 0x120a2, 0x3 }, + { 0x120a3, 0x2 }, + { 0x120a4, 0x5 }, + { 0x120a5, 0x4 }, + { 0x120a6, 0x7 }, + { 0x120a7, 0x6 }, + { 0x130a0, 0x0 }, + { 0x130a1, 0x1 }, + { 0x130a2, 0x2 }, + { 0x130a3, 0x3 }, + { 0x130a4, 0x4 }, + { 0x130a5, 0x5 }, + { 0x130a6, 0x6 }, + { 0x130a7, 0x7 }, + { 0x1005f, 0x1ff }, + { 0x1015f, 0x1ff }, + { 0x1105f, 0x1ff }, + { 0x1115f, 0x1ff }, + { 0x1205f, 0x1ff }, + { 0x1215f, 0x1ff }, + { 0x1305f, 0x1ff }, + { 0x1315f, 0x1ff }, + { 0x11005f, 0x1ff }, + { 0x11015f, 0x1ff }, + { 0x11105f, 0x1ff }, + { 0x11115f, 0x1ff }, + { 0x11205f, 0x1ff }, + { 0x11215f, 0x1ff }, + { 0x11305f, 0x1ff }, + { 0x11315f, 0x1ff }, + { 0x21005f, 0x1ff }, + { 0x21015f, 0x1ff }, + { 0x21105f, 0x1ff }, + { 0x21115f, 0x1ff }, + { 0x21205f, 0x1ff }, + { 0x21215f, 0x1ff }, + { 0x21305f, 0x1ff }, + { 0x21315f, 0x1ff }, + { 0x55, 0x1ff }, + { 0x1055, 0x1ff }, + { 0x2055, 0x1ff }, + { 0x3055, 0x1ff }, + { 0x4055, 0x1ff }, + { 0x5055, 0x1ff }, + { 0x6055, 0x1ff }, + { 0x7055, 0x1ff }, + { 0x8055, 0x1ff }, + { 0x9055, 0x1ff }, + { 0x200c5, 0x19 }, + { 0x1200c5, 0x7 }, + { 0x2200c5, 0x7 }, + { 0x2002e, 0x2 }, + { 0x12002e, 0x2 }, + { 0x22002e, 0x2 }, + { 0x90204, 0x0 }, + { 0x190204, 0x0 }, + { 0x290204, 0x0 }, + { 0x20024, 0x1e3 }, + { 0x2003a, 0x2 }, + { 0x120024, 0x1e3 }, + { 0x2003a, 0x2 }, + { 0x220024, 0x1e3 }, + { 0x2003a, 0x2 }, + { 0x20056, 0x3 }, + { 0x120056, 0x3 }, + { 0x220056, 0x3 }, + { 0x1004d, 0xe00 }, + { 0x1014d, 0xe00 }, + { 0x1104d, 0xe00 }, + { 0x1114d, 0xe00 }, + { 0x1204d, 0xe00 }, + { 0x1214d, 0xe00 }, + { 0x1304d, 0xe00 }, + { 0x1314d, 0xe00 }, + { 0x11004d, 0xe00 }, + { 0x11014d, 0xe00 }, + { 0x11104d, 0xe00 }, + { 0x11114d, 0xe00 }, + { 0x11204d, 0xe00 }, + { 0x11214d, 0xe00 }, + { 0x11304d, 0xe00 }, + { 0x11314d, 0xe00 }, + { 0x21004d, 0xe00 }, + { 0x21014d, 0xe00 }, + { 0x21104d, 0xe00 }, + { 0x21114d, 0xe00 }, + { 0x21204d, 0xe00 }, + { 0x21214d, 0xe00 }, + { 0x21304d, 0xe00 }, + { 0x21314d, 0xe00 }, + { 0x10049, 0xeba }, + { 0x10149, 0xeba }, + { 0x11049, 0xeba }, + { 0x11149, 0xeba }, + { 0x12049, 0xeba }, + { 0x12149, 0xeba }, + { 0x13049, 0xeba }, + { 0x13149, 0xeba }, + { 0x110049, 0xeba }, + { 0x110149, 0xeba }, + { 0x111049, 0xeba }, + { 0x111149, 0xeba }, + { 0x112049, 0xeba }, + { 0x112149, 0xeba }, + { 0x113049, 0xeba }, + { 0x113149, 0xeba }, + { 0x210049, 0xeba }, + { 0x210149, 0xeba }, + { 0x211049, 0xeba }, + { 0x211149, 0xeba }, + { 0x212049, 0xeba }, + { 0x212149, 0xeba }, + { 0x213049, 0xeba }, + { 0x213149, 0xeba }, + { 0x43, 0x63 }, + { 0x1043, 0x63 }, + { 0x2043, 0x63 }, + { 0x3043, 0x63 }, + { 0x4043, 0x63 }, + { 0x5043, 0x63 }, + { 0x6043, 0x63 }, + { 0x7043, 0x63 }, + { 0x8043, 0x63 }, + { 0x9043, 0x63 }, + { 0x20018, 0x3 }, + { 0x20075, 0x4 }, + { 0x20050, 0x0 }, + { 0x20008, 0x3a2 }, + { 0x120008, 0x64 }, + { 0x220008, 0x19 }, + { 0x20088, 0x9 }, + { 0x200b2, 0x104 }, + { 0x10043, 0x5a1 }, + { 0x10143, 0x5a1 }, + { 0x11043, 0x5a1 }, + { 0x11143, 0x5a1 }, + { 0x12043, 0x5a1 }, + { 0x12143, 0x5a1 }, + { 0x13043, 0x5a1 }, + { 0x13143, 0x5a1 }, + { 0x1200b2, 0x104 }, + { 0x110043, 0x5a1 }, + { 0x110143, 0x5a1 }, + { 0x111043, 0x5a1 }, + { 0x111143, 0x5a1 }, + { 0x112043, 0x5a1 }, + { 0x112143, 0x5a1 }, + { 0x113043, 0x5a1 }, + { 0x113143, 0x5a1 }, + { 0x2200b2, 0x104 }, + { 0x210043, 0x5a1 }, + { 0x210143, 0x5a1 }, + { 0x211043, 0x5a1 }, + { 0x211143, 0x5a1 }, + { 0x212043, 0x5a1 }, + { 0x212143, 0x5a1 }, + { 0x213043, 0x5a1 }, + { 0x213143, 0x5a1 }, + { 0x200fa, 0x1 }, + { 0x1200fa, 0x1 }, + { 0x2200fa, 0x1 }, + { 0x20019, 0x1 }, + { 0x120019, 0x1 }, + { 0x220019, 0x1 }, + { 0x200f0, 0x660 }, + { 0x200f1, 0x0 }, + { 0x200f2, 0x4444 }, + { 0x200f3, 0x8888 }, + { 0x200f4, 0x5665 }, + { 0x200f5, 0x0 }, + { 0x200f6, 0x0 }, + { 0x200f7, 0xf000 }, + { 0x20025, 0x0 }, + { 0x2002d, 0x0 }, + { 0x12002d, 0x0 }, + { 0x22002d, 0x0 }, + { 0x2007d, 0x212 }, + { 0x12007d, 0x212 }, + { 0x22007d, 0x212 }, + { 0x2007c, 0x61 }, + { 0x12007c, 0x61 }, + { 0x22007c, 0x61 }, + { 0x1004a, 0x500 }, + { 0x1104a, 0x500 }, + { 0x1204a, 0x500 }, + { 0x1304a, 0x500 }, + { 0x2002c, 0x0 }, +}; + +/* ddr phy trained csr */ +struct dram_cfg_param ddr_ddrphy_trained_csr[] = { + { 0x200b2, 0x0 }, + { 0x1200b2, 0x0 }, + { 0x2200b2, 0x0 }, + { 0x200cb, 0x0 }, + { 0x10043, 0x0 }, + { 0x110043, 0x0 }, + { 0x210043, 0x0 }, + { 0x10143, 0x0 }, + { 0x110143, 0x0 }, + { 0x210143, 0x0 }, + { 0x11043, 0x0 }, + { 0x111043, 0x0 }, + { 0x211043, 0x0 }, + { 0x11143, 0x0 }, + { 0x111143, 0x0 }, + { 0x211143, 0x0 }, + { 0x12043, 0x0 }, + { 0x112043, 0x0 }, + { 0x212043, 0x0 }, + { 0x12143, 0x0 }, + { 0x112143, 0x0 }, + { 0x212143, 0x0 }, + { 0x13043, 0x0 }, + { 0x113043, 0x0 }, + { 0x213043, 0x0 }, + { 0x13143, 0x0 }, + { 0x113143, 0x0 }, + { 0x213143, 0x0 }, + { 0x80, 0x0 }, + { 0x100080, 0x0 }, + { 0x200080, 0x0 }, + { 0x1080, 0x0 }, + { 0x101080, 0x0 }, + { 0x201080, 0x0 }, + { 0x2080, 0x0 }, + { 0x102080, 0x0 }, + { 0x202080, 0x0 }, + { 0x3080, 0x0 }, + { 0x103080, 0x0 }, + { 0x203080, 0x0 }, + { 0x4080, 0x0 }, + { 0x104080, 0x0 }, + { 0x204080, 0x0 }, + { 0x5080, 0x0 }, + { 0x105080, 0x0 }, + { 0x205080, 0x0 }, + { 0x6080, 0x0 }, + { 0x106080, 0x0 }, + { 0x206080, 0x0 }, + { 0x7080, 0x0 }, + { 0x107080, 0x0 }, + { 0x207080, 0x0 }, + { 0x8080, 0x0 }, + { 0x108080, 0x0 }, + { 0x208080, 0x0 }, + { 0x9080, 0x0 }, + { 0x109080, 0x0 }, + { 0x209080, 0x0 }, + { 0x10080, 0x0 }, + { 0x110080, 0x0 }, + { 0x210080, 0x0 }, + { 0x10180, 0x0 }, + { 0x110180, 0x0 }, + { 0x210180, 0x0 }, + { 0x11080, 0x0 }, + { 0x111080, 0x0 }, + { 0x211080, 0x0 }, + { 0x11180, 0x0 }, + { 0x111180, 0x0 }, + { 0x211180, 0x0 }, + { 0x12080, 0x0 }, + { 0x112080, 0x0 }, + { 0x212080, 0x0 }, + { 0x12180, 0x0 }, + { 0x112180, 0x0 }, + { 0x212180, 0x0 }, + { 0x13080, 0x0 }, + { 0x113080, 0x0 }, + { 0x213080, 0x0 }, + { 0x13180, 0x0 }, + { 0x113180, 0x0 }, + { 0x213180, 0x0 }, + { 0x10081, 0x0 }, + { 0x110081, 0x0 }, + { 0x210081, 0x0 }, + { 0x10181, 0x0 }, + { 0x110181, 0x0 }, + { 0x210181, 0x0 }, + { 0x11081, 0x0 }, + { 0x111081, 0x0 }, + { 0x211081, 0x0 }, + { 0x11181, 0x0 }, + { 0x111181, 0x0 }, + { 0x211181, 0x0 }, + { 0x12081, 0x0 }, + { 0x112081, 0x0 }, + { 0x212081, 0x0 }, + { 0x12181, 0x0 }, + { 0x112181, 0x0 }, + { 0x212181, 0x0 }, + { 0x13081, 0x0 }, + { 0x113081, 0x0 }, + { 0x213081, 0x0 }, + { 0x13181, 0x0 }, + { 0x113181, 0x0 }, + { 0x213181, 0x0 }, + { 0x100d0, 0x0 }, + { 0x1100d0, 0x0 }, + { 0x2100d0, 0x0 }, + { 0x101d0, 0x0 }, + { 0x1101d0, 0x0 }, + { 0x2101d0, 0x0 }, + { 0x110d0, 0x0 }, + { 0x1110d0, 0x0 }, + { 0x2110d0, 0x0 }, + { 0x111d0, 0x0 }, + { 0x1111d0, 0x0 }, + { 0x2111d0, 0x0 }, + { 0x120d0, 0x0 }, + { 0x1120d0, 0x0 }, + { 0x2120d0, 0x0 }, + { 0x121d0, 0x0 }, + { 0x1121d0, 0x0 }, + { 0x2121d0, 0x0 }, + { 0x130d0, 0x0 }, + { 0x1130d0, 0x0 }, + { 0x2130d0, 0x0 }, + { 0x131d0, 0x0 }, + { 0x1131d0, 0x0 }, + { 0x2131d0, 0x0 }, + { 0x100d1, 0x0 }, + { 0x1100d1, 0x0 }, + { 0x2100d1, 0x0 }, + { 0x101d1, 0x0 }, + { 0x1101d1, 0x0 }, + { 0x2101d1, 0x0 }, + { 0x110d1, 0x0 }, + { 0x1110d1, 0x0 }, + { 0x2110d1, 0x0 }, + { 0x111d1, 0x0 }, + { 0x1111d1, 0x0 }, + { 0x2111d1, 0x0 }, + { 0x120d1, 0x0 }, + { 0x1120d1, 0x0 }, + { 0x2120d1, 0x0 }, + { 0x121d1, 0x0 }, + { 0x1121d1, 0x0 }, + { 0x2121d1, 0x0 }, + { 0x130d1, 0x0 }, + { 0x1130d1, 0x0 }, + { 0x2130d1, 0x0 }, + { 0x131d1, 0x0 }, + { 0x1131d1, 0x0 }, + { 0x2131d1, 0x0 }, + { 0x10068, 0x0 }, + { 0x10168, 0x0 }, + { 0x10268, 0x0 }, + { 0x10368, 0x0 }, + { 0x10468, 0x0 }, + { 0x10568, 0x0 }, + { 0x10668, 0x0 }, + { 0x10768, 0x0 }, + { 0x10868, 0x0 }, + { 0x11068, 0x0 }, + { 0x11168, 0x0 }, + { 0x11268, 0x0 }, + { 0x11368, 0x0 }, + { 0x11468, 0x0 }, + { 0x11568, 0x0 }, + { 0x11668, 0x0 }, + { 0x11768, 0x0 }, + { 0x11868, 0x0 }, + { 0x12068, 0x0 }, + { 0x12168, 0x0 }, + { 0x12268, 0x0 }, + { 0x12368, 0x0 }, + { 0x12468, 0x0 }, + { 0x12568, 0x0 }, + { 0x12668, 0x0 }, + { 0x12768, 0x0 }, + { 0x12868, 0x0 }, + { 0x13068, 0x0 }, + { 0x13168, 0x0 }, + { 0x13268, 0x0 }, + { 0x13368, 0x0 }, + { 0x13468, 0x0 }, + { 0x13568, 0x0 }, + { 0x13668, 0x0 }, + { 0x13768, 0x0 }, + { 0x13868, 0x0 }, + { 0x10069, 0x0 }, + { 0x10169, 0x0 }, + { 0x10269, 0x0 }, + { 0x10369, 0x0 }, + { 0x10469, 0x0 }, + { 0x10569, 0x0 }, + { 0x10669, 0x0 }, + { 0x10769, 0x0 }, + { 0x10869, 0x0 }, + { 0x11069, 0x0 }, + { 0x11169, 0x0 }, + { 0x11269, 0x0 }, + { 0x11369, 0x0 }, + { 0x11469, 0x0 }, + { 0x11569, 0x0 }, + { 0x11669, 0x0 }, + { 0x11769, 0x0 }, + { 0x11869, 0x0 }, + { 0x12069, 0x0 }, + { 0x12169, 0x0 }, + { 0x12269, 0x0 }, + { 0x12369, 0x0 }, + { 0x12469, 0x0 }, + { 0x12569, 0x0 }, + { 0x12669, 0x0 }, + { 0x12769, 0x0 }, + { 0x12869, 0x0 }, + { 0x13069, 0x0 }, + { 0x13169, 0x0 }, + { 0x13269, 0x0 }, + { 0x13369, 0x0 }, + { 0x13469, 0x0 }, + { 0x13569, 0x0 }, + { 0x13669, 0x0 }, + { 0x13769, 0x0 }, + { 0x13869, 0x0 }, + { 0x1008c, 0x0 }, + { 0x11008c, 0x0 }, + { 0x21008c, 0x0 }, + { 0x1018c, 0x0 }, + { 0x11018c, 0x0 }, + { 0x21018c, 0x0 }, + { 0x1108c, 0x0 }, + { 0x11108c, 0x0 }, + { 0x21108c, 0x0 }, + { 0x1118c, 0x0 }, + { 0x11118c, 0x0 }, + { 0x21118c, 0x0 }, + { 0x1208c, 0x0 }, + { 0x11208c, 0x0 }, + { 0x21208c, 0x0 }, + { 0x1218c, 0x0 }, + { 0x11218c, 0x0 }, + { 0x21218c, 0x0 }, + { 0x1308c, 0x0 }, + { 0x11308c, 0x0 }, + { 0x21308c, 0x0 }, + { 0x1318c, 0x0 }, + { 0x11318c, 0x0 }, + { 0x21318c, 0x0 }, + { 0x1008d, 0x0 }, + { 0x11008d, 0x0 }, + { 0x21008d, 0x0 }, + { 0x1018d, 0x0 }, + { 0x11018d, 0x0 }, + { 0x21018d, 0x0 }, + { 0x1108d, 0x0 }, + { 0x11108d, 0x0 }, + { 0x21108d, 0x0 }, + { 0x1118d, 0x0 }, + { 0x11118d, 0x0 }, + { 0x21118d, 0x0 }, + { 0x1208d, 0x0 }, + { 0x11208d, 0x0 }, + { 0x21208d, 0x0 }, + { 0x1218d, 0x0 }, + { 0x11218d, 0x0 }, + { 0x21218d, 0x0 }, + { 0x1308d, 0x0 }, + { 0x11308d, 0x0 }, + { 0x21308d, 0x0 }, + { 0x1318d, 0x0 }, + { 0x11318d, 0x0 }, + { 0x21318d, 0x0 }, + { 0x100c0, 0x0 }, + { 0x1100c0, 0x0 }, + { 0x2100c0, 0x0 }, + { 0x101c0, 0x0 }, + { 0x1101c0, 0x0 }, + { 0x2101c0, 0x0 }, + { 0x102c0, 0x0 }, + { 0x1102c0, 0x0 }, + { 0x2102c0, 0x0 }, + { 0x103c0, 0x0 }, + { 0x1103c0, 0x0 }, + { 0x2103c0, 0x0 }, + { 0x104c0, 0x0 }, + { 0x1104c0, 0x0 }, + { 0x2104c0, 0x0 }, + { 0x105c0, 0x0 }, + { 0x1105c0, 0x0 }, + { 0x2105c0, 0x0 }, + { 0x106c0, 0x0 }, + { 0x1106c0, 0x0 }, + { 0x2106c0, 0x0 }, + { 0x107c0, 0x0 }, + { 0x1107c0, 0x0 }, + { 0x2107c0, 0x0 }, + { 0x108c0, 0x0 }, + { 0x1108c0, 0x0 }, + { 0x2108c0, 0x0 }, + { 0x110c0, 0x0 }, + { 0x1110c0, 0x0 }, + { 0x2110c0, 0x0 }, + { 0x111c0, 0x0 }, + { 0x1111c0, 0x0 }, + { 0x2111c0, 0x0 }, + { 0x112c0, 0x0 }, + { 0x1112c0, 0x0 }, + { 0x2112c0, 0x0 }, + { 0x113c0, 0x0 }, + { 0x1113c0, 0x0 }, + { 0x2113c0, 0x0 }, + { 0x114c0, 0x0 }, + { 0x1114c0, 0x0 }, + { 0x2114c0, 0x0 }, + { 0x115c0, 0x0 }, + { 0x1115c0, 0x0 }, + { 0x2115c0, 0x0 }, + { 0x116c0, 0x0 }, + { 0x1116c0, 0x0 }, + { 0x2116c0, 0x0 }, + { 0x117c0, 0x0 }, + { 0x1117c0, 0x0 }, + { 0x2117c0, 0x0 }, + { 0x118c0, 0x0 }, + { 0x1118c0, 0x0 }, + { 0x2118c0, 0x0 }, + { 0x120c0, 0x0 }, + { 0x1120c0, 0x0 }, + { 0x2120c0, 0x0 }, + { 0x121c0, 0x0 }, + { 0x1121c0, 0x0 }, + { 0x2121c0, 0x0 }, + { 0x122c0, 0x0 }, + { 0x1122c0, 0x0 }, + { 0x2122c0, 0x0 }, + { 0x123c0, 0x0 }, + { 0x1123c0, 0x0 }, + { 0x2123c0, 0x0 }, + { 0x124c0, 0x0 }, + { 0x1124c0, 0x0 }, + { 0x2124c0, 0x0 }, + { 0x125c0, 0x0 }, + { 0x1125c0, 0x0 }, + { 0x2125c0, 0x0 }, + { 0x126c0, 0x0 }, + { 0x1126c0, 0x0 }, + { 0x2126c0, 0x0 }, + { 0x127c0, 0x0 }, + { 0x1127c0, 0x0 }, + { 0x2127c0, 0x0 }, + { 0x128c0, 0x0 }, + { 0x1128c0, 0x0 }, + { 0x2128c0, 0x0 }, + { 0x130c0, 0x0 }, + { 0x1130c0, 0x0 }, + { 0x2130c0, 0x0 }, + { 0x131c0, 0x0 }, + { 0x1131c0, 0x0 }, + { 0x2131c0, 0x0 }, + { 0x132c0, 0x0 }, + { 0x1132c0, 0x0 }, + { 0x2132c0, 0x0 }, + { 0x133c0, 0x0 }, + { 0x1133c0, 0x0 }, + { 0x2133c0, 0x0 }, + { 0x134c0, 0x0 }, + { 0x1134c0, 0x0 }, + { 0x2134c0, 0x0 }, + { 0x135c0, 0x0 }, + { 0x1135c0, 0x0 }, + { 0x2135c0, 0x0 }, + { 0x136c0, 0x0 }, + { 0x1136c0, 0x0 }, + { 0x2136c0, 0x0 }, + { 0x137c0, 0x0 }, + { 0x1137c0, 0x0 }, + { 0x2137c0, 0x0 }, + { 0x138c0, 0x0 }, + { 0x1138c0, 0x0 }, + { 0x2138c0, 0x0 }, + { 0x100c1, 0x0 }, + { 0x1100c1, 0x0 }, + { 0x2100c1, 0x0 }, + { 0x101c1, 0x0 }, + { 0x1101c1, 0x0 }, + { 0x2101c1, 0x0 }, + { 0x102c1, 0x0 }, + { 0x1102c1, 0x0 }, + { 0x2102c1, 0x0 }, + { 0x103c1, 0x0 }, + { 0x1103c1, 0x0 }, + { 0x2103c1, 0x0 }, + { 0x104c1, 0x0 }, + { 0x1104c1, 0x0 }, + { 0x2104c1, 0x0 }, + { 0x105c1, 0x0 }, + { 0x1105c1, 0x0 }, + { 0x2105c1, 0x0 }, + { 0x106c1, 0x0 }, + { 0x1106c1, 0x0 }, + { 0x2106c1, 0x0 }, + { 0x107c1, 0x0 }, + { 0x1107c1, 0x0 }, + { 0x2107c1, 0x0 }, + { 0x108c1, 0x0 }, + { 0x1108c1, 0x0 }, + { 0x2108c1, 0x0 }, + { 0x110c1, 0x0 }, + { 0x1110c1, 0x0 }, + { 0x2110c1, 0x0 }, + { 0x111c1, 0x0 }, + { 0x1111c1, 0x0 }, + { 0x2111c1, 0x0 }, + { 0x112c1, 0x0 }, + { 0x1112c1, 0x0 }, + { 0x2112c1, 0x0 }, + { 0x113c1, 0x0 }, + { 0x1113c1, 0x0 }, + { 0x2113c1, 0x0 }, + { 0x114c1, 0x0 }, + { 0x1114c1, 0x0 }, + { 0x2114c1, 0x0 }, + { 0x115c1, 0x0 }, + { 0x1115c1, 0x0 }, + { 0x2115c1, 0x0 }, + { 0x116c1, 0x0 }, + { 0x1116c1, 0x0 }, + { 0x2116c1, 0x0 }, + { 0x117c1, 0x0 }, + { 0x1117c1, 0x0 }, + { 0x2117c1, 0x0 }, + { 0x118c1, 0x0 }, + { 0x1118c1, 0x0 }, + { 0x2118c1, 0x0 }, + { 0x120c1, 0x0 }, + { 0x1120c1, 0x0 }, + { 0x2120c1, 0x0 }, + { 0x121c1, 0x0 }, + { 0x1121c1, 0x0 }, + { 0x2121c1, 0x0 }, + { 0x122c1, 0x0 }, + { 0x1122c1, 0x0 }, + { 0x2122c1, 0x0 }, + { 0x123c1, 0x0 }, + { 0x1123c1, 0x0 }, + { 0x2123c1, 0x0 }, + { 0x124c1, 0x0 }, + { 0x1124c1, 0x0 }, + { 0x2124c1, 0x0 }, + { 0x125c1, 0x0 }, + { 0x1125c1, 0x0 }, + { 0x2125c1, 0x0 }, + { 0x126c1, 0x0 }, + { 0x1126c1, 0x0 }, + { 0x2126c1, 0x0 }, + { 0x127c1, 0x0 }, + { 0x1127c1, 0x0 }, + { 0x2127c1, 0x0 }, + { 0x128c1, 0x0 }, + { 0x1128c1, 0x0 }, + { 0x2128c1, 0x0 }, + { 0x130c1, 0x0 }, + { 0x1130c1, 0x0 }, + { 0x2130c1, 0x0 }, + { 0x131c1, 0x0 }, + { 0x1131c1, 0x0 }, + { 0x2131c1, 0x0 }, + { 0x132c1, 0x0 }, + { 0x1132c1, 0x0 }, + { 0x2132c1, 0x0 }, + { 0x133c1, 0x0 }, + { 0x1133c1, 0x0 }, + { 0x2133c1, 0x0 }, + { 0x134c1, 0x0 }, + { 0x1134c1, 0x0 }, + { 0x2134c1, 0x0 }, + { 0x135c1, 0x0 }, + { 0x1135c1, 0x0 }, + { 0x2135c1, 0x0 }, + { 0x136c1, 0x0 }, + { 0x1136c1, 0x0 }, + { 0x2136c1, 0x0 }, + { 0x137c1, 0x0 }, + { 0x1137c1, 0x0 }, + { 0x2137c1, 0x0 }, + { 0x138c1, 0x0 }, + { 0x1138c1, 0x0 }, + { 0x2138c1, 0x0 }, + { 0x10020, 0x0 }, + { 0x110020, 0x0 }, + { 0x210020, 0x0 }, + { 0x11020, 0x0 }, + { 0x111020, 0x0 }, + { 0x211020, 0x0 }, + { 0x12020, 0x0 }, + { 0x112020, 0x0 }, + { 0x212020, 0x0 }, + { 0x13020, 0x0 }, + { 0x113020, 0x0 }, + { 0x213020, 0x0 }, + { 0x20072, 0x0 }, + { 0x20073, 0x0 }, + { 0x20074, 0x0 }, + { 0x100aa, 0x0 }, + { 0x110aa, 0x0 }, + { 0x120aa, 0x0 }, + { 0x130aa, 0x0 }, + { 0x20010, 0x0 }, + { 0x120010, 0x0 }, + { 0x220010, 0x0 }, + { 0x20011, 0x0 }, + { 0x120011, 0x0 }, + { 0x220011, 0x0 }, + { 0x100ae, 0x0 }, + { 0x1100ae, 0x0 }, + { 0x2100ae, 0x0 }, + { 0x100af, 0x0 }, + { 0x1100af, 0x0 }, + { 0x2100af, 0x0 }, + { 0x110ae, 0x0 }, + { 0x1110ae, 0x0 }, + { 0x2110ae, 0x0 }, + { 0x110af, 0x0 }, + { 0x1110af, 0x0 }, + { 0x2110af, 0x0 }, + { 0x120ae, 0x0 }, + { 0x1120ae, 0x0 }, + { 0x2120ae, 0x0 }, + { 0x120af, 0x0 }, + { 0x1120af, 0x0 }, + { 0x2120af, 0x0 }, + { 0x130ae, 0x0 }, + { 0x1130ae, 0x0 }, + { 0x2130ae, 0x0 }, + { 0x130af, 0x0 }, + { 0x1130af, 0x0 }, + { 0x2130af, 0x0 }, + { 0x20020, 0x0 }, + { 0x120020, 0x0 }, + { 0x220020, 0x0 }, + { 0x100a0, 0x0 }, + { 0x100a1, 0x0 }, + { 0x100a2, 0x0 }, + { 0x100a3, 0x0 }, + { 0x100a4, 0x0 }, + { 0x100a5, 0x0 }, + { 0x100a6, 0x0 }, + { 0x100a7, 0x0 }, + { 0x110a0, 0x0 }, + { 0x110a1, 0x0 }, + { 0x110a2, 0x0 }, + { 0x110a3, 0x0 }, + { 0x110a4, 0x0 }, + { 0x110a5, 0x0 }, + { 0x110a6, 0x0 }, + { 0x110a7, 0x0 }, + { 0x120a0, 0x0 }, + { 0x120a1, 0x0 }, + { 0x120a2, 0x0 }, + { 0x120a3, 0x0 }, + { 0x120a4, 0x0 }, + { 0x120a5, 0x0 }, + { 0x120a6, 0x0 }, + { 0x120a7, 0x0 }, + { 0x130a0, 0x0 }, + { 0x130a1, 0x0 }, + { 0x130a2, 0x0 }, + { 0x130a3, 0x0 }, + { 0x130a4, 0x0 }, + { 0x130a5, 0x0 }, + { 0x130a6, 0x0 }, + { 0x130a7, 0x0 }, + { 0x2007c, 0x0 }, + { 0x12007c, 0x0 }, + { 0x22007c, 0x0 }, + { 0x2007d, 0x0 }, + { 0x12007d, 0x0 }, + { 0x22007d, 0x0 }, + { 0x400fd, 0x0 }, + { 0x400c0, 0x0 }, + { 0x90201, 0x0 }, + { 0x190201, 0x0 }, + { 0x290201, 0x0 }, + { 0x90202, 0x0 }, + { 0x190202, 0x0 }, + { 0x290202, 0x0 }, + { 0x90203, 0x0 }, + { 0x190203, 0x0 }, + { 0x290203, 0x0 }, + { 0x90204, 0x0 }, + { 0x190204, 0x0 }, + { 0x290204, 0x0 }, + { 0x90205, 0x0 }, + { 0x190205, 0x0 }, + { 0x290205, 0x0 }, + { 0x90206, 0x0 }, + { 0x190206, 0x0 }, + { 0x290206, 0x0 }, + { 0x90207, 0x0 }, + { 0x190207, 0x0 }, + { 0x290207, 0x0 }, + { 0x90208, 0x0 }, + { 0x190208, 0x0 }, + { 0x290208, 0x0 }, + { 0x10062, 0x0 }, + { 0x10162, 0x0 }, + { 0x10262, 0x0 }, + { 0x10362, 0x0 }, + { 0x10462, 0x0 }, + { 0x10562, 0x0 }, + { 0x10662, 0x0 }, + { 0x10762, 0x0 }, + { 0x10862, 0x0 }, + { 0x11062, 0x0 }, + { 0x11162, 0x0 }, + { 0x11262, 0x0 }, + { 0x11362, 0x0 }, + { 0x11462, 0x0 }, + { 0x11562, 0x0 }, + { 0x11662, 0x0 }, + { 0x11762, 0x0 }, + { 0x11862, 0x0 }, + { 0x12062, 0x0 }, + { 0x12162, 0x0 }, + { 0x12262, 0x0 }, + { 0x12362, 0x0 }, + { 0x12462, 0x0 }, + { 0x12562, 0x0 }, + { 0x12662, 0x0 }, + { 0x12762, 0x0 }, + { 0x12862, 0x0 }, + { 0x13062, 0x0 }, + { 0x13162, 0x0 }, + { 0x13262, 0x0 }, + { 0x13362, 0x0 }, + { 0x13462, 0x0 }, + { 0x13562, 0x0 }, + { 0x13662, 0x0 }, + { 0x13762, 0x0 }, + { 0x13862, 0x0 }, + { 0x20077, 0x0 }, + { 0x10001, 0x0 }, + { 0x11001, 0x0 }, + { 0x12001, 0x0 }, + { 0x13001, 0x0 }, + { 0x10040, 0x0 }, + { 0x10140, 0x0 }, + { 0x10240, 0x0 }, + { 0x10340, 0x0 }, + { 0x10440, 0x0 }, + { 0x10540, 0x0 }, + { 0x10640, 0x0 }, + { 0x10740, 0x0 }, + { 0x10840, 0x0 }, + { 0x10030, 0x0 }, + { 0x10130, 0x0 }, + { 0x10230, 0x0 }, + { 0x10330, 0x0 }, + { 0x10430, 0x0 }, + { 0x10530, 0x0 }, + { 0x10630, 0x0 }, + { 0x10730, 0x0 }, + { 0x10830, 0x0 }, + { 0x11040, 0x0 }, + { 0x11140, 0x0 }, + { 0x11240, 0x0 }, + { 0x11340, 0x0 }, + { 0x11440, 0x0 }, + { 0x11540, 0x0 }, + { 0x11640, 0x0 }, + { 0x11740, 0x0 }, + { 0x11840, 0x0 }, + { 0x11030, 0x0 }, + { 0x11130, 0x0 }, + { 0x11230, 0x0 }, + { 0x11330, 0x0 }, + { 0x11430, 0x0 }, + { 0x11530, 0x0 }, + { 0x11630, 0x0 }, + { 0x11730, 0x0 }, + { 0x11830, 0x0 }, + { 0x12040, 0x0 }, + { 0x12140, 0x0 }, + { 0x12240, 0x0 }, + { 0x12340, 0x0 }, + { 0x12440, 0x0 }, + { 0x12540, 0x0 }, + { 0x12640, 0x0 }, + { 0x12740, 0x0 }, + { 0x12840, 0x0 }, + { 0x12030, 0x0 }, + { 0x12130, 0x0 }, + { 0x12230, 0x0 }, + { 0x12330, 0x0 }, + { 0x12430, 0x0 }, + { 0x12530, 0x0 }, + { 0x12630, 0x0 }, + { 0x12730, 0x0 }, + { 0x12830, 0x0 }, + { 0x13040, 0x0 }, + { 0x13140, 0x0 }, + { 0x13240, 0x0 }, + { 0x13340, 0x0 }, + { 0x13440, 0x0 }, + { 0x13540, 0x0 }, + { 0x13640, 0x0 }, + { 0x13740, 0x0 }, + { 0x13840, 0x0 }, + { 0x13030, 0x0 }, + { 0x13130, 0x0 }, + { 0x13230, 0x0 }, + { 0x13330, 0x0 }, + { 0x13430, 0x0 }, + { 0x13530, 0x0 }, + { 0x13630, 0x0 }, + { 0x13730, 0x0 }, + { 0x13830, 0x0 }, +}; + +/* P0 message block paremeter for training firmware */ +struct dram_cfg_param ddr_fsp0_cfg[] = { + { 0xd0000, 0x0 }, + { 0x54003, 0xe88 }, + { 0x54004, 0x2 }, + { 0x54005, 0x2228 }, + { 0x54006, 0x14 }, + { 0x54008, 0x131f }, + { 0x54009, 0xc8 }, + { 0x5400b, 0x2 }, + { 0x5400f, 0x100 }, + { 0x54012, 0x110 }, + { 0x54019, 0x36e4 }, + { 0x5401a, 0x33 }, + { 0x5401b, 0x4866 }, + { 0x5401c, 0x4800 }, + { 0x5401e, 0x16 }, + { 0x5401f, 0x36e4 }, + { 0x54020, 0x33 }, + { 0x54021, 0x4866 }, + { 0x54022, 0x4800 }, + { 0x54024, 0x16 }, + { 0x5402b, 0x1000 }, + { 0x5402c, 0x1 }, + { 0x54032, 0xe400 }, + { 0x54033, 0x3336 }, + { 0x54034, 0x6600 }, + { 0x54035, 0x48 }, + { 0x54036, 0x48 }, + { 0x54037, 0x1600 }, + { 0x54038, 0xe400 }, + { 0x54039, 0x3336 }, + { 0x5403a, 0x6600 }, + { 0x5403b, 0x48 }, + { 0x5403c, 0x48 }, + { 0x5403d, 0x1600 }, + { 0xd0000, 0x1 }, +}; + +/* P1 message block paremeter for training firmware */ +struct dram_cfg_param ddr_fsp1_cfg[] = { + { 0xd0000, 0x0 }, + { 0x54002, 0x101 }, + { 0x54003, 0x190 }, + { 0x54004, 0x2 }, + { 0x54005, 0x2228 }, + { 0x54006, 0x14 }, + { 0x54008, 0x121f }, + { 0x54009, 0xc8 }, + { 0x5400b, 0x2 }, + { 0x5400f, 0x100 }, + { 0x54012, 0x110 }, + { 0x54019, 0x84 }, + { 0x5401a, 0x33 }, + { 0x5401b, 0x4866 }, + { 0x5401c, 0x4800 }, + { 0x5401e, 0x16 }, + { 0x5401f, 0x84 }, + { 0x54020, 0x33 }, + { 0x54021, 0x4866 }, + { 0x54022, 0x4800 }, + { 0x54024, 0x16 }, + { 0x5402b, 0x1000 }, + { 0x5402c, 0x1 }, + { 0x54032, 0x8400 }, + { 0x54033, 0x3300 }, + { 0x54034, 0x6600 }, + { 0x54035, 0x48 }, + { 0x54036, 0x48 }, + { 0x54037, 0x1600 }, + { 0x54038, 0x8400 }, + { 0x54039, 0x3300 }, + { 0x5403a, 0x6600 }, + { 0x5403b, 0x48 }, + { 0x5403c, 0x48 }, + { 0x5403d, 0x1600 }, + { 0xd0000, 0x1 }, +}; + +/* P2 message block paremeter for training firmware */ +struct dram_cfg_param ddr_fsp2_cfg[] = { + { 0xd0000, 0x0 }, + { 0x54002, 0x102 }, + { 0x54003, 0x64 }, + { 0x54004, 0x2 }, + { 0x54005, 0x2228 }, + { 0x54006, 0x14 }, + { 0x54008, 0x121f }, + { 0x54009, 0xc8 }, + { 0x5400b, 0x2 }, + { 0x5400f, 0x100 }, + { 0x54012, 0x110 }, + { 0x54019, 0x84 }, + { 0x5401a, 0x33 }, + { 0x5401b, 0x4866 }, + { 0x5401c, 0x4800 }, + { 0x5401e, 0x16 }, + { 0x5401f, 0x84 }, + { 0x54020, 0x33 }, + { 0x54021, 0x4866 }, + { 0x54022, 0x4800 }, + { 0x54024, 0x16 }, + { 0x5402b, 0x1000 }, + { 0x5402c, 0x1 }, + { 0x54032, 0x8400 }, + { 0x54033, 0x3300 }, + { 0x54034, 0x6600 }, + { 0x54035, 0x48 }, + { 0x54036, 0x48 }, + { 0x54037, 0x1600 }, + { 0x54038, 0x8400 }, + { 0x54039, 0x3300 }, + { 0x5403a, 0x6600 }, + { 0x5403b, 0x48 }, + { 0x5403c, 0x48 }, + { 0x5403d, 0x1600 }, + { 0xd0000, 0x1 }, +}; + +/* P0 2D message block paremeter for training firmware */ +struct dram_cfg_param ddr_fsp0_2d_cfg[] = { + { 0xd0000, 0x0 }, + { 0x54003, 0xe88 }, + { 0x54004, 0x2 }, + { 0x54005, 0x2228 }, + { 0x54006, 0x14 }, + { 0x54008, 0x61 }, + { 0x54009, 0xc8 }, + { 0x5400b, 0x2 }, + { 0x5400f, 0x100 }, + { 0x54010, 0x1f7f }, + { 0x54012, 0x110 }, + { 0x54019, 0x36e4 }, + { 0x5401a, 0x33 }, + { 0x5401b, 0x4866 }, + { 0x5401c, 0x4800 }, + { 0x5401e, 0x16 }, + { 0x5401f, 0x36e4 }, + { 0x54020, 0x33 }, + { 0x54021, 0x4866 }, + { 0x54022, 0x4800 }, + { 0x54024, 0x16 }, + { 0x5402b, 0x1000 }, + { 0x5402c, 0x1 }, + { 0x54032, 0xe400 }, + { 0x54033, 0x3336 }, + { 0x54034, 0x6600 }, + { 0x54035, 0x48 }, + { 0x54036, 0x48 }, + { 0x54037, 0x1600 }, + { 0x54038, 0xe400 }, + { 0x54039, 0x3336 }, + { 0x5403a, 0x6600 }, + { 0x5403b, 0x48 }, + { 0x5403c, 0x48 }, + { 0x5403d, 0x1600 }, + { 0xd0000, 0x1 }, +}; + +/* DRAM PHY init engine image */ +struct dram_cfg_param ddr_phy_pie[] = { + { 0xd0000, 0x0 }, + { 0x90000, 0x10 }, + { 0x90001, 0x400 }, + { 0x90002, 0x10e }, + { 0x90003, 0x0 }, + { 0x90004, 0x0 }, + { 0x90005, 0x8 }, + { 0x90029, 0xb }, + { 0x9002a, 0x480 }, + { 0x9002b, 0x109 }, + { 0x9002c, 0x8 }, + { 0x9002d, 0x448 }, + { 0x9002e, 0x139 }, + { 0x9002f, 0x8 }, + { 0x90030, 0x478 }, + { 0x90031, 0x109 }, + { 0x90032, 0x0 }, + { 0x90033, 0xe8 }, + { 0x90034, 0x109 }, + { 0x90035, 0x2 }, + { 0x90036, 0x10 }, + { 0x90037, 0x139 }, + { 0x90038, 0xb }, + { 0x90039, 0x7c0 }, + { 0x9003a, 0x139 }, + { 0x9003b, 0x44 }, + { 0x9003c, 0x633 }, + { 0x9003d, 0x159 }, + { 0x9003e, 0x14f }, + { 0x9003f, 0x630 }, + { 0x90040, 0x159 }, + { 0x90041, 0x47 }, + { 0x90042, 0x633 }, + { 0x90043, 0x149 }, + { 0x90044, 0x4f }, + { 0x90045, 0x633 }, + { 0x90046, 0x179 }, + { 0x90047, 0x8 }, + { 0x90048, 0xe0 }, + { 0x90049, 0x109 }, + { 0x9004a, 0x0 }, + { 0x9004b, 0x7c8 }, + { 0x9004c, 0x109 }, + { 0x9004d, 0x0 }, + { 0x9004e, 0x1 }, + { 0x9004f, 0x8 }, + { 0x90050, 0x0 }, + { 0x90051, 0x45a }, + { 0x90052, 0x9 }, + { 0x90053, 0x0 }, + { 0x90054, 0x448 }, + { 0x90055, 0x109 }, + { 0x90056, 0x40 }, + { 0x90057, 0x633 }, + { 0x90058, 0x179 }, + { 0x90059, 0x1 }, + { 0x9005a, 0x618 }, + { 0x9005b, 0x109 }, + { 0x9005c, 0x40c0 }, + { 0x9005d, 0x633 }, + { 0x9005e, 0x149 }, + { 0x9005f, 0x8 }, + { 0x90060, 0x4 }, + { 0x90061, 0x48 }, + { 0x90062, 0x4040 }, + { 0x90063, 0x633 }, + { 0x90064, 0x149 }, + { 0x90065, 0x0 }, + { 0x90066, 0x4 }, + { 0x90067, 0x48 }, + { 0x90068, 0x40 }, + { 0x90069, 0x633 }, + { 0x9006a, 0x149 }, + { 0x9006b, 0x10 }, + { 0x9006c, 0x4 }, + { 0x9006d, 0x18 }, + { 0x9006e, 0x0 }, + { 0x9006f, 0x4 }, + { 0x90070, 0x78 }, + { 0x90071, 0x549 }, + { 0x90072, 0x633 }, + { 0x90073, 0x159 }, + { 0x90074, 0xd49 }, + { 0x90075, 0x633 }, + { 0x90076, 0x159 }, + { 0x90077, 0x94a }, + { 0x90078, 0x633 }, + { 0x90079, 0x159 }, + { 0x9007a, 0x441 }, + { 0x9007b, 0x633 }, + { 0x9007c, 0x149 }, + { 0x9007d, 0x42 }, + { 0x9007e, 0x633 }, + { 0x9007f, 0x149 }, + { 0x90080, 0x1 }, + { 0x90081, 0x633 }, + { 0x90082, 0x149 }, + { 0x90083, 0x0 }, + { 0x90084, 0xe0 }, + { 0x90085, 0x109 }, + { 0x90086, 0xa }, + { 0x90087, 0x10 }, + { 0x90088, 0x109 }, + { 0x90089, 0x9 }, + { 0x9008a, 0x3c0 }, + { 0x9008b, 0x149 }, + { 0x9008c, 0x9 }, + { 0x9008d, 0x3c0 }, + { 0x9008e, 0x159 }, + { 0x9008f, 0x18 }, + { 0x90090, 0x10 }, + { 0x90091, 0x109 }, + { 0x90092, 0x0 }, + { 0x90093, 0x3c0 }, + { 0x90094, 0x109 }, + { 0x90095, 0x18 }, + { 0x90096, 0x4 }, + { 0x90097, 0x48 }, + { 0x90098, 0x18 }, + { 0x90099, 0x4 }, + { 0x9009a, 0x58 }, + { 0x9009b, 0xb }, + { 0x9009c, 0x10 }, + { 0x9009d, 0x109 }, + { 0x9009e, 0x1 }, + { 0x9009f, 0x10 }, + { 0x900a0, 0x109 }, + { 0x900a1, 0x5 }, + { 0x900a2, 0x7c0 }, + { 0x900a3, 0x109 }, + { 0x40000, 0x811 }, + { 0x40020, 0x880 }, + { 0x40040, 0x0 }, + { 0x40060, 0x0 }, + { 0x40001, 0x4008 }, + { 0x40021, 0x83 }, + { 0x40041, 0x4f }, + { 0x40061, 0x0 }, + { 0x40002, 0x4040 }, + { 0x40022, 0x83 }, + { 0x40042, 0x51 }, + { 0x40062, 0x0 }, + { 0x40003, 0x811 }, + { 0x40023, 0x880 }, + { 0x40043, 0x0 }, + { 0x40063, 0x0 }, + { 0x40004, 0x720 }, + { 0x40024, 0xf }, + { 0x40044, 0x1740 }, + { 0x40064, 0x0 }, + { 0x40005, 0x16 }, + { 0x40025, 0x83 }, + { 0x40045, 0x4b }, + { 0x40065, 0x0 }, + { 0x40006, 0x716 }, + { 0x40026, 0xf }, + { 0x40046, 0x2001 }, + { 0x40066, 0x0 }, + { 0x40007, 0x716 }, + { 0x40027, 0xf }, + { 0x40047, 0x2800 }, + { 0x40067, 0x0 }, + { 0x40008, 0x716 }, + { 0x40028, 0xf }, + { 0x40048, 0xf00 }, + { 0x40068, 0x0 }, + { 0x40009, 0x720 }, + { 0x40029, 0xf }, + { 0x40049, 0x1400 }, + { 0x40069, 0x0 }, + { 0x4000a, 0xe08 }, + { 0x4002a, 0xc15 }, + { 0x4004a, 0x0 }, + { 0x4006a, 0x0 }, + { 0x4000b, 0x625 }, + { 0x4002b, 0x15 }, + { 0x4004b, 0x0 }, + { 0x4006b, 0x0 }, + { 0x4000c, 0x4028 }, + { 0x4002c, 0x80 }, + { 0x4004c, 0x0 }, + { 0x4006c, 0x0 }, + { 0x4000d, 0xe08 }, + { 0x4002d, 0xc1a }, + { 0x4004d, 0x0 }, + { 0x4006d, 0x0 }, + { 0x4000e, 0x625 }, + { 0x4002e, 0x1a }, + { 0x4004e, 0x0 }, + { 0x4006e, 0x0 }, + { 0x4000f, 0x4040 }, + { 0x4002f, 0x80 }, + { 0x4004f, 0x0 }, + { 0x4006f, 0x0 }, + { 0x40010, 0x2604 }, + { 0x40030, 0x15 }, + { 0x40050, 0x0 }, + { 0x40070, 0x0 }, + { 0x40011, 0x708 }, + { 0x40031, 0x5 }, + { 0x40051, 0x0 }, + { 0x40071, 0x2002 }, + { 0x40012, 0x8 }, + { 0x40032, 0x80 }, + { 0x40052, 0x0 }, + { 0x40072, 0x0 }, + { 0x40013, 0x2604 }, + { 0x40033, 0x1a }, + { 0x40053, 0x0 }, + { 0x40073, 0x0 }, + { 0x40014, 0x708 }, + { 0x40034, 0xa }, + { 0x40054, 0x0 }, + { 0x40074, 0x2002 }, + { 0x40015, 0x4040 }, + { 0x40035, 0x80 }, + { 0x40055, 0x0 }, + { 0x40075, 0x0 }, + { 0x40016, 0x60a }, + { 0x40036, 0x15 }, + { 0x40056, 0x1200 }, + { 0x40076, 0x0 }, + { 0x40017, 0x61a }, + { 0x40037, 0x15 }, + { 0x40057, 0x1300 }, + { 0x40077, 0x0 }, + { 0x40018, 0x60a }, + { 0x40038, 0x1a }, + { 0x40058, 0x1200 }, + { 0x40078, 0x0 }, + { 0x40019, 0x642 }, + { 0x40039, 0x1a }, + { 0x40059, 0x1300 }, + { 0x40079, 0x0 }, + { 0x4001a, 0x4808 }, + { 0x4003a, 0x880 }, + { 0x4005a, 0x0 }, + { 0x4007a, 0x0 }, + { 0x900a4, 0x0 }, + { 0x900a5, 0x790 }, + { 0x900a6, 0x11a }, + { 0x900a7, 0x8 }, + { 0x900a8, 0x7aa }, + { 0x900a9, 0x2a }, + { 0x900aa, 0x10 }, + { 0x900ab, 0x7b2 }, + { 0x900ac, 0x2a }, + { 0x900ad, 0x0 }, + { 0x900ae, 0x7c8 }, + { 0x900af, 0x109 }, + { 0x900b0, 0x10 }, + { 0x900b1, 0x10 }, + { 0x900b2, 0x109 }, + { 0x900b3, 0x10 }, + { 0x900b4, 0x2a8 }, + { 0x900b5, 0x129 }, + { 0x900b6, 0x8 }, + { 0x900b7, 0x370 }, + { 0x900b8, 0x129 }, + { 0x900b9, 0xa }, + { 0x900ba, 0x3c8 }, + { 0x900bb, 0x1a9 }, + { 0x900bc, 0xc }, + { 0x900bd, 0x408 }, + { 0x900be, 0x199 }, + { 0x900bf, 0x14 }, + { 0x900c0, 0x790 }, + { 0x900c1, 0x11a }, + { 0x900c2, 0x8 }, + { 0x900c3, 0x4 }, + { 0x900c4, 0x18 }, + { 0x900c5, 0xe }, + { 0x900c6, 0x408 }, + { 0x900c7, 0x199 }, + { 0x900c8, 0x8 }, + { 0x900c9, 0x8568 }, + { 0x900ca, 0x108 }, + { 0x900cb, 0x18 }, + { 0x900cc, 0x790 }, + { 0x900cd, 0x16a }, + { 0x900ce, 0x8 }, + { 0x900cf, 0x1d8 }, + { 0x900d0, 0x169 }, + { 0x900d1, 0x10 }, + { 0x900d2, 0x8558 }, + { 0x900d3, 0x168 }, + { 0x900d4, 0x70 }, + { 0x900d5, 0x788 }, + { 0x900d6, 0x16a }, + { 0x900d7, 0x1ff8 }, + { 0x900d8, 0x85a8 }, + { 0x900d9, 0x1e8 }, + { 0x900da, 0x50 }, + { 0x900db, 0x798 }, + { 0x900dc, 0x16a }, + { 0x900dd, 0x60 }, + { 0x900de, 0x7a0 }, + { 0x900df, 0x16a }, + { 0x900e0, 0x8 }, + { 0x900e1, 0x8310 }, + { 0x900e2, 0x168 }, + { 0x900e3, 0x8 }, + { 0x900e4, 0xa310 }, + { 0x900e5, 0x168 }, + { 0x900e6, 0xa }, + { 0x900e7, 0x408 }, + { 0x900e8, 0x169 }, + { 0x900e9, 0x6e }, + { 0x900ea, 0x0 }, + { 0x900eb, 0x68 }, + { 0x900ec, 0x0 }, + { 0x900ed, 0x408 }, + { 0x900ee, 0x169 }, + { 0x900ef, 0x0 }, + { 0x900f0, 0x8310 }, + { 0x900f1, 0x168 }, + { 0x900f2, 0x0 }, + { 0x900f3, 0xa310 }, + { 0x900f4, 0x168 }, + { 0x900f5, 0x1ff8 }, + { 0x900f6, 0x85a8 }, + { 0x900f7, 0x1e8 }, + { 0x900f8, 0x68 }, + { 0x900f9, 0x798 }, + { 0x900fa, 0x16a }, + { 0x900fb, 0x78 }, + { 0x900fc, 0x7a0 }, + { 0x900fd, 0x16a }, + { 0x900fe, 0x68 }, + { 0x900ff, 0x790 }, + { 0x90100, 0x16a }, + { 0x90101, 0x8 }, + { 0x90102, 0x8b10 }, + { 0x90103, 0x168 }, + { 0x90104, 0x8 }, + { 0x90105, 0xab10 }, + { 0x90106, 0x168 }, + { 0x90107, 0xa }, + { 0x90108, 0x408 }, + { 0x90109, 0x169 }, + { 0x9010a, 0x58 }, + { 0x9010b, 0x0 }, + { 0x9010c, 0x68 }, + { 0x9010d, 0x0 }, + { 0x9010e, 0x408 }, + { 0x9010f, 0x169 }, + { 0x90110, 0x0 }, + { 0x90111, 0x8b10 }, + { 0x90112, 0x168 }, + { 0x90113, 0x1 }, + { 0x90114, 0xab10 }, + { 0x90115, 0x168 }, + { 0x90116, 0x0 }, + { 0x90117, 0x1d8 }, + { 0x90118, 0x169 }, + { 0x90119, 0x80 }, + { 0x9011a, 0x790 }, + { 0x9011b, 0x16a }, + { 0x9011c, 0x18 }, + { 0x9011d, 0x7aa }, + { 0x9011e, 0x6a }, + { 0x9011f, 0xa }, + { 0x90120, 0x0 }, + { 0x90121, 0x1e9 }, + { 0x90122, 0x8 }, + { 0x90123, 0x8080 }, + { 0x90124, 0x108 }, + { 0x90125, 0xf }, + { 0x90126, 0x408 }, + { 0x90127, 0x169 }, + { 0x90128, 0xc }, + { 0x90129, 0x0 }, + { 0x9012a, 0x68 }, + { 0x9012b, 0x9 }, + { 0x9012c, 0x0 }, + { 0x9012d, 0x1a9 }, + { 0x9012e, 0x0 }, + { 0x9012f, 0x408 }, + { 0x90130, 0x169 }, + { 0x90131, 0x0 }, + { 0x90132, 0x8080 }, + { 0x90133, 0x108 }, + { 0x90134, 0x8 }, + { 0x90135, 0x7aa }, + { 0x90136, 0x6a }, + { 0x90137, 0x0 }, + { 0x90138, 0x8568 }, + { 0x90139, 0x108 }, + { 0x9013a, 0xb7 }, + { 0x9013b, 0x790 }, + { 0x9013c, 0x16a }, + { 0x9013d, 0x1f }, + { 0x9013e, 0x0 }, + { 0x9013f, 0x68 }, + { 0x90140, 0x8 }, + { 0x90141, 0x8558 }, + { 0x90142, 0x168 }, + { 0x90143, 0xf }, + { 0x90144, 0x408 }, + { 0x90145, 0x169 }, + { 0x90146, 0xd }, + { 0x90147, 0x0 }, + { 0x90148, 0x68 }, + { 0x90149, 0x0 }, + { 0x9014a, 0x408 }, + { 0x9014b, 0x169 }, + { 0x9014c, 0x0 }, + { 0x9014d, 0x8558 }, + { 0x9014e, 0x168 }, + { 0x9014f, 0x8 }, + { 0x90150, 0x3c8 }, + { 0x90151, 0x1a9 }, + { 0x90152, 0x3 }, + { 0x90153, 0x370 }, + { 0x90154, 0x129 }, + { 0x90155, 0x20 }, + { 0x90156, 0x2aa }, + { 0x90157, 0x9 }, + { 0x90158, 0x8 }, + { 0x90159, 0xe8 }, + { 0x9015a, 0x109 }, + { 0x9015b, 0x0 }, + { 0x9015c, 0x8140 }, + { 0x9015d, 0x10c }, + { 0x9015e, 0x10 }, + { 0x9015f, 0x8138 }, + { 0x90160, 0x104 }, + { 0x90161, 0x8 }, + { 0x90162, 0x448 }, + { 0x90163, 0x109 }, + { 0x90164, 0xf }, + { 0x90165, 0x7c0 }, + { 0x90166, 0x109 }, + { 0x90167, 0x0 }, + { 0x90168, 0xe8 }, + { 0x90169, 0x109 }, + { 0x9016a, 0x47 }, + { 0x9016b, 0x630 }, + { 0x9016c, 0x109 }, + { 0x9016d, 0x8 }, + { 0x9016e, 0x618 }, + { 0x9016f, 0x109 }, + { 0x90170, 0x8 }, + { 0x90171, 0xe0 }, + { 0x90172, 0x109 }, + { 0x90173, 0x0 }, + { 0x90174, 0x7c8 }, + { 0x90175, 0x109 }, + { 0x90176, 0x8 }, + { 0x90177, 0x8140 }, + { 0x90178, 0x10c }, + { 0x90179, 0x0 }, + { 0x9017a, 0x478 }, + { 0x9017b, 0x109 }, + { 0x9017c, 0x0 }, + { 0x9017d, 0x1 }, + { 0x9017e, 0x8 }, + { 0x9017f, 0x8 }, + { 0x90180, 0x4 }, + { 0x90181, 0x0 }, + { 0x90006, 0x8 }, + { 0x90007, 0x7c8 }, + { 0x90008, 0x109 }, + { 0x90009, 0x0 }, + { 0x9000a, 0x400 }, + { 0x9000b, 0x106 }, + { 0xd00e7, 0x400 }, + { 0x90017, 0x0 }, + { 0x9001f, 0x29 }, + { 0x90026, 0x68 }, + { 0x400d0, 0x0 }, + { 0x400d1, 0x101 }, + { 0x400d2, 0x105 }, + { 0x400d3, 0x107 }, + { 0x400d4, 0x10f }, + { 0x400d5, 0x202 }, + { 0x400d6, 0x20a }, + { 0x400d7, 0x20b }, + { 0x2003a, 0x2 }, + { 0x200be, 0x3 }, + { 0x2000b, 0x74 }, + { 0x2000c, 0xe8 }, + { 0x2000d, 0x915 }, + { 0x2000e, 0x2c }, + { 0x12000b, 0xc }, + { 0x12000c, 0x19 }, + { 0x12000d, 0xfa }, + { 0x12000e, 0x10 }, + { 0x22000b, 0x3 }, + { 0x22000c, 0x6 }, + { 0x22000d, 0x3e }, + { 0x22000e, 0x10 }, + { 0x9000c, 0x0 }, + { 0x9000d, 0x173 }, + { 0x9000e, 0x60 }, + { 0x9000f, 0x6110 }, + { 0x90010, 0x2152 }, + { 0x90011, 0xdfbd }, + { 0x90012, 0x2060 }, + { 0x90013, 0x6152 }, + { 0x20010, 0x5a }, + { 0x20011, 0x3 }, + { 0x40080, 0xe0 }, + { 0x40081, 0x12 }, + { 0x40082, 0xe0 }, + { 0x40083, 0x12 }, + { 0x40084, 0xe0 }, + { 0x40085, 0x12 }, + { 0x140080, 0xe0 }, + { 0x140081, 0x12 }, + { 0x140082, 0xe0 }, + { 0x140083, 0x12 }, + { 0x140084, 0xe0 }, + { 0x140085, 0x12 }, + { 0x240080, 0xe0 }, + { 0x240081, 0x12 }, + { 0x240082, 0xe0 }, + { 0x240083, 0x12 }, + { 0x240084, 0xe0 }, + { 0x240085, 0x12 }, + { 0x400fd, 0xf }, + { 0x10011, 0x1 }, + { 0x10012, 0x1 }, + { 0x10013, 0x180 }, + { 0x10018, 0x1 }, + { 0x10002, 0x6209 }, + { 0x100b2, 0x1 }, + { 0x101b4, 0x1 }, + { 0x102b4, 0x1 }, + { 0x103b4, 0x1 }, + { 0x104b4, 0x1 }, + { 0x105b4, 0x1 }, + { 0x106b4, 0x1 }, + { 0x107b4, 0x1 }, + { 0x108b4, 0x1 }, + { 0x11011, 0x1 }, + { 0x11012, 0x1 }, + { 0x11013, 0x180 }, + { 0x11018, 0x1 }, + { 0x11002, 0x6209 }, + { 0x110b2, 0x1 }, + { 0x111b4, 0x1 }, + { 0x112b4, 0x1 }, + { 0x113b4, 0x1 }, + { 0x114b4, 0x1 }, + { 0x115b4, 0x1 }, + { 0x116b4, 0x1 }, + { 0x117b4, 0x1 }, + { 0x118b4, 0x1 }, + { 0x12011, 0x1 }, + { 0x12012, 0x1 }, + { 0x12013, 0x180 }, + { 0x12018, 0x1 }, + { 0x12002, 0x6209 }, + { 0x120b2, 0x1 }, + { 0x121b4, 0x1 }, + { 0x122b4, 0x1 }, + { 0x123b4, 0x1 }, + { 0x124b4, 0x1 }, + { 0x125b4, 0x1 }, + { 0x126b4, 0x1 }, + { 0x127b4, 0x1 }, + { 0x128b4, 0x1 }, + { 0x13011, 0x1 }, + { 0x13012, 0x1 }, + { 0x13013, 0x180 }, + { 0x13018, 0x1 }, + { 0x13002, 0x6209 }, + { 0x130b2, 0x1 }, + { 0x131b4, 0x1 }, + { 0x132b4, 0x1 }, + { 0x133b4, 0x1 }, + { 0x134b4, 0x1 }, + { 0x135b4, 0x1 }, + { 0x136b4, 0x1 }, + { 0x137b4, 0x1 }, + { 0x138b4, 0x1 }, + { 0x20089, 0x1 }, + { 0x20088, 0x19 }, + { 0xc0080, 0x2 }, + { 0xd0000, 0x1 } +}; + +struct dram_fsp_msg ddr_dram_fsp_msg[] = { + { + /* P0 3732mts 1D */ + .drate = 3732, + .fw_type = FW_1D_IMAGE, + .fsp_cfg = ddr_fsp0_cfg, + .fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_cfg), + }, + { + /* P1 400mts 1D */ + .drate = 400, + .fw_type = FW_1D_IMAGE, + .fsp_cfg = ddr_fsp1_cfg, + .fsp_cfg_num = ARRAY_SIZE(ddr_fsp1_cfg), + }, + { + /* P2 100mts 1D */ + .drate = 100, + .fw_type = FW_1D_IMAGE, + .fsp_cfg = ddr_fsp2_cfg, + .fsp_cfg_num = ARRAY_SIZE(ddr_fsp2_cfg), + }, + { + /* P0 3732mts 2D */ + .drate = 3732, + .fw_type = FW_2D_IMAGE, + .fsp_cfg = ddr_fsp0_2d_cfg, + .fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_2d_cfg), + }, +}; + +/* ddr timing config params */ +struct dram_timing_info dram_timing = { + .ddrc_cfg = ddr_ddrc_cfg, + .ddrc_cfg_num = ARRAY_SIZE(ddr_ddrc_cfg), + .ddrphy_cfg = ddr_ddrphy_cfg, + .ddrphy_cfg_num = ARRAY_SIZE(ddr_ddrphy_cfg), + .fsp_msg = ddr_dram_fsp_msg, + .fsp_msg_num = ARRAY_SIZE(ddr_dram_fsp_msg), + .ddrphy_trained_csr = ddr_ddrphy_trained_csr, + .ddrphy_trained_csr_num = ARRAY_SIZE(ddr_ddrphy_trained_csr), + .ddrphy_pie = ddr_phy_pie, + .ddrphy_pie_num = ARRAY_SIZE(ddr_phy_pie), + .fsp_table = { 3732, 400, 100, }, +}; + diff --git a/board/polyhex/imx8mp_debix_model_a/spl.c b/board/polyhex/imx8mp_debix_model_a/spl.c new file mode 100644 index 00000000000..eb904e116b1 --- /dev/null +++ b/board/polyhex/imx8mp_debix_model_a/spl.c @@ -0,0 +1,129 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Copyright 2018-2019, 2021 NXP + * Copyright 2023 Gilles Talis + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +int spl_board_boot_device(enum boot_device boot_dev_spl) +{ + return BOOT_DEVICE_BOOTROM; +} + +void spl_dram_init(void) +{ + ddr_init(&dram_timing); +} + +void spl_board_init(void) +{ + /* + * Set GIC clock to 500Mhz for OD VDD_SOC. Kernel driver does + * not allow to change it. Should set the clock after PMIC + * setting done. Default is 400Mhz (system_pll1_800m with div = 2) + * set by ROM for ND VDD_SOC + */ + clock_enable(CCGR_GIC, 0); + clock_set_target_val(GIC_CLK_ROOT, CLK_ROOT_ON | CLK_ROOT_SOURCE_SEL(5)); + clock_enable(CCGR_GIC, 1); + + puts("Normal Boot\n"); +} + +static int power_init_board(void) +{ + struct udevice *dev; + int ret; + + ret = pmic_get("pmic@25", &dev); + if (ret == -ENODEV) { + puts("Failed to get PMIC\n"); + return 0; + } + if (ret != 0) + return ret; + + /* BUCKxOUT_DVS0/1 control BUCK123 output. */ + pmic_reg_write(dev, PCA9450_BUCK123_DVS, 0x29); + + /* Increase VDD_SOC to typical value 0.95V before first DRAM access. */ + if (IS_ENABLED(CONFIG_IMX8M_VDD_SOC_850MV)) + /* Set DVS0 to 0.85V for special case. */ + pmic_reg_write(dev, PCA9450_BUCK1OUT_DVS0, 0x14); + else + pmic_reg_write(dev, PCA9450_BUCK1OUT_DVS0, 0x1c); + + /* Set DVS1 to 0.85v for suspend. */ + pmic_reg_write(dev, PCA9450_BUCK1OUT_DVS1, 0x14); + + /* + * Enable DVS control through PMIC_STBY_REQ and + * set B1_ENMODE=1 (ON by PMIC_ON_REQ=H). + */ + pmic_reg_write(dev, PCA9450_BUCK1CTRL, 0x59); + + /* + * Kernel uses OD/OD frequency for SoC. + * To avoid timing risk from SoC to ARM, + * increase VDD_ARM to OD voltage 0.95V + */ + pmic_reg_write(dev, PCA9450_BUCK2OUT_DVS0, 0x1C); + + return 0; +} + +int board_fit_config_name_match(const char *name) +{ + if (is_imx8mp() && + !strcmp(name, "imx8mp-debix-model-a")) + return 0; + + return -1; +} + +void board_init_f(ulong dummy) +{ + int ret; + + arch_cpu_init(); + + init_uart_clk(1); + + /* Clear the BSS. */ + memset(__bss_start, 0, __bss_end - __bss_start); + + ret = spl_init(); + if (ret) { + debug("spl_init() failed: %d\n", ret); + hang(); + } + + preloader_console_init(); + + enable_tzc380(); + + power_init_board(); + + /* DDR initialization */ + spl_dram_init(); + + board_init_r(NULL, 0); +} diff --git a/configs/imx8mp_debix_model_a_defconfig b/configs/imx8mp_debix_model_a_defconfig new file mode 100644 index 00000000000..5de80233bd5 --- /dev/null +++ b/configs/imx8mp_debix_model_a_defconfig @@ -0,0 +1,110 @@ +CONFIG_ARM=y +CONFIG_ARCH_IMX8M=y +CONFIG_TEXT_BASE=0x40200000 +CONFIG_SYS_MALLOC_LEN=0x2000000 +CONFIG_SPL_GPIO=y +CONFIG_SPL_LIBCOMMON_SUPPORT=y +CONFIG_SPL_LIBGENERIC_SUPPORT=y +CONFIG_ENV_SIZE=0x1000 +CONFIG_ENV_OFFSET=0x400000 +CONFIG_DM_GPIO=y +CONFIG_DEFAULT_DEVICE_TREE="imx8mp-debix-model-a" +CONFIG_SPL_TEXT_BASE=0x920000 +CONFIG_TARGET_IMX8MP_DEBIX_MODEL_A=y +CONFIG_SYS_PROMPT="u-boot=> " +CONFIG_SPL_MMC=y +CONFIG_SPL_SERIAL=y +CONFIG_SPL_DRIVERS_MISC=y +CONFIG_SPL_STACK=0x960000 +CONFIG_SPL=y +CONFIG_SPL_IMX_ROMAPI_LOADADDR=0x48000000 +CONFIG_SYS_LOAD_ADDR=0x40480000 +CONFIG_SYS_MONITOR_LEN=524288 +CONFIG_FIT=y +CONFIG_FIT_EXTERNAL_OFFSET=0x3000 +CONFIG_SPL_LOAD_FIT=y +CONFIG_OF_SYSTEM_SETUP=y +CONFIG_DISTRO_DEFAULTS=y +CONFIG_DEFAULT_FDT_FILE="imx8mp-debix-model-a.dtb" +CONFIG_BOARD_LATE_INIT=y +CONFIG_SPL_MAX_SIZE=0x26000 +CONFIG_SPL_HAS_BSS_LINKER_SECTION=y +CONFIG_SPL_BSS_START_ADDR=0x98fc00 +CONFIG_SPL_BSS_MAX_SIZE=0x400 +CONFIG_SPL_BOARD_INIT=y +CONFIG_SPL_BOOTROM_SUPPORT=y +CONFIG_SPL_SYS_MALLOC_SIMPLE=y +# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set +CONFIG_SYS_SPL_MALLOC=y +CONFIG_HAS_CUSTOM_SPL_MALLOC_START=y +CONFIG_CUSTOM_SYS_SPL_MALLOC_ADDR=0x42200000 +CONFIG_SYS_SPL_MALLOC_SIZE=0x80000 +CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y +CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x300 +CONFIG_SPL_I2C=y +CONFIG_SPL_POWER=y +CONFIG_SPL_WATCHDOG=y +CONFIG_SYS_MAXARGS=64 +CONFIG_SYS_CBSIZE=2048 +CONFIG_SYS_PBSIZE=2074 +CONFIG_SYS_BOOTM_LEN=0x2000000 +# CONFIG_CMD_EXPORTENV is not set +# CONFIG_CMD_IMPORTENV is not set +# CONFIG_CMD_CRC32 is not set +CONFIG_CMD_CLK=y +CONFIG_CMD_FUSE=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_REGULATOR=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_OF_CONTROL=y +CONFIG_SPL_OF_CONTROL=y +CONFIG_ENV_OVERWRITE=y +CONFIG_ENV_IS_IN_MMC=y +CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_SYS_MMC_ENV_DEV=1 +CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y +CONFIG_USE_ETHPRIME=y +CONFIG_ETHPRIME="eth1" +CONFIG_SPL_DM=y +CONFIG_CLK_COMPOSITE_CCF=y +CONFIG_CLK_IMX8MP=y +CONFIG_MXC_GPIO=y +CONFIG_DM_I2C=y +CONFIG_LED=y +CONFIG_LED_GPIO=y +CONFIG_SUPPORT_EMMC_BOOT=y +CONFIG_MMC_IO_VOLTAGE=y +CONFIG_MMC_UHS_SUPPORT=y +CONFIG_MMC_HS400_ES_SUPPORT=y +CONFIG_MMC_HS400_SUPPORT=y +CONFIG_FSL_USDHC=y +CONFIG_PHY_REALTEK=y +CONFIG_DM_ETH_PHY=y +CONFIG_PHY_GIGE=y +CONFIG_DWC_ETH_QOS=y +CONFIG_DWC_ETH_QOS_IMX=y +CONFIG_FEC_MXC=y +CONFIG_MII=y +CONFIG_PINCTRL=y +CONFIG_SPL_PINCTRL=y +CONFIG_PINCTRL_IMX8M=y +CONFIG_DM_PMIC=y +CONFIG_DM_PMIC_PCA9450=y +CONFIG_SPL_DM_PMIC_PCA9450=y +CONFIG_DM_REGULATOR=y +CONFIG_SPL_DM_REGULATOR=y +CONFIG_DM_REGULATOR_PCA9450=y +CONFIG_SPL_DM_REGULATOR_PCA9450=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +# CONFIG_SPL_POWER_I2C=y +CONFIG_DM_SERIAL=y +CONFIG_MXC_UART=y +CONFIG_SYSRESET=y +CONFIG_SPL_SYSRESET=y +CONFIG_SYSRESET_PSCI=y +CONFIG_SYSRESET_WATCHDOG=y +CONFIG_IMX_WATCHDOG=y diff --git a/include/configs/imx8mp_debix_model_a.h b/include/configs/imx8mp_debix_model_a.h new file mode 100644 index 00000000000..e82e8b16b1d --- /dev/null +++ b/include/configs/imx8mp_debix_model_a.h @@ -0,0 +1,54 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2019 NXP + * Copyright 2023 Gilles Talis + */ + +#ifndef __IMX8MP_DEBIX_MODEL_A_H +#define __IMX8MP_DEBIX_MODEL_A_H + +#include +#include +#include + +#define CFG_SYS_UBOOT_BASE (QSPI0_AMBA_BASE + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512) + +#if defined(CONFIG_CMD_NET) +#define CFG_FEC_MXC_PHYADDR 1 + +#define PHY_ANEG_TIMEOUT 20000 + +#endif + +#define BOOT_TARGET_DEVICES(func) \ + func(MMC, mmc, 1) \ + func(MMC, mmc, 2) + +#include + +/* Initial environment variables */ +#define CFG_EXTRA_ENV_SETTINGS \ + BOOTENV \ + "scriptaddr=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \ + "kernel_addr_r=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \ + "image=Image\0" \ + "console=ttymxc1,115200 earlycon=ec_imx6q,0x30890000,115200\0" \ + "fdt_addr_r=0x43000000\0" \ + "boot_fdt=try\0" \ + "fdtfile=" CONFIG_DEFAULT_FDT_FILE "\0" \ + "initrd_addr=0x43800000\0" \ + "bootm_size=0x10000000\0" \ + "mmcpart=1\0" \ + "mmcroot=/dev/mmcblk1p2 rootwait rw\0" \ + +/* Link Definitions */ + +#define CFG_SYS_INIT_RAM_ADDR 0x40000000 +#define CFG_SYS_INIT_RAM_SIZE 0x80000 + +/* 2GB DDR */ +#define CFG_SYS_SDRAM_BASE 0x40000000 +#define PHYS_SDRAM 0x40000000 +#define PHYS_SDRAM_SIZE 0x80000000 /* 2 GB */ + +#endif -- cgit v1.3.1 From c435538888f128afa8ab2519496fc2e7ad17a4c2 Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Wed, 13 Dec 2023 09:37:08 -0300 Subject: imx7d-sdb: Sync devicetree with kernel 6.5-rc1 Commit 0aea5dda2928 ("ARM: dts: imx7d-sdb-u-boot: Fix usdhc1 UHS operation") did a temporary workaround by addng the usdhc1 fix inside the -u-boot.dtsi file. The imx7d-sdb.dts from kernel 6.5-rc1 contains the proper UHS fix, so sync the devicetree tree and remove the previous fix from -u-boot.dtsi. Also, adjust the PMIC node name inside pmic_get() to match the devicetree update. Signed-off-by: Fabio Estevam --- arch/arm/dts/imx7d-sdb-u-boot.dtsi | 51 --------------------- arch/arm/dts/imx7d-sdb.dts | 73 +++++++++++++++++++++++-------- board/freescale/mx7dsabresd/mx7dsabresd.c | 2 +- 3 files changed, 56 insertions(+), 70 deletions(-) diff --git a/arch/arm/dts/imx7d-sdb-u-boot.dtsi b/arch/arm/dts/imx7d-sdb-u-boot.dtsi index 71bfd80aab8..eace17e052e 100644 --- a/arch/arm/dts/imx7d-sdb-u-boot.dtsi +++ b/arch/arm/dts/imx7d-sdb-u-boot.dtsi @@ -18,57 +18,6 @@ dr_mode = "peripheral"; }; -&usdhc1 { - pinctrl-names = "default", "state_100mhz", "state_200mhz"; - pinctrl-0 = <&pinctrl_usdhc1>, <&pinctrl_usdhc1_gpio>; - pinctrl-1 = <&pinctrl_usdhc1_100mhz>, <&pinctrl_usdhc1_gpio>; - pinctrl-2 = <&pinctrl_usdhc1_200mhz>, <&pinctrl_usdhc1_gpio>; -}; - -&pinctrl_usdhc1 { - fsl,pins = < - MX7D_PAD_SD1_CMD__SD1_CMD 0x59 - MX7D_PAD_SD1_CLK__SD1_CLK 0x19 - MX7D_PAD_SD1_DATA0__SD1_DATA0 0x59 - MX7D_PAD_SD1_DATA1__SD1_DATA1 0x59 - MX7D_PAD_SD1_DATA2__SD1_DATA2 0x59 - MX7D_PAD_SD1_DATA3__SD1_DATA3 0x59 - >; -}; - -&iomuxc { - pinctrl_usdhc1_gpio: usdhc1gpiogrp { - fsl,pins = < - MX7D_PAD_SD1_CD_B__GPIO5_IO0 0x59 /* CD */ - MX7D_PAD_SD1_WP__GPIO5_IO1 0x59 /* WP */ - MX7D_PAD_SD1_RESET_B__GPIO5_IO2 0x59 /* vmmc */ - MX7D_PAD_GPIO1_IO08__SD1_VSELECT 0x59 /* VSELECT */ - >; - }; - - pinctrl_usdhc1_100mhz: usdhc1100mhzgrp { - fsl,pins = < - MX7D_PAD_SD1_CMD__SD1_CMD 0x5a - MX7D_PAD_SD1_CLK__SD1_CLK 0x1a - MX7D_PAD_SD1_DATA0__SD1_DATA0 0x5a - MX7D_PAD_SD1_DATA1__SD1_DATA1 0x5a - MX7D_PAD_SD1_DATA2__SD1_DATA2 0x5a - MX7D_PAD_SD1_DATA3__SD1_DATA3 0x5a - >; - }; - - pinctrl_usdhc1_200mhz: usdhc1200mhzgrp { - fsl,pins = < - MX7D_PAD_SD1_CMD__SD1_CMD 0x5b - MX7D_PAD_SD1_CLK__SD1_CLK 0x1b - MX7D_PAD_SD1_DATA0__SD1_DATA0 0x5b - MX7D_PAD_SD1_DATA1__SD1_DATA1 0x5b - MX7D_PAD_SD1_DATA2__SD1_DATA2 0x5b - MX7D_PAD_SD1_DATA3__SD1_DATA3 0x5b - >; - }; -}; - &wdog1 { bootph-pre-ram; }; diff --git a/arch/arm/dts/imx7d-sdb.dts b/arch/arm/dts/imx7d-sdb.dts index 78f4224a9bf..75f1cd14bea 100644 --- a/arch/arm/dts/imx7d-sdb.dts +++ b/arch/arm/dts/imx7d-sdb.dts @@ -24,14 +24,14 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_gpio_keys>; - volume-up { + key-volume-up { label = "Volume Up"; gpios = <&gpio5 11 GPIO_ACTIVE_LOW>; linux,code = ; wakeup-source; }; - volume-down { + key-volume-down { label = "Volume Down"; gpios = <&gpio5 10 GPIO_ACTIVE_LOW>; linux,code = ; @@ -39,12 +39,12 @@ }; }; - spi4 { + spi-4 { compatible = "spi-gpio"; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_spi4>; - gpio-sck = <&gpio1 13 GPIO_ACTIVE_HIGH>; - gpio-mosi = <&gpio1 9 GPIO_ACTIVE_HIGH>; + sck-gpios = <&gpio1 13 GPIO_ACTIVE_HIGH>; + mosi-gpios = <&gpio1 9 GPIO_ACTIVE_HIGH>; cs-gpios = <&gpio1 12 GPIO_ACTIVE_LOW>; num-chipselects = <1>; #address-cells = <1>; @@ -60,6 +60,17 @@ }; }; + reg_sd1_vmmc: regulator-sd1-vmmc { + compatible = "regulator-fixed"; + regulator-name = "VDD_SD1"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio5 2 GPIO_ACTIVE_HIGH>; + enable-active-high; + startup-delay-us = <200000>; + off-on-delay-us = <20000>; + }; + reg_usb_otg1_vbus: regulator-usb-otg1-vbus { compatible = "regulator-fixed"; regulator-name = "usb_otg1_vbus"; @@ -205,13 +216,8 @@ pinctrl-0 = <&pinctrl_tsc2046_pendown>; interrupt-parent = <&gpio2>; interrupts = <29 0>; - pendown-gpio = <&gpio2 29 GPIO_ACTIVE_HIGH>; - ti,x-min = /bits/ 16 <0>; - ti,x-max = /bits/ 16 <0>; - ti,y-min = /bits/ 16 <0>; - ti,y-max = /bits/ 16 <0>; - ti,pressure-max = /bits/ 16 <0>; - ti,x-plate-ohms = /bits/ 16 <400>; + pendown-gpio = <&gpio2 29 GPIO_ACTIVE_LOW>; + touchscreen-max-pressure = <255>; wakeup-source; }; }; @@ -269,7 +275,7 @@ pinctrl-0 = <&pinctrl_i2c1>; status = "okay"; - pmic: pfuze3000@8 { + pmic: pmic@8 { compatible = "fsl,pfuze3000"; reg = <0x08>; @@ -478,10 +484,13 @@ }; &usdhc1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usdhc1>; + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc1>, <&pinctrl_usdhc1_gpio>; + pinctrl-1 = <&pinctrl_usdhc1_100mhz>, <&pinctrl_usdhc1_gpio>; + pinctrl-2 = <&pinctrl_usdhc1_200mhz>, <&pinctrl_usdhc1_gpio>; cd-gpios = <&gpio5 0 GPIO_ACTIVE_LOW>; wp-gpios = <&gpio5 1 GPIO_ACTIVE_HIGH>; + vmmc-supply = <®_sd1_vmmc>; wakeup-source; keep-power-in-suspend; status = "okay"; @@ -736,6 +745,15 @@ >; }; + pinctrl_usdhc1_gpio: usdhc1_gpiogrp { + fsl,pins = < + MX7D_PAD_SD1_CD_B__GPIO5_IO0 0x59 /* CD */ + MX7D_PAD_SD1_WP__GPIO5_IO1 0x59 /* WP */ + MX7D_PAD_SD1_RESET_B__GPIO5_IO2 0x59 /* vmmc */ + MX7D_PAD_GPIO1_IO08__SD1_VSELECT 0x59 /* VSELECT */ + >; + }; + pinctrl_usdhc1: usdhc1grp { fsl,pins = < MX7D_PAD_SD1_CMD__SD1_CMD 0x59 @@ -744,9 +762,28 @@ MX7D_PAD_SD1_DATA1__SD1_DATA1 0x59 MX7D_PAD_SD1_DATA2__SD1_DATA2 0x59 MX7D_PAD_SD1_DATA3__SD1_DATA3 0x59 - MX7D_PAD_SD1_CD_B__GPIO5_IO0 0x59 /* CD */ - MX7D_PAD_SD1_WP__GPIO5_IO1 0x59 /* WP */ - MX7D_PAD_SD1_RESET_B__GPIO5_IO2 0x59 /* vmmc */ + >; + }; + + pinctrl_usdhc1_100mhz: usdhc1grp_100mhz { + fsl,pins = < + MX7D_PAD_SD1_CMD__SD1_CMD 0x5a + MX7D_PAD_SD1_CLK__SD1_CLK 0x1a + MX7D_PAD_SD1_DATA0__SD1_DATA0 0x5a + MX7D_PAD_SD1_DATA1__SD1_DATA1 0x5a + MX7D_PAD_SD1_DATA2__SD1_DATA2 0x5a + MX7D_PAD_SD1_DATA3__SD1_DATA3 0x5a + >; + }; + + pinctrl_usdhc1_200mhz: usdhc1grp_200mhz { + fsl,pins = < + MX7D_PAD_SD1_CMD__SD1_CMD 0x5b + MX7D_PAD_SD1_CLK__SD1_CLK 0x1b + MX7D_PAD_SD1_DATA0__SD1_DATA0 0x5b + MX7D_PAD_SD1_DATA1__SD1_DATA1 0x5b + MX7D_PAD_SD1_DATA2__SD1_DATA2 0x5b + MX7D_PAD_SD1_DATA3__SD1_DATA3 0x5b >; }; diff --git a/board/freescale/mx7dsabresd/mx7dsabresd.c b/board/freescale/mx7dsabresd/mx7dsabresd.c index cff2e6a8717..4fe23b51cd1 100644 --- a/board/freescale/mx7dsabresd/mx7dsabresd.c +++ b/board/freescale/mx7dsabresd/mx7dsabresd.c @@ -267,7 +267,7 @@ int power_init_board(void) struct udevice *dev; int ret, dev_id, rev_id; - ret = pmic_get("pfuze3000@8", &dev); + ret = pmic_get("pmic@8", &dev); if (ret == -ENODEV) return 0; if (ret != 0) -- cgit v1.3.1 From 3e0b1966961b458d21a7dab468777f63e11f9ab7 Mon Sep 17 00:00:00 2001 From: Cem Tenruh Date: Fri, 14 Jul 2023 10:23:26 +0200 Subject: arm: dts: imx8mm-phyboard-polis-rdk: Sync dts files with kernel Sync the devicetree files used in the kernel for the imx8mm-phyboard-polis with the corresponding devicetree files in U-Boot. Replaced phycore-imx8mm.dts with kernel dts imx8mm-phyboard-polis-rdk.dts Synced with kernel 6.5.0-rc1 commit e752a4f9589c (arm64: dts: freescale: imx8mm-phyboard: Add I2C4 pinmuxing) Signed-off-by: Cem Tenruh --- arch/arm/dts/Makefile | 2 +- arch/arm/dts/imx8mm-phyboard-polis-rdk-u-boot.dtsi | 71 ++++ arch/arm/dts/imx8mm-phyboard-polis-rdk.dts | 460 +++++++++++++++++++++ arch/arm/dts/imx8mm-phycore-som.dtsi | 440 ++++++++++++++++++++ arch/arm/dts/phycore-imx8mm-u-boot.dtsi | 71 ---- arch/arm/dts/phycore-imx8mm.dts | 287 ------------- board/phytec/phycore_imx8mm/MAINTAINERS | 5 +- configs/phycore-imx8mm_defconfig | 2 +- 8 files changed, 976 insertions(+), 362 deletions(-) create mode 100644 arch/arm/dts/imx8mm-phyboard-polis-rdk-u-boot.dtsi create mode 100644 arch/arm/dts/imx8mm-phyboard-polis-rdk.dts create mode 100644 arch/arm/dts/imx8mm-phycore-som.dtsi delete mode 100644 arch/arm/dts/phycore-imx8mm-u-boot.dtsi delete mode 100644 arch/arm/dts/phycore-imx8mm.dts diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index b415613740c..ef0e705f3d7 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -1074,6 +1074,7 @@ dtb-$(CONFIG_ARCH_IMX8M) += \ imx8mm-kontron-bl-osm-s.dtb \ imx8mm-mx8menlo.dtb \ imx8mm-phg.dtb \ + imx8mm-phyboard-polis-rdk.dtb \ imx8mm-venice.dtb \ imx8mm-venice-gw71xx-0x.dtb \ imx8mm-venice-gw72xx-0x.dtb \ @@ -1084,7 +1085,6 @@ dtb-$(CONFIG_ARCH_IMX8M) += \ imx8mm-venice-gw7904.dtb \ imx8mm-venice-gw7905-0x.dtb \ imx8mm-verdin-wifi-dev.dtb \ - phycore-imx8mm.dtb \ imx8mn-bsh-smm-s2.dtb \ imx8mn-bsh-smm-s2pro.dtb \ imx8mn-ddr4-evk.dtb \ diff --git a/arch/arm/dts/imx8mm-phyboard-polis-rdk-u-boot.dtsi b/arch/arm/dts/imx8mm-phyboard-polis-rdk-u-boot.dtsi new file mode 100644 index 00000000000..516e52e1f5d --- /dev/null +++ b/arch/arm/dts/imx8mm-phyboard-polis-rdk-u-boot.dtsi @@ -0,0 +1,71 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Copyright (C) 2020 PHYTEC Messtechnik GmbH + * Author: Teresa Remmet + */ + +#include "imx8mm-u-boot.dtsi" + +/ { + wdt-reboot { + compatible = "wdt-reboot"; + wdt = <&wdog1>; + bootph-pre-ram; + }; +}; + +&pinctrl_uart3 { + bootph-pre-ram; +}; + +&pinctrl_usdhc2_gpio { + bootph-pre-ram; +}; + +&pinctrl_usdhc2 { + bootph-pre-ram; +}; + +&pinctrl_usdhc3 { + bootph-pre-ram; +}; + +&pinctrl_wdog { + bootph-pre-ram; +}; + +&gpio1 { + bootph-pre-ram; +}; + +&gpio2 { + bootph-pre-ram; +}; + +&gpio3 { + bootph-pre-ram; +}; + +&gpio4 { + bootph-pre-ram; +}; + +&gpio5 { + bootph-pre-ram; +}; + +&uart3 { + bootph-pre-ram; +}; + +&usdhc2 { + bootph-pre-ram; +}; + +&usdhc3 { + bootph-pre-ram; +}; + +&wdog1 { + bootph-pre-ram; +}; diff --git a/arch/arm/dts/imx8mm-phyboard-polis-rdk.dts b/arch/arm/dts/imx8mm-phyboard-polis-rdk.dts new file mode 100644 index 00000000000..03e7679217b --- /dev/null +++ b/arch/arm/dts/imx8mm-phyboard-polis-rdk.dts @@ -0,0 +1,460 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2022 PHYTEC Messtechnik GmbH + * Author: Teresa Remmet + */ + +/dts-v1/; + +#include +#include +#include +#include "imx8mm-phycore-som.dtsi" + +/ { + model = "PHYTEC phyBOARD-Polis-i.MX8MM RDK"; + compatible = "phytec,imx8mm-phyboard-polis-rdk", + "phytec,imx8mm-phycore-som", "fsl,imx8mm"; + + chosen { + stdout-path = &uart3; + }; + + bt_osc_32k: bt-lp-clock { + compatible = "fixed-clock"; + clock-frequency = <32768>; + clock-output-names = "bt_osc_32k"; + #clock-cells = <0>; + }; + + can_osc_40m: can-clock { + compatible = "fixed-clock"; + clock-frequency = <40000000>; + clock-output-names = "can_osc_40m"; + #clock-cells = <0>; + }; + + fan { + compatible = "gpio-fan"; + gpios = <&gpio4 8 GPIO_ACTIVE_HIGH>; + gpio-fan,speed-map = <0 0 + 13000 1>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_fan>; + #cooling-cells = <2>; + }; + + leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_leds>; + + led-0 { + color = ; + function = LED_FUNCTION_DISK; + gpios = <&gpio1 1 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "mmc2"; + }; + + led-1 { + color = ; + function = LED_FUNCTION_DISK; + gpios = <&gpio1 15 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "mmc1"; + }; + + led-2 { + color = ; + function = LED_FUNCTION_CPU; + gpios = <&gpio1 14 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "heartbeat"; + }; + }; + + usdhc1_pwrseq: pwr-seq { + compatible = "mmc-pwrseq-simple"; + post-power-on-delay-ms = <100>; + power-off-delay-us = <60>; + reset-gpios = <&gpio2 7 GPIO_ACTIVE_LOW>; + }; + + reg_can_en: regulator-can-en { + compatible = "regulator-fixed"; + gpio = <&gpio1 9 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_can_en>; + regulator-max-microvolt = <3300000>; + regulator-min-microvolt = <3300000>; + regulator-name = "CAN_EN"; + startup-delay-us = <20>; + }; + + reg_usb_otg1_vbus: regulator-usb-otg1 { + compatible = "regulator-fixed"; + gpio = <&gpio1 12 GPIO_ACTIVE_HIGH>; + enable-active-high; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbotg1pwrgrp>; + regulator-name = "usb_otg1_vbus"; + regulator-max-microvolt = <5000000>; + regulator-min-microvolt = <5000000>; + }; + + reg_usdhc2_vmmc: regulator-usdhc2 { + compatible = "regulator-fixed"; + gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>; + enable-active-high; + off-on-delay-us = <20000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>; + regulator-max-microvolt = <3300000>; + regulator-min-microvolt = <3300000>; + regulator-name = "VSD_3V3"; + }; + + reg_vcc_3v3: regulator-vcc-3v3 { + compatible = "regulator-fixed"; + regulator-max-microvolt = <3300000>; + regulator-min-microvolt = <3300000>; + regulator-name = "VCC_3V3"; + }; +}; + +/* SPI - CAN MCP251XFD */ +&ecspi1 { + cs-gpios = <&gpio5 9 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi1>; + status = "okay"; + + can0: can@0 { + compatible = "microchip,mcp251xfd"; + clocks = <&can_osc_40m>; + interrupt-parent = <&gpio1>; + interrupts = <8 IRQ_TYPE_LEVEL_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_can_int>; + reg = <0>; + spi-max-frequency = <20000000>; + xceiver-supply = <®_can_en>; + }; +}; + +&gpio1 { + gpio-line-names = "nINT_ETHPHY", "LED_RED", "WDOG_INT", "X_RTC_INT", + "", "", "", "RESET_ETHPHY", + "CAN_nINT", "CAN_EN", "nENABLE_FLATLINK", "", + "USB_OTG_VBUS_EN", "", "LED_GREEN", "LED_BLUE"; +}; + +&gpio2 { + gpio-line-names = "", "", "", "", + "", "", "BT_REG_ON", "WL_REG_ON", + "BT_DEV_WAKE", "BT_HOST_WAKE", "", "", + "X_SD2_CD_B", "", "", "", + "", "", "", "SD2_RESET_B"; +}; + +&gpio4 { + gpio-line-names = "", "", "", "", + "", "", "", "", + "FAN", "miniPCIe_nPERST", "", "", + "COEX1", "COEX2"; +}; + +&gpio5 { + gpio-line-names = "", "", "", "", + "", "", "", "", + "", "ECSPI1_SS0"; +}; + +&i2c4 { + clock-frequency = <400000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c4>; +}; + +/* PCIe */ +&pcie0 { + assigned-clocks = <&clk IMX8MM_CLK_PCIE1_AUX>, + <&clk IMX8MM_CLK_PCIE1_CTRL>; + assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_50M>, + <&clk IMX8MM_SYS_PLL2_250M>; + assigned-clock-rates = <10000000>, <250000000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pcie>; + reset-gpio = <&gpio4 9 GPIO_ACTIVE_LOW>; + status = "okay"; +}; + +&pcie_phy { + clocks = <&clk IMX8MM_CLK_PCIE1_PHY>; + fsl,clkreq-unsupported; + fsl,refclk-pad-mode = ; + fsl,tx-deemph-gen1 = <0x2d>; + fsl,tx-deemph-gen2 = <0xf>; + status = "okay"; +}; + +&rv3028 { + trickle-resistor-ohms = <3000>; +}; + +&snvs_pwrkey { + status = "okay"; +}; + +/* UART - RS232/RS485 */ +&uart1 { + assigned-clocks = <&clk IMX8MM_CLK_UART1>; + assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_80M>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + uart-has-rtscts; + status = "okay"; +}; + +/* UART - Sterling-LWB Bluetooth */ +&uart2 { + assigned-clocks = <&clk IMX8MM_CLK_UART2>; + assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_80M>; + fsl,dte-mode; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2_bt>; + uart-has-rtscts; + status = "okay"; + + bluetooth { + compatible = "brcm,bcm43438-bt"; + clocks = <&bt_osc_32k>; + clock-names = "lpo"; + device-wakeup-gpios = <&gpio2 8 GPIO_ACTIVE_HIGH>; + interrupt-names = "host-wakeup"; + interrupt-parent = <&gpio2>; + interrupts = <9 IRQ_TYPE_EDGE_BOTH>; + max-speed = <2000000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_bt>; + shutdown-gpios = <&gpio2 6 GPIO_ACTIVE_HIGH>; + vddio-supply = <®_vcc_3v3>; + }; +}; + +/* UART - console */ +&uart3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart3>; + status = "okay"; +}; + +/* USB */ +&usbotg1 { + adp-disable; + dr_mode = "otg"; + over-current-active-low; + samsung,picophy-pre-emp-curr-control = <3>; + samsung,picophy-dc-vol-level-adjust = <7>; + srp-disable; + vbus-supply = <®_usb_otg1_vbus>; + status = "okay"; +}; + +&usbotg2 { + disable-over-current; + dr_mode = "host"; + samsung,picophy-pre-emp-curr-control = <3>; + samsung,picophy-dc-vol-level-adjust = <7>; + status = "okay"; +}; + +/* SDIO - Sterling-LWB Wifi */ +&usdhc1 { + assigned-clocks = <&clk IMX8MM_CLK_USDHC1>; + assigned-clock-rates = <200000000>; + bus-width = <4>; + mmc-pwrseq = <&usdhc1_pwrseq>; + non-removable; + no-1-8-v; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc1>, <&pinctrl_wlan>; + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + brcmf: wifi@1 { + compatible = "brcm,bcm4329-fmac"; + reg = <1>; + }; +}; + +/* SD-Card */ +&usdhc2 { + assigned-clocks = <&clk IMX8MM_CLK_USDHC2>; + assigned-clock-rates = <200000000>; + bus-width = <4>; + cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>; + disable-wp; + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; + pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>; + pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>; + vmmc-supply = <®_usdhc2_vmmc>; + vqmmc-supply = <®_nvcc_sd2>; + status = "okay"; +}; + +&iomuxc { + pinctrl_bt: btgrp { + fsl,pins = < + MX8MM_IOMUXC_SD1_DATA4_GPIO2_IO6 0x00 + MX8MM_IOMUXC_SD1_DATA6_GPIO2_IO8 0x00 + MX8MM_IOMUXC_SD1_DATA7_GPIO2_IO9 0x00 + >; + }; + + pinctrl_can_en: can-engrp { + fsl,pins = < + MX8MM_IOMUXC_GPIO1_IO09_GPIO1_IO9 0x00 + >; + }; + + pinctrl_can_int: can-intgrp { + fsl,pins = < + MX8MM_IOMUXC_GPIO1_IO08_GPIO1_IO8 0x00 + >; + }; + + pinctrl_ecspi1: ecspi1grp { + fsl,pins = < + MX8MM_IOMUXC_ECSPI1_MISO_ECSPI1_MISO 0x80 + MX8MM_IOMUXC_ECSPI1_MOSI_ECSPI1_MOSI 0x80 + MX8MM_IOMUXC_ECSPI1_SCLK_ECSPI1_SCLK 0x80 + MX8MM_IOMUXC_ECSPI1_SS0_GPIO5_IO9 0x00 + >; + }; + + pinctrl_fan: fan0grp { + fsl,pins = < + MX8MM_IOMUXC_SAI1_RXD6_GPIO4_IO8 0x16 + >; + }; + + pinctrl_i2c4: i2c4grp { + fsl,pins = < + MX8MM_IOMUXC_I2C4_SCL_I2C4_SCL 0x400001c2 + MX8MM_IOMUXC_I2C4_SDA_I2C4_SDA 0x400001c2 + >; + }; + + pinctrl_leds: leds1grp { + fsl,pins = < + MX8MM_IOMUXC_GPIO1_IO01_GPIO1_IO1 0x16 + MX8MM_IOMUXC_GPIO1_IO14_GPIO1_IO14 0x16 + MX8MM_IOMUXC_GPIO1_IO15_GPIO1_IO15 0x16 + >; + }; + + pinctrl_pcie: pciegrp { + fsl,pins = < + MX8MM_IOMUXC_SAI1_RXD7_GPIO4_IO9 0x00 + MX8MM_IOMUXC_SAI1_TXD0_GPIO4_IO12 0x12 + MX8MM_IOMUXC_SAI1_TXD7_GPIO4_IO19 0x12 + >; + }; + + pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp { + fsl,pins = < + MX8MM_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x40 + >; + }; + + pinctrl_uart1: uart1grp { + fsl,pins = < + MX8MM_IOMUXC_SAI2_RXC_UART1_DCE_RX 0x00 + MX8MM_IOMUXC_SAI2_RXD0_UART1_DCE_RTS_B 0x00 + MX8MM_IOMUXC_SAI2_RXFS_UART1_DCE_TX 0x00 + MX8MM_IOMUXC_SAI2_TXFS_UART1_DCE_CTS_B 0x00 + >; + }; + + pinctrl_uart2_bt: uart2btgrp { + fsl,pins = < + MX8MM_IOMUXC_SAI3_RXC_UART2_DTE_RTS_B 0x00 + MX8MM_IOMUXC_SAI3_RXD_UART2_DTE_CTS_B 0x00 + MX8MM_IOMUXC_SAI3_TXC_UART2_DTE_RX 0x00 + MX8MM_IOMUXC_SAI3_TXFS_UART2_DTE_TX 0x00 + >; + }; + + pinctrl_uart3: uart3grp { + fsl,pins = < + MX8MM_IOMUXC_UART3_RXD_UART3_DCE_RX 0x40 + MX8MM_IOMUXC_UART3_TXD_UART3_DCE_TX 0x40 + >; + }; + + pinctrl_usbotg1pwrgrp: usbotg1pwrgrp { + fsl,pins = < + MX8MM_IOMUXC_GPIO1_IO12_GPIO1_IO12 0x00 + >; + }; + + pinctrl_usdhc1: usdhc1grp { + fsl,pins = < + MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x182 + MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0xc6 + MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xc6 + MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xc6 + MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xc6 + MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xc6 + >; + }; + + pinctrl_usdhc2_gpio: usdhc2gpiogrp { + fsl,pins = < + MX8MM_IOMUXC_SD2_CD_B_GPIO2_IO12 0x40 + >; + }; + + pinctrl_usdhc2: usdhc2grp { + fsl,pins = < + MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0 + MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x192 + MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d2 + MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d2 + MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d2 + MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d2 + MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d2 + >; + }; + + pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp { + fsl,pins = < + MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0 + MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x194 + MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d4 + MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d4 + MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d4 + MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d4 + MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d4 + >; + }; + + pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp { + fsl,pins = < + MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0 + MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x196 + MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d6 + MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d6 + MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d6 + MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d6 + MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d6 + >; + }; + + pinctrl_wlan: wlangrp { + fsl,pins = < + MX8MM_IOMUXC_SD1_DATA5_GPIO2_IO7 0x00 + >; + }; +}; diff --git a/arch/arm/dts/imx8mm-phycore-som.dtsi b/arch/arm/dts/imx8mm-phycore-som.dtsi new file mode 100644 index 00000000000..92616bc4f71 --- /dev/null +++ b/arch/arm/dts/imx8mm-phycore-som.dtsi @@ -0,0 +1,440 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2022 PHYTEC Messtechnik GmbH + * Author: Teresa Remmet + */ + +#include "imx8mm.dtsi" +#include + +/ { + model = "PHYTEC phyCORE-i.MX8MM"; + compatible = "phytec,imx8mm-phycore-som", "fsl,imx8mm"; + + aliases { + rtc0 = &rv3028; + rtc1 = &snvs_rtc; + }; + + memory@40000000 { + device_type = "memory"; + reg = <0x0 0x40000000 0 0x80000000>; + }; + + reg_vdd_3v3_s: regulator-vdd-3v3-s { + compatible = "regulator-fixed"; + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <3300000>; + regulator-min-microvolt = <3300000>; + regulator-name = "VDD_3V3_S"; + }; +}; + +&A53_0 { + cpu-supply = <®_vdd_arm>; +}; + +&A53_1 { + cpu-supply = <®_vdd_arm>; +}; + +&A53_2 { + cpu-supply = <®_vdd_arm>; +}; + +&A53_3 { + cpu-supply = <®_vdd_arm>; +}; + +&ddrc { + operating-points-v2 = <&ddrc_opp_table>; + + ddrc_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-25000000 { + opp-hz = /bits/ 64 <25000000>; + }; + + opp-100000000 { + opp-hz = /bits/ 64 <100000000>; + }; + + opp-750000000 { + opp-hz = /bits/ 64 <750000000>; + }; + }; +}; + +/* Ethernet */ +&fec1 { + fsl,magic-packet; + phy-mode = "rgmii-id"; + phy-handle = <ðphy0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_fec1>; + status = "okay"; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + ethphy0: ethernet-phy@0 { + compatible = "ethernet-phy-ieee802.3-c22"; + enet-phy-lane-no-swap; + ti,clk-output-sel = ; + ti,fifo-depth = ; + ti,rx-internal-delay = ; + ti,tx-internal-delay = ; + reg = <0>; + reset-gpios = <&gpio1 7 GPIO_ACTIVE_HIGH>; + reset-assert-us = <1000>; + reset-deassert-us = <1000>; + }; + }; +}; + +/* SPI Flash */ +&flexspi { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexspi0>; + status = "okay"; + + som_flash: flash@0 { + compatible = "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <80000000>; + spi-rx-bus-width = <4>; + spi-tx-bus-width = <1>; + }; +}; + +&gpio1 { + gpio-line-names = "nINT_ETHPHY", "", "WDOG_INT", "X_RTC_INT", + "", "", "", "RESET_ETHPHY", + "", "", "nENABLE_FLATLINK"; +}; + +/* I2C1 */ +&i2c1 { + clock-frequency = <400000>; + pinctrl-names = "default","gpio"; + pinctrl-0 = <&pinctrl_i2c1>; + pinctrl-1 = <&pinctrl_i2c1_gpio>; + scl-gpios = <&gpio5 14 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio5 15 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + status = "okay"; + + pmic@8 { + compatible = "nxp,pf8121a"; + reg = <0x08>; + + regulators { + reg_nvcc_sd1: ldo1 { + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <3300000>; + regulator-min-microvolt = <3300000>; + regulator-name = "NVCC_SD1 (LDO1)"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + reg_nvcc_sd2: ldo2 { + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <3300000>; + regulator-min-microvolt = <1800000>; + regulator-name = "NVCC_SD2 (LDO2)"; + vselect-en; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + reg_vcc_enet: ldo3 { + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <2500000>; + regulator-min-microvolt = <1500000>; + regulator-name = "VCC_ENET_2V5 (LDO3)"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + reg_vdda_1v8: ldo4 { + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <1800000>; + regulator-min-microvolt = <1500000>; + regulator-name = "VDDA_1V8 (LDO4)"; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-min-microvolt = <1500000>; + regulator-suspend-max-microvolt = <1500000>; + }; + }; + + reg_soc_vdda_phy: buck1 { + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <900000>; + regulator-min-microvolt = <400000>; + regulator-name = "VDD_SOC_VDDA_PHY_0P8 (BUCK1)"; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-min-microvolt = <400000>; + regulator-suspend-max-microvolt = <400000>; + }; + }; + + reg_vdd_gpu_dram: buck2 { + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <1000000>; + regulator-min-microvolt = <1000000>; + regulator-name = "VDD_GPU_DRAM (BUCK2)"; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-max-microvolt = <1000000>; + regulator-suspend-min-microvolt = <1000000>; + }; + }; + + reg_vdd_gpu: buck3 { + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <1000000>; + regulator-min-microvolt = <400000>; + regulator-name = "VDD_VPU (BUCK3)"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + reg_vdd_mipi: buck4 { + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <1050000>; + regulator-min-microvolt = <900000>; + regulator-name = "VDD_MIPI_0P9 (BUCK4)"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + reg_vdd_arm: buck5 { + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <1050000>; + regulator-min-microvolt = <400000>; + regulator-name = "VDD_ARM (BUCK5)"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + reg_vdd_1v8: buck6 { + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <1800000>; + regulator-min-microvolt = <1800000>; + regulator-name = "VDD_1V8 (BUCK6)"; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-max-microvolt = <1800000>; + regulator-suspend-min-microvolt = <1800000>; + }; + }; + + reg_nvcc_dram: buck7 { + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <1100000>; + regulator-min-microvolt = <1100000>; + regulator-name = "NVCC_DRAM_1P1V (BUCK7)"; + }; + + reg_vsnvs: vsnvs { + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <1800000>; + regulator-min-microvolt = <1800000>; + regulator-name = "NVCC_SNVS_1P8 (VSNVS)"; + }; + }; + }; + + sn65dsi83: bridge@2d { + compatible = "ti,sn65dsi83"; + enable-gpios = <&gpio1 10 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sn65dsi83>; + reg = <0x2d>; + status = "disabled"; + }; + + eeprom@51 { + compatible = "atmel,24c32"; + pagesize = <32>; + reg = <0x51>; + vcc-supply = <®_vdd_3v3_s>; + }; + + rv3028: rtc@52 { + compatible = "microcrystal,rv3028"; + interrupts = <3 IRQ_TYPE_LEVEL_LOW>; + interrupt-parent = <&gpio1>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_rtc>; + reg = <0x52>; + }; +}; + +/* EMMC */ +&usdhc3 { + assigned-clocks = <&clk IMX8MM_CLK_USDHC3_ROOT>; + assigned-clock-rates = <400000000>; + bus-width = <8>; + keep-power-in-suspend; + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc3>; + pinctrl-1 = <&pinctrl_usdhc3_100mhz>; + pinctrl-2 = <&pinctrl_usdhc3_200mhz>; + non-removable; + status = "okay"; +}; + +/* Watchdog */ +&wdog1 { + fsl,ext-reset-output; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_wdog>; + status = "okay"; +}; + +&iomuxc { + pinctrl_fec1: fec1grp { + fsl,pins = < + MX8MM_IOMUXC_ENET_MDC_ENET1_MDC 0x2 + MX8MM_IOMUXC_ENET_MDIO_ENET1_MDIO 0x2 + MX8MM_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x90 + MX8MM_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x90 + MX8MM_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x90 + MX8MM_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x90 + MX8MM_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x90 + MX8MM_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x90 + MX8MM_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x16 + MX8MM_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x16 + MX8MM_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x16 + MX8MM_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x16 + MX8MM_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x16 + MX8MM_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x16 + MX8MM_IOMUXC_GPIO1_IO07_GPIO1_IO7 0x10 + >; + }; + + pinctrl_flexspi0: flexspi0grp { + fsl,pins = < + MX8MM_IOMUXC_NAND_ALE_QSPI_A_SCLK 0x1c2 + MX8MM_IOMUXC_NAND_CE0_B_QSPI_A_SS0_B 0x82 + MX8MM_IOMUXC_NAND_DATA00_QSPI_A_DATA0 0x82 + MX8MM_IOMUXC_NAND_DATA01_QSPI_A_DATA1 0x82 + MX8MM_IOMUXC_NAND_DATA02_QSPI_A_DATA2 0x82 + MX8MM_IOMUXC_NAND_DATA03_QSPI_A_DATA3 0x82 + >; + }; + + pinctrl_i2c1: i2c1grp { + fsl,pins = < + MX8MM_IOMUXC_I2C1_SDA_I2C1_SDA 0x400001c0 + MX8MM_IOMUXC_I2C1_SCL_I2C1_SCL 0x400001c0 + >; + }; + + pinctrl_i2c1_gpio: i2c1gpiogrp { + fsl,pins = < + MX8MM_IOMUXC_I2C1_SDA_GPIO5_IO15 0x1e0 + MX8MM_IOMUXC_I2C1_SCL_GPIO5_IO14 0x1e0 + >; + }; + + pinctrl_rtc: rtcgrp { + fsl,pins = < + MX8MM_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x1c0 + >; + }; + + pinctrl_sn65dsi83: sn65dsi83grp { + fsl,pins = < + MX8MM_IOMUXC_GPIO1_IO10_GPIO1_IO10 0x0 + >; + }; + + pinctrl_usdhc3: usdhc3grp { + fsl,pins = < + MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d0 + MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x190 + MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d0 + MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d0 + MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d0 + MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d0 + MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d0 + MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d0 + MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d0 + MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x190 + MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d0 + >; + }; + + pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp { + fsl,pins = < + MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d4 + MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x194 + MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d4 + MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d4 + MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d4 + MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d4 + MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d4 + MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d4 + MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d4 + MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x194 + MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d4 + >; + }; + + pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp { + fsl,pins = < + MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d6 + MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x196 + MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d6 + MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d6 + MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d6 + MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d6 + MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d6 + MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d6 + MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d6 + MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x196 + MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d6 + >; + }; + + pinctrl_wdog: wdoggrp { + fsl,pins = < + MX8MM_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0x26 + >; + }; +}; diff --git a/arch/arm/dts/phycore-imx8mm-u-boot.dtsi b/arch/arm/dts/phycore-imx8mm-u-boot.dtsi deleted file mode 100644 index 516e52e1f5d..00000000000 --- a/arch/arm/dts/phycore-imx8mm-u-boot.dtsi +++ /dev/null @@ -1,71 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -/* - * Copyright (C) 2020 PHYTEC Messtechnik GmbH - * Author: Teresa Remmet - */ - -#include "imx8mm-u-boot.dtsi" - -/ { - wdt-reboot { - compatible = "wdt-reboot"; - wdt = <&wdog1>; - bootph-pre-ram; - }; -}; - -&pinctrl_uart3 { - bootph-pre-ram; -}; - -&pinctrl_usdhc2_gpio { - bootph-pre-ram; -}; - -&pinctrl_usdhc2 { - bootph-pre-ram; -}; - -&pinctrl_usdhc3 { - bootph-pre-ram; -}; - -&pinctrl_wdog { - bootph-pre-ram; -}; - -&gpio1 { - bootph-pre-ram; -}; - -&gpio2 { - bootph-pre-ram; -}; - -&gpio3 { - bootph-pre-ram; -}; - -&gpio4 { - bootph-pre-ram; -}; - -&gpio5 { - bootph-pre-ram; -}; - -&uart3 { - bootph-pre-ram; -}; - -&usdhc2 { - bootph-pre-ram; -}; - -&usdhc3 { - bootph-pre-ram; -}; - -&wdog1 { - bootph-pre-ram; -}; diff --git a/arch/arm/dts/phycore-imx8mm.dts b/arch/arm/dts/phycore-imx8mm.dts deleted file mode 100644 index e57dfd368d6..00000000000 --- a/arch/arm/dts/phycore-imx8mm.dts +++ /dev/null @@ -1,287 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -/* - * Copyright (C) 2019-2020 PHYTEC Messtechnik GmbH - * Author: Teresa Remmet - */ - -/dts-v1/; - -#include -#include "imx8mm.dtsi" - -/ { - model = "PHYTEC phyCORE-i.MX8MM"; - compatible = "phytec,imx8mm-phycore-som", "fsl,imx8mm"; - - chosen { - stdout-path = &uart3; - }; - - reg_usdhc2_vmmc: regulator-usdhc2 { - compatible = "regulator-fixed"; - regulator-name = "VSD_3V3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - startup-delay-us = <100>; - off-on-delay-us = <12000>; - }; -}; - -/* ethernet */ -&fec1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_fec1>; - phy-mode = "rgmii-id"; - phy-handle = <ðphy0>; - phy-reset-gpios = <&gpio1 7 GPIO_ACTIVE_HIGH>; - phy-reset-duration = <1>; - phy-reset-post-delay = <1>; - status = "okay"; - - mdio { - #address-cells = <1>; - #size-cells = <0>; - - ethphy0: ethernet-phy@0 { - compatible = "ethernet-phy-ieee802.3-c22"; - reg = <0x0>; - ti,rx-internal-delay = ; - ti,tx-internal-delay = ; - ti,fifo-depth = ; - ti,clk-output-sel = ; - enet-phy-lane-no-swap; - }; - }; -}; - -/* SPI nor flash */ -&flexspi { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_flexspi0>; - status = "okay"; - - flash0: norflash@0 { - reg = <0>; - #address-cells = <1>; - #size-cells = <1>; - compatible = "jedec,spi-nor"; - spi-max-frequency = <80000000>; - spi-tx-bus-width = <4>; - spi-rx-bus-width = <4>; - }; -}; - -/* i2c eeprom */ -&i2c1 { - clock-frequency = <400000>; - pinctrl-names = "default", "gpio"; - pinctrl-0 = <&pinctrl_i2c1>; - pinctrl-1 = <&pinctrl_i2c1_gpio>; - scl-gpios = <&gpio5 14 GPIO_ACTIVE_HIGH>; - sda-gpios = <&gpio5 15 GPIO_ACTIVE_HIGH>; - status = "okay"; - - /* M24C32-D */ - i2c_eeprom: eeprom@51 { - compatible = "atmel,24c32"; - reg = <0x51>; - u-boot,i2c-offset-len = <2>; - }; - - /* M24C32-D Identification page */ - i2c_eeprom_id: eeprom@59 { - compatible = "atmel,24c32"; - reg = <0x59>; - u-boot,i2c-offset-len = <2>; - }; -}; - -/* debug console */ -&uart3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart3>; - status = "okay"; -}; - -/* sd-card */ -&usdhc2 { - pinctrl-names = "default", "state_100mhz", "state_200mhz"; - pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; - pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>; - pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>; - cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>; - bus-width = <4>; - vmmc-supply = <®_usdhc2_vmmc>; - status = "okay"; -}; - -/* eMMC */ -&usdhc3 { - pinctrl-names = "default", "state_100mhz", "state_200mhz"; - pinctrl-0 = <&pinctrl_usdhc3>; - pinctrl-1 = <&pinctrl_usdhc3_100mhz>; - pinctrl-2 = <&pinctrl_usdhc3_200mhz>; - bus-width = <8>; - non-removable; - status = "okay"; -}; - -/* watchdog */ -&wdog1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_wdog>; - fsl,ext-reset-output; - status = "okay"; -}; - -&iomuxc { - pinctrl-names = "default"; - - pinctrl_fec1: fec1grp { - fsl,pins = < - MX8MM_IOMUXC_ENET_MDC_ENET1_MDC 0x3 - MX8MM_IOMUXC_ENET_MDIO_ENET1_MDIO 0x3 - MX8MM_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f - MX8MM_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f - MX8MM_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f - MX8MM_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f - MX8MM_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91 - MX8MM_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91 - MX8MM_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91 - MX8MM_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91 - MX8MM_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f - MX8MM_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91 - MX8MM_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91 - MX8MM_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f - MX8MM_IOMUXC_GPIO1_IO07_GPIO1_IO7 0x19 - >; - }; - - pinctrl_flexspi0: flexspi0grp { - fsl,pins = < - MX8MM_IOMUXC_NAND_ALE_QSPI_A_SCLK 0x1c2 - MX8MM_IOMUXC_NAND_CE0_B_QSPI_A_SS0_B 0x82 - MX8MM_IOMUXC_NAND_DATA00_QSPI_A_DATA0 0x82 - MX8MM_IOMUXC_NAND_DATA01_QSPI_A_DATA1 0x82 - MX8MM_IOMUXC_NAND_DATA02_QSPI_A_DATA2 0x82 - MX8MM_IOMUXC_NAND_DATA03_QSPI_A_DATA3 0x82 - >; - }; - - pinctrl_i2c1: i2c1grp { - fsl,pins = < - MX8MM_IOMUXC_I2C1_SCL_I2C1_SCL 0x400001c3 - MX8MM_IOMUXC_I2C1_SDA_I2C1_SDA 0x400001c3 - >; - }; - - pinctrl_i2c1_gpio: i2c1grp-gpio { - fsl,pins = < - MX8MM_IOMUXC_I2C1_SCL_GPIO5_IO14 0x1c3 - MX8MM_IOMUXC_I2C1_SDA_GPIO5_IO15 0x1c3 - >; - }; - - pinctrl_uart3: uart3grp { - fsl,pins = < - MX8MM_IOMUXC_UART3_RXD_UART3_DCE_RX 0x49 - MX8MM_IOMUXC_UART3_TXD_UART3_DCE_TX 0x49 - >; - }; - - pinctrl_usdhc2_gpio: usdhc2grpgpio { - fsl,pins = < - MX8MM_IOMUXC_SD2_CD_B_GPIO2_IO12 0x41 - >; - }; - - pinctrl_usdhc2: usdhc2grp { - fsl,pins = < - MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x190 - MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d0 - MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d0 - MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d0 - MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d0 - MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d0 - MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0 - >; - }; - - pinctrl_usdhc2_100mhz: usdhc2grp100mhz { - fsl,pins = < - MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x194 - MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d4 - MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d4 - MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d4 - MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d4 - MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d4 - MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0 - >; - }; - - pinctrl_usdhc2_200mhz: usdhc2grp200mhz { - fsl,pins = < - MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x196 - MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d6 - MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d6 - MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d6 - MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d6 - MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d6 - MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0 - >; - }; - - pinctrl_usdhc3: usdhc3grp { - fsl,pins = < - MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x40000190 - MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d0 - MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d0 - MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d0 - MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d0 - MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d0 - MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d0 - MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d0 - MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d0 - MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d0 - MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x190 - >; - }; - - pinctrl_usdhc3_100mhz: usdhc3grp100mhz { - fsl,pins = < - MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x40000194 - MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d4 - MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d4 - MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d4 - MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d4 - MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d4 - MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d4 - MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d4 - MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d4 - MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d4 - MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x194 - >; - }; - - pinctrl_usdhc3_200mhz: usdhc3grp200mhz { - fsl,pins = < - MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x40000196 - MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d6 - MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d6 - MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d6 - MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d6 - MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d6 - MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d6 - MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d6 - MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d6 - MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d6 - MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x196 - >; - }; - - pinctrl_wdog: wdoggrp { - fsl,pins = < - MX8MM_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0xc6 - >; - }; -}; diff --git a/board/phytec/phycore_imx8mm/MAINTAINERS b/board/phytec/phycore_imx8mm/MAINTAINERS index 9edec7b7d28..acffda61c04 100644 --- a/board/phytec/phycore_imx8mm/MAINTAINERS +++ b/board/phytec/phycore_imx8mm/MAINTAINERS @@ -2,8 +2,9 @@ phyCORE-i.MX8M Mini M: Teresa Remmet W: https://www.phytec.eu/product-eu/system-on-modules/phycore-imx-8m-mini-nano/ S: Maintained -F: arch/arm/dts/phycore-imx8mm.dts -F: arch/arm/dts/phycore-imx8mm-u-boot.dtsi +F: arch/arm/dts/imx8mm-phyboard-polis-rdk.dts +F: arch/arm/dts/imx8mm-phycore-som.dtsi +F: arch/arm/dts/imx8mm-phyboard-polis-rdk-u-boot.dtsi F: board/phytec/phycore_imx8mm/ F: configs/phycore-imx8mm_defconfig F: include/configs/phycore_imx8mm.h diff --git a/configs/phycore-imx8mm_defconfig b/configs/phycore-imx8mm_defconfig index bff35e739c4..3ac250270d1 100644 --- a/configs/phycore-imx8mm_defconfig +++ b/configs/phycore-imx8mm_defconfig @@ -9,7 +9,7 @@ CONFIG_SF_DEFAULT_SPEED=80000000 CONFIG_ENV_SIZE=0x10000 CONFIG_ENV_OFFSET=0x3C0000 CONFIG_DM_GPIO=y -CONFIG_DEFAULT_DEVICE_TREE="phycore-imx8mm" +CONFIG_DEFAULT_DEVICE_TREE="imx8mm-phyboard-polis-rdk" CONFIG_SPL_TEXT_BASE=0x7E1000 CONFIG_TARGET_PHYCORE_IMX8MM=y CONFIG_SYS_MONITOR_LEN=524288 -- cgit v1.3.1 From 452e385b081f91f37456f2203b29d721ac7bae44 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Sat, 29 Jul 2023 15:29:41 +0200 Subject: arm: mxs: Fix ICOLL macro name typo The interrupt collector macro name for i.MX23 is MXS_ICOLL_BASE, this is correct and matches the documentation of both i.MX23 and i.MX28. Align the i.MX28 macro accordingly. No functional change. Signed-off-by: Marek Vasut Reviewed-by: Lukasz Majewski --- arch/arm/include/asm/arch-mxs/regs-base.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/include/asm/arch-mxs/regs-base.h b/arch/arm/include/asm/arch-mxs/regs-base.h index 44d40cade87..33d2ab5230f 100644 --- a/arch/arm/include/asm/arch-mxs/regs-base.h +++ b/arch/arm/include/asm/arch-mxs/regs-base.h @@ -60,7 +60,7 @@ * Register base addresses for i.MX28 */ #elif defined(CONFIG_MX28) -#define MXS_ICOL_BASE 0x80000000 +#define MXS_ICOLL_BASE 0x80000000 #define MXS_HSADC_BASE 0x80002000 #define MXS_APBH_BASE 0x80004000 #define MXS_PERFMON_BASE 0x80006000 -- cgit v1.3.1 From 9e9d92f823732ef3f765586770e7c2cd2cfe6709 Mon Sep 17 00:00:00 2001 From: Igor Opaniuk Date: Mon, 21 Aug 2023 22:33:41 +0300 Subject: imx: imx8: ahab: refactor do_ahab_close command Move an OEM closing logic to ahab_close() function to be able to use it directly without calling a u-boot command. Signed-off-by: Igor Opaniuk Co-developed-by: Oleksandr Suvorov Signed-off-by: Oleksandr Suvorov --- arch/arm/include/asm/arch-imx8/sys_proto.h | 1 + arch/arm/mach-imx/imx8/ahab.c | 45 +++++++++++++++++++----------- 2 files changed, 30 insertions(+), 16 deletions(-) diff --git a/arch/arm/include/asm/arch-imx8/sys_proto.h b/arch/arm/include/asm/arch-imx8/sys_proto.h index e7625c42985..405e9bd3d81 100644 --- a/arch/arm/include/asm/arch-imx8/sys_proto.h +++ b/arch/arm/include/asm/arch-imx8/sys_proto.h @@ -23,6 +23,7 @@ struct pass_over_info_t { extern unsigned long boot_pointer[]; void build_info(void); +int ahab_close(void); int print_bootinfo(void); int sc_pm_setup_uart(sc_rsrc_t uart_rsrc, sc_pm_clock_rate_t clk_rate); int imx8_power_domain_lookup_name(const char *name, diff --git a/arch/arm/mach-imx/imx8/ahab.c b/arch/arm/mach-imx/imx8/ahab.c index 994becccefd..1c072f6af11 100644 --- a/arch/arm/mach-imx/imx8/ahab.c +++ b/arch/arm/mach-imx/imx8/ahab.c @@ -340,6 +340,32 @@ static int do_ahab_status(struct cmd_tbl *cmdtp, int flag, int argc, return 0; } +int ahab_close(void) +{ + int err; + u16 lc; + + err = sc_seco_chip_info(-1, &lc, NULL, NULL, NULL); + if (err != SC_ERR_NONE) { + printf("Error in get lifecycle\n"); + return -EIO; + } + + if (lc != 0x20) { + puts("Current lifecycle is NOT NXP closed, can't move to OEM closed\n"); + display_life_cycle(lc); + return -EPERM; + } + + err = sc_seco_forward_lifecycle(-1, 16); + if (err != SC_ERR_NONE) { + printf("Error in forward lifecycle to OEM closed\n"); + return -EIO; + } + + return 0; +} + static int confirm_close(void) { puts("Warning: Please ensure your sample is in NXP closed state, " @@ -361,27 +387,14 @@ static int do_ahab_close(struct cmd_tbl *cmdtp, int flag, int argc, { int confirmed = argc >= 2 && !strcmp(argv[1], "-y"); int err; - u16 lc; if (!confirmed && !confirm_close()) return -EACCES; - err = sc_seco_chip_info(-1, &lc, NULL, NULL, NULL); + err = ahab_close(); if (err) { - printf("Error in get lifecycle\n"); - return -EIO; - } - - if (lc != 0x20) { - puts("Current lifecycle is NOT NXP closed, can't move to OEM closed\n"); - display_life_cycle(lc); - return -EPERM; - } - - err = sc_seco_forward_lifecycle(-1, 16); - if (err) { - printf("Error in forward lifecycle to OEM closed\n"); - return -EIO; + printf("Change to OEM closed failed\n"); + return err; } printf("Change to OEM closed successfully\n"); -- cgit v1.3.1 From 85053a1c14cb2c132dc80ac1dae8203d121b0932 Mon Sep 17 00:00:00 2001 From: Ricardo Salveti Date: Fri, 25 Aug 2023 17:44:14 +0300 Subject: ARM: imx8ulp: support env in fat and ext4 Change boot device logic to also allow environment stored in fat and in ext4 when booting from SD or eMMC. As the boot device check for SD and for eMMC was depending on ENV_IS_IN_MMC being defined, change the ifdef blocks at env_get_location to use IS_ENABLED instead for all modes, returning NOWHERE when no valid mode is found. Signed-off-by: Ricardo Salveti Co-developed-by: Oleksandr Suvorov Signed-off-by: Oleksandr Suvorov --- arch/arm/mach-imx/imx8ulp/soc.c | 28 ++++++++++++---------------- 1 file changed, 12 insertions(+), 16 deletions(-) diff --git a/arch/arm/mach-imx/imx8ulp/soc.c b/arch/arm/mach-imx/imx8ulp/soc.c index fd436dd8851..c3722c60836 100644 --- a/arch/arm/mach-imx/imx8ulp/soc.c +++ b/arch/arm/mach-imx/imx8ulp/soc.c @@ -865,33 +865,29 @@ u32 spl_arch_boot_image_offset(u32 image_offset, u32 rom_bt_dev) enum env_location env_get_location(enum env_operation op, int prio) { enum boot_device dev = get_boot_device(); - enum env_location env_loc = ENVL_UNKNOWN; if (prio) - return env_loc; + return ENVL_UNKNOWN; switch (dev) { -#ifdef CONFIG_ENV_IS_IN_SPI_FLASH case QSPI_BOOT: - env_loc = ENVL_SPI_FLASH; - break; -#endif -#ifdef CONFIG_ENV_IS_IN_MMC + if (CONFIG_IS_ENABLED(ENV_IS_IN_SPI_FLASH)) + return ENVL_SPI_FLASH; + return ENVL_NOWHERE; case SD1_BOOT: case SD2_BOOT: case SD3_BOOT: case MMC1_BOOT: case MMC2_BOOT: case MMC3_BOOT: - env_loc = ENVL_MMC; - break; -#endif + if (CONFIG_IS_ENABLED(ENV_IS_IN_MMC)) + return ENVL_MMC; + else if (CONFIG_IS_ENABLED(ENV_IS_IN_EXT4)) + return ENVL_EXT4; + else if (CONFIG_IS_ENABLED(ENV_IS_IN_FAT)) + return ENVL_FAT; + return ENVL_NOWHERE; default: -#if defined(CONFIG_ENV_IS_NOWHERE) - env_loc = ENVL_NOWHERE; -#endif - break; + return ENVL_NOWHERE; } - - return env_loc; } -- cgit v1.3.1 From 9e1f79bd694b277bff44578b8bfc597e29e5350a Mon Sep 17 00:00:00 2001 From: Sébastien Szymanski Date: Tue, 17 Oct 2023 11:44:58 +0200 Subject: net: dwc_eth_qos: add i.MX93 support MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Add support for DWC EQoS MAC on i.MX93. Signed-off-by: Sébastien Szymanski Reviewed-by: Fabio Estevam --- drivers/net/dwc_eth_qos.c | 4 ++++ drivers/net/dwc_eth_qos_imx.c | 3 +++ 2 files changed, 7 insertions(+) diff --git a/drivers/net/dwc_eth_qos.c b/drivers/net/dwc_eth_qos.c index a4e3698c600..e40e399c802 100644 --- a/drivers/net/dwc_eth_qos.c +++ b/drivers/net/dwc_eth_qos.c @@ -1711,6 +1711,10 @@ static const struct udevice_id eqos_ids[] = { .compatible = "nxp,imx8mp-dwmac-eqos", .data = (ulong)&eqos_imx_config }, + { + .compatible = "nxp,imx93-dwmac-eqos", + .data = (ulong)&eqos_imx_config + }, #endif #if IS_ENABLED(CONFIG_DWC_ETH_QOS_ROCKCHIP) { diff --git a/drivers/net/dwc_eth_qos_imx.c b/drivers/net/dwc_eth_qos_imx.c index 60f3f3f5a10..e3f55dd9817 100644 --- a/drivers/net/dwc_eth_qos_imx.c +++ b/drivers/net/dwc_eth_qos_imx.c @@ -181,6 +181,9 @@ static int eqos_set_tx_clk_speed_imx(struct udevice *dev) ulong rate; int ret; + if (device_is_compatible(dev, "nxp,imx93-dwmac-eqos")) + return 0; + debug("%s(dev=%p):\n", __func__, dev); if (eqos->phy->interface == PHY_INTERFACE_MODE_RMII) -- cgit v1.3.1 From d5eae216d833c8043d62e86c893bb492c56802f1 Mon Sep 17 00:00:00 2001 From: Sébastien Szymanski Date: Tue, 17 Oct 2023 11:44:59 +0200 Subject: net: dwc_eth_qos: Add board_interface_eth_init() for i.MX93 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Add a common board_interface_eth_init() called by the DWC MAC driver to setup the MAC <-> PHY interface according to the PHY mode obtained from DT. Remove the board-side configuration in the i.MX93 EVK files. Signed-off-by: Sébastien Szymanski --- arch/arm/mach-imx/imx9/clock.c | 53 +++++++++++++++++++++++++++++++++++ board/freescale/imx93_evk/imx93_evk.c | 16 ----------- 2 files changed, 53 insertions(+), 16 deletions(-) diff --git a/arch/arm/mach-imx/imx9/clock.c b/arch/arm/mach-imx/imx9/clock.c index 766a8811c1f..92c41e9a67b 100644 --- a/arch/arm/mach-imx/imx9/clock.c +++ b/arch/arm/mach-imx/imx9/clock.c @@ -18,6 +18,7 @@ #include #include #include +#include DECLARE_GLOBAL_DATA_PTR; @@ -832,6 +833,58 @@ u32 imx_get_fecclk(void) return ccm_clk_root_get_rate(WAKEUP_AXI_CLK_ROOT); } +#if defined(CONFIG_IMX93) && defined(CONFIG_DWC_ETH_QOS) +static int imx93_eqos_interface_init(struct udevice *dev, phy_interface_t interface_type) +{ + struct blk_ctrl_wakeupmix_regs *bctrl = + (struct blk_ctrl_wakeupmix_regs *)BLK_CTRL_WAKEUPMIX_BASE_ADDR; + + clrbits_le32(&bctrl->eqos_gpr, + BCTRL_GPR_ENET_QOS_INTF_MODE_MASK | + BCTRL_GPR_ENET_QOS_CLK_GEN_EN); + + switch (interface_type) { + case PHY_INTERFACE_MODE_MII: + setbits_le32(&bctrl->eqos_gpr, + BCTRL_GPR_ENET_QOS_INTF_SEL_MII | + BCTRL_GPR_ENET_QOS_CLK_GEN_EN); + break; + case PHY_INTERFACE_MODE_RMII: + setbits_le32(&bctrl->eqos_gpr, + BCTRL_GPR_ENET_QOS_INTF_SEL_RMII | + BCTRL_GPR_ENET_QOS_CLK_GEN_EN); + break; + case PHY_INTERFACE_MODE_RGMII: + case PHY_INTERFACE_MODE_RGMII_ID: + case PHY_INTERFACE_MODE_RGMII_RXID: + case PHY_INTERFACE_MODE_RGMII_TXID: + setbits_le32(&bctrl->eqos_gpr, + BCTRL_GPR_ENET_QOS_INTF_SEL_RGMII | + BCTRL_GPR_ENET_QOS_CLK_GEN_EN); + break; + default: + return -EINVAL; + } + + return 0; +} +#else +static int imx93_eqos_interface_init(struct udevice *dev, phy_interface_t interface_type) +{ + return 0; +} +#endif + +int board_interface_eth_init(struct udevice *dev, phy_interface_t interface_type) +{ + if (IS_ENABLED(CONFIG_IMX93) && + IS_ENABLED(CONFIG_DWC_ETH_QOS) && + device_is_compatible(dev, "nxp,imx93-dwmac-eqos")) + return imx93_eqos_interface_init(dev, interface_type); + + return -EINVAL; +} + int set_clk_enet(enum enet_freq type) { u32 div; diff --git a/board/freescale/imx93_evk/imx93_evk.c b/board/freescale/imx93_evk/imx93_evk.c index f4297f8fd4d..c54dc9d05c5 100644 --- a/board/freescale/imx93_evk/imx93_evk.c +++ b/board/freescale/imx93_evk/imx93_evk.c @@ -49,27 +49,11 @@ int board_phy_config(struct phy_device *phydev) return 0; } -static int setup_eqos(void) -{ - struct blk_ctrl_wakeupmix_regs *bctrl = - (struct blk_ctrl_wakeupmix_regs *)BLK_CTRL_WAKEUPMIX_BASE_ADDR; - - /* set INTF as RGMII, enable RGMII TXC clock */ - clrsetbits_le32(&bctrl->eqos_gpr, - BCTRL_GPR_ENET_QOS_INTF_MODE_MASK, - BCTRL_GPR_ENET_QOS_INTF_SEL_RGMII | BCTRL_GPR_ENET_QOS_CLK_GEN_EN); - - return set_clk_eqos(ENET_125MHZ); -} - int board_init(void) { if (IS_ENABLED(CONFIG_FEC_MXC)) setup_fec(); - if (IS_ENABLED(CONFIG_DWC_ETH_QOS)) - setup_eqos(); - return 0; } -- cgit v1.3.1 From f935716935438dcf2445a8e817c6b4da910ce44f Mon Sep 17 00:00:00 2001 From: Sébastien Szymanski Date: Tue, 17 Oct 2023 11:45:00 +0200 Subject: net: phy: realtek: Add support for RTL8211F(D)(I)-VD-CG MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Add support for the RTL8211F(D)(I)-VD-CG PHY present on the i.MX93 EVK board. Signed-off-by: Sébastien Szymanski --- drivers/net/phy/realtek.c | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/drivers/net/phy/realtek.c b/drivers/net/phy/realtek.c index 396cac76d63..7e1036b2271 100644 --- a/drivers/net/phy/realtek.c +++ b/drivers/net/phy/realtek.c @@ -446,6 +446,20 @@ U_BOOT_PHY_DRIVER(rtl8211f) = { .writeext = &rtl8211f_phy_extwrite, }; +/* Support for RTL8211F-VD PHY */ +U_BOOT_PHY_DRIVER(rtl8211fvd) = { + .name = "RealTek RTL8211F-VD", + .uid = 0x1cc878, + .mask = 0xffffff, + .features = PHY_GBIT_FEATURES, + .probe = &rtl8211f_probe, + .config = &rtl8211f_config, + .startup = &rtl8211f_startup, + .shutdown = &genphy_shutdown, + .readext = &rtl8211f_phy_extread, + .writeext = &rtl8211f_phy_extwrite, +}; + /* Support for RTL8201F PHY */ U_BOOT_PHY_DRIVER(rtl8201f) = { .name = "RealTek RTL8201F 10/100Mbps Ethernet", -- cgit v1.3.1 From 97af4d69d2b8fca7d5227c6bac0a9e08c8696a9e Mon Sep 17 00:00:00 2001 From: Sébastien Szymanski Date: Tue, 17 Oct 2023 11:45:01 +0200 Subject: arm: dts: imx93-evk: remove wrong eqos compatible string MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The correct compatible string for i.MX93 variant of DWC EQoS MAC is now "nxp,imx93-dwmac-eqos". Signed-off-by: Sébastien Szymanski --- arch/arm/dts/imx93-11x11-evk-u-boot.dtsi | 4 ---- 1 file changed, 4 deletions(-) diff --git a/arch/arm/dts/imx93-11x11-evk-u-boot.dtsi b/arch/arm/dts/imx93-11x11-evk-u-boot.dtsi index a9dffa5a71e..4ecb53ed8be 100644 --- a/arch/arm/dts/imx93-11x11-evk-u-boot.dtsi +++ b/arch/arm/dts/imx93-11x11-evk-u-boot.dtsi @@ -131,10 +131,6 @@ phy-reset-post-delay = <100>; }; -&eqos { - compatible = "fsl,imx-eqos"; -}; - ðphy1 { reset-gpios = <&pcal6524 15 GPIO_ACTIVE_LOW>; reset-assert-us = <15000>; -- cgit v1.3.1 From 2b9bcc2f47bae04002caca82e0a878edd77930e8 Mon Sep 17 00:00:00 2001 From: Hugo Villeneuve Date: Tue, 17 Oct 2023 10:25:00 -0400 Subject: imx8mn-var-som: add manufacturer to target description Add Variscite manufacturer to the IMX8MN_VAR_SOM target menu label as the majority of targets include the manufacturer as part of their menu description/label and it helps when looking for a particular manufacturer/board. Signed-off-by: Hugo Villeneuve Reviewed-by: Fabio Estevam --- arch/arm/mach-imx/imx8m/Kconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/mach-imx/imx8m/Kconfig b/arch/arm/mach-imx/imx8m/Kconfig index b802d5cf280..67da198956c 100644 --- a/arch/arm/mach-imx/imx8m/Kconfig +++ b/arch/arm/mach-imx/imx8m/Kconfig @@ -256,7 +256,7 @@ config TARGET_PICO_IMX8MQ select IMX8M_LPDDR4 config TARGET_IMX8MN_VAR_SOM - bool "imx8mn_var_som" + bool "Variscite imx8mn_var_som" select BINMAN select IMX8MN select SUPPORT_SPL -- cgit v1.3.1 From bb1e22ca5399c76471f0dc9295135bad3d36c0ba Mon Sep 17 00:00:00 2001 From: Tim Harvey Date: Wed, 18 Oct 2023 11:33:38 -0700 Subject: arm: dts: imx8mm-venice-gw73xx: add TPM device Add the TPM device found on the GW73xx revision F PCB. This hangs off of SPI2, uses gpio1_10 as a CS and gpio1_11 as RST#. Signed-off-by: Tim Harvey Reviewed-by: Fabio Estevam --- arch/arm/dts/imx8mm-venice-gw73xx-0x-u-boot.dtsi | 7 +++++++ arch/arm/dts/imx8mm-venice-gw73xx.dtsi | 10 +++++++++- 2 files changed, 16 insertions(+), 1 deletion(-) diff --git a/arch/arm/dts/imx8mm-venice-gw73xx-0x-u-boot.dtsi b/arch/arm/dts/imx8mm-venice-gw73xx-0x-u-boot.dtsi index 92e44d4ba96..31f9d47bced 100644 --- a/arch/arm/dts/imx8mm-venice-gw73xx-0x-u-boot.dtsi +++ b/arch/arm/dts/imx8mm-venice-gw73xx-0x-u-boot.dtsi @@ -39,6 +39,13 @@ gpios = <9 GPIO_ACTIVE_HIGH>; line-name = "dio1"; }; + + tpm_rst { + gpio-hog; + output-high; + gpios = <11 GPIO_ACTIVE_HIGH>; + line-name = "tpm_rst#"; + }; }; &gpio4 { diff --git a/arch/arm/dts/imx8mm-venice-gw73xx.dtsi b/arch/arm/dts/imx8mm-venice-gw73xx.dtsi index 244ef8d6cc6..7b2130dbdb2 100644 --- a/arch/arm/dts/imx8mm-venice-gw73xx.dtsi +++ b/arch/arm/dts/imx8mm-venice-gw73xx.dtsi @@ -104,8 +104,15 @@ &ecspi2 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_spi2>; - cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>; + cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>, + <&gpio1 10 GPIO_ACTIVE_LOW>; status = "okay"; + + tpm@1 { + compatible = "tcg,tpm_tis-spi"; + reg = <0x1>; + spi-max-frequency = <36000000>; + }; }; &gpio1 { @@ -364,6 +371,7 @@ MX8MM_IOMUXC_ECSPI2_MOSI_ECSPI2_MOSI 0xd6 MX8MM_IOMUXC_ECSPI2_MISO_ECSPI2_MISO 0xd6 MX8MM_IOMUXC_ECSPI2_SS0_GPIO5_IO13 0xd6 + MX8MM_IOMUXC_GPIO1_IO10_GPIO1_IO10 0xd6 >; }; -- cgit v1.3.1 From a7d54d3de87d84479a0fd349a2ce7ef8740e9b20 Mon Sep 17 00:00:00 2001 From: Tim Harvey Date: Wed, 18 Oct 2023 11:33:52 -0700 Subject: arm: dts: imx8mp-venice-gw73xx: add TPM device Add the TPM device found on the GW73xx revision F PCB. This hangs off of SPI2, uses gpio1_10 as a CS and gpio1_11 as RST#. Signed-off-by: Tim Harvey Reviewed-by: Fabio Estevam --- arch/arm/dts/imx8mp-venice-gw73xx-2x-u-boot.dtsi | 9 +++++++++ arch/arm/dts/imx8mp-venice-gw73xx.dtsi | 9 ++++++++- 2 files changed, 17 insertions(+), 1 deletion(-) diff --git a/arch/arm/dts/imx8mp-venice-gw73xx-2x-u-boot.dtsi b/arch/arm/dts/imx8mp-venice-gw73xx-2x-u-boot.dtsi index 70433c07329..4d0e9a1e67c 100644 --- a/arch/arm/dts/imx8mp-venice-gw73xx-2x-u-boot.dtsi +++ b/arch/arm/dts/imx8mp-venice-gw73xx-2x-u-boot.dtsi @@ -10,6 +10,15 @@ reset-post-delay-us = <300000>; }; +&gpio1 { + tpm_rst { + gpio-hog; + output-high; + gpios = <11 GPIO_ACTIVE_HIGH>; + line-name = "tpm_rst#"; + }; +}; + &gpio4 { dio_1 { gpio-hog; diff --git a/arch/arm/dts/imx8mp-venice-gw73xx.dtsi b/arch/arm/dts/imx8mp-venice-gw73xx.dtsi index 1c05398c862..88c3c006fa2 100644 --- a/arch/arm/dts/imx8mp-venice-gw73xx.dtsi +++ b/arch/arm/dts/imx8mp-venice-gw73xx.dtsi @@ -95,8 +95,14 @@ &ecspi2 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_spi2>; - cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>; + cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>, + <&gpio1 10 GPIO_ACTIVE_LOW>; status = "okay"; + tpm@1 { + compatible = "tcg,tpm_tis-spi"; + reg = <0x1>; + spi-max-frequency = <36000000>; + }; }; &gpio4 { @@ -327,6 +333,7 @@ MX8MP_IOMUXC_ECSPI2_MOSI__ECSPI2_MOSI 0x140 MX8MP_IOMUXC_ECSPI2_MISO__ECSPI2_MISO 0x140 MX8MP_IOMUXC_ECSPI2_SS0__GPIO5_IO13 0x140 + MX8MP_IOMUXC_GPIO1_IO10__GPIO1_IO10 0x140 >; }; -- cgit v1.3.1 From 6e6492c85defa51d7d8def8580d0d49610ebf0fa Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Wed, 18 Oct 2023 16:17:41 -0300 Subject: imx8mp_evk: Convert to DM_PMIC Currently, the imx8mp_evk uses the non-DM code to initialize the PMIC. Convert to DM_PMIC, which is the recommended way to access the PMIC. While at it, fix multi-line comments style. Signed-off-by: Fabio Estevam Reviewed-by: Peng Fan --- arch/arm/dts/imx8mp-evk-u-boot.dtsi | 18 ++++++++++++- board/freescale/imx8mp_evk/spl.c | 50 +++++++++++++++++++------------------ configs/imx8mp_evk_defconfig | 12 +++------ 3 files changed, 47 insertions(+), 33 deletions(-) diff --git a/arch/arm/dts/imx8mp-evk-u-boot.dtsi b/arch/arm/dts/imx8mp-evk-u-boot.dtsi index 9ed62f1bb02..0bf489b4624 100644 --- a/arch/arm/dts/imx8mp-evk-u-boot.dtsi +++ b/arch/arm/dts/imx8mp-evk-u-boot.dtsi @@ -13,6 +13,22 @@ }; }; +&pinctrl_i2c1 { + bootph-all; +}; + +&pinctrl_pmic { + bootph-all; +}; + +&{/soc@0/bus@30800000/i2c@30a20000/pmic@25} { + bootph-all; +}; + +&{/soc@0/bus@30800000/i2c@30a20000/pmic@25/regulators} { + bootph-all; +}; + ®_usdhc2_vmmc { u-boot,off-on-delay-us = <20000>; }; @@ -66,7 +82,7 @@ }; &i2c1 { - bootph-pre-ram; + bootph-all; }; &i2c2 { diff --git a/board/freescale/imx8mp_evk/spl.c b/board/freescale/imx8mp_evk/spl.c index 246826a0d48..9dd2cbc799c 100644 --- a/board/freescale/imx8mp_evk/spl.c +++ b/board/freescale/imx8mp_evk/spl.c @@ -67,40 +67,44 @@ struct i2c_pads_info i2c_pad_info1 = { }, }; -#if CONFIG_IS_ENABLED(POWER_LEGACY) -#define I2C_PMIC 0 +#if CONFIG_IS_ENABLED(DM_PMIC_PCA9450) int power_init_board(void) { - struct pmic *p; + struct udevice *dev; int ret; - ret = power_pca9450_init(I2C_PMIC, 0x25); - if (ret) - printf("power init failed"); - p = pmic_get("PCA9450"); - pmic_probe(p); + ret = pmic_get("pmic@25", &dev); + if (ret == -ENODEV) { + puts("No pmic@25\n"); + return 0; + } + if (ret < 0) + return ret; /* BUCKxOUT_DVS0/1 control BUCK123 output */ - pmic_reg_write(p, PCA9450_BUCK123_DVS, 0x29); + pmic_reg_write(dev, PCA9450_BUCK123_DVS, 0x29); /* - * increase VDD_SOC to typical value 0.95V before first - * DRAM access, set DVS1 to 0.85v for suspend. + * Increase VDD_SOC to typical value 0.95V before first + * DRAM access, set DVS1 to 0.85V for suspend. * Enable DVS control through PMIC_STBY_REQ and * set B1_ENMODE=1 (ON by PMIC_ON_REQ=H) */ -#ifdef CONFIG_IMX8M_VDD_SOC_850MV - /* set DVS0 to 0.85v for special case*/ - pmic_reg_write(p, PCA9450_BUCK1OUT_DVS0, 0x14); -#else - pmic_reg_write(p, PCA9450_BUCK1OUT_DVS0, 0x1C); -#endif - pmic_reg_write(p, PCA9450_BUCK1OUT_DVS1, 0x14); - pmic_reg_write(p, PCA9450_BUCK1CTRL, 0x59); + if (CONFIG_IS_ENABLED(IMX8M_VDD_SOC_850MV)) + pmic_reg_write(dev, PCA9450_BUCK1OUT_DVS0, 0x14); + else + pmic_reg_write(dev, PCA9450_BUCK1OUT_DVS0, 0x1C); - /* Kernel uses OD/OD freq for SOC */ - /* To avoid timing risk from SOC to ARM,increase VDD_ARM to OD voltage 0.95v */ - pmic_reg_write(p, PCA9450_BUCK2OUT_DVS0, 0x1C); + pmic_reg_write(dev, PCA9450_BUCK1OUT_DVS1, 0x14); + pmic_reg_write(dev, PCA9450_BUCK1CTRL, 0x59); + + /* + * Kernel uses OD/OD freq for SOC. + * To avoid timing risk from SOC to ARM,increase VDD_ARM to OD + * voltage 0.95V. + */ + + pmic_reg_write(dev, PCA9450_BUCK2OUT_DVS0, 0x1C); return 0; } @@ -135,8 +139,6 @@ void board_init_f(ulong dummy) enable_tzc380(); - setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1); - power_init_board(); /* DDR initialization */ diff --git a/configs/imx8mp_evk_defconfig b/configs/imx8mp_evk_defconfig index d538b85c1f8..0b59971723c 100644 --- a/configs/imx8mp_evk_defconfig +++ b/configs/imx8mp_evk_defconfig @@ -7,9 +7,6 @@ CONFIG_SPL_LIBCOMMON_SUPPORT=y CONFIG_SPL_LIBGENERIC_SUPPORT=y CONFIG_ENV_SIZE=0x1000 CONFIG_ENV_OFFSET=0x400000 -CONFIG_SYS_I2C_MXC_I2C1=y -CONFIG_SYS_I2C_MXC_I2C2=y -CONFIG_SYS_I2C_MXC_I2C3=y CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="imx8mp-evk" CONFIG_SPL_TEXT_BASE=0x920000 @@ -88,8 +85,6 @@ CONFIG_FASTBOOT_MMC_USER_SUPPORT=y CONFIG_MXC_GPIO=y CONFIG_DM_PCA953X=y CONFIG_DM_I2C=y -# CONFIG_SPL_DM_I2C is not set -CONFIG_SPL_SYS_I2C_LEGACY=y CONFIG_LED=y CONFIG_LED_GPIO=y CONFIG_SUPPORT_EMMC_BOOT=y @@ -110,15 +105,16 @@ CONFIG_PHY_IMX8MQ_USB=y CONFIG_PINCTRL=y CONFIG_SPL_PINCTRL=y CONFIG_PINCTRL_IMX8M=y -CONFIG_SPL_POWER_LEGACY=y CONFIG_POWER_DOMAIN=y CONFIG_IMX8M_POWER_DOMAIN=y CONFIG_IMX8MP_HSIOMIX_BLKCTRL=y -CONFIG_POWER_PCA9450=y +CONFIG_DM_PMIC=y +CONFIG_DM_PMIC_PCA9450=y +CONFIG_SPL_DM_PMIC_PCA9450=y CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_PCA9450=y CONFIG_DM_REGULATOR_FIXED=y CONFIG_DM_REGULATOR_GPIO=y -CONFIG_SPL_POWER_I2C=y CONFIG_DM_SERIAL=y CONFIG_MXC_UART=y CONFIG_SYSRESET=y -- cgit v1.3.1 From ae09edaeec3d2e8686e6685badd35b2ae81018f7 Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Wed, 18 Oct 2023 16:17:42 -0300 Subject: imx8mp_evk: Add myself to MAINTAINERS I would like to help maintaining the imx8mp_evk board. Add myself to MAINTAINERS. Signed-off-by: Fabio Estevam Acked-by: Peng Fan --- board/freescale/imx8mp_evk/MAINTAINERS | 1 + 1 file changed, 1 insertion(+) diff --git a/board/freescale/imx8mp_evk/MAINTAINERS b/board/freescale/imx8mp_evk/MAINTAINERS index 2759652cc42..c2c7c830b5d 100644 --- a/board/freescale/imx8mp_evk/MAINTAINERS +++ b/board/freescale/imx8mp_evk/MAINTAINERS @@ -1,4 +1,5 @@ i.MX8MP EVK BOARD +M: Fabio Estevm M: Peng Fan S: Maintained F: board/freescale/imx8mp_evk/ -- cgit v1.3.1 From 5037bd532d31894ac420038c8c4f82e1cd52f150 Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Thu, 19 Oct 2023 09:06:21 -0300 Subject: arm: dts: imx8mm: Sync with linux-next 20231019 Sync imx8mm.dtsi with linux-next 20231019. The motivation for doing this sync was a bug when doing "ums 0 mmc 1" on imx8mm-evk. It worked well for the first time, but after doing a CTRL+C and launching the ums again, the command did not work. Adam Ford suggested to sync imx8mm.dtsi with the Linux dts, as there was a recent USB power domain reorganization there. After syncing the imx8mm.dtsi with Linux, the ums command works without problem after a CTRL+C. Suggested-by: Adam Ford Signed-off-by: Fabio Estevam Acked-by: Tim Harvey --- arch/arm/dts/imx8mm.dtsi | 153 +++++++++++++++++++++++++++++++++++++++-------- 1 file changed, 129 insertions(+), 24 deletions(-) diff --git a/arch/arm/dts/imx8mm.dtsi b/arch/arm/dts/imx8mm.dtsi index afb90f59c83..738024baaa5 100644 --- a/arch/arm/dts/imx8mm.dtsi +++ b/arch/arm/dts/imx8mm.dtsi @@ -139,6 +139,7 @@ A53_L2: l2-cache0 { compatible = "cache"; cache-level = <2>; + cache-unified; cache-size = <0x80000>; cache-line-size = <64>; cache-sets = <512>; @@ -276,6 +277,7 @@ assigned-clocks = <&clk IMX8MM_CLK_USB_PHY_REF>; assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_100M>; clock-names = "main_clk"; + power-domains = <&pgc_otg1>; }; usbphynop2: usbphynop2 { @@ -285,6 +287,7 @@ assigned-clocks = <&clk IMX8MM_CLK_USB_PHY_REF>; assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_100M>; clock-names = "main_clk"; + power-domains = <&pgc_otg2>; }; soc: soc@0 { @@ -396,6 +399,7 @@ "pll8k", "pll11k", "clkext3"; dmas = <&sdma2 24 25 0x80000000>; dma-names = "rx"; + #sound-dai-cells = <0>; status = "disabled"; }; @@ -493,6 +497,8 @@ compatible = "fsl,imx8mm-tmu"; reg = <0x30260000 0x10000>; clocks = <&clk IMX8MM_CLK_TMU_ROOT>; + nvmem-cells = <&tmu_calib>; + nvmem-cell-names = "calib"; #thermal-sensor-cells = <0>; }; @@ -547,8 +553,8 @@ reg = <0x30330000 0x10000>; }; - gpr: iomuxc-gpr@30340000 { - compatible = "fsl,imx8mm-iomuxc-gpr", "fsl,imx6q-iomuxc-gpr", "syscon"; + gpr: syscon@30340000 { + compatible = "fsl,imx8mm-iomuxc-gpr", "syscon"; reg = <0x30340000 0x10000>; }; @@ -560,22 +566,40 @@ #address-cells = <1>; #size-cells = <1>; - imx8mm_uid: unique-id@410 { + /* + * The register address below maps to the MX8M + * Fusemap Description Table entries this way. + * Assuming + * reg = ; + * then + * Fuse Address = (ADDR * 4) + 0x400 + * Note that if SIZE is greater than 4, then + * each subsequent fuse is located at offset + * +0x10 in Fusemap Description Table (e.g. + * reg = <0x4 0x8> describes fuses 0x410 and + * 0x420). + */ + imx8mm_uid: unique-id@4 { /* 0x410-0x420 */ reg = <0x4 0x8>; }; - cpu_speed_grade: speed-grade@10 { + cpu_speed_grade: speed-grade@10 { /* 0x440 */ reg = <0x10 4>; }; - fec_mac_address: mac-address@90 { + tmu_calib: calib@3c { /* 0x4f0 */ + reg = <0x3c 4>; + }; + + fec_mac_address: mac-address@90 { /* 0x640 */ reg = <0x90 6>; }; }; - anatop: anatop@30360000 { - compatible = "fsl,imx8mm-anatop", "syscon"; + anatop: clock-controller@30360000 { + compatible = "fsl,imx8mm-anatop"; reg = <0x30360000 0x10000>; + #clock-cells = <1>; }; snvs: snvs@30370000 { @@ -674,13 +698,11 @@ pgc_otg1: power-domain@2 { #power-domain-cells = <0>; reg = ; - power-domains = <&pgc_hsiomix>; }; pgc_otg2: power-domain@3 { #power-domain-cells = <0>; reg = ; - power-domains = <&pgc_hsiomix>; }; pgc_gpumix: power-domain@4 { @@ -1098,6 +1120,61 @@ #size-cells = <1>; ranges = <0x32c00000 0x32c00000 0x400000>; + lcdif: lcdif@32e00000 { + compatible = "fsl,imx8mm-lcdif", "fsl,imx6sx-lcdif"; + reg = <0x32e00000 0x10000>; + clocks = <&clk IMX8MM_CLK_LCDIF_PIXEL>, + <&clk IMX8MM_CLK_DISP_APB_ROOT>, + <&clk IMX8MM_CLK_DISP_AXI_ROOT>; + clock-names = "pix", "axi", "disp_axi"; + assigned-clocks = <&clk IMX8MM_CLK_LCDIF_PIXEL>, + <&clk IMX8MM_CLK_DISP_AXI>, + <&clk IMX8MM_CLK_DISP_APB>; + assigned-clock-parents = <&clk IMX8MM_VIDEO_PLL1_OUT>, + <&clk IMX8MM_SYS_PLL2_1000M>, + <&clk IMX8MM_SYS_PLL1_800M>; + assigned-clock-rates = <594000000>, <500000000>, <200000000>; + interrupts = ; + power-domains = <&disp_blk_ctrl IMX8MM_DISPBLK_PD_LCDIF>; + status = "disabled"; + + port { + lcdif_to_dsim: endpoint { + remote-endpoint = <&dsim_from_lcdif>; + }; + }; + }; + + mipi_dsi: dsi@32e10000 { + compatible = "fsl,imx8mm-mipi-dsim"; + reg = <0x32e10000 0x400>; + clocks = <&clk IMX8MM_CLK_DSI_CORE>, + <&clk IMX8MM_CLK_DSI_PHY_REF>; + clock-names = "bus_clk", "sclk_mipi"; + assigned-clocks = <&clk IMX8MM_CLK_DSI_CORE>, + <&clk IMX8MM_CLK_DSI_PHY_REF>; + assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_266M>, + <&clk IMX8MM_CLK_24M>; + assigned-clock-rates = <266000000>, <24000000>; + samsung,pll-clock-frequency = <24000000>; + interrupts = ; + power-domains = <&disp_blk_ctrl IMX8MM_DISPBLK_PD_MIPI_DSI>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + dsim_from_lcdif: endpoint { + remote-endpoint = <&lcdif_to_dsim>; + }; + }; + }; + }; + csi: csi@32e20000 { compatible = "fsl,imx8mm-csi", "fsl,imx7-csi"; reg = <0x32e20000 0x1000>; @@ -1145,10 +1222,9 @@ compatible = "fsl,imx8mm-mipi-csi2"; reg = <0x32e30000 0x1000>; interrupts = ; - assigned-clocks = <&clk IMX8MM_CLK_CSI1_CORE>, - <&clk IMX8MM_CLK_CSI1_PHY_REF>; - assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_1000M>, - <&clk IMX8MM_SYS_PLL2_1000M>; + assigned-clocks = <&clk IMX8MM_CLK_CSI1_CORE>; + assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_1000M>; + clock-frequency = <333000000>; clocks = <&clk IMX8MM_CLK_DISP_APB_ROOT>, <&clk IMX8MM_CLK_CSI1_ROOT>, @@ -1177,7 +1253,7 @@ }; usbotg1: usb@32e40000 { - compatible = "fsl,imx8mm-usb", "fsl,imx7d-usb"; + compatible = "fsl,imx8mm-usb", "fsl,imx7d-usb", "fsl,imx27-usb"; reg = <0x32e40000 0x200>; interrupts = ; clocks = <&clk IMX8MM_CLK_USB1_CTRL_ROOT>; @@ -1186,18 +1262,19 @@ assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_500M>; phys = <&usbphynop1>; fsl,usbmisc = <&usbmisc1 0>; - power-domains = <&pgc_otg1>; + power-domains = <&pgc_hsiomix>; status = "disabled"; }; usbmisc1: usbmisc@32e40200 { - compatible = "fsl,imx8mm-usbmisc", "fsl,imx7d-usbmisc"; + compatible = "fsl,imx8mm-usbmisc", "fsl,imx7d-usbmisc", + "fsl,imx6q-usbmisc"; #index-cells = <1>; reg = <0x32e40200 0x200>; }; usbotg2: usb@32e50000 { - compatible = "fsl,imx8mm-usb", "fsl,imx7d-usb"; + compatible = "fsl,imx8mm-usb", "fsl,imx7d-usb", "fsl,imx27-usb"; reg = <0x32e50000 0x200>; interrupts = ; clocks = <&clk IMX8MM_CLK_USB1_CTRL_ROOT>; @@ -1206,12 +1283,13 @@ assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_500M>; phys = <&usbphynop2>; fsl,usbmisc = <&usbmisc2 0>; - power-domains = <&pgc_otg2>; + power-domains = <&pgc_hsiomix>; status = "disabled"; }; usbmisc2: usbmisc@32e50200 { - compatible = "fsl,imx8mm-usbmisc", "fsl,imx7d-usbmisc"; + compatible = "fsl,imx8mm-usbmisc", "fsl,imx7d-usbmisc", + "fsl,imx6q-usbmisc"; #index-cells = <1>; reg = <0x32e50200 0x200>; }; @@ -1238,16 +1316,15 @@ , , ; - interrupt-names = "gpmi0", "gpmi1", "gpmi2", "gpmi3"; #dma-cells = <1>; dma-channels = <4>; clocks = <&clk IMX8MM_CLK_NAND_USDHC_BUS_RAWNAND_CLK>; }; - gpmi: nand-controller@33002000{ + gpmi: nand-controller@33002000 { compatible = "fsl,imx8mm-gpmi-nand", "fsl,imx7d-gpmi-nand"; #address-cells = <1>; - #size-cells = <1>; + #size-cells = <0>; reg = <0x33002000 0x2000>, <0x33004000 0x4000>; reg-names = "gpmi-nand", "bch"; interrupts = ; @@ -1268,8 +1345,8 @@ #size-cells = <2>; device_type = "pci"; bus-range = <0x00 0xff>; - ranges = <0x81000000 0 0x00000000 0x1ff80000 0 0x00010000 /* downstream I/O 64KB */ - 0x82000000 0 0x18000000 0x18000000 0 0x07f00000>; /* non-prefetchable memory */ + ranges = <0x81000000 0 0x00000000 0x1ff80000 0 0x00010000>, /* downstream I/O 64KB */ + <0x82000000 0 0x18000000 0x18000000 0 0x07f00000>; /* non-prefetchable memory */ num-lanes = <1>; num-viewport = <4>; interrupts = ; @@ -1282,12 +1359,40 @@ <0 0 0 4 &gic GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>; fsl,max-link-speed = <2>; linux,pci-domain = <0>; + clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>, + <&clk IMX8MM_CLK_PCIE1_PHY>, + <&clk IMX8MM_CLK_PCIE1_AUX>; + clock-names = "pcie", "pcie_bus", "pcie_aux"; + power-domains = <&pgc_pcie>; + resets = <&src IMX8MQ_RESET_PCIE_CTRL_APPS_EN>, + <&src IMX8MQ_RESET_PCIE_CTRL_APPS_TURNOFF>; + reset-names = "apps", "turnoff"; + phys = <&pcie_phy>; + phy-names = "pcie-phy"; + status = "disabled"; + }; + + pcie0_ep: pcie-ep@33800000 { + compatible = "fsl,imx8mm-pcie-ep"; + reg = <0x33800000 0x400000>, + <0x18000000 0x8000000>; + reg-names = "dbi", "addr_space"; + num-lanes = <1>; + interrupts = ; + interrupt-names = "dma"; + fsl,max-link-speed = <2>; + clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>, + <&clk IMX8MM_CLK_PCIE1_PHY>, + <&clk IMX8MM_CLK_PCIE1_AUX>; + clock-names = "pcie", "pcie_bus", "pcie_aux"; power-domains = <&pgc_pcie>; resets = <&src IMX8MQ_RESET_PCIE_CTRL_APPS_EN>, <&src IMX8MQ_RESET_PCIE_CTRL_APPS_TURNOFF>; reset-names = "apps", "turnoff"; phys = <&pcie_phy>; phy-names = "pcie-phy"; + num-ib-windows = <4>; + num-ob-windows = <4>; status = "disabled"; }; -- cgit v1.3.1 From 05dffb9fb12a15c44a20177343b22a98378f5357 Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Thu, 19 Oct 2023 09:06:22 -0300 Subject: arm: dts: imx8mn: Sync with linux-next 20231019 Sync imx8mn.dtsi with linux-next 20231019. Signed-off-by: Fabio Estevam --- arch/arm/dts/imx8mn.dtsi | 167 +++++++++++++++++++++++++++++++++++++++++++---- 1 file changed, 154 insertions(+), 13 deletions(-) diff --git a/arch/arm/dts/imx8mn.dtsi b/arch/arm/dts/imx8mn.dtsi index cb2836bfbd9..1bb1d0c1bae 100644 --- a/arch/arm/dts/imx8mn.dtsi +++ b/arch/arm/dts/imx8mn.dtsi @@ -139,6 +139,7 @@ A53_L2: l2-cache0 { compatible = "cache"; cache-level = <2>; + cache-unified; cache-size = <0x80000>; cache-line-size = <64>; cache-sets = <512>; @@ -295,6 +296,7 @@ sai2: sai@30020000 { compatible = "fsl,imx8mn-sai", "fsl,imx8mq-sai"; reg = <0x30020000 0x10000>; + #sound-dai-cells = <0>; interrupts = ; clocks = <&clk IMX8MN_CLK_SAI2_IPG>, <&clk IMX8MN_CLK_DUMMY>, @@ -309,6 +311,7 @@ sai3: sai@30030000 { compatible = "fsl,imx8mn-sai", "fsl,imx8mq-sai"; reg = <0x30030000 0x10000>; + #sound-dai-cells = <0>; interrupts = ; clocks = <&clk IMX8MN_CLK_SAI3_IPG>, <&clk IMX8MN_CLK_DUMMY>, @@ -323,6 +326,7 @@ sai5: sai@30050000 { compatible = "fsl,imx8mn-sai", "fsl,imx8mq-sai"; reg = <0x30050000 0x10000>; + #sound-dai-cells = <0>; interrupts = ; clocks = <&clk IMX8MN_CLK_SAI5_IPG>, <&clk IMX8MN_CLK_DUMMY>, @@ -339,6 +343,7 @@ sai6: sai@30060000 { compatible = "fsl,imx8mn-sai", "fsl,imx8mq-sai"; reg = <0x30060000 0x10000>; + #sound-dai-cells = <0>; interrupts = ; clocks = <&clk IMX8MN_CLK_SAI6_IPG>, <&clk IMX8MN_CLK_DUMMY>, @@ -366,6 +371,7 @@ "pll8k", "pll11k", "clkext3"; dmas = <&sdma2 24 25 0x80000000>; dma-names = "rx"; + #sound-dai-cells = <0>; status = "disabled"; }; @@ -396,6 +402,7 @@ sai7: sai@300b0000 { compatible = "fsl,imx8mn-sai", "fsl,imx8mq-sai"; reg = <0x300b0000 0x10000>; + #sound-dai-cells = <0>; interrupts = ; clocks = <&clk IMX8MN_CLK_SAI7_IPG>, <&clk IMX8MN_CLK_DUMMY>, @@ -497,6 +504,8 @@ compatible = "fsl,imx8mn-tmu", "fsl,imx8mm-tmu"; reg = <0x30260000 0x10000>; clocks = <&clk IMX8MN_CLK_TMU_ROOT>; + nvmem-cells = <&tmu_calib>; + nvmem-cell-names = "calib"; #thermal-sensor-cells = <0>; }; @@ -551,7 +560,7 @@ reg = <0x30330000 0x10000>; }; - gpr: iomuxc-gpr@30340000 { + gpr: syscon@30340000 { compatible = "fsl,imx8mn-iomuxc-gpr", "syscon"; reg = <0x30340000 0x10000>; }; @@ -563,23 +572,40 @@ #address-cells = <1>; #size-cells = <1>; - imx8mn_uid: unique-id@410 { + /* + * The register address below maps to the MX8M + * Fusemap Description Table entries this way. + * Assuming + * reg = ; + * then + * Fuse Address = (ADDR * 4) + 0x400 + * Note that if SIZE is greater than 4, then + * each subsequent fuse is located at offset + * +0x10 in Fusemap Description Table (e.g. + * reg = <0x4 0x8> describes fuses 0x410 and + * 0x420). + */ + imx8mn_uid: unique-id@4 { /* 0x410-0x420 */ reg = <0x4 0x8>; }; - cpu_speed_grade: speed-grade@10 { + cpu_speed_grade: speed-grade@10 { /* 0x440 */ reg = <0x10 4>; }; - fec_mac_address: mac-address@90 { + tmu_calib: calib@3c { /* 0x4f0 */ + reg = <0x3c 4>; + }; + + fec_mac_address: mac-address@90 { /* 0x640 */ reg = <0x90 6>; }; }; - anatop: anatop@30360000 { - compatible = "fsl,imx8mn-anatop", "fsl,imx8mm-anatop", - "syscon"; + anatop: clock-controller@30360000 { + compatible = "fsl,imx8mn-anatop", "fsl,imx8mm-anatop"; reg = <0x30360000 0x10000>; + #clock-cells = <1>; }; snvs: snvs@30370000 { @@ -662,7 +688,6 @@ pgc_otg1: power-domain@1 { #power-domain-cells = <0>; reg = ; - power-domains = <&pgc_hsiomix>; }; pgc_gpumix: power-domain@2 { @@ -1038,6 +1063,72 @@ #size-cells = <1>; ranges; + lcdif: lcdif@32e00000 { + compatible = "fsl,imx8mn-lcdif", "fsl,imx6sx-lcdif"; + reg = <0x32e00000 0x10000>; + clocks = <&clk IMX8MN_CLK_DISP_PIXEL_ROOT>, + <&clk IMX8MN_CLK_DISP_APB_ROOT>, + <&clk IMX8MN_CLK_DISP_AXI_ROOT>; + clock-names = "pix", "axi", "disp_axi"; + interrupts = ; + power-domains = <&disp_blk_ctrl IMX8MN_DISPBLK_PD_LCDIF>; + status = "disabled"; + + port { + lcdif_to_dsim: endpoint { + remote-endpoint = <&dsim_from_lcdif>; + }; + }; + }; + + mipi_dsi: dsi@32e10000 { + compatible = "fsl,imx8mn-mipi-dsim", "fsl,imx8mm-mipi-dsim"; + reg = <0x32e10000 0x400>; + clocks = <&clk IMX8MN_CLK_DSI_CORE>, + <&clk IMX8MN_CLK_DSI_PHY_REF>; + clock-names = "bus_clk", "sclk_mipi"; + interrupts = ; + power-domains = <&disp_blk_ctrl IMX8MN_DISPBLK_PD_MIPI_DSI>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + dsim_from_lcdif: endpoint { + remote-endpoint = <&lcdif_to_dsim>; + }; + }; + }; + }; + + isi: isi@32e20000 { + compatible = "fsl,imx8mn-isi"; + reg = <0x32e20000 0x8000>; + interrupts = ; + clocks = <&clk IMX8MN_CLK_DISP_AXI_ROOT>, + <&clk IMX8MN_CLK_DISP_APB_ROOT>; + clock-names = "axi", "apb"; + fsl,blk-ctrl = <&disp_blk_ctrl>; + power-domains = <&disp_blk_ctrl IMX8MN_DISPBLK_PD_ISI>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + isi_in: endpoint { + remote-endpoint = <&mipi_csi_out>; + }; + }; + }; + }; + disp_blk_ctrl: blk-ctrl@32e28000 { compatible = "fsl,imx8mn-disp-blk-ctrl", "syscon"; reg = <0x32e28000 0x100>; @@ -1063,11 +1154,60 @@ "lcdif-axi", "lcdif-apb", "lcdif-pix", "dsi-pclk", "dsi-ref", "csi-aclk", "csi-pclk"; + assigned-clocks = <&clk IMX8MN_CLK_DSI_CORE>, + <&clk IMX8MN_CLK_DSI_PHY_REF>, + <&clk IMX8MN_CLK_DISP_PIXEL>, + <&clk IMX8MN_CLK_DISP_AXI>, + <&clk IMX8MN_CLK_DISP_APB>; + assigned-clock-parents = <&clk IMX8MN_SYS_PLL1_266M>, + <&clk IMX8MN_CLK_24M>, + <&clk IMX8MN_VIDEO_PLL1_OUT>, + <&clk IMX8MN_SYS_PLL2_1000M>, + <&clk IMX8MN_SYS_PLL1_800M>; + assigned-clock-rates = <266000000>, + <24000000>, + <594000000>, + <500000000>, + <200000000>; #power-domain-cells = <1>; }; + mipi_csi: mipi-csi@32e30000 { + compatible = "fsl,imx8mm-mipi-csi2"; + reg = <0x32e30000 0x1000>; + interrupts = ; + assigned-clocks = <&clk IMX8MN_CLK_CAMERA_PIXEL>; + assigned-clock-parents = <&clk IMX8MN_SYS_PLL2_1000M>; + assigned-clock-rates = <333000000>; + clock-frequency = <333000000>; + clocks = <&clk IMX8MN_CLK_DISP_APB_ROOT>, + <&clk IMX8MN_CLK_CAMERA_PIXEL>, + <&clk IMX8MN_CLK_CSI1_PHY_REF>, + <&clk IMX8MN_CLK_DISP_AXI_ROOT>; + clock-names = "pclk", "wrap", "phy", "axi"; + power-domains = <&disp_blk_ctrl IMX8MN_DISPBLK_PD_MIPI_CSI>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + }; + + port@1 { + reg = <1>; + + mipi_csi_out: endpoint { + remote-endpoint = <&isi_in>; + }; + }; + }; + }; + usbotg1: usb@32e40000 { - compatible = "fsl,imx8mn-usb", "fsl,imx7d-usb"; + compatible = "fsl,imx8mn-usb", "fsl,imx7d-usb", "fsl,imx27-usb"; reg = <0x32e40000 0x200>; interrupts = ; clocks = <&clk IMX8MN_CLK_USB1_CTRL_ROOT>; @@ -1076,12 +1216,13 @@ assigned-clock-parents = <&clk IMX8MN_SYS_PLL2_500M>; phys = <&usbphynop1>; fsl,usbmisc = <&usbmisc1 0>; - power-domains = <&pgc_otg1>; + power-domains = <&pgc_hsiomix>; status = "disabled"; }; usbmisc1: usbmisc@32e40200 { - compatible = "fsl,imx8mn-usbmisc", "fsl,imx7d-usbmisc"; + compatible = "fsl,imx8mn-usbmisc", "fsl,imx7d-usbmisc", + "fsl,imx6q-usbmisc"; #index-cells = <1>; reg = <0x32e40200 0x200>; }; @@ -1094,7 +1235,6 @@ , , ; - interrupt-names = "gpmi0", "gpmi1", "gpmi2", "gpmi3"; #dma-cells = <1>; dma-channels = <4>; clocks = <&clk IMX8MN_CLK_NAND_USDHC_BUS_RAWNAND_CLK>; @@ -1103,7 +1243,7 @@ gpmi: nand-controller@33002000 { compatible = "fsl,imx8mn-gpmi-nand", "fsl,imx7d-gpmi-nand"; #address-cells = <1>; - #size-cells = <1>; + #size-cells = <0>; reg = <0x33002000 0x2000>, <0x33004000 0x4000>; reg-names = "gpmi-nand", "bch"; interrupts = ; @@ -1175,5 +1315,6 @@ assigned-clocks = <&clk IMX8MN_CLK_USB_PHY_REF>; assigned-clock-parents = <&clk IMX8MN_SYS_PLL1_100M>; clock-names = "main_clk"; + power-domains = <&pgc_otg1>; }; }; -- cgit v1.3.1 From f3197668919b2830825b4fd32a7208b704fef829 Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Thu, 19 Oct 2023 09:06:23 -0300 Subject: arm: dts: imx8mp: Sync with linux-next 20231019 Sync imx8mp.dtsi and imx8mp-clock.h with linux-next 20231019. Signed-off-by: Fabio Estevam --- arch/arm/dts/imx8mp.dtsi | 542 ++++++++++++++++++++++++++++++- include/dt-bindings/clock/imx8mp-clock.h | 3 +- 2 files changed, 526 insertions(+), 19 deletions(-) diff --git a/arch/arm/dts/imx8mp.dtsi b/arch/arm/dts/imx8mp.dtsi index 428c60462e3..c9a610ba483 100644 --- a/arch/arm/dts/imx8mp.dtsi +++ b/arch/arm/dts/imx8mp.dtsi @@ -202,6 +202,60 @@ clock-output-names = "clk_ext4"; }; + funnel { + /* + * non-configurable funnel don't show up on the AMBA + * bus. As such no need to add "arm,primecell". + */ + compatible = "arm,coresight-static-funnel"; + + in-ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + ca_funnel_in_port0: endpoint { + remote-endpoint = <&etm0_out_port>; + }; + }; + + port@1 { + reg = <1>; + + ca_funnel_in_port1: endpoint { + remote-endpoint = <&etm1_out_port>; + }; + }; + + port@2 { + reg = <2>; + + ca_funnel_in_port2: endpoint { + remote-endpoint = <&etm2_out_port>; + }; + }; + + port@3 { + reg = <3>; + + ca_funnel_in_port3: endpoint { + remote-endpoint = <&etm3_out_port>; + }; + }; + }; + + out-ports { + port { + + ca_funnel_out_port0: endpoint { + remote-endpoint = <&hugo_funnel_in_port0>; + }; + }; + }; + }; + reserved-memory { #address-cells = <2>; #size-cells = <2>; @@ -304,6 +358,153 @@ nvmem-cells = <&imx8mp_uid>; nvmem-cell-names = "soc_unique_id"; + etm0: etm@28440000 { + compatible = "arm,coresight-etm4x", "arm,primecell"; + reg = <0x28440000 0x1000>; + cpu = <&A53_0>; + clocks = <&clk IMX8MP_CLK_MAIN_AXI>; + clock-names = "apb_pclk"; + + out-ports { + port { + etm0_out_port: endpoint { + remote-endpoint = <&ca_funnel_in_port0>; + }; + }; + }; + }; + + etm1: etm@28540000 { + compatible = "arm,coresight-etm4x", "arm,primecell"; + reg = <0x28540000 0x1000>; + cpu = <&A53_1>; + clocks = <&clk IMX8MP_CLK_MAIN_AXI>; + clock-names = "apb_pclk"; + + out-ports { + port { + etm1_out_port: endpoint { + remote-endpoint = <&ca_funnel_in_port1>; + }; + }; + }; + }; + + etm2: etm@28640000 { + compatible = "arm,coresight-etm4x", "arm,primecell"; + reg = <0x28640000 0x1000>; + cpu = <&A53_2>; + clocks = <&clk IMX8MP_CLK_MAIN_AXI>; + clock-names = "apb_pclk"; + + out-ports { + port { + etm2_out_port: endpoint { + remote-endpoint = <&ca_funnel_in_port2>; + }; + }; + }; + }; + + etm3: etm@28740000 { + compatible = "arm,coresight-etm4x", "arm,primecell"; + reg = <0x28740000 0x1000>; + cpu = <&A53_3>; + clocks = <&clk IMX8MP_CLK_MAIN_AXI>; + clock-names = "apb_pclk"; + + out-ports { + port { + etm3_out_port: endpoint { + remote-endpoint = <&ca_funnel_in_port3>; + }; + }; + }; + }; + + funnel@28c03000 { + compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; + reg = <0x28c03000 0x1000>; + clocks = <&clk IMX8MP_CLK_MAIN_AXI>; + clock-names = "apb_pclk"; + + in-ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + hugo_funnel_in_port0: endpoint { + remote-endpoint = <&ca_funnel_out_port0>; + }; + }; + + port@1 { + reg = <1>; + + hugo_funnel_in_port1: endpoint { + /* M7 input */ + }; + }; + + port@2 { + reg = <2>; + + hugo_funnel_in_port2: endpoint { + /* DSP input */ + }; + }; + /* the other input ports are not connect to anything */ + }; + + out-ports { + port { + hugo_funnel_out_port0: endpoint { + remote-endpoint = <&etf_in_port>; + }; + }; + }; + }; + + etf@28c04000 { + compatible = "arm,coresight-tmc", "arm,primecell"; + reg = <0x28c04000 0x1000>; + clocks = <&clk IMX8MP_CLK_MAIN_AXI>; + clock-names = "apb_pclk"; + + in-ports { + port { + etf_in_port: endpoint { + remote-endpoint = <&hugo_funnel_out_port0>; + }; + }; + }; + + out-ports { + port { + etf_out_port: endpoint { + remote-endpoint = <&etr_in_port>; + }; + }; + }; + }; + + etr@28c06000 { + compatible = "arm,coresight-tmc", "arm,primecell"; + reg = <0x28c06000 0x1000>; + clocks = <&clk IMX8MP_CLK_MAIN_AXI>; + clock-names = "apb_pclk"; + + in-ports { + port { + etr_in_port: endpoint { + remote-endpoint = <&etf_out_port>; + }; + }; + }; + }; + aips1: bus@30000000 { compatible = "fsl,aips-bus", "simple-bus"; reg = <0x30000000 0x400000>; @@ -497,7 +698,7 @@ snvs_rtc: snvs-rtc-lp { compatible = "fsl,sec-v4.0-mon-rtc-lp"; - regmap =<&snvs>; + regmap = <&snvs>; offset = <0x34>; interrupts = , ; @@ -534,26 +735,16 @@ <&clk IMX8MP_CLK_A53_CORE>, <&clk IMX8MP_CLK_NOC>, <&clk IMX8MP_CLK_NOC_IO>, - <&clk IMX8MP_CLK_GIC>, - <&clk IMX8MP_CLK_AUDIO_AHB>, - <&clk IMX8MP_CLK_AUDIO_AXI_SRC>, - <&clk IMX8MP_AUDIO_PLL1>, - <&clk IMX8MP_AUDIO_PLL2>; + <&clk IMX8MP_CLK_GIC>; assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>, <&clk IMX8MP_ARM_PLL_OUT>, <&clk IMX8MP_SYS_PLL2_1000M>, <&clk IMX8MP_SYS_PLL1_800M>, - <&clk IMX8MP_SYS_PLL2_500M>, - <&clk IMX8MP_SYS_PLL1_800M>, - <&clk IMX8MP_SYS_PLL1_800M>; + <&clk IMX8MP_SYS_PLL2_500M>; assigned-clock-rates = <0>, <0>, <1000000000>, <800000000>, - <500000000>, - <400000000>, - <800000000>, - <393216000>, - <361267200>; + <500000000>; }; src: reset-controller@30390000 { @@ -595,6 +786,19 @@ reg = ; }; + pgc_audio: power-domain@5 { + #power-domain-cells = <0>; + reg = ; + clocks = <&clk IMX8MP_CLK_AUDIO_ROOT>, + <&clk IMX8MP_CLK_AUDIO_AXI>; + assigned-clocks = <&clk IMX8MP_CLK_AUDIO_AHB>, + <&clk IMX8MP_CLK_AUDIO_AXI_SRC>; + assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>, + <&clk IMX8MP_SYS_PLL1_800M>; + assigned-clock-rates = <400000000>, + <600000000>; + }; + pgc_gpu2d: power-domain@6 { #power-domain-cells = <0>; reg = ; @@ -653,7 +857,7 @@ pgc_vpumix: power-domain@19 { #power-domain-cells = <0>; reg = ; - clocks =<&clk IMX8MP_CLK_VPU_ROOT>; + clocks = <&clk IMX8MP_CLK_VPU_ROOT>; }; pgc_vpu_g1: power-domain@20 { @@ -1147,6 +1351,198 @@ }; }; + aips5: bus@30c00000 { + compatible = "fsl,aips-bus", "simple-bus"; + reg = <0x30c00000 0x400000>; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + spba-bus@30c00000 { + compatible = "fsl,spba-bus", "simple-bus"; + reg = <0x30c00000 0x100000>; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + sai1: sai@30c10000 { + compatible = "fsl,imx8mp-sai", "fsl,imx8mq-sai"; + reg = <0x30c10000 0x10000>; + #sound-dai-cells = <0>; + clocks = <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI1_IPG>, + <&clk IMX8MP_CLK_DUMMY>, + <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI1_MCLK1>, + <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI1_MCLK2>, + <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI1_MCLK3>; + clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; + dmas = <&sdma2 0 2 0>, <&sdma2 1 2 0>; + dma-names = "rx", "tx"; + interrupts = ; + status = "disabled"; + }; + + sai2: sai@30c20000 { + compatible = "fsl,imx8mp-sai", "fsl,imx8mq-sai"; + reg = <0x30c20000 0x10000>; + #sound-dai-cells = <0>; + clocks = <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI2_IPG>, + <&clk IMX8MP_CLK_DUMMY>, + <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI2_MCLK1>, + <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI2_MCLK2>, + <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI2_MCLK3>; + clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; + dmas = <&sdma2 2 2 0>, <&sdma2 3 2 0>; + dma-names = "rx", "tx"; + interrupts = ; + status = "disabled"; + }; + + sai3: sai@30c30000 { + compatible = "fsl,imx8mp-sai", "fsl,imx8mq-sai"; + reg = <0x30c30000 0x10000>; + #sound-dai-cells = <0>; + clocks = <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI3_IPG>, + <&clk IMX8MP_CLK_DUMMY>, + <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI3_MCLK1>, + <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI3_MCLK2>, + <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI3_MCLK3>; + clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; + dmas = <&sdma2 4 2 0>, <&sdma2 5 2 0>; + dma-names = "rx", "tx"; + interrupts = ; + status = "disabled"; + }; + + sai5: sai@30c50000 { + compatible = "fsl,imx8mp-sai", "fsl,imx8mq-sai"; + reg = <0x30c50000 0x10000>; + #sound-dai-cells = <0>; + clocks = <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI5_IPG>, + <&clk IMX8MP_CLK_DUMMY>, + <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI5_MCLK1>, + <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI5_MCLK2>, + <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI5_MCLK3>; + clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; + dmas = <&sdma2 8 2 0>, <&sdma2 9 2 0>; + dma-names = "rx", "tx"; + interrupts = ; + status = "disabled"; + }; + + sai6: sai@30c60000 { + compatible = "fsl,imx8mp-sai", "fsl,imx8mq-sai"; + reg = <0x30c60000 0x10000>; + #sound-dai-cells = <0>; + clocks = <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI6_IPG>, + <&clk IMX8MP_CLK_DUMMY>, + <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI6_MCLK1>, + <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI6_MCLK2>, + <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI6_MCLK3>; + clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; + dmas = <&sdma2 10 2 0>, <&sdma2 11 2 0>; + dma-names = "rx", "tx"; + interrupts = ; + status = "disabled"; + }; + + sai7: sai@30c80000 { + compatible = "fsl,imx8mp-sai", "fsl,imx8mq-sai"; + reg = <0x30c80000 0x10000>; + #sound-dai-cells = <0>; + clocks = <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI7_IPG>, + <&clk IMX8MP_CLK_DUMMY>, + <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI7_MCLK1>, + <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI7_MCLK2>, + <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI7_MCLK3>; + clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; + dmas = <&sdma2 12 2 0>, <&sdma2 13 2 0>; + dma-names = "rx", "tx"; + interrupts = ; + status = "disabled"; + }; + + easrc: easrc@30c90000 { + compatible = "fsl,imx8mp-easrc", "fsl,imx8mn-easrc"; + reg = <0x30c90000 0x10000>; + interrupts = ; + clocks = <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_ASRC_IPG>; + clock-names = "mem"; + dmas = <&sdma2 16 23 0> , <&sdma2 17 23 0>, + <&sdma2 18 23 0> , <&sdma2 19 23 0>, + <&sdma2 20 23 0> , <&sdma2 21 23 0>, + <&sdma2 22 23 0> , <&sdma2 23 23 0>; + dma-names = "ctx0_rx", "ctx0_tx", + "ctx1_rx", "ctx1_tx", + "ctx2_rx", "ctx2_tx", + "ctx3_rx", "ctx3_tx"; + firmware-name = "imx/easrc/easrc-imx8mn.bin"; + fsl,asrc-rate = <8000>; + fsl,asrc-format = <2>; + status = "disabled"; + }; + + micfil: audio-controller@30ca0000 { + compatible = "fsl,imx8mp-micfil"; + reg = <0x30ca0000 0x10000>; + #sound-dai-cells = <0>; + interrupts = , + , + , + ; + clocks = <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_PDM_IPG>, + <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_PDM_SEL>, + <&clk IMX8MP_AUDIO_PLL1_OUT>, + <&clk IMX8MP_AUDIO_PLL2_OUT>, + <&clk IMX8MP_CLK_EXT3>; + clock-names = "ipg_clk", "ipg_clk_app", + "pll8k", "pll11k", "clkext3"; + dmas = <&sdma2 24 25 0x80000000>; + dma-names = "rx"; + status = "disabled"; + }; + + }; + + sdma3: dma-controller@30e00000 { + compatible = "fsl,imx8mp-sdma", "fsl,imx8mq-sdma"; + reg = <0x30e00000 0x10000>; + #dma-cells = <3>; + clocks = <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SDMA3_ROOT>, + <&clk IMX8MP_CLK_AUDIO_ROOT>; + clock-names = "ipg", "ahb"; + interrupts = ; + fsl,sdma-ram-script-name = "imx/sdma/sdma-imx7d.bin"; + }; + + sdma2: dma-controller@30e10000 { + compatible = "fsl,imx8mp-sdma", "fsl,imx8mq-sdma"; + reg = <0x30e10000 0x10000>; + #dma-cells = <3>; + clocks = <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SDMA2_ROOT>, + <&clk IMX8MP_CLK_AUDIO_ROOT>; + clock-names = "ipg", "ahb"; + interrupts = ; + fsl,sdma-ram-script-name = "imx/sdma/sdma-imx7d.bin"; + }; + + audio_blk_ctrl: clock-controller@30e20000 { + compatible = "fsl,imx8mp-audio-blk-ctrl"; + reg = <0x30e20000 0x10000>; + #clock-cells = <1>; + clocks = <&clk IMX8MP_CLK_AUDIO_ROOT>, + <&clk IMX8MP_CLK_SAI1>, + <&clk IMX8MP_CLK_SAI2>, + <&clk IMX8MP_CLK_SAI3>, + <&clk IMX8MP_CLK_SAI5>, + <&clk IMX8MP_CLK_SAI6>, + <&clk IMX8MP_CLK_SAI7>; + clock-names = "ahb", + "sai1", "sai2", "sai3", + "sai5", "sai6", "sai7"; + power-domains = <&pgc_audio>; + }; + }; + noc: interconnect@32700000 { compatible = "fsl,imx8mp-noc", "fsl,imx8m-noc"; reg = <0x32700000 0x100000>; @@ -1174,6 +1570,118 @@ #size-cells = <1>; ranges; + isi_0: isi@32e00000 { + compatible = "fsl,imx8mp-isi"; + reg = <0x32e00000 0x4000>; + interrupts = , + ; + clocks = <&clk IMX8MP_CLK_MEDIA_AXI_ROOT>, + <&clk IMX8MP_CLK_MEDIA_APB_ROOT>; + clock-names = "axi", "apb"; + fsl,blk-ctrl = <&media_blk_ctrl>; + power-domains = <&media_blk_ctrl IMX8MP_MEDIABLK_PD_ISI>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + isi_in_0: endpoint { + remote-endpoint = <&mipi_csi_0_out>; + }; + }; + + port@1 { + reg = <1>; + + isi_in_1: endpoint { + remote-endpoint = <&mipi_csi_1_out>; + }; + }; + }; + }; + + dewarp: dwe@32e30000 { + compatible = "nxp,imx8mp-dw100"; + reg = <0x32e30000 0x10000>; + interrupts = ; + clocks = <&clk IMX8MP_CLK_MEDIA_AXI_ROOT>, + <&clk IMX8MP_CLK_MEDIA_APB_ROOT>; + clock-names = "axi", "ahb"; + power-domains = <&media_blk_ctrl IMX8MP_MEDIABLK_PD_DWE>; + }; + + mipi_csi_0: csi@32e40000 { + compatible = "fsl,imx8mp-mipi-csi2", "fsl,imx8mm-mipi-csi2"; + reg = <0x32e40000 0x10000>; + interrupts = ; + clock-frequency = <500000000>; + clocks = <&clk IMX8MP_CLK_MEDIA_APB_ROOT>, + <&clk IMX8MP_CLK_MEDIA_CAM1_PIX_ROOT>, + <&clk IMX8MP_CLK_MEDIA_MIPI_PHY1_REF_ROOT>, + <&clk IMX8MP_CLK_MEDIA_AXI_ROOT>; + clock-names = "pclk", "wrap", "phy", "axi"; + assigned-clocks = <&clk IMX8MP_CLK_MEDIA_CAM1_PIX>; + assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_1000M>; + assigned-clock-rates = <500000000>; + power-domains = <&media_blk_ctrl IMX8MP_MEDIABLK_PD_MIPI_CSI2_1>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + }; + + port@1 { + reg = <1>; + + mipi_csi_0_out: endpoint { + remote-endpoint = <&isi_in_0>; + }; + }; + }; + }; + + mipi_csi_1: csi@32e50000 { + compatible = "fsl,imx8mp-mipi-csi2", "fsl,imx8mm-mipi-csi2"; + reg = <0x32e50000 0x10000>; + interrupts = ; + clock-frequency = <266000000>; + clocks = <&clk IMX8MP_CLK_MEDIA_APB_ROOT>, + <&clk IMX8MP_CLK_MEDIA_CAM2_PIX_ROOT>, + <&clk IMX8MP_CLK_MEDIA_MIPI_PHY1_REF_ROOT>, + <&clk IMX8MP_CLK_MEDIA_AXI_ROOT>; + clock-names = "pclk", "wrap", "phy", "axi"; + assigned-clocks = <&clk IMX8MP_CLK_MEDIA_CAM2_PIX>; + assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_1000M>; + assigned-clock-rates = <266000000>; + power-domains = <&media_blk_ctrl IMX8MP_MEDIABLK_PD_MIPI_CSI2_2>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + }; + + port@1 { + reg = <1>; + + mipi_csi_1_out: endpoint { + remote-endpoint = <&isi_in_1>; + }; + }; + }; + }; + mipi_dsi: dsi@32e60000 { compatible = "fsl,imx8mp-mipi-dsim"; reg = <0x32e60000 0x400>; @@ -1382,8 +1890,8 @@ #size-cells = <2>; device_type = "pci"; bus-range = <0x00 0xff>; - ranges = <0x81000000 0 0x00000000 0x1ff80000 0 0x00010000>, /* downstream I/O 64KB */ - <0x82000000 0 0x18000000 0x18000000 0 0x07f00000>; /* non-prefetchable memory */ + ranges = <0x81000000 0 0x00000000 0x1ff80000 0 0x00010000>, /* downstream I/O 64KB */ + <0x82000000 0 0x18000000 0x18000000 0 0x07f00000>; /* non-prefetchable memory */ num-lanes = <1>; num-viewport = <4>; interrupts = ; diff --git a/include/dt-bindings/clock/imx8mp-clock.h b/include/dt-bindings/clock/imx8mp-clock.h index 3f28ce685f4..7da4243984b 100644 --- a/include/dt-bindings/clock/imx8mp-clock.h +++ b/include/dt-bindings/clock/imx8mp-clock.h @@ -130,7 +130,7 @@ #define IMX8MP_CLK_SAI1 123 #define IMX8MP_CLK_SAI2 124 #define IMX8MP_CLK_SAI3 125 -#define IMX8MP_CLK_SAI4 126 +/* #define IMX8MP_CLK_SAI4 126 */ #define IMX8MP_CLK_SAI5 127 #define IMX8MP_CLK_SAI6 128 #define IMX8MP_CLK_ENET_QOS 129 @@ -376,7 +376,6 @@ #define IMX8MP_CLK_AUDIOMIX_MU2_ROOT 36 #define IMX8MP_CLK_AUDIOMIX_MU3_ROOT 37 #define IMX8MP_CLK_AUDIOMIX_EARC_PHY 38 -#define IMX8MP_CLK_AUDIOMIX_PDM_ROOT 39 #define IMX8MP_CLK_AUDIOMIX_SAI1_MCLK1_SEL 40 #define IMX8MP_CLK_AUDIOMIX_SAI1_MCLK2_SEL 41 #define IMX8MP_CLK_AUDIOMIX_SAI2_MCLK1_SEL 42 -- cgit v1.3.1 From 7e3d6ec9bfc56dd779d4c618915bac708b7dccb6 Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Thu, 19 Oct 2023 09:36:09 -0300 Subject: phy: phy-imx8mq-usb: Remove .exit operation Currently, when running "ums 0 mmc 2" and breaking it via CTRL + C, the following message is seen: u-boot=> ums 0 mmc 1 UMS: LUN 0, dev mmc 1, hwpart 0, sector 0x0, count 0x1dacc00 CTRL+C - Operation aborted clk usb_phy_root_clk already disabled The USB PHY clock is disabled twice: first it gets disabled inside imx8mq_usb_phy_power_off(), then it is disabled again inside imx8mq_usb_phy_exit(). Let the USB PHY clock be disabled only once inside imx8mq_usb_phy_power_off() by removing the .exit operation. Signed-off-by: Fabio Estevam Reviewed-by: Marek Vasut --- drivers/phy/phy-imx8mq-usb.c | 6 ------ 1 file changed, 6 deletions(-) diff --git a/drivers/phy/phy-imx8mq-usb.c b/drivers/phy/phy-imx8mq-usb.c index b660eadecf1..e5e96e77a68 100644 --- a/drivers/phy/phy-imx8mq-usb.c +++ b/drivers/phy/phy-imx8mq-usb.c @@ -231,16 +231,10 @@ static int imx8mq_usb_phy_power_off(struct phy *usb_phy) return 0; } -static int imx8mq_usb_phy_exit(struct phy *usb_phy) -{ - return imx8mq_usb_phy_power_off(usb_phy); -} - struct phy_ops imx8mq_usb_phy_ops = { .init = imx8mpq_usb_phy_init, .power_on = imx8mq_usb_phy_power_on, .power_off = imx8mq_usb_phy_power_off, - .exit = imx8mq_usb_phy_exit, }; int imx8mq_usb_phy_probe(struct udevice *dev) -- cgit v1.3.1 From 21b30c237aa649f7de0ddf6140eb747e114a2063 Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Thu, 19 Oct 2023 18:51:12 -0300 Subject: imx8mp_evk: Simplify Ethernet initialization With DM enabled, there is no need for board code to initialize the Ethernet interfaces. The RTL8211FDI Ethernet PHYs have 25MHz oscillator, so there is no need to enable the RGMII TX clk output. Also, there is no need for describing the deprecated phy-reset FEC properties, nor passing reset properties to the EQOS interface in u-boot.dtsi. Remove all these unneeded pieces. Tested both Ethernet interfaces after these changes. Signed-off-by: Fabio Estevam Reviewed-by: Hugo Villeneuve --- arch/arm/dts/imx8mp-evk-u-boot.dtsi | 14 -------------- board/freescale/imx8mp_evk/imx8mp_evk.c | 28 +--------------------------- 2 files changed, 1 insertion(+), 41 deletions(-) diff --git a/arch/arm/dts/imx8mp-evk-u-boot.dtsi b/arch/arm/dts/imx8mp-evk-u-boot.dtsi index 0bf489b4624..51c84383673 100644 --- a/arch/arm/dts/imx8mp-evk-u-boot.dtsi +++ b/arch/arm/dts/imx8mp-evk-u-boot.dtsi @@ -137,17 +137,3 @@ &wdog1 { bootph-pre-ram; }; - -ðphy0 { - reset-gpios = <&gpio4 22 GPIO_ACTIVE_LOW>; - reset-delay-us = <15000>; - reset-post-delay-us = <100000>; -}; - -&fec { - phy-reset-gpios = <&gpio4 2 GPIO_ACTIVE_LOW>; - phy-reset-duration = <15>; - phy-reset-post-delay = <100>; -}; - - diff --git a/board/freescale/imx8mp_evk/imx8mp_evk.c b/board/freescale/imx8mp_evk/imx8mp_evk.c index a24b8c1d860..42291c958e3 100644 --- a/board/freescale/imx8mp_evk/imx8mp_evk.c +++ b/board/freescale/imx8mp_evk/imx8mp_evk.c @@ -7,8 +7,6 @@ #include #include #include -#include -#include #include #include #include @@ -20,33 +18,9 @@ DECLARE_GLOBAL_DATA_PTR; -static void setup_fec(void) -{ - struct iomuxc_gpr_base_regs *gpr = - (struct iomuxc_gpr_base_regs *)IOMUXC_GPR_BASE_ADDR; - - /* Enable RGMII TX clk output */ - setbits_le32(&gpr->gpr[1], BIT(22)); -} - -#if CONFIG_IS_ENABLED(NET) -int board_phy_config(struct phy_device *phydev) -{ - if (phydev->drv->config) - phydev->drv->config(phydev); - return 0; -} -#endif - int board_init(void) { - int ret = 0; - - if (IS_ENABLED(CONFIG_FEC_MXC)) { - setup_fec(); - } - - return ret; + return 0; } int board_late_init(void) -- cgit v1.3.1 From 7d6b706d10081b88ed747cd1fe048e5363c6a32e Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Thu, 19 Oct 2023 18:51:13 -0300 Subject: imx8mp_evk: Remove unneeded header files Cleanup the file by removing unneeded header files. Signed-off-by: Fabio Estevam Reviewed-by: Hugo Villeneuve --- board/freescale/imx8mp_evk/imx8mp_evk.c | 13 ------------- 1 file changed, 13 deletions(-) diff --git a/board/freescale/imx8mp_evk/imx8mp_evk.c b/board/freescale/imx8mp_evk/imx8mp_evk.c index 42291c958e3..024b46ef8bc 100644 --- a/board/freescale/imx8mp_evk/imx8mp_evk.c +++ b/board/freescale/imx8mp_evk/imx8mp_evk.c @@ -3,20 +3,7 @@ * Copyright 2019 NXP */ -#include #include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -DECLARE_GLOBAL_DATA_PTR; int board_init(void) { -- cgit v1.3.1 From 458ab6b9f224f2dc36a6203a2eddb98445309b0e Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Thu, 19 Oct 2023 21:47:35 -0300 Subject: clock_imx8mm: Add a stub for imx8mp_fec_interface_init() When CONFIG_DWC_ETH_QOS_IMX=y and CONFIG_FEC_MXC is not selected, the following warning is seen: arch/arm/mach-imx/imx8m/clock_imx8mm.c: In function 'board_interface_eth_init': arch/arm/mach-imx/imx8m/clock_imx8mm.c:914:24: warning: implicit declaration of function 'imx8mp_fec_interface_init; did you mean 'imx8mp_eqos_interface_init'? [-Wimplicit-function-declaration] Fix it by adding a stub for imx8mp_fec_interface_init() to handle this case. This follows the same approach done on imx8mp_eqos_interface_init(). Signed-off-by: Fabio Estevam Reviewed-by: Marek Vasut --- arch/arm/mach-imx/imx8m/clock_imx8mm.c | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/arch/arm/mach-imx/imx8m/clock_imx8mm.c b/arch/arm/mach-imx/imx8m/clock_imx8mm.c index 986870799d3..5cf97a5ea95 100644 --- a/arch/arm/mach-imx/imx8m/clock_imx8mm.c +++ b/arch/arm/mach-imx/imx8m/clock_imx8mm.c @@ -904,6 +904,13 @@ static int imx8mp_fec_interface_init(struct udevice *dev, return 0; } +#else +static int imx8mp_fec_interface_init(struct udevice *dev, + phy_interface_t interface_type, + bool mx8mp) +{ + return 0; +} #endif int board_interface_eth_init(struct udevice *dev, phy_interface_t interface_type) -- cgit v1.3.1 From 38bcce4bb64e1796fe668697e544b366804778be Mon Sep 17 00:00:00 2001 From: Hugo Villeneuve Date: Thu, 19 Oct 2023 15:42:41 -0400 Subject: imx8mn_var_som: Add myself to MAINTAINERS I would like to help maintaining the imx8mn_var_som symphony board. Add myself to MAINTAINERS. Signed-off-by: Hugo Villeneuve Reviewed-by: Fabio Estevam --- board/variscite/imx8mn_var_som/MAINTAINERS | 1 + 1 file changed, 1 insertion(+) diff --git a/board/variscite/imx8mn_var_som/MAINTAINERS b/board/variscite/imx8mn_var_som/MAINTAINERS index 068f807ae69..367f72dfe4f 100644 --- a/board/variscite/imx8mn_var_som/MAINTAINERS +++ b/board/variscite/imx8mn_var_som/MAINTAINERS @@ -1,5 +1,6 @@ ARM i.MX8MN VARISCITE VAR-SOM-MX8MN MODULE M: Ariel D'Alessandro +M: Hugo Villeneuve S: Maintained F: arch/arm/dts/imx8mn-var-som* F: board/variscite/imx8mn_var_som/ -- cgit v1.3.1 From 739d9b8f7c97a25af96d36b8fd36cf7e8eb4f8c3 Mon Sep 17 00:00:00 2001 From: Hugo Villeneuve Date: Thu, 19 Oct 2023 15:43:23 -0400 Subject: imx8mn-var-som: Simplify FEC initialization With DM enabled, there is no need for board code to initialize the FEC interface. The ethernet PHYs on the symphony carrier board have a dedicated crystal/oscillator. If the SOM has the EC configuration option (onboard ethernet PHY), it also has a dedicated crystal/oscillator. So in all cases, there is no need to enable the RGMII TX clk output. This follows a similar change introduced by Fabio Estevam: Link: https://lore.kernel.org/u-boot/20231019170441.1610453-1-festevam@gmail.com/ Signed-off-by: Hugo Villeneuve Reviewed-by: Fabio Estevam --- board/variscite/imx8mn_var_som/imx8mn_var_som.c | 13 ------------- 1 file changed, 13 deletions(-) diff --git a/board/variscite/imx8mn_var_som/imx8mn_var_som.c b/board/variscite/imx8mn_var_som/imx8mn_var_som.c index 61b9455a8f4..994fd4f7058 100644 --- a/board/variscite/imx8mn_var_som/imx8mn_var_som.c +++ b/board/variscite/imx8mn_var_som/imx8mn_var_som.c @@ -12,7 +12,6 @@ #include #include #include -#include #include #include #include @@ -46,20 +45,8 @@ struct var_imx8_eeprom_info { u8 partnumber2[5]; /* Part number 2 */ } __packed; -static void setup_fec(void) -{ - struct iomuxc_gpr_base_regs *gpr = - (struct iomuxc_gpr_base_regs *)IOMUXC_GPR_BASE_ADDR; - - /* Use 125M anatop REF_CLK1 for ENET1, not from external */ - clrsetbits_le32(&gpr->gpr[1], 0x2000, 0); -} - int board_init(void) { - if (IS_ENABLED(CONFIG_FEC_MXC)) - setup_fec(); - return 0; } -- cgit v1.3.1 From bdd32b8cbca645520d1b1370a9c320440a6d420e Mon Sep 17 00:00:00 2001 From: Hugo Villeneuve Date: Mon, 23 Oct 2023 11:26:28 -0400 Subject: MAINTAINERS: Remove non-working address from MAINTAINERS The address ariel.dalessandro@collabora.com is no longer working: A message that you sent could not be delivered to one or more of its recipients. This is a permanent error. The following address(es) failed: ariel.dalessandro@collabora.com host mx.collabora.co.uk [46.235.227.165] SMTP error from remote mail server after RCPT TO:: 550 5.1.1 : Recipient address rejected: undeliverable address: host mail.collabora.co.uk[46.235.227.172] said: 550 5.1.1 : Recipient address rejected: User unknown in local recipient table (in reply to RCPT TO command) Remove this address from MAINTAINERS. Signed-off-by: Hugo Villeneuve Reviewed-by: Fabio Estevam --- board/bsh/imx8mn_smm_s2/MAINTAINERS | 1 - board/variscite/imx8mn_var_som/MAINTAINERS | 1 - 2 files changed, 2 deletions(-) diff --git a/board/bsh/imx8mn_smm_s2/MAINTAINERS b/board/bsh/imx8mn_smm_s2/MAINTAINERS index 1de816ca871..c7898278359 100644 --- a/board/bsh/imx8mn_smm_s2/MAINTAINERS +++ b/board/bsh/imx8mn_smm_s2/MAINTAINERS @@ -1,5 +1,4 @@ ARM i.MX8MN BSH SMM S2 BOARDS -M: Ariel D'Alessandro M: Michael Trimarchi S: Maintained F: arch/arm/dts/imx8mn-bsh-smm-s2* diff --git a/board/variscite/imx8mn_var_som/MAINTAINERS b/board/variscite/imx8mn_var_som/MAINTAINERS index 367f72dfe4f..a0fb1546f2f 100644 --- a/board/variscite/imx8mn_var_som/MAINTAINERS +++ b/board/variscite/imx8mn_var_som/MAINTAINERS @@ -1,5 +1,4 @@ ARM i.MX8MN VARISCITE VAR-SOM-MX8MN MODULE -M: Ariel D'Alessandro M: Hugo Villeneuve S: Maintained F: arch/arm/dts/imx8mn-var-som* -- cgit v1.3.1 From dc48e263a60d15236369e43944ef2e3a0d613a23 Mon Sep 17 00:00:00 2001 From: Adam Ford Date: Wed, 25 Oct 2023 18:04:52 -0500 Subject: configs: imx8mp_beacon: Do not set SYS_CONSOLE_IS_IN_ENV The hardware only supports a specific console port, so remove the option to change the console location in the environment. Signed-off-by: Adam Ford Reviewed-by: Fabio Estevam --- configs/imx8mp_beacon_defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/configs/imx8mp_beacon_defconfig b/configs/imx8mp_beacon_defconfig index b686af8d188..c758ff371d3 100644 --- a/configs/imx8mp_beacon_defconfig +++ b/configs/imx8mp_beacon_defconfig @@ -42,6 +42,7 @@ CONFIG_DISTRO_DEFAULTS=y CONFIG_OF_SYSTEM_SETUP=y CONFIG_BOOTCOMMAND="mmc dev ${mmcdev}; if mmc rescan; then if run loadbootscript; then run bootscript; else if run loadimage; then run mmcboot; else run netboot; fi; fi; else booti ${loadaddr} - ${fdt_addr}; fi" CONFIG_DEFAULT_FDT_FILE="imx8mp-beacon-kit.dtb" +# CONFIG_SYS_CONSOLE_IS_IN_ENV is not set # CONFIG_SYS_DEVICE_NULLDEV is not set CONFIG_SPL_MAX_SIZE=0x26000 CONFIG_SPL_HAS_BSS_LINKER_SECTION=y -- cgit v1.3.1 From 495bec2ec87b9dc59c18898cf7e884d55fb8e075 Mon Sep 17 00:00:00 2001 From: Adam Ford Date: Wed, 25 Oct 2023 18:04:53 -0500 Subject: configs: imx8mm_beacon: Enable fastboot downloading Fastboot is necessary to use UUU enhanced functions, so enable it. Signed-off-by: Adam Ford --- configs/imx8mm_beacon_defconfig | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/configs/imx8mm_beacon_defconfig b/configs/imx8mm_beacon_defconfig index 031470c1692..886d912650e 100644 --- a/configs/imx8mm_beacon_defconfig +++ b/configs/imx8mm_beacon_defconfig @@ -86,6 +86,11 @@ CONFIG_SPL_CLK_COMPOSITE_CCF=y CONFIG_CLK_COMPOSITE_CCF=y CONFIG_SPL_CLK_IMX8MM=y CONFIG_CLK_IMX8MM=y +CONFIG_USB_FUNCTION_FASTBOOT=y +CONFIG_FASTBOOT_BUF_ADDR=0x42800000 +CONFIG_FASTBOOT_BUF_SIZE=0x20000000 +CONFIG_FASTBOOT_FLASH=y +CONFIG_FASTBOOT_FLASH_MMC_DEV=2 CONFIG_MXC_GPIO=y CONFIG_DM_PCA953X=y CONFIG_DM_I2C=y @@ -142,6 +147,5 @@ CONFIG_USB_GADGET_VENDOR_NUM=0x0525 CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 CONFIG_CI_UDC=y CONFIG_SDP_LOADADDR=0x40400000 -CONFIG_USB_GADGET_DOWNLOAD=y CONFIG_SPL_USB_SDP_SUPPORT=y CONFIG_IMX_WATCHDOG=y -- cgit v1.3.1 From 856227292aa0027170a4e3e73e87e5bbe8da54d6 Mon Sep 17 00:00:00 2001 From: Adam Ford Date: Wed, 25 Oct 2023 18:04:54 -0500 Subject: configs: imx8mm_beacon: Disable the WDT autostart Auto-starting the WDT can cause false reboots when the user is not intentionally trying to use the WDT, so leave it off until it is requested. Signed-off-by: Adam Ford --- configs/imx8mm_beacon_defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/configs/imx8mm_beacon_defconfig b/configs/imx8mm_beacon_defconfig index 886d912650e..b33e113580b 100644 --- a/configs/imx8mm_beacon_defconfig +++ b/configs/imx8mm_beacon_defconfig @@ -148,4 +148,5 @@ CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 CONFIG_CI_UDC=y CONFIG_SDP_LOADADDR=0x40400000 CONFIG_SPL_USB_SDP_SUPPORT=y +# CONFIG_WATCHDOG_AUTOSTART is not set CONFIG_IMX_WATCHDOG=y -- cgit v1.3.1 From 353c9aa18c3e8016751e03a44fd58cac291626fd Mon Sep 17 00:00:00 2001 From: Adam Ford Date: Wed, 25 Oct 2023 18:04:55 -0500 Subject: configs: imx8mn_beacon: Do not set SYS_CONSOLE_IS_IN_ENV The hardware only supports a specific console port, so remove the option to change the console location in the environment. Signed-off-by: Adam Ford --- configs/imx8mn_beacon_defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/configs/imx8mn_beacon_defconfig b/configs/imx8mn_beacon_defconfig index 9409d5142c7..cfff20f84ff 100644 --- a/configs/imx8mn_beacon_defconfig +++ b/configs/imx8mn_beacon_defconfig @@ -34,6 +34,7 @@ CONFIG_OF_SYSTEM_SETUP=y CONFIG_USE_BOOTCOMMAND=y CONFIG_BOOTCOMMAND="mmc dev ${mmcdev}; if mmc rescan; then if run loadbootscript; then run bootscript; else if run loadimage; then run mmcboot; else run netboot; fi; fi; else booti ${loadaddr} - ${fdt_addr}; fi" CONFIG_DEFAULT_FDT_FILE="imx8mn-beacon-kit.dtb" +# CONFIG_SYS_CONSOLE_IS_IN_ENV is not set CONFIG_SPL_MAX_SIZE=0x25000 CONFIG_SPL_HAS_BSS_LINKER_SECTION=y CONFIG_SPL_BSS_START_ADDR=0x950000 -- cgit v1.3.1 From 4c303a389545dc8ba76ba9fe4928b20ae94502ec Mon Sep 17 00:00:00 2001 From: Adam Ford Date: Wed, 25 Oct 2023 18:04:56 -0500 Subject: configs: imx8mn_beacon: Disable the WDT autostart Auto-starting the WDT can cause false reboots when the user is not intentionally trying to use the WDT, so leave it off until it is requested. Signed-off-by: Adam Ford --- configs/imx8mn_beacon_defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/configs/imx8mn_beacon_defconfig b/configs/imx8mn_beacon_defconfig index cfff20f84ff..d1c27ce22ca 100644 --- a/configs/imx8mn_beacon_defconfig +++ b/configs/imx8mn_beacon_defconfig @@ -150,4 +150,5 @@ CONFIG_USB_GADGET_MANUFACTURER="FSL" CONFIG_USB_GADGET_VENDOR_NUM=0x0525 CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 CONFIG_CI_UDC=y +# CONFIG_WATCHDOG_AUTOSTART is not set CONFIG_IMX_WATCHDOG=y -- cgit v1.3.1 From 4ae3fcdf7b5cb9625e78110183392d0d4e8fe783 Mon Sep 17 00:00:00 2001 From: Arnaud Ferraris Date: Fri, 27 Oct 2023 15:40:44 +0200 Subject: librem5: properly set the `fdtfile` env variable In order to use the generic "distro boot" using an extlinux.conf file, the `fdtfile` environment variable is mandatory. This commit ensure this variable is properly constructed based on the detected board revision. Signed-off-by: Arnaud Ferraris --- board/purism/librem5/librem5.c | 27 ++++++++++++++++++++++++++- 1 file changed, 26 insertions(+), 1 deletion(-) diff --git a/board/purism/librem5/librem5.c b/board/purism/librem5/librem5.c index 386ed1b4fb2..d0249e71f09 100644 --- a/board/purism/librem5/librem5.c +++ b/board/purism/librem5/librem5.c @@ -399,21 +399,46 @@ int board_init(void) int board_late_init(void) { if (IS_ENABLED(CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG)) { - u32 rev; + /* + * Use the r4 dtb by default as those are the most + * widespread devices. + */ + u32 rev, dtb_rev = 4; char rev_str[3]; + char fdt_str[50]; env_set("board_name", "librem5"); if (fuse_read(9, 0, &rev)) { env_set("board_rev", BOARD_REV_ERROR); } else if (rev == 0) { + /* + * If the fuses aren't burnt we should use either the + * r2 or r3 DTB. The latter makes more sense as there + * are far more r3 devices out there. + */ + dtb_rev = 3; env_set("board_rev", BOARD_REV_UNKNOWN); } else if (rev > 0) { + if (rev == 1) + dtb_rev = 2; + else if (rev < dtb_rev) + dtb_rev = rev; + /* + * FCC-approved devices report '5' as their board + * revision but use the r4 DTB as the PCB's are + * functionally identical. + */ + else if (rev == 5) + dtb_rev = 4; sprintf(rev_str, "%u", rev); env_set("board_rev", rev_str); } printf("Board name: %s\n", env_get("board_name")); printf("Board rev: %s\n", env_get("board_rev")); + + sprintf(fdt_str, "freescale/imx8mq-librem5-r%u.dtb", dtb_rev); + env_set("fdtfile", fdt_str); } if (is_usb_boot()) { -- cgit v1.3.1 From 62b1bbdfdf453e8438c404b4ea40e63ee60f03e9 Mon Sep 17 00:00:00 2001 From: Arnaud Ferraris Date: Fri, 27 Oct 2023 15:40:45 +0200 Subject: librem5: Add addresses for compressed kernel load The "booti" command to load arm64 Linux kernels supports automatic decompression of zipped kernel images, but relies on some environment variables to point to usable buffer RAM. Add those variables and let them point to some default values, that should cover most use-cases. Signed-off-by: Arnaud Ferraris --- include/configs/librem5.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/include/configs/librem5.h b/include/configs/librem5.h index ce0a340ba26..876b02f4da6 100644 --- a/include/configs/librem5.h +++ b/include/configs/librem5.h @@ -56,6 +56,8 @@ "scriptaddr=0x80000000\0" \ "pxefile_addr_r=0x80100000\0" \ "kernel_addr_r=0x80800000\0" \ + "kernel_comp_addr_r=0x90000000\0" \ + "kernel_comp_size=0x08000000\0" \ "fdt_addr_r=0x84800000\0" \ "ramdisk_addr_r=0x85000000\0" \ "console=" CONSOLE ",115200\0" \ -- cgit v1.3.1 From 99da64e1efce5eaa59c78cc6e7586d014b5917ef Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Fri, 3 Nov 2023 19:47:33 -0300 Subject: pico-imx7d: Remove board_phy_config() With Ethernet DM in place, there is no longer the need for having the board_phy_config() anymore. Remove it. Tested on imx7d-pico-pi board: => setenv autoload no => dhcp BOOTP broadcast 1 *** Unhandled DHCP Option in OFFER/ACK: 42 DHCP client bound to address 192.168.0.138 (138 ms) => tftp zImage Using ethernet@30be0000 device TFTP from server 192.168.0.16; our IP address is 192.168.0.138 Filename 'zImage'. Load address: 0x80800000 Loading: ################################################################# .... ################################################################# ########## 4.3 MiB/s done Bytes transferred = 9034120 (89d988 hex) Signed-off-by: Fabio Estevam --- board/technexion/pico-imx7d/pico-imx7d.c | 26 -------------------------- 1 file changed, 26 deletions(-) diff --git a/board/technexion/pico-imx7d/pico-imx7d.c b/board/technexion/pico-imx7d/pico-imx7d.c index 6e98b85b287..5def6eda43e 100644 --- a/board/technexion/pico-imx7d/pico-imx7d.c +++ b/board/technexion/pico-imx7d/pico-imx7d.c @@ -101,32 +101,6 @@ static int setup_fec(void) return set_clk_enet(ENET_125MHZ); } - -int board_phy_config(struct phy_device *phydev) -{ - unsigned short val; - - /* To enable AR8035 ouput a 125MHz clk from CLK_25M */ - phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x7); - phy_write(phydev, MDIO_DEVAD_NONE, 0xe, 0x8016); - phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x4007); - - val = phy_read(phydev, MDIO_DEVAD_NONE, 0xe); - val &= 0xffe7; - val |= 0x18; - phy_write(phydev, MDIO_DEVAD_NONE, 0xe, val); - - /* introduce tx clock delay */ - phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x5); - val = phy_read(phydev, MDIO_DEVAD_NONE, 0x1e); - val |= 0x0100; - phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, val); - - if (phydev->drv->config) - phydev->drv->config(phydev); - - return 0; -} #endif static void setup_iomux_uart(void) -- cgit v1.3.1 From 4b5c1175a2ba8493ecb223d99b31d5f55eb4c3f4 Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Fri, 3 Nov 2023 20:00:54 -0300 Subject: imx7d-pico-pi-u-boot.dtsi: Fix aliases indentation The aliases are currently indented using spaces. Fix it to use the standard tab indentation. Signed-off-by: Fabio Estevam --- arch/arm/dts/imx7d-pico-pi-u-boot.dtsi | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/arch/arm/dts/imx7d-pico-pi-u-boot.dtsi b/arch/arm/dts/imx7d-pico-pi-u-boot.dtsi index 843b4583e53..3a6294daff3 100644 --- a/arch/arm/dts/imx7d-pico-pi-u-boot.dtsi +++ b/arch/arm/dts/imx7d-pico-pi-u-boot.dtsi @@ -1,11 +1,11 @@ #include "imx7s-u-boot.dtsi" /{ - aliases { - mmc0 = &usdhc3; - usb0 = &usbotg1; - display0 = &lcdif; - }; + aliases { + mmc0 = &usdhc3; + usb0 = &usbotg1; + display0 = &lcdif; + }; }; &usbotg1 { -- cgit v1.3.1 From 50c67ddbe4a6a3f7a2afe14152e0fc5561435dac Mon Sep 17 00:00:00 2001 From: Hiago De Franco Date: Thu, 9 Nov 2023 13:24:00 -0300 Subject: apalis/colibri imx6/imx6ull/imx7: defconfig: Enable fastboot support Add fastboot support for Apalis iMX6, Colibri iMX6, Colibri iMX6ULL and Colibri iMX7 boards. Remove CONFIG_FASTBOOT_BUF_SIZE from colibri_imx7_emmc_defconfig to get the default value of 0x7000000 instead of 0x10000000, to make it consistent with the other boards. Signed-off-by: Hiago De Franco Reviewed-by: Fabio Estevam --- configs/apalis_imx6_defconfig | 3 +++ configs/colibri-imx6ull-emmc_defconfig | 3 +++ configs/colibri-imx6ull_defconfig | 3 +++ configs/colibri_imx6_defconfig | 3 +++ configs/colibri_imx7_defconfig | 3 +++ configs/colibri_imx7_emmc_defconfig | 4 ++-- 6 files changed, 17 insertions(+), 2 deletions(-) diff --git a/configs/apalis_imx6_defconfig b/configs/apalis_imx6_defconfig index cf2af5797f3..4a27738eb70 100644 --- a/configs/apalis_imx6_defconfig +++ b/configs/apalis_imx6_defconfig @@ -88,6 +88,9 @@ CONFIG_DWC_AHSATA=y CONFIG_LBA48=y CONFIG_BOOTCOUNT_LIMIT=y CONFIG_BOOTCOUNT_ENV=y +CONFIG_USB_FUNCTION_FASTBOOT=y +CONFIG_FASTBOOT_BUF_ADDR=0x14420000 +CONFIG_FASTBOOT_UUU_SUPPORT=y CONFIG_DM_I2C=y CONFIG_SPL_SYS_I2C_LEGACY=y CONFIG_SYS_I2C_MXC=y diff --git a/configs/colibri-imx6ull-emmc_defconfig b/configs/colibri-imx6ull-emmc_defconfig index 2fead59f5f2..20cba723ee0 100644 --- a/configs/colibri-imx6ull-emmc_defconfig +++ b/configs/colibri-imx6ull-emmc_defconfig @@ -64,6 +64,9 @@ CONFIG_SERVERIP="192.168.10.1" CONFIG_BOUNCE_BUFFER=y CONFIG_BOOTCOUNT_LIMIT=y CONFIG_BOOTCOUNT_ENV=y +CONFIG_USB_FUNCTION_FASTBOOT=y +CONFIG_FASTBOOT_BUF_ADDR=0x81100000 +CONFIG_FASTBOOT_UUU_SUPPORT=y CONFIG_DM_I2C=y CONFIG_SYS_I2C_MXC=y CONFIG_SUPPORT_EMMC_BOOT=y diff --git a/configs/colibri-imx6ull_defconfig b/configs/colibri-imx6ull_defconfig index 5164374c67f..d904621f5e2 100644 --- a/configs/colibri-imx6ull_defconfig +++ b/configs/colibri-imx6ull_defconfig @@ -75,6 +75,9 @@ CONFIG_BOOTCOUNT_LIMIT=y CONFIG_BOOTCOUNT_ENV=y CONFIG_DFU_NAND=y CONFIG_SYS_DFU_DATA_BUF_SIZE=0x1000000 +CONFIG_USB_FUNCTION_FASTBOOT=y +CONFIG_FASTBOOT_BUF_ADDR=0x81100000 +CONFIG_FASTBOOT_UUU_SUPPORT=y CONFIG_DM_I2C=y CONFIG_SYS_I2C_MXC=y CONFIG_FSL_USDHC=y diff --git a/configs/colibri_imx6_defconfig b/configs/colibri_imx6_defconfig index 51f3eeca754..cd68264eca1 100644 --- a/configs/colibri_imx6_defconfig +++ b/configs/colibri_imx6_defconfig @@ -85,6 +85,9 @@ CONFIG_SERVERIP="192.168.10.1" CONFIG_BOUNCE_BUFFER=y CONFIG_BOOTCOUNT_LIMIT=y CONFIG_BOOTCOUNT_ENV=y +CONFIG_USB_FUNCTION_FASTBOOT=y +CONFIG_FASTBOOT_BUF_ADDR=0x14420000 +CONFIG_FASTBOOT_UUU_SUPPORT=y CONFIG_DM_I2C=y CONFIG_SPL_SYS_I2C_LEGACY=y CONFIG_SYS_I2C_MXC=y diff --git a/configs/colibri_imx7_defconfig b/configs/colibri_imx7_defconfig index eba2b41c842..e24a606bc45 100644 --- a/configs/colibri_imx7_defconfig +++ b/configs/colibri_imx7_defconfig @@ -72,6 +72,9 @@ CONFIG_BOUNCE_BUFFER=y CONFIG_BOOTCOUNT_LIMIT=y CONFIG_BOOTCOUNT_ENV=y CONFIG_DFU_NAND=y +CONFIG_USB_FUNCTION_FASTBOOT=y +CONFIG_FASTBOOT_BUF_ADDR=0x81100000 +CONFIG_FASTBOOT_UUU_SUPPORT=y CONFIG_DM_I2C=y CONFIG_SYS_I2C_MXC=y CONFIG_FSL_USDHC=y diff --git a/configs/colibri_imx7_emmc_defconfig b/configs/colibri_imx7_emmc_defconfig index 49a51e9272f..687dbb5e3e7 100644 --- a/configs/colibri_imx7_emmc_defconfig +++ b/configs/colibri_imx7_emmc_defconfig @@ -62,9 +62,9 @@ CONFIG_SERVERIP="192.168.10.1" CONFIG_BOOTCOUNT_LIMIT=y CONFIG_BOOTCOUNT_ENV=y CONFIG_USB_FUNCTION_FASTBOOT=y -CONFIG_FASTBOOT_BUF_ADDR=0x82000000 -CONFIG_FASTBOOT_BUF_SIZE=0x10000000 +CONFIG_FASTBOOT_BUF_ADDR=0x81100000 CONFIG_FASTBOOT_FLASH=y +CONFIG_FASTBOOT_UUU_SUPPORT=y CONFIG_FASTBOOT_FLASH_MMC_DEV=0 CONFIG_FASTBOOT_CMD_OEM_FORMAT=y CONFIG_DM_I2C=y -- cgit v1.3.1 From 220bb4e15086f9cc7a43a5726fde1919f65c8277 Mon Sep 17 00:00:00 2001 From: Hiago De Franco Date: Thu, 9 Nov 2023 13:24:01 -0300 Subject: board: apalis/colibri imx6/imx6ull/imx7: Add fastboot bootcmd support This commit adds support for Fastboot boot commands by checking both CONFIG_CMD_USB_SDP and CONFIG_USB_FUNCTION_FASTBOOT. If either of these configurations is set, it indicates that the board is in recovery mode and can use either SDP or Fastboot. The default option remains the SDP command, but if CONFIG_CMD_FASTBOOT is set, it changes to 'fastboot usb 0' as the boot command. Signed-off-by: Hiago De Franco Reviewed-by: Fabio Estevam --- board/toradex/apalis_imx6/apalis_imx6.c | 13 ++++++++----- board/toradex/colibri-imx6ull/colibri-imx6ull.c | 13 ++++++++----- board/toradex/colibri_imx6/colibri_imx6.c | 13 ++++++++----- board/toradex/colibri_imx7/colibri_imx7.c | 14 +++++++++----- 4 files changed, 33 insertions(+), 20 deletions(-) diff --git a/board/toradex/apalis_imx6/apalis_imx6.c b/board/toradex/apalis_imx6/apalis_imx6.c index dc0e09991dd..164fcc41f55 100644 --- a/board/toradex/apalis_imx6/apalis_imx6.c +++ b/board/toradex/apalis_imx6/apalis_imx6.c @@ -701,13 +701,16 @@ int board_late_init(void) env_set("board_rev", env_str); #endif /* CONFIG_BOARD_LATE_INIT */ -#ifdef CONFIG_CMD_USB_SDP - if (is_boot_from_usb()) { - printf("Serial Downloader recovery mode, using sdp command\n"); + if (IS_ENABLED(CONFIG_USB) && is_boot_from_usb()) { env_set("bootdelay", "0"); - env_set("bootcmd", "sdp 0"); + if (IS_ENABLED(CONFIG_CMD_USB_SDP)) { + printf("Serial Downloader recovery mode, using sdp command\n"); + env_set("bootcmd", "sdp 0"); + } else if (IS_ENABLED(CONFIG_CMD_FASTBOOT)) { + printf("Fastboot recovery mode, using fastboot command\n"); + env_set("bootcmd", "fastboot usb 0"); + } } -#endif /* CONFIG_CMD_USB_SDP */ return 0; } diff --git a/board/toradex/colibri-imx6ull/colibri-imx6ull.c b/board/toradex/colibri-imx6ull/colibri-imx6ull.c index 6c8eeff38fa..a775f54eb3f 100644 --- a/board/toradex/colibri-imx6ull/colibri-imx6ull.c +++ b/board/toradex/colibri-imx6ull/colibri-imx6ull.c @@ -187,13 +187,16 @@ int board_late_init(void) add_board_boot_modes(board_boot_modes); #endif -#ifdef CONFIG_CMD_USB_SDP - if (is_boot_from_usb()) { - printf("Serial Downloader recovery mode, using sdp command\n"); + if (IS_ENABLED(CONFIG_USB) && is_boot_from_usb()) { env_set("bootdelay", "0"); - env_set("bootcmd", "sdp 0"); + if (IS_ENABLED(CONFIG_CMD_USB_SDP)) { + printf("Serial Downloader recovery mode, using sdp command\n"); + env_set("bootcmd", "sdp 0"); + } else if (IS_ENABLED(CONFIG_CMD_FASTBOOT)) { + printf("Fastboot recovery mode, using fastboot command\n"); + env_set("bootcmd", "fastboot usb 0"); + } } -#endif /* CONFIG_CMD_USB_SDP */ #if defined(CONFIG_VIDEO) setup_lcd(); diff --git a/board/toradex/colibri_imx6/colibri_imx6.c b/board/toradex/colibri_imx6/colibri_imx6.c index 7635c5811d2..784ca7f65f7 100644 --- a/board/toradex/colibri_imx6/colibri_imx6.c +++ b/board/toradex/colibri_imx6/colibri_imx6.c @@ -621,13 +621,16 @@ int board_late_init(void) env_set("board_rev", env_str); #endif -#ifdef CONFIG_CMD_USB_SDP - if (is_boot_from_usb()) { - printf("Serial Downloader recovery mode, using sdp command\n"); + if (IS_ENABLED(CONFIG_USB) && is_boot_from_usb()) { env_set("bootdelay", "0"); - env_set("bootcmd", "sdp 0"); + if (IS_ENABLED(CONFIG_CMD_USB_SDP)) { + printf("Serial Downloader recovery mode, using sdp command\n"); + env_set("bootcmd", "sdp 0"); + } else if (IS_ENABLED(CONFIG_CMD_FASTBOOT)) { + printf("Fastboot recovery mode, using fastboot command\n"); + env_set("bootcmd", "fastboot usb 0"); + } } -#endif /* CONFIG_CMD_USB_SDP */ return 0; } diff --git a/board/toradex/colibri_imx7/colibri_imx7.c b/board/toradex/colibri_imx7/colibri_imx7.c index c3478b15111..e23f9af20da 100644 --- a/board/toradex/colibri_imx7/colibri_imx7.c +++ b/board/toradex/colibri_imx7/colibri_imx7.c @@ -360,13 +360,17 @@ int board_late_init(void) setup_lcd(); #endif -#if defined(CONFIG_CMD_USB_SDP) - if (is_boot_from_usb()) { - printf("Serial Downloader recovery mode, using sdp command\n"); + if (IS_ENABLED(CONFIG_USB) && is_boot_from_usb()) { env_set("bootdelay", "0"); - env_set("bootcmd", "sdp 0"); + if (IS_ENABLED(CONFIG_CMD_USB_SDP)) { + printf("Serial Downloader recovery mode, using sdp command\n"); + env_set("bootcmd", "sdp 0"); + } else if (IS_ENABLED(CONFIG_CMD_FASTBOOT)) { + printf("Fastboot recovery mode, using fastboot command\n"); + env_set("bootcmd", "fastboot usb 0"); + } } -#endif + if (is_emmc) env_set("variant", "-emmc"); else -- cgit v1.3.1 From cb1d68b143afb1129f84c8e3971785e27949fc6b Mon Sep 17 00:00:00 2001 From: Nicolas Heemeryck Date: Mon, 11 Dec 2023 11:06:13 +0100 Subject: clk: imx8mn: add pwm clocks Based on Linux kernel 6.7-rc4, add necessary clocks for the PWM controllers. Signed-off-by: Nicolas Heemeryck Reviewed-by: Fabio Estevam --- drivers/clk/imx/clk-imx8mn.c | 30 ++++++++++++++++++++++++++++++ 1 file changed, 30 insertions(+) diff --git a/drivers/clk/imx/clk-imx8mn.c b/drivers/clk/imx/clk-imx8mn.c index 692823e74b8..457acb8a401 100644 --- a/drivers/clk/imx/clk-imx8mn.c +++ b/drivers/clk/imx/clk-imx8mn.c @@ -83,6 +83,20 @@ static const char *imx8mn_i2c3_sels[] = {"clock-osc-24m", "sys_pll1_160m", "sys_ static const char *imx8mn_i2c4_sels[] = {"clock-osc-24m", "sys_pll1_160m", "sys_pll2_50m", "sys_pll3_out", "audio_pll1_out", "video_pll_out", "audio_pll2_out", "sys_pll1_133m", }; +#ifndef CONFIG_SPL_BUILD +static const char *imx8mn_pwm1_sels[] = {"clock-osc-24m", "sys_pll2_100m", "sys_pll1_160m", "sys_pll1_40m", + "sys_pll3_out", "clk_ext1", "sys_pll1_80m", "video_pll_out", }; + +static const char *imx8mn_pwm2_sels[] = {"clock-osc-24m", "sys_pll2_100m", "sys_pll1_160m", "sys_pll1_40m", + "sys_pll3_out", "clk_ext1", "sys_pll1_80m", "video_pll_out", }; + +static const char *imx8mn_pwm3_sels[] = {"clock-osc-24m", "sys_pll2_100m", "sys_pll1_160m", "sys_pll1_40m", + "sys_pll3_out", "clk_ext2", "sys_pll1_80m", "video_pll_out", }; + +static const char *imx8mn_pwm4_sels[] = {"clock-osc-24m", "sys_pll2_100m", "sys_pll1_160m", "sys_pll1_40m", + "sys_pll3_out", "clk_ext2", "sys_pll1_80m", "video_pll_out", }; +#endif + static const char *imx8mn_wdog_sels[] = {"clock-osc-24m", "sys_pll1_133m", "sys_pll1_160m", "m7_alt_pll", "sys_pll2_125m", "sys_pll3_out", "sys_pll1_80m", "sys_pll2_166m", }; @@ -330,6 +344,22 @@ static int imx8mn_clk_probe(struct udevice *dev) clk_dm(IMX8MN_CLK_ENET1_ROOT, imx_clk_gate4("enet1_root_clk", "enet_axi", base + 0x40a0, 0)); + clk_dm(IMX8MN_CLK_PWM1, + imx8m_clk_composite("pwm1", imx8mn_pwm1_sels, base + 0xb380)); + clk_dm(IMX8MN_CLK_PWM2, + imx8m_clk_composite("pwm2", imx8mn_pwm2_sels, base + 0xb400)); + clk_dm(IMX8MN_CLK_PWM3, + imx8m_clk_composite("pwm3", imx8mn_pwm3_sels, base + 0xb480)); + clk_dm(IMX8MN_CLK_PWM4, + imx8m_clk_composite("pwm4", imx8mn_pwm4_sels, base + 0xb500)); + clk_dm(IMX8MN_CLK_PWM1_ROOT, + imx_clk_gate4("pwm1_root_clk", "pwm1", base + 0x4280, 0)); + clk_dm(IMX8MN_CLK_PWM2_ROOT, + imx_clk_gate4("pwm2_root_clk", "pwm2", base + 0x4290, 0)); + clk_dm(IMX8MN_CLK_PWM3_ROOT, + imx_clk_gate4("pwm3_root_clk", "pwm3", base + 0x42a0, 0)); + clk_dm(IMX8MN_CLK_PWM4_ROOT, + imx_clk_gate4("pwm4_root_clk", "pwm4", base + 0x42b0, 0)); #endif #if CONFIG_IS_ENABLED(DM_SPI) -- cgit v1.3.1 From 712aa6e24cd624e60d49e520837dab4a7e44faa0 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Wed, 18 Oct 2023 20:51:59 +0200 Subject: arm: mxs: Clear CPSR V bit to activate low vectors The MXS starts with CPSR V bit set, which makes the CPU jump to high vectors in case of an exception. Those high vectors are located at 0xffff0000, which is where the BootROM exception table is located as well. U-Boot should handle exceptions on its own using its own exception handling code, which is located at 0x0, i.e. at low vectors. Clear the CPSR V bit, so that the CPU would jump to low vectors on exception instead, and therefore run the U-Boot exception handling code. Signed-off-by: Marek Vasut Reviewed-by: Fabio Estevam --- arch/arm/cpu/arm926ejs/mxs/mxs.c | 4 ++++ arch/arm/cpu/arm926ejs/mxs/spl_boot.c | 8 +++++++- 2 files changed, 11 insertions(+), 1 deletion(-) diff --git a/arch/arm/cpu/arm926ejs/mxs/mxs.c b/arch/arm/cpu/arm926ejs/mxs/mxs.c index 6d6166cb839..4f3cb63c56d 100644 --- a/arch/arm/cpu/arm926ejs/mxs/mxs.c +++ b/arch/arm/cpu/arm926ejs/mxs/mxs.c @@ -71,6 +71,7 @@ void reset_cpu(void) * actually 0x20, this the associated . Loading the PC * register with an address performs a jump to that address. */ +noinline __attribute__((target("arm"))) void mx28_fixup_vt(uint32_t start_addr) { /* ldr pc, [pc, #0x18] */ @@ -85,6 +86,9 @@ void mx28_fixup_vt(uint32_t start_addr) /* cppcheck-suppress nullPointer */ vt[i + 8] = start_addr + (4 * i); } + + /* Make sure ARM core points to low vectors */ + set_cr(get_cr() & ~CR_V); } #ifdef CONFIG_ARCH_MISC_INIT diff --git a/arch/arm/cpu/arm926ejs/mxs/spl_boot.c b/arch/arm/cpu/arm926ejs/mxs/spl_boot.c index 5e7bdb78be1..249f8de8fbe 100644 --- a/arch/arm/cpu/arm926ejs/mxs/spl_boot.c +++ b/arch/arm/cpu/arm926ejs/mxs/spl_boot.c @@ -17,6 +17,7 @@ #include #include #include +#include #include #include "mxs_init.h" @@ -93,7 +94,9 @@ static uint8_t mxs_get_bootmode_index(void) return i; } -static void mxs_spl_fixup_vectors(void) +static noinline +__attribute__((target("arm"))) +void mxs_spl_fixup_vectors(void) { /* * Copy our vector table to 0x0, since due to HAB, we cannot @@ -104,6 +107,9 @@ static void mxs_spl_fixup_vectors(void) /* cppcheck-suppress nullPointer */ memcpy(0x0, _start, 0x60); + + /* Make sure ARM core points to low vectors */ + set_cr(get_cr() & ~CR_V); } static void mxs_spl_console_init(void) -- cgit v1.3.1 From 4ac5620270ddc5b31cf8600ffa5990be197597c9 Mon Sep 17 00:00:00 2001 From: Alessandro Rubini Date: Sun, 3 Dec 2023 18:08:26 +0100 Subject: tools: mxsboot: pre-fill buffer with 0xff, not 0 The tool works for me, with imx28 and NAND memory, but the resulting blocks are reported as bad, both by u-boot and the kernel. This makes it impossible to erase from Linux (for an upgrade without console access, for example -- u-boot can "nand scrub" but linux can't). pre-filling with 0xff creates a proper boot loader image, but no bad-block marker is there when written to flash. Signed-off-by: Alessandro Rubini Reviewed-by: Fabio Estevam Reviewed-by: Marek Vasut --- tools/mxsboot.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/tools/mxsboot.c b/tools/mxsboot.c index 04d86f87a86..8f4018aa560 100644 --- a/tools/mxsboot.c +++ b/tools/mxsboot.c @@ -478,7 +478,7 @@ static int mx28_create_nand_image(int infd, int outfd) goto err0; } - memset(buf, 0, size); + memset(buf, 0xff, size); fcb = mx28_nand_get_fcb(MAX_BOOTSTREAM_SIZE); if (!fcb) { -- cgit v1.3.1 From 04bb59b4083147ad164594048258961c30089a64 Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Mon, 11 Dec 2023 10:46:17 -0300 Subject: imx: imx-hab: Select SPL_DRIVERS_MISC in the SPL case MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Selecting CONFIG_IMX_HAB=y on a SPL target, such as apalis_imx6_defconfig, for example, leads to the following build error: /usr/bin/arm-linux-gnueabihf-ld.bfd: arch/arm/mach-imx/hab.o: in function `imx_hab_is_enabled': arch/arm/mach-imx/hab.c:879: undefined reference to `fuse_read' fuse_read() comes from SPL_MXC_OCOTP, which depends on SPL_DRIVERS_MISC, since commit 251a3053b1e6 ("misc: imx: remove DM dependency for ocotp driver in SPL"). Select SPL_DRIVERS_MISC in the SPL case to fix this build issue. Reported-by: Lisandro Pérez Meyer Signed-off-by: Fabio Estevam Tested-by: Lisandro Pérez Meyer --- arch/arm/mach-imx/Kconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/mach-imx/Kconfig b/arch/arm/mach-imx/Kconfig index abd48d42583..c34bc25c0bf 100644 --- a/arch/arm/mach-imx/Kconfig +++ b/arch/arm/mach-imx/Kconfig @@ -54,6 +54,7 @@ config IMX_HAB bool "Support i.MX HAB features" depends on ARCH_MX7 || ARCH_MX6 || ARCH_MX5 || ARCH_IMX8M || ARCH_MX7ULP select FSL_CAAM if HAS_CAAM + select SPL_DRIVERS_MISC if SPL imply CMD_DEKBLOB if HAS_CAAM help This option enables the support for secure boot (HAB). -- cgit v1.3.1 From 03622f301265f4797e55bc01a603f1b6d3b5a856 Mon Sep 17 00:00:00 2001 From: Benjamin Szőke Date: Wed, 13 Dec 2023 15:51:49 -0300 Subject: pico-imx7d: add baseboard SD card boot detect MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Technexion PICO-IMX7 SoM is supporting USDHC3 (eMMC or micro SD on SoM) and USDHC1 (SD on carrier board) to use on any carrier board like PICO-NYMPH. Based on the U-Boot version from Technexion it adds baseboard SD card boot detect to able to boot from selected USDHC1 or USDHC3 boot devices. Signed-off-by: Benjamin Szőke Tested-by: Fabio Estevam --- arch/arm/dts/imx7d-pico-pi-u-boot.dtsi | 1 + board/technexion/pico-imx7d/Makefile | 2 +- board/technexion/pico-imx7d/pico-imx7d.c | 62 ++++++++++++++++++++++ board/technexion/pico-imx7d/spl.c | 91 +++++++++++++++++++++++++++++--- include/configs/pico-imx7d.h | 4 +- 5 files changed, 151 insertions(+), 9 deletions(-) diff --git a/arch/arm/dts/imx7d-pico-pi-u-boot.dtsi b/arch/arm/dts/imx7d-pico-pi-u-boot.dtsi index 3a6294daff3..3dd01e36a4a 100644 --- a/arch/arm/dts/imx7d-pico-pi-u-boot.dtsi +++ b/arch/arm/dts/imx7d-pico-pi-u-boot.dtsi @@ -3,6 +3,7 @@ /{ aliases { mmc0 = &usdhc3; + mmc1 = &usdhc1; usb0 = &usbotg1; display0 = &lcdif; }; diff --git a/board/technexion/pico-imx7d/Makefile b/board/technexion/pico-imx7d/Makefile index 4ae3d606b58..61b55fcc55a 100644 --- a/board/technexion/pico-imx7d/Makefile +++ b/board/technexion/pico-imx7d/Makefile @@ -1,4 +1,4 @@ # SPDX-License-Identifier: GPL-2.0+ # (C) Copyright 2017 NXP Semiconductors -obj-y := pico-imx7d.o spl.o +obj-y := pico-imx7d.o spl.o ../../freescale/common/mmc.o diff --git a/board/technexion/pico-imx7d/pico-imx7d.c b/board/technexion/pico-imx7d/pico-imx7d.c index 5def6eda43e..b12941ccf82 100644 --- a/board/technexion/pico-imx7d/pico-imx7d.c +++ b/board/technexion/pico-imx7d/pico-imx7d.c @@ -13,6 +13,7 @@ #include #include #include +#include #include #include #include @@ -25,6 +26,11 @@ DECLARE_GLOBAL_DATA_PTR; #define UART_PAD_CTRL (PAD_CTL_DSE_3P3V_49OHM | \ PAD_CTL_PUS_PU100KOHM | PAD_CTL_HYS) +#define PICO_MMC0 0 +#define PICO_MMC0_BLK 2 +#define PICO_MMC1 1 +#define PICO_MMC1_BLK 0 + int dram_init(void) { gd->ram_size = imx_ddr_size(); @@ -150,6 +156,12 @@ int board_late_init(void) set_wdog_reset(wdog); +#if CONFIG_IS_ENABLED(FSL_ESDHC_IMX) +#if CONFIG_IS_ENABLED(ENV_IS_IN_MMC) || CONFIG_IS_ENABLED(ENV_IS_NOWHERE) + board_late_mmc_env_init(); +#endif /* CONFIG_ENV_IS_IN_MMC or CONFIG_ENV_IS_NOWHERE */ +#endif + /* * Do not assert internal WDOG_RESET_B_DEB(controlled by bit 4), * since we use PMIC_PWRON to reset the board. @@ -184,3 +196,53 @@ int board_ehci_hcd_init(int port) } return 0; } + +#if CONFIG_IS_ENABLED(FSL_ESDHC_IMX) +#if CONFIG_IS_ENABLED(ENV_IS_IN_MMC) || CONFIG_IS_ENABLED(ENV_IS_NOWHERE) +int board_mmc_get_env_dev(int devno) +{ + int dev_env = 0; + + switch (get_boot_device()) { + case SD3_BOOT: + case MMC3_BOOT: + env_set("bootdev", "MMC3"); + dev_env = PICO_MMC0; + break; + case SD1_BOOT: + env_set("bootdev", "SD1"); + dev_env = PICO_MMC1; + break; + default: + printf("Wrong boot device!"); + } + + return dev_env; +} + +int mmc_map_to_kernel_blk(int dev_no) +{ + int blk_no = 0; + + switch (dev_no) { + case PICO_MMC0: + blk_no = PICO_MMC0_BLK; + break; + case PICO_MMC1: + blk_no = PICO_MMC1_BLK; + break; + default: + printf("Invalid MMC device!"); + } + + return blk_no; +} +#endif + +#if CONFIG_IS_ENABLED(ENV_IS_NOWHERE) +int mmc_get_env_dev(void) +{ + return board_mmc_get_env_dev(0); +} +#endif +#endif /* CONFIG_FSL_ESDHC_IMX */ diff --git a/board/technexion/pico-imx7d/spl.c b/board/technexion/pico-imx7d/spl.c index c6b21aaa42d..0192eafbaa1 100644 --- a/board/technexion/pico-imx7d/spl.c +++ b/board/technexion/pico-imx7d/spl.c @@ -15,6 +15,7 @@ #include #include #include +#include #include #include #include @@ -159,7 +160,20 @@ void reset_cpu(void) #define USDHC_PAD_CTRL (PAD_CTL_DSE_3P3V_32OHM | PAD_CTL_SRE_SLOW | \ PAD_CTL_HYS | PAD_CTL_PUE | PAD_CTL_PUS_PU47KOHM) -static iomux_v3_cfg_t const usdhc3_pads[] = { +#define USDHC1_CD_GPIO IMX_GPIO_NR(5, 0) +/* EMMC/SD */ +static const iomux_v3_cfg_t usdhc1_pads[] = { + MX7D_PAD_SD1_CLK__SD1_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX7D_PAD_SD1_CMD__SD1_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX7D_PAD_SD1_DATA0__SD1_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX7D_PAD_SD1_DATA1__SD1_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX7D_PAD_SD1_DATA2__SD1_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX7D_PAD_SD1_DATA3__SD1_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX7D_PAD_SD1_CD_B__GPIO5_IO0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), +}; + +#define USDHC3_CD_GPIO IMX_GPIO_NR(1, 14) +static const iomux_v3_cfg_t usdhc3_emmc_pads[] = { MX7D_PAD_SD3_CLK__SD3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), MX7D_PAD_SD3_CMD__SD3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), MX7D_PAD_SD3_DATA0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), @@ -173,20 +187,83 @@ static iomux_v3_cfg_t const usdhc3_pads[] = { MX7D_PAD_GPIO1_IO14__GPIO1_IO14 | MUX_PAD_CTRL(USDHC_PAD_CTRL), }; -static struct fsl_esdhc_cfg usdhc_cfg[1] = { +static struct fsl_esdhc_cfg usdhc_cfg[2] = { {USDHC3_BASE_ADDR}, + {USDHC1_BASE_ADDR}, }; int board_mmc_getcd(struct mmc *mmc) { - /* Assume uSDHC3 emmc is always present */ - return 1; + struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv; + int ret = 0; + + switch (cfg->esdhc_base) { + case USDHC1_BASE_ADDR: + ret = !gpio_get_value(USDHC1_CD_GPIO); + break; + case USDHC3_BASE_ADDR: + ret = !gpio_get_value(USDHC3_CD_GPIO); + break; + } + + return ret; } int board_mmc_init(struct bd_info *bis) { - imx_iomux_v3_setup_multiple_pads(usdhc3_pads, ARRAY_SIZE(usdhc3_pads)); - usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK); - return fsl_esdhc_initialize(bis, &usdhc_cfg[0]); + int ret; + u32 index; + + /* + * Following map is done: + * (USDHC) (Physical Port) + * usdhc3 SOM MicroSD/MMC + * usdhc1 Carrier board MicroSD + * Always set boot USDHC as mmc0 + */ + + imx_iomux_v3_setup_multiple_pads(usdhc3_emmc_pads, + ARRAY_SIZE(usdhc3_emmc_pads)); + gpio_direction_input(USDHC3_CD_GPIO); + + imx_iomux_v3_setup_multiple_pads(usdhc1_pads, + ARRAY_SIZE(usdhc1_pads)); + gpio_direction_input(USDHC1_CD_GPIO); + + switch (get_boot_device()) { + case SD1_BOOT: + usdhc_cfg[0].esdhc_base = USDHC1_BASE_ADDR; + usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK); + usdhc_cfg[0].max_bus_width = 4; + usdhc_cfg[1].esdhc_base = USDHC3_BASE_ADDR; + usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK); + usdhc_cfg[1].max_bus_width = 4; + break; + case MMC3_BOOT: + usdhc_cfg[0].esdhc_base = USDHC3_BASE_ADDR; + usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK); + usdhc_cfg[0].max_bus_width = 8; + usdhc_cfg[1].esdhc_base = USDHC1_BASE_ADDR; + usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK); + usdhc_cfg[1].max_bus_width = 4; + break; + case SD3_BOOT: + default: + usdhc_cfg[0].esdhc_base = USDHC3_BASE_ADDR; + usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK); + usdhc_cfg[0].max_bus_width = 4; + usdhc_cfg[1].esdhc_base = USDHC1_BASE_ADDR; + usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK); + usdhc_cfg[1].max_bus_width = 4; + break; + } + + for (index = 0; index < CFG_SYS_FSL_USDHC_NUM; ++index) { + ret = fsl_esdhc_initialize(bis, &usdhc_cfg[index]); + if (ret) + return ret; + } + + return 0; } #endif diff --git a/include/configs/pico-imx7d.h b/include/configs/pico-imx7d.h index 096e5bbe663..e7a8cb20dff 100644 --- a/include/configs/pico-imx7d.h +++ b/include/configs/pico-imx7d.h @@ -13,7 +13,7 @@ #define CFG_MXC_UART_BASE UART5_IPS_BASE_ADDR /* MMC Config */ -#define CFG_SYS_FSL_ESDHC_ADDR 0 +#define CFG_SYS_FSL_ESDHC_ADDR USDHC3_BASE_ADDR #define CFG_DFU_ENV_SETTINGS \ "dfu_alt_info=" \ @@ -79,9 +79,11 @@ "name=rootfs,size=0,uuid=${uuid_gpt_rootfs}\0" \ "fastboot_partition_alias_system=rootfs\0" \ "setup_emmc=mmc dev 0; gpt write mmc 0 $partitions; reset;\0" \ + "mmcautodetect=yes\0" \ PICO_BOOT_ENV #define BOOT_TARGET_DEVICES(func) \ + func(MMC, mmc, 1) \ func(MMC, mmc, 0) \ func(USB, usb, 0) \ func(PXE, pxe, na) \ -- cgit v1.3.1 From 0d1186991ee4ec5f9d442bb87c7a8916a8b8f071 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Sat, 4 Nov 2023 17:32:20 +0100 Subject: arm: imx6: Enable TCP, IPv6, wget on DH i.MX6 DHCOM Enable support for TCP protocol, wget, and IPv6 on this platform. The former two allow users download payload into the U-Boot from a web server, which may be more convenient or easier to set up than TFTP server. The later is enabled to future proof the IP stack on this platform. Signed-off-by: Marek Vasut Reviewed-by: Fabio Estevam --- configs/dh_imx6_defconfig | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/configs/dh_imx6_defconfig b/configs/dh_imx6_defconfig index 154131e62e0..071898b1e39 100644 --- a/configs/dh_imx6_defconfig +++ b/configs/dh_imx6_defconfig @@ -56,6 +56,9 @@ CONFIG_CMD_SATA=y CONFIG_CMD_USB=y CONFIG_CMD_USB_MASS_STORAGE=y CONFIG_CMD_WDT=y +CONFIG_CMD_DHCP6=y +CONFIG_CMD_TFTPPUT=y +CONFIG_CMD_WGET=y CONFIG_CMD_BOOTCOUNT=y CONFIG_CMD_CACHE=y CONFIG_CMD_TIME=y @@ -72,6 +75,10 @@ CONFIG_USE_ETHPRIME=y CONFIG_ETHPRIME="FEC" CONFIG_VERSION_VARIABLE=y CONFIG_ARP_TIMEOUT=200 +CONFIG_IP_DEFRAG=y +CONFIG_TFTP_TSIZE=y +CONFIG_PROT_TCP_SACK=y +CONFIG_IPV6=y CONFIG_BOUNCE_BUFFER=y CONFIG_DWC_AHSATA=y CONFIG_LBA48=y -- cgit v1.3.1 From 91613b1539d2004a7873413d3c13aa2ce3fc4d33 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Sat, 4 Nov 2023 17:32:21 +0100 Subject: arm64: imx8mp: Enable TCP, IPv6, wget on DH i.MX8MP DHCOM Enable support for TCP protocol, wget, and IPv6 on this platform. The former two allow users download payload into the U-Boot from a web server, which may be more convenient or easier to set up than TFTP server. The later is enabled to future proof the IP stack on this platform. Signed-off-by: Marek Vasut Reviewed-by: Fabio Estevam --- configs/imx8mp_dhcom_pdk2_defconfig | 5 +++++ configs/imx8mp_dhcom_pdk3_defconfig | 5 +++++ 2 files changed, 10 insertions(+) diff --git a/configs/imx8mp_dhcom_pdk2_defconfig b/configs/imx8mp_dhcom_pdk2_defconfig index a77139ab06a..54c02dfd7ab 100644 --- a/configs/imx8mp_dhcom_pdk2_defconfig +++ b/configs/imx8mp_dhcom_pdk2_defconfig @@ -109,6 +109,9 @@ CONFIG_CMD_USB=y CONFIG_CMD_USB_SDP=y CONFIG_CMD_USB_MASS_STORAGE=y CONFIG_CMD_DHCP=y +CONFIG_CMD_DHCP6=y +CONFIG_CMD_TFTPPUT=y +CONFIG_CMD_WGET=y CONFIG_CMD_MII=y CONFIG_CMD_PING=y CONFIG_CMD_PXE=y @@ -151,6 +154,8 @@ CONFIG_NET_RANDOM_ETHADDR=y CONFIG_NETCONSOLE=y CONFIG_IP_DEFRAG=y CONFIG_TFTP_TSIZE=y +CONFIG_PROT_TCP_SACK=y +CONFIG_IPV6=y CONFIG_SPL_DM=y CONFIG_REGMAP=y CONFIG_SYSCON=y diff --git a/configs/imx8mp_dhcom_pdk3_defconfig b/configs/imx8mp_dhcom_pdk3_defconfig index c1f8fbd3ec3..6799f0c8b73 100644 --- a/configs/imx8mp_dhcom_pdk3_defconfig +++ b/configs/imx8mp_dhcom_pdk3_defconfig @@ -111,6 +111,9 @@ CONFIG_CMD_USB=y CONFIG_CMD_USB_SDP=y CONFIG_CMD_USB_MASS_STORAGE=y CONFIG_CMD_DHCP=y +CONFIG_CMD_DHCP6=y +CONFIG_CMD_TFTPPUT=y +CONFIG_CMD_WGET=y CONFIG_CMD_MII=y CONFIG_CMD_PING=y CONFIG_CMD_PXE=y @@ -153,6 +156,8 @@ CONFIG_NET_RANDOM_ETHADDR=y CONFIG_NETCONSOLE=y CONFIG_IP_DEFRAG=y CONFIG_TFTP_TSIZE=y +CONFIG_PROT_TCP_SACK=y +CONFIG_IPV6=y CONFIG_SPL_DM=y CONFIG_REGMAP=y CONFIG_SYSCON=y -- cgit v1.3.1 From 6b73200aedb1d3fb0a52e2600bd6b1e3ff5e5faf Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Thu, 23 Nov 2023 00:37:38 +0100 Subject: arm64: imx8mp: Enable TCP, IPv6, wget on Data Modul i.MX8M eDM SBC Enable support for TCP protocol, wget, and IPv6 on this platform. The former two allow users download payload into the U-Boot from a web server, which may be more convenient or easier to set up than TFTP server. The later is enabled to future proof the IP stack on this platform. Signed-off-by: Marek Vasut Reviewed-by: Fabio Estevam --- configs/imx8mm_data_modul_edm_sbc_defconfig | 5 +++++ configs/imx8mp_data_modul_edm_sbc_defconfig | 5 +++++ 2 files changed, 10 insertions(+) diff --git a/configs/imx8mm_data_modul_edm_sbc_defconfig b/configs/imx8mm_data_modul_edm_sbc_defconfig index e724607c6ee..20a38a38280 100644 --- a/configs/imx8mm_data_modul_edm_sbc_defconfig +++ b/configs/imx8mm_data_modul_edm_sbc_defconfig @@ -108,6 +108,9 @@ CONFIG_CMD_USB=y CONFIG_CMD_USB_SDP=y CONFIG_CMD_USB_MASS_STORAGE=y CONFIG_CMD_DHCP=y +CONFIG_CMD_DHCP6=y +CONFIG_CMD_TFTPPUT=y +CONFIG_CMD_WGET=y CONFIG_CMD_MII=y CONFIG_CMD_PING=y CONFIG_CMD_PXE=y @@ -148,6 +151,8 @@ CONFIG_NET_RANDOM_ETHADDR=y CONFIG_NETCONSOLE=y CONFIG_IP_DEFRAG=y CONFIG_TFTP_TSIZE=y +CONFIG_PROT_TCP_SACK=y +CONFIG_IPV6=y CONFIG_SPL_DM=y CONFIG_REGMAP=y CONFIG_SYSCON=y diff --git a/configs/imx8mp_data_modul_edm_sbc_defconfig b/configs/imx8mp_data_modul_edm_sbc_defconfig index ae1a48c6812..7ee454076c6 100644 --- a/configs/imx8mp_data_modul_edm_sbc_defconfig +++ b/configs/imx8mp_data_modul_edm_sbc_defconfig @@ -114,6 +114,9 @@ CONFIG_CMD_USB=y CONFIG_CMD_USB_SDP=y CONFIG_CMD_USB_MASS_STORAGE=y CONFIG_CMD_DHCP=y +CONFIG_CMD_DHCP6=y +CONFIG_CMD_TFTPPUT=y +CONFIG_CMD_WGET=y CONFIG_CMD_MII=y CONFIG_CMD_PING=y CONFIG_CMD_PXE=y @@ -155,6 +158,8 @@ CONFIG_NET_RANDOM_ETHADDR=y CONFIG_NETCONSOLE=y CONFIG_IP_DEFRAG=y CONFIG_TFTP_TSIZE=y +CONFIG_PROT_TCP_SACK=y +CONFIG_IPV6=y CONFIG_SPL_DM=y CONFIG_REGMAP=y CONFIG_SYSCON=y -- cgit v1.3.1