From d043e977104650ce8f00eeaf57a7484e4684900d Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Thu, 11 Jun 2026 20:04:26 +0200 Subject: arm: renesas: Build u-boot-elf.shdr for R-Car X5H Cortex-M33 RSIP port Currently, the default build target for all R-Car Gen3/4/5 is the u-boot-elf.srec, which depends on u-boot.bin and other vital build artifacts, which get built as prerequisites. The R-Car Gen5 RSIP port benefits from u-boot-elf.shdr being built as well, because the u-boot-elf.shdr contains header used by the BootROM to load and start U-Boot on the RSIP core. Because u-boot-elf.shdr depends on u-boot-elf.srec, switch the default build target for R-Car Gen5 RSIP port to u-boot-elf.shdr. This way, both u-boot-elf.shdr and u-boot-elf.srec are built for R-Car Gen5 RSIP port. Fixes: 9d47a5a4d560 ("arm: renesas: Add Renesas R-Car R8A78000 X5H Cortex-M33 RSIP port") Signed-off-by: Marek Vasut --- Kconfig | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/Kconfig b/Kconfig index 8428d039a1c..99b896b6cf1 100644 --- a/Kconfig +++ b/Kconfig @@ -548,7 +548,8 @@ config REMAKE_ELF config BUILD_TARGET string "Build target special images" - default "u-boot-elf.srec" if RCAR_64 + default "u-boot-elf.shdr" if RCAR_64 && RCAR_64_RSIP + default "u-boot-elf.srec" if RCAR_64 && !RCAR_64_RSIP default "u-boot-with-spl.bin" if ARCH_AT91 && SPL_NAND_SUPPORT default "u-boot-with-spl.bin" if MPC85xx && !E500MC && !E5500 && !E6500 && SPL default "u-boot-with-spl.imx" if (ARCH_MX6 || ARCH_MX7) && SPL -- cgit v1.3.1 From 79d6bd525ce03fba9fe958eb11734c1ebb16838a Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Thu, 11 Jun 2026 20:05:58 +0200 Subject: arm: renesas: Make R-Car Gen5 u-boot-elf.shdr compatible with SDK flash_writer The SDK 4.32 flash_writer tool, built from the SDK IPL source, requires SREC S7 "Start address (termination)" record [1] at the end of the SREC file that is sent to it during installation of content into storage, otherwise the tool waits for the S7 record indefinitelly and the payload does not get installed into storage. Specifically, the tool considers SREC S3 and S7 records as mandatory, S0, S5, S6 as ignored, and any other records as unsupported. Configure srec_cat such that it explicitly generates the trailing S7 record, and also that it never generates the ignored S5 Count record. This fixes installation of u-boot-elf.shdr using the flash_writer tool, which can not finish successfully without the trailing S7 record. [1] https://en.wikipedia.org/wiki/Motorola_S-record#Record_types Fixes: 3b2ce3743c1a ("arm: renesas: Generate u-boot-elf.shdr for R-Car Gen5 RSIP") Signed-off-by: Marek Vasut --- arch/arm/mach-renesas/Makefile | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm/mach-renesas/Makefile b/arch/arm/mach-renesas/Makefile index 83c576d6007..4c8dbc465a6 100644 --- a/arch/arm/mach-renesas/Makefile +++ b/arch/arm/mach-renesas/Makefile @@ -50,6 +50,8 @@ quiet_cmd_srec_cat = SRECCAT $@ quiet_cmd_srec_shdr_cat = SRECCAT $@ cmd_srec_shdr_cat = srec_cat -output $@ -M 8 \ -Output_Block_Size 16 \ + -DISable Data_Count \ + -Execution_Start_Address 0x18400000 \ -generate 0x18400000 0x18400004 $(srec_cat_le_cmd) 0x00000003 4 \ -generate 0x18400004 0x18400008 $(srec_cat_le_cmd) 0x0 4 \ -generate 0x18402000 0x18402004 $(srec_cat_le_cmd) 0x6b657963 4 \ -- cgit v1.3.1 From a298f3066ef292466f58c4f1d545830e184cd051 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Sun, 14 Jun 2026 03:52:08 +0200 Subject: arm64: renesas: Fold mach_cpu_init into board_init_f on R-Car S4/V4H/V4M SPL The mach_cpu_init() function is not invoked in SPL. Instead of having two functions, fold mach_cpu_init() into board_init_f(), which is called very early in the boot process and assures that the CPG and APMU setup will be invoked before DM is brought up. Fixes: 37997a214ed1 ("arm: renesas: Use stock lowlevel_init function and remove s_init") Signed-off-by: Marek Vasut --- board/renesas/common/gen4-spl.c | 41 ++++++++++++++++++----------------------- 1 file changed, 18 insertions(+), 23 deletions(-) diff --git a/board/renesas/common/gen4-spl.c b/board/renesas/common/gen4-spl.c index e4c1190eac7..5a0b0ebe115 100644 --- a/board/renesas/common/gen4-spl.c +++ b/board/renesas/common/gen4-spl.c @@ -18,6 +18,12 @@ #include #include +#define APMU_BASE 0xe6170000U +#define CL0GRP3_BIT BIT(3) +#define CL1GRP3_BIT BIT(7) +#define RTGRP3_BIT BIT(19) +#define APMU_ACC_ENB_FOR_ARM_CPU (CL0GRP3_BIT | CL1GRP3_BIT | RTGRP3_BIT) + #define CNTCR_EN BIT(0) #ifdef CONFIG_SPL_BUILD @@ -47,6 +53,18 @@ void board_init_f(ulong dummy) struct udevice *dev; int ret; + /* Unlock CPG access */ + writel(0x5A5AFFFF, CPGWPR); + writel(0xA5A50000, CPGWPCR); + init_generic_timer(); + + /* Define for Work Around of APMU */ + writel(0x00ff00ff, APMU_BASE + 0x10); + writel(0x00ff00ff, APMU_BASE + 0x14); + writel(0x00ff00ff, APMU_BASE + 0x18); + writel(0x00ff00ff, APMU_BASE + 0x1c); + clrbits_le32(APMU_BASE + 0x68, BIT(29)); + if (CONFIG_IS_ENABLED(OF_CONTROL)) { ret = spl_early_init(); if (ret) { @@ -76,29 +94,6 @@ struct legacy_img_hdr *spl_get_load_buffer(ssize_t offset, size_t size) return map_sysmem(CONFIG_SYS_LOAD_ADDR + offset, 0); } -#define APMU_BASE 0xe6170000U -#define CL0GRP3_BIT BIT(3) -#define CL1GRP3_BIT BIT(7) -#define RTGRP3_BIT BIT(19) -#define APMU_ACC_ENB_FOR_ARM_CPU (CL0GRP3_BIT | CL1GRP3_BIT | RTGRP3_BIT) - -int mach_cpu_init(void) -{ - /* Unlock CPG access */ - writel(0x5A5AFFFF, CPGWPR); - writel(0xA5A50000, CPGWPCR); - init_generic_timer(); - - /* Define for Work Around of APMU */ - writel(0x00ff00ff, APMU_BASE + 0x10); - writel(0x00ff00ff, APMU_BASE + 0x14); - writel(0x00ff00ff, APMU_BASE + 0x18); - writel(0x00ff00ff, APMU_BASE + 0x1c); - clrbits_le32(APMU_BASE + 0x68, BIT(29)); - - return 0; -} - void reset_cpu(void) { } -- cgit v1.3.1 From cc5d760ace890b57d78b23aafb47ba220e63ae4f Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Sun, 14 Jun 2026 03:52:21 +0200 Subject: arm64: renesas: Initialize GIC600 fully on R-Car S4/V4H/V4M ARM GIC-600 IP complies with ARM GICv3 architecture, but among others, implements a power control register in the Redistributor frame. This register must be programmed to mark the frame as powered on, before accessing other registers in the frame. Before the switch to generic lowlevel_init function, this did not pose a problem as the previous custom lowlevel_init did not access the GICR registers. The generic function does and that does lead to a hang early in SPL. Enable the GIC600 initialization variant to mitigate the hang. Fixes: 37997a214ed1 ("arm: renesas: Use stock lowlevel_init function and remove s_init") Signed-off-by: Marek Vasut --- arch/arm/mach-renesas/Kconfig.rcar4 | 3 +++ 1 file changed, 3 insertions(+) diff --git a/arch/arm/mach-renesas/Kconfig.rcar4 b/arch/arm/mach-renesas/Kconfig.rcar4 index 2439501d07e..39814950b1a 100644 --- a/arch/arm/mach-renesas/Kconfig.rcar4 +++ b/arch/arm/mach-renesas/Kconfig.rcar4 @@ -11,12 +11,14 @@ config R8A779A0 config R8A779F0 bool "Renesas SoC R8A779F0" select GICV3 + select GICV3_SUPPORT_GIC600 imply CLK_R8A779F0 imply PINCTRL_PFC_R8A779F0 config R8A779G0 bool "Renesas SoC R8A779G0" select GICV3 + select GICV3_SUPPORT_GIC600 select BINMAN select SUPPORT_SPL imply SPL @@ -33,6 +35,7 @@ config R8A779G0 config R8A779H0 bool "Renesas SoC R8A779H0" select GICV3 + select GICV3_SUPPORT_GIC600 imply CLK_R8A779H0 imply PINCTRL_PFC_R8A779H0 -- cgit v1.3.1