From ac9153c74f30c13ce773367166bcb44aa847ff67 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Thu, 5 Sep 2024 17:35:00 +0200 Subject: ARM: imx: Enable MMU and dcache very early on i.MX8M Enable MMU and caches very early on in the boot process on i.MX8M in U-Boot proper. This allows board_init_f to run with icache and dcache enabled, which saves some 700 milliseconds of boot time on i.MX8M Plus based device. The 'bootstage report' output is below: Before: ``` Timer summary in microseconds (8 records): Mark Elapsed Stage 0 0 reset 961,363 961,363 board_init_f 1,818,874 857,511 board_init_r 1,921,474 102,600 eth_common_init 2,013,702 92,228 eth_initialize 2,015,238 1,536 main_loop Accumulated time: 32,775 dm_r 289,165 dm_f ``` After: ``` Timer summary in microseconds (8 records): Mark Elapsed Stage 0 0 reset 989,466 989,466 board_init_f 1,179,100 189,634 board_init_r 1,281,456 102,356 eth_common_init 1,373,857 92,401 eth_initialize 1,375,396 1,539 main_loop Accumulated time: 12,630 dm_f 32,635 dm_r ``` Signed-off-by: Marek Vasut Reviewed-by: Peng Fan Reviewed-by: Fabio Estevam --- arch/arm/mach-imx/imx8m/soc.c | 47 +++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 47 insertions(+) diff --git a/arch/arm/mach-imx/imx8m/soc.c b/arch/arm/mach-imx/imx8m/soc.c index f30178ae213..986687e9ce4 100644 --- a/arch/arm/mach-imx/imx8m/soc.c +++ b/arch/arm/mach-imx/imx8m/soc.c @@ -32,6 +32,7 @@ #include #include #include +#include DECLARE_GLOBAL_DATA_PTR; @@ -206,6 +207,14 @@ void enable_caches(void) int entry = imx8m_find_dram_entry_in_mem_map(); u64 attrs = imx8m_mem_map[entry].attrs; + /* Deactivate the data cache, possibly enabled in arch_cpu_init() */ + dcache_disable(); + /* + * Force the call of setup_all_pgtables() in mmu_setup() by clearing tlb_fillptr + * to update the TLB location udpated in board_f.c::reserve_mmu + */ + gd->arch.tlb_fillptr = 0; + while (i < CONFIG_NR_DRAM_BANKS && entry < ARRAY_SIZE(imx8m_mem_map)) { if (gd->bd->bi_dram[i].start == 0) @@ -587,12 +596,50 @@ static void imx8m_setup_csu_tzasc(void) } } +/* + * Place early TLB into the .data section so that it will not + * get cleared, use 16 kiB alignment. + */ +#define EARLY_TLB_SIZE SZ_64K +u8 early_tlb[EARLY_TLB_SIZE] __section(".data") __aligned(0x4000); + +/* + * Initialize the MMU and activate cache in U-Boot pre-reloc stage + * MMU/TLB is updated in enable_caches() for U-Boot after relocation + */ +static void early_enable_caches(void) +{ + phys_size_t sdram_size; + int entry, ret; + + if (IS_ENABLED(CONFIG_SPL_BUILD)) + return; + + if (CONFIG_IS_ENABLED(SYS_ICACHE_OFF) || CONFIG_IS_ENABLED(SYS_DCACHE_OFF)) + return; + + /* Use maximum available DRAM size in first bank. */ + ret = board_phys_sdram_size(&sdram_size); + if (ret) + return; + + entry = imx8m_find_dram_entry_in_mem_map(); + imx8m_mem_map[entry].size = max(sdram_size, (phys_size_t)0xc0000000); + + gd->arch.tlb_size = EARLY_TLB_SIZE; + gd->arch.tlb_addr = (unsigned long)&early_tlb; + + /* Enable MMU (default configuration) */ + dcache_enable(); +} + int arch_cpu_init(void) { struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR; #if !CONFIG_IS_ENABLED(SYS_ICACHE_OFF) icache_enable(); + early_enable_caches(); #endif /* -- cgit v1.3.1 From 4aea3110aba9238fbcb6c4a5273abce4cb176691 Mon Sep 17 00:00:00 2001 From: Tim Harvey Date: Thu, 5 Sep 2024 12:08:26 -0700 Subject: configs: venice: enable DM_RNG Enable DM_RNG so that the kaslr-seed property is set in the dt allowing Linux KASLR. Signed-off-by: Tim Harvey Reviewed-by: Fabio Estevam --- configs/imx8mm_venice_defconfig | 1 - configs/imx8mn_venice_defconfig | 1 - configs/imx8mp_venice_defconfig | 1 - 3 files changed, 3 deletions(-) diff --git a/configs/imx8mm_venice_defconfig b/configs/imx8mm_venice_defconfig index fc3e3ec3779..3633401a349 100644 --- a/configs/imx8mm_venice_defconfig +++ b/configs/imx8mm_venice_defconfig @@ -139,7 +139,6 @@ CONFIG_DM_PMIC_MP5416=y CONFIG_SPL_DM_PMIC_MP5416=y CONFIG_DM_REGULATOR_FIXED=y CONFIG_DM_REGULATOR_GPIO=y -# CONFIG_DM_RNG is not set CONFIG_DM_SERIAL=y CONFIG_MXC_UART=y CONFIG_SPI=y diff --git a/configs/imx8mn_venice_defconfig b/configs/imx8mn_venice_defconfig index 93e6a28535c..d2925f247e1 100644 --- a/configs/imx8mn_venice_defconfig +++ b/configs/imx8mn_venice_defconfig @@ -134,7 +134,6 @@ CONFIG_SPL_DM_PMIC_MP5416=y CONFIG_DM_REGULATOR=y CONFIG_DM_REGULATOR_FIXED=y CONFIG_DM_REGULATOR_GPIO=y -# CONFIG_DM_RNG is not set CONFIG_DM_SERIAL=y CONFIG_MXC_UART=y CONFIG_SPI=y diff --git a/configs/imx8mp_venice_defconfig b/configs/imx8mp_venice_defconfig index b08e4ae4e1f..09a88418143 100644 --- a/configs/imx8mp_venice_defconfig +++ b/configs/imx8mp_venice_defconfig @@ -139,7 +139,6 @@ CONFIG_DM_PMIC_MP5416=y CONFIG_SPL_DM_PMIC_MP5416=y CONFIG_DM_REGULATOR_FIXED=y CONFIG_DM_REGULATOR_GPIO=y -# CONFIG_DM_RNG is not set CONFIG_DM_SERIAL=y CONFIG_MXC_UART=y CONFIG_SPI=y -- cgit v1.3.1 From 5748aa1e372d2db3db6bf3e863f4571bf2ffedb9 Mon Sep 17 00:00:00 2001 From: Miquel Raynal Date: Tue, 10 Sep 2024 11:13:59 +0200 Subject: pwm: imx: Don't drop the enable bit once set Changing the duty-cycle should not blindly override (and clear) the enable (EN) bit if it has already been set. For instance, a PWM backlight can be enabled and set to a specific intensity using two operations. The order of these operations should not matter. Signed-off-by: Miquel Raynal Reviewed-by: Fabio Estevam --- drivers/pwm/pwm-imx.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/drivers/pwm/pwm-imx.c b/drivers/pwm/pwm-imx.c index 320ea7c4239..bb37b39fa0e 100644 --- a/drivers/pwm/pwm-imx.c +++ b/drivers/pwm/pwm-imx.c @@ -20,10 +20,11 @@ int pwm_config_internal(struct pwm_regs *pwm, unsigned long period_cycles, u32 cr; writel(0, &pwm->ir); - cr = PWMCR_PRESCALER(prescale) | + + cr = readl(&pwm->cr) & PWMCR_EN; + cr |= PWMCR_PRESCALER(prescale) | PWMCR_DOZEEN | PWMCR_WAITEN | PWMCR_DBGEN | PWMCR_CLKSRC_IPG_HIGH; - writel(cr, &pwm->cr); /* set duty cycles */ writel(duty_cycles, &pwm->sar); -- cgit v1.3.1