From 20f2b9bbd2a6bc938055f41b2a10b3cf2f378e5c Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Sun, 5 Jul 2026 17:52:24 +0200 Subject: MAINTAINERS: Update SH/SoCFPGA/USB email addresses Update the email addresses to a valid one. Use N: usb to match on all USB related bits. Signed-off-by: Marek Vasut --- .mailmap | 7 ++++--- MAINTAINERS | 12 ++++-------- 2 files changed, 8 insertions(+), 11 deletions(-) diff --git a/.mailmap b/.mailmap index e73b98ae0ae..bcb393e581b 100644 --- a/.mailmap +++ b/.mailmap @@ -87,9 +87,10 @@ Love Kumar Lukasz Majewski Marek Behún Marek Behún Marek Behun -Marek Vasut -Marek Vasut -Marek Vasut +Marek Vasut +Marek Vasut +Marek Vasut +Marek Vasut Markus Klotzbuecher Masahiro Yamada Masahiro Yamada diff --git a/MAINTAINERS b/MAINTAINERS index 86ab813aee4..e1379a6a3e7 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -168,7 +168,7 @@ F: arch/arm/dts/Makefile F: cmd/arm/ ARM ALTERA SOCFPGA -M: Marek Vasut +M: Marek Vasut M: Simon Goldschmidt M: Tien Fong Chee S: Maintained @@ -1655,7 +1655,7 @@ F: cmd/printf.c F: doc/usage/setexpr.rst SH -M: Marek Vasut +M: Marek Vasut M: Nobuhiro Iwamatsu S: Maintained T: git https://git.u-boot-project.org/u-boot/custodians/u-boot-sh.git @@ -1869,14 +1869,10 @@ F: test/boot/upl.c F: test/py/tests/test_upl.py USB -M: Marek Vasut +M: Marek Vasut S: Maintained T: git https://git.u-boot-project.org/u-boot/custodians/u-boot-usb.git -F: drivers/usb/ -F: common/usb.c -F: common/usb_kbd.c -F: common/usb_storage.c -F: include/usb.h +N: usb USB TCPM M: Sebastian Reichel -- cgit v1.3.1 From 202d31f930ef87771e76c1696f843c176bbda1e1 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Thu, 23 Jul 2026 00:53:37 +0200 Subject: clk: renesas: Add SDK SCP 4.36 map to Renesas R-Car R8A78000 X5H CPG clock driver The SCMI IDs did not change between SDK SCP 4.32 and SDK SCP 4.36. Add SDK SCP 4.36 as supported version and reuse SDK SCP 4.32 remap table. Signed-off-by: Marek Vasut --- drivers/clk/renesas/r8a78000-cpg.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/drivers/clk/renesas/r8a78000-cpg.c b/drivers/clk/renesas/r8a78000-cpg.c index e9ca06476f6..67d820bbde8 100644 --- a/drivers/clk/renesas/r8a78000-cpg.c +++ b/drivers/clk/renesas/r8a78000-cpg.c @@ -105,6 +105,7 @@ struct clk_map_in { #define GEN5_SCMI_SDK_4_30 0x010c0000 #define GEN5_SCMI_SDK_4_31 0x010d0000 #define GEN5_SCMI_SDK_4_32 0x010e0000 +#define GEN5_SCMI_SDK_4_36 0x01100000 static const struct clk_map_in gen5_clk_map_dt_sdk_4_28[] = { { SCP_CLOCK_ID_MDLC_UFS0, 202 }, @@ -186,7 +187,8 @@ static int gen5_clk_of_xlate(struct clk *clk, struct ofnode_phandle_args *args) map = gen5_clk_map_dt_sdk_4_28; map_size = ARRAY_SIZE(gen5_clk_map_dt_sdk_4_28); } else if (priv->basever == GEN5_SCMI_SDK_4_31 || - priv->basever == GEN5_SCMI_SDK_4_32) { + priv->basever == GEN5_SCMI_SDK_4_32 || + priv->basever == GEN5_SCMI_SDK_4_36) { map = gen5_clk_map_dt_sdk_4_31; map_size = ARRAY_SIZE(gen5_clk_map_dt_sdk_4_31); } else { -- cgit v1.3.1 From 99203d9dac5246937854fa41677365c66d2a2264 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Sun, 19 Jul 2026 20:11:49 +0200 Subject: clk: rs9: Add Renesas 9-series PCIe clock generator driver Add driver for Renesas 9-series PCIe clock generators. This driver is designed to support 9FGV/9DBV/9DMV/9FGL/9DML/9QXL/9SQ series I2C PCIe clock generators. The driver is capable of configuring per-chip spread spectrum mode and output amplitude, as well as per-output slew rate. Losely based on Linux 7.1 commit 5ec820fc28d0 ("clk: rs9: Reserve 8 struct clk_hw slots for for 9FGV0841") Signed-off-by: Marek Vasut --- drivers/clk/Kconfig | 7 + drivers/clk/Makefile | 1 + drivers/clk/clk-renesas-pcie.c | 327 +++++++++++++++++++++++++++++++++++++++++ 3 files changed, 335 insertions(+) create mode 100644 drivers/clk/clk-renesas-pcie.c diff --git a/drivers/clk/Kconfig b/drivers/clk/Kconfig index 145e4cfa2de..47da49c8314 100644 --- a/drivers/clk/Kconfig +++ b/drivers/clk/Kconfig @@ -215,6 +215,13 @@ config CLK_HSDK Enable this to support the cgu clocks on Synopsys ARC HSDK and Synopsys ARC HSDK-4xD boards +config CLK_RS9_PCIE + tristate "Clock driver for Renesas 9-series PCIe clock generators" + depends on CLK + help + This driver supports the Renesas 9-series PCIe clock generator + models 9FGV/9DBV/9DMV/9FGL/9DML/9QXL/9SQ. + config CLK_VERSACLOCK bool "Enable VersaClock 5/6 devices" depends on CLK diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile index 2bfa789e48a..4b241a9240a 100644 --- a/drivers/clk/Makefile +++ b/drivers/clk/Makefile @@ -45,6 +45,7 @@ obj-$(CONFIG_CLK_OCTEON) += clk_octeon.o obj-$(CONFIG_CLK_OWL) += owl/ obj-$(CONFIG_CLK_QCOM) += qcom/ obj-$(CONFIG_CLK_RENESAS) += renesas/ +obj-$(CONFIG_$(PHASE_)CLK_RS9_PCIE) += clk-renesas-pcie.o obj-$(CONFIG_$(PHASE_)CLK_SCMI) += clk_scmi.o obj-$(CONFIG_CLK_SIFIVE) += sifive/ obj-$(CONFIG_CLK_SOPHGO) += sophgo/ diff --git a/drivers/clk/clk-renesas-pcie.c b/drivers/clk/clk-renesas-pcie.c new file mode 100644 index 00000000000..ad57cd4fd28 --- /dev/null +++ b/drivers/clk/clk-renesas-pcie.c @@ -0,0 +1,327 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Driver for Renesas 9-series PCIe clock generator driver + * + * The following series can be supported: + * - 9FGV/9DBV/9DMV/9FGL/9DML/9QXL/9SQ + * Currently supported: + * - 9FGV0241 + * - 9FGV0441 + * - 9FGV0841 + * + * Copyright (C) 2022-2026 Marek Vasut + */ + +#include +#include +#include +#include +#include +#include + +#define RS9_REG_OE 0x0 +#define RS9_REG_SS 0x1 +#define RS9_REG_SS_AMP_0V6 0x0 +#define RS9_REG_SS_AMP_0V7 0x1 +#define RS9_REG_SS_AMP_0V8 0x2 +#define RS9_REG_SS_AMP_0V9 0x3 +#define RS9_REG_SS_AMP_DEFAULT RS9_REG_SS_AMP_0V8 +#define RS9_REG_SS_AMP_MASK 0x3 +#define RS9_REG_SS_SSC_100 0 +#define RS9_REG_SS_SSC_M025 (1 << 3) +#define RS9_REG_SS_SSC_M050 (3 << 3) +#define RS9_REG_SS_SSC_DEFAULT RS9_REG_SS_SSC_100 +#define RS9_REG_SS_SSC_MASK (3 << 3) +#define RS9_REG_SS_SSC_LOCK BIT(5) +#define RS9_REG_SR 0x2 +#define RS9_REG_REF 0x3 +#define RS9_REG_REF_OE BIT(4) +#define RS9_REG_REF_OD BIT(5) +#define RS9_REG_REF_SR_SLOWEST 0 +#define RS9_REG_REF_SR_SLOW (1 << 6) +#define RS9_REG_REF_SR_FAST (2 << 6) +#define RS9_REG_REF_SR_FASTER (3 << 6) +#define RS9_REG_VID 0x5 +#define RS9_REG_DID 0x6 +#define RS9_REG_BCP 0x7 + +#define RS9_REG_VID_MASK GENMASK(3, 0) +#define RS9_REG_VID_IDT 0x01 + +#define RS9_REG_DID_TYPE_FGV (0x0 << RS9_REG_DID_TYPE_SHIFT) +#define RS9_REG_DID_TYPE_DBV (0x1 << RS9_REG_DID_TYPE_SHIFT) +#define RS9_REG_DID_TYPE_DMV (0x2 << RS9_REG_DID_TYPE_SHIFT) +#define RS9_REG_DID_TYPE_SHIFT 0x6 + +/* Structure to describe features of a particular 9-series model */ +struct rs9_chip_info { + unsigned int num_clks; + u8 outshift; + u8 did; +}; + +struct rs9_driver_data { + struct udevice *i2c; + struct rs9_chip_info *chip_info; + unsigned long rate; + u8 pll_amplitude; + u8 pll_ssc; + u8 clk_dif_sr; +}; + +static int clk_rs9_request(struct clk *clk) +{ + struct rs9_driver_data *rs9 = dev_get_priv(clk->dev); + + if (clk->id > rs9->chip_info->num_clks) + return -EINVAL; + + return 0; +} + +static ulong clk_rs9_get_rate(struct clk *clk) +{ + struct rs9_driver_data *rs9 = dev_get_priv(clk->dev); + + return rs9->rate * 4; +} + +static const struct clk_ops clk_rs9_ops = { + .request = clk_rs9_request, + .get_rate = clk_rs9_get_rate, +}; + +static int rs9_write(struct udevice *dev, u8 reg, u8 val) +{ + u8 data[2] = { 1, val }; + + return dm_i2c_write(dev, reg, data, 2); +} + +static int rs9_read(struct udevice *dev, u8 reg, u8 *val) +{ + struct dm_i2c_chip *chip = dev_get_parent_plat(dev); + struct i2c_msg xfer[2]; + u8 txdata = reg; + u8 rxdata[2]; + int ret; + + xfer[0].addr = chip->chip_addr; + xfer[0].flags = 0; + xfer[0].len = 1; + xfer[0].buf = (void *)&txdata; + + xfer[1].addr = chip->chip_addr; + xfer[1].flags = I2C_M_RD; + xfer[1].len = 2; + xfer[1].buf = (void *)rxdata; + + ret = dm_i2c_xfer(dev, xfer, 2); + if (ret < 0) + return ret; + + /* + * Byte 0 is transfer length, which is always 1 due + * to BCP register programming to 1 in rs9_probe(), + * ignore it and use data from Byte 1. + */ + *val = rxdata[1]; + return 0; +} + +static u8 rs9_calc_dif(const struct rs9_driver_data *rs9, int idx) +{ + /* + * On 9FGV0241, the DIF OE0 is BIT(1) and DIF OE(1) is BIT(2), + * on 9FGV0441 and 9FGV0841 the DIF OE0 is BIT(0) and so on. + * Increment the index in the 9FGV0241 special case here. + */ + return BIT(idx + rs9->chip_info->outshift); +} + +static int rs9_get_output_config(struct rs9_driver_data *rs9, int idx) +{ + struct udevice *dev = rs9->i2c; + u8 dif = rs9_calc_dif(rs9, idx); + unsigned char name[5] = "DIF0"; + ofnode np; + u32 sr; + + /* Set defaults */ + rs9->clk_dif_sr |= dif; + + snprintf(name, 5, "DIF%d", idx); + np = dev_read_subnode(dev, name); + if (!ofnode_valid(np)) + return 0; + + /* Output clock slew rate */ + sr = ofnode_read_u32_default(np, "renesas,slew-rate", 3000000); + if (sr == 2000000) { /* 2V/ns */ + rs9->clk_dif_sr &= ~dif; + } else if (sr == 3000000) { /* 3V/ns (default) */ + rs9->clk_dif_sr |= dif; + } else { + dev_err(dev, "Invalid renesas,slew-rate value\n"); + return -EINVAL; + } + + return 0; +} + +static int rs9_get_common_config(struct rs9_driver_data *rs9) +{ + struct udevice *dev = rs9->i2c; + unsigned int amp, ssc; + + /* Set defaults */ + rs9->pll_amplitude = RS9_REG_SS_AMP_DEFAULT; + rs9->pll_ssc = RS9_REG_SS_SSC_DEFAULT; + + /* Output clock amplitude */ + amp = dev_read_u32_default(dev, "renesas,out-amplitude-microvolt", 700000); + if (amp == 600000) { /* 0.6V */ + rs9->pll_amplitude = RS9_REG_SS_AMP_0V6; + } else if (amp == 700000) { /* 0.7V (default) */ + rs9->pll_amplitude = RS9_REG_SS_AMP_0V7; + } else if (amp == 800000) { /* 0.8V */ + rs9->pll_amplitude = RS9_REG_SS_AMP_0V8; + } else if (amp == 900000) { /* 0.9V */ + rs9->pll_amplitude = RS9_REG_SS_AMP_0V9; + } else { + dev_err(dev, "Invalid renesas,out-amplitude-microvolt value\n"); + return -EINVAL; + } + + /* Output clock spread spectrum */ + ssc = dev_read_u32_default(dev, "renesas,out-spread-spectrum", 100000); + if (ssc == 100000) { /* 100% ... no spread (default) */ + rs9->pll_ssc = RS9_REG_SS_SSC_100; + } else if (ssc == 99750) { /* -0.25% ... down spread */ + rs9->pll_ssc = RS9_REG_SS_SSC_M025; + } else if (ssc == 99500) { /* -0.50% ... down spread */ + rs9->pll_ssc = RS9_REG_SS_SSC_M050; + } else { + dev_err(dev, "Invalid renesas,out-spread-spectrum value\n"); + return -EINVAL; + } + + return 0; +} + +static void rs9_update_config(struct rs9_driver_data *rs9) +{ + struct udevice *dev = rs9->i2c; + int i; + + /* If amplitude is non-default, update it. */ + if (rs9->pll_amplitude != RS9_REG_SS_AMP_DEFAULT) { + dm_i2c_reg_clrset(dev, RS9_REG_SS, RS9_REG_SS_AMP_MASK, + rs9->pll_amplitude); + } + + /* If SSC is non-default, update it. */ + if (rs9->pll_ssc != RS9_REG_SS_SSC_DEFAULT) { + dm_i2c_reg_clrset(dev, RS9_REG_SS, RS9_REG_SS_SSC_MASK, + rs9->pll_ssc); + } + + for (i = 0; i < rs9->chip_info->num_clks; i++) { + u8 dif = rs9_calc_dif(rs9, i); + + if (rs9->clk_dif_sr & dif) + continue; + + dm_i2c_reg_clrset(dev, RS9_REG_SR, dif, + rs9->clk_dif_sr & dif); + } +} + +static int clk_rs9_probe(struct udevice *dev) +{ + struct rs9_driver_data *rs9 = dev_get_priv(dev); + struct clk *clk; + u8 vid, did; + int i, ret; + + rs9->i2c = dev; + rs9->chip_info = (struct rs9_chip_info *)dev_get_driver_data(dev); + if (!rs9->chip_info) + return -EINVAL; + + clk = devm_clk_get(dev, NULL); + if (IS_ERR(clk)) + return PTR_ERR(clk); + + rs9->rate = clk_get_rate(clk); + + /* Fetch common configuration from DT (if specified) */ + ret = rs9_get_common_config(rs9); + if (ret) + return ret; + + /* Fetch DIFx output configuration from DT (if specified) */ + for (i = 0; i < rs9->chip_info->num_clks; i++) { + ret = rs9_get_output_config(rs9, i); + if (ret) + return ret; + } + + /* Always read back 1 Byte via I2C */ + ret = rs9_write(dev, RS9_REG_BCP, 1); + if (ret < 0) + return ret; + + ret = rs9_read(dev, RS9_REG_VID, &vid); + if (ret < 0) + return ret; + + ret = rs9_read(dev, RS9_REG_DID, &did); + if (ret < 0) + return ret; + + vid &= RS9_REG_VID_MASK; + if (vid != RS9_REG_VID_IDT || did != rs9->chip_info->did) { + dev_err(dev, "Incorrect VID/DID: %#02x, %#02x. Expected %#02x, %#02x\n", + vid, did, RS9_REG_VID_IDT, rs9->chip_info->did); + return -ENODEV; + } + + rs9_update_config(rs9); + + return 0; +} + +static const struct rs9_chip_info renesas_9fgv0241_info = { + .num_clks = 2, + .outshift = 1, + .did = RS9_REG_DID_TYPE_FGV | 0x02, +}; + +static const struct rs9_chip_info renesas_9fgv0441_info = { + .num_clks = 4, + .outshift = 0, + .did = RS9_REG_DID_TYPE_FGV | 0x04, +}; + +static const struct rs9_chip_info renesas_9fgv0841_info = { + .num_clks = 8, + .outshift = 0, + .did = RS9_REG_DID_TYPE_FGV | 0x08, +}; + +static const struct udevice_id clk_rs9_of_match[] = { + { .compatible = "renesas,9fgv0241", .data = (ulong)&renesas_9fgv0241_info }, + { .compatible = "renesas,9fgv0441", .data = (ulong)&renesas_9fgv0441_info }, + { .compatible = "renesas,9fgv0841", .data = (ulong)&renesas_9fgv0841_info }, + { /* sentinel */ }, +}; + +U_BOOT_DRIVER(clk_rs9) = { + .name = "clk-renesas-pcie-9series", + .id = UCLASS_CLK, + .of_match = clk_rs9_of_match, + .ops = &clk_rs9_ops, + .probe = clk_rs9_probe, + .priv_auto = sizeof(struct rs9_driver_data), +}; -- cgit v1.3.1 From 50d73309201df8fcaae64c8f02ac5413c11c8b56 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Sun, 19 Jul 2026 20:11:50 +0200 Subject: pci: pcie-rcar-gen4: Handle always on reference clock The clock controller driver for the device which supplies reference clock to the PCIe core and bus may not implement .enable / .disable callbacks in case the clock supplied by the device are always on, in which case the clk_prepare_enable() call returns -ENOSYS. This is the case on e.g. 9FGV0441. Handle the -ENOSYS as a valid return value and proceed with probing. Signed-off-by: Marek Vasut --- drivers/pci/pci-rcar-gen4.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/pci/pci-rcar-gen4.c b/drivers/pci/pci-rcar-gen4.c index e165271f58c..8c5c8095c73 100644 --- a/drivers/pci/pci-rcar-gen4.c +++ b/drivers/pci/pci-rcar-gen4.c @@ -451,7 +451,7 @@ static int rcar_gen4_pcie_probe(struct udevice *dev) return PTR_ERR(rcar->ref_clk); ret = clk_prepare_enable(rcar->ref_clk); - if (ret) + if (ret && ret != -ENOSYS) return ret; ret = gpio_request_by_name(dev, "reset-gpios", 0, &rcar->pe_rst, -- cgit v1.3.1 From e8bb5fdab94c999cd9aa663960dc8acdd6bbe527 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Sun, 19 Jul 2026 20:11:51 +0200 Subject: arm64: renesas: r8a779g3: Enable PCIe clock generator and I2C mux drivers on Retronix R-Car V4H Sparrow Hawk board Enable Renesas 9-series PCIe clock generator driver to operate the Renesas 9FGV0441 PCIe clock generator which supplies PCIe busses on this device with 100 MHz clock. Enable PCA954x I2C mux driver to access the PCIe clock generator which is attached to one of the muxed I2C busses. Signed-off-by: Marek Vasut --- configs/r8a779g3_sparrowhawk_defconfig | 3 +++ 1 file changed, 3 insertions(+) diff --git a/configs/r8a779g3_sparrowhawk_defconfig b/configs/r8a779g3_sparrowhawk_defconfig index 8bbe9721d7b..e39d14df806 100644 --- a/configs/r8a779g3_sparrowhawk_defconfig +++ b/configs/r8a779g3_sparrowhawk_defconfig @@ -25,8 +25,11 @@ CONFIG_CMD_REMOTEPROC=y CONFIG_GPIO_HOG=y CONFIG_REMOTEPROC_RENESAS_APMU=y CONFIG_BITBANGMII=y +CONFIG_CLK_RS9_PCIE=y CONFIG_CMD_PCI=y CONFIG_CMD_USB=y +CONFIG_I2C_MUX=y +CONFIG_I2C_MUX_PCA954x=y CONFIG_NET_RANDOM_ETHADDR=y CONFIG_NVME_PCI=y CONFIG_PCI=y -- cgit v1.3.1 From 53e0237c15c92fe333034cdd11df53e5a13c1781 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Sun, 19 Jul 2026 20:11:52 +0200 Subject: Revert "arm64: dts: renesas: r8a779g3: Reinstate basic PCIe clock description for Sparrow Hawk" This reverts commit a6f018b7b503c026cc66d25bd59868bac70150dc. The a6f018b7b503 ("arm64: dts: renesas: r8a779g3: Reinstate basic PCIe clock description for Sparrow Hawk") workaround for missing PCIe clock generator driver is no longer necessary, as the Renesas 9-series PCIe clock generator driver is now available. Drop the workaround. Signed-off-by: Marek Vasut --- arch/arm/dts/r8a779g3-sparrow-hawk-u-boot.dtsi | 18 ------------------ 1 file changed, 18 deletions(-) diff --git a/arch/arm/dts/r8a779g3-sparrow-hawk-u-boot.dtsi b/arch/arm/dts/r8a779g3-sparrow-hawk-u-boot.dtsi index 968cf6684c5..dff0355150d 100644 --- a/arch/arm/dts/r8a779g3-sparrow-hawk-u-boot.dtsi +++ b/arch/arm/dts/r8a779g3-sparrow-hawk-u-boot.dtsi @@ -49,24 +49,6 @@ status = "okay"; }; -&pcie0_clkref { - clock-frequency = <100000000>; - status = "okay"; -}; - -&pciec0 { - clocks = <&cpg CPG_MOD 624>, <&pcie0_clkref>; -}; - -&pcie1_clkref { - clock-frequency = <100000000>; - status = "okay"; -}; - -&pciec1 { - clocks = <&cpg CPG_MOD 625>, <&pcie1_clkref>; -}; - &rpc { flash@0 { /* -- cgit v1.3.1 From 18b1ecb34a6b925d2c945a4fa3861a1004c7e0d1 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Sun, 21 Jun 2026 04:38:51 +0200 Subject: pinctrl: renesas: Further minimize R8A77951 H3 PFC tables Reduce the PFC tables further by gating DRIF, MLB, TMU, TPU and SATA behind PINCTRL_PFC_FULL, none of which are currently supported by U-Boot. This helps reduce the size of the bootloader in 4 kiB range. Signed-off-by: Marek Vasut --- drivers/pinctrl/renesas/pfc-r8a77951.c | 28 ++++++++++++++-------------- 1 file changed, 14 insertions(+), 14 deletions(-) diff --git a/drivers/pinctrl/renesas/pfc-r8a77951.c b/drivers/pinctrl/renesas/pfc-r8a77951.c index 99b90e6df0d..0c4e91b6df5 100644 --- a/drivers/pinctrl/renesas/pfc-r8a77951.c +++ b/drivers/pinctrl/renesas/pfc-r8a77951.c @@ -1827,7 +1827,6 @@ static const unsigned int canfd1_data_pins[] = { static const unsigned int canfd1_data_mux[] = { CANFD1_TX_MARK, CANFD1_RX_MARK, }; -#endif #ifdef CONFIG_PINCTRL_PFC_R8A77951 /* - DRIF0 --------------------------------------------------------------- */ @@ -2046,7 +2045,6 @@ static const unsigned int drif3_data1_b_mux[] = { }; #endif /* CONFIG_PINCTRL_PFC_R8A77951 */ -#ifdef CONFIG_PINCTRL_PFC_FULL /* - DU --------------------------------------------------------------------- */ static const unsigned int du_rgb666_pins[] = { /* R[7:2], G[7:2], B[7:2] */ @@ -2459,7 +2457,6 @@ static const unsigned int intc_ex_irq5_pins[] = { static const unsigned int intc_ex_irq5_mux[] = { IRQ5_MARK, }; -#endif #ifdef CONFIG_PINCTRL_PFC_R8A77951 /* - MLB+ ------------------------------------------------------------------- */ @@ -2471,7 +2468,6 @@ static const unsigned int mlb_3pin_mux[] = { }; #endif /* CONFIG_PINCTRL_PFC_R8A77951 */ -#ifdef CONFIG_PINCTRL_PFC_FULL /* - MSIOF0 ----------------------------------------------------------------- */ static const unsigned int msiof0_clk_pins[] = { /* SCK */ @@ -3307,6 +3303,7 @@ static const unsigned int qspi1_data_mux[] = { QSPI1_IO2_MARK, QSPI1_IO3_MARK, }; +#ifdef CONFIG_PINCTRL_PFC_FULL /* - SATA --------------------------------------------------------------------*/ static const unsigned int sata0_devslp_a_pins[] = { /* DEVSLP */ @@ -3322,6 +3319,7 @@ static const unsigned int sata0_devslp_b_pins[] = { static const unsigned int sata0_devslp_b_mux[] = { SATA_DEVSLP_B_MARK, }; +#endif /* - SCIF0 ------------------------------------------------------------------ */ static const unsigned int scif0_data_pins[] = { @@ -3874,7 +3872,6 @@ static const unsigned int ssi9_ctrl_b_pins[] = { static const unsigned int ssi9_ctrl_b_mux[] = { SSI_SCK9_B_MARK, SSI_WS9_B_MARK, }; -#endif /* - TMU -------------------------------------------------------------------- */ static const unsigned int tmu_tclk1_a_pins[] = { @@ -3935,6 +3932,7 @@ static const unsigned int tpu_to3_pins[] = { static const unsigned int tpu_to3_mux[] = { TPU0TO3_MARK, }; +#endif /* - USB0 ------------------------------------------------------------------- */ static const unsigned int usb0_pins[] = { @@ -4378,8 +4376,10 @@ static const struct { SH_PFC_PIN_GROUP(qspi1_ctrl), BUS_DATA_PIN_GROUP(qspi1_data, 2), BUS_DATA_PIN_GROUP(qspi1_data, 4), +#ifdef CONFIG_PINCTRL_PFC_FULL SH_PFC_PIN_GROUP(sata0_devslp_a), SH_PFC_PIN_GROUP(sata0_devslp_b), +#endif SH_PFC_PIN_GROUP(scif0_data), SH_PFC_PIN_GROUP(scif0_clk), SH_PFC_PIN_GROUP(scif0_ctrl), @@ -4461,7 +4461,6 @@ static const struct { SH_PFC_PIN_GROUP(ssi9_data_b), SH_PFC_PIN_GROUP(ssi9_ctrl_a), SH_PFC_PIN_GROUP(ssi9_ctrl_b), -#endif SH_PFC_PIN_GROUP(tmu_tclk1_a), SH_PFC_PIN_GROUP(tmu_tclk1_b), SH_PFC_PIN_GROUP(tmu_tclk2_a), @@ -4470,6 +4469,7 @@ static const struct { SH_PFC_PIN_GROUP(tpu_to1), SH_PFC_PIN_GROUP(tpu_to2), SH_PFC_PIN_GROUP(tpu_to3), +#endif SH_PFC_PIN_GROUP(usb0), SH_PFC_PIN_GROUP(usb1), SH_PFC_PIN_GROUP(usb2), @@ -4506,7 +4506,7 @@ static const struct { SH_PFC_PIN_GROUP(vin5_clk), #endif }, -#ifdef CONFIG_PINCTRL_PFC_R8A77951 +#if defined(CONFIG_PINCTRL_PFC_FULL) && defined(CONFIG_PINCTRL_PFC_R8A77951) .automotive = { SH_PFC_PIN_GROUP(drif0_ctrl_a), SH_PFC_PIN_GROUP(drif0_data0_a), @@ -4601,7 +4601,6 @@ static const char * const canfd0_groups[] = { static const char * const canfd1_groups[] = { "canfd1_data", }; -#endif #ifdef CONFIG_PINCTRL_PFC_R8A77951 static const char * const drif0_groups[] = { @@ -4647,7 +4646,6 @@ static const char * const drif3_groups[] = { }; #endif /* CONFIG_PINCTRL_PFC_R8A77951 */ -#ifdef CONFIG_PINCTRL_PFC_FULL static const char * const du_groups[] = { "du_rgb666", "du_rgb888", @@ -4740,7 +4738,6 @@ static const char * const intc_ex_groups[] = { "intc_ex_irq4", "intc_ex_irq5", }; -#endif #ifdef CONFIG_PINCTRL_PFC_R8A77951 static const char * const mlb_3pin_groups[] = { @@ -4748,7 +4745,6 @@ static const char * const mlb_3pin_groups[] = { }; #endif /* CONFIG_PINCTRL_PFC_R8A77951 */ -#ifdef CONFIG_PINCTRL_PFC_FULL static const char * const msiof0_groups[] = { "msiof0_clk", "msiof0_sync", @@ -4907,10 +4903,12 @@ static const char * const qspi1_groups[] = { "qspi1_data4", }; +#ifdef CONFIG_PINCTRL_PFC_FULL static const char * const sata0_groups[] = { "sata0_devslp_a", "sata0_devslp_b", }; +#endif static const char * const scif0_groups[] = { "scif0_data", @@ -5028,7 +5026,6 @@ static const char * const ssi_groups[] = { "ssi9_ctrl_a", "ssi9_ctrl_b", }; -#endif static const char * const tmu_groups[] = { "tmu_tclk1_a", @@ -5043,6 +5040,7 @@ static const char * const tpu_groups[] = { "tpu_to2", "tpu_to3", }; +#endif static const char * const usb0_groups[] = { "usb0", @@ -5146,7 +5144,9 @@ static const struct { #endif SH_PFC_FUNCTION(qspi0), SH_PFC_FUNCTION(qspi1), +#ifdef CONFIG_PINCTRL_PFC_FULL SH_PFC_FUNCTION(sata0), +#endif SH_PFC_FUNCTION(scif0), SH_PFC_FUNCTION(scif1), SH_PFC_FUNCTION(scif2), @@ -5160,9 +5160,9 @@ static const struct { SH_PFC_FUNCTION(sdhi3), #ifdef CONFIG_PINCTRL_PFC_FULL SH_PFC_FUNCTION(ssi), -#endif SH_PFC_FUNCTION(tmu), SH_PFC_FUNCTION(tpu), +#endif SH_PFC_FUNCTION(usb0), SH_PFC_FUNCTION(usb1), SH_PFC_FUNCTION(usb2), @@ -5173,7 +5173,7 @@ static const struct { SH_PFC_FUNCTION(vin5), #endif }, -#ifdef CONFIG_PINCTRL_PFC_R8A77951 +#if defined(CONFIG_PINCTRL_PFC_FULL) && defined(CONFIG_PINCTRL_PFC_R8A77951) .automotive = { SH_PFC_FUNCTION(drif0), SH_PFC_FUNCTION(drif1), -- cgit v1.3.1 From 394e63e7c9451f5d177257ee979100b8cf7bd7ef Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Sun, 21 Jun 2026 04:38:52 +0200 Subject: pinctrl: renesas: Further minimize R8A77960 M3-W and R8A77961 M3-W+ PFC tables Reduce the PFC tables further by gating DRIF, MLB, TMU and TPU behind PINCTRL_PFC_FULL, none of which are currently supported by U-Boot. This helps reduce the size of the bootloader in 4 kiB range. Signed-off-by: Marek Vasut --- drivers/pinctrl/renesas/pfc-r8a7796.c | 22 ++++++++-------------- 1 file changed, 8 insertions(+), 14 deletions(-) diff --git a/drivers/pinctrl/renesas/pfc-r8a7796.c b/drivers/pinctrl/renesas/pfc-r8a7796.c index a587dfb89d4..ac1dbae9954 100644 --- a/drivers/pinctrl/renesas/pfc-r8a7796.c +++ b/drivers/pinctrl/renesas/pfc-r8a7796.c @@ -1833,7 +1833,6 @@ static const unsigned int canfd1_data_pins[] = { static const unsigned int canfd1_data_mux[] = { CANFD1_TX_MARK, CANFD1_RX_MARK, }; -#endif #if defined(CONFIG_PINCTRL_PFC_R8A77960) || defined(CONFIG_PINCTRL_PFC_R8A77961) /* - DRIF0 --------------------------------------------------------------- */ @@ -2052,7 +2051,6 @@ static const unsigned int drif3_data1_b_mux[] = { }; #endif /* CONFIG_PINCTRL_PFC_R8A77960 || CONFIG_PINCTRL_PFC_R8A77961 */ -#ifdef CONFIG_PINCTRL_PFC_FULL /* - DU --------------------------------------------------------------------- */ static const unsigned int du_rgb666_pins[] = { /* R[7:2], G[7:2], B[7:2] */ @@ -2465,7 +2463,6 @@ static const unsigned int intc_ex_irq5_pins[] = { static const unsigned int intc_ex_irq5_mux[] = { IRQ5_MARK, }; -#endif #if defined(CONFIG_PINCTRL_PFC_R8A77960) || defined(CONFIG_PINCTRL_PFC_R8A77961) /* - MLB+ ------------------------------------------------------------------- */ @@ -2477,7 +2474,6 @@ static const unsigned int mlb_3pin_mux[] = { }; #endif /* CONFIG_PINCTRL_PFC_R8A77960 || CONFIG_PINCTRL_PFC_R8A77961 */ -#ifdef CONFIG_PINCTRL_PFC_FULL /* - MSIOF0 ----------------------------------------------------------------- */ static const unsigned int msiof0_clk_pins[] = { /* SCK */ @@ -3866,7 +3862,6 @@ static const unsigned int ssi9_ctrl_b_pins[] = { static const unsigned int ssi9_ctrl_b_mux[] = { SSI_SCK9_B_MARK, SSI_WS9_B_MARK, }; -#endif /* - TMU -------------------------------------------------------------------- */ static const unsigned int tmu_tclk1_a_pins[] = { @@ -3927,6 +3922,7 @@ static const unsigned int tpu_to3_pins[] = { static const unsigned int tpu_to3_mux[] = { TPU0TO3_MARK, }; +#endif /* - USB0 ------------------------------------------------------------------- */ static const unsigned int usb0_pins[] = { @@ -4435,7 +4431,6 @@ static const struct { SH_PFC_PIN_GROUP(ssi9_data_b), SH_PFC_PIN_GROUP(ssi9_ctrl_a), SH_PFC_PIN_GROUP(ssi9_ctrl_b), -#endif SH_PFC_PIN_GROUP(tmu_tclk1_a), SH_PFC_PIN_GROUP(tmu_tclk1_b), SH_PFC_PIN_GROUP(tmu_tclk2_a), @@ -4444,6 +4439,7 @@ static const struct { SH_PFC_PIN_GROUP(tpu_to1), SH_PFC_PIN_GROUP(tpu_to2), SH_PFC_PIN_GROUP(tpu_to3), +#endif SH_PFC_PIN_GROUP(usb0), SH_PFC_PIN_GROUP(usb1), SH_PFC_PIN_GROUP(usb30), @@ -4478,7 +4474,8 @@ static const struct { SH_PFC_PIN_GROUP(vin5_clk), #endif }, -#if defined(CONFIG_PINCTRL_PFC_R8A77960) || defined(CONFIG_PINCTRL_PFC_R8A77961) +#if defined(CONFIG_PINCTRL_PFC_FULL) && \ + (defined(CONFIG_PINCTRL_PFC_R8A77960) || defined(CONFIG_PINCTRL_PFC_R8A77961)) .automotive = { SH_PFC_PIN_GROUP(drif0_ctrl_a), SH_PFC_PIN_GROUP(drif0_data0_a), @@ -4573,7 +4570,6 @@ static const char * const canfd0_groups[] = { static const char * const canfd1_groups[] = { "canfd1_data", }; -#endif #if defined(CONFIG_PINCTRL_PFC_R8A77960) || defined(CONFIG_PINCTRL_PFC_R8A77961) static const char * const drif0_groups[] = { @@ -4619,7 +4615,6 @@ static const char * const drif3_groups[] = { }; #endif /* CONFIG_PINCTRL_PFC_R8A77960 || CONFIG_PINCTRL_PFC_R8A77961 */ -#ifdef CONFIG_PINCTRL_PFC_FULL static const char * const du_groups[] = { "du_rgb666", "du_rgb888", @@ -4712,7 +4707,6 @@ static const char * const intc_ex_groups[] = { "intc_ex_irq4", "intc_ex_irq5", }; -#endif #if defined(CONFIG_PINCTRL_PFC_R8A77960) || defined(CONFIG_PINCTRL_PFC_R8A77961) static const char * const mlb_3pin_groups[] = { @@ -4720,7 +4714,6 @@ static const char * const mlb_3pin_groups[] = { }; #endif /* CONFIG_PINCTRL_PFC_R8A77960 || CONFIG_PINCTRL_PFC_R8A77961 */ -#ifdef CONFIG_PINCTRL_PFC_FULL static const char * const msiof0_groups[] = { "msiof0_clk", "msiof0_sync", @@ -4995,7 +4988,6 @@ static const char * const ssi_groups[] = { "ssi9_ctrl_a", "ssi9_ctrl_b", }; -#endif static const char * const tmu_groups[] = { "tmu_tclk1_a", @@ -5010,6 +5002,7 @@ static const char * const tpu_groups[] = { "tpu_to2", "tpu_to3", }; +#endif static const char * const usb0_groups[] = { "usb0", @@ -5118,9 +5111,9 @@ static const struct { SH_PFC_FUNCTION(sdhi3), #ifdef CONFIG_PINCTRL_PFC_FULL SH_PFC_FUNCTION(ssi), -#endif SH_PFC_FUNCTION(tmu), SH_PFC_FUNCTION(tpu), +#endif SH_PFC_FUNCTION(usb0), SH_PFC_FUNCTION(usb1), SH_PFC_FUNCTION(usb30), @@ -5129,7 +5122,8 @@ static const struct { SH_PFC_FUNCTION(vin5), #endif }, -#if defined(CONFIG_PINCTRL_PFC_R8A77960) || defined(CONFIG_PINCTRL_PFC_R8A77961) +#if defined(CONFIG_PINCTRL_PFC_FULL) && \ + (defined(CONFIG_PINCTRL_PFC_R8A77960) || defined(CONFIG_PINCTRL_PFC_R8A77961)) .automotive = { SH_PFC_FUNCTION(drif0), SH_PFC_FUNCTION(drif1), -- cgit v1.3.1 From 7feb56b8ef617c3ead531e3aca2f49b3cc2e00f5 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Sun, 21 Jun 2026 04:38:53 +0200 Subject: pinctrl: renesas: Further minimize R8A77965 M3-N PFC tables Reduce the PFC tables further by gating DRIF, MLB, TMU, TPU and SATA behind PINCTRL_PFC_FULL, none of which are currently supported by U-Boot. This helps reduce the size of the bootloader in 4 kiB range. Signed-off-by: Marek Vasut --- drivers/pinctrl/renesas/pfc-r8a77965.c | 28 ++++++++++++++-------------- 1 file changed, 14 insertions(+), 14 deletions(-) diff --git a/drivers/pinctrl/renesas/pfc-r8a77965.c b/drivers/pinctrl/renesas/pfc-r8a77965.c index 9049d762a59..d1c1f562fca 100644 --- a/drivers/pinctrl/renesas/pfc-r8a77965.c +++ b/drivers/pinctrl/renesas/pfc-r8a77965.c @@ -1848,7 +1848,6 @@ static const unsigned int canfd1_data_pins[] = { static const unsigned int canfd1_data_mux[] = { CANFD1_TX_MARK, CANFD1_RX_MARK, }; -#endif #ifdef CONFIG_PINCTRL_PFC_R8A77965 /* - DRIF0 --------------------------------------------------------------- */ @@ -2126,7 +2125,6 @@ static const unsigned int drif3_data1_b_mux[] = { }; #endif /* CONFIG_PINCTRL_PFC_R8A77965 */ -#ifdef CONFIG_PINCTRL_PFC_FULL /* - DU --------------------------------------------------------------------- */ static const unsigned int du_rgb666_pins[] = { /* R[7:2], G[7:2], B[7:2] */ @@ -2616,7 +2614,6 @@ static const unsigned int intc_ex_irq5_pins[] = { static const unsigned int intc_ex_irq5_mux[] = { IRQ5_MARK, }; -#endif #ifdef CONFIG_PINCTRL_PFC_R8A77965 /* - MLB+ ------------------------------------------------------------------- */ @@ -2628,7 +2625,6 @@ static const unsigned int mlb_3pin_mux[] = { }; #endif /* CONFIG_PINCTRL_PFC_R8A77965 */ -#ifdef CONFIG_PINCTRL_PFC_FULL /* - MSIOF0 ----------------------------------------------------------------- */ static const unsigned int msiof0_clk_pins[] = { /* SCK */ @@ -3464,6 +3460,7 @@ static const unsigned int qspi1_data_mux[] = { QSPI1_IO2_MARK, QSPI1_IO3_MARK, }; +#ifdef CONFIG_PINCTRL_PFC_FULL /* - SATA --------------------------------------------------------------------*/ static const unsigned int sata0_devslp_a_pins[] = { /* DEVSLP */ @@ -3482,6 +3479,7 @@ static const unsigned int sata0_devslp_b_pins[] = { static const unsigned int sata0_devslp_b_mux[] = { SATA_DEVSLP_B_MARK, }; +#endif /* - SCIF0 ------------------------------------------------------------------ */ static const unsigned int scif0_data_pins[] = { @@ -4071,7 +4069,6 @@ static const unsigned int ssi9_ctrl_b_pins[] = { static const unsigned int ssi9_ctrl_b_mux[] = { SSI_SCK9_B_MARK, SSI_WS9_B_MARK, }; -#endif /* - TMU -------------------------------------------------------------------- */ static const unsigned int tmu_tclk1_a_pins[] = { @@ -4139,6 +4136,7 @@ static const unsigned int tpu_to3_pins[] = { static const unsigned int tpu_to3_mux[] = { TPU0TO3_MARK, }; +#endif /* - USB0 ------------------------------------------------------------------- */ static const unsigned int usb0_pins[] = { @@ -4588,8 +4586,10 @@ static const struct { SH_PFC_PIN_GROUP(qspi1_ctrl), BUS_DATA_PIN_GROUP(qspi1_data, 2), BUS_DATA_PIN_GROUP(qspi1_data, 4), +#ifdef CONFIG_PINCTRL_PFC_FULL SH_PFC_PIN_GROUP(sata0_devslp_a), SH_PFC_PIN_GROUP(sata0_devslp_b), +#endif SH_PFC_PIN_GROUP(scif0_data), SH_PFC_PIN_GROUP(scif0_clk), SH_PFC_PIN_GROUP(scif0_ctrl), @@ -4671,7 +4671,6 @@ static const struct { SH_PFC_PIN_GROUP(ssi9_data_b), SH_PFC_PIN_GROUP(ssi9_ctrl_a), SH_PFC_PIN_GROUP(ssi9_ctrl_b), -#endif SH_PFC_PIN_GROUP(tmu_tclk1_a), SH_PFC_PIN_GROUP(tmu_tclk1_b), SH_PFC_PIN_GROUP(tmu_tclk2_a), @@ -4680,6 +4679,7 @@ static const struct { SH_PFC_PIN_GROUP(tpu_to1), SH_PFC_PIN_GROUP(tpu_to2), SH_PFC_PIN_GROUP(tpu_to3), +#endif SH_PFC_PIN_GROUP(usb0), SH_PFC_PIN_GROUP(usb1), SH_PFC_PIN_GROUP(usb30), @@ -4714,7 +4714,7 @@ static const struct { SH_PFC_PIN_GROUP(vin5_clk), #endif }, -#ifdef CONFIG_PINCTRL_PFC_R8A77965 +#if defined(CONFIG_PINCTRL_PFC_FULL) && defined(CONFIG_PINCTRL_PFC_R8A77965) .automotive = { SH_PFC_PIN_GROUP(drif0_ctrl_a), SH_PFC_PIN_GROUP(drif0_data0_a), @@ -4809,7 +4809,6 @@ static const char * const canfd0_groups[] = { static const char * const canfd1_groups[] = { "canfd1_data", }; -#endif #ifdef CONFIG_PINCTRL_PFC_R8A77965 static const char * const drif0_groups[] = { @@ -4855,7 +4854,6 @@ static const char * const drif3_groups[] = { }; #endif /* CONFIG_PINCTRL_PFC_R8A77965 */ -#ifdef CONFIG_PINCTRL_PFC_FULL static const char * const du_groups[] = { "du_rgb666", "du_rgb888", @@ -4948,7 +4946,6 @@ static const char * const intc_ex_groups[] = { "intc_ex_irq4", "intc_ex_irq5", }; -#endif #ifdef CONFIG_PINCTRL_PFC_R8A77965 static const char * const mlb_3pin_groups[] = { @@ -4956,7 +4953,6 @@ static const char * const mlb_3pin_groups[] = { }; #endif /* CONFIG_PINCTRL_PFC_R8A77965 */ -#ifdef CONFIG_PINCTRL_PFC_FULL static const char * const msiof0_groups[] = { "msiof0_clk", "msiof0_sync", @@ -5115,10 +5111,12 @@ static const char * const qspi1_groups[] = { "qspi1_data4", }; +#ifdef CONFIG_PINCTRL_PFC_FULL static const char * const sata0_groups[] = { "sata0_devslp_a", "sata0_devslp_b", }; +#endif static const char * const scif0_groups[] = { "scif0_data", @@ -5235,7 +5233,6 @@ static const char * const ssi_groups[] = { "ssi9_ctrl_a", "ssi9_ctrl_b", }; -#endif static const char * const tmu_groups[] = { "tmu_tclk1_a", @@ -5250,6 +5247,7 @@ static const char * const tpu_groups[] = { "tpu_to2", "tpu_to3", }; +#endif static const char * const usb0_groups[] = { "usb0", @@ -5345,7 +5343,9 @@ static const struct { #endif SH_PFC_FUNCTION(qspi0), SH_PFC_FUNCTION(qspi1), +#ifdef CONFIG_PINCTRL_PFC_FULL SH_PFC_FUNCTION(sata0), +#endif SH_PFC_FUNCTION(scif0), SH_PFC_FUNCTION(scif1), SH_PFC_FUNCTION(scif2), @@ -5359,9 +5359,9 @@ static const struct { SH_PFC_FUNCTION(sdhi3), #ifdef CONFIG_PINCTRL_PFC_FULL SH_PFC_FUNCTION(ssi), -#endif SH_PFC_FUNCTION(tmu), SH_PFC_FUNCTION(tpu), +#endif SH_PFC_FUNCTION(usb0), SH_PFC_FUNCTION(usb1), SH_PFC_FUNCTION(usb30), @@ -5370,7 +5370,7 @@ static const struct { SH_PFC_FUNCTION(vin5), #endif }, -#ifdef CONFIG_PINCTRL_PFC_R8A77965 +#if defined(CONFIG_PINCTRL_PFC_FULL) && defined(CONFIG_PINCTRL_PFC_R8A77965) .automotive = { SH_PFC_FUNCTION(drif0), SH_PFC_FUNCTION(drif1), -- cgit v1.3.1 From 8fa2ad1a2c66502cb4eb154c384a67996ab46c2a Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Sun, 21 Jun 2026 04:38:22 +0200 Subject: arm: dts: renesas: Remove unused OPP nodes from R-Car H3/M3-W/M3-W+/M3-N Remove OPP DT nodes from R-Car H3, M3-W, M3-W+ and M3-N DTs, those nodes are not used by U-Boot and only increase the control DT size and complexity. This saves about 1 kiB on the resulting U-Boot binary without any impact on functionality. Signed-off-by: Marek Vasut --- arch/arm/dts/r8a77951-u-boot.dtsi | 34 ++++++++++++++++++++++++++++++++++ arch/arm/dts/r8a77960-u-boot.dtsi | 26 ++++++++++++++++++++++++++ arch/arm/dts/r8a77965-u-boot.dtsi | 9 +++++++++ 3 files changed, 69 insertions(+) diff --git a/arch/arm/dts/r8a77951-u-boot.dtsi b/arch/arm/dts/r8a77951-u-boot.dtsi index e8a7fa27a76..0c00cc8bef9 100644 --- a/arch/arm/dts/r8a77951-u-boot.dtsi +++ b/arch/arm/dts/r8a77951-u-boot.dtsi @@ -11,6 +11,8 @@ /delete-node/ &can0; /delete-node/ &can1; /delete-node/ &canfd; +/delete-node/ &cluster0_opp; +/delete-node/ &cluster1_opp; /delete-node/ &csi20; /delete-node/ &csi40; /delete-node/ &csi41; @@ -62,6 +64,38 @@ /delete-node/ vga; }; +&a53_0 { + /delete-property/ operating-points-v2; +}; + +&a53_1 { + /delete-property/ operating-points-v2; +}; + +&a53_2 { + /delete-property/ operating-points-v2; +}; + +&a53_3 { + /delete-property/ operating-points-v2; +}; + +&a57_0 { + /delete-property/ operating-points-v2; +}; + +&a57_1 { + /delete-property/ operating-points-v2; +}; + +&a57_2 { + /delete-property/ operating-points-v2; +}; + +&a57_3 { + /delete-property/ operating-points-v2; +}; + &i2c4 { /delete-node/ video-receiver@70; }; diff --git a/arch/arm/dts/r8a77960-u-boot.dtsi b/arch/arm/dts/r8a77960-u-boot.dtsi index b437792a172..2a8c5a96390 100644 --- a/arch/arm/dts/r8a77960-u-boot.dtsi +++ b/arch/arm/dts/r8a77960-u-boot.dtsi @@ -11,6 +11,8 @@ /delete-node/ &can0; /delete-node/ &can1; /delete-node/ &canfd; +/delete-node/ &cluster0_opp; +/delete-node/ &cluster1_opp; /delete-node/ &csi20; /delete-node/ &csi40; /delete-node/ &drif00; @@ -70,3 +72,27 @@ /delete-node/ imr-lx4@fe890000; }; }; + +&a53_0 { + /delete-property/ operating-points-v2; +}; + +&a53_1 { + /delete-property/ operating-points-v2; +}; + +&a53_2 { + /delete-property/ operating-points-v2; +}; + +&a53_3 { + /delete-property/ operating-points-v2; +}; + +&a57_0 { + /delete-property/ operating-points-v2; +}; + +&a57_1 { + /delete-property/ operating-points-v2; +}; diff --git a/arch/arm/dts/r8a77965-u-boot.dtsi b/arch/arm/dts/r8a77965-u-boot.dtsi index 57382e34912..6eb7bbeed26 100644 --- a/arch/arm/dts/r8a77965-u-boot.dtsi +++ b/arch/arm/dts/r8a77965-u-boot.dtsi @@ -11,6 +11,7 @@ /delete-node/ &can0; /delete-node/ &can1; /delete-node/ &canfd; +/delete-node/ &cluster0_opp; /delete-node/ &csi20; /delete-node/ &csi40; /delete-node/ &du; @@ -60,3 +61,11 @@ /delete-node/ imr-lx4@fe890000; }; }; + +&a57_0 { + /delete-property/ operating-points-v2; +}; + +&a57_1 { + /delete-property/ operating-points-v2; +}; -- cgit v1.3.1