From 24308102cdce8301e10600b112ed68028fde7cd7 Mon Sep 17 00:00:00 2001 From: Padmarao Begari Date: Tue, 4 Nov 2025 18:27:25 +0530 Subject: board: xilinx: Update ESRT after copying GUID The EFI System Resource Table (ESRT) is updated after the firmware image GUID is copied to the fw_images structure. This ensures that the ESRT accurately reflects the current firmware resources. Signed-off-by: Padmarao Begari Signed-off-by: Michal Simek Link: https://lore.kernel.org/r/20251104125725.1628068-1-padmarao.begari@amd.com --- board/xilinx/common/board.c | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/board/xilinx/common/board.c b/board/xilinx/common/board.c index 26facb6daea..ab50a795e6b 100644 --- a/board/xilinx/common/board.c +++ b/board/xilinx/common/board.c @@ -766,6 +766,17 @@ int fwu_platform_hook(struct udevice *dev, struct fwu_data *data) /* Copy image type GUID */ memcpy(&fw_images[0].image_type_id, &img_entry->image_type_guid, 16); + if (IS_ENABLED(CONFIG_EFI_ESRT)) { + efi_status_t ret; + + /* Rebuild the ESRT to reflect any updated FW images. */ + ret = efi_esrt_populate(); + if (ret != EFI_SUCCESS) { + log_warning("ESRT update failed\n"); + return ret; + } + } + return 0; } -- cgit v1.3.1 From 16f0332b180321c1c0a2f8decc6005e37202bcc9 Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Fri, 7 Nov 2025 11:28:49 +0100 Subject: clk: versal: Use __data macro for moving variable to data section The commit 1b267fe1824e ("firmware: xilinx: Prepare code for new SMC firmware format") introduce new __data macro that's why use it in clock driver too. Signed-off-by: Michal Simek Link: https://lore.kernel.org/r/eac8d0ab60a018d6c59aa28c49691839a3eec174.1762511327.git.michal.simek@amd.com --- drivers/clk/clk_versal.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/drivers/clk/clk_versal.c b/drivers/clk/clk_versal.c index c62a747036d..0c754943ded 100644 --- a/drivers/clk/clk_versal.c +++ b/drivers/clk/clk_versal.c @@ -106,8 +106,8 @@ struct versal_clk_priv { struct versal_clock *clk; }; -static ulong pl_alt_ref_clk __section(".data"); -static ulong ref_clk __section(".data"); +static ulong __data pl_alt_ref_clk; +static ulong __data ref_clk; struct versal_pm_query_data { u32 qid; @@ -116,8 +116,8 @@ struct versal_pm_query_data { u32 arg3; }; -static struct versal_clock *clock __section(".data"); -static unsigned int clock_max_idx __section(".data"); +static struct versal_clock __data *clock; +static unsigned int __data clock_max_idx; #define PM_QUERY_DATA 35 -- cgit v1.3.1 From 2b7255cfa06ccd967583b035622476a42043131e Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Mon, 10 Nov 2025 13:33:32 +0100 Subject: clk: versal: Add support for CLK_AUTO_ID When CLK_AUTO_ID is enabled 8 higher bits of clk->id is unique clock identifier in clk uclass that's why it is necessary to mask lower bits which are clock ID. Also check that ID not bigger then maximum supported clock. Signed-off-by: Michal Simek Link: https://lore.kernel.org/r/647f1d2c7d274c1106558a655386ef92e0baf2c8.1762778011.git.michal.simek@amd.com --- drivers/clk/clk_versal.c | 16 +++++++++++++--- 1 file changed, 13 insertions(+), 3 deletions(-) diff --git a/drivers/clk/clk_versal.c b/drivers/clk/clk_versal.c index 0c754943ded..ddaff07de0f 100644 --- a/drivers/clk/clk_versal.c +++ b/drivers/clk/clk_versal.c @@ -712,10 +712,13 @@ static int versal_clk_probe(struct udevice *dev) static ulong versal_clk_get_rate(struct clk *clk) { struct versal_clk_priv *priv = dev_get_priv(clk->dev); - u32 id = clk->id; + u32 id = clk_get_id(clk); u32 clk_id; u64 clk_rate = 0; + if (id >= clock_max_idx) + return -ENODEV; + debug("%s\n", __func__); clk_id = priv->clk[id].clk_id; @@ -728,7 +731,7 @@ static ulong versal_clk_get_rate(struct clk *clk) static ulong versal_clk_set_rate(struct clk *clk, ulong rate) { struct versal_clk_priv *priv = dev_get_priv(clk->dev); - u32 id = clk->id; + u32 id = clk_get_id(clk); u32 clk_id; u64 clk_rate = 0; u32 div; @@ -736,6 +739,9 @@ static ulong versal_clk_set_rate(struct clk *clk, ulong rate) debug("%s\n", __func__); + if (id >= clock_max_idx) + return -ENODEV; + clk_id = priv->clk[id].clk_id; ret = versal_clock_get_rate(clk_id, &clk_rate); @@ -766,9 +772,13 @@ static ulong versal_clk_set_rate(struct clk *clk, ulong rate) static int versal_clk_enable(struct clk *clk) { struct versal_clk_priv *priv = dev_get_priv(clk->dev); + u32 id = clk_get_id(clk); u32 clk_id; - clk_id = priv->clk[clk->id].clk_id; + if (id >= clock_max_idx) + return -ENODEV; + + clk_id = priv->clk[id].clk_id; if (versal_clock_gate(clk_id)) { return xilinx_pm_request(PM_CLOCK_ENABLE, clk_id, 0, 0, 0, -- cgit v1.3.1 From ac9494e96bd07a78d0f22ed24a03b06ba1f7b77d Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Mon, 10 Nov 2025 13:33:33 +0100 Subject: clk: versal: Cleanup driver Remove unneeded debug messages, parenthesis and fix error message. Signed-off-by: Michal Simek Link: https://lore.kernel.org/r/5b6fbcff1025415adc97e3e17eeb18863df4383e.1762778011.git.michal.simek@amd.com --- drivers/clk/clk_versal.c | 9 ++------- 1 file changed, 2 insertions(+), 7 deletions(-) diff --git a/drivers/clk/clk_versal.c b/drivers/clk/clk_versal.c index ddaff07de0f..4a498e22f96 100644 --- a/drivers/clk/clk_versal.c +++ b/drivers/clk/clk_versal.c @@ -719,8 +719,6 @@ static ulong versal_clk_get_rate(struct clk *clk) if (id >= clock_max_idx) return -ENODEV; - debug("%s\n", __func__); - clk_id = priv->clk[id].clk_id; versal_clock_get_rate(clk_id, &clk_rate); @@ -737,8 +735,6 @@ static ulong versal_clk_set_rate(struct clk *clk, ulong rate) u32 div; int ret; - debug("%s\n", __func__); - if (id >= clock_max_idx) return -ENODEV; @@ -764,7 +760,7 @@ static ulong versal_clk_set_rate(struct clk *clk, ulong rate) } while (((clk_id >> NODE_SUBCLASS_SHIFT) & NODE_CLASS_MASK) != NODE_SUBCLASS_CLOCK_REF); - printf("Clock didn't has Divisors:0x%x\n", priv->clk[id].clk_id); + printf("Clock has no divider: 0x%x\n", clk_id); return clk_rate; } @@ -780,10 +776,9 @@ static int versal_clk_enable(struct clk *clk) clk_id = priv->clk[id].clk_id; - if (versal_clock_gate(clk_id)) { + if (versal_clock_gate(clk_id)) return xilinx_pm_request(PM_CLOCK_ENABLE, clk_id, 0, 0, 0, 0, 0, NULL); - } return 0; } -- cgit v1.3.1 From a078ebb86f6c414f12aa132fc6d15c4946fedad0 Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Mon, 10 Nov 2025 16:24:12 +0100 Subject: firmware: xilinx: Add support for enhancement SMC format Versal Gen 2 is using different SMC format that's why firmware and clock drivers needs to be align with it. Signed-off-by: Michal Simek Link: https://lore.kernel.org/r/16bdee56fd75113c6d531bae7a8a34900b10280d.1762788250.git.michal.simek@amd.com --- drivers/firmware/firmware-zynqmp.c | 34 ++++++++++++++++++++++++++++++++++ include/zynqmp_firmware.h | 6 ++++++ 2 files changed, 40 insertions(+) diff --git a/drivers/firmware/firmware-zynqmp.c b/drivers/firmware/firmware-zynqmp.c index 3742467caee..2ef499bf408 100644 --- a/drivers/firmware/firmware-zynqmp.c +++ b/drivers/firmware/firmware-zynqmp.c @@ -16,6 +16,7 @@ #include #include #include +#include #if defined(CONFIG_ZYNQMP_IPI) #include @@ -451,6 +452,38 @@ static int smc_call_legacy(u32 api_id, u32 arg0, u32 arg1, u32 arg2, return (ret_payload) ? ret_payload[0] : 0; } +static int smc_call_enhanced(u32 api_id, u32 arg0, u32 arg1, u32 arg2, + u32 arg3, u32 arg4, u32 arg5, u32 *ret_payload) +{ + struct pt_regs regs; + u32 module_id = FIELD_GET(PLM_MODULE_ID_MASK, api_id); + + if (module_id == 0) + module_id = PM_MODULE_ID; + + regs.regs[0] = PM_SIP_SVC | PASS_THROUGH_FW_CMD_ID; + regs.regs[1] = ((u64)arg0 << 32U) | + FIELD_PREP(PLM_MODULE_ID_MASK, module_id) | + (api_id & API_ID_MASK); + regs.regs[2] = arg1 | ((u64)arg2 << 32); + regs.regs[3] = arg3 | ((u64)arg4 << 32); + regs.regs[4] = arg5; + + smc_call(®s); + + if (ret_payload) { + ret_payload[0] = regs.regs[0]; + ret_payload[1] = upper_32_bits(regs.regs[0]); + ret_payload[2] = (u32)regs.regs[1]; + ret_payload[3] = upper_32_bits(regs.regs[1]); + ret_payload[4] = (u32)regs.regs[2]; + ret_payload[5] = upper_32_bits((u32)regs.regs[2]); + ret_payload[6] = (u32)regs.regs[3]; + } + + return regs.regs[0]; +} + int __maybe_unused xilinx_pm_request(u32 api_id, u32 arg0, u32 arg1, u32 arg2, u32 arg3, u32 arg4, u32 arg5, u32 *ret_payload) { @@ -494,6 +527,7 @@ static const struct udevice_id zynqmp_firmware_ids[] = { { .compatible = "xlnx,zynqmp-firmware", .data = (ulong)smc_call_legacy }, { .compatible = "xlnx,versal-firmware", .data = (ulong)smc_call_legacy}, { .compatible = "xlnx,versal-net-firmware", .data = (ulong)smc_call_legacy }, + { .compatible = "xlnx,versal2-firmware", .data = (ulong)smc_call_enhanced}, { } }; diff --git a/include/zynqmp_firmware.h b/include/zynqmp_firmware.h index 7f93241b193..72f6459b91c 100644 --- a/include/zynqmp_firmware.h +++ b/include/zynqmp_firmware.h @@ -521,4 +521,10 @@ typedef int (*smc_call_handler_t)(u32 api_id, u32 arg0, u32 arg1, u32 arg2, extern smc_call_handler_t __data smc_call_handler; +#define PM_MODULE_ID 2 + +#define PASS_THROUGH_FW_CMD_ID GENMASK(11, 0) +#define PLM_MODULE_ID_MASK GENMASK(15, 8) +#define API_ID_MASK GENMASK(7, 0) + #endif /* _ZYNQMP_FIRMWARE_H_ */ -- cgit v1.3.1 From 7c1e03704830d607935487e3b6c710f063dbe9e8 Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Mon, 10 Nov 2025 16:24:13 +0100 Subject: clk: versal: Enable clock driver for Versal Gen 2 Versal Gen 2 is using enhancement SMC format but in near future SCMI client should be used. This patch is just bridging this gap till SCMI server is fully tested. Signed-off-by: Michal Simek Link: https://lore.kernel.org/r/e83c665408d1453a464dd02cd2a25bb0ed267131.1762788250.git.michal.simek@amd.com --- configs/amd_versal2_virt_defconfig | 1 + drivers/clk/Kconfig | 2 +- drivers/clk/clk_versal.c | 20 ++++++++++++++++++++ 3 files changed, 22 insertions(+), 1 deletion(-) diff --git a/configs/amd_versal2_virt_defconfig b/configs/amd_versal2_virt_defconfig index caf4aefe898..4f0c4ba5c96 100644 --- a/configs/amd_versal2_virt_defconfig +++ b/configs/amd_versal2_virt_defconfig @@ -75,6 +75,7 @@ CONFIG_NET_RANDOM_ETHADDR=y CONFIG_SIMPLE_PM_BUS=y CONFIG_CLK_CCF=y CONFIG_CLK_SCMI=y +CONFIG_CLK_VERSAL=y CONFIG_DFU_RAM=y CONFIG_ARM_FFA_TRANSPORT=y CONFIG_FPGA_XILINX=y diff --git a/drivers/clk/Kconfig b/drivers/clk/Kconfig index b884a02bdeb..85cc472b4cb 100644 --- a/drivers/clk/Kconfig +++ b/drivers/clk/Kconfig @@ -224,7 +224,7 @@ config CLK_VERSACLOCK config CLK_VERSAL bool "Enable clock driver support for Versal" - depends on (ARCH_VERSAL || ARCH_VERSAL_NET) + depends on (ARCH_VERSAL || ARCH_VERSAL_NET || ARCH_VERSAL2) depends on ZYNQMP_FIRMWARE help This clock driver adds support for clock realted settings for diff --git a/drivers/clk/clk_versal.c b/drivers/clk/clk_versal.c index 4a498e22f96..78a2410ca21 100644 --- a/drivers/clk/clk_versal.c +++ b/drivers/clk/clk_versal.c @@ -136,6 +136,25 @@ static int versal_pm_query_legacy(struct versal_pm_query_data qdata, return qdata.qid == PM_QID_CLOCK_GET_NAME ? 0 : ret; } +static int versal_pm_query_enhanced(struct versal_pm_query_data qdata, + u32 *ret_payload) +{ + int ret; + + ret = smc_call_handler(PM_QUERY_DATA, qdata.qid, qdata.arg1, qdata.arg2, + qdata.arg3, 0, 0, ret_payload); + + if (qdata.qid == PM_QID_CLOCK_GET_NAME) { + ret_payload[0] = ret_payload[1]; + ret_payload[1] = ret_payload[2]; + ret_payload[2] = ret_payload[3]; + ret_payload[3] = ret_payload[4]; + ret_payload[4] = 0; + } + + return ret; +} + static inline int versal_is_valid_clock(u32 clk_id) { if (clk_id >= clock_max_idx) @@ -794,6 +813,7 @@ static struct clk_ops versal_clk_ops = { static const struct udevice_id versal_clk_ids[] = { { .compatible = "xlnx,versal-clk", .data = (ulong)versal_pm_query_legacy }, + { .compatible = "xlnx,versal2-clk", .data = (ulong)versal_pm_query_enhanced }, { } }; -- cgit v1.3.1 From 55e097ec88af7d28eb4cdb67000ac8b7a7543e74 Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Mon, 10 Nov 2025 16:19:56 +0100 Subject: spi: cadence: Remove cdns,is-dma DT property cdns,is-dma is not documented property that's why setup CQSPI_DMA_MODE quirk to enable DMA mode based on compatible string. And also change compatible string for mini configurations also with recording compatible string in the driver (Compatible string is already the part of existing DT binding). Signed-off-by: Michal Simek Link: https://lore.kernel.org/r/f109829793900e57558d98ed22caf80c1a72b232.1762787994.git.michal.simek@amd.com --- arch/arm/dts/versal-mini-ospi.dtsi | 3 +-- arch/arm/dts/versal-net-mini-ospi.dtsi | 3 +-- drivers/spi/cadence_qspi.c | 20 ++++++++++++++++---- drivers/spi/cadence_qspi.h | 2 -- 4 files changed, 18 insertions(+), 10 deletions(-) diff --git a/arch/arm/dts/versal-mini-ospi.dtsi b/arch/arm/dts/versal-mini-ospi.dtsi index eec2a08e7c7..8429dc585d5 100644 --- a/arch/arm/dts/versal-mini-ospi.dtsi +++ b/arch/arm/dts/versal-mini-ospi.dtsi @@ -29,7 +29,7 @@ }; ospi: spi@f1010000 { - compatible = "cdns,qspi-nor"; + compatible = "xlnx,versal-ospi-1.0", "cdns,qspi-nor"; status = "okay"; reg = <0 0xf1010000 0 0x10000 0 0xc0000000 0 0x20000000>; clock-names = "ref_clk", "pclk"; @@ -38,7 +38,6 @@ num-cs = <1>; cdns,fifo-depth = <256>; cdns,fifo-width = <4>; - cdns,is-dma = <1>; cdns,trigger-address = <0xc0000000>; #address-cells = <1>; #size-cells = <0>; diff --git a/arch/arm/dts/versal-net-mini-ospi.dtsi b/arch/arm/dts/versal-net-mini-ospi.dtsi index 1c94b352dc9..78404960f2f 100644 --- a/arch/arm/dts/versal-net-mini-ospi.dtsi +++ b/arch/arm/dts/versal-net-mini-ospi.dtsi @@ -43,7 +43,7 @@ }; ospi: spi@f1010000 { - compatible = "cdns,qspi-nor"; + compatible = "xlnx,versal-ospi-1.0", "cdns,qspi-nor"; status = "okay"; reg = <0 0xf1010000 0 0x10000>, <0 0xc0000000 0 0x20000000>; clock-names = "ref_clk", "pclk"; @@ -52,7 +52,6 @@ num-cs = <1>; cdns,fifo-depth = <256>; cdns,fifo-width = <4>; - cdns,is-dma = <1>; cdns,is-stig-pgm = <1>; cdns,trigger-address = <0xc0000000>; #address-cells = <1>; diff --git a/drivers/spi/cadence_qspi.c b/drivers/spi/cadence_qspi.c index 9b45cab9c04..892dc3557a5 100644 --- a/drivers/spi/cadence_qspi.c +++ b/drivers/spi/cadence_qspi.c @@ -29,6 +29,7 @@ /* Quirks */ #define CQSPI_DISABLE_STIG_MODE BIT(0) +#define CQSPI_DMA_MODE BIT(1) __weak int cadence_qspi_apb_dma_read(struct cadence_spi_priv *priv, const struct spi_mem_op *op) @@ -210,7 +211,6 @@ static int cadence_spi_probe(struct udevice *bus) priv->regbase = plat->regbase; priv->ahbbase = plat->ahbbase; - priv->is_dma = plat->is_dma; priv->is_decoded_cs = plat->is_decoded_cs; priv->fifo_depth = plat->fifo_depth; priv->fifo_width = plat->fifo_width; @@ -227,6 +227,11 @@ static int cadence_spi_probe(struct udevice *bus) priv->tslch_ns = plat->tslch_ns; priv->quirks = plat->quirks; + if (priv->quirks & CQSPI_DMA_MODE) { + priv->is_dma = true; + debug("Cadence QSPI: DMA mode enabled\n"); + } + if (IS_ENABLED(CONFIG_ZYNQMP_FIRMWARE)) xilinx_pm_request(PM_REQUEST_NODE, PM_DEV_OSPI, ZYNQMP_PM_CAPABILITY_ACCESS, ZYNQMP_PM_MAX_QOS, @@ -412,8 +417,6 @@ static int cadence_spi_of_to_plat(struct udevice *bus) if (plat->ahbsize >= SZ_8M) priv->use_dac_mode = true; - plat->is_dma = dev_read_bool(bus, "cdns,is-dma"); - /* All other parameters are embedded in the child node */ subnode = cadence_qspi_get_subnode(bus); if (!ofnode_valid(subnode)) { @@ -473,6 +476,10 @@ static const struct cqspi_driver_platdata cdns_qspi = { .quirks = CQSPI_DISABLE_STIG_MODE, }; +static const struct cqspi_driver_platdata cdns_xilinx_qspi = { + .quirks = CQSPI_DMA_MODE, +}; + static const struct udevice_id cadence_spi_ids[] = { { .compatible = "cdns,qspi-nor", @@ -482,7 +489,12 @@ static const struct udevice_id cadence_spi_ids[] = { .compatible = "ti,am654-ospi" }, { - .compatible = "amd,versal2-ospi" + .compatible = "amd,versal2-ospi", + .data = (ulong)&cdns_xilinx_qspi, + }, + { + .compatible = "xlnx,versal-ospi-1.0", + .data = (ulong)&cdns_xilinx_qspi, }, { } }; diff --git a/drivers/spi/cadence_qspi.h b/drivers/spi/cadence_qspi.h index 879e7f8dbfb..1e9081c2d17 100644 --- a/drivers/spi/cadence_qspi.h +++ b/drivers/spi/cadence_qspi.h @@ -223,8 +223,6 @@ struct cadence_spi_plat { u32 tchsh_ns; u32 tslch_ns; u32 quirks; - - bool is_dma; }; struct cadence_spi_priv { -- cgit v1.3.1 From b2a8ac78202ec5c3917fc8f635fdd4abc6ce752c Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Wed, 19 Nov 2025 12:32:38 +0100 Subject: arm64: xilinx: Remove unnecessary #address/size-cells GEMs are using mdio node that's why don't need cells description in the node. SPIs should be using partitions subnode that's why don't need to have cells description in the node Also no need to specify cells in DT overlay root node when there is no child which needs it. Signed-off-by: Michal Simek Link: https://lore.kernel.org/r/7612a3817480f4089aea3e14cca07d585f8fddb5.1763551956.git.michal.simek@amd.com --- arch/arm/dts/zynqmp-sc-vn-p-b2197-00-revA.dtso | 3 --- 1 file changed, 3 deletions(-) diff --git a/arch/arm/dts/zynqmp-sc-vn-p-b2197-00-revA.dtso b/arch/arm/dts/zynqmp-sc-vn-p-b2197-00-revA.dtso index c1945ea6f8d..5a4e5f09250 100644 --- a/arch/arm/dts/zynqmp-sc-vn-p-b2197-00-revA.dtso +++ b/arch/arm/dts/zynqmp-sc-vn-p-b2197-00-revA.dtso @@ -13,9 +13,6 @@ /plugin/; &{/} { - #address-cells = <2>; - #size-cells = <2>; - compatible = "xlnx,zynqmp-sc-vn-p-b2197-revA", "xlnx,zynqmp-sc-vn-p-b2197", "xlnx,zynqmp"; -- cgit v1.3.1 From 66a9a431ee62c90762f919c038b54393c7fa5bd8 Mon Sep 17 00:00:00 2001 From: Padmarao Begari Date: Wed, 19 Nov 2025 09:50:23 +0100 Subject: board: xilinx: Retry FRU EEPROM read on timeout Wrap the dm_i2c_read() call is used for FRU EEPROM reads in a retry loop, attempting up to EEPROM_FRU_READ_RETRY times if a -ETIMEDOUT error is returned. The loop exits immediately on success or any error other than -ETIMEDOUT. This improves robustness against transient I2C timeouts during FRU detection and decoding. Signed-off-by: Padmarao Begari Reviewed-by: Matthias Brugger Signed-off-by: Michal Simek Link: https://lore.kernel.org/r/9556d204c351d2dc40176a31dab11f789fd1cc7f.1763542221.git.michal.simek@amd.com --- board/xilinx/common/board.c | 12 ++++++++++-- 1 file changed, 10 insertions(+), 2 deletions(-) diff --git a/board/xilinx/common/board.c b/board/xilinx/common/board.c index ab50a795e6b..d022308f943 100644 --- a/board/xilinx/common/board.c +++ b/board/xilinx/common/board.c @@ -70,6 +70,8 @@ struct efi_capsule_update_info update_info = { #define EEPROM_HDR_ETH_ALEN ETH_ALEN #define EEPROM_HDR_UUID_LEN 16 +#define EEPROM_FRU_READ_RETRY 5 + struct xilinx_board_description { u32 header; char manufacturer[EEPROM_HDR_MANUFACTURER_LEN + 1]; @@ -207,8 +209,14 @@ static int xilinx_read_eeprom_fru(struct udevice *dev, char *name, debug("%s: I2C EEPROM read pass data at %p\n", __func__, fru_content); - ret = dm_i2c_read(dev, 0, (uchar *)fru_content, - eeprom_size); + i = 0; + do { + ret = dm_i2c_read(dev, 0, (uchar *)fru_content, + eeprom_size); + if (!ret) + break; + } while (++i < EEPROM_FRU_READ_RETRY && ret == -ETIMEDOUT); + if (ret) { debug("%s: I2C EEPROM read failed\n", __func__); goto end; -- cgit v1.3.1 From 16eaf907d5808c6b2ab6a7814d72d8277f3e7e44 Mon Sep 17 00:00:00 2001 From: Venkatesh Yadav Abbarapu Date: Wed, 26 Nov 2025 16:09:41 +0100 Subject: common: memtop: Update the MEM_RGN_COUNT macro to 64 Crashes are occurring due to the number of reserved memory regions exceeding the current maximum limit of 16. It is recommended to increase the supported number of memory regions to 64, as newer platforms may utilize more reserved regions. Signed-off-by: Venkatesh Yadav Abbarapu Signed-off-by: Michal Simek Link: https://lore.kernel.org/r/d9f73d26af832e19dfd79a4b7bfcf09c498a4873.1764169780.git.michal.simek@amd.com --- common/memtop.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/common/memtop.c b/common/memtop.c index bff27d8211e..8ad394193f3 100644 --- a/common/memtop.c +++ b/common/memtop.c @@ -9,7 +9,7 @@ #include -#define MEM_RGN_COUNT 16 +#define MEM_RGN_COUNT 64 struct region { phys_addr_t base; -- cgit v1.3.1 From 358b5e62018eb7a1881cfd9e22b50abf5daa45de Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Wed, 26 Nov 2025 16:23:43 +0100 Subject: xilinx: amd: Enable the PCA9541 I2C Bus arbiter Enable the new PCA9541 i2c bus arbiter on AMD/Xilinx SOCs by default. Signed-off-by: Michal Simek Link: https://lore.kernel.org/r/edfb7e7a6e800484d3ac3bf45a4f83adfcdd1754.1764170621.git.michal.simek@amd.com --- configs/amd_versal2_virt_defconfig | 1 + configs/xilinx_versal_virt_defconfig | 1 + configs/xilinx_zynqmp_virt_defconfig | 1 + 3 files changed, 3 insertions(+) diff --git a/configs/amd_versal2_virt_defconfig b/configs/amd_versal2_virt_defconfig index 4f0c4ba5c96..416128fa937 100644 --- a/configs/amd_versal2_virt_defconfig +++ b/configs/amd_versal2_virt_defconfig @@ -83,6 +83,7 @@ CONFIG_FPGA_VERSALPL=y CONFIG_DM_I2C=y CONFIG_SYS_I2C_CADENCE=y CONFIG_I2C_MUX=y +CONFIG_I2C_MUX_PCA9541=y CONFIG_I2C_MUX_PCA954x=y CONFIG_DM_MAILBOX=y CONFIG_ZYNQMP_IPI=y diff --git a/configs/xilinx_versal_virt_defconfig b/configs/xilinx_versal_virt_defconfig index bd6bfb7deac..652121e27a0 100644 --- a/configs/xilinx_versal_virt_defconfig +++ b/configs/xilinx_versal_virt_defconfig @@ -89,6 +89,7 @@ CONFIG_FPGA_VERSALPL=y CONFIG_DM_I2C=y CONFIG_SYS_I2C_CADENCE=y CONFIG_I2C_MUX=y +CONFIG_I2C_MUX_PCA9541=y CONFIG_I2C_MUX_PCA954x=y CONFIG_DM_MAILBOX=y CONFIG_ZYNQMP_IPI=y diff --git a/configs/xilinx_zynqmp_virt_defconfig b/configs/xilinx_zynqmp_virt_defconfig index 525744b0f61..fc610fd4af5 100644 --- a/configs/xilinx_zynqmp_virt_defconfig +++ b/configs/xilinx_zynqmp_virt_defconfig @@ -140,6 +140,7 @@ CONFIG_SLG7XL45106_I2C_GPO=y CONFIG_DM_I2C=y CONFIG_SYS_I2C_CADENCE=y CONFIG_I2C_MUX=y +CONFIG_I2C_MUX_PCA9541=y CONFIG_I2C_MUX_PCA954x=y CONFIG_LED=y CONFIG_LED_GPIO=y -- cgit v1.3.1 From 9d5b4f63beb65d9b9a8767d76f098a29ddeeb537 Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Wed, 26 Nov 2025 16:23:44 +0100 Subject: arm64: versal2: Enable USB5744 usb hub USB hub is available on the first evaluation board called vek385. Signed-off-by: Michal Simek Link: https://lore.kernel.org/r/4cd72e28bc0e2a9720fe5481dcab2e923d708b34.1764170621.git.michal.simek@amd.com --- configs/amd_versal2_virt_defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/configs/amd_versal2_virt_defconfig b/configs/amd_versal2_virt_defconfig index 416128fa937..c3893fa833a 100644 --- a/configs/amd_versal2_virt_defconfig +++ b/configs/amd_versal2_virt_defconfig @@ -149,6 +149,7 @@ CONFIG_USB_XHCI_DWC3=y CONFIG_USB_DWC3=y CONFIG_USB_DWC3_GENERIC=y CONFIG_USB_ULPI=y +CONFIG_USB_ONBOARD_HUB=y CONFIG_USB_GADGET=y CONFIG_USB_GADGET_MANUFACTURER="Xilinx" CONFIG_USB_GADGET_VENDOR_NUM=0x03FD -- cgit v1.3.1 From a4b96effecfb6df4a94ef615933fe55e56e7bbe9 Mon Sep 17 00:00:00 2001 From: Venkatesh Yadav Abbarapu Date: Wed, 26 Nov 2025 16:23:45 +0100 Subject: arm64: versal2: Update the text base and dtb address Update the TEXT_BASE and DTB address as per the new memory map. Signed-off-by: Venkatesh Yadav Abbarapu Signed-off-by: Michal Simek Link: https://lore.kernel.org/r/6c6eeab25c8bc8739127fb40e1a941920d04fc77.1764170621.git.michal.simek@amd.com --- configs/amd_versal2_virt_defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/configs/amd_versal2_virt_defconfig b/configs/amd_versal2_virt_defconfig index c3893fa833a..ce633dfc61a 100644 --- a/configs/amd_versal2_virt_defconfig +++ b/configs/amd_versal2_virt_defconfig @@ -11,6 +11,7 @@ CONFIG_OF_LIBFDT_OVERLAY=y CONFIG_DM_RESET=y CONFIG_SYS_BOOTM_LEN=0x6400000 CONFIG_SYS_LOAD_ADDR=0x8000000 +CONFIG_XILINX_OF_BOARD_DTB_ADDR=0x1000000 CONFIG_CMD_FRU=y CONFIG_SYS_MEMTEST_START=0x00000000 CONFIG_SYS_MEMTEST_END=0x00001000 -- cgit v1.3.1 From b869d31797513cd466d581378334e0de680e6004 Mon Sep 17 00:00:00 2001 From: Venkatesh Yadav Abbarapu Date: Wed, 26 Nov 2025 16:23:46 +0100 Subject: arm64: versal2: Enable reset and poweroff via sysreset framework reset and poweroff are called via hooks in psci driver which is going around sysreset framework that's why enable sysreset drivers and do reset and poweroff via this framework. Signed-off-by: Venkatesh Yadav Abbarapu Signed-off-by: Michal Simek Link: https://lore.kernel.org/r/a0b13b17fbf99fd16341b68b649ec08ef2b3536a.1764170621.git.michal.simek@amd.com --- configs/amd_versal2_virt_defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/configs/amd_versal2_virt_defconfig b/configs/amd_versal2_virt_defconfig index ce633dfc61a..0344089030c 100644 --- a/configs/amd_versal2_virt_defconfig +++ b/configs/amd_versal2_virt_defconfig @@ -139,6 +139,7 @@ CONFIG_ZYNQ_SPI=y CONFIG_ZYNQMP_GQSPI=y CONFIG_SPI_STACKED_PARALLEL=y CONFIG_SYSRESET=y +CONFIG_SYSRESET_CMD_POWEROFF=y CONFIG_SYSRESET_PSCI=y CONFIG_TEE=y CONFIG_OPTEE=y -- cgit v1.3.1 From 857a3b49c36e3fc53c4a5e1280216359ab2b92bf Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Wed, 26 Nov 2025 19:15:39 +0100 Subject: cadence_qspi: Remove duplicated return The commit 6d234a79e9eb ("cadence_qspi: Refactor the flash reset functionality") introduced two returns in cadence_spi_probe() that's why remove it. Fixes: 6d234a79e9eb ("cadence_qspi: Refactor the flash reset functionality") Signed-off-by: Michal Simek Link: https://lore.kernel.org/r/5f6d6db9c301daf10ddb707a9031f1a467d6ebf1.1764180937.git.michal.simek@amd.com --- drivers/spi/cadence_qspi.c | 2 -- 1 file changed, 2 deletions(-) diff --git a/drivers/spi/cadence_qspi.c b/drivers/spi/cadence_qspi.c index 892dc3557a5..2d2469565b5 100644 --- a/drivers/spi/cadence_qspi.c +++ b/drivers/spi/cadence_qspi.c @@ -270,8 +270,6 @@ static int cadence_spi_probe(struct udevice *bus) /* Reset ospi flash device */ return cadence_qspi_flash_reset(bus); - - return 0; } static int cadence_spi_remove(struct udevice *dev) -- cgit v1.3.1 From b6391d1d9b3d04c1986b3ce7951528f8fde76bbd Mon Sep 17 00:00:00 2001 From: Venkatesh Yadav Abbarapu Date: Wed, 26 Nov 2025 19:21:49 +0100 Subject: cadence_qspi: Update the delays for flash reset Updating the delays for flash reset in the mini u-boot case. These experimental delay values by looking at different flash device vendors datasheets. Signed-off-by: Venkatesh Yadav Abbarapu Signed-off-by: Michal Simek Link: https://lore.kernel.org/r/3fd0641a164a4d628fdf28a94771829f3bf9cb0c.1764181308.git.michal.simek@amd.com --- drivers/spi/cadence_ospi_versal.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/spi/cadence_ospi_versal.c b/drivers/spi/cadence_ospi_versal.c index 0efbbf56a5e..e3ddf127e5a 100644 --- a/drivers/spi/cadence_ospi_versal.c +++ b/drivers/spi/cadence_ospi_versal.c @@ -178,15 +178,15 @@ int cadence_qspi_flash_reset(struct udevice *dev) /* Disable Tri-state */ writel((readl(BANK0_TRI) & ~BIT(FLASH_RESET_GPIO)), BANK0_TRI); - udelay(1); + udelay(5); /* Set value 0 to pin */ writel((readl(BANK0_OUTPUT) & ~BIT(FLASH_RESET_GPIO)), BANK0_OUTPUT); - udelay(10); + udelay(150); /* Set value 1 to pin */ writel((readl(BANK0_OUTPUT) | BIT(FLASH_RESET_GPIO)), BANK0_OUTPUT); - udelay(10); + udelay(1200); return 0; } -- cgit v1.3.1 From 29427fdf7198953f361ce6535b67272e3645d53b Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Thu, 27 Nov 2025 09:28:46 +0100 Subject: arm64: versal2: Read and show multiboot value SOC can boot from different boot medias and also different offsets that's why by default show multiboot value to be aware which image system is booting out of. It is especially useful for systems with A/B update enabled. Also limit zynqmp_pm_get_pmc_multi_boot_reg() usage only for Versal and Versal Gen 2. Signed-off-by: Michal Simek Link: https://lore.kernel.org/r/fd7564ce2f51d965c273e939e98de01beb92e6f5.1764232124.git.michal.simek@amd.com --- arch/arm/mach-versal2/include/mach/hardware.h | 4 +++- board/amd/versal2/board.c | 22 ++++++++++++++++++++++ drivers/firmware/firmware-zynqmp.c | 2 ++ 3 files changed, 27 insertions(+), 1 deletion(-) diff --git a/arch/arm/mach-versal2/include/mach/hardware.h b/arch/arm/mach-versal2/include/mach/hardware.h index 7ca2bbb7550..81a0df89357 100644 --- a/arch/arm/mach-versal2/include/mach/hardware.h +++ b/arch/arm/mach-versal2/include/mach/hardware.h @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0 */ /* * Copyright (C) 2016 - 2022, Xilinx, Inc. - * Copyright (C) 2022 - 2024, Advanced Micro Devices, Inc. + * Copyright (C) 2022 - 2025, Advanced Micro Devices, Inc. */ #ifndef __ASSEMBLY__ @@ -73,6 +73,8 @@ struct crp_regs { #define JTAG_MODE 0x00000000 #define BOOT_MODE_USE_ALT 0x100 #define BOOT_MODE_ALT_SHIFT 12 +#define PMC_MULTI_BOOT_REG 0xF1110004 +#define PMC_MULTI_BOOT_MASK 0x1FFF enum versal2_platform { VERSAL2_SILICON = 0, diff --git a/board/amd/versal2/board.c b/board/amd/versal2/board.c index 7d91d288d2e..1fd05a1157a 100644 --- a/board/amd/versal2/board.c +++ b/board/amd/versal2/board.c @@ -21,6 +21,7 @@ #include #include #include +#include #include "../../xilinx/common/board.h" #include @@ -180,6 +181,23 @@ static u8 versal2_get_bootmode(void) return bootmode; } +static u32 versal2_multi_boot(void) +{ + u8 bootmode = versal2_get_bootmode(); + u32 reg = 0; + + /* Mostly workaround for QEMU CI pipeline */ + if (bootmode == JTAG_MODE) + return 0; + + if (IS_ENABLED(CONFIG_ZYNQMP_FIRMWARE) && current_el() != 3) + reg = zynqmp_pm_get_pmc_multi_boot_reg(); + else + reg = readl(PMC_MULTI_BOOT_REG); + + return reg & PMC_MULTI_BOOT_MASK; +} + static int boot_targets_setup(void) { u8 bootmode; @@ -319,6 +337,7 @@ static int boot_targets_setup(void) int board_late_init(void) { int ret; + u32 multiboot; if (!(gd->flags & GD_FLG_ENV_DEFAULT)) { debug("Saved variables - Skipping\n"); @@ -328,6 +347,9 @@ int board_late_init(void) if (!IS_ENABLED(CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG)) return 0; + multiboot = versal2_multi_boot(); + env_set_hex("multiboot", multiboot); + if (IS_ENABLED(CONFIG_DISTRO_DEFAULTS)) { ret = boot_targets_setup(); if (ret) diff --git a/drivers/firmware/firmware-zynqmp.c b/drivers/firmware/firmware-zynqmp.c index 2ef499bf408..f8a9945c1da 100644 --- a/drivers/firmware/firmware-zynqmp.c +++ b/drivers/firmware/firmware-zynqmp.c @@ -248,6 +248,7 @@ u32 zynqmp_pm_get_bootmode_reg(void) return ret_payload[1]; } +#if defined(CONFIG_ARCH_VERSAL) || defined(CONFIG_ARCH_VERSAL2) u32 zynqmp_pm_get_pmc_multi_boot_reg(void) { int ret; @@ -271,6 +272,7 @@ u32 zynqmp_pm_get_pmc_multi_boot_reg(void) return ret_payload[1]; } +#endif int zynqmp_pm_feature(const u32 api_id) { -- cgit v1.3.1 From e9ce819f935aaeb84ca4046960459d8f790bf7a5 Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Thu, 27 Nov 2025 09:59:25 +0100 Subject: xilinx: versal: Get rid of xlnx-versal-power.h from bindings Remove xlnx-versal-power.h dt binding header because they should be moved directly to folder where DTs are. In the Linux kernel this shift already started by moving xlnx-zynqmp-clk.h to arch/arm64/boot/dts/xilinx/ folder. U-Boot is using only one PD_DEV_OSPI constact which is moved to zynqmp_firmware.h header. But handling around it should be fixed anyway because no driver should be calling xilinx_pm_request() directly. Signed-off-by: Michal Simek Link: https://lore.kernel.org/r/a0f0154ef89929517c3217efe025e8021a910b90.1764233963.git.michal.simek@amd.com --- drivers/spi/cadence_ospi_versal.c | 1 - drivers/spi/cadence_qspi.c | 1 - include/dt-bindings/power/xlnx-versal-power.h | 54 --------------------------- include/zynqmp_firmware.h | 2 + 4 files changed, 2 insertions(+), 56 deletions(-) delete mode 100644 include/dt-bindings/power/xlnx-versal-power.h diff --git a/drivers/spi/cadence_ospi_versal.c b/drivers/spi/cadence_ospi_versal.c index e3ddf127e5a..a00642d09d3 100644 --- a/drivers/spi/cadence_ospi_versal.c +++ b/drivers/spi/cadence_ospi_versal.c @@ -15,7 +15,6 @@ #include #include #include "cadence_qspi.h" -#include int cadence_qspi_apb_dma_read(struct cadence_spi_priv *priv, const struct spi_mem_op *op) diff --git a/drivers/spi/cadence_qspi.c b/drivers/spi/cadence_qspi.c index 2d2469565b5..d1404e13810 100644 --- a/drivers/spi/cadence_qspi.c +++ b/drivers/spi/cadence_qspi.c @@ -20,7 +20,6 @@ #include #include #include "cadence_qspi.h" -#include #define CQSPI_STIG_READ 0 #define CQSPI_STIG_WRITE 1 diff --git a/include/dt-bindings/power/xlnx-versal-power.h b/include/dt-bindings/power/xlnx-versal-power.h deleted file mode 100644 index 51d1def6773..00000000000 --- a/include/dt-bindings/power/xlnx-versal-power.h +++ /dev/null @@ -1,54 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Copyright (C) 2019 - 2021 Xilinx, Inc. - */ - -#ifndef _DT_BINDINGS_VERSAL_POWER_H -#define _DT_BINDINGS_VERSAL_POWER_H - -#define PM_DEV_RPU0_0 (0x18110005U) -#define PM_DEV_RPU0_1 (0x18110006U) -#define PM_DEV_OCM_0 (0x18314007U) -#define PM_DEV_OCM_1 (0x18314008U) -#define PM_DEV_OCM_2 (0x18314009U) -#define PM_DEV_OCM_3 (0x1831400aU) -#define PM_DEV_TCM_0_A (0x1831800bU) -#define PM_DEV_TCM_0_B (0x1831800cU) -#define PM_DEV_TCM_1_A (0x1831800dU) -#define PM_DEV_TCM_1_B (0x1831800eU) -#define PM_DEV_USB_0 (0x18224018U) -#define PM_DEV_GEM_0 (0x18224019U) -#define PM_DEV_GEM_1 (0x1822401aU) -#define PM_DEV_SPI_0 (0x1822401bU) -#define PM_DEV_SPI_1 (0x1822401cU) -#define PM_DEV_I2C_0 (0x1822401dU) -#define PM_DEV_I2C_1 (0x1822401eU) -#define PM_DEV_CAN_FD_0 (0x1822401fU) -#define PM_DEV_CAN_FD_1 (0x18224020U) -#define PM_DEV_UART_0 (0x18224021U) -#define PM_DEV_UART_1 (0x18224022U) -#define PM_DEV_GPIO (0x18224023U) -#define PM_DEV_TTC_0 (0x18224024U) -#define PM_DEV_TTC_1 (0x18224025U) -#define PM_DEV_TTC_2 (0x18224026U) -#define PM_DEV_TTC_3 (0x18224027U) -#define PM_DEV_SWDT_FPD (0x18224029U) -#define PM_DEV_OSPI (0x1822402aU) -#define PM_DEV_QSPI (0x1822402bU) -#define PM_DEV_GPIO_PMC (0x1822402cU) -#define PM_DEV_I2C_PMC (0x1822402dU) -#define PM_DEV_SDIO_0 (0x1822402eU) -#define PM_DEV_SDIO_1 (0x1822402fU) -#define PM_DEV_RTC (0x18224034U) -#define PM_DEV_ADMA_0 (0x18224035U) -#define PM_DEV_ADMA_1 (0x18224036U) -#define PM_DEV_ADMA_2 (0x18224037U) -#define PM_DEV_ADMA_3 (0x18224038U) -#define PM_DEV_ADMA_4 (0x18224039U) -#define PM_DEV_ADMA_5 (0x1822403aU) -#define PM_DEV_ADMA_6 (0x1822403bU) -#define PM_DEV_ADMA_7 (0x1822403cU) -#define PM_DEV_AMS_ROOT (0x18224055U) -#define PM_DEV_AI (0x18224072U) - -#endif diff --git a/include/zynqmp_firmware.h b/include/zynqmp_firmware.h index 72f6459b91c..05df49f292a 100644 --- a/include/zynqmp_firmware.h +++ b/include/zynqmp_firmware.h @@ -527,4 +527,6 @@ extern smc_call_handler_t __data smc_call_handler; #define PLM_MODULE_ID_MASK GENMASK(15, 8) #define API_ID_MASK GENMASK(7, 0) +#define PM_DEV_OSPI (0x1822402aU) + #endif /* _ZYNQMP_FIRMWARE_H_ */ -- cgit v1.3.1 From 38e3f9658ef8c5054999f93d3c5f97cbb485c696 Mon Sep 17 00:00:00 2001 From: Padmarao Begari Date: Wed, 26 Nov 2025 16:12:35 +0100 Subject: i2c: cdns: Add timeout for RXDV status bit polling Add a timeout mechanism when waiting for the RXDV (Receive Data Valid) status bit to be set before reading data from the FIFO. This prevents infinite polling loops that could occur if the hardware doesn't respond as expected. The timeout is set to 1000ms (CDNS_I2C_RXDV_TIMEOUT_MS) and uses the wait_for_bit_le32() function to poll the status register. If the timeout expires, an error code is returned. Signed-off-by: Padmarao Begari Reviewed-by: Heiko Schocher Signed-off-by: Michal Simek Link: https://lore.kernel.org/r/ba53d57c179f3390b32bc6094f3ffb5f4cde931e.1764169953.git.michal.simek@amd.com --- drivers/i2c/i2c-cdns.c | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/drivers/i2c/i2c-cdns.c b/drivers/i2c/i2c-cdns.c index 3f7cf8533ec..4e9d4e44899 100644 --- a/drivers/i2c/i2c-cdns.c +++ b/drivers/i2c/i2c-cdns.c @@ -85,6 +85,8 @@ struct cdns_i2c_regs { #define CDNS_I2C_ARB_LOST_MAX_RETRIES 10 +#define CDNS_I2C_RXDV_TIMEOUT_MS 1000 + #ifdef DEBUG static void cdns_i2c_debug_status(struct cdns_i2c_regs *cdns_i2c) { @@ -349,6 +351,11 @@ static int cdns_i2c_read_data(struct i2c_cdns_bus *i2c_bus, u32 addr, u8 *data, hold_quirk = (i2c_bus->quirks & CDNS_I2C_BROKEN_HOLD_BIT) && updatetx; while (recv_count && !is_arbitration_lost(regs)) { + int err = wait_for_bit_le32(®s->status, CDNS_I2C_STATUS_RXDV, + true, CDNS_I2C_RXDV_TIMEOUT_MS, false); + if (err) + return err; + while (readl(®s->status) & CDNS_I2C_STATUS_RXDV) { if (recv_count < i2c_bus->fifo_depth && !i2c_bus->hold_flag) { @@ -452,6 +459,10 @@ static int cdns_i2c_xfer(struct udevice *dev, struct i2c_msg *msg, ret = cdns_i2c_write_data(i2c_bus, msg->addr, msg->buf, msg->len); } + + if (ret == -ETIMEDOUT) + return ret; + if (ret == -EAGAIN) { msg = message; nmsgs = num_msgs; -- cgit v1.3.1 From e94fe1c16d88ed861546dc4369bf034df79bc511 Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Wed, 3 Dec 2025 08:20:32 +0100 Subject: xilinx: mbv32: Disable floating point MB-V 32 has optional single precision FPU (64bit has single and double precision FPU) but there is no use and reason to enable FPU by default that's why disable it. Signed-off-by: Michal Simek Link: https://lore.kernel.org/r/2c043ed05643fee200a79eb08bfd5c0041663bd2.1764746430.git.michal.simek@amd.com --- configs/xilinx_mbv32_defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/configs/xilinx_mbv32_defconfig b/configs/xilinx_mbv32_defconfig index 88d9e5ce6b2..81c0f8e9e93 100644 --- a/configs/xilinx_mbv32_defconfig +++ b/configs/xilinx_mbv32_defconfig @@ -18,6 +18,7 @@ CONFIG_SYS_CLK_FREQ=100000000 CONFIG_BOOT_SCRIPT_OFFSET=0x0 CONFIG_DEBUG_UART=y CONFIG_TARGET_XILINX_MBV=y +# CONFIG_RISCV_ISA_F is not set # CONFIG_SPL_SMP is not set CONFIG_REMAKE_ELF=y CONFIG_FIT=y -- cgit v1.3.1 From 794cbdb08c65152c0114ec724fa800d87a845324 Mon Sep 17 00:00:00 2001 From: Padmarao Begari Date: Wed, 3 Dec 2025 08:34:52 +0100 Subject: xilinx: mbv: Disable SPL GZIP GZIP compression is disabled to reduce the SPL size by 12KB. Signed-off-by: Padmarao Begari Signed-off-by: Michal Simek Link: https://lore.kernel.org/r/339520b249a3c69a36faf5432cbd581459563e32.1764747291.git.michal.simek@amd.com --- configs/xilinx_mbv32_defconfig | 1 - 1 file changed, 1 deletion(-) diff --git a/configs/xilinx_mbv32_defconfig b/configs/xilinx_mbv32_defconfig index 81c0f8e9e93..d10517094c6 100644 --- a/configs/xilinx_mbv32_defconfig +++ b/configs/xilinx_mbv32_defconfig @@ -47,4 +47,3 @@ CONFIG_XILINX_TIMER=y # CONFIG_BINMAN_FDT is not set CONFIG_BINMAN_DTB="./arch/riscv/dts/xilinx-binman.dtb" CONFIG_PANIC_HANG=y -CONFIG_SPL_GZIP=y -- cgit v1.3.1 From 3af56e2e55fc03c9453d79374f9dd9f0fff6ec41 Mon Sep 17 00:00:00 2001 From: Padmarao Begari Date: Wed, 3 Dec 2025 08:35:48 +0100 Subject: xilinx: mbv: Remove debug UART support Remove debug UART support as it is intended for development and debugging purposes, and should not be enabled in production builds. Signed-off-by: Padmarao Begari Signed-off-by: Michal Simek Link: https://lore.kernel.org/r/6eaad47c30990ffd230d21c7158bc7234cda1752.1764747346.git.michal.simek@amd.com --- configs/xilinx_mbv32_defconfig | 5 ----- 1 file changed, 5 deletions(-) diff --git a/configs/xilinx_mbv32_defconfig b/configs/xilinx_mbv32_defconfig index d10517094c6..9e3c44352a1 100644 --- a/configs/xilinx_mbv32_defconfig +++ b/configs/xilinx_mbv32_defconfig @@ -12,11 +12,8 @@ CONFIG_SYS_BOOTM_LEN=0x800000 CONFIG_SYS_LOAD_ADDR=0x80200000 CONFIG_SPL_SIZE_LIMIT=0x40000 CONFIG_SPL=y -CONFIG_DEBUG_UART_BASE=0x40600000 -CONFIG_DEBUG_UART_CLOCK=100000000 CONFIG_SYS_CLK_FREQ=100000000 CONFIG_BOOT_SCRIPT_OFFSET=0x0 -CONFIG_DEBUG_UART=y CONFIG_TARGET_XILINX_MBV=y # CONFIG_RISCV_ISA_F is not set # CONFIG_SPL_SMP is not set @@ -40,8 +37,6 @@ CONFIG_SPL_DM_SEQ_ALIAS=y CONFIG_DM_MTD=y CONFIG_DM_RTC=y CONFIG_RTC_EMULATION=y -CONFIG_DEBUG_UART_ANNOUNCE=y -CONFIG_DEBUG_UART_SKIP_INIT=y CONFIG_XILINX_UARTLITE=y CONFIG_XILINX_TIMER=y # CONFIG_BINMAN_FDT is not set -- cgit v1.3.1 From c8898f12d307db97ad2a18442273b7f0e2750c01 Mon Sep 17 00:00:00 2001 From: Padmarao Begari Date: Wed, 3 Dec 2025 08:36:59 +0100 Subject: board: xilinx: add SPL boot device support Add board_boot_order() function and remove spl_boot_device() function because it is called from weak board_boot_order(). Add support to U-Boot SPL for booting from RAM or SPI, as configured in defconfig. Signed-off-by: Padmarao Begari Signed-off-by: Michal Simek Link: https://lore.kernel.org/r/a1f26a9392128309a1affed28b14809845714c21.1764747417.git.michal.simek@amd.com --- board/xilinx/mbv/board.c | 14 ++++++++++---- 1 file changed, 10 insertions(+), 4 deletions(-) diff --git a/board/xilinx/mbv/board.c b/board/xilinx/mbv/board.c index ed3fe16af7b..2b0005955ca 100644 --- a/board/xilinx/mbv/board.c +++ b/board/xilinx/mbv/board.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0+ /* - * (C) Copyright 2023, Advanced Micro Devices, Inc. + * (C) Copyright 2023-2025, Advanced Micro Devices, Inc. * * Michal Simek */ @@ -8,9 +8,15 @@ #include #ifdef CONFIG_SPL -u32 spl_boot_device(void) +void board_boot_order(u32 *spl_boot_list) { - /* RISC-V QEMU only supports RAM as SPL boot device */ - return BOOT_DEVICE_RAM; + u32 i = 0; + + if (CONFIG_IS_ENABLED(SPI_FLASH_SUPPORT)) + spl_boot_list[i++] = BOOT_DEVICE_SPI; + + if (CONFIG_IS_ENABLED(RAM_SUPPORT)) + spl_boot_list[i++] = BOOT_DEVICE_RAM; + } #endif -- cgit v1.3.1 From 6b743f66d83934cb5435a328a5be09697123428e Mon Sep 17 00:00:00 2001 From: Padmarao Begari Date: Mon, 8 Dec 2025 16:03:34 +0100 Subject: xilinx: mbv: Update defconfigs as per memory map U-Boot SPL should be executed from LMB BRAM, where its text and data sections are located, while the heap and stack are allocated in DDR memory. Because on the MB-V platform, after power-up, reset, or FPGA load, execution begins from LMB BRAM at address 0x0. Therefore, the SPL binary must be placed in BRAM to support this boot flow. Without it, the system can only be booted via JTAG. A 64KB LMB BRAM region is allocated for U-Boot SPL, starting at address 0x0. This region contains the SPL's text, data, and device tree blob (DTB) sections. The .bss section is placed separately at address 0xF000. _________________0xFFFF |BSS | |_______________|0xF000 |DTB | |_______________| |Data | |_______________| |Text | |_______________|0x0000 A 2MB region of DDR memory is allocated for U-Boot SPL, with the heap starting at address 0x80000000 and the stack at 0x80200000. _________________0xBFFFFFFF |Full U-Boot | |_______________|0x80400000 |Load FIT Image | |_______________|0x80200000 |Stack | |_______________| |Heap | |_______________|0x80000000 Since LMB BRAM is a limited resource with a practical size constraint of 64KB - it cannot accommodate all runtime data. Therefore, the heap and stack are placed at the beginning of DDR memory to ensure sufficient space for SPL execution. Signed-off-by: Padmarao Begari Signed-off-by: Michal Simek Link: https://lore.kernel.org/r/ed4a3618875869287b87b6b57fd55f4c6a36f046.1765206211.git.michal.simek@amd.com --- configs/xilinx_mbv32_defconfig | 12 ++++++++---- 1 file changed, 8 insertions(+), 4 deletions(-) diff --git a/configs/xilinx_mbv32_defconfig b/configs/xilinx_mbv32_defconfig index 9e3c44352a1..42dc5fb282a 100644 --- a/configs/xilinx_mbv32_defconfig +++ b/configs/xilinx_mbv32_defconfig @@ -6,11 +6,12 @@ CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x81200000 CONFIG_ENV_SIZE=0x20000 CONFIG_DEFAULT_DEVICE_TREE="xilinx-mbv32" CONFIG_SPL_STACK=0x80200000 -CONFIG_SPL_BSS_START_ADDR=0x84000000 -CONFIG_SPL_BSS_MAX_SIZE=0x80000 +CONFIG_SPL_TEXT_BASE=0x0 +CONFIG_SPL_BSS_START_ADDR=0xf000 +CONFIG_SPL_BSS_MAX_SIZE=0x1000 CONFIG_SYS_BOOTM_LEN=0x800000 CONFIG_SYS_LOAD_ADDR=0x80200000 -CONFIG_SPL_SIZE_LIMIT=0x40000 +CONFIG_SPL_SIZE_LIMIT=0x10000 CONFIG_SPL=y CONFIG_SYS_CLK_FREQ=100000000 CONFIG_BOOT_SCRIPT_OFFSET=0x0 @@ -25,10 +26,13 @@ CONFIG_DISPLAY_CPUINFO=y CONFIG_DISPLAY_BOARDINFO=y # CONFIG_BOARD_INIT is not set # CONFIG_BOARD_LATE_INIT is not set -CONFIG_SPL_MAX_SIZE=0x40000 +CONFIG_SPL_MAX_SIZE=0xf000 # CONFIG_SPL_SHARES_INIT_SP_ADDR is not set CONFIG_SPL_HAVE_INIT_STACK=y CONFIG_SPL_SYS_MALLOC=y +CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y +CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x80000000 +CONFIG_SPL_SYS_MALLOC_SIZE=0x200000 # CONFIG_CMD_MII is not set CONFIG_CMD_SNTP=y CONFIG_CMD_TIMER=y -- cgit v1.3.1 From 0b880fc95dbaed88dd55060730857b8f52765c57 Mon Sep 17 00:00:00 2001 From: Neal Frager Date: Wed, 17 Dec 2025 12:51:07 +0000 Subject: arch/arm/mach-zynqmp: configure default BL32_LOAD_ADDR The default entry point address for the optee-os tee.bin for the zynqmp platform is 0x60000000. For this reason, set the default u-boot BL32_LOAD_ADDR to match the default optee-os entry point address of 0x60000000. Signed-off-by: Neal Frager Signed-off-by: Michal Simek Link: https://lore.kernel.org/r/20251217125107.1095397-1-neal.frager@amd.com --- arch/arm/mach-zynqmp/Kconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/mach-zynqmp/Kconfig b/arch/arm/mach-zynqmp/Kconfig index 151cfada436..8a4356bc060 100644 --- a/arch/arm/mach-zynqmp/Kconfig +++ b/arch/arm/mach-zynqmp/Kconfig @@ -138,7 +138,7 @@ config BL31_LOAD_ADDR config BL32_LOAD_ADDR hex "Load address of BL32 image (mostly secure OS)" - default 0 + default 0x60000000 help The load address for the BL32 image. This value is used to build the FIT image header that places BL32 in memory where it will run. -- cgit v1.3.1