From 2fcb08a2b477667741f194b8b8a8a08a711dc974 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Jonas=20Schw=C3=B6bel?= Date: Tue, 11 Mar 2025 23:11:47 +0100 Subject: pwm: tegra: fix pulse_width calculation MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The pulse_width is expressed as N/256. A 100% duty cycle is only possible when multiplied by 256 instead of 255. Signed-off-by: Jonas Schwöbel Signed-off-by: Svyatoslav Ryhel --- drivers/pwm/tegra_pwm.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/pwm/tegra_pwm.c b/drivers/pwm/tegra_pwm.c index 4b57751f73f..4bbfeba8d98 100644 --- a/drivers/pwm/tegra_pwm.c +++ b/drivers/pwm/tegra_pwm.c @@ -40,7 +40,7 @@ static int tegra_pwm_set_config(struct udevice *dev, uint channel, return -EINVAL; debug("%s: Configure '%s' channel %u\n", __func__, dev->name, channel); - pulse_width = duty_ns * 255 / period_ns; + pulse_width = duty_ns * 256 / period_ns; if (priv->polarity & BIT(channel)) pulse_width = 256 - pulse_width; -- cgit v1.2.3