From 3a3b34eeaa7fbcf1548d348d2e6fc7676c9230ee Mon Sep 17 00:00:00 2001 From: Alif Zakuan Yuslaimi Date: Tue, 9 Jun 2026 10:03:56 +0800 Subject: arm: socfpga: Consolidate dram_bank_mmu_setup() Share dram_bank_mmu_setup() between Gen5 and Arria10 in misc.c. Before relocation, map OCRAM and DRAM write-through so SPL can run sdram_init_ecc_bits() with dcache; after relocation, use default DRAM cache attributes. See also commit e26ecebc684b ("socfpga: arria10: Allow dcache_enable before relocation") Fixes: 503eea451903 ("arm: cp15: update DACR value to activate access control") Signed-off-by: Alif Zakuan Yuslaimi --- arch/arm/mach-socfpga/misc.c | 30 ++++++++++++++++++++++++++++++ arch/arm/mach-socfpga/misc_arria10.c | 24 ------------------------ 2 files changed, 30 insertions(+), 24 deletions(-) diff --git a/arch/arm/mach-socfpga/misc.c b/arch/arm/mach-socfpga/misc.c index 6d7128c77be..2ee4aa8b5f2 100644 --- a/arch/arm/mach-socfpga/misc.c +++ b/arch/arm/mach-socfpga/misc.c @@ -320,3 +320,33 @@ phys_addr_t socfpga_get_clkmgr_addr(void) { return socfpga_clkmgr_base; } + +#if IS_ENABLED(CONFIG_SYS_ARM_CACHE_CP15) +void dram_bank_mmu_setup(int bank) +{ + u32 start, size; + int i; + + /* If we're still in OCRAM, don't set the XN bit on it */ + if (!(gd->flags & GD_FLG_RELOC)) { + set_section_dcache(CFG_SYS_INIT_RAM_ADDR >> MMU_SECTION_SHIFT, + DCACHE_WRITETHROUGH); + + /* + * The default implementation of this function allows the DRAM dcache + * to be enabled only after relocation. However, to speed up ECC + * initialization, we want to be able to enable DRAM dcache before + * relocation. + */ + start = gd->dram[bank].start >> MMU_SECTION_SHIFT; + size = gd->dram[bank].size >> MMU_SECTION_SHIFT; + for (i = start; i < start + size; i++) + set_section_dcache(i, DCACHE_WRITETHROUGH); + } else { + start = gd->dram[bank].start >> MMU_SECTION_SHIFT; + size = gd->dram[bank].size >> MMU_SECTION_SHIFT; + for (i = start; i < start + size; i++) + set_section_dcache(i, DCACHE_DEFAULT_OPTION); + } +} +#endif diff --git a/arch/arm/mach-socfpga/misc_arria10.c b/arch/arm/mach-socfpga/misc_arria10.c index 338f73d6e73..729a4e7f264 100644 --- a/arch/arm/mach-socfpga/misc_arria10.c +++ b/arch/arm/mach-socfpga/misc_arria10.c @@ -244,27 +244,3 @@ int qspi_flash_software_reset(void) } #endif -void dram_bank_mmu_setup(int bank) -{ - u32 start, size; - int i; - - /* If we're still in OCRAM, don't set the XN bit on it */ - if (!(gd->flags & GD_FLG_RELOC)) { - set_section_dcache( - CFG_SYS_INIT_RAM_ADDR >> MMU_SECTION_SHIFT, - DCACHE_WRITETHROUGH); - } - - /* - * The default implementation of this function allows the DRAM dcache - * to be enabled only after relocation. However, to speed up ECC - * initialization, we want to be able to enable DRAM dcache before - * relocation, so we don't check GD_FLG_RELOC (this assumes gd->dram - * is set first). - */ - start = gd->dram[bank].start >> MMU_SECTION_SHIFT; - size = gd->dram[bank].size >> MMU_SECTION_SHIFT; - for (i = start; i < start + size; i++) - set_section_dcache(i, DCACHE_DEFAULT_OPTION); -} -- cgit v1.3.1