From d7fee32b7e61fe11c64e371cde79faa4768e8350 Mon Sep 17 00:00:00 2001 From: Sam Sparks Date: Fri, 14 Sep 2007 11:14:42 -0600 Subject: Update MPC8349ITX*_config to place config.tmp in right place. MPC834ITX*_config does not store config.tmp at the correct locatation, causing MPC8349ITXGP to have the wrong TEXT_BASE. Signed-off-by: Sam Sparks Signed-off-by: Grant Likely Signed-off-by: Kim Phillips --- Makefile | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/Makefile b/Makefile index c1c64462f03..85885b166a6 100644 --- a/Makefile +++ b/Makefile @@ -1794,13 +1794,13 @@ MPC8349ITX_config \ MPC8349ITX_LOWBOOT_config \ MPC8349ITXGP_config: unconfig @mkdir -p $(obj)include - @mkdir -p $(obj)board/mpc8349itx + @mkdir -p $(obj)board/freescale/mpc8349itx @echo "#define CONFIG_$(subst _LOWBOOT,,$(@:_config=))" >> $(obj)include/config.h @if [ "$(findstring GP,$@)" ] ; then \ - echo "TEXT_BASE = 0xFE000000" >$(obj)board/mpc8349itx/config.tmp ; \ + echo "TEXT_BASE = 0xFE000000" >$(obj)board/freescale/mpc8349itx/config.tmp ; \ fi @if [ "$(findstring LOWBOOT,$@)" ] ; then \ - echo "TEXT_BASE = 0xFE000000" >$(obj)board/mpc8349itx/config.tmp ; \ + echo "TEXT_BASE = 0xFE000000" >$(obj)board/freescale/mpc8349itx/config.tmp ; \ fi @$(MKCONFIG) -a -n $(@:_config=) MPC8349ITX ppc mpc83xx mpc8349itx freescale -- cgit v1.2.3 From 1487adbdcf9594bb2eb686325a6f9540dad1b70a Mon Sep 17 00:00:00 2001 From: Ed Swarthout Date: Wed, 26 Sep 2007 16:35:54 -0500 Subject: 85xx io out functions need sync after write. This fixes the mc146818 rtc_read/write functions for 85xx. Signed-off-by: Ed Swarthout --- cpu/mpc85xx/start.S | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/cpu/mpc85xx/start.S b/cpu/mpc85xx/start.S index 2c98c2ad8a0..5d65190ede8 100644 --- a/cpu/mpc85xx/start.S +++ b/cpu/mpc85xx/start.S @@ -701,6 +701,7 @@ in8: .globl out8 out8: stb r4,0x0000(r3) + sync blr /*------------------------------------------------------------------------------- */ @@ -710,6 +711,7 @@ out8: .globl out16 out16: sth r4,0x0000(r3) + sync blr /*------------------------------------------------------------------------------- */ @@ -719,6 +721,7 @@ out16: .globl out16r out16r: sthbrx r4,r0,r3 + sync blr /*------------------------------------------------------------------------------- */ @@ -728,6 +731,7 @@ out16r: .globl out32 out32: stw r4,0x0000(r3) + sync blr /*------------------------------------------------------------------------------- */ @@ -737,6 +741,7 @@ out32: .globl out32r out32r: stwbrx r4,r0,r3 + sync blr /*------------------------------------------------------------------------------- */ -- cgit v1.2.3 From 9ef57bbee1c67cc01da2026c242c4692db32be36 Mon Sep 17 00:00:00 2001 From: Martin Krause Date: Wed, 26 Sep 2007 17:55:55 +0200 Subject: TQM866M: adjust for doubled flash sector size. Adjust flash map to support the new S29GLxxN (N-Type) Flashes with doubled sector size. Signed-off-by: Martin Krause --- include/configs/TQM866M.h | 13 +++++++++---- 1 file changed, 9 insertions(+), 4 deletions(-) diff --git a/include/configs/TQM866M.h b/include/configs/TQM866M.h index 0d778919a2b..76facc42958 100644 --- a/include/configs/TQM866M.h +++ b/include/configs/TQM866M.h @@ -81,9 +81,14 @@ "net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \ "rootpath=/opt/eldk/ppc_8xx\0" \ "bootfile=/tftpboot/TQM866M/uImage\0" \ - "fdt_addr=40080000\0" \ - "kernel_addr=400A0000\0" \ + "fdt_addr=400C0000\0" \ + "kernel_addr=40100000\0" \ "ramdisk_addr=40280000\0" \ + "load=tftp 200000 ${u-boot}\0" \ + "update=protect off 40000000 +${filesize};" \ + "erase 40000000 +${filesize};" \ + "cp.b 200000 40000000 ${filesize};" \ + "protect on 40000000 +${filesize}\0" \ "" #define CONFIG_BOOTCOMMAND "run flash_self" @@ -215,7 +220,7 @@ #define CFG_FLASH_BASE 0x40000000 #define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ #define CFG_MONITOR_BASE CFG_FLASH_BASE -#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ +#define CFG_MALLOC_LEN (256 << 10) /* Reserve 256 kB for malloc() */ /* * For booting Linux, the board info and command line data @@ -236,7 +241,7 @@ #define CFG_ENV_IS_IN_FLASH 1 #define CFG_ENV_OFFSET 0x40000 /* Offset of Environment Sector */ #define CFG_ENV_SIZE 0x08000 /* Total Size of Environment Sector */ -#define CFG_ENV_SECT_SIZE 0x20000 /* Total Size of Environment Sector */ +#define CFG_ENV_SECT_SIZE 0x40000 /* Total Size of Environment Sector */ /* Address and size of Redundant Environment Sector */ #define CFG_ENV_OFFSET_REDUND (CFG_ENV_OFFSET+CFG_ENV_SECT_SIZE) -- cgit v1.2.3 From d43e489baf02afae49077791fb22332d240d8656 Mon Sep 17 00:00:00 2001 From: Martin Krause Date: Thu, 27 Sep 2007 14:54:36 +0200 Subject: TQM866M: fix SDRAM refresh At 133 MHz the current SDRAM refresh rate is too fast (measured 4 * 1.17 us). CFG_MAMR_PTA changes from 39 to 97. This result in a refresh rate of 4 * 7.8 us at the default clock 50 MHz. At 133 MHz the value will be then 4 * 2.9 us. This is a compromise until a new method is found to adjust the refresh rate. Signed-off-by: Martin Krause --- include/configs/TQM866M.h | 36 ++++++++++++++++++++---------------- 1 file changed, 20 insertions(+), 16 deletions(-) diff --git a/include/configs/TQM866M.h b/include/configs/TQM866M.h index 76facc42958..ca3c166524f 100644 --- a/include/configs/TQM866M.h +++ b/include/configs/TQM866M.h @@ -426,26 +426,30 @@ #define CFG_PTA_PER_CLK ((4096 * 64 * 1000) / (4 * 64)) /* - * Memory Periodic Timer Prescaler - * Periodic timer for refresh, start with refresh rate for 40 MHz clock - * (CFG_8xx_CPUCLK_MIN / CFG_PTA_PER_CLK) + * Periodic timer (MAMR[PTx]) for 4 * 7.8 us refresh (= 31.2 us per quad) + * + * CPUclock(MHz) * 31.2 + * CFG_MAMR_PTA = ----------------------------------- with DFBRG = 0 + * 2^(2*SCCR[DFBRG]) * MPTPR_PTP_DIV16 + * + * CPU clock = 15 MHz: CFG_MAMR_PTA = 29 -> 4 * 7.73 us + * CPU clock = 50 MHz: CFG_MAMR_PTA = 97 -> 4 * 7.76 us + * CPU clock = 66 MHz: CFG_MAMR_PTA = 128 -> 4 * 7.75 us + * CPU clock = 133 MHz: CFG_MAMR_PTA = 255 -> 4 * 7.67 us + * + * Value 97 is for 4 * 7.8 us at 50 MHz. So the refresh cycle requirement will + * be met also in the default configuration, i.e. if environment variable + * 'cpuclk' is not set. */ -#define CFG_MAMR_PTA 39 +#define CFG_MAMR_PTA 97 /* - * For 16 MBit, refresh rates could be 31.3 us - * (= 64 ms / 2K = 125 / quad bursts). - * For a simpler initialization, 15.6 us is used instead. - * - * #define CFG_MPTPR_2BK_2K MPTPR_PTP_DIV32 for 2 banks - * #define CFG_MPTPR_1BK_2K MPTPR_PTP_DIV64 for 1 bank + * Memory Periodic Timer Prescaler Register (MPTPR) values. */ -#define CFG_MPTPR_2BK_4K MPTPR_PTP_DIV16 /* setting for 2 banks */ -#define CFG_MPTPR_1BK_4K MPTPR_PTP_DIV32 /* setting for 1 bank */ - -/* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit */ -#define CFG_MPTPR_2BK_8K MPTPR_PTP_DIV8 /* setting for 2 banks */ -#define CFG_MPTPR_1BK_8K MPTPR_PTP_DIV16 /* setting for 1 bank */ +/* 4 * 7.8 us refresh (= 31.2 us per quad) at 50 MHz and PTA = 97 */ +#define CFG_MPTPR_2BK_4K MPTPR_PTP_DIV16 +/* 4 * 3.9 us refresh (= 15.6 us per quad) at 50 MHz and PTA = 97 */ +#define CFG_MPTPR_2BK_8K MPTPR_PTP_DIV8 /* * MAMR settings for SDRAM -- cgit v1.2.3 From 9d29250e2e62f4bf20c7a20b4173d84c48f11f5d Mon Sep 17 00:00:00 2001 From: Jens Gehrlein Date: Wed, 26 Sep 2007 17:55:54 +0200 Subject: TQM8xx: Fix CAN timing. Signed-off-by: Martin Krause --- board/tqm8xx/tqm8xx.c | 16 +++++++++------- 1 file changed, 9 insertions(+), 7 deletions(-) diff --git a/board/tqm8xx/tqm8xx.c b/board/tqm8xx/tqm8xx.c index 6b206f8a184..cebdcc07649 100644 --- a/board/tqm8xx/tqm8xx.c +++ b/board/tqm8xx/tqm8xx.c @@ -354,6 +354,8 @@ long int initdram (int board_type) udelay (10000); #ifdef CONFIG_CAN_DRIVER + /* UPM initialization for CAN @ CLKOUT <= 66 MHz */ + /* Initialize OR3 / BR3 */ memctl->memc_or3 = CFG_OR3_CAN; memctl->memc_br3 = CFG_BR3_CAN; @@ -362,7 +364,7 @@ long int initdram (int board_type) memctl->memc_mbmr = MBMR_GPL_B4DIS; /* GPL_B4 ouput line Disable */ /* Initialize UPMB for CAN: single read */ - memctl->memc_mdr = 0xFFFFC004; + memctl->memc_mdr = 0xFFFFCC04; memctl->memc_mcr = 0x0100 | UPMB; memctl->memc_mdr = 0x0FFFD004; @@ -374,23 +376,23 @@ long int initdram (int board_type) memctl->memc_mdr = 0x3FFFC004; memctl->memc_mcr = 0x0103 | UPMB; - memctl->memc_mdr = 0xFFFFDC05; + memctl->memc_mdr = 0xFFFFDC07; memctl->memc_mcr = 0x0104 | UPMB; /* Initialize UPMB for CAN: single write */ - memctl->memc_mdr = 0xFFFCC004; + memctl->memc_mdr = 0xFFFCCC04; memctl->memc_mcr = 0x0118 | UPMB; - memctl->memc_mdr = 0xCFFCD004; + memctl->memc_mdr = 0xCFFCDC04; memctl->memc_mcr = 0x0119 | UPMB; - memctl->memc_mdr = 0x0FFCC000; + memctl->memc_mdr = 0x3FFCC000; memctl->memc_mcr = 0x011A | UPMB; - memctl->memc_mdr = 0x7FFCC004; + memctl->memc_mdr = 0xFFFCC004; memctl->memc_mcr = 0x011B | UPMB; - memctl->memc_mdr = 0xFFFDCC05; + memctl->memc_mdr = 0xFFFDC405; memctl->memc_mcr = 0x011C | UPMB; #endif /* CONFIG_CAN_DRIVER */ -- cgit v1.2.3 From da3aad55cbde80ab6e301aafa82a2c411aa53eff Mon Sep 17 00:00:00 2001 From: Martin Krause Date: Wed, 26 Sep 2007 17:55:56 +0200 Subject: TQM860M: adjust for doubled flash sector size. Adjust flash map to support the new S29GLxxN (N-Type) Flashes with doubled sector size. Signed-off-by: Martin Krause --- include/configs/TQM860M.h | 13 +++++++++---- 1 file changed, 9 insertions(+), 4 deletions(-) diff --git a/include/configs/TQM860M.h b/include/configs/TQM860M.h index 684b86f2efe..fe3a2f020c0 100644 --- a/include/configs/TQM860M.h +++ b/include/configs/TQM860M.h @@ -69,9 +69,14 @@ "net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \ "rootpath=/opt/eldk/ppc_8xx\0" \ "bootfile=/tftpboot/TQM860M/uImage\0" \ - "fdt_addr=40080000\0" \ - "kernel_addr=400A0000\0" \ + "fdt_addr=400C0000\0" \ + "kernel_addr=40100000\0" \ "ramdisk_addr=40280000\0" \ + "load=tftp 200000 ${u-boot}\0" \ + "update=protect off 40000000 +${filesize};" \ + "erase 40000000 +${filesize};" \ + "cp.b 200000 40000000 ${filesize};" \ + "protect on 40000000 +${filesize}\0" \ "" #define CONFIG_BOOTCOMMAND "run flash_self" @@ -172,7 +177,7 @@ #define CFG_FLASH_BASE 0x40000000 #define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ #define CFG_MONITOR_BASE CFG_FLASH_BASE -#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ +#define CFG_MALLOC_LEN (256 << 10) /* Reserve 256 kB for malloc() */ /* * For booting Linux, the board info and command line data @@ -193,7 +198,7 @@ #define CFG_ENV_IS_IN_FLASH 1 #define CFG_ENV_OFFSET 0x40000 /* Offset of Environment Sector */ #define CFG_ENV_SIZE 0x08000 /* Total Size of Environment Sector */ -#define CFG_ENV_SECT_SIZE 0x20000 /* Total Size of Environment Sector */ +#define CFG_ENV_SECT_SIZE 0x40000 /* Total Size of Environment Sector */ /* Address and size of Redundant Environment Sector */ #define CFG_ENV_OFFSET_REDUND (CFG_ENV_OFFSET+CFG_ENV_SECT_SIZE) -- cgit v1.2.3 From 7ee6ba1a056e4061ab4cfde30127e332e7957afd Mon Sep 17 00:00:00 2001 From: "runet@innovsys.com" Date: Tue, 16 Oct 2007 14:50:40 -0500 Subject: Make MPC8266ADS board compile again. Signed-off-by: Runet Torgersen --- include/configs/MPC8266ADS.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/include/configs/MPC8266ADS.h b/include/configs/MPC8266ADS.h index 14b041e3aec..d392b981edd 100644 --- a/include/configs/MPC8266ADS.h +++ b/include/configs/MPC8266ADS.h @@ -168,6 +168,7 @@ #undef CONFIG_CMD_MFSL #undef CONFIG_CMD_MMC #undef CONFIG_CMD_NAND +#undef CONFIG_CMD_ONENAND #undef CONFIG_CMD_PCMCIA #undef CONFIG_CMD_REISER #undef CONFIG_CMD_SCSI @@ -177,6 +178,7 @@ #undef CONFIG_CMD_UNIVERSE #undef CONFIG_CMD_USB #undef CONFIG_CMD_XIMG +#undef CONFIG_CMD_AT91_SPIMUX /* Define a command string that is automatically executed when no character * is read on the console interface withing "Boot Delay" after reset. -- cgit v1.2.3 From 3e11ae80fec1ee12194940955431186abf6009c2 Mon Sep 17 00:00:00 2001 From: Stefan Roese Date: Wed, 17 Oct 2007 15:40:19 +0200 Subject: ppc4xx: Add 667/133 (CPU/PLB) frequency setup to Sequoia bootstrap command Signed-off-by: Stefan Roese --- board/amcc/sequoia/cmd_sequoia.c | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) diff --git a/board/amcc/sequoia/cmd_sequoia.c b/board/amcc/sequoia/cmd_sequoia.c index e7997e94db7..6b9043a0586 100644 --- a/board/amcc/sequoia/cmd_sequoia.c +++ b/board/amcc/sequoia/cmd_sequoia.c @@ -40,7 +40,7 @@ * All Sequoias & Rainiers select from two possible EEPROMs in Boot * Config F. One for 33MHz PCI, one for 66MHz PCI. The following * values are for the 33MHz PCI configuration. Byte 5 (0 base) is - * the only value affected for a 66MHz PCI and simply needs a +0x10. + * the only value affected for a 33MHz PCI and simply needs a | 0x08. */ #define NAND_COMPATIBLE 0x01 @@ -57,6 +57,7 @@ static char *config_labels[] = { "CPU: 416 PLB: 166 OPB: 83 EBC: 55", "CPU: 500 PLB: 166 OPB: 83 EBC: 55", "CPU: 533 PLB: 133 OPB: 66 EBC: 66", + "CPU: 667 PLB: 133 OPB: 66 EBC: 66", "CPU: 667 PLB: 166 OPB: 83 EBC: 55", NULL }; @@ -97,6 +98,11 @@ static u8 boot_configs[][17] = { 0x87, 0x78, 0x82, 0x52, 0x09, 0x57, 0xa0, 0x30, 0x40, 0x08, 0x23, 0x50, 0x0d, 0x05, 0x00, 0x00 }, + { + (NOR_COMPATIBLE), + 0x87, 0x78, 0xa2, 0x56, 0x09, 0x57, 0xa0, 0x30, 0x40, + 0x08, 0x23, 0x50, 0x0d, 0x05, 0x00, 0x00 + }, { (NAND_COMPATIBLE | NOR_COMPATIBLE), 0x87, 0x78, 0xa2, 0x52, 0x09, 0xd7, 0xa0, 0x30, 0x40, -- cgit v1.2.3 From d2646554f529a9577515eceb0ec5eceee18244ba Mon Sep 17 00:00:00 2001 From: Tony Li Date: Thu, 18 Oct 2007 17:44:38 +0800 Subject: mpc83xx: pq-mds-pib.c typo error Correct to val8 from val. Signed-off-by: Tony Li Signed-off-by: Kim Phillips --- board/freescale/common/pq-mds-pib.c | 26 +++++++++++++------------- 1 file changed, 13 insertions(+), 13 deletions(-) diff --git a/board/freescale/common/pq-mds-pib.c b/board/freescale/common/pq-mds-pib.c index d79f2eb2e82..e4f96e8848d 100644 --- a/board/freescale/common/pq-mds-pib.c +++ b/board/freescale/common/pq-mds-pib.c @@ -79,19 +79,19 @@ int pib_init(void) printf("QOC3 ATM card on PMC0\n"); #elif defined(CONFIG_MPC832XEMDS) - val = 0; - i2c_write(0x26, 0x7, 1, &val, 1); - val = 0xf7; - i2c_write(0x26, 0x3, 1, &val, 1); - - val = 0; - i2c_write(0x21, 0x6, 1, &val, 1); - i2c_write(0x21, 0x7, 1, &val, 1); - - val = 0xdf; - i2c_write(0x21, 0x2, 1, &val, 1); - val = 0xef; - i2c_write(0x21, 0x3, 1, &val, 1); + val8 = 0; + i2c_write(0x26, 0x7, 1, &val8, 1); + val8 = 0xf7; + i2c_write(0x26, 0x3, 1, &val8, 1); + + val8 = 0; + i2c_write(0x21, 0x6, 1, &val8, 1); + i2c_write(0x21, 0x7, 1, &val8, 1); + + val8 = 0xdf; + i2c_write(0x21, 0x2, 1, &val8, 1); + val8 = 0xef; + i2c_write(0x21, 0x3, 1, &val8, 1); eieio(); -- cgit v1.2.3 From 281df457c1aa50d2752165d0c5c3282d4027b974 Mon Sep 17 00:00:00 2001 From: Tony Li Date: Thu, 18 Oct 2007 17:47:19 +0800 Subject: mpc83xx: Add configure entry for MPC83xx ATM support Add MPC8360EMDS_ATM_config and MPC832XEMDS_ATM_config into Makfile and MAKEALL Signed-off-by: Tony Li Signed-off-by: Kim Phillips --- MAKEALL | 2 ++ Makefile | 22 +++++++++++++++++++--- 2 files changed, 21 insertions(+), 3 deletions(-) diff --git a/MAKEALL b/MAKEALL index 2597d1fa352..20e81370f7c 100755 --- a/MAKEALL +++ b/MAKEALL @@ -301,10 +301,12 @@ LIST_83xx=" \ MPC8313ERDB_66 \ MPC8323ERDB \ MPC832XEMDS \ + MPC832XEMDS_ATM \ MPC8349EMDS \ MPC8349ITX \ MPC8349ITXGP \ MPC8360EMDS \ + MPC8360EMDS_ATM \ sbc8349 \ TQM834x \ " diff --git a/Makefile b/Makefile index e1cea0d36fb..ce7b07f9d18 100644 --- a/Makefile +++ b/Makefile @@ -1766,7 +1766,8 @@ MPC8323ERDB_config: unconfig MPC832XEMDS_config \ MPC832XEMDS_HOST_33_config \ MPC832XEMDS_HOST_66_config \ -MPC832XEMDS_SLAVE_config: unconfig +MPC832XEMDS_SLAVE_config \ +MPC832XEMDS_ATM_config: unconfig @mkdir -p $(obj)include @echo "" >$(obj)include/config.h ; \ if [ "$(findstring _HOST_,$@)" ] ; then \ @@ -1781,11 +1782,18 @@ MPC832XEMDS_SLAVE_config: unconfig if [ "$(findstring _33_,$@)" ] ; then \ echo -n "...33M ..." ; \ echo "#define PCI_33M" >>$(obj)include/config.h ; \ + echo "#define CONFIG_PQ_MDS_PIB 1" >>$(obj)include/config.h ; \ fi ; \ if [ "$(findstring _66_,$@)" ] ; then \ echo -n "...66M..." ; \ echo "#define PCI_66M" >>$(obj)include/config.h ; \ - fi ; + echo "#define CONFIG_PQ_MDS_PIB 1" >>$(obj)include/config.h ; \ + fi ; \ + if [ "$(findstring _ATM_,$@)" ] ; then \ + echo -n "...ATM..." ; \ + echo "#define CONFIG_PQ_MDS_PIB 1" >>$(obj)include/config.h ; \ + echo "#define CONFIG_PQ_MDS_PIB_ATM 1" >>$(obj)include/config.h ; \ + fi ; @$(MKCONFIG) -a MPC832XEMDS ppc mpc83xx mpc832xemds freescale MPC8349EMDS_config: unconfig @@ -1808,7 +1816,8 @@ MPC8349ITXGP_config: unconfig MPC8360EMDS_config \ MPC8360EMDS_HOST_33_config \ MPC8360EMDS_HOST_66_config \ -MPC8360EMDS_SLAVE_config: unconfig +MPC8360EMDS_SLAVE_config \ +MPC8360EMDS_ATM_config: unconfig @mkdir -p $(obj)include @echo "" >$(obj)include/config.h ; \ if [ "$(findstring _HOST_,$@)" ] ; then \ @@ -1823,10 +1832,17 @@ MPC8360EMDS_SLAVE_config: unconfig if [ "$(findstring _33_,$@)" ] ; then \ echo -n "...33M ..." ; \ echo "#define PCI_33M" >>$(obj)include/config.h ; \ + echo "#define CONFIG_PQ_MDS_PIB 1" >>$(obj)include/config.h ; \ fi ; \ if [ "$(findstring _66_,$@)" ] ; then \ echo -n "...66M..." ; \ echo "#define PCI_66M" >>$(obj)include/config.h ; \ + echo "#define CONFIG_PQ_MDS_PIB 1" >>$(obj)include/config.h ; \ + fi ; \ + if [ "$(findstring _ATM_,$@)" ] ; then \ + echo -n "...ATM..." ; \ + echo "#define CONFIG_PQ_MDS_PIB 1" >>$(obj)include/config.h ; \ + echo "#define CONFIG_PQ_MDS_PIB_ATM 1" >>$(obj)include/config.h ; \ fi ; @$(MKCONFIG) -a MPC8360EMDS ppc mpc83xx mpc8360emds freescale -- cgit v1.2.3 From 5441f61a3d8b7034f19fc1361183e936198e6dbb Mon Sep 17 00:00:00 2001 From: Detlev Zundel Date: Fri, 19 Oct 2007 16:47:26 +0200 Subject: Fix two typos. Signed-off-by: Detlev Zundel --- common/cmd_bootm.c | 2 +- common/cmd_dtt.c | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/common/cmd_bootm.c b/common/cmd_bootm.c index 6ebedfbc833..d8163494e82 100644 --- a/common/cmd_bootm.c +++ b/common/cmd_bootm.c @@ -466,7 +466,7 @@ U_BOOT_CMD( "\t'arg' can be the address of an initrd image\n" #if defined(CONFIG_OF_FLAT_TREE) || defined(CONFIG_OF_LIBFDT) "\tWhen booting a Linux kernel which requires a flat device-tree\n" - "\ta third argument is required which is the address of the of the\n" + "\ta third argument is required which is the address of the\n" "\tdevice-tree blob. To boot that kernel without an initrd image,\n" "\tuse a '-' for the second argument. If you do not pass a third\n" "\ta bd_info struct will be passed instead\n" diff --git a/common/cmd_dtt.c b/common/cmd_dtt.c index 8da95bf9d39..804d467f251 100644 --- a/common/cmd_dtt.c +++ b/common/cmd_dtt.c @@ -57,7 +57,7 @@ int do_dtt (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]) U_BOOT_CMD( dtt, 1, 1, do_dtt, - "dtt - Digital Thermometer and Themostat\n", + "dtt - Digital Thermometer and Thermostat\n", " - Read temperature from digital thermometer and thermostat.\n" ); -- cgit v1.2.3 From e1ce3cb617bb06f91f82f98915391175addf3e82 Mon Sep 17 00:00:00 2001 From: Kumar Gala Date: Tue, 2 Oct 2007 11:12:27 -0500 Subject: Remove magic numbers from cache related operations for mpc85xx The mpc85xx start code uses some magic numbers that we actually have #defines for in so use those instead. Signed-off-by: Kumar Gala --- cpu/mpc85xx/start.S | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/cpu/mpc85xx/start.S b/cpu/mpc85xx/start.S index 5d65190ede8..e5cabcac054 100644 --- a/cpu/mpc85xx/start.S +++ b/cpu/mpc85xx/start.S @@ -266,13 +266,13 @@ _start_e500: */ lis r3,CFG_INIT_RAM_ADDR@h ori r3,r3,CFG_INIT_RAM_ADDR@l - li r2,512 /* 512*32=16K */ + li r2,(CFG_DCACHE_SIZE / (2 * CFG_CACHELINE_SIZE)) mtctr r2 li r0,0 1: dcbz r0,r3 dcbtls 0,r0,r3 - addi r3,r3,32 + addi r3,r3,CFG_CACHELINE_SIZE bdnz 1b /* Jump out the last 4K page and continue to 'normal' start */ @@ -1066,11 +1066,11 @@ unlock_ram_in_cache: /* invalidate the INIT_RAM section */ lis r3,(CFG_INIT_RAM_ADDR & ~31)@h ori r3,r3,(CFG_INIT_RAM_ADDR & ~31)@l - li r4,512 + li r4,(CFG_DCACHE_SIZE / (2 * CFG_CACHELINE_SIZE)) mtctr r4 1: icbi r0,r3 dcbi r0,r3 - addi r3,r3,32 + addi r3,r3,CFG_CACHELINE_SIZE bdnz 1b sync /* Wait for all icbi to complete on bus */ isync -- cgit v1.2.3 From a3063eec775719b7e91023bbec3f64b3118791df Mon Sep 17 00:00:00 2001 From: Kumar Gala Date: Thu, 11 Oct 2007 00:18:48 -0500 Subject: Set OF_STDOUT_PATH to match the default console on MPC8568 MDS On the MPC8568 MDS we use ttyS0, UART0, etc. as the standard configured console. Make it so we match that config what we tell Linux as the early STDOUT console. Signed-off-by: Kumar Gala --- include/configs/MPC8568MDS.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/include/configs/MPC8568MDS.h b/include/configs/MPC8568MDS.h index ba744e99f8d..548e1582a8f 100644 --- a/include/configs/MPC8568MDS.h +++ b/include/configs/MPC8568MDS.h @@ -297,7 +297,7 @@ extern unsigned long get_clock_freq(void); #define OF_SOC "soc8568@e0000000" #define OF_QE "qe@e0080000" #define OF_TBCLK (bd->bi_busfreq / 8) -#define OF_STDOUT_PATH "/soc8568@e0000000/serial@4600" +#define OF_STDOUT_PATH "/soc8568@e0000000/serial@4500" /* * I2C -- cgit v1.2.3 From 7600d47b8f6a10019e537dc9a62aa1498df58d25 Mon Sep 17 00:00:00 2001 From: Kumar Gala Date: Thu, 11 Oct 2007 00:29:18 -0500 Subject: Improve handling of PCI interrupt device tree fixup on MPC85xx CDS On the MPC85xx CDS we have two issues: 1. The device tree fixup code did not check to see if the property we are trying to update is actually found. Its possible that it would update random memory starting at 0. 2. Newer Linux kernel's have moved the location of the PCI nodes to be sibilings of the soc node and not children. The explicit PATH to the PCI node would not be found for these device trees. Add the ability to handle both paths. In the future we shouldn't handle such fixups by explicit path. Signed-off-by: Kumar Gala --- board/cds/common/ft_board.c | 23 +++++++++++++++-------- include/configs/MPC8541CDS.h | 1 + include/configs/MPC8548CDS.h | 1 + include/configs/MPC8555CDS.h | 1 + 4 files changed, 18 insertions(+), 8 deletions(-) diff --git a/board/cds/common/ft_board.c b/board/cds/common/ft_board.c index 9d97905ca9b..3eda1009efd 100644 --- a/board/cds/common/ft_board.c +++ b/board/cds/common/ft_board.c @@ -37,17 +37,24 @@ static void cds_pci_fixup(void *blob) map = ft_get_prop(blob, "/" OF_SOC "/pci@8000/interrupt-map", &len); - len /= sizeof(u32); + if (!map) + map = ft_get_prop(blob, "/" OF_PCI "/interrupt-map", &len); - slot = get_pci_slot(); + if (map) { + len /= sizeof(u32); - for (i=0;ibi_busfreq / 8) #define OF_STDOUT_PATH "/soc8541@e0000000/serial@4600" +#define OF_PCI "pci@e0008000" /* * I2C diff --git a/include/configs/MPC8548CDS.h b/include/configs/MPC8548CDS.h index 60837151893..4edc7fd2b6a 100644 --- a/include/configs/MPC8548CDS.h +++ b/include/configs/MPC8548CDS.h @@ -340,6 +340,7 @@ extern unsigned long get_clock_freq(void); #define OF_SOC "soc8548@e0000000" #define OF_TBCLK (bd->bi_busfreq / 8) #define OF_STDOUT_PATH "/soc8548@e0000000/serial@4600" +#define OF_PCI "pci@e0008000" /* * I2C diff --git a/include/configs/MPC8555CDS.h b/include/configs/MPC8555CDS.h index 1d1b7c90795..c414bf033e4 100644 --- a/include/configs/MPC8555CDS.h +++ b/include/configs/MPC8555CDS.h @@ -316,6 +316,7 @@ extern unsigned long get_clock_freq(void); #define OF_SOC "soc8555@e0000000" #define OF_TBCLK (bd->bi_busfreq / 8) #define OF_STDOUT_PATH "/soc8555@e0000000/serial@4600" +#define OF_PCI "pci@e0008000" /* * I2C -- cgit v1.2.3 From 5c7ea64bb74a850a2b2303f853a8270695ad8602 Mon Sep 17 00:00:00 2001 From: Dan Wilson Date: Fri, 19 Oct 2007 11:33:48 -0500 Subject: tsec driver should clear RHALT on startup This was causing problems for some people. Signed-off-by: Alain Gravel Signed-off-by: Dan Wilson Signed-off-by: Andy Fleming --- drivers/tsec.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/tsec.c b/drivers/tsec.c index 4ff3339c7de..7ba8f0cace9 100644 --- a/drivers/tsec.c +++ b/drivers/tsec.c @@ -803,6 +803,7 @@ static void startup_tsec(struct eth_device *dev) /* Tell the DMA it is clear to go */ regs->dmactrl |= DMACTRL_INIT_SETTINGS; regs->tstat = TSTAT_CLEAR_THALT; + regs->rstat = RSTAT_CLEAR_RHALT; regs->dmactrl &= ~(DMACTRL_GRS | DMACTRL_GTS); } -- cgit v1.2.3 From 1e701e701304b3c3a3768ca83dd2ab7b9e88c77d Mon Sep 17 00:00:00 2001 From: "urwithsughosh@gmail.com" Date: Mon, 24 Sep 2007 13:36:01 -0400 Subject: MSR overwrite fix Hello, This patch fixes the MSR overwrite in the start.S when moving out of the last 4K page. Signed-off-by: Sughosh Ganu --- cpu/mpc85xx/start.S | 11 +++-------- 1 file changed, 3 insertions(+), 8 deletions(-) diff --git a/cpu/mpc85xx/start.S b/cpu/mpc85xx/start.S index e5cabcac054..ada6ea505fb 100644 --- a/cpu/mpc85xx/start.S +++ b/cpu/mpc85xx/start.S @@ -218,6 +218,8 @@ _start_e500: bdnz 0b /* Clear and set up some registers. */ + li r0,0 + mtmsr r0 li r0,0x0000 lis r1,0xffff mtspr DEC,r0 /* prevent dec exceptions */ @@ -277,7 +279,6 @@ _start_e500: /* Jump out the last 4K page and continue to 'normal' start */ #ifdef CFG_RAMBOOT - bl 3f b _start_cont #else /* Calculate absolute address in FLASH and jump there */ @@ -286,15 +287,9 @@ _start_e500: ori r3,r3,CFG_MONITOR_BASE@l addi r3,r3,_start_cont - _start + _START_OFFSET mtlr r3 + blr #endif -3: li r0,0 - mtspr SRR1,r0 /* Keep things disabled for now */ - mflr r1 - mtspr SRR0,r1 - rfi - isync - .text .globl _start _start: -- cgit v1.2.3 From df90968b48fb34fa9072fab150db2ac89678f537 Mon Sep 17 00:00:00 2001 From: "urwithsughosh@gmail.com" Date: Mon, 24 Sep 2007 13:32:13 -0400 Subject: Setting MSR[DE] in do_reset Hello, This patch ensures the soft reset of the board for the 85xx boards by setting the MSR[DE] in the do_reset function. Signed-off-by: Sughosh Ganu --- cpu/mpc85xx/cpu.c | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/cpu/mpc85xx/cpu.c b/cpu/mpc85xx/cpu.c index 08e04685f59..bbc54448daa 100644 --- a/cpu/mpc85xx/cpu.c +++ b/cpu/mpc85xx/cpu.c @@ -163,7 +163,12 @@ int do_reset (cmd_tbl_t *cmdtp, bd_t *bd, int flag, int argc, char *argv[]) * Initiate hard reset in debug control register DBCR0 * Make sure MSR[DE] = 1 */ - unsigned long val; + unsigned long val, msr; + + msr = mfmsr (); + msr |= MSR_DE; + mtmsr (msr); + val = mfspr(DBCR0); val |= 0x70000000; mtspr(DBCR0,val); -- cgit v1.2.3 From ff285ca07eda1ea4a8909848cc1cc604ec8fec9c Mon Sep 17 00:00:00 2001 From: Vlad Lungu Date: Thu, 4 Oct 2007 20:47:10 +0300 Subject: Fix NE2000 driver: Fixed typo in ne2000.h, thinko re n2k_inb() usage, don't try to do anything in eth_stop() if eth_init() was not called. Simplified RX path in order to avoid timeouts on really really fast NE2000 cards (read: qemu with internal tftp), NetLoop() is clever enough to cope with 1 packet per eth_rx(). Signed-off-by: Vlad Lungu --- drivers/ne2000.c | 36 +++++++++++++----------------------- drivers/ne2000.h | 2 +- 2 files changed, 14 insertions(+), 24 deletions(-) diff --git a/drivers/ne2000.c b/drivers/ne2000.c index b7ed8761659..0bfe74e5472 100644 --- a/drivers/ne2000.c +++ b/drivers/ne2000.c @@ -755,7 +755,7 @@ static void pcnet_reset_8390(void) #endif n2k_outb(E8390_NODMA+E8390_PAGE0+E8390_STOP, E8390_CMD); - n2k_outb(n2k_inb(nic_base + PCNET_RESET), PCNET_RESET); + n2k_outb(n2k_inb(PCNET_RESET), PCNET_RESET); for (i = 0; i < 100; i++) { if ((r = (n2k_inb(EN0_ISR) & ENISR_RESET)) != 0) @@ -833,6 +833,7 @@ static int plen[NB]; static int nrx = 0; static int pkey = -1; +static int initialized=0; void uboot_push_packet_len(int len) { PRINTK("pushed len = %d, nrx = %d\n", len, nrx); @@ -846,7 +847,12 @@ void uboot_push_packet_len(int len) { } plen[nrx] = len; dp83902a_recv(&pbuf[nrx*2000], len); +/*Just pass it to the upper layer*/ + NetReceive(&pbuf[nrx*2000], plen[nrx]); +/*eth_rx() was gutted, so this is not needed anymore*/ +#if 0 nrx++; +#endif } void uboot_push_tx_done(int key, int val) { @@ -903,37 +909,21 @@ int eth_init(bd_t *bd) { if (dp83902a_init() == false) return -1; dp83902a_start(dev_addr); + initialized=1; return 0; } void eth_halt() { PRINTK("### eth_halt\n"); - - dp83902a_stop(); + if(initialized) + dp83902a_stop(); + initialized=0; } int eth_rx() { - int j, tmo; - - PRINTK("### eth_rx\n"); - - tmo = get_timer (0) + TOUT * CFG_HZ; - while(1) { - dp83902a_poll(); - if (nrx > 0) { - for(j=0; j= tmo) { - printf("timeout during rx\n"); - return 0; - } - } - return 0; +dp83902a_poll(); +return 1; } int eth_send(volatile void *packet, int length) { diff --git a/drivers/ne2000.h b/drivers/ne2000.h index 2955533d7a7..c13d9f0bbb7 100644 --- a/drivers/ne2000.h +++ b/drivers/ne2000.h @@ -42,7 +42,7 @@ are GPL, so this is, of course, GPL. this file might be covered by the GNU General Public License. Alternative licenses for eCos may be arranged by contacting Red Hat, Inc. - at http://sources.redhat.com/ecos/ecos-license/ */ + at http://sources.redhat.com/ecos/ecos-license/ ------------------------------------------- ####ECOSGPLCOPYRIGHTEND#### ####BSDCOPYRIGHTBEGIN#### -- cgit v1.2.3 From 05bf4919c1ce49cdedadacd564d0786a8ed796a1 Mon Sep 17 00:00:00 2001 From: Wolfgang Denk Date: Sun, 21 Oct 2007 01:01:17 +0200 Subject: Minor coding style cleanup; update CHANGELOG Signed-off-by: Wolfgang Denk --- CHANGELOG | 248 +++++++++++++++++++++++++++++++++++++++++++++++++++++++ Makefile | 18 ++-- drivers/ne2000.c | 10 +-- 3 files changed, 259 insertions(+), 17 deletions(-) diff --git a/CHANGELOG b/CHANGELOG index b038749c9b3..05400013897 100644 --- a/CHANGELOG +++ b/CHANGELOG @@ -1,3 +1,206 @@ +commit ff285ca07eda1ea4a8909848cc1cc604ec8fec9c +Author: Vlad Lungu +Date: Thu Oct 4 20:47:10 2007 +0300 + + Fix NE2000 driver: + + Fixed typo in ne2000.h, thinko re n2k_inb() usage, don't try + to do anything in eth_stop() if eth_init() was not called. + Simplified RX path in order to avoid timeouts on really really + fast NE2000 cards (read: qemu with internal tftp), NetLoop() is + clever enough to cope with 1 packet per eth_rx(). + + Signed-off-by: Vlad Lungu + +commit 5441f61a3d8b7034f19fc1361183e936198e6dbb +Author: Detlev Zundel +Date: Fri Oct 19 16:47:26 2007 +0200 + + Fix two typos. + + Signed-off-by: Detlev Zundel + +commit 281df457c1aa50d2752165d0c5c3282d4027b974 +Author: Tony Li +Date: Thu Oct 18 17:47:19 2007 +0800 + + mpc83xx: Add configure entry for MPC83xx ATM support + + Add MPC8360EMDS_ATM_config and MPC832XEMDS_ATM_config into + Makfile and MAKEALL + + Signed-off-by: Tony Li + Signed-off-by: Kim Phillips + +commit d2646554f529a9577515eceb0ec5eceee18244ba +Author: Tony Li +Date: Thu Oct 18 17:44:38 2007 +0800 + + mpc83xx: pq-mds-pib.c typo error + + Correct to val8 from val. + + Signed-off-by: Tony Li + Signed-off-by: Kim Phillips + +commit 3e11ae80fec1ee12194940955431186abf6009c2 +Author: Stefan Roese +Date: Wed Oct 17 15:40:19 2007 +0200 + + ppc4xx: Add 667/133 (CPU/PLB) frequency setup to Sequoia bootstrap command + + Signed-off-by: Stefan Roese + +commit 7ee6ba1a056e4061ab4cfde30127e332e7957afd +Author: runet@innovsys.com +Date: Tue Oct 16 14:50:40 2007 -0500 + + Make MPC8266ADS board compile again. + + Signed-off-by: Runet Torgersen + +commit 2491167c245d8ebe6f2dbd8c4287aaa0d14fe93a +Author: Jon Loeliger +Date: Mon Aug 27 12:41:03 2007 -0500 + + 86xx: Allow for fewer DDR slots per memory controller. + + As a direct correlation exists between DDR DIMM slots + and SPD EEPROM addresses used to configure them, use + the individually defined SPD_EEPROM_ADDRESS* values to + determine if a DDR DIMM slot should have its SPD + configuration read or not. + + Effectively, this now allows for 1 or 2 DIMM slots + per memory controller. + + Signed-off-by: Jon Loeliger + +commit 4d4a945e189a2f384c66432316da2788a0ac1607 +Author: Rodolfo Giometti +Date: Mon Oct 15 11:59:17 2007 +0200 + + PXA USB OHCI: "usb stop" implementation. + + Some USB keys need to be switched off before loading the kernel + otherwise they can remain in an undefined status which prevents them + to be correctly recognized by the kernel. + + Signed-off-by: Rodolfo Giometti + +commit e2e93442e558cf1500e92861f99713b2f045ea22 +Author: Stefan Roese +Date: Mon Oct 15 11:39:00 2007 +0200 + + ppc4xx: Fix bug in I2C bootstrap values for Sequoia/Rainier + + The I2C bootstrap values that can be setup via the "bootstrap" command, + were setup incorrect regarding the generation of the internal sync PCI + clock. The values for PLB clock == 133MHz were slighly incorrect and the + values for PLB clock == 166MHz were totally incorrect. This could + lead to a hangup upon booting while PCI configuration scan. + + This patch fixes this issue and configures valid PCI divisor values + for the sync PCI clock, with respect to the provided external async + PCI frequency. + + Here the values of the formula in the chapter 14.2 "PCI clocking" + from the 440EPx users manual: + + AsyncPCICLK - 1MHz <= SyncPCIClk <= (2 * AsyncPCIClk) - 1MHz + + 33MHz async PCI frequency: + PLB = 133: + => 32 <= 44.3 <= 65 (div = 3) + + PLB = 166: + => 32 <= 55.3 <= 65 (div = 3) + + 66MHz async PCI frequency: + PLB = 133: + => 65 <= 66.5 <= 132 (div = 2) + + PLB = 166: + => 65 <= 83 <= 132 (div = 2) + + Signed-off-by: Stefan Roese + +commit 5a5958b7de70ae99f0e7cbd5c97ec1346e051587 +Author: Stefan Roese +Date: Mon Oct 15 11:29:33 2007 +0200 + + ppc4xx: Fix incorrect 33/66MHz PCI clock log-message on Sequoia & Yosemite + + The BCSR status bit for the 66MHz PCI operation was correctly + addressed (MSB/LSB problem). Now the correct currently setup + PCI frequency is displayed upon bootup. + + This patch also fixes this problem on Rainier & Yellowstone, since these + boards use the same souce code as Sequoia & Yosemite do. + + Signed-off-by: Stefan Roese + +commit da3aad55cbde80ab6e301aafa82a2c411aa53eff +Author: Martin Krause +Date: Wed Sep 26 17:55:56 2007 +0200 + + TQM860M: adjust for doubled flash sector size. + + Adjust flash map to support the new S29GLxxN (N-Type) Flashes with + doubled sector size. + + Signed-off-by: Martin Krause + +commit 9d29250e2e62f4bf20c7a20b4173d84c48f11f5d +Author: Jens Gehrlein +Date: Wed Sep 26 17:55:54 2007 +0200 + + TQM8xx: Fix CAN timing. + + Signed-off-by: Martin Krause + +commit d43e489baf02afae49077791fb22332d240d8656 +Author: Martin Krause +Date: Thu Sep 27 14:54:36 2007 +0200 + + TQM866M: fix SDRAM refresh + + At 133 MHz the current SDRAM refresh rate is too fast + (measured 4 * 1.17 us). + CFG_MAMR_PTA changes from 39 to 97. This result + in a refresh rate of 4 * 7.8 us at the default clock + 50 MHz. At 133 MHz the value will be then 4 * 2.9 us. + This is a compromise until a new method is found to + adjust the refresh rate. + + Signed-off-by: Martin Krause + +commit 9ef57bbee1c67cc01da2026c242c4692db32be36 +Author: Martin Krause +Date: Wed Sep 26 17:55:55 2007 +0200 + + TQM866M: adjust for doubled flash sector size. + + Adjust flash map to support the new S29GLxxN (N-Type) Flashes with + doubled sector size. + + Signed-off-by: Martin Krause + +commit f8bf90461d9bad2e6fed31fcebaf235f60dd6763 +Author: Michal Simek +Date: Sun Oct 14 16:12:29 2007 +0200 + + [FIX] XUPV2P change command handling + and remove code violation + +commit 636400198228d96983c06657b17f760f5989958e +Author: Wolfgang Denk +Date: Sun Oct 14 00:13:19 2007 +0200 + + Prepare for 1.3.0-rc3 release + + Signed-off-by: Wolfgang Denk + commit 68f14f77ca5fe5f9cc025c8cae101671f628309f Author: Jean-Christophe PLAGNIOL-VILLARD Date: Sat Sep 29 13:41:37 2007 +0200 @@ -109,6 +312,26 @@ Date: Mon Oct 1 09:51:50 2007 +0200 Signed-off-by: Grzegorz Bernacki +commit 785c13477b77dcd2e6c5128fffcdb4e1943f4818 +Author: Timo Ketola +Date: Mon Sep 24 14:50:32 2007 +0300 + + Bugfix: Use only one PTD for one endpoint + + Original isp116x-hcd code prepared multiple PTDs for longer than 16 + byte transfers for one endpoint. That is unnecessary because the + ISP116x is able to split long data from one PTD into multiple + transactions based on the buffer size of the endpoint. It also caused + serious problems if the endpoint NAKed some of the transactions. In + that case ISP116x wouldn't notice that the other PTDs were for the same + endpoint and would try the other PTDs possibly out of order. That would + break the whole transfer. + + This patch makes isp116x_submit_job to use one PTD for one transfer. + + Signed-off-by: Timo Ketola + Signed-off-by: Markus Klotzbuecher + commit 86ec86c04326c3913178a7679aa910de071da75d Author: Jean-Christophe PLAGNIOL-VILLARD Date: Thu Sep 27 23:27:47 2007 +0200 @@ -331,6 +554,12 @@ Date: Mon Sep 10 17:13:49 2007 +0900 Signed-off-by: Kyungmin Park +commit b49c90df6e7cfcfb8b862b8bbf8448dff5eed9a5 +Author: Michal Simek +Date: Sun Sep 16 20:51:57 2007 +0200 + + [FIX] remove files form repository + commit 67c31036acaaaa992fc346cc89db0909a7e733c4 Author: Wolfgang Denk Date: Sun Sep 16 17:10:04 2007 +0200 @@ -478,6 +707,25 @@ Date: Sat Sep 15 11:55:42 2007 +0200 [1] http://article.gmane.org/gmane.comp.boot-loaders.u-boot/31805 +commit 991b089d1ce5ad945725e3657a8f106dfa02a38e +Author: Michal Simek +Date: Sat Sep 15 00:03:35 2007 +0200 + + Synchronize with U-BOOT mainline + +commit d7fee32b7e61fe11c64e371cde79faa4768e8350 +Author: Sam Sparks +Date: Fri Sep 14 11:14:42 2007 -0600 + + Update MPC8349ITX*_config to place config.tmp in right place. + + MPC834ITX*_config does not store config.tmp at the correct locatation, + causing MPC8349ITXGP to have the wrong TEXT_BASE. + + Signed-off-by: Sam Sparks + Signed-off-by: Grant Likely + Signed-off-by: Kim Phillips + commit 6e7b7b6ea1b6d04dbe96242eb6a0c1c664c98e8c Author: Bartlomiej Sieka Date: Thu Sep 13 18:21:48 2007 +0200 diff --git a/Makefile b/Makefile index ce7b07f9d18..5643aa91213 100644 --- a/Makefile +++ b/Makefile @@ -393,7 +393,7 @@ BC3450_config: unconfig cpci5200_config: unconfig @$(MKCONFIG) -a cpci5200 ppc mpc5xxx cpci5200 esd -hmi1001_config: unconfig +hmi1001_config: unconfig @$(MKCONFIG) hmi1001 ppc mpc5xxx hmi1001 Lite5200_config \ @@ -435,7 +435,7 @@ icecube_5100_config: unconfig } @$(MKCONFIG) -a IceCube ppc mpc5xxx icecube -jupiter_config: unconfig +jupiter_config: unconfig @$(MKCONFIG) jupiter ppc mpc5xxx jupiter v38b_config: unconfig @@ -640,9 +640,9 @@ TQM5200_STK100_config: unconfig { echo "TEXT_BASE = 0xFFF00000" >$(obj)board/tqm5200/config.tmp ; \ } @$(MKCONFIG) -n $@ -a TQM5200 ppc mpc5xxx tqm5200 -uc101_config: unconfig +uc101_config: unconfig @$(MKCONFIG) uc101 ppc mpc5xxx uc101 -motionpro_config: unconfig +motionpro_config: unconfig @$(MKCONFIG) motionpro ppc mpc5xxx motionpro @@ -930,7 +930,7 @@ RPXlite_DW_NVRAM_config \ RPXlite_DW_NVRAM_64_config \ RPXlite_DW_NVRAM_LCD_config \ RPXlite_DW_NVRAM_64_LCD_config \ -RPXlite_DW_config: unconfig +RPXlite_DW_config: unconfig @mkdir -p $(obj)include @ >$(obj)include/config.h @[ -z "$(findstring _64,$@)" ] || \ @@ -1793,7 +1793,7 @@ MPC832XEMDS_ATM_config: unconfig echo -n "...ATM..." ; \ echo "#define CONFIG_PQ_MDS_PIB 1" >>$(obj)include/config.h ; \ echo "#define CONFIG_PQ_MDS_PIB_ATM 1" >>$(obj)include/config.h ; \ - fi ; + fi ; @$(MKCONFIG) -a MPC832XEMDS ppc mpc83xx mpc832xemds freescale MPC8349EMDS_config: unconfig @@ -2001,13 +2001,13 @@ AmigaOneG3SE_config: unconfig BAB7xx_config: unconfig @$(MKCONFIG) $(@:_config=) ppc 74xx_7xx bab7xx eltec -CPCI750_config: unconfig +CPCI750_config: unconfig @$(MKCONFIG) CPCI750 ppc 74xx_7xx cpci750 esd -DB64360_config: unconfig +DB64360_config: unconfig @$(MKCONFIG) DB64360 ppc 74xx_7xx db64360 Marvell -DB64460_config: unconfig +DB64460_config: unconfig @$(MKCONFIG) DB64460 ppc 74xx_7xx db64460 Marvell ELPPC_config: unconfig diff --git a/drivers/ne2000.c b/drivers/ne2000.c index 0bfe74e5472..695a1dc6c90 100644 --- a/drivers/ne2000.c +++ b/drivers/ne2000.c @@ -745,14 +745,12 @@ static void pcnet_reset_8390(void) PRINTK("nic base is %lx\n", nic_base); -#if 1 n2k_outb(E8390_NODMA+E8390_PAGE0+E8390_STOP, E8390_CMD); PRINTK("cmd (at %lx) is %x\n", nic_base+ E8390_CMD, n2k_inb(E8390_CMD)); n2k_outb(E8390_NODMA+E8390_PAGE1+E8390_STOP, E8390_CMD); PRINTK("cmd (at %lx) is %x\n", nic_base+ E8390_CMD, n2k_inb(E8390_CMD)); n2k_outb(E8390_NODMA+E8390_PAGE0+E8390_STOP, E8390_CMD); PRINTK("cmd (at %lx) is %x\n", nic_base+ E8390_CMD, n2k_inb(E8390_CMD)); -#endif n2k_outb(E8390_NODMA+E8390_PAGE0+E8390_STOP, E8390_CMD); n2k_outb(n2k_inb(PCNET_RESET), PCNET_RESET); @@ -847,12 +845,9 @@ void uboot_push_packet_len(int len) { } plen[nrx] = len; dp83902a_recv(&pbuf[nrx*2000], len); -/*Just pass it to the upper layer*/ + + /*Just pass it to the upper layer*/ NetReceive(&pbuf[nrx*2000], plen[nrx]); -/*eth_rx() was gutted, so this is not needed anymore*/ -#if 0 - nrx++; -#endif } void uboot_push_tx_done(int key, int val) { @@ -949,5 +944,4 @@ int eth_send(volatile void *packet, int length) { } return 0; } - #endif -- cgit v1.2.3 From e5f325fec5b48ae705c89522923ba5a2e37cd5c7 Mon Sep 17 00:00:00 2001 From: Shinya Kuribayashi Date: Sun, 21 Oct 2007 10:55:36 +0900 Subject: [MIPS] u-boot.lds: Remove duplicated .sdata section Signed-off-by: Shinya Kuribayashi --- board/dbau1x00/u-boot.lds | 3 --- board/gth2/u-boot.lds | 3 --- board/incaip/u-boot.lds | 3 --- board/pb1x00/u-boot.lds | 3 --- board/purple/u-boot.lds | 3 --- board/tb0229/u-boot.lds | 3 --- examples/mips.lds | 3 --- 7 files changed, 21 deletions(-) diff --git a/board/dbau1x00/u-boot.lds b/board/dbau1x00/u-boot.lds index 10c99179864..75a3af64b99 100644 --- a/board/dbau1x00/u-boot.lds +++ b/board/dbau1x00/u-boot.lds @@ -43,9 +43,6 @@ SECTIONS . = ALIGN(4); .data : { *(.data) } - . = ALIGN(4); - .sdata : { *(.sdata) } - _gp = ALIGN(16); __got_start = .; diff --git a/board/gth2/u-boot.lds b/board/gth2/u-boot.lds index 8ba0b6d4c12..69c8c9d51a8 100644 --- a/board/gth2/u-boot.lds +++ b/board/gth2/u-boot.lds @@ -43,9 +43,6 @@ SECTIONS . = ALIGN(4); .data : { *(.data) } - . = ALIGN(4); - .sdata : { *(.sdata) } - _gp = ALIGN(16); __got_start = .; diff --git a/board/incaip/u-boot.lds b/board/incaip/u-boot.lds index 10c99179864..75a3af64b99 100644 --- a/board/incaip/u-boot.lds +++ b/board/incaip/u-boot.lds @@ -43,9 +43,6 @@ SECTIONS . = ALIGN(4); .data : { *(.data) } - . = ALIGN(4); - .sdata : { *(.sdata) } - _gp = ALIGN(16); __got_start = .; diff --git a/board/pb1x00/u-boot.lds b/board/pb1x00/u-boot.lds index a2d19a84c9e..865be77bf3d 100644 --- a/board/pb1x00/u-boot.lds +++ b/board/pb1x00/u-boot.lds @@ -43,9 +43,6 @@ SECTIONS . = ALIGN(4); .data : { *(.data) } - . = ALIGN(4); - .sdata : { *(.sdata) } - _gp = ALIGN(16); __got_start = .; diff --git a/board/purple/u-boot.lds b/board/purple/u-boot.lds index 1bdac1f4a6f..6b3783f6643 100644 --- a/board/purple/u-boot.lds +++ b/board/purple/u-boot.lds @@ -53,9 +53,6 @@ SECTIONS . = ALIGN(4); .data : { *(.data) } - . = ALIGN(4); - .sdata : { *(.sdata) } - _gp = ALIGN(16); __got_start = .; diff --git a/board/tb0229/u-boot.lds b/board/tb0229/u-boot.lds index 30a2bc57eac..26d8c818b19 100644 --- a/board/tb0229/u-boot.lds +++ b/board/tb0229/u-boot.lds @@ -43,9 +43,6 @@ SECTIONS . = ALIGN(4); .data : { *(.data) } - . = ALIGN(4); - .sdata : { *(.sdata) } - _gp = ALIGN(16); __got_start = .; diff --git a/examples/mips.lds b/examples/mips.lds index 9d9849bf5c2..6f31eb7198e 100644 --- a/examples/mips.lds +++ b/examples/mips.lds @@ -39,9 +39,6 @@ SECTIONS . = ALIGN(4); .data : { *(.data) } - . = ALIGN(4); - .sdata : { *(.sdata) } - _gp = ALIGN(16); __got_start = .; -- cgit v1.2.3 From cbf2323b5b8285ea01acba7bbb905a3162d9b021 Mon Sep 17 00:00:00 2001 From: Shinya Kuribayashi Date: Sun, 21 Oct 2007 10:55:36 +0900 Subject: [MIPS] u-boot.lds: Fix __got_start and __got_end Ensure that __got_start points to top of the `.got', and __got_end points to bottom as well, so that we never fail to count num_got_entries. Signed-off-by: Shinya Kuribayashi --- board/dbau1x00/u-boot.lds | 8 +++++--- board/gth2/u-boot.lds | 8 +++++--- board/incaip/u-boot.lds | 8 +++++--- board/pb1x00/u-boot.lds | 8 +++++--- board/purple/u-boot.lds | 8 +++++--- board/tb0229/u-boot.lds | 8 +++++--- examples/mips.lds | 8 +++++--- 7 files changed, 35 insertions(+), 21 deletions(-) diff --git a/board/dbau1x00/u-boot.lds b/board/dbau1x00/u-boot.lds index 75a3af64b99..9c71ef7e4b7 100644 --- a/board/dbau1x00/u-boot.lds +++ b/board/dbau1x00/u-boot.lds @@ -45,9 +45,11 @@ SECTIONS _gp = ALIGN(16); - __got_start = .; - .got : { *(.got) } - __got_end = .; + .got : { + __got_start = .; + *(.got) + __got_end = .; + } .sdata : { *(.sdata) } diff --git a/board/gth2/u-boot.lds b/board/gth2/u-boot.lds index 69c8c9d51a8..0ab42db1b01 100644 --- a/board/gth2/u-boot.lds +++ b/board/gth2/u-boot.lds @@ -45,9 +45,11 @@ SECTIONS _gp = ALIGN(16); - __got_start = .; - .got : { *(.got) } - __got_end = .; + .got : { + __got_start = .; + *(.got) + __got_end = .; + } .sdata : { *(.sdata) } diff --git a/board/incaip/u-boot.lds b/board/incaip/u-boot.lds index 75a3af64b99..9c71ef7e4b7 100644 --- a/board/incaip/u-boot.lds +++ b/board/incaip/u-boot.lds @@ -45,9 +45,11 @@ SECTIONS _gp = ALIGN(16); - __got_start = .; - .got : { *(.got) } - __got_end = .; + .got : { + __got_start = .; + *(.got) + __got_end = .; + } .sdata : { *(.sdata) } diff --git a/board/pb1x00/u-boot.lds b/board/pb1x00/u-boot.lds index 865be77bf3d..7329e6aaa09 100644 --- a/board/pb1x00/u-boot.lds +++ b/board/pb1x00/u-boot.lds @@ -45,9 +45,11 @@ SECTIONS _gp = ALIGN(16); - __got_start = .; - .got : { *(.got) } - __got_end = .; + .got : { + __got_start = .; + *(.got) + __got_end = .; + } .sdata : { *(.sdata) } diff --git a/board/purple/u-boot.lds b/board/purple/u-boot.lds index 6b3783f6643..aa51cbf07c5 100644 --- a/board/purple/u-boot.lds +++ b/board/purple/u-boot.lds @@ -55,9 +55,11 @@ SECTIONS _gp = ALIGN(16); - __got_start = .; - .got : { *(.got) } - __got_end = .; + .got : { + __got_start = .; + *(.got) + __got_end = .; + } .sdata : { *(.sdata) } diff --git a/board/tb0229/u-boot.lds b/board/tb0229/u-boot.lds index 26d8c818b19..148f5e670b8 100644 --- a/board/tb0229/u-boot.lds +++ b/board/tb0229/u-boot.lds @@ -45,9 +45,11 @@ SECTIONS _gp = ALIGN(16); - __got_start = .; - .got : { *(.got) } - __got_end = .; + .got : { + __got_start = .; + *(.got) + __got_end = .; + } .sdata : { *(.sdata) } diff --git a/examples/mips.lds b/examples/mips.lds index 6f31eb7198e..3bd573cc54a 100644 --- a/examples/mips.lds +++ b/examples/mips.lds @@ -41,9 +41,11 @@ SECTIONS _gp = ALIGN(16); - __got_start = .; - .got : { *(.got) } - __got_end = .; + .got : { + __got_start = .; + *(.got) + __got_end = .; + } .sdata : { *(.sdata) } -- cgit v1.2.3 From 22069215eb7adf5a3888bf7c7784ea9d70a72cd0 Mon Sep 17 00:00:00 2001 From: Shinya Kuribayashi Date: Sun, 21 Oct 2007 10:55:36 +0900 Subject: [MIPS] Fix $gp usage Now we load $gp with _GLOBAL_OFFSET_TABLE_, but this is incorrect use. As a general principle, we should use _gp for $gp. Thanks to linker script's help we fortunately have _gp which equals to _GLOBAL_OFFSET_TABLE_. But once _gp gets out of alignment, we will not be able to access to GOT entires, global variables and procedure entry points. The right thing to do is to use _gp. This patch also introduce a new symbol `.gpword _GLOBAL_OFFSET_TABLE_' which holds the offset from _gp. When updating GOT entries, we use this offset and _gp to calculate the final _GLOBAL_OFFSET_TABLE_. This patch is originally submitted by Vlad Lungu , then I made some change to leave over num_got_entries. Signed-off-by: Shinya Kuribayashi Cc: Vlad Lungu --- cpu/mips/start.S | 19 +++++++++++++------ 1 file changed, 13 insertions(+), 6 deletions(-) diff --git a/cpu/mips/start.S b/cpu/mips/start.S index e91e2137d70..074d01d2dde 100644 --- a/cpu/mips/start.S +++ b/cpu/mips/start.S @@ -234,11 +234,11 @@ reset: li t0, CONF_CM_UNCACHED mtc0 t0, CP0_CONFIG - /* Initialize GOT pointer. + /* Initialize $gp. */ bal 1f nop - .word _GLOBAL_OFFSET_TABLE_ + .word _gp 1: move gp, ra lw t1, 0(ra) @@ -306,9 +306,9 @@ relocate_code: move t1, a2 /* - * Fix GOT pointer: + * Fix $gp: * - * New GOT-PTR = (old GOT-PTR - CFG_MONITOR_BASE) + Destination Address + * New $gp = (Old $gp - CFG_MONITOR_BASE) + Destination Address */ move t6, gp sub gp, CFG_MONITOR_BASE @@ -341,15 +341,22 @@ relocate_code: j t0 nop + .gpword _GLOBAL_OFFSET_TABLE_ /* _GLOBAL_OFFSET_TABLE_ - _gp */ .word uboot_end_data .word uboot_end .word num_got_entries in_ram: - /* Now we want to update GOT. + /* + * Now we want to update GOT. + * + * GOT[0] is reserved. GOT[1] is also reserved for the dynamic object + * generated by GNU ld. Skip these reserved entries from relocation. */ lw t3, -4(t0) /* t3 <-- num_got_entries */ - addi t4, gp, 8 /* Skipping first two entries. */ + lw t4, -16(t0) /* t4 <-- (_GLOBAL_OFFSET_TABLE_ - _gp) */ + add t4, t4, gp /* t4 now holds _GLOBAL_OFFSET_TABLE_ */ + addi t4, t4, 8 /* Skipping first two entries. */ li t2, 2 1: lw t1, 0(t4) -- cgit v1.2.3 From eb700636db017d310edaeb559b13d82588560674 Mon Sep 17 00:00:00 2001 From: Shinya Kuribayashi Date: Sun, 21 Oct 2007 10:55:37 +0900 Subject: [MIPS] u-boot.lds: Define _gp in a standard manner Signed-off-by: Shinya Kuribayashi --- board/dbau1x00/u-boot.lds | 3 ++- board/gth2/u-boot.lds | 3 ++- board/incaip/u-boot.lds | 3 ++- board/pb1x00/u-boot.lds | 3 ++- board/purple/u-boot.lds | 3 ++- board/tb0229/u-boot.lds | 3 ++- examples/mips.lds | 3 ++- 7 files changed, 14 insertions(+), 7 deletions(-) diff --git a/board/dbau1x00/u-boot.lds b/board/dbau1x00/u-boot.lds index 9c71ef7e4b7..9639b81acc6 100644 --- a/board/dbau1x00/u-boot.lds +++ b/board/dbau1x00/u-boot.lds @@ -43,7 +43,8 @@ SECTIONS . = ALIGN(4); .data : { *(.data) } - _gp = ALIGN(16); + . = .; + _gp = ALIGN(16) + 0x7ff0; .got : { __got_start = .; diff --git a/board/gth2/u-boot.lds b/board/gth2/u-boot.lds index 0ab42db1b01..90432cb8887 100644 --- a/board/gth2/u-boot.lds +++ b/board/gth2/u-boot.lds @@ -43,7 +43,8 @@ SECTIONS . = ALIGN(4); .data : { *(.data) } - _gp = ALIGN(16); + . = .; + _gp = ALIGN(16) + 0x7ff0; .got : { __got_start = .; diff --git a/board/incaip/u-boot.lds b/board/incaip/u-boot.lds index 9c71ef7e4b7..9639b81acc6 100644 --- a/board/incaip/u-boot.lds +++ b/board/incaip/u-boot.lds @@ -43,7 +43,8 @@ SECTIONS . = ALIGN(4); .data : { *(.data) } - _gp = ALIGN(16); + . = .; + _gp = ALIGN(16) + 0x7ff0; .got : { __got_start = .; diff --git a/board/pb1x00/u-boot.lds b/board/pb1x00/u-boot.lds index 7329e6aaa09..363d974c48f 100644 --- a/board/pb1x00/u-boot.lds +++ b/board/pb1x00/u-boot.lds @@ -43,7 +43,8 @@ SECTIONS . = ALIGN(4); .data : { *(.data) } - _gp = ALIGN(16); + . = .; + _gp = ALIGN(16) + 0x7ff0; .got : { __got_start = .; diff --git a/board/purple/u-boot.lds b/board/purple/u-boot.lds index aa51cbf07c5..e7ec012c3be 100644 --- a/board/purple/u-boot.lds +++ b/board/purple/u-boot.lds @@ -53,7 +53,8 @@ SECTIONS . = ALIGN(4); .data : { *(.data) } - _gp = ALIGN(16); + . = .; + _gp = ALIGN(16) + 0x7ff0; .got : { __got_start = .; diff --git a/board/tb0229/u-boot.lds b/board/tb0229/u-boot.lds index 148f5e670b8..b2fa9f22dc9 100644 --- a/board/tb0229/u-boot.lds +++ b/board/tb0229/u-boot.lds @@ -43,7 +43,8 @@ SECTIONS . = ALIGN(4); .data : { *(.data) } - _gp = ALIGN(16); + . = .; + _gp = ALIGN(16) + 0x7ff0; .got : { __got_start = .; diff --git a/examples/mips.lds b/examples/mips.lds index 3bd573cc54a..a7707287a24 100644 --- a/examples/mips.lds +++ b/examples/mips.lds @@ -39,7 +39,8 @@ SECTIONS . = ALIGN(4); .data : { *(.data) } - _gp = ALIGN(16); + . = .; + _gp = ALIGN(16) + 0x7ff0; .got : { __got_start = .; -- cgit v1.2.3 From 00101dd7a32d12f698150123e47e4b3420279f86 Mon Sep 17 00:00:00 2001 From: Shinya Kuribayashi Date: Sun, 21 Oct 2007 21:30:42 +0900 Subject: [MIPS] Add PIC-related switches to PLATFORM_{CPP,LD}FLAGS and cleanup Signed-off-by: Shinya Kuribayashi --- cpu/mips/config.mk | 2 +- mips_config.mk | 25 +++++++++++++++++++++++++ 2 files changed, 26 insertions(+), 1 deletion(-) diff --git a/cpu/mips/config.mk b/cpu/mips/config.mk index b29986e26b7..487c4eb5d64 100644 --- a/cpu/mips/config.mk +++ b/cpu/mips/config.mk @@ -35,6 +35,6 @@ else ENDIANNESS = -EB endif -MIPSFLAGS += $(ENDIANNESS) -mabicalls +MIPSFLAGS += $(ENDIANNESS) PLATFORM_CPPFLAGS += $(MIPSFLAGS) diff --git a/mips_config.mk b/mips_config.mk index d8aa5fa777b..67fb67d291d 100644 --- a/mips_config.mk +++ b/mips_config.mk @@ -22,3 +22,28 @@ # PLATFORM_CPPFLAGS += -DCONFIG_MIPS -D__MIPS__ + +# +# From Linux arch/mips/Makefile +# +# GCC uses -G 0 -mabicalls -fpic as default. We don't want PIC in the kernel +# code since it only slows down the whole thing. At some point we might make +# use of global pointer optimizations but their use of $28 conflicts with +# the current pointer optimization. +# +# The DECStation requires an ECOFF kernel for remote booting, other MIPS +# machines may also. Since BFD is incredibly buggy with respect to +# crossformat linking we rely on the elf2ecoff tool for format conversion. +# +# cflags-y += -G 0 -mno-abicalls -fno-pic -pipe +# cflags-y += -msoft-float +# LDFLAGS_vmlinux += -G 0 -static -n -nostdlib +# MODFLAGS += -mlong-calls +# + +# +# Meanwhile, U-Boot rely on PIC. We add proper switches explicitly. +# +PLATFORM_CPPFLAGS += -G 0 -mabicalls -fpic -pipe +PLATFORM_CPPFLAGS += -msoft-float +PLATFORM_LDFLAGS += -G 0 -static -n -nostdlib -- cgit v1.2.3 From de9a738faa7c2f47286119c3bfebc3dfbfe7d86d Mon Sep 17 00:00:00 2001 From: Vlad Lungu Date: Sun, 21 Oct 2007 22:10:10 +0900 Subject: [MIPS] Fix UNCACHED_SDRAM PHYSADDR is for physical address, KSEG1ADDR is for uncached. Signed-off-by: Vlad Lungu Signed-off-by: Shinya Kuribayashi --- include/asm-mips/addrspace.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/include/asm-mips/addrspace.h b/include/asm-mips/addrspace.h index b8214b1c859..0e6abd7d0fa 100644 --- a/include/asm-mips/addrspace.h +++ b/include/asm-mips/addrspace.h @@ -49,7 +49,7 @@ cannot access physical memory directly from core */ #define UNCACHED_SDRAM(a) (((unsigned long)(a)) | 0x20000000) #else /* !CONFIG_AU1X00 */ -#define UNCACHED_SDRAM(a) PHYSADDR(a) +#define UNCACHED_SDRAM(a) KSEG1ADDR(a) #endif /* CONFIG_AU1X00 */ #endif /* __ASSEMBLY__ */ /* -- cgit v1.2.3 From 7a9348728ebda63cdbaacffd83099aa71d9d4c54 Mon Sep 17 00:00:00 2001 From: Peter Pearse Date: Tue, 23 Oct 2007 10:22:16 +0100 Subject: Move PL01* serial drivers to drivers/serial and adjust Makefiles. --- drivers/Makefile | 2 +- drivers/serial/Makefile | 2 +- drivers/serial/serial_pl010.c | 171 ++++++++++++++++++++++++++++++++++++++++++ drivers/serial/serial_pl011.c | 161 +++++++++++++++++++++++++++++++++++++++ drivers/serial/serial_pl011.h | 137 +++++++++++++++++++++++++++++++++ drivers/serial_pl010.c | 171 ------------------------------------------ drivers/serial_pl011.c | 161 --------------------------------------- drivers/serial_pl011.h | 137 --------------------------------- 8 files changed, 471 insertions(+), 471 deletions(-) create mode 100644 drivers/serial/serial_pl010.c create mode 100644 drivers/serial/serial_pl011.c create mode 100644 drivers/serial/serial_pl011.h delete mode 100644 drivers/serial_pl010.c delete mode 100644 drivers/serial_pl011.c delete mode 100644 drivers/serial_pl011.h diff --git a/drivers/Makefile b/drivers/Makefile index 6bf05ccad19..1889698bca8 100755 --- a/drivers/Makefile +++ b/drivers/Makefile @@ -42,7 +42,7 @@ COBJS = 3c589.o 5701rls.o ali512x.o at45.o ata_piix.o atmel_usart.o \ s3c4510b_eth.o s3c4510b_uart.o \ sed13806.o sed156x.o \ serial.o serial_max3100.o \ - serial_pl010.o serial_pl011.o serial_xuartlite.o \ + serial_xuartlite.o \ sil680.o sl811_usb.o sm501.o smc91111.o smiLynxEM.o \ status_led.o sym53c8xx.o systemace.o ahci.o \ ti_pci1410a.o tigon3.o tsec.o \ diff --git a/drivers/serial/Makefile b/drivers/serial/Makefile index 93c68dd2e08..40f3d672ec9 100644 --- a/drivers/serial/Makefile +++ b/drivers/serial/Makefile @@ -25,7 +25,7 @@ include $(TOPDIR)/config.mk LIB := $(obj)libserial.a -COBJS := mcfuart.o +COBJS := mcfuart.o serial_pl010.o serial_pl011.o SRCS := $(COBJS:.o=.c) OBJS := $(addprefix $(obj),$(COBJS)) diff --git a/drivers/serial/serial_pl010.c b/drivers/serial/serial_pl010.c new file mode 100644 index 00000000000..417b6aeda64 --- /dev/null +++ b/drivers/serial/serial_pl010.c @@ -0,0 +1,171 @@ +/* + * (C) Copyright 2000 + * Rob Taylor, Flying Pig Systems. robt@flyingpig.com. + * + * (C) Copyright 2004 + * ARM Ltd. + * Philippe Robin, + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* Simple U-Boot driver for the PrimeCell PL011 UARTs on the IntegratorCP */ +/* Should be fairly simple to make it work with the PL010 as well */ + +#include + +#ifdef CFG_PL010_SERIAL + +#include "serial_pl011.h" + +#define IO_WRITE(addr, val) (*(volatile unsigned int *)(addr) = (val)) +#define IO_READ(addr) (*(volatile unsigned int *)(addr)) + +/* Integrator AP has two UARTs, we use the first one, at 38400-8-N-1 */ +#define CONSOLE_PORT CONFIG_CONS_INDEX +#define baudRate CONFIG_BAUDRATE +static volatile unsigned char *const port[] = CONFIG_PL01x_PORTS; +#define NUM_PORTS (sizeof(port)/sizeof(port[0])) + + +static void pl010_putc (int portnum, char c); +static int pl010_getc (int portnum); +static int pl010_tstc (int portnum); + + +int serial_init (void) +{ + unsigned int divisor; + + /* + ** First, disable everything. + */ + IO_WRITE (port[CONSOLE_PORT] + UART_PL010_CR, 0x0); + + /* + ** Set baud rate + ** + */ + switch (baudRate) { + case 9600: + divisor = UART_PL010_BAUD_9600; + break; + + case 19200: + divisor = UART_PL010_BAUD_9600; + break; + + case 38400: + divisor = UART_PL010_BAUD_38400; + break; + + case 57600: + divisor = UART_PL010_BAUD_57600; + break; + + case 115200: + divisor = UART_PL010_BAUD_115200; + break; + + default: + divisor = UART_PL010_BAUD_38400; + } + + IO_WRITE (port[CONSOLE_PORT] + UART_PL010_LCRM, + ((divisor & 0xf00) >> 8)); + IO_WRITE (port[CONSOLE_PORT] + UART_PL010_LCRL, (divisor & 0xff)); + + /* + ** Set the UART to be 8 bits, 1 stop bit, no parity, fifo enabled. + */ + IO_WRITE (port[CONSOLE_PORT] + UART_PL010_LCRH, + (UART_PL010_LCRH_WLEN_8 | UART_PL010_LCRH_FEN)); + + /* + ** Finally, enable the UART + */ + IO_WRITE (port[CONSOLE_PORT] + UART_PL010_CR, (UART_PL010_CR_UARTEN)); + + return (0); +} + +void serial_putc (const char c) +{ + if (c == '\n') + pl010_putc (CONSOLE_PORT, '\r'); + + pl010_putc (CONSOLE_PORT, c); +} + +void serial_puts (const char *s) +{ + while (*s) { + serial_putc (*s++); + } +} + +int serial_getc (void) +{ + return pl010_getc (CONSOLE_PORT); +} + +int serial_tstc (void) +{ + return pl010_tstc (CONSOLE_PORT); +} + +void serial_setbrg (void) +{ +} + +static void pl010_putc (int portnum, char c) +{ + /* Wait until there is space in the FIFO */ + while (IO_READ (port[portnum] + UART_PL01x_FR) & UART_PL01x_FR_TXFF); + + /* Send the character */ + IO_WRITE (port[portnum] + UART_PL01x_DR, c); +} + +static int pl010_getc (int portnum) +{ + unsigned int data; + + /* Wait until there is data in the FIFO */ + while (IO_READ (port[portnum] + UART_PL01x_FR) & UART_PL01x_FR_RXFE); + + data = IO_READ (port[portnum] + UART_PL01x_DR); + + /* Check for an error flag */ + if (data & 0xFFFFFF00) { + /* Clear the error */ + IO_WRITE (port[portnum] + UART_PL01x_ECR, 0xFFFFFFFF); + return -1; + } + + return (int) data; +} + +static int pl010_tstc (int portnum) +{ + return !(IO_READ (port[portnum] + UART_PL01x_FR) & + UART_PL01x_FR_RXFE); +} + +#endif diff --git a/drivers/serial/serial_pl011.c b/drivers/serial/serial_pl011.c new file mode 100644 index 00000000000..4d35fe5e9ed --- /dev/null +++ b/drivers/serial/serial_pl011.c @@ -0,0 +1,161 @@ +/* + * (C) Copyright 2000 + * Rob Taylor, Flying Pig Systems. robt@flyingpig.com. + * + * (C) Copyright 2004 + * ARM Ltd. + * Philippe Robin, + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* Simple U-Boot driver for the PrimeCell PL011 UARTs on the IntegratorCP */ +/* Should be fairly simple to make it work with the PL010 as well */ + +#include + +#ifdef CFG_PL011_SERIAL + +#include "serial_pl011.h" + +#define IO_WRITE(addr, val) (*(volatile unsigned int *)(addr) = (val)) +#define IO_READ(addr) (*(volatile unsigned int *)(addr)) + +/* + * IntegratorCP has two UARTs, use the first one, at 38400-8-N-1 + * Versatile PB has four UARTs. + */ + +#define CONSOLE_PORT CONFIG_CONS_INDEX +#define baudRate CONFIG_BAUDRATE +static volatile unsigned char *const port[] = CONFIG_PL01x_PORTS; +#define NUM_PORTS (sizeof(port)/sizeof(port[0])) + +static void pl011_putc (int portnum, char c); +static int pl011_getc (int portnum); +static int pl011_tstc (int portnum); + + +int serial_init (void) +{ + unsigned int temp; + unsigned int divider; + unsigned int remainder; + unsigned int fraction; + + /* + ** First, disable everything. + */ + IO_WRITE (port[CONSOLE_PORT] + UART_PL011_CR, 0x0); + + /* + ** Set baud rate + ** + ** IBRD = UART_CLK / (16 * BAUD_RATE) + ** FBRD = ROUND((64 * MOD(UART_CLK,(16 * BAUD_RATE))) / (16 * BAUD_RATE)) + */ + temp = 16 * baudRate; + divider = CONFIG_PL011_CLOCK / temp; + remainder = CONFIG_PL011_CLOCK % temp; + temp = (8 * remainder) / baudRate; + fraction = (temp >> 1) + (temp & 1); + + IO_WRITE (port[CONSOLE_PORT] + UART_PL011_IBRD, divider); + IO_WRITE (port[CONSOLE_PORT] + UART_PL011_FBRD, fraction); + + /* + ** Set the UART to be 8 bits, 1 stop bit, no parity, fifo enabled. + */ + IO_WRITE (port[CONSOLE_PORT] + UART_PL011_LCRH, + (UART_PL011_LCRH_WLEN_8 | UART_PL011_LCRH_FEN)); + + /* + ** Finally, enable the UART + */ + IO_WRITE (port[CONSOLE_PORT] + UART_PL011_CR, + (UART_PL011_CR_UARTEN | UART_PL011_CR_TXE | + UART_PL011_CR_RXE)); + + return 0; +} + +void serial_putc (const char c) +{ + if (c == '\n') + pl011_putc (CONSOLE_PORT, '\r'); + + pl011_putc (CONSOLE_PORT, c); +} + +void serial_puts (const char *s) +{ + while (*s) { + serial_putc (*s++); + } +} + +int serial_getc (void) +{ + return pl011_getc (CONSOLE_PORT); +} + +int serial_tstc (void) +{ + return pl011_tstc (CONSOLE_PORT); +} + +void serial_setbrg (void) +{ +} + +static void pl011_putc (int portnum, char c) +{ + /* Wait until there is space in the FIFO */ + while (IO_READ (port[portnum] + UART_PL01x_FR) & UART_PL01x_FR_TXFF); + + /* Send the character */ + IO_WRITE (port[portnum] + UART_PL01x_DR, c); +} + +static int pl011_getc (int portnum) +{ + unsigned int data; + + /* Wait until there is data in the FIFO */ + while (IO_READ (port[portnum] + UART_PL01x_FR) & UART_PL01x_FR_RXFE); + + data = IO_READ (port[portnum] + UART_PL01x_DR); + + /* Check for an error flag */ + if (data & 0xFFFFFF00) { + /* Clear the error */ + IO_WRITE (port[portnum] + UART_PL01x_ECR, 0xFFFFFFFF); + return -1; + } + + return (int) data; +} + +static int pl011_tstc (int portnum) +{ + return !(IO_READ (port[portnum] + UART_PL01x_FR) & + UART_PL01x_FR_RXFE); +} + +#endif diff --git a/drivers/serial/serial_pl011.h b/drivers/serial/serial_pl011.h new file mode 100644 index 00000000000..5f20fdd108a --- /dev/null +++ b/drivers/serial/serial_pl011.h @@ -0,0 +1,137 @@ +/* + * (C) Copyright 2003, 2004 + * ARM Ltd. + * Philippe Robin, + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * ARM PrimeCell UART's (PL010 & PL011) + * ------------------------------------ + * + * Definitions common to both PL010 & PL011 + * + */ +#define UART_PL01x_DR 0x00 /* Data read or written from the interface. */ +#define UART_PL01x_RSR 0x04 /* Receive status register (Read). */ +#define UART_PL01x_ECR 0x04 /* Error clear register (Write). */ +#define UART_PL01x_FR 0x18 /* Flag register (Read only). */ + +#define UART_PL01x_RSR_OE 0x08 +#define UART_PL01x_RSR_BE 0x04 +#define UART_PL01x_RSR_PE 0x02 +#define UART_PL01x_RSR_FE 0x01 + +#define UART_PL01x_FR_TXFE 0x80 +#define UART_PL01x_FR_RXFF 0x40 +#define UART_PL01x_FR_TXFF 0x20 +#define UART_PL01x_FR_RXFE 0x10 +#define UART_PL01x_FR_BUSY 0x08 +#define UART_PL01x_FR_TMSK (UART_PL01x_FR_TXFF + UART_PL01x_FR_BUSY) + +/* + * PL010 definitions + * + */ +#define UART_PL010_LCRH 0x08 /* Line control register, high byte. */ +#define UART_PL010_LCRM 0x0C /* Line control register, middle byte. */ +#define UART_PL010_LCRL 0x10 /* Line control register, low byte. */ +#define UART_PL010_CR 0x14 /* Control register. */ +#define UART_PL010_IIR 0x1C /* Interrupt indentification register (Read). */ +#define UART_PL010_ICR 0x1C /* Interrupt clear register (Write). */ +#define UART_PL010_ILPR 0x20 /* IrDA low power counter register. */ + +#define UART_PL010_CR_LPE (1 << 7) +#define UART_PL010_CR_RTIE (1 << 6) +#define UART_PL010_CR_TIE (1 << 5) +#define UART_PL010_CR_RIE (1 << 4) +#define UART_PL010_CR_MSIE (1 << 3) +#define UART_PL010_CR_IIRLP (1 << 2) +#define UART_PL010_CR_SIREN (1 << 1) +#define UART_PL010_CR_UARTEN (1 << 0) + +#define UART_PL010_LCRH_WLEN_8 (3 << 5) +#define UART_PL010_LCRH_WLEN_7 (2 << 5) +#define UART_PL010_LCRH_WLEN_6 (1 << 5) +#define UART_PL010_LCRH_WLEN_5 (0 << 5) +#define UART_PL010_LCRH_FEN (1 << 4) +#define UART_PL010_LCRH_STP2 (1 << 3) +#define UART_PL010_LCRH_EPS (1 << 2) +#define UART_PL010_LCRH_PEN (1 << 1) +#define UART_PL010_LCRH_BRK (1 << 0) + + +#define UART_PL010_BAUD_460800 1 +#define UART_PL010_BAUD_230400 3 +#define UART_PL010_BAUD_115200 7 +#define UART_PL010_BAUD_57600 15 +#define UART_PL010_BAUD_38400 23 +#define UART_PL010_BAUD_19200 47 +#define UART_PL010_BAUD_14400 63 +#define UART_PL010_BAUD_9600 95 +#define UART_PL010_BAUD_4800 191 +#define UART_PL010_BAUD_2400 383 +#define UART_PL010_BAUD_1200 767 +/* + * PL011 definitions + * + */ +#define UART_PL011_IBRD 0x24 +#define UART_PL011_FBRD 0x28 +#define UART_PL011_LCRH 0x2C +#define UART_PL011_CR 0x30 +#define UART_PL011_IMSC 0x38 +#define UART_PL011_PERIPH_ID0 0xFE0 + +#define UART_PL011_LCRH_SPS (1 << 7) +#define UART_PL011_LCRH_WLEN_8 (3 << 5) +#define UART_PL011_LCRH_WLEN_7 (2 << 5) +#define UART_PL011_LCRH_WLEN_6 (1 << 5) +#define UART_PL011_LCRH_WLEN_5 (0 << 5) +#define UART_PL011_LCRH_FEN (1 << 4) +#define UART_PL011_LCRH_STP2 (1 << 3) +#define UART_PL011_LCRH_EPS (1 << 2) +#define UART_PL011_LCRH_PEN (1 << 1) +#define UART_PL011_LCRH_BRK (1 << 0) + +#define UART_PL011_CR_CTSEN (1 << 15) +#define UART_PL011_CR_RTSEN (1 << 14) +#define UART_PL011_CR_OUT2 (1 << 13) +#define UART_PL011_CR_OUT1 (1 << 12) +#define UART_PL011_CR_RTS (1 << 11) +#define UART_PL011_CR_DTR (1 << 10) +#define UART_PL011_CR_RXE (1 << 9) +#define UART_PL011_CR_TXE (1 << 8) +#define UART_PL011_CR_LPE (1 << 7) +#define UART_PL011_CR_IIRLP (1 << 2) +#define UART_PL011_CR_SIREN (1 << 1) +#define UART_PL011_CR_UARTEN (1 << 0) + +#define UART_PL011_IMSC_OEIM (1 << 10) +#define UART_PL011_IMSC_BEIM (1 << 9) +#define UART_PL011_IMSC_PEIM (1 << 8) +#define UART_PL011_IMSC_FEIM (1 << 7) +#define UART_PL011_IMSC_RTIM (1 << 6) +#define UART_PL011_IMSC_TXIM (1 << 5) +#define UART_PL011_IMSC_RXIM (1 << 4) +#define UART_PL011_IMSC_DSRMIM (1 << 3) +#define UART_PL011_IMSC_DCDMIM (1 << 2) +#define UART_PL011_IMSC_CTSMIM (1 << 1) +#define UART_PL011_IMSC_RIMIM (1 << 0) diff --git a/drivers/serial_pl010.c b/drivers/serial_pl010.c deleted file mode 100644 index 417b6aeda64..00000000000 --- a/drivers/serial_pl010.c +++ /dev/null @@ -1,171 +0,0 @@ -/* - * (C) Copyright 2000 - * Rob Taylor, Flying Pig Systems. robt@flyingpig.com. - * - * (C) Copyright 2004 - * ARM Ltd. - * Philippe Robin, - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/* Simple U-Boot driver for the PrimeCell PL011 UARTs on the IntegratorCP */ -/* Should be fairly simple to make it work with the PL010 as well */ - -#include - -#ifdef CFG_PL010_SERIAL - -#include "serial_pl011.h" - -#define IO_WRITE(addr, val) (*(volatile unsigned int *)(addr) = (val)) -#define IO_READ(addr) (*(volatile unsigned int *)(addr)) - -/* Integrator AP has two UARTs, we use the first one, at 38400-8-N-1 */ -#define CONSOLE_PORT CONFIG_CONS_INDEX -#define baudRate CONFIG_BAUDRATE -static volatile unsigned char *const port[] = CONFIG_PL01x_PORTS; -#define NUM_PORTS (sizeof(port)/sizeof(port[0])) - - -static void pl010_putc (int portnum, char c); -static int pl010_getc (int portnum); -static int pl010_tstc (int portnum); - - -int serial_init (void) -{ - unsigned int divisor; - - /* - ** First, disable everything. - */ - IO_WRITE (port[CONSOLE_PORT] + UART_PL010_CR, 0x0); - - /* - ** Set baud rate - ** - */ - switch (baudRate) { - case 9600: - divisor = UART_PL010_BAUD_9600; - break; - - case 19200: - divisor = UART_PL010_BAUD_9600; - break; - - case 38400: - divisor = UART_PL010_BAUD_38400; - break; - - case 57600: - divisor = UART_PL010_BAUD_57600; - break; - - case 115200: - divisor = UART_PL010_BAUD_115200; - break; - - default: - divisor = UART_PL010_BAUD_38400; - } - - IO_WRITE (port[CONSOLE_PORT] + UART_PL010_LCRM, - ((divisor & 0xf00) >> 8)); - IO_WRITE (port[CONSOLE_PORT] + UART_PL010_LCRL, (divisor & 0xff)); - - /* - ** Set the UART to be 8 bits, 1 stop bit, no parity, fifo enabled. - */ - IO_WRITE (port[CONSOLE_PORT] + UART_PL010_LCRH, - (UART_PL010_LCRH_WLEN_8 | UART_PL010_LCRH_FEN)); - - /* - ** Finally, enable the UART - */ - IO_WRITE (port[CONSOLE_PORT] + UART_PL010_CR, (UART_PL010_CR_UARTEN)); - - return (0); -} - -void serial_putc (const char c) -{ - if (c == '\n') - pl010_putc (CONSOLE_PORT, '\r'); - - pl010_putc (CONSOLE_PORT, c); -} - -void serial_puts (const char *s) -{ - while (*s) { - serial_putc (*s++); - } -} - -int serial_getc (void) -{ - return pl010_getc (CONSOLE_PORT); -} - -int serial_tstc (void) -{ - return pl010_tstc (CONSOLE_PORT); -} - -void serial_setbrg (void) -{ -} - -static void pl010_putc (int portnum, char c) -{ - /* Wait until there is space in the FIFO */ - while (IO_READ (port[portnum] + UART_PL01x_FR) & UART_PL01x_FR_TXFF); - - /* Send the character */ - IO_WRITE (port[portnum] + UART_PL01x_DR, c); -} - -static int pl010_getc (int portnum) -{ - unsigned int data; - - /* Wait until there is data in the FIFO */ - while (IO_READ (port[portnum] + UART_PL01x_FR) & UART_PL01x_FR_RXFE); - - data = IO_READ (port[portnum] + UART_PL01x_DR); - - /* Check for an error flag */ - if (data & 0xFFFFFF00) { - /* Clear the error */ - IO_WRITE (port[portnum] + UART_PL01x_ECR, 0xFFFFFFFF); - return -1; - } - - return (int) data; -} - -static int pl010_tstc (int portnum) -{ - return !(IO_READ (port[portnum] + UART_PL01x_FR) & - UART_PL01x_FR_RXFE); -} - -#endif diff --git a/drivers/serial_pl011.c b/drivers/serial_pl011.c deleted file mode 100644 index 4d35fe5e9ed..00000000000 --- a/drivers/serial_pl011.c +++ /dev/null @@ -1,161 +0,0 @@ -/* - * (C) Copyright 2000 - * Rob Taylor, Flying Pig Systems. robt@flyingpig.com. - * - * (C) Copyright 2004 - * ARM Ltd. - * Philippe Robin, - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/* Simple U-Boot driver for the PrimeCell PL011 UARTs on the IntegratorCP */ -/* Should be fairly simple to make it work with the PL010 as well */ - -#include - -#ifdef CFG_PL011_SERIAL - -#include "serial_pl011.h" - -#define IO_WRITE(addr, val) (*(volatile unsigned int *)(addr) = (val)) -#define IO_READ(addr) (*(volatile unsigned int *)(addr)) - -/* - * IntegratorCP has two UARTs, use the first one, at 38400-8-N-1 - * Versatile PB has four UARTs. - */ - -#define CONSOLE_PORT CONFIG_CONS_INDEX -#define baudRate CONFIG_BAUDRATE -static volatile unsigned char *const port[] = CONFIG_PL01x_PORTS; -#define NUM_PORTS (sizeof(port)/sizeof(port[0])) - -static void pl011_putc (int portnum, char c); -static int pl011_getc (int portnum); -static int pl011_tstc (int portnum); - - -int serial_init (void) -{ - unsigned int temp; - unsigned int divider; - unsigned int remainder; - unsigned int fraction; - - /* - ** First, disable everything. - */ - IO_WRITE (port[CONSOLE_PORT] + UART_PL011_CR, 0x0); - - /* - ** Set baud rate - ** - ** IBRD = UART_CLK / (16 * BAUD_RATE) - ** FBRD = ROUND((64 * MOD(UART_CLK,(16 * BAUD_RATE))) / (16 * BAUD_RATE)) - */ - temp = 16 * baudRate; - divider = CONFIG_PL011_CLOCK / temp; - remainder = CONFIG_PL011_CLOCK % temp; - temp = (8 * remainder) / baudRate; - fraction = (temp >> 1) + (temp & 1); - - IO_WRITE (port[CONSOLE_PORT] + UART_PL011_IBRD, divider); - IO_WRITE (port[CONSOLE_PORT] + UART_PL011_FBRD, fraction); - - /* - ** Set the UART to be 8 bits, 1 stop bit, no parity, fifo enabled. - */ - IO_WRITE (port[CONSOLE_PORT] + UART_PL011_LCRH, - (UART_PL011_LCRH_WLEN_8 | UART_PL011_LCRH_FEN)); - - /* - ** Finally, enable the UART - */ - IO_WRITE (port[CONSOLE_PORT] + UART_PL011_CR, - (UART_PL011_CR_UARTEN | UART_PL011_CR_TXE | - UART_PL011_CR_RXE)); - - return 0; -} - -void serial_putc (const char c) -{ - if (c == '\n') - pl011_putc (CONSOLE_PORT, '\r'); - - pl011_putc (CONSOLE_PORT, c); -} - -void serial_puts (const char *s) -{ - while (*s) { - serial_putc (*s++); - } -} - -int serial_getc (void) -{ - return pl011_getc (CONSOLE_PORT); -} - -int serial_tstc (void) -{ - return pl011_tstc (CONSOLE_PORT); -} - -void serial_setbrg (void) -{ -} - -static void pl011_putc (int portnum, char c) -{ - /* Wait until there is space in the FIFO */ - while (IO_READ (port[portnum] + UART_PL01x_FR) & UART_PL01x_FR_TXFF); - - /* Send the character */ - IO_WRITE (port[portnum] + UART_PL01x_DR, c); -} - -static int pl011_getc (int portnum) -{ - unsigned int data; - - /* Wait until there is data in the FIFO */ - while (IO_READ (port[portnum] + UART_PL01x_FR) & UART_PL01x_FR_RXFE); - - data = IO_READ (port[portnum] + UART_PL01x_DR); - - /* Check for an error flag */ - if (data & 0xFFFFFF00) { - /* Clear the error */ - IO_WRITE (port[portnum] + UART_PL01x_ECR, 0xFFFFFFFF); - return -1; - } - - return (int) data; -} - -static int pl011_tstc (int portnum) -{ - return !(IO_READ (port[portnum] + UART_PL01x_FR) & - UART_PL01x_FR_RXFE); -} - -#endif diff --git a/drivers/serial_pl011.h b/drivers/serial_pl011.h deleted file mode 100644 index 5f20fdd108a..00000000000 --- a/drivers/serial_pl011.h +++ /dev/null @@ -1,137 +0,0 @@ -/* - * (C) Copyright 2003, 2004 - * ARM Ltd. - * Philippe Robin, - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/* - * ARM PrimeCell UART's (PL010 & PL011) - * ------------------------------------ - * - * Definitions common to both PL010 & PL011 - * - */ -#define UART_PL01x_DR 0x00 /* Data read or written from the interface. */ -#define UART_PL01x_RSR 0x04 /* Receive status register (Read). */ -#define UART_PL01x_ECR 0x04 /* Error clear register (Write). */ -#define UART_PL01x_FR 0x18 /* Flag register (Read only). */ - -#define UART_PL01x_RSR_OE 0x08 -#define UART_PL01x_RSR_BE 0x04 -#define UART_PL01x_RSR_PE 0x02 -#define UART_PL01x_RSR_FE 0x01 - -#define UART_PL01x_FR_TXFE 0x80 -#define UART_PL01x_FR_RXFF 0x40 -#define UART_PL01x_FR_TXFF 0x20 -#define UART_PL01x_FR_RXFE 0x10 -#define UART_PL01x_FR_BUSY 0x08 -#define UART_PL01x_FR_TMSK (UART_PL01x_FR_TXFF + UART_PL01x_FR_BUSY) - -/* - * PL010 definitions - * - */ -#define UART_PL010_LCRH 0x08 /* Line control register, high byte. */ -#define UART_PL010_LCRM 0x0C /* Line control register, middle byte. */ -#define UART_PL010_LCRL 0x10 /* Line control register, low byte. */ -#define UART_PL010_CR 0x14 /* Control register. */ -#define UART_PL010_IIR 0x1C /* Interrupt indentification register (Read). */ -#define UART_PL010_ICR 0x1C /* Interrupt clear register (Write). */ -#define UART_PL010_ILPR 0x20 /* IrDA low power counter register. */ - -#define UART_PL010_CR_LPE (1 << 7) -#define UART_PL010_CR_RTIE (1 << 6) -#define UART_PL010_CR_TIE (1 << 5) -#define UART_PL010_CR_RIE (1 << 4) -#define UART_PL010_CR_MSIE (1 << 3) -#define UART_PL010_CR_IIRLP (1 << 2) -#define UART_PL010_CR_SIREN (1 << 1) -#define UART_PL010_CR_UARTEN (1 << 0) - -#define UART_PL010_LCRH_WLEN_8 (3 << 5) -#define UART_PL010_LCRH_WLEN_7 (2 << 5) -#define UART_PL010_LCRH_WLEN_6 (1 << 5) -#define UART_PL010_LCRH_WLEN_5 (0 << 5) -#define UART_PL010_LCRH_FEN (1 << 4) -#define UART_PL010_LCRH_STP2 (1 << 3) -#define UART_PL010_LCRH_EPS (1 << 2) -#define UART_PL010_LCRH_PEN (1 << 1) -#define UART_PL010_LCRH_BRK (1 << 0) - - -#define UART_PL010_BAUD_460800 1 -#define UART_PL010_BAUD_230400 3 -#define UART_PL010_BAUD_115200 7 -#define UART_PL010_BAUD_57600 15 -#define UART_PL010_BAUD_38400 23 -#define UART_PL010_BAUD_19200 47 -#define UART_PL010_BAUD_14400 63 -#define UART_PL010_BAUD_9600 95 -#define UART_PL010_BAUD_4800 191 -#define UART_PL010_BAUD_2400 383 -#define UART_PL010_BAUD_1200 767 -/* - * PL011 definitions - * - */ -#define UART_PL011_IBRD 0x24 -#define UART_PL011_FBRD 0x28 -#define UART_PL011_LCRH 0x2C -#define UART_PL011_CR 0x30 -#define UART_PL011_IMSC 0x38 -#define UART_PL011_PERIPH_ID0 0xFE0 - -#define UART_PL011_LCRH_SPS (1 << 7) -#define UART_PL011_LCRH_WLEN_8 (3 << 5) -#define UART_PL011_LCRH_WLEN_7 (2 << 5) -#define UART_PL011_LCRH_WLEN_6 (1 << 5) -#define UART_PL011_LCRH_WLEN_5 (0 << 5) -#define UART_PL011_LCRH_FEN (1 << 4) -#define UART_PL011_LCRH_STP2 (1 << 3) -#define UART_PL011_LCRH_EPS (1 << 2) -#define UART_PL011_LCRH_PEN (1 << 1) -#define UART_PL011_LCRH_BRK (1 << 0) - -#define UART_PL011_CR_CTSEN (1 << 15) -#define UART_PL011_CR_RTSEN (1 << 14) -#define UART_PL011_CR_OUT2 (1 << 13) -#define UART_PL011_CR_OUT1 (1 << 12) -#define UART_PL011_CR_RTS (1 << 11) -#define UART_PL011_CR_DTR (1 << 10) -#define UART_PL011_CR_RXE (1 << 9) -#define UART_PL011_CR_TXE (1 << 8) -#define UART_PL011_CR_LPE (1 << 7) -#define UART_PL011_CR_IIRLP (1 << 2) -#define UART_PL011_CR_SIREN (1 << 1) -#define UART_PL011_CR_UARTEN (1 << 0) - -#define UART_PL011_IMSC_OEIM (1 << 10) -#define UART_PL011_IMSC_BEIM (1 << 9) -#define UART_PL011_IMSC_PEIM (1 << 8) -#define UART_PL011_IMSC_FEIM (1 << 7) -#define UART_PL011_IMSC_RTIM (1 << 6) -#define UART_PL011_IMSC_TXIM (1 << 5) -#define UART_PL011_IMSC_RXIM (1 << 4) -#define UART_PL011_IMSC_DSRMIM (1 << 3) -#define UART_PL011_IMSC_DCDMIM (1 << 2) -#define UART_PL011_IMSC_CTSMIM (1 << 1) -#define UART_PL011_IMSC_RIMIM (1 << 0) -- cgit v1.2.3 From eff501904df2bf1724a750062628ba2c51dbb1f8 Mon Sep 17 00:00:00 2001 From: Bartlomiej Sieka Date: Tue, 23 Oct 2007 11:36:07 +0200 Subject: Motion-PRO: Add setting of SDelay reg. to SDRAM controller configuration. Per AN3221 (MPC5200B SDRAM Initialization and Configuration), the SDelay register must be written a value of 0x00000004 as the first step of the SDRAM contorller configuration. Signed-off-by: Bartlomiej Sieka --- board/motionpro/motionpro.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/board/motionpro/motionpro.c b/board/motionpro/motionpro.c index f83998e5aa0..68257b861d5 100644 --- a/board/motionpro/motionpro.c +++ b/board/motionpro/motionpro.c @@ -138,6 +138,12 @@ long int initdram(int board_type) #ifndef CFG_RAMBOOT ulong test1, test2; + /* According to AN3221 (MPC5200B SDRAM Initialization and + * Configuration), the SDelay register must be written a value of + * 0x00000004 as the first step of the SDRAM contorller configuration. + */ + *(vu_long *)MPC5XXX_SDRAM_SDELAY = 0x04; + /* configure SDRAM start/end for detection */ *(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0x0000001e; /* 2G at 0x0 */ *(vu_long *)MPC5XXX_SDRAM_CS1CFG = 0x80000000; /* disabled */ -- cgit v1.2.3 From d3afa1ee19345a31fd1eaad3e98b97d13ca47315 Mon Sep 17 00:00:00 2001 From: Bartlomiej Sieka Date: Tue, 23 Oct 2007 13:14:10 +0200 Subject: Motion-PRO: Update configuration to accomodate next generation board. New board has faster oscillator and a different Flash chip. This affects: - CFG_MPC5XXX_CLKIN - SDRAM timings - Flash CS configuration (timings) - Flash sector size, and thus MTD partition layout - malloc() arena size (due to bigger Flash sectors) - smaller memory test range (due to bigger malloc() arena) This patch also enables more extensive memory testing via "mtest". Signed-off-by: Bartlomiej Sieka --- include/configs/motionpro.h | 29 +++++++++++++++-------------- 1 file changed, 15 insertions(+), 14 deletions(-) diff --git a/include/configs/motionpro.h b/include/configs/motionpro.h index 9a216321628..1503598166c 100644 --- a/include/configs/motionpro.h +++ b/include/configs/motionpro.h @@ -163,9 +163,9 @@ /* - * Clock configuration: SYS_XTALIN = 25MHz + * Clock configuration: SYS_XTALIN = 33MHz */ -#define CFG_MPC5XXX_CLKIN 25000000 +#define CFG_MPC5XXX_CLKIN 33000000 /* @@ -211,7 +211,7 @@ #endif #define CFG_MONITOR_LEN (256 << 10) /* 256 kB for Monitor */ -#define CFG_MALLOC_LEN (128 << 10) /* 128 kB for malloc() */ +#define CFG_MALLOC_LEN (1024 << 10) /* 1 MiB for malloc() */ #define CFG_BOOTMAPSZ (8 << 20) /* initial mem map for Linux */ @@ -221,7 +221,7 @@ /* Boot Chipselect */ #define CFG_BOOTCS_START CFG_FLASH_BASE #define CFG_BOOTCS_SIZE CFG_FLASH_SIZE -#define CFG_BOOTCS_CFG 0x03035D00 +#define CFG_BOOTCS_CFG 0x00045D00 /* Flash memory addressing */ #define CFG_CS0_START CFG_FLASH_BASE @@ -251,11 +251,11 @@ /* * SDRAM configuration */ -/* 2 x MT48LC16M16A2BG-75 IT:D, CASL 2, 32 bit data bus */ -#define SDRAM_CONFIG1 0x52222600 -#define SDRAM_CONFIG2 0x88b70000 -#define SDRAM_CONTROL 0x50570000 -#define SDRAM_MODE 0x008d0000 +/* 2 x MT48LC16M16A2BG-75 IT:D, CASL 3, 32 bit data bus */ +#define SDRAM_CONFIG1 0x62322900 +#define SDRAM_CONFIG2 0x88c70000 +#define SDRAM_CONTROL 0x504f0000 +#define SDRAM_MODE 0x00cd0000 /* @@ -267,7 +267,7 @@ #define CFG_FLASH_SIZE 0x01000000 #define CFG_MAX_FLASH_BANKS 1 /* max num of memory banks */ #define CFG_FLASH_BANKS_LIST { CFG_FLASH_BASE } -#define CFG_MAX_FLASH_SECT 256 /* max num of sects on one chip */ +#define CFG_MAX_FLASH_SECT 128 /* max num of sects on one chip */ #define CONFIG_FLASH_16BIT /* Flash is 16-bit */ /* @@ -277,8 +277,8 @@ #define MTDIDS_DEFAULT "nor0=motionpro-0" #define MTDPARTS_DEFAULT "mtdparts=motionpro-0:" \ "13m(fs),2m(kernel),256k(uboot)," \ - "64k(env),64k(redund_env),64k(dtb)," \ - "-(user_data)" + "128k(env),128k(redund_env)," \ + "128k(dtb),-(user_data)" /* * IDE/ATA configuration @@ -356,7 +356,7 @@ extern void __led_set(led_id_t id, int state); /* This has to be a multiple of the Flash sector size */ #define CFG_ENV_ADDR (CFG_MONITOR_BASE + CFG_MONITOR_LEN) #define CFG_ENV_SIZE 0x1000 -#define CFG_ENV_SECT_SIZE 0x10000 +#define CFG_ENV_SECT_SIZE 0x20000 /* Configuration of redundant environment */ #define CFG_ENV_ADDR_REDUND (CFG_ENV_ADDR + CFG_ENV_SECT_SIZE) @@ -394,7 +394,8 @@ extern void __led_set(led_id_t id, int state); #define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ #define CFG_MEMTEST_START 0x00100000 /* memtest works on */ -#define CFG_MEMTEST_END 0x03f00000 /* 1 ... 64 MiB in DRAM */ +#define CFG_MEMTEST_END 0x03e00000 /* 1 ... 62 MiB in DRAM */ +#define CFG_ALT_MEMTEST #define CFG_LOAD_ADDR 0x200000 /* default kernel load addr */ -- cgit v1.2.3 From 298cd4cafe81ff8a6c87be8fbc440a20720d3ed6 Mon Sep 17 00:00:00 2001 From: Rune Torgersen Date: Wed, 17 Oct 2007 11:56:31 -0500 Subject: Make MPC8266ADS command selection more robust Fix MPC8266 command line definition so it won't break when new commands are added to u-boot. Signed-off-by Rune Torgersen --- include/configs/MPC8266ADS.h | 53 +++++++++++++++++--------------------------- 1 file changed, 20 insertions(+), 33 deletions(-) diff --git a/include/configs/MPC8266ADS.h b/include/configs/MPC8266ADS.h index d392b981edd..3659002d5e8 100644 --- a/include/configs/MPC8266ADS.h +++ b/include/configs/MPC8266ADS.h @@ -146,39 +146,26 @@ /* * Command line configuration. */ -#include - -#undef CONFIG_CMD_BEDBUG -#undef CONFIG_CMD_BMP -#undef CONFIG_CMD_BSP -#undef CONFIG_CMD_DATE -#undef CONFIG_CMD_DHCP -#undef CONFIG_CMD_DISPLAY -#undef CONFIG_CMD_DOC -#undef CONFIG_CMD_DTT -#undef CONFIG_CMD_EEPROM -#undef CONFIG_CMD_ELF -#undef CONFIG_CMD_EXT2 -#undef CONFIG_CMD_FDC -#undef CONFIG_CMD_FDOS -#undef CONFIG_CMD_HWFLOW -#undef CONFIG_CMD_IDE -#undef CONFIG_CMD_JFFS2 -#undef CONFIG_CMD_KGDB -#undef CONFIG_CMD_MFSL -#undef CONFIG_CMD_MMC -#undef CONFIG_CMD_NAND -#undef CONFIG_CMD_ONENAND -#undef CONFIG_CMD_PCMCIA -#undef CONFIG_CMD_REISER -#undef CONFIG_CMD_SCSI -#undef CONFIG_CMD_SPI -#undef CONFIG_CMD_SNTP -#undef CONFIG_CMD_VFD -#undef CONFIG_CMD_UNIVERSE -#undef CONFIG_CMD_USB -#undef CONFIG_CMD_XIMG -#undef CONFIG_CMD_AT91_SPIMUX +#include + +/* Commands we want, that are not part of default set */ +#define CONFIG_CMD_ASKENV /* ask for env variable */ +#define CONFIG_CMD_CACHE /* icache, dcache */ +#define CONFIG_CMD_DHCP /* DHCP Support */ +#define CONFIG_CMD_DIAG /* Diagnostics */ +#define CONFIG_CMD_IMMAP /* IMMR dump support */ +#define CONFIG_CMD_IRQ /* irqinfo */ +#define CONFIG_CMD_MII /* MII support */ +#define CONFIG_CMD_PCI /* pciinfo */ +#define CONFIG_CMD_PING /* ping support */ +#define CONFIG_CMD_PORTIO /* Port I/O */ +#define CONFIG_CMD_REGINFO /* Register dump */ +#define CONFIG_CMD_SAVES /* save S record dump */ +#define CONFIG_CMD_SDRAM /* SDRAM DIMM SPD info printout */ + +/* Commands from default set we don't need */ +#undef CONFIG_CMD_FPGA /* FPGA configuration Support */ +#undef CONFIG_CMD_SETGETDCR /* DCR support on 4xx */ /* Define a command string that is automatically executed when no character * is read on the console interface withing "Boot Delay" after reset. -- cgit v1.2.3 From 2a4741d9a14ec475f50e9856d2c0a67e8b4271bd Mon Sep 17 00:00:00 2001 From: Marcel Ziswiler Date: Fri, 19 Oct 2007 00:25:33 +0200 Subject: fix pxa255_idp board The pxa255_idp being an old unmaintained board showed several issues: 1. CONFIG_INIT_CRITICAL was still defined. 2. Neither CONFIG_MAC_PARTITION nor CONFIG_DOS_PARTITION was defined. 3. Symbol flash_addr was undeclared. 4. The boards lowlevel_init function was still called memsetup. 5. The TEXT_BASE was still 0xa3000000 rather than 0xa3080000. 6. Using -march=armv5 instead of -march=armv5te resulted in lots of 'target CPU does not support interworking' warnings on recent compilers. 7. The PXA's serial driver redefined FFUART, BTUART and STUART used as indexes rather than the register definitions from the pxa-regs header file. Renamed them to FFUART_INDEX, BTUART_INDEX and STUART_INDEX to avoid any ambiguities. 8. There were several redefinition warnings concerning ICMR, OSMR3, OSCR, OWER, OIER, RCSR and CCCR in the PXA's assembly start file. 9. The board configuration file was rather outdated. 10. The part header file defined the vendor, product and revision arrays as unsigned chars instead of just chars in the block_dev_desc_t structure. Signed-off-by: Marcel Ziswiler --- board/pxa255_idp/Makefile | 2 +- board/pxa255_idp/config.mk | 2 +- board/pxa255_idp/lowlevel_init.S | 496 +++++++++++++++++++++++++++++++++++++++ board/pxa255_idp/memsetup.S | 496 --------------------------------------- board/pxa255_idp/u-boot.lds | 1 + cpu/pxa/config.mk | 3 +- cpu/pxa/serial.c | 72 +++--- cpu/pxa/start.S | 6 +- include/configs/pxa255_idp.h | 13 +- include/part.h | 6 +- 10 files changed, 551 insertions(+), 546 deletions(-) create mode 100644 board/pxa255_idp/lowlevel_init.S delete mode 100644 board/pxa255_idp/memsetup.S diff --git a/board/pxa255_idp/Makefile b/board/pxa255_idp/Makefile index a957dd39615..32399f0e940 100644 --- a/board/pxa255_idp/Makefile +++ b/board/pxa255_idp/Makefile @@ -27,7 +27,7 @@ include $(TOPDIR)/config.mk LIB = $(obj)lib$(BOARD).a COBJS := pxa_idp.o -SOBJS := memsetup.o +SOBJS := lowlevel_init.o SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) OBJS := $(addprefix $(obj),$(COBJS)) diff --git a/board/pxa255_idp/config.mk b/board/pxa255_idp/config.mk index d2a2040e689..55c8b270a11 100644 --- a/board/pxa255_idp/config.mk +++ b/board/pxa255_idp/config.mk @@ -1,3 +1,3 @@ #TEXT_BASE = 0xa1700000 -TEXT_BASE = 0xa3000000 +TEXT_BASE = 0xa3080000 #TEXT_BASE = 0 diff --git a/board/pxa255_idp/lowlevel_init.S b/board/pxa255_idp/lowlevel_init.S new file mode 100644 index 00000000000..aaa4d8eb93b --- /dev/null +++ b/board/pxa255_idp/lowlevel_init.S @@ -0,0 +1,496 @@ +/* + * Most of this taken from Redboot hal_platform_setup.h with cleanup + * + * NOTE: I haven't clean this up considerably, just enough to get it + * running. See hal_platform_setup.h for the source. See + * board/cradle/lowlevel_init.S for another PXA250 setup that is + * much cleaner. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include + +DRAM_SIZE: .long CFG_DRAM_SIZE + +/* wait for coprocessor write complete */ + .macro CPWAIT reg + mrc p15,0,\reg,c2,c0,0 + mov \reg,\reg + sub pc,pc,#4 + .endm + +/* + * Memory setup + */ +.globl lowlevel_init +lowlevel_init: + + mov r10, lr + +#ifdef DEBUG_BLINK_ENABLE + /* 3rd blink */ + bl blink +#endif + + /* Set up GPIO pins first ----------------------------------------- */ + ldr r0, =GPSR0 + ldr r1, =CFG_GPSR0_VAL + str r1, [r0] + + ldr r0, =GPSR1 + ldr r1, =CFG_GPSR1_VAL + str r1, [r0] + + ldr r0, =GPSR2 + ldr r1, =CFG_GPSR2_VAL + str r1, [r0] + + ldr r0, =GPCR0 + ldr r1, =CFG_GPCR0_VAL + str r1, [r0] + + ldr r0, =GPCR1 + ldr r1, =CFG_GPCR1_VAL + str r1, [r0] + + ldr r0, =GPCR2 + ldr r1, =CFG_GPCR2_VAL + str r1, [r0] + + ldr r0, =GPDR0 + ldr r1, =CFG_GPDR0_VAL + str r1, [r0] + + ldr r0, =GPDR1 + ldr r1, =CFG_GPDR1_VAL + str r1, [r0] + + ldr r0, =GPDR2 + ldr r1, =CFG_GPDR2_VAL + str r1, [r0] + + ldr r0, =GAFR0_L + ldr r1, =CFG_GAFR0_L_VAL + str r1, [r0] + + ldr r0, =GAFR0_U + ldr r1, =CFG_GAFR0_U_VAL + str r1, [r0] + + ldr r0, =GAFR1_L + ldr r1, =CFG_GAFR1_L_VAL + str r1, [r0] + + ldr r0, =GAFR1_U + ldr r1, =CFG_GAFR1_U_VAL + str r1, [r0] + + ldr r0, =GAFR2_L + ldr r1, =CFG_GAFR2_L_VAL + str r1, [r0] + + ldr r0, =GAFR2_U + ldr r1, =CFG_GAFR2_U_VAL + str r1, [r0] + + ldr r0, =PSSR /* enable GPIO pins */ + ldr r1, =CFG_PSSR_VAL + str r1, [r0] + +#ifdef DEBUG_BLINK_ENABLE + /* 4th debug blink */ + bl blink +#endif + + /* ---------------------------------------------------------------- */ + /* Enable memory interface */ + /* */ + /* The sequence below is based on the recommended init steps */ + /* detailed in the Intel PXA250 Operating Systems Developers Guide, */ + /* Chapter 10. */ + /* ---------------------------------------------------------------- */ + + /* ---------------------------------------------------------------- */ + /* Step 1: Wait for at least 200 microsedonds to allow internal */ + /* clocks to settle. Only necessary after hard reset... */ + /* FIXME: can be optimized later */ + /* ---------------------------------------------------------------- */ + + ldr r3, =OSCR /* reset the OS Timer Count to zero */ + mov r2, #0 + str r2, [r3] + ldr r4, =0x300 /* really 0x2E1 is about 200usec, */ + /* so 0x300 should be plenty */ +1: + ldr r2, [r3] + cmp r4, r2 + bgt 1b + +mem_init: + + ldr r1, =MEMC_BASE /* get memory controller base addr. */ + + /* ---------------------------------------------------------------- */ + /* Step 2a: Initialize Asynchronous static memory controller */ + /* ---------------------------------------------------------------- */ + + /* MSC registers: timing, bus width, mem type */ + + /* MSC0: nCS(0,1) */ + ldr r2, =CFG_MSC0_VAL + str r2, [r1, #MSC0_OFFSET] + ldr r2, [r1, #MSC0_OFFSET] /* read back to ensure */ + /* that data latches */ + /* MSC1: nCS(2,3) */ + ldr r2, =CFG_MSC1_VAL + str r2, [r1, #MSC1_OFFSET] + ldr r2, [r1, #MSC1_OFFSET] + + /* MSC2: nCS(4,5) */ + ldr r2, =CFG_MSC2_VAL + str r2, [r1, #MSC2_OFFSET] + ldr r2, [r1, #MSC2_OFFSET] + + /* ---------------------------------------------------------------- */ + /* Step 2b: Initialize Card Interface */ + /* ---------------------------------------------------------------- */ + + /* MECR: Memory Expansion Card Register */ + ldr r2, =CFG_MECR_VAL + str r2, [r1, #MECR_OFFSET] + ldr r2, [r1, #MECR_OFFSET] + + /* MCMEM0: Card Interface slot 0 timing */ + ldr r2, =CFG_MCMEM0_VAL + str r2, [r1, #MCMEM0_OFFSET] + ldr r2, [r1, #MCMEM0_OFFSET] + + /* MCMEM1: Card Interface slot 1 timing */ + ldr r2, =CFG_MCMEM1_VAL + str r2, [r1, #MCMEM1_OFFSET] + ldr r2, [r1, #MCMEM1_OFFSET] + + /* MCATT0: Card Interface Attribute Space Timing, slot 0 */ + ldr r2, =CFG_MCATT0_VAL + str r2, [r1, #MCATT0_OFFSET] + ldr r2, [r1, #MCATT0_OFFSET] + + /* MCATT1: Card Interface Attribute Space Timing, slot 1 */ + ldr r2, =CFG_MCATT1_VAL + str r2, [r1, #MCATT1_OFFSET] + ldr r2, [r1, #MCATT1_OFFSET] + + /* MCIO0: Card Interface I/O Space Timing, slot 0 */ + ldr r2, =CFG_MCIO0_VAL + str r2, [r1, #MCIO0_OFFSET] + ldr r2, [r1, #MCIO0_OFFSET] + + /* MCIO1: Card Interface I/O Space Timing, slot 1 */ + ldr r2, =CFG_MCIO1_VAL + str r2, [r1, #MCIO1_OFFSET] + ldr r2, [r1, #MCIO1_OFFSET] + +#ifdef DEBUG_BLINK_ENABLE + /* 5th blink */ + bl blink +#endif + + /* ---------------------------------------------------------------- */ + /* Step 2c: Write FLYCNFG FIXME: what's that??? */ + /* ---------------------------------------------------------------- */ + + /* ---------------------------------------------------------------- */ + /* Step 2d: Initialize Timing for Sync Memory (SDCLK0) */ + /* ---------------------------------------------------------------- */ + + /* Before accessing MDREFR we need a valid DRI field, so we set */ + /* this to power on defaults + DRI field. */ + + ldr r3, =CFG_MDREFR_VAL + ldr r2, =0xFFF + and r3, r3, r2 + ldr r4, =0x03ca4000 + orr r4, r4, r3 + str r4, [r1, #MDREFR_OFFSET] /* write back MDREFR */ + ldr r4, [r1, #MDREFR_OFFSET] + + /* Note: preserve the mdrefr value in r4 */ + + /* ---------------------------------------------------------------- */ + /* Step 3: Initialize Synchronous Static Memory (Flash/Peripherals) */ + /* ---------------------------------------------------------------- */ + + /* Initialize SXCNFG register. Assert the enable bits */ + + /* Write SXMRS to cause an MRS command to all enabled banks of */ + /* synchronous static memory. Note that SXLCR need not be written */ + /* at this time. */ + + /* FIXME: we use async mode for now */ + + /* ---------------------------------------------------------------- */ + /* Step 4: Initialize SDRAM */ + /* ---------------------------------------------------------------- */ + + /* set MDREFR according to user define with exception of a few bits */ + + ldr r4, =CFG_MDREFR_VAL + orr r4, r4, #(MDREFR_SLFRSH) + bic r4, r4, #(MDREFR_E1PIN|MDREFR_E0PIN) + str r4, [r1, #MDREFR_OFFSET] /* write back MDREFR */ + ldr r4, [r1, #MDREFR_OFFSET] + + /* Step 4b: de-assert MDREFR:SLFRSH. */ + + bic r4, r4, #(MDREFR_SLFRSH) + str r4, [r1, #MDREFR_OFFSET] /* write back MDREFR */ + ldr r4, [r1, #MDREFR_OFFSET] + + /* Step 4c: assert MDREFR:E1PIN and E0PIO as desired */ + + ldr r4, =CFG_MDREFR_VAL + str r4, [r1, #MDREFR_OFFSET] /* write back MDREFR */ + ldr r4, [r1, #MDREFR_OFFSET] + + + /* Step 4d: write MDCNFG with MDCNFG:DEx deasserted (set to 0), to */ + /* configure but not enable each SDRAM partition pair. */ + + ldr r4, =CFG_MDCNFG_VAL + bic r4, r4, #(MDCNFG_DE0|MDCNFG_DE1) + + str r4, [r1, #MDCNFG_OFFSET] /* write back MDCNFG */ + ldr r4, [r1, #MDCNFG_OFFSET] + + /* Step 4e: Wait for the clock to the SDRAMs to stabilize, */ + /* 100..200 µsec. */ + + ldr r3, =OSCR /* reset the OS Timer Count to zero */ + mov r2, #0 + str r2, [r3] + ldr r4, =0x300 /* really 0x2E1 is about 200usec, */ + /* so 0x300 should be plenty */ +1: + ldr r2, [r3] + cmp r4, r2 + bgt 1b + + /* Step 4f: Trigger a number (usually 8) refresh cycles by */ + /* attempting non-burst read or write accesses to disabled */ + /* SDRAM, as commonly specified in the power up sequence */ + /* documented in SDRAM data sheets. The address(es) used */ + /* for this purpose must not be cacheable. */ + + ldr r3, =CFG_DRAM_BASE + str r2, [r3] + str r2, [r3] + str r2, [r3] + str r2, [r3] + str r2, [r3] + str r2, [r3] + str r2, [r3] + str r2, [r3] + + /* Step 4g: Write MDCNFG with enable bits asserted */ + /* (MDCNFG:DEx set to 1). */ + + ldr r3, [r1, #MDCNFG_OFFSET] + orr r3, r3, #(MDCNFG_DE0|MDCNFG_DE1) + str r3, [r1, #MDCNFG_OFFSET] + + /* Step 4h: Write MDMRS. */ + + ldr r2, =CFG_MDMRS_VAL + str r2, [r1, #MDMRS_OFFSET] + + /* We are finished with Intel's memory controller initialisation */ +#if 0 + /* FIXME turn on serial ports */ + /* look into moving this to board_init() */ + ldr r2, =(PXA_CS5_PHYS + 0x03C0002c) + mov r3, #0x13 + str r3, [r2] +#endif + +#ifdef DEBUG_BLINK_ENABLE + /* 6th blink */ + bl blink +#endif + + /* ---------------------------------------------------------------- */ + /* Disable (mask) all interrupts at interrupt controller */ + /* ---------------------------------------------------------------- */ + +initirqs: + + mov r1, #0 /* clear int. level register (IRQ, not FIQ) */ + ldr r2, =ICLR + str r1, [r2] + + ldr r2, =ICMR /* mask all interrupts at the controller */ + str r1, [r2] + + /* ---------------------------------------------------------------- */ + /* Clock initialisation */ + /* ---------------------------------------------------------------- */ + +initclks: + + /* Disable the peripheral clocks, and set the core clock frequency */ + /* (hard-coding at 398.12MHz for now). */ + + /* Turn Off ALL on-chip peripheral clocks for re-configuration */ + /* Note: See label 'ENABLECLKS' for the re-enabling */ +#if 0 + ldr r1, =CKEN + mov r2, #0 + str r2, [r1] + + /* default value in case no valid rotary switch setting is found */ + ldr r2, =(CCCR_L27|CCCR_M2|CCCR_N10) /* DEFAULT: {200/200/100} */ + + /* ... and write the core clock config register */ + ldr r1, =CCCR + str r2, [r1] + +#endif + +#ifdef RTC + /* enable the 32Khz oscillator for RTC and PowerManager */ + + ldr r1, =OSCC + mov r2, #OSCC_OON + str r2, [r1] + + /* NOTE: spin here until OSCC.OOK get set, meaning the PLL */ + /* has settled. */ +60: + ldr r2, [r1] + ands r2, r2, #1 + beq 60b +#endif + + /* ---------------------------------------------------------------- */ + /* */ + /* ---------------------------------------------------------------- */ + + /* Save SDRAM size */ + ldr r1, =DRAM_SIZE + str r8, [r1] + + /* Interrupt init: Mask all interrupts */ + ldr r0, =ICMR /* enable no sources */ + mov r1, #0 + str r1, [r0] + + /* FIXME */ + +#define NODEBUG +#ifdef NODEBUG + /*Disable software and data breakpoints */ + mov r0,#0 + mcr p15,0,r0,c14,c8,0 /* ibcr0 */ + mcr p15,0,r0,c14,c9,0 /* ibcr1 */ + mcr p15,0,r0,c14,c4,0 /* dbcon */ + + /*Enable all debug functionality */ + mov r0,#0x80000000 + mcr p14,0,r0,c10,c0,0 /* dcsr */ +#endif + + /* ---------------------------------------------------------------- */ + /* End memsetup */ + /* ---------------------------------------------------------------- */ + +#ifdef DEBUG_BLINK_ENABLE + /* 7th blink */ + bl blink +#endif + +endlowlevel_init: + + mov pc, r10 + + +#ifdef DEBUG_BLINK_ENABLE + +/* debug LED code */ + +/* delay about 200ms */ +delay: + + /* reset OSCR to 0 */ + ldr r8, =OSCR + mov r9, #0 + str r9, [r8] + + /* make sure new value has stuck */ +1: + ldr r8, =OSCR + ldr r9, [r8] + mov r8, #0x10000 + cmp r9, r8 + bgt 1b + + /* now, wait for delay to expire */ +1: + ldr r8, =OSCR + ldr r9, [r8] + mov r8, #0xd4000 + cmp r8, r9 + bgt 1b + + mov pc, lr + +/* blink code -- trashes r7, r8, r9 */ + +.globl blink +blink: + + mov r7, lr + + /* set GPIO10 as outout */ + ldr r8, =GPDR0 + ldr r9, [r8] + orr r9, r9, #(1<<10) + str r9, [r8] + + /* turn LED off */ + mov r9, #(1<<10) + ldr r8, =GPCR0 + str r9, [r8] + bl delay + + /* turn LED on */ + mov r9, #(1<<10) + ldr r8, =GPSR0 + str r9, [r8] + bl delay + + /* turn LED off */ + mov r9, #(1<<10) + ldr r8, =GPCR0 + str r9, [r8] + + mov pc, r7 + +#endif diff --git a/board/pxa255_idp/memsetup.S b/board/pxa255_idp/memsetup.S deleted file mode 100644 index 7e485a28a61..00000000000 --- a/board/pxa255_idp/memsetup.S +++ /dev/null @@ -1,496 +0,0 @@ -/* - * Most of this taken from Redboot hal_platform_setup.h with cleanup - * - * NOTE: I haven't clean this up considerably, just enough to get it - * running. See hal_platform_setup.h for the source. See - * board/cradle/memsetup.S for another PXA250 setup that is - * much cleaner. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include -#include - -DRAM_SIZE: .long CFG_DRAM_SIZE - -/* wait for coprocessor write complete */ - .macro CPWAIT reg - mrc p15,0,\reg,c2,c0,0 - mov \reg,\reg - sub pc,pc,#4 - .endm - -/* - * Memory setup - */ -.globl memsetup -memsetup: - - mov r10, lr - -#ifdef DEBUG_BLINK_ENABLE - /* 3rd blink */ - bl blink -#endif - - /* Set up GPIO pins first ----------------------------------------- */ - ldr r0, =GPSR0 - ldr r1, =CFG_GPSR0_VAL - str r1, [r0] - - ldr r0, =GPSR1 - ldr r1, =CFG_GPSR1_VAL - str r1, [r0] - - ldr r0, =GPSR2 - ldr r1, =CFG_GPSR2_VAL - str r1, [r0] - - ldr r0, =GPCR0 - ldr r1, =CFG_GPCR0_VAL - str r1, [r0] - - ldr r0, =GPCR1 - ldr r1, =CFG_GPCR1_VAL - str r1, [r0] - - ldr r0, =GPCR2 - ldr r1, =CFG_GPCR2_VAL - str r1, [r0] - - ldr r0, =GPDR0 - ldr r1, =CFG_GPDR0_VAL - str r1, [r0] - - ldr r0, =GPDR1 - ldr r1, =CFG_GPDR1_VAL - str r1, [r0] - - ldr r0, =GPDR2 - ldr r1, =CFG_GPDR2_VAL - str r1, [r0] - - ldr r0, =GAFR0_L - ldr r1, =CFG_GAFR0_L_VAL - str r1, [r0] - - ldr r0, =GAFR0_U - ldr r1, =CFG_GAFR0_U_VAL - str r1, [r0] - - ldr r0, =GAFR1_L - ldr r1, =CFG_GAFR1_L_VAL - str r1, [r0] - - ldr r0, =GAFR1_U - ldr r1, =CFG_GAFR1_U_VAL - str r1, [r0] - - ldr r0, =GAFR2_L - ldr r1, =CFG_GAFR2_L_VAL - str r1, [r0] - - ldr r0, =GAFR2_U - ldr r1, =CFG_GAFR2_U_VAL - str r1, [r0] - - ldr r0, =PSSR /* enable GPIO pins */ - ldr r1, =CFG_PSSR_VAL - str r1, [r0] - -#ifdef DEBUG_BLINK_ENABLE - /* 4th debug blink */ - bl blink -#endif - - /* ---------------------------------------------------------------- */ - /* Enable memory interface */ - /* */ - /* The sequence below is based on the recommended init steps */ - /* detailed in the Intel PXA250 Operating Systems Developers Guide, */ - /* Chapter 10. */ - /* ---------------------------------------------------------------- */ - - /* ---------------------------------------------------------------- */ - /* Step 1: Wait for at least 200 microsedonds to allow internal */ - /* clocks to settle. Only necessary after hard reset... */ - /* FIXME: can be optimized later */ - /* ---------------------------------------------------------------- */ - - ldr r3, =OSCR /* reset the OS Timer Count to zero */ - mov r2, #0 - str r2, [r3] - ldr r4, =0x300 /* really 0x2E1 is about 200usec, */ - /* so 0x300 should be plenty */ -1: - ldr r2, [r3] - cmp r4, r2 - bgt 1b - -mem_init: - - ldr r1, =MEMC_BASE /* get memory controller base addr. */ - - /* ---------------------------------------------------------------- */ - /* Step 2a: Initialize Asynchronous static memory controller */ - /* ---------------------------------------------------------------- */ - - /* MSC registers: timing, bus width, mem type */ - - /* MSC0: nCS(0,1) */ - ldr r2, =CFG_MSC0_VAL - str r2, [r1, #MSC0_OFFSET] - ldr r2, [r1, #MSC0_OFFSET] /* read back to ensure */ - /* that data latches */ - /* MSC1: nCS(2,3) */ - ldr r2, =CFG_MSC1_VAL - str r2, [r1, #MSC1_OFFSET] - ldr r2, [r1, #MSC1_OFFSET] - - /* MSC2: nCS(4,5) */ - ldr r2, =CFG_MSC2_VAL - str r2, [r1, #MSC2_OFFSET] - ldr r2, [r1, #MSC2_OFFSET] - - /* ---------------------------------------------------------------- */ - /* Step 2b: Initialize Card Interface */ - /* ---------------------------------------------------------------- */ - - /* MECR: Memory Expansion Card Register */ - ldr r2, =CFG_MECR_VAL - str r2, [r1, #MECR_OFFSET] - ldr r2, [r1, #MECR_OFFSET] - - /* MCMEM0: Card Interface slot 0 timing */ - ldr r2, =CFG_MCMEM0_VAL - str r2, [r1, #MCMEM0_OFFSET] - ldr r2, [r1, #MCMEM0_OFFSET] - - /* MCMEM1: Card Interface slot 1 timing */ - ldr r2, =CFG_MCMEM1_VAL - str r2, [r1, #MCMEM1_OFFSET] - ldr r2, [r1, #MCMEM1_OFFSET] - - /* MCATT0: Card Interface Attribute Space Timing, slot 0 */ - ldr r2, =CFG_MCATT0_VAL - str r2, [r1, #MCATT0_OFFSET] - ldr r2, [r1, #MCATT0_OFFSET] - - /* MCATT1: Card Interface Attribute Space Timing, slot 1 */ - ldr r2, =CFG_MCATT1_VAL - str r2, [r1, #MCATT1_OFFSET] - ldr r2, [r1, #MCATT1_OFFSET] - - /* MCIO0: Card Interface I/O Space Timing, slot 0 */ - ldr r2, =CFG_MCIO0_VAL - str r2, [r1, #MCIO0_OFFSET] - ldr r2, [r1, #MCIO0_OFFSET] - - /* MCIO1: Card Interface I/O Space Timing, slot 1 */ - ldr r2, =CFG_MCIO1_VAL - str r2, [r1, #MCIO1_OFFSET] - ldr r2, [r1, #MCIO1_OFFSET] - -#ifdef DEBUG_BLINK_ENABLE - /* 5th blink */ - bl blink -#endif - - /* ---------------------------------------------------------------- */ - /* Step 2c: Write FLYCNFG FIXME: what's that??? */ - /* ---------------------------------------------------------------- */ - - /* ---------------------------------------------------------------- */ - /* Step 2d: Initialize Timing for Sync Memory (SDCLK0) */ - /* ---------------------------------------------------------------- */ - - /* Before accessing MDREFR we need a valid DRI field, so we set */ - /* this to power on defaults + DRI field. */ - - ldr r3, =CFG_MDREFR_VAL - ldr r2, =0xFFF - and r3, r3, r2 - ldr r4, =0x03ca4000 - orr r4, r4, r3 - str r4, [r1, #MDREFR_OFFSET] /* write back MDREFR */ - ldr r4, [r1, #MDREFR_OFFSET] - - /* Note: preserve the mdrefr value in r4 */ - - /* ---------------------------------------------------------------- */ - /* Step 3: Initialize Synchronous Static Memory (Flash/Peripherals) */ - /* ---------------------------------------------------------------- */ - - /* Initialize SXCNFG register. Assert the enable bits */ - - /* Write SXMRS to cause an MRS command to all enabled banks of */ - /* synchronous static memory. Note that SXLCR need not be written */ - /* at this time. */ - - /* FIXME: we use async mode for now */ - - /* ---------------------------------------------------------------- */ - /* Step 4: Initialize SDRAM */ - /* ---------------------------------------------------------------- */ - - /* set MDREFR according to user define with exception of a few bits */ - - ldr r4, =CFG_MDREFR_VAL - orr r4, r4, #(MDREFR_SLFRSH) - bic r4, r4, #(MDREFR_E1PIN|MDREFR_E0PIN) - str r4, [r1, #MDREFR_OFFSET] /* write back MDREFR */ - ldr r4, [r1, #MDREFR_OFFSET] - - /* Step 4b: de-assert MDREFR:SLFRSH. */ - - bic r4, r4, #(MDREFR_SLFRSH) - str r4, [r1, #MDREFR_OFFSET] /* write back MDREFR */ - ldr r4, [r1, #MDREFR_OFFSET] - - /* Step 4c: assert MDREFR:E1PIN and E0PIO as desired */ - - ldr r4, =CFG_MDREFR_VAL - str r4, [r1, #MDREFR_OFFSET] /* write back MDREFR */ - ldr r4, [r1, #MDREFR_OFFSET] - - - /* Step 4d: write MDCNFG with MDCNFG:DEx deasserted (set to 0), to */ - /* configure but not enable each SDRAM partition pair. */ - - ldr r4, =CFG_MDCNFG_VAL - bic r4, r4, #(MDCNFG_DE0|MDCNFG_DE1) - - str r4, [r1, #MDCNFG_OFFSET] /* write back MDCNFG */ - ldr r4, [r1, #MDCNFG_OFFSET] - - /* Step 4e: Wait for the clock to the SDRAMs to stabilize, */ - /* 100..200 µsec. */ - - ldr r3, =OSCR /* reset the OS Timer Count to zero */ - mov r2, #0 - str r2, [r3] - ldr r4, =0x300 /* really 0x2E1 is about 200usec, */ - /* so 0x300 should be plenty */ -1: - ldr r2, [r3] - cmp r4, r2 - bgt 1b - - /* Step 4f: Trigger a number (usually 8) refresh cycles by */ - /* attempting non-burst read or write accesses to disabled */ - /* SDRAM, as commonly specified in the power up sequence */ - /* documented in SDRAM data sheets. The address(es) used */ - /* for this purpose must not be cacheable. */ - - ldr r3, =CFG_DRAM_BASE - str r2, [r3] - str r2, [r3] - str r2, [r3] - str r2, [r3] - str r2, [r3] - str r2, [r3] - str r2, [r3] - str r2, [r3] - - /* Step 4g: Write MDCNFG with enable bits asserted */ - /* (MDCNFG:DEx set to 1). */ - - ldr r3, [r1, #MDCNFG_OFFSET] - orr r3, r3, #(MDCNFG_DE0|MDCNFG_DE1) - str r3, [r1, #MDCNFG_OFFSET] - - /* Step 4h: Write MDMRS. */ - - ldr r2, =CFG_MDMRS_VAL - str r2, [r1, #MDMRS_OFFSET] - - /* We are finished with Intel's memory controller initialisation */ -#if 0 - /* FIXME turn on serial ports */ - /* look into moving this to board_init() */ - ldr r2, =(PXA_CS5_PHYS + 0x03C0002c) - mov r3, #0x13 - str r3, [r2] -#endif - -#ifdef DEBUG_BLINK_ENABLE - /* 6th blink */ - bl blink -#endif - - /* ---------------------------------------------------------------- */ - /* Disable (mask) all interrupts at interrupt controller */ - /* ---------------------------------------------------------------- */ - -initirqs: - - mov r1, #0 /* clear int. level register (IRQ, not FIQ) */ - ldr r2, =ICLR - str r1, [r2] - - ldr r2, =ICMR /* mask all interrupts at the controller */ - str r1, [r2] - - /* ---------------------------------------------------------------- */ - /* Clock initialisation */ - /* ---------------------------------------------------------------- */ - -initclks: - - /* Disable the peripheral clocks, and set the core clock frequency */ - /* (hard-coding at 398.12MHz for now). */ - - /* Turn Off ALL on-chip peripheral clocks for re-configuration */ - /* Note: See label 'ENABLECLKS' for the re-enabling */ -#if 0 - ldr r1, =CKEN - mov r2, #0 - str r2, [r1] - - /* default value in case no valid rotary switch setting is found */ - ldr r2, =(CCCR_L27|CCCR_M2|CCCR_N10) /* DEFAULT: {200/200/100} */ - - /* ... and write the core clock config register */ - ldr r1, =CCCR - str r2, [r1] - -#endif - -#ifdef RTC - /* enable the 32Khz oscillator for RTC and PowerManager */ - - ldr r1, =OSCC - mov r2, #OSCC_OON - str r2, [r1] - - /* NOTE: spin here until OSCC.OOK get set, meaning the PLL */ - /* has settled. */ -60: - ldr r2, [r1] - ands r2, r2, #1 - beq 60b -#endif - - /* ---------------------------------------------------------------- */ - /* */ - /* ---------------------------------------------------------------- */ - - /* Save SDRAM size */ - ldr r1, =DRAM_SIZE - str r8, [r1] - - /* Interrupt init: Mask all interrupts */ - ldr r0, =ICMR /* enable no sources */ - mov r1, #0 - str r1, [r0] - - /* FIXME */ - -#define NODEBUG -#ifdef NODEBUG - /*Disable software and data breakpoints */ - mov r0,#0 - mcr p15,0,r0,c14,c8,0 /* ibcr0 */ - mcr p15,0,r0,c14,c9,0 /* ibcr1 */ - mcr p15,0,r0,c14,c4,0 /* dbcon */ - - /*Enable all debug functionality */ - mov r0,#0x80000000 - mcr p14,0,r0,c10,c0,0 /* dcsr */ -#endif - - /* ---------------------------------------------------------------- */ - /* End memsetup */ - /* ---------------------------------------------------------------- */ - -#ifdef DEBUG_BLINK_ENABLE - /* 7th blink */ - bl blink -#endif - -endmemsetup: - - mov pc, r10 - - -#ifdef DEBUG_BLINK_ENABLE - -/* debug LED code */ - -/* delay about 200ms */ -delay: - - /* reset OSCR to 0 */ - ldr r8, =OSCR - mov r9, #0 - str r9, [r8] - - /* make sure new value has stuck */ -1: - ldr r8, =OSCR - ldr r9, [r8] - mov r8, #0x10000 - cmp r9, r8 - bgt 1b - - /* now, wait for delay to expire */ -1: - ldr r8, =OSCR - ldr r9, [r8] - mov r8, #0xd4000 - cmp r8, r9 - bgt 1b - - mov pc, lr - -/* blink code -- trashes r7, r8, r9 */ - -.globl blink -blink: - - mov r7, lr - - /* set GPIO10 as outout */ - ldr r8, =GPDR0 - ldr r9, [r8] - orr r9, r9, #(1<<10) - str r9, [r8] - - /* turn LED off */ - mov r9, #(1<<10) - ldr r8, =GPCR0 - str r9, [r8] - bl delay - - /* turn LED on */ - mov r9, #(1<<10) - ldr r8, =GPSR0 - str r9, [r8] - bl delay - - /* turn LED off */ - mov r9, #(1<<10) - ldr r8, =GPCR0 - str r9, [r8] - - mov pc, r7 - -#endif diff --git a/board/pxa255_idp/u-boot.lds b/board/pxa255_idp/u-boot.lds index 20ce1089389..2facd832e9b 100644 --- a/board/pxa255_idp/u-boot.lds +++ b/board/pxa255_idp/u-boot.lds @@ -44,6 +44,7 @@ SECTIONS . = ALIGN(4); .got : { *(.got) } + . = .; __u_boot_cmd_start = .; .u_boot_cmd : { *(.u_boot_cmd) } __u_boot_cmd_end = .; diff --git a/cpu/pxa/config.mk b/cpu/pxa/config.mk index fb810ca7c26..f0b86b7dc16 100644 --- a/cpu/pxa/config.mk +++ b/cpu/pxa/config.mk @@ -25,8 +25,7 @@ PLATFORM_RELFLAGS += -fno-strict-aliasing -fno-common -ffixed-r8 \ -msoft-float -#PLATFORM_CPPFLAGS += -mapcs-32 -march=armv4 -mtune=strongarm1100 -PLATFORM_CPPFLAGS += -march=armv5 -mtune=xscale +PLATFORM_CPPFLAGS += -march=armv5te -mtune=xscale # ========================================================================= # # Supply options according to compiler version diff --git a/cpu/pxa/serial.c b/cpu/pxa/serial.c index 51e7f658878..9ba457e75aa 100644 --- a/cpu/pxa/serial.c +++ b/cpu/pxa/serial.c @@ -35,17 +35,17 @@ DECLARE_GLOBAL_DATA_PTR; -#define FFUART 0 -#define BTUART 1 -#define STUART 2 +#define FFUART_INDEX 0 +#define BTUART_INDEX 1 +#define STUART_INDEX 2 #ifndef CONFIG_SERIAL_MULTI #if defined (CONFIG_FFUART) -#define UART_INDEX FFUART +#define UART_INDEX FFUART_INDEX #elif defined (CONFIG_BTUART) -#define UART_INDEX BTUART +#define UART_INDEX BTUART_INDEX #elif defined (CONFIG_STUART) -#define UART_INDEX STUART +#define UART_INDEX STUART_INDEX #else #error "Bad: you didn't configure serial ..." #endif @@ -71,7 +71,7 @@ void pxa_setbrg_dev (unsigned int uart_index) hang (); switch (uart_index) { - case FFUART: + case FFUART_INDEX: #ifdef CONFIG_CPU_MONAHANS CKENA |= CKENA_22_FFUART; #else @@ -90,7 +90,7 @@ void pxa_setbrg_dev (unsigned int uart_index) FFIER = IER_UUE; /* Enable FFUART */ break; - case BTUART: + case BTUART_INDEX: #ifdef CONFIG_CPU_MONAHANS CKENA |= CKENA_21_BTUART; #else @@ -110,7 +110,7 @@ void pxa_setbrg_dev (unsigned int uart_index) break; - case STUART: + case STUART_INDEX: #ifdef CONFIG_CPU_MONAHANS CKENA |= CKENA_23_STUART; #else @@ -154,20 +154,20 @@ int pxa_init_dev (unsigned int uart_index) void pxa_putc_dev (unsigned int uart_index,const char c) { switch (uart_index) { - case FFUART: + case FFUART_INDEX: /* wait for room in the tx FIFO on FFUART */ while ((FFLSR & LSR_TEMT) == 0) WATCHDOG_RESET (); /* Reset HW Watchdog, if needed */ FFTHR = c; break; - case BTUART: + case BTUART_INDEX: while ((BTLSR & LSR_TEMT ) == 0 ) WATCHDOG_RESET (); /* Reset HW Watchdog, if needed */ BTTHR = c; break; - case STUART: + case STUART_INDEX: while ((STLSR & LSR_TEMT ) == 0 ) WATCHDOG_RESET (); /* Reset HW Watchdog, if needed */ STTHR = c; @@ -187,11 +187,11 @@ void pxa_putc_dev (unsigned int uart_index,const char c) int pxa_tstc_dev (unsigned int uart_index) { switch (uart_index) { - case FFUART: + case FFUART_INDEX: return FFLSR & LSR_DR; - case BTUART: + case BTUART_INDEX: return BTLSR & LSR_DR; - case STUART: + case STUART_INDEX: return STLSR & LSR_DR; } return -1; @@ -205,16 +205,16 @@ int pxa_tstc_dev (unsigned int uart_index) int pxa_getc_dev (unsigned int uart_index) { switch (uart_index) { - case FFUART: + case FFUART_INDEX: while (!(FFLSR & LSR_DR)) WATCHDOG_RESET (); /* Reset HW Watchdog, if needed */ return (char) FFRBR & 0xff; - case BTUART: + case BTUART_INDEX: while (!(BTLSR & LSR_DR)) WATCHDOG_RESET (); /* Reset HW Watchdog, if needed */ return (char) BTRBR & 0xff; - case STUART: + case STUART_INDEX: while (!(STLSR & LSR_DR)) WATCHDOG_RESET (); /* Reset HW Watchdog, if needed */ return (char) STRBR & 0xff; @@ -233,32 +233,32 @@ pxa_puts_dev (unsigned int uart_index,const char *s) #if defined (CONFIG_FFUART) static int ffuart_init(void) { - return pxa_init_dev(FFUART); + return pxa_init_dev(FFUART_INDEX); } static void ffuart_setbrg(void) { - return pxa_setbrg_dev(FFUART); + return pxa_setbrg_dev(FFUART_INDEX); } static void ffuart_putc(const char c) { - return pxa_putc_dev(FFUART,c); + return pxa_putc_dev(FFUART_INDEX,c); } static void ffuart_puts(const char *s) { - return pxa_puts_dev(FFUART,s); + return pxa_puts_dev(FFUART_INDEX,s); } static int ffuart_getc(void) { - return pxa_getc_dev(FFUART); + return pxa_getc_dev(FFUART_INDEX); } static int ffuart_tstc(void) { - return pxa_tstc_dev(FFUART); + return pxa_tstc_dev(FFUART_INDEX); } struct serial_device serial_ffuart_device = @@ -277,32 +277,32 @@ struct serial_device serial_ffuart_device = #if defined (CONFIG_BTUART) static int btuart_init(void) { - return pxa_init_dev(BTUART); + return pxa_init_dev(BTUART_INDEX); } static void btuart_setbrg(void) { - return pxa_setbrg_dev(BTUART); + return pxa_setbrg_dev(BTUART_INDEX); } static void btuart_putc(const char c) { - return pxa_putc_dev(BTUART,c); + return pxa_putc_dev(BTUART_INDEX,c); } static void btuart_puts(const char *s) { - return pxa_puts_dev(BTUART,s); + return pxa_puts_dev(BTUART_INDEX,s); } static int btuart_getc(void) { - return pxa_getc_dev(BTUART); + return pxa_getc_dev(BTUART_INDEX); } static int btuart_tstc(void) { - return pxa_tstc_dev(BTUART); + return pxa_tstc_dev(BTUART_INDEX); } struct serial_device serial_btuart_device = @@ -321,32 +321,32 @@ struct serial_device serial_btuart_device = #if defined (CONFIG_STUART) static int stuart_init(void) { - return pxa_init_dev(STUART); + return pxa_init_dev(STUART_INDEX); } static void stuart_setbrg(void) { - return pxa_setbrg_dev(STUART); + return pxa_setbrg_dev(STUART_INDEX); } static void stuart_putc(const char c) { - return pxa_putc_dev(STUART,c); + return pxa_putc_dev(STUART_INDEX,c); } static void stuart_puts(const char *s) { - return pxa_puts_dev(STUART,s); + return pxa_puts_dev(STUART_INDEX,s); } static int stuart_getc(void) { - return pxa_getc_dev(STUART); + return pxa_getc_dev(STUART_INDEX); } static int stuart_tstc(void) { - return pxa_tstc_dev(STUART); + return pxa_tstc_dev(STUART_INDEX); } struct serial_device serial_stuart_device = diff --git a/cpu/pxa/start.S b/cpu/pxa/start.S index ffaa30fdc58..b922485ed33 100644 --- a/cpu/pxa/start.S +++ b/cpu/pxa/start.S @@ -166,13 +166,17 @@ _start_armboot: .word start_armboot /* */ /****************************************************************************/ /* mk@tbd: Fix this! */ -#ifdef CONFIG_CPU_MONAHANS +#if defined(CONFIG_PXA250) || defined(CONFIG_CPU_MONAHANS) #undef ICMR #undef OSMR3 #undef OSCR #undef OWER #undef OIER #endif +#ifdef CONFIG_PXA250 +#undef RCSR +#undef CCCR +#endif /* Interrupt-Controller base address */ IC_BASE: .word 0x40d00000 diff --git a/include/configs/pxa255_idp.h b/include/configs/pxa255_idp.h index 0e884fc114c..4a9cadbc738 100644 --- a/include/configs/pxa255_idp.h +++ b/include/configs/pxa255_idp.h @@ -38,10 +38,11 @@ #include /* - * If we are developing, we might want to start armboot from ram + * If we are developing, we might want to start U-Boot from RAM * so we MUST NOT initialize critical regs like mem-timing ... */ -#define CONFIG_INIT_CRITICAL /* undef for developing */ +#undef CONFIG_SKIP_LOWLEVEL_INIT /* define for developing */ +#undef CONFIG_SKIP_RELOCATE_UBOOT /* define for developing */ /* * define the following to enable debug blinks. A debug blink function @@ -62,6 +63,7 @@ #endif #define CONFIG_MMC 1 +#define CONFIG_DOS_PARTITION 1 #define BOARD_LATE_INIT 1 #undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */ @@ -121,7 +123,6 @@ #define CONFIG_CMD_FAT #define CONFIG_CMD_DHCP - #define CONFIG_BOOTDELAY 3 #define CONFIG_BOOTCOMMAND "bootm 40000" #define CONFIG_BOOTARGS "root=/dev/mtdblock2 rootfstype=cramfs console=ttyS0,115200" @@ -332,7 +333,7 @@ #define CFG_FLASH_CFI_DRIVER 1 #define CFG_MONITOR_BASE 0 -#define CFG_MONITOR_LEN 0x40000 +#define CFG_MONITOR_LEN PHYS_FLASH_SECT_SIZE #define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ #define CFG_MAX_FLASH_SECT 128 /* max number of sectors on one chip */ @@ -347,7 +348,7 @@ #define CFG_ENV_IS_IN_FLASH 1 /* Addr of Environment Sector */ #define CFG_ENV_ADDR (PHYS_FLASH_1 + PHYS_FLASH_SIZE - 0x40000) -#define CFG_ENV_SIZE 0x40000 /* Total Size of Environment Sector */ -#define CFG_ENV_SECT_SIZE 0x40000 +#define CFG_ENV_SIZE PHYS_FLASH_SECT_SIZE /* Total Size of Environment Sector */ +#define CFG_ENV_SECT_SIZE (PHYS_FLASH_SECT_SIZE / 16) #endif /* __CONFIG_H */ diff --git a/include/part.h b/include/part.h index 29c03205f2d..37b2b6845bc 100644 --- a/include/part.h +++ b/include/part.h @@ -38,9 +38,9 @@ typedef struct block_dev_desc { #endif lbaint_t lba; /* number of blocks */ unsigned long blksz; /* block size */ - unsigned char vendor [40+1]; /* IDE model, SCSI Vendor */ - unsigned char product[20+1]; /* IDE Serial no, SCSI product */ - unsigned char revision[8+1]; /* firmware revision */ + char vendor [40+1]; /* IDE model, SCSI Vendor */ + char product[20+1]; /* IDE Serial no, SCSI product */ + char revision[8+1]; /* firmware revision */ unsigned long (*block_read)(int dev, unsigned long start, lbaint_t blkcnt, -- cgit v1.2.3 From 96455bfebc9887837095c9051d216f53c61b5f10 Mon Sep 17 00:00:00 2001 From: Jean-Christophe PLAGNIOL-VILLARD Date: Fri, 19 Oct 2007 00:07:39 +0200 Subject: Fix warning differ in signedness in board/innokom/innokom.c Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD --- board/innokom/innokom.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/board/innokom/innokom.c b/board/innokom/innokom.c index 7f8f47c3a2e..c2b88ae16ad 100644 --- a/board/innokom/innokom.c +++ b/board/innokom/innokom.c @@ -72,7 +72,7 @@ int i2c_init_board(void) int misc_init_r(void) { - uchar *str; + char *str; /* determine if the software update key is pressed during startup */ if (GPLR0 & 0x00000800) { -- cgit v1.2.3 From 58b74b05c621e2835ecf4e2d3243042cf4186777 Mon Sep 17 00:00:00 2001 From: Jean-Christophe PLAGNIOL-VILLARD Date: Fri, 19 Oct 2007 00:09:05 +0200 Subject: Fix missing drivers makefile entries ds1722.c mw_eeprom.c Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD --- drivers/Makefile | 3 ++- drivers/ds1722.c | 4 ++-- drivers/mw_eeprom.c | 4 ++-- 3 files changed, 6 insertions(+), 5 deletions(-) diff --git a/drivers/Makefile b/drivers/Makefile index 6bf05ccad19..aba64f573a5 100755 --- a/drivers/Makefile +++ b/drivers/Makefile @@ -54,7 +54,8 @@ COBJS = 3c589.o 5701rls.o ali512x.o at45.o ata_piix.o atmel_usart.o \ ks8695eth.o \ pxa_pcmcia.o mpc8xx_pcmcia.o tqm8xx_pcmcia.o \ rpx_pcmcia.o \ - fsl_i2c.o fsl_pci_init.o ati_radeon_fb.o + fsl_i2c.o fsl_pci_init.o ati_radeon_fb.o \ + ds1722.o mw_eeprom.o SRCS := $(COBJS:.o=.c) OBJS := $(addprefix $(obj),$(COBJS)) diff --git a/drivers/ds1722.c b/drivers/ds1722.c index 227d8169a5b..c19ee01393f 100644 --- a/drivers/ds1722.c +++ b/drivers/ds1722.c @@ -1,10 +1,10 @@ #include -#include - #ifdef CONFIG_DS1722 +#include + static void ds1722_select(int dev) { ssi_set_interface(4096, 0, 0, 0); diff --git a/drivers/mw_eeprom.c b/drivers/mw_eeprom.c index 2a1f4898429..2b3348810d2 100644 --- a/drivers/mw_eeprom.c +++ b/drivers/mw_eeprom.c @@ -1,11 +1,11 @@ /* Three-wire (MicroWire) serial eeprom driver (for 93C46 and compatibles) */ #include -#include - #ifdef CONFIG_MW_EEPROM +#include + /* * Serial EEPROM opcodes, including start bit */ -- cgit v1.2.3 From 41b4d282d38fa7231c315c5f6cfff5bdd24e0191 Mon Sep 17 00:00:00 2001 From: Wolfgang Denk Date: Tue, 23 Oct 2007 16:50:03 +0200 Subject: Coding style: keep lists sorted; update CHANGELOG Signed-off-by: Wolfgang Denk --- CHANGELOG | 61 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++ drivers/Makefile | 30 +++++++++++++--------------- 2 files changed, 75 insertions(+), 16 deletions(-) diff --git a/CHANGELOG b/CHANGELOG index 05400013897..549c4f919cb 100644 --- a/CHANGELOG +++ b/CHANGELOG @@ -1,3 +1,64 @@ +commit 58b74b05c621e2835ecf4e2d3243042cf4186777 +Author: Jean-Christophe PLAGNIOL-VILLARD +Date: Fri Oct 19 00:09:05 2007 +0200 + + Fix missing drivers makefile entries ds1722.c mw_eeprom.c + + Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD + +commit 96455bfebc9887837095c9051d216f53c61b5f10 +Author: Jean-Christophe PLAGNIOL-VILLARD +Date: Fri Oct 19 00:07:39 2007 +0200 + + Fix warning differ in signedness in board/innokom/innokom.c + + Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD + +commit 2a4741d9a14ec475f50e9856d2c0a67e8b4271bd +Author: Marcel Ziswiler +Date: Fri Oct 19 00:25:33 2007 +0200 + + fix pxa255_idp board + + The pxa255_idp being an old unmaintained board showed several issues: + 1. CONFIG_INIT_CRITICAL was still defined. + 2. Neither CONFIG_MAC_PARTITION nor CONFIG_DOS_PARTITION was defined. + 3. Symbol flash_addr was undeclared. + 4. The boards lowlevel_init function was still called memsetup. + 5. The TEXT_BASE was still 0xa3000000 rather than 0xa3080000. + 6. Using -march=armv5 instead of -march=armv5te resulted in lots of + 'target CPU does not support interworking' warnings on recent compilers. + 7. The PXA's serial driver redefined FFUART, BTUART and STUART used as + indexes rather than the register definitions from the pxa-regs header + file. Renamed them to FFUART_INDEX, BTUART_INDEX and STUART_INDEX to + avoid any ambiguities. + 8. There were several redefinition warnings concerning ICMR, OSMR3, + OSCR, OWER, OIER, RCSR and CCCR in the PXA's assembly start file. + 9. The board configuration file was rather outdated. + 10. The part header file defined the vendor, product and revision arrays + as unsigned chars instead of just chars in the block_dev_desc_t + structure. + + Signed-off-by: Marcel Ziswiler + +commit 298cd4cafe81ff8a6c87be8fbc440a20720d3ed6 +Author: Rune Torgersen +Date: Wed Oct 17 11:56:31 2007 -0500 + + Make MPC8266ADS command selection more robust + + Fix MPC8266 command line definition so it won't break when new commands + are added to u-boot. + Signed-off-by Rune Torgersen + +commit 05bf4919c1ce49cdedadacd564d0786a8ed796a1 +Author: Wolfgang Denk +Date: Sun Oct 21 01:01:17 2007 +0200 + + Minor coding style cleanup; update CHANGELOG + + Signed-off-by: Wolfgang Denk + commit ff285ca07eda1ea4a8909848cc1cc604ec8fec9c Author: Vlad Lungu Date: Thu Oct 4 20:47:10 2007 +0300 diff --git a/drivers/Makefile b/drivers/Makefile index aba64f573a5..00978d82853 100755 --- a/drivers/Makefile +++ b/drivers/Makefile @@ -1,5 +1,5 @@ # -# (C) Copyright 2000-2006 +# (C) Copyright 2000-2007 # Wolfgang Denk, DENX Software Engineering, wd@denx.de. # # See file CREDITS for list of people who contributed to this @@ -27,35 +27,33 @@ include $(TOPDIR)/config.mk LIB = $(obj)libdrivers.a -COBJS = 3c589.o 5701rls.o ali512x.o at45.o ata_piix.o atmel_usart.o \ +COBJS = 3c589.o 5701rls.o ali512x.o at45.o ata_piix.o \ + ati_radeon_fb.o atmel_usart.o \ bcm570x.o bcm570x_autoneg.o cfb_console.o cfi_flash.o \ cs8900.o ct69000.o dataflash.o dc2114x.o dm9000x.o \ - e1000.o eepro100.o enc28j60.o \ - i8042.o inca-ip_sw.o isp116x-hcd.o keyboard.o \ - lan91c96.o macb.o \ + ds1722.o e1000.o eepro100.o enc28j60.o \ + fsl_i2c.o fsl_pci_init.o \ + i8042.o inca-ip_sw.o isp116x-hcd.o \ + keyboard.o ks8695eth.o \ + lan91c96.o macb.o mpc8xx_pcmcia.o mw_eeprom.o \ natsemi.o ne2000.o netarm_eth.o netconsole.o \ ns16550.o ns8382x.o ns87308.o ns7520_eth.o omap1510_i2c.o \ - omap24xx_i2c.o pci.o pci_auto.o pci_indirect.o \ - pcnet.o plb2800_eth.o \ - ps2ser.o ps2mult.o pc_keyb.o \ - rtl8019.o rtl8139.o rtl8169.o \ + omap24xx_i2c.o pc_keyb.o \ + pci.o pci_auto.o pci_indirect.o \ + pcnet.o plb2800_eth.o ps2ser.o ps2mult.o pxa_pcmcia.o \ + rpx_pcmcia.o rtl8019.o rtl8139.o rtl8169.o \ s3c4510b_eth.o s3c4510b_uart.o \ sed13806.o sed156x.o \ serial.o serial_max3100.o \ serial_pl010.o serial_pl011.o serial_xuartlite.o \ sil680.o sl811_usb.o sm501.o smc91111.o smiLynxEM.o \ status_led.o sym53c8xx.o systemace.o ahci.o \ - ti_pci1410a.o tigon3.o tsec.o \ + ti_pci1410a.o tigon3.o tqm8xx_pcmcia.o tsec.o \ tsi108_eth.o tsi108_i2c.o tsi108_pci.o \ usb_ohci.o \ usbdcore.o usbdcore_ep0.o usbdcore_mpc8xx.o usbdcore_omap1510.o \ usbtty.o \ - videomodes.o w83c553f.o \ - ks8695eth.o \ - pxa_pcmcia.o mpc8xx_pcmcia.o tqm8xx_pcmcia.o \ - rpx_pcmcia.o \ - fsl_i2c.o fsl_pci_init.o ati_radeon_fb.o \ - ds1722.o mw_eeprom.o + videomodes.o w83c553f.o SRCS := $(COBJS:.o=.c) OBJS := $(addprefix $(obj),$(COBJS)) -- cgit v1.2.3 From 10cdb8dbd67a818823ab9ec88b68fc348903db59 Mon Sep 17 00:00:00 2001 From: Jean-Christophe PLAGNIOL-VILLARD Date: Fri, 19 Oct 2007 00:24:59 +0200 Subject: lubbock: Fix no partition type specified, use DOS as default Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD --- include/configs/lubbock.h | 1 + 1 file changed, 1 insertion(+) diff --git a/include/configs/lubbock.h b/include/configs/lubbock.h index 4adf2542219..82fe19c725f 100644 --- a/include/configs/lubbock.h +++ b/include/configs/lubbock.h @@ -42,6 +42,7 @@ #endif #define CONFIG_MMC 1 #define BOARD_LATE_INIT 1 +#define CONFIG_DOS_PARTITION #undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */ -- cgit v1.2.3 From e78220f6e514206757acfe247297fc9a328a881f Mon Sep 17 00:00:00 2001 From: Jean-Christophe PLAGNIOL-VILLARD Date: Fri, 19 Oct 2007 06:33:45 +0200 Subject: xsengine: Fix no partition type specified, use DOS as default Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD --- board/xsengine/flash.c | 4 ++-- include/configs/xsengine.h | 1 + 2 files changed, 3 insertions(+), 2 deletions(-) diff --git a/board/xsengine/flash.c b/board/xsengine/flash.c index 2b9afc7a77b..a188e244089 100644 --- a/board/xsengine/flash.c +++ b/board/xsengine/flash.c @@ -46,11 +46,11 @@ unsigned long flash_init (void) for (i = 0; i < CFG_MAX_FLASH_BANKS; i++) { switch (i) { case 0: - flash_get_size ((long *) PHYS_FLASH_1, &flash_info[i]); + flash_get_size ((vu_long *) PHYS_FLASH_1, &flash_info[i]); flash_get_offsets (PHYS_FLASH_1, &flash_info[i]); break; case 1: - flash_get_size ((long *) PHYS_FLASH_2, &flash_info[i]); + flash_get_size ((vu_long *) PHYS_FLASH_2, &flash_info[i]); flash_get_offsets (PHYS_FLASH_2, &flash_info[i]); break; default: diff --git a/include/configs/xsengine.h b/include/configs/xsengine.h index 5733933d616..766617e0753 100644 --- a/include/configs/xsengine.h +++ b/include/configs/xsengine.h @@ -32,6 +32,7 @@ #define CONFIG_PXA250 1 /* This is an PXA250 CPU */ #define CONFIG_XSENGINE 1 #define CONFIG_MMC 1 +#define CONFIG_DOS_PARTITION 1 #define BOARD_POST_INIT 1 #undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */ #define CFG_HZ 3686400 /* incrementer freq: 3.6864 MHz */ -- cgit v1.2.3 From 9c4884f54da982ce990c7d1760ac81b0704d3c64 Mon Sep 17 00:00:00 2001 From: Jean-Christophe PLAGNIOL-VILLARD Date: Fri, 19 Oct 2007 08:10:15 +0200 Subject: fix warning: no return statement in function returning non-void Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD --- cpu/arm920t/at91rm9200/usb.c | 8 ++++---- cpu/pxa/usb.c | 6 +++--- 2 files changed, 7 insertions(+), 7 deletions(-) diff --git a/cpu/arm920t/at91rm9200/usb.c b/cpu/arm920t/at91rm9200/usb.c index 366262e4ccd..c121de6328e 100644 --- a/cpu/arm920t/at91rm9200/usb.c +++ b/cpu/arm920t/at91rm9200/usb.c @@ -28,7 +28,7 @@ #include -int usb_cpu_init() +int usb_cpu_init(void) { /* Enable USB host clock. */ *AT91C_PMC_SCER = AT91C_PMC_UHP; /* 48MHz clock enabled for UHP */ @@ -36,7 +36,7 @@ int usb_cpu_init() return 0; } -int usb_cpu_stop() +int usb_cpu_stop(void) { /* Initialization failed */ *AT91C_PMC_PCDR = 1 << AT91C_ID_UHP; /* Peripheral Clock Disable Register */ @@ -44,9 +44,9 @@ int usb_cpu_stop() return 0; } -int usb_cpu_init_fail() +int usb_cpu_init_fail(void) { - usb_cpu_stop(); + return usb_cpu_stop(); } # endif /* CONFIG_AT91RM9200 */ diff --git a/cpu/pxa/usb.c b/cpu/pxa/usb.c index 3c11d4de44f..d2812a413ed 100644 --- a/cpu/pxa/usb.c +++ b/cpu/pxa/usb.c @@ -28,7 +28,7 @@ #include -int usb_cpu_init() +int usb_cpu_init(void) { #if defined(CONFIG_CPU_MONAHANS) /* Enable USB host clock. */ @@ -65,7 +65,7 @@ int usb_cpu_init() return 0; } -int usb_cpu_stop() +int usb_cpu_stop(void) { UHCHR |= UHCHR_FHR; udelay(11); @@ -86,7 +86,7 @@ int usb_cpu_stop() return 0; } -int usb_cpu_init_fail() +int usb_cpu_init_fail(void) { return 0; } -- cgit v1.2.3 From e9d0d527992566ebef9826962ff1745b2f082b92 Mon Sep 17 00:00:00 2001 From: Jean-Christophe PLAGNIOL-VILLARD Date: Fri, 19 Oct 2007 10:55:24 +0200 Subject: delta: Fix OHCI_REGS_BASE undeclared and wait_ms implicit declaration Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD --- cpu/pxa/usb.c | 1 + include/configs/delta.h | 2 ++ 2 files changed, 3 insertions(+) diff --git a/cpu/pxa/usb.c b/cpu/pxa/usb.c index d2812a413ed..72b7dfadfe7 100644 --- a/cpu/pxa/usb.c +++ b/cpu/pxa/usb.c @@ -27,6 +27,7 @@ # if defined(CONFIG_CPU_MONAHANS) || defined(CONFIG_PXA27X) #include +#include int usb_cpu_init(void) { diff --git a/include/configs/delta.h b/include/configs/delta.h index 09667edaa5a..14fde1a9579 100644 --- a/include/configs/delta.h +++ b/include/configs/delta.h @@ -123,6 +123,8 @@ #define CONFIG_USB_STORAGE 1 #define CONFIG_DOS_PARTITION 1 +#include /* for OHCI_REGS_BASE */ + #undef CFG_USB_OHCI_BOARD_INIT #define CFG_USB_OHCI_CPU_INIT 1 #define CFG_USB_OHCI_REGS_BASE OHCI_REGS_BASE -- cgit v1.2.3 From cb8250fe4b3c4ed549b270e8a20bc22060e7e1d2 Mon Sep 17 00:00:00 2001 From: Ed Swarthout Date: Fri, 19 Oct 2007 17:51:40 -0500 Subject: fsl_pci_init enable COMMAND_MEMORY if inbound window Patch 16e23c3f removed PCSRBAR allocation. But passing zero windows to pciauto_setup_device has the side effect of not getting COMMAND_MEMORY set. Signed-off-by: Ed Swarthout --- drivers/fsl_pci_init.c | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/drivers/fsl_pci_init.c b/drivers/fsl_pci_init.c index 3a13eea1f2b..1e778844a5a 100644 --- a/drivers/fsl_pci_init.c +++ b/drivers/fsl_pci_init.c @@ -54,6 +54,7 @@ fsl_pci_init(struct pci_controller *hose) u8 temp8; int r; int bridge; + int inbound = 0; volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) hose->cfg_addr; pci_dev_t dev = PCI_BDF(busno,0,0); @@ -74,6 +75,7 @@ fsl_pci_init(struct pci_controller *hose) PIWAR_READ_SNOOP | PIWAR_WRITE_SNOOP | (__ilog2(hose->regions[r].size) - 1); pi++; + inbound = hose->regions[r].size > 0; } else { /* Outbound */ po->powbar = (hose->regions[r].phys_start >> 12) & 0x000fffff; po->potar = (hose->regions[r].bus_start >> 12) & 0x000fffff; @@ -138,6 +140,12 @@ fsl_pci_init(struct pci_controller *hose) pciauto_setup_device(hose, dev, 0, hose->pci_mem, hose->pci_prefetch, hose->pci_io); + if (inbound) { + pci_hose_read_config_word(hose, dev, PCI_COMMAND, &temp16); + pci_hose_write_config_word(hose, dev, PCI_COMMAND, + temp16 | PCI_COMMAND_MEMORY); + } + #ifndef CONFIG_PCI_NOSCAN printf (" Scanning PCI bus %02x\n", hose->current_busno); hose->last_busno = pci_hose_scan_bus(hose,hose->current_busno); -- cgit v1.2.3 From 7b0a42219f30277f71f4405cbaf8a269f6d2d227 Mon Sep 17 00:00:00 2001 From: Jean-Christophe PLAGNIOL-VILLARD Date: Sun, 21 Oct 2007 09:14:28 +0200 Subject: Mips: Fix string functions differ prototype declaration Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD --- include/asm-mips/string.h | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/include/asm-mips/string.h b/include/asm-mips/string.h index c42ad82c477..579a591e629 100644 --- a/include/asm-mips/string.h +++ b/include/asm-mips/string.h @@ -19,21 +19,21 @@ extern char *strcpy(char *__dest, __const__ char *__src); #undef __HAVE_ARCH_STRNCPY -extern char *strncpy(char *__dest, __const__ char *__src, size_t __n); +extern char *strncpy(char *__dest, __const__ char *__src, __kernel_size_t __n); #undef __HAVE_ARCH_STRCMP extern int strcmp(__const__ char *__cs, __const__ char *__ct); #undef __HAVE_ARCH_STRNCMP -extern int strncmp(__const__ char *__cs, __const__ char *__ct, size_t __count); +extern int strncmp(__const__ char *__cs, __const__ char *__ct, __kernel_size_t __count); #undef __HAVE_ARCH_MEMSET -extern void *memset(void *__s, int __c, size_t __count); +extern void *memset(void *__s, int __c, __kernel_size_t __count); #undef __HAVE_ARCH_MEMCPY -extern void *memcpy(void *__to, __const__ void *__from, size_t __n); +extern void *memcpy(void *__to, __const__ void *__from, __kernel_size_t __n); #undef __HAVE_ARCH_MEMMOVE -extern void *memmove(void *__dest, __const__ void *__src, size_t __n); +extern void *memmove(void *__dest, __const__ void *__src, __kernel_size_t __n); #endif /* _ASM_STRING_H */ -- cgit v1.2.3 From 0fc0f91b20ffa802f5a66534ca5c2844910583f6 Mon Sep 17 00:00:00 2001 From: Martin Krause Date: Mon, 22 Oct 2007 16:40:06 +0200 Subject: TQM5200S: fix commands for STK52xx base board because of missing SM501 grafic controller Some commands for the STK52xx base board try to access the SM501 grafic controller. But the TQM5200S has no grafic controller (only the TQM5200 and the TQM5200B have). This patch deactivates the commands accessing the SM501 for the TQM5200S. Signed-off-by: Martin Krause --- board/tqm5200/cmd_stk52xx.c | 17 ++++++++++------- board/tqm5200/tqm5200.c | 2 ++ 2 files changed, 12 insertions(+), 7 deletions(-) diff --git a/board/tqm5200/cmd_stk52xx.c b/board/tqm5200/cmd_stk52xx.c index b746679afaa..27a6c4163de 100644 --- a/board/tqm5200/cmd_stk52xx.c +++ b/board/tqm5200/cmd_stk52xx.c @@ -561,7 +561,7 @@ void led_init(void) gpt->gpt6.emsr |= 0x00000024; gpt->gpt7.emsr |= 0x00000024; - +#ifndef CONFIG_TQM5200S /* enable SM501 GPIO control (in both power modes) */ *(vu_long *) (SM501_MMIO_BASE+SM501_POWER_MODE0_GATE) |= POWER_MODE_GATE_GPIO_PWM_I2C; @@ -574,6 +574,7 @@ void led_init(void) /* configure SM501 gpio pins 48-51 as output */ *(vu_long *) (SM501_MMIO_BASE+SM501_GPIO_DATA_DIR_HIGH) |= (0xF << 16); +#endif /* !CONFIG_TQM5200S */ } /* @@ -650,7 +651,7 @@ int do_led(char *argv[]) gpt->gpt7.emsr &= ~(1 << 4); } break; - +#ifndef CONFIG_TQM5200S case 24: if (strcmp (argv[3], "on") == 0) { *(vu_long *) (SM501_MMIO_BASE+SM501_GPIO_DATA_LOW) |= @@ -730,7 +731,7 @@ int do_led(char *argv[]) ~(0x1 << 19); } break; - +#endif /* !CONFIG_TQM5200S */ default: printf ("%s: invalid led number %s\n", __FUNCTION__, argv[2]); return 1; @@ -1110,7 +1111,7 @@ int do_rs232(char *argv[]) return error_status; } -#ifndef CONFIG_FO300 +#if !defined(CONFIG_FO300) && !defined(CONFIG_TQM5200S) static void sm501_backlight (unsigned int state) { if (state == BL_ON) { @@ -1120,7 +1121,7 @@ static void sm501_backlight (unsigned int state) *(vu_long *)(SM501_MMIO_BASE+SM501_PANEL_DISPLAY_CONTROL) &= ~((1 << 26) | (1 << 27)); } -#endif +#endif /* !CONFIG_FO300 & !CONFIG_TQM5200S */ int cmd_fkt(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) { @@ -1160,7 +1161,7 @@ int cmd_fkt(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) else printf ("Error\n"); return rcode; -#ifndef CONFIG_FO300 +#if !defined(CONFIG_FO300) && !defined(CONFIG_TQM5200S) } else if (strncmp (argv[1], "backlight", 4) == 0) { if (strncmp (argv[2], "on", 2) == 0) { sm501_backlight (BL_ON); @@ -1170,7 +1171,7 @@ int cmd_fkt(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) sm501_backlight (BL_OFF); return 0; } -#endif +#endif /* !CONFIG_FO300 & !CONFIG_TQM5200S */ } break; @@ -1228,8 +1229,10 @@ U_BOOT_CMD( " - loopback plug for X83 required\n" "fkt rs232 number\n" " - loopback plug(s) for X2 required\n" +#ifndef CONFIG_TQM5200S "fkt backlight on/off\n" " - switch backlight on or off\n" +#endif /* !CONFIG_TQM5200S */ ); #elif defined(CONFIG_FO300) U_BOOT_CMD( diff --git a/board/tqm5200/tqm5200.c b/board/tqm5200/tqm5200.c index 29d6f00427f..d10cb5937d6 100644 --- a/board/tqm5200/tqm5200.c +++ b/board/tqm5200/tqm5200.c @@ -543,6 +543,7 @@ int last_stage_init (void) __asm__ volatile ("sync"); } +#ifndef CONFIG_TQM5200S /* The TQM5200S has no SM501 grafic controller */ /* * Check for Grafic Controller */ @@ -586,6 +587,7 @@ int last_stage_init (void) #endif return 0; +#endif /* !CONFIG_TQM5200S */ } #ifdef CONFIG_VIDEO_SM501 -- cgit v1.2.3 From b31f64343ead9482cd439b1adbe4c34026a641b1 Mon Sep 17 00:00:00 2001 From: Martin Krause Date: Mon, 22 Oct 2007 16:45:53 +0200 Subject: TQM5200: fix spurious characters on second serial interface With this patch PSC3 is configured as UART. This is done, because if the pins of PSC3 are not configured at all (-> all pins are GPI), due to crosstalk, spurious characters may be send over the RX232_2_TXD signal line. Signed-off-by: Martin Krause --- include/configs/TQM5200.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/include/configs/TQM5200.h b/include/configs/TQM5200.h index d55340404d8..c3f16f524ef 100644 --- a/include/configs/TQM5200.h +++ b/include/configs/TQM5200.h @@ -547,7 +547,7 @@ # if defined (CONFIG_TQM5200_REV100) # error TQM5200 REV100 not supported on STK52XX REV200 or above # else/* TQM5200 REV200 and above */ -# define CFG_GPS_PORT_CONFIG 0x91500004 +# define CFG_GPS_PORT_CONFIG 0x91500404 # endif # endif #elif defined (CONFIG_FO300) -- cgit v1.2.3 From be4a87f11e297a5cededbf7dd71c0248f3874acd Mon Sep 17 00:00:00 2001 From: Martin Krause Date: Wed, 24 Oct 2007 08:41:27 +0200 Subject: TQM5200S: fix commands for STK52xx base board because of missing SM501 grafic controller Some commands for the STK52xx base board try to access the SM501 grafic controller. But the TQM5200S has no grafic controller (only the TQM5200 and the TQM5200B have). This patch deactivates the commands accessing the SM501 for the TQM5200S. Signed-off-by: Martin Krause Signed-off-by: Grant Likely --- board/tqm5200/cmd_stk52xx.c | 17 ++++++++++------- board/tqm5200/tqm5200.c | 2 ++ 2 files changed, 12 insertions(+), 7 deletions(-) diff --git a/board/tqm5200/cmd_stk52xx.c b/board/tqm5200/cmd_stk52xx.c index b746679afaa..27a6c4163de 100644 --- a/board/tqm5200/cmd_stk52xx.c +++ b/board/tqm5200/cmd_stk52xx.c @@ -561,7 +561,7 @@ void led_init(void) gpt->gpt6.emsr |= 0x00000024; gpt->gpt7.emsr |= 0x00000024; - +#ifndef CONFIG_TQM5200S /* enable SM501 GPIO control (in both power modes) */ *(vu_long *) (SM501_MMIO_BASE+SM501_POWER_MODE0_GATE) |= POWER_MODE_GATE_GPIO_PWM_I2C; @@ -574,6 +574,7 @@ void led_init(void) /* configure SM501 gpio pins 48-51 as output */ *(vu_long *) (SM501_MMIO_BASE+SM501_GPIO_DATA_DIR_HIGH) |= (0xF << 16); +#endif /* !CONFIG_TQM5200S */ } /* @@ -650,7 +651,7 @@ int do_led(char *argv[]) gpt->gpt7.emsr &= ~(1 << 4); } break; - +#ifndef CONFIG_TQM5200S case 24: if (strcmp (argv[3], "on") == 0) { *(vu_long *) (SM501_MMIO_BASE+SM501_GPIO_DATA_LOW) |= @@ -730,7 +731,7 @@ int do_led(char *argv[]) ~(0x1 << 19); } break; - +#endif /* !CONFIG_TQM5200S */ default: printf ("%s: invalid led number %s\n", __FUNCTION__, argv[2]); return 1; @@ -1110,7 +1111,7 @@ int do_rs232(char *argv[]) return error_status; } -#ifndef CONFIG_FO300 +#if !defined(CONFIG_FO300) && !defined(CONFIG_TQM5200S) static void sm501_backlight (unsigned int state) { if (state == BL_ON) { @@ -1120,7 +1121,7 @@ static void sm501_backlight (unsigned int state) *(vu_long *)(SM501_MMIO_BASE+SM501_PANEL_DISPLAY_CONTROL) &= ~((1 << 26) | (1 << 27)); } -#endif +#endif /* !CONFIG_FO300 & !CONFIG_TQM5200S */ int cmd_fkt(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) { @@ -1160,7 +1161,7 @@ int cmd_fkt(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) else printf ("Error\n"); return rcode; -#ifndef CONFIG_FO300 +#if !defined(CONFIG_FO300) && !defined(CONFIG_TQM5200S) } else if (strncmp (argv[1], "backlight", 4) == 0) { if (strncmp (argv[2], "on", 2) == 0) { sm501_backlight (BL_ON); @@ -1170,7 +1171,7 @@ int cmd_fkt(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) sm501_backlight (BL_OFF); return 0; } -#endif +#endif /* !CONFIG_FO300 & !CONFIG_TQM5200S */ } break; @@ -1228,8 +1229,10 @@ U_BOOT_CMD( " - loopback plug for X83 required\n" "fkt rs232 number\n" " - loopback plug(s) for X2 required\n" +#ifndef CONFIG_TQM5200S "fkt backlight on/off\n" " - switch backlight on or off\n" +#endif /* !CONFIG_TQM5200S */ ); #elif defined(CONFIG_FO300) U_BOOT_CMD( diff --git a/board/tqm5200/tqm5200.c b/board/tqm5200/tqm5200.c index 29d6f00427f..d10cb5937d6 100644 --- a/board/tqm5200/tqm5200.c +++ b/board/tqm5200/tqm5200.c @@ -543,6 +543,7 @@ int last_stage_init (void) __asm__ volatile ("sync"); } +#ifndef CONFIG_TQM5200S /* The TQM5200S has no SM501 grafic controller */ /* * Check for Grafic Controller */ @@ -586,6 +587,7 @@ int last_stage_init (void) #endif return 0; +#endif /* !CONFIG_TQM5200S */ } #ifdef CONFIG_VIDEO_SM501 -- cgit v1.2.3 From 1a0ce20aa4cb4e3068da04e7290ee9986fd0b834 Mon Sep 17 00:00:00 2001 From: Martin Krause Date: Wed, 24 Oct 2007 08:42:25 +0200 Subject: TQM5200: fix spurious characters on second serial interface With this patch PSC3 is configured as UART. This is done, because if the pins of PSC3 are not configured at all (-> all pins are GPI), due to crosstalk, spurious characters may be send over the RX232_2_TXD signal line. Signed-off-by: Martin Krause Signed-off-by: Grant Likely --- include/configs/TQM5200.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/include/configs/TQM5200.h b/include/configs/TQM5200.h index d55340404d8..c3f16f524ef 100644 --- a/include/configs/TQM5200.h +++ b/include/configs/TQM5200.h @@ -547,7 +547,7 @@ # if defined (CONFIG_TQM5200_REV100) # error TQM5200 REV100 not supported on STK52XX REV200 or above # else/* TQM5200 REV200 and above */ -# define CFG_GPS_PORT_CONFIG 0x91500004 +# define CFG_GPS_PORT_CONFIG 0x91500404 # endif # endif #elif defined (CONFIG_FO300) -- cgit v1.2.3 From d78791ae914d4e7c5edca1cdad73b3dc81a4eb82 Mon Sep 17 00:00:00 2001 From: Bartlomiej Sieka Date: Thu, 25 Oct 2007 17:20:01 +0200 Subject: TQM5200: increase kernel_addr_r and fdt_addr_r (hinted by Wolfgang Denk). Signed-off-by: Bartlomiej Sieka --- include/configs/TQM5200.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/include/configs/TQM5200.h b/include/configs/TQM5200.h index c3f16f524ef..7ecc275a1cd 100644 --- a/include/configs/TQM5200.h +++ b/include/configs/TQM5200.h @@ -257,8 +257,8 @@ "fdt_addr=FC0A0000\0" \ "kernel_addr=FC0C0000\0" \ "ramdisk_addr=FC300000\0" \ - "kernel_addr_r=200000\0" \ - "fdt_addr_r=400000\0" \ + "kernel_addr_r=400000\0" \ + "fdt_addr_r=600000\0" \ "rootpath=/opt/eldk/ppc_6xx\0" \ "ramargs=setenv bootargs root=/dev/ram rw\0" \ "nfsargs=setenv bootargs root=/dev/nfs rw " \ -- cgit v1.2.3 From 2acefa72ee0026f862ab65597ca687428f63a973 Mon Sep 17 00:00:00 2001 From: TsiChungLiew Date: Thu, 25 Oct 2007 17:09:17 -0500 Subject: ColdFire 5282: Fix external flash boot and return dramsize Signed-off-by: TsiChungLiew --- board/m5282evb/m5282evb.c | 1 + cpu/mcf52x2/start.S | 6 +++++- include/configs/M5282EVB.h | 2 +- 3 files changed, 7 insertions(+), 2 deletions(-) diff --git a/board/m5282evb/m5282evb.c b/board/m5282evb/m5282evb.c index 243d6a4d83e..7d6d1d6231a 100644 --- a/board/m5282evb/m5282evb.c +++ b/board/m5282evb/m5282evb.c @@ -89,4 +89,5 @@ long int initdram (int board_type) /* Write to the SDRAM Mode Register */ *(u32 *)(CFG_SDRAM_BASE + 0x400) = 0xA5A59696; } + return dramsize; } diff --git a/cpu/mcf52x2/start.S b/cpu/mcf52x2/start.S index 686e2a53330..260a09abf76 100644 --- a/cpu/mcf52x2/start.S +++ b/cpu/mcf52x2/start.S @@ -58,7 +58,7 @@ _vectors: .long 0x00000000 /* Flash offset is 0 until we setup CS0 */ #if defined(CONFIG_R5200) .long 0x400 -#elif defined(CONFIG_M5282) +#elif defined(CONFIG_M5282) && (TEXT_BASE == CFG_INT_FLASH_BASE) .long _start - TEXT_BASE #else .long _START @@ -177,7 +177,11 @@ _after_flashbar_copy: * therefore no VBR to set */ #if !defined(CONFIG_MONITOR_IS_IN_RAM) +#if defined(CONFIG_M5282) && (TEXT_BASE == CFG_INT_FLASH_BASE) + move.l #CFG_INT_FLASH_BASE, %d0 +#else move.l #CFG_FLASH_BASE, %d0 +#endif movec %d0, %VBR #endif diff --git a/include/configs/M5282EVB.h b/include/configs/M5282EVB.h index 3c17c1ea146..7bb9f60f765 100644 --- a/include/configs/M5282EVB.h +++ b/include/configs/M5282EVB.h @@ -163,7 +163,7 @@ * Please note that CFG_SDRAM_BASE _must_ start at 0 */ #define CFG_SDRAM_BASE 0x00000000 -#define CFG_SDRAM_SIZE 8 /* SDRAM size in MB */ +#define CFG_SDRAM_SIZE 16 /* SDRAM size in MB */ #define CFG_FLASH_BASE 0xffe00000 #define CFG_INT_FLASH_BASE 0xf0000000 #define CFG_INT_FLASH_ENABLE 0x21 -- cgit v1.2.3 From 95e9f2c212a65610b2e59a5c00d0113383a4da0b Mon Sep 17 00:00:00 2001 From: TsiChungLiew Date: Thu, 25 Oct 2007 17:10:23 -0500 Subject: ColdFire 5253: Assign correct SDRAM size Signed-off-by: TsiChungLiew --- include/configs/M5253EVBE.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/include/configs/M5253EVBE.h b/include/configs/M5253EVBE.h index 48170e7a35a..f5e1b646ca2 100644 --- a/include/configs/M5253EVBE.h +++ b/include/configs/M5253EVBE.h @@ -146,7 +146,7 @@ * Please note that CFG_SDRAM_BASE _must_ start at 0 */ #define CFG_SDRAM_BASE 0x00000000 -#define CFG_SDRAM_SIZE 16 /* SDRAM size in MB */ +#define CFG_SDRAM_SIZE 8 /* SDRAM size in MB */ #ifdef CONFIG_MONITOR_IS_IN_RAM #define CFG_MONITOR_BASE 0x20000 -- cgit v1.2.3 From c67e12e705b204cfe914e3e3e693d69a445dcabf Mon Sep 17 00:00:00 2001 From: TsiChungLiew Date: Thu, 25 Oct 2007 17:12:36 -0500 Subject: ColdFire 5329: Assign correct SDRAM size and fix cache Signed-off-by: TsiChungLiew --- cpu/mcf532x/start.S | 4 ++-- include/configs/M5329EVB.h | 2 +- 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/cpu/mcf532x/start.S b/cpu/mcf532x/start.S index 5cc1c87cdd0..61be2eac695 100644 --- a/cpu/mcf532x/start.S +++ b/cpu/mcf532x/start.S @@ -131,7 +131,7 @@ _start: movec %d0, %VBR move.l #(CFG_INIT_RAM_ADDR + CFG_INIT_RAM_CTRL), %d0 - movec %d0, %RAMBAR0 + movec %d0, %RAMBAR1 /* invalidate and disable cache */ move.l #0x01000000, %d0 /* Invalidate cache cmd */ @@ -268,7 +268,7 @@ _int_handler: icache_enable: move.l #0x01000000, %d0 /* Invalidate cache cmd */ movec %d0, %CACR /* Invalidate cache */ - move.l #(CFG_SDRAM_BASE + 0xc000 + ((CFG_SDRAM_SIZE & 0x1fe0) << 11)), %d0 + move.l #(CFG_SDRAM_BASE + 0x1c000), %d0 movec %d0, %ACR0 /* Enable cache */ move.l #0x80000200, %d0 /* Setup cache mask */ diff --git a/include/configs/M5329EVB.h b/include/configs/M5329EVB.h index d3b160505be..47d74a3c37a 100644 --- a/include/configs/M5329EVB.h +++ b/include/configs/M5329EVB.h @@ -175,7 +175,7 @@ * Please note that CFG_SDRAM_BASE _must_ start at 0 */ #define CFG_SDRAM_BASE 0x40000000 -#define CFG_SDRAM_SIZE 16 /* SDRAM size in MB */ +#define CFG_SDRAM_SIZE 32 /* SDRAM size in MB */ #define CFG_SDRAM_CFG1 0x53722730 #define CFG_SDRAM_CFG2 0x56670000 #define CFG_SDRAM_CTRL 0xE1092000 -- cgit v1.2.3 From 688e8eb414ac111cca7ce60bdf30e805ab9a7bcb Mon Sep 17 00:00:00 2001 From: TsiChungLiew Date: Thu, 25 Oct 2007 17:14:00 -0500 Subject: ColdFire: Fix build error when CONFIG_WATCHDOG is defined Signed-off-by: TsiChungLiew --- lib_m68k/m68k_linux.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/lib_m68k/m68k_linux.c b/lib_m68k/m68k_linux.c index bea97441b14..cc974c2d60d 100644 --- a/lib_m68k/m68k_linux.c +++ b/lib_m68k/m68k_linux.c @@ -26,6 +26,7 @@ #include #include #include +#include #include #include @@ -36,6 +37,8 @@ DECLARE_GLOBAL_DATA_PTR; #define LINUX_MAX_ENVS 256 #define LINUX_MAX_ARGS 256 +#define CHUNKSZ (64 * 1024) + #ifdef CONFIG_SHOW_BOOT_PROGRESS # include # define SHOW_BOOT_PROGRESS(arg) show_boot_progress(arg) -- cgit v1.2.3 From e8ee8f3ade2a06c1893dd5e68f223070d650c7ed Mon Sep 17 00:00:00 2001 From: TsiChungLiew Date: Thu, 25 Oct 2007 17:16:22 -0500 Subject: ColdFire 54455: Fix correct boot location for atmel and intel Signed-off-by: TsiChungLiew --- Makefile | 4 ++++ board/freescale/m54455evb/config.mk | 4 +++- include/configs/M54455EVB.h | 36 ++++++++++++++++++++---------------- 3 files changed, 27 insertions(+), 17 deletions(-) diff --git a/Makefile b/Makefile index ce7b07f9d18..850c68e235c 100644 --- a/Makefile +++ b/Makefile @@ -1733,9 +1733,13 @@ M54455EVB_i66_config : unconfig >include/config.h ; \ if [ "$${FLASH}" == "INTEL" ] ; then \ echo "#undef CFG_ATMEL_BOOT" >> $(obj)include/config.h ; \ + echo "TEXT_BASE = 0x00000000" > $(obj)board/freescale/m54455evb/config.tmp ; \ + cp $(obj)board/freescale/m54455evb/u-boot.int $(obj)board/freescale/m54455evb/u-boot.lds ; \ echo "... with INTEL boot..." ; \ else \ echo "#define CFG_ATMEL_BOOT" >> $(obj)include/config.h ; \ + echo "TEXT_BASE = 0x04000000" > $(obj)board/freescale/m54455evb/config.tmp ; \ + cp $(obj)board/freescale/m54455evb/u-boot.atm $(obj)board/freescale/m54455evb/u-boot.lds ; \ echo "... with ATMEL boot..." ; \ fi; \ echo "#define CFG_INPUT_CLKSRC $${FREQ}" >> $(obj)include/config.h ; \ diff --git a/board/freescale/m54455evb/config.mk b/board/freescale/m54455evb/config.mk index ce014edca8f..b42fcc94ce7 100644 --- a/board/freescale/m54455evb/config.mk +++ b/board/freescale/m54455evb/config.mk @@ -22,4 +22,6 @@ # MA 02111-1307 USA # -TEXT_BASE = 0 +sinclude $(OBJTREE)/board/$(BOARDDIR)/config.tmp + +PLATFORM_CPPFLAGS += -DTEXT_BASE=$(TEXT_BASE) diff --git a/include/configs/M54455EVB.h b/include/configs/M54455EVB.h index 6f4859c2380..ba050cb7e46 100644 --- a/include/configs/M54455EVB.h +++ b/include/configs/M54455EVB.h @@ -27,8 +27,8 @@ * board/config.h - configuration options, board specific */ -#ifndef _JAMICA54455_H -#define _JAMICA54455_H +#ifndef _M54455EVB_H +#define _M54455EVB_H /* * High Level Configuration Options @@ -75,7 +75,7 @@ #define CONFIG_CMD_MISC #define CONFIG_CMD_MII #define CONFIG_CMD_NET -#define CONFIG_CMD_PCI +#undef CONFIG_CMD_PCI #define CONFIG_CMD_PING #define CONFIG_CMD_REGINFO @@ -129,8 +129,8 @@ "u-boot=u-boot.bin\0" \ "load=tftp ${loadaddr) ${u-boot}\0" \ "upd=run load; run prog\0" \ - "prog=prot off 0 2ffff;" \ - "era 0 2ffff;" \ + "prog=prot off 4000000 402ffff;" \ + "era 4000000 402ffff;" \ "cp.b ${loadaddr} 0 ${filesize};" \ "save\0" \ "" @@ -174,6 +174,7 @@ #define CFG_IMMR CFG_MBAR /* PCI */ +#ifdef CONFIG_CMD_PCI #define CONFIG_PCI 1 #define CFG_PCI_MEM_BUS 0xA0000000 @@ -187,6 +188,7 @@ #define CFG_PCI_CFG_BUS 0xB0000000 #define CFG_PCI_CFG_PHYS CFG_PCI_CFG_BUS #define CFG_PCI_CFG_SIZE 0x01000000 +#endif /* FPGA - Spartan 2 */ /* experiment @@ -268,8 +270,6 @@ /* Configuration for environment * Environment is embedded in u-boot in the second sector of the flash */ -#define CFG_ENV_OFFSET 0x4000 -#define CFG_ENV_SECT_SIZE 0x2000 #define CFG_ENV_IS_IN_FLASH 1 #define CONFIG_ENV_OVERWRITE 1 #undef CFG_ENV_IS_EMBEDDED @@ -278,13 +278,17 @@ * FLASH organization */ #ifdef CFG_ATMEL_BOOT -# define CFG_FLASH_BASE 0 +# define CFG_FLASH_BASE CFG_CS0_BASE # define CFG_FLASH0_BASE CFG_CS0_BASE # define CFG_FLASH1_BASE CFG_CS1_BASE +# define CFG_ENV_ADDR (CFG_FLASH_BASE + 0x4000) +# define CFG_ENV_SECT_SIZE 0x2000 #else # define CFG_FLASH_BASE CFG_FLASH0_BASE # define CFG_FLASH0_BASE CFG_CS1_BASE # define CFG_FLASH1_BASE CFG_CS0_BASE +# define CFG_ENV_ADDR (CFG_FLASH_BASE + 0x60000) +# define CFG_ENV_SECT_SIZE 0x20000 #endif /* M54455EVB has one non CFI flash, defined CFG_FLASH_CFI will cause the system @@ -328,9 +332,9 @@ * NOTE: Enable CONFIG_CMD_JFFS2 for JFFS2 support. */ #ifdef CFG_ATMEL_BOOT -# define CONFIG_JFFS2_DEV "nor0" +# define CONFIG_JFFS2_DEV "nor1" # define CONFIG_JFFS2_PART_SIZE 0x01000000 -# define CONFIG_JFFS2_PART_OFFSET CFG_FLASH1_BASE +# define CONFIG_JFFS2_PART_OFFSET (CFG_FLASH1_BASE + 0x500000) #else # define CONFIG_JFFS2_DEV "nor0" # define CONFIG_JFFS2_PART_SIZE (0x01000000 - 0x500000) @@ -356,20 +360,20 @@ #ifdef CFG_ATMEL_BOOT /* Atmel Flash */ -#define CFG_CS0_BASE 0 +#define CFG_CS0_BASE 0x04000000 #define CFG_CS0_MASK 0x00070001 #define CFG_CS0_CTRL 0x00001140 /* Intel Flash */ -#define CFG_CS1_BASE 0x04000000 +#define CFG_CS1_BASE 0x00000000 #define CFG_CS1_MASK 0x01FF0001 -#define CFG_CS1_CTRL 0x003F3D60 +#define CFG_CS1_CTRL 0x00000D60 #define CFG_ATMEL_BASE CFG_CS0_BASE #else /* Intel Flash */ -#define CFG_CS0_BASE 0 +#define CFG_CS0_BASE 0x00000000 #define CFG_CS0_MASK 0x01FF0001 -#define CFG_CS0_CTRL 0x003F3D60 +#define CFG_CS0_CTRL 0x00000D60 /* Atmel Flash */ #define CFG_CS1_BASE 0x04000000 #define CFG_CS1_MASK 0x00070001 @@ -388,4 +392,4 @@ #define CFG_CS3_MASK 0x00070001 #define CFG_CS3_CTRL 0x00000020 -#endif /* _JAMICA54455_H */ +#endif /* _M54455EVB_H */ -- cgit v1.2.3 From e5c794e491a57d829b6d8733e2ed8368a2269abf Mon Sep 17 00:00:00 2001 From: Justin Flammia Date: Mon, 29 Oct 2007 17:40:35 -0400 Subject: DHCP Client Fix This is a multi-part message in MIME format. commit e6e505eae94ed721e123e177489291fc4544b7b8 Author: Justin Flammia Date: Mon Oct 29 17:19:03 2007 -0400 Found a bug in the way the DHCP Request packet is built, where the IP address that is offered by the server is bound to prematurely. This patch is a fix of that bug where the IP address offered by the DHCP server is not used until after the DHCP ACK from the server is received. Signed-off-by: Justin Flammia Signed-off-by: Ben Warren --- net/bootp.c | 11 +++++++---- 1 file changed, 7 insertions(+), 4 deletions(-) diff --git a/net/bootp.c b/net/bootp.c index 749d3e5e0c2..cfe6f8dd6b9 100644 --- a/net/bootp.c +++ b/net/bootp.c @@ -850,9 +850,9 @@ static void DhcpSendRequestPkt(Bootp_t *bp_offer) bp->bp_hlen = HWL_ETHER; bp->bp_hops = 0; bp->bp_secs = htons(get_timer(0) / CFG_HZ); - NetCopyIP(&bp->bp_ciaddr, &bp_offer->bp_ciaddr); /* both in network byte order */ - NetCopyIP(&bp->bp_yiaddr, &bp_offer->bp_yiaddr); - NetCopyIP(&bp->bp_siaddr, &bp_offer->bp_siaddr); + /* Do not set the client IP, your IP, or server IP yet, since it hasn't been ACK'ed by + * the server yet */ + /* * RFC3046 requires Relay Agents to discard packets with * nonzero and offered giaddr @@ -870,7 +870,9 @@ static void DhcpSendRequestPkt(Bootp_t *bp_offer) /* * Copy options from OFFER packet if present */ - NetCopyIP(&OfferedIP, &bp->bp_yiaddr); + + /* Copy offered IP into the parameters request list */ + NetCopyIP(&OfferedIP, &bp_offer->bp_yiaddr); extlen = DhcpExtended((u8 *)bp->bp_vend, DHCP_REQUEST, NetDHCPServerIP, OfferedIP); pktlen = BOOTP_SIZE - sizeof(bp->bp_vend) + extlen; @@ -980,3 +982,4 @@ void DhcpRequest(void) #endif #endif + -- cgit v1.2.3 From 8b6684a698500be9c142ec2c9f46cfc348e17f0c Mon Sep 17 00:00:00 2001 From: Haavard Skinnemoen Date: Wed, 24 Oct 2007 15:48:37 +0200 Subject: ATSTK1002: Remove default ethernet addresses Wolfgang is right: It's not a good idea to set up default initial ethernet addresses for a board, even though they belong to the local range. This will change the failure mode from "IT manager screams at you for using duplicate ethernet addresses" to a nice error message explaining that the ethernet address hasn't been set properly. Signed-off-by: Haavard Skinnemoen --- include/configs/atstk1002.h | 11 +++-------- 1 file changed, 3 insertions(+), 8 deletions(-) diff --git a/include/configs/atstk1002.h b/include/configs/atstk1002.h index 1809fc5d864..b33e26fe011 100644 --- a/include/configs/atstk1002.h +++ b/include/configs/atstk1002.h @@ -114,15 +114,10 @@ #define CONFIG_AUTOBOOT_STOP_STR " " /* - * These are "locally administered ethernet addresses" generated by - * ./tools/gen_eth_addr - * - * After booting the board for the first time, new addresses should be - * generated and assigned to the environment variables "ethaddr" and - * "eth1addr". + * After booting the board for the first time, new ethernet addresses + * should be generated and assigned to the environment variables + * "ethaddr" and "eth1addr". This is normally done during production. */ -#define CONFIG_ETHADDR 6a:87:71:14:cd:cb -#define CONFIG_ETH1ADDR ca:f8:15:e6:3e:e6 #define CONFIG_OVERWRITE_ETHADDR_ONCE 1 #define CONFIG_NET_MULTI 1 -- cgit v1.2.3