From 11d5655919ab94f4452f45f1a1b38a6a30030705 Mon Sep 17 00:00:00 2001 From: Pratyush Yadav Date: Tue, 4 Jun 2024 11:39:10 +0530 Subject: mtd: spi-nor-core: Do not start or end writes at odd address in DTR mode On DTR capable flashes like Micron Xcella the writes cannot start or end at an odd address in DTR mode. Extra 0xff bytes need to be prepended or appended respectively to make sure both the start and end addresses are even. Signed-off-by: Pratyush Yadav Signed-off-by: Apurva Nandan Signed-off-by: Vignesh Raghavendra Tested-by: Jonathan Humphreys Signed-off-by: Manorit Chawdhry --- drivers/mtd/spi/spi-nor-core.c | 59 +++++++++++++++++++++++++++++++++++++++--- 1 file changed, 55 insertions(+), 4 deletions(-) diff --git a/drivers/mtd/spi/spi-nor-core.c b/drivers/mtd/spi/spi-nor-core.c index 982dd251150..aea611fef52 100644 --- a/drivers/mtd/spi/spi-nor-core.c +++ b/drivers/mtd/spi/spi-nor-core.c @@ -1804,11 +1804,62 @@ static int spi_nor_write(struct mtd_info *mtd, loff_t to, size_t len, if (ret < 0) return ret; #endif + write_enable(nor); - ret = nor->write(nor, addr, page_remain, buf + i); - if (ret < 0) - goto write_err; - written = ret; + + /* + * On DTR capable flashes like Micron Xcella the writes cannot + * start or end at an odd address in DTR mode. So we need to + * append or prepend extra 0xff bytes to make sure the start + * address and end address are even. + */ + if (spi_nor_protocol_is_dtr(nor->write_proto) && + ((addr | page_remain) & 1)) { + u_char *tmp; + size_t extra_bytes = 0; + + tmp = kmalloc(nor->page_size, 0); + if (!tmp) { + ret = -ENOMEM; + goto write_err; + } + + /* Prepend a 0xff byte if the start address is odd. */ + if (addr & 1) { + tmp[0] = 0xff; + memcpy(tmp + 1, buf + i, page_remain); + addr--; + page_remain++; + extra_bytes++; + } else { + memcpy(tmp, buf + i, page_remain); + } + + /* Append a 0xff byte if the end address is odd. */ + if ((addr + page_remain) & 1) { + tmp[page_remain + extra_bytes] = 0xff; + extra_bytes++; + page_remain++; + } + + ret = nor->write(nor, addr, page_remain, tmp); + + kfree(tmp); + + if (ret < 0) + goto write_err; + + /* + * We write extra bytes but they are not part of the + * original write. + */ + written = ret - extra_bytes; + } else { + ret = nor->write(nor, addr, page_remain, buf + i); + if (ret < 0) + goto write_err; + written = ret; + } ret = spi_nor_wait_till_ready(nor); if (ret) -- cgit v1.3.1 From 512863ecfead05c407b620a205fd4ffb64f03357 Mon Sep 17 00:00:00 2001 From: Manorit Chawdhry Date: Tue, 4 Jun 2024 11:39:11 +0530 Subject: arch: arm: dts: k3-j721s2-r5: Override ospi and fss for 32-bit mode R5 being a 32-bit processor can't understand the 64-bit mapping being done in ospi node. Override the ospi node for 32-bit register ranges and the fss node ( the parent node of ospi ) to map the ranges for the updated child node correctly. Reviewed-by: Apurva Nandan Signed-off-by: Manorit Chawdhry --- arch/arm/dts/k3-j721s2-r5.dtsi | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/arch/arm/dts/k3-j721s2-r5.dtsi b/arch/arm/dts/k3-j721s2-r5.dtsi index eb0df42583a..dbea6b9d011 100644 --- a/arch/arm/dts/k3-j721s2-r5.dtsi +++ b/arch/arm/dts/k3-j721s2-r5.dtsi @@ -79,3 +79,16 @@ &mcu_udmap { ti,sci = <&dm_tifs>; }; + +&ospi0 { + reg = <0x0 0x47040000 0x0 0x100>, + <0x0 0x50000000 0x0 0x8000000>; +}; + +&fss { + /* fss node has 64 bit address regions mapped to it and since the ospi + * nodes is being override, override the fss node ranges as well + */ + ranges = <0x0 0x47000000 0x0 0x47000000 0x0 0x00068400>, + <0x0 0x50000000 0x0 0x50000000 0x0 0x08000000>; +}; -- cgit v1.3.1 From 595dbb44aac27c9b1affdac8bb77c31b733d9efb Mon Sep 17 00:00:00 2001 From: Manorit Chawdhry Date: Tue, 4 Jun 2024 11:39:12 +0530 Subject: arch: arm: dts: k3-j721s2-*-u-boot.dtsi: Enable the ospi0 node Enable ospi0 node for all boot stages Reviewed-by: Apurva Nandan Signed-off-by: Manorit Chawdhry --- arch/arm/dts/k3-j721s2-common-proc-board-u-boot.dtsi | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/arch/arm/dts/k3-j721s2-common-proc-board-u-boot.dtsi b/arch/arm/dts/k3-j721s2-common-proc-board-u-boot.dtsi index 91a82b3b7ca..54eb9b4072c 100644 --- a/arch/arm/dts/k3-j721s2-common-proc-board-u-boot.dtsi +++ b/arch/arm/dts/k3-j721s2-common-proc-board-u-boot.dtsi @@ -102,7 +102,9 @@ }; &ospi0 { - status = "disabled"; + flash@0 { + bootph-all; + }; }; &ospi1 { -- cgit v1.3.1 From 1c86db01fb10de8983e47582d460a0733c592898 Mon Sep 17 00:00:00 2001 From: Manorit Chawdhry Date: Tue, 4 Jun 2024 11:39:13 +0530 Subject: configs: j721s2_evm_*_defconfig: Enable OSPI configs Enable OSPI related configs to boot using OSPI Reviewed-by: Apurva Nandan Signed-off-by: Manorit Chawdhry --- configs/j721s2_evm_a72_defconfig | 1 + configs/j721s2_evm_r5_defconfig | 1 + 2 files changed, 2 insertions(+) diff --git a/configs/j721s2_evm_a72_defconfig b/configs/j721s2_evm_a72_defconfig index 5ed8d00662e..5c3b52baaee 100644 --- a/configs/j721s2_evm_a72_defconfig +++ b/configs/j721s2_evm_a72_defconfig @@ -10,6 +10,7 @@ CONFIG_SOC_K3_J721S2=y CONFIG_TARGET_J721S2_A72_EVM=y CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x80480000 +CONFIG_SF_DEFAULT_SPEED=25000000 CONFIG_ENV_SIZE=0x20000 CONFIG_DM_GPIO=y CONFIG_SPL_DM_SPI=y diff --git a/configs/j721s2_evm_r5_defconfig b/configs/j721s2_evm_r5_defconfig index 3c958cafbe8..7413ddd0810 100644 --- a/configs/j721s2_evm_r5_defconfig +++ b/configs/j721s2_evm_r5_defconfig @@ -10,6 +10,7 @@ CONFIG_K3_EARLY_CONS=y CONFIG_TARGET_J721S2_R5_EVM=y CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x41c76000 +CONFIG_SF_DEFAULT_SPEED=25000000 CONFIG_ENV_SIZE=0x20000 CONFIG_DM_GPIO=y CONFIG_SPL_DM_SPI=y -- cgit v1.3.1