From a4dcf3183ff04321bea3a1ab2054e40cda2f672f Mon Sep 17 00:00:00 2001 From: Quentin Schulz Date: Wed, 30 Jul 2025 14:46:33 +0200 Subject: board: theobroma-systems: update instructions for newer Rockchip rkbin The instructions are regularly out of date because the generated or prebuilt binaries are updated and the filename doesn't match our instructions anymore. Additionally, since commit 55a95caaef15 ("tools: ddrbin_tool: add ddrbin_tool.py and update to v1.21 20241211") end of October 2024, ddrbin_tool doesn't exist anymore and has been replaced by ddrbin_tool.py python script (which currently isn't an executable) so let's update these instructions as well. Signed-off-by: Quentin Schulz Reviewed-by: Kever Yang --- doc/board/theobroma-systems/jaguar_rk3588.rst | 9 ++++----- doc/board/theobroma-systems/puma_rk3399.rst | 6 ++++-- doc/board/theobroma-systems/ringneck_px30.rst | 3 ++- doc/board/theobroma-systems/tiger_rk3588.rst | 9 ++++----- 4 files changed, 14 insertions(+), 13 deletions(-) diff --git a/doc/board/theobroma-systems/jaguar_rk3588.rst b/doc/board/theobroma-systems/jaguar_rk3588.rst index cba4fd066ab..33cd7276852 100644 --- a/doc/board/theobroma-systems/jaguar_rk3588.rst +++ b/doc/board/theobroma-systems/jaguar_rk3588.rst @@ -39,13 +39,12 @@ Get the TF-A and DDR init (TPL) binaries git clone https://github.com/rockchip-linux/rkbin cd rkbin - export RKBIN=$(pwd) - export BL31=$RKBIN/bin/rk35/rk3588_bl31_v1.47.elf - export ROCKCHIP_TPL=$RKBIN/bin/rk35/rk3588_ddr_lp4_2112MHz_lp5_2400MHz_v1.18.bin + export BL31=$(readlink -f bin/rk35/rk3588_bl31_v*.elf | head -1) + export ROCKCHIP_TPL=$(readlink -f bin/rk35/rk3588_ddr_lp4_2112MHz_lp5_2400MHz_v*.bin | head -1) sed -i 's/^uart baudrate=.*$/uart baudrate=115200/' tools/ddrbin_param.txt - ./tools/ddrbin_tool rk3588 tools/ddrbin_param.txt "$ROCKCHIP_TPL" + python3 ./tools/ddrbin_tool.py rk3588 tools/ddrbin_param.txt "$ROCKCHIP_TPL" ./tools/boot_merger RKBOOT/RK3588MINIALL.ini - export RKDB=$RKBIN/rk3588_spl_loader_v1.11.112.bin + export RKDB=$(readlink -f rk3588_spl_loader_v*.bin | head -1) This will setup all required external dependencies for compiling U-Boot. This will be updated in the future once upstream Trusted-Firmware-A supports RK3588 or U-Boot diff --git a/doc/board/theobroma-systems/puma_rk3399.rst b/doc/board/theobroma-systems/puma_rk3399.rst index a2a5e7bca4b..1a8d33f188d 100644 --- a/doc/board/theobroma-systems/puma_rk3399.rst +++ b/doc/board/theobroma-systems/puma_rk3399.rst @@ -95,8 +95,9 @@ To flash U-Boot on the eMMC with ``rkdeveloptool``: git clone https://github.com/rockchip-linux/rkbin.git cd rkbin ./tools/boot_merger RKBOOT/RK3399MINIALL.ini + export RKDB=$(readlink -f rk3399_loader_v*.bin | head -1) cd .. - ./rkdeveloptool db rkbin/rk3399_loader_v1.30.130.bin + ./rkdeveloptool db "$RKDB" ./rkdeveloptool wl 64 ../u-boot-rockchip.bin NOR-Flash @@ -121,7 +122,8 @@ To flash U-Boot on the SPI with ``rkdeveloptool``: git clone https://github.com/rockchip-linux/rkbin.git cd rkbin ./tools/boot_merger RKBOOT/RK3399MINIALL_SPINOR.ini + export RKDB=$(readlink -f rk3399_loader_spinor_v*.bin | head -1) cd .. - ./rkdeveloptool db rkbin/rk3399_loader_spinor_v1.30.114.bin + ./rkdeveloptool db "$RKDB" ./rkdeveloptool ef ./rkdeveloptool wl 0 ../u-boot-rockchip-spi.bin diff --git a/doc/board/theobroma-systems/ringneck_px30.rst b/doc/board/theobroma-systems/ringneck_px30.rst index c16b9ed17ed..d3feedf6062 100644 --- a/doc/board/theobroma-systems/ringneck_px30.rst +++ b/doc/board/theobroma-systems/ringneck_px30.rst @@ -90,6 +90,7 @@ To flash U-Boot on the eMMC with ``rkdeveloptool``: git clone https://github.com/rockchip-linux/rkbin.git cd rkbin ./tools/boot_merger RKBOOT/PX30MINIALL.ini + export RKDB=$(readlink -f px30_loader_v*.bin | head -1) cd .. - ./rkdeveloptool db rkbin/px30_loader_v2.08.135.bin + ./rkdeveloptool db "$RKDB" ./rkdeveloptool wl 64 ../u-boot-rockchip.bin diff --git a/doc/board/theobroma-systems/tiger_rk3588.rst b/doc/board/theobroma-systems/tiger_rk3588.rst index 4586b8d8b5a..71dbe4c59de 100644 --- a/doc/board/theobroma-systems/tiger_rk3588.rst +++ b/doc/board/theobroma-systems/tiger_rk3588.rst @@ -46,14 +46,13 @@ Get the TF-A and DDR init (TPL) binaries git clone https://github.com/rockchip-linux/rkbin cd rkbin - export RKBIN=$(pwd) - export BL31=$RKBIN/bin/rk35/rk3588_bl31_v1.47.elf - export ROCKCHIP_TPL=$RKBIN/bin/rk35/rk3588_ddr_lp4_2112MHz_lp5_2400MHz_v1.18.bin + export BL31=$(readlink -f bin/rk35/rk3588_bl31_v*.elf | head -1) + export ROCKCHIP_TPL=$(readlink -f bin/rk35/rk3588_ddr_lp4_2112MHz_lp5_2400MHz_v*.bin | head -1) sed -i 's/^uart baudrate=.*$/uart baudrate=115200/' tools/ddrbin_param.txt sed -i 's/^uart iomux=.*$/uart iomux=2/' tools/ddrbin_param.txt - ./tools/ddrbin_tool rk3588 tools/ddrbin_param.txt "$ROCKCHIP_TPL" + python3 ./tools/ddrbin_tool.py rk3588 tools/ddrbin_param.txt "$ROCKCHIP_TPL" ./tools/boot_merger RKBOOT/RK3588MINIALL.ini - export RKDB=$RKBIN/rk3588_spl_loader_v1.11.112.bin + export RKDB=$(readlink -f rk3588_spl_loader_v*.bin | head -1) This will setup all required external dependencies for compiling U-Boot. This will be updated in the future once upstream Trusted-Firmware-A supports RK3588 or U-Boot -- cgit v1.2.3 From 1bea4284b0f0a5722bb1b6fec4baa096cb808bc4 Mon Sep 17 00:00:00 2001 From: Quentin Schulz Date: Wed, 30 Jul 2025 14:46:34 +0200 Subject: board: theobroma-systems: add instructions for how to use upstream TF-A Upstream TF-A has support for RK3588 since v2.12 so let's document how to use upstream TF-A instead of the prebuilt binary blob from Rockchip if one wants to do that. Signed-off-by: Quentin Schulz Reviewed-by: Kever Yang --- doc/board/theobroma-systems/jaguar_rk3588.rst | 38 +++++++++++++++++++++++---- doc/board/theobroma-systems/tiger_rk3588.rst | 38 +++++++++++++++++++++++---- 2 files changed, 66 insertions(+), 10 deletions(-) diff --git a/doc/board/theobroma-systems/jaguar_rk3588.rst b/doc/board/theobroma-systems/jaguar_rk3588.rst index 33cd7276852..eff0ee7347c 100644 --- a/doc/board/theobroma-systems/jaguar_rk3588.rst +++ b/doc/board/theobroma-systems/jaguar_rk3588.rst @@ -32,14 +32,13 @@ It provides the following features: Here is the step-by-step to boot to U-Boot on SBC-RK3588-AMR Jaguar from Theobroma Systems. -Get the TF-A and DDR init (TPL) binaries ----------------------------------------- +Get DDR init (TPL) binary +------------------------- .. prompt:: bash git clone https://github.com/rockchip-linux/rkbin cd rkbin - export BL31=$(readlink -f bin/rk35/rk3588_bl31_v*.elf | head -1) export ROCKCHIP_TPL=$(readlink -f bin/rk35/rk3588_ddr_lp4_2112MHz_lp5_2400MHz_v*.bin | head -1) sed -i 's/^uart baudrate=.*$/uart baudrate=115200/' tools/ddrbin_param.txt python3 ./tools/ddrbin_tool.py rk3588 tools/ddrbin_param.txt "$ROCKCHIP_TPL" @@ -47,8 +46,32 @@ Get the TF-A and DDR init (TPL) binaries export RKDB=$(readlink -f rk3588_spl_loader_v*.bin | head -1) This will setup all required external dependencies for compiling U-Boot. This will -be updated in the future once upstream Trusted-Firmware-A supports RK3588 or U-Boot -gains support for open-source DRAM initialization in TPL. +be updated in the future once U-Boot gains support for open-source DRAM initialization +in TPL. + +Get TF-A +-------- + +There are two possible options, pick one or the other. Note that the instructions need +to be run from the ``rkbin`` directory. + +Prebuilt binary from Rockchip +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +.. prompt:: bash + + export BL31=$(readlink -f bin/rk35/rk3588_bl31_v*.elf | head -1) + +Upstream +~~~~~~~~ + +.. prompt:: bash + + cd ../ + git clone https://git.trustedfirmware.org/TF-A/trusted-firmware-a.git + cd trusted-firmware-a + make CROSS_COMPILE=aarch64-linux-gnu- PLAT=rk3588 bl31 + export BL31=$PWD/build/rk3588/release/bl31/bl31.elf Build U-Boot ------------ @@ -58,6 +81,11 @@ Build U-Boot cd ../u-boot make CROSS_COMPILE=aarch64-linux-gnu- jaguar-rk3588_defconfig all +.. note:: + If using upstream TF-A, one should disable ``SPL_ATF_NO_PLATFORM_PARAM`` symbol in + U-Boot config (via e.g. ``make CROSS_COMPILE=aarch64-linux-gnu- menuconfig``) which + will, among other things, enable console output in TF-A. + This will build ``u-boot-rockchip.bin`` which can be written to an MMC device (eMMC or SD card). diff --git a/doc/board/theobroma-systems/tiger_rk3588.rst b/doc/board/theobroma-systems/tiger_rk3588.rst index 71dbe4c59de..493f191020f 100644 --- a/doc/board/theobroma-systems/tiger_rk3588.rst +++ b/doc/board/theobroma-systems/tiger_rk3588.rst @@ -39,14 +39,13 @@ It provides the following feature set: Here is the step-by-step to boot to U-Boot on SOM-RK3588-Q7 Tiger from Theobroma Systems. -Get the TF-A and DDR init (TPL) binaries ----------------------------------------- +Get DDR init (TPL) binary +------------------------- .. prompt:: bash git clone https://github.com/rockchip-linux/rkbin cd rkbin - export BL31=$(readlink -f bin/rk35/rk3588_bl31_v*.elf | head -1) export ROCKCHIP_TPL=$(readlink -f bin/rk35/rk3588_ddr_lp4_2112MHz_lp5_2400MHz_v*.bin | head -1) sed -i 's/^uart baudrate=.*$/uart baudrate=115200/' tools/ddrbin_param.txt sed -i 's/^uart iomux=.*$/uart iomux=2/' tools/ddrbin_param.txt @@ -55,8 +54,32 @@ Get the TF-A and DDR init (TPL) binaries export RKDB=$(readlink -f rk3588_spl_loader_v*.bin | head -1) This will setup all required external dependencies for compiling U-Boot. This will -be updated in the future once upstream Trusted-Firmware-A supports RK3588 or U-Boot -gains support for open-source DRAM initialization in TPL. +be updated in the future once U-Boot gains support for open-source DRAM initialization +in TPL. + +Get TF-A +-------- + +There are two possible options, pick one or the other. Note that the instructions need +to be run from the ``rkbin`` directory. + +Prebuilt binary from Rockchip +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +.. prompt:: bash + + export BL31=$(readlink -f bin/rk35/rk3588_bl31_v*.elf | head -1) + +Upstream +~~~~~~~~ + +.. prompt:: bash + + cd ../ + git clone https://git.trustedfirmware.org/TF-A/trusted-firmware-a.git + cd trusted-firmware-a + make CROSS_COMPILE=aarch64-linux-gnu- PLAT=rk3588 bl31 + export BL31=$PWD/build/rk3588/release/bl31/bl31.elf Build U-Boot ------------ @@ -66,6 +89,11 @@ Build U-Boot cd ../u-boot make CROSS_COMPILE=aarch64-linux-gnu- tiger-rk3588_defconfig all +.. note:: + If using upstream TF-A, one should disable ``SPL_ATF_NO_PLATFORM_PARAM`` symbol in + U-Boot config (via e.g. ``make CROSS_COMPILE=aarch64-linux-gnu- menuconfig``) which + will, among other things, enable console output in TF-A. + This will build ``u-boot-rockchip.bin`` which can be written to an MMC device (eMMC or SD card). -- cgit v1.2.3 From b3a141846b05f00e8f2654d888a2e2cd7d11b40d Mon Sep 17 00:00:00 2001 From: Quentin Schulz Date: Wed, 30 Jul 2025 14:46:35 +0200 Subject: board: theobroma-systems: jaguar_rk3588: explicit UART IOMUX When one attempts to build Tiger and Jaguar from the same directory, because Tiger will set the IOMUX to 2 but Jaguar doesn't reset it, Jaguar will have IOMUX set to 2 if built after Tiger. This isn't an issue if in separate directories or building Tiger after Jaguar because the default if missing from the configuration file is 0. Let's make it explicit that the iomux is 0 for Jaguar. Signed-off-by: Quentin Schulz Reviewed-by: Kever Yang --- doc/board/theobroma-systems/jaguar_rk3588.rst | 1 + 1 file changed, 1 insertion(+) diff --git a/doc/board/theobroma-systems/jaguar_rk3588.rst b/doc/board/theobroma-systems/jaguar_rk3588.rst index eff0ee7347c..d09cfaa88ff 100644 --- a/doc/board/theobroma-systems/jaguar_rk3588.rst +++ b/doc/board/theobroma-systems/jaguar_rk3588.rst @@ -41,6 +41,7 @@ Get DDR init (TPL) binary cd rkbin export ROCKCHIP_TPL=$(readlink -f bin/rk35/rk3588_ddr_lp4_2112MHz_lp5_2400MHz_v*.bin | head -1) sed -i 's/^uart baudrate=.*$/uart baudrate=115200/' tools/ddrbin_param.txt + sed -i 's/^uart iomux=.*$/uart iomux=0/' tools/ddrbin_param.txt python3 ./tools/ddrbin_tool.py rk3588 tools/ddrbin_param.txt "$ROCKCHIP_TPL" ./tools/boot_merger RKBOOT/RK3588MINIALL.ini export RKDB=$(readlink -f rk3588_spl_loader_v*.bin | head -1) -- cgit v1.2.3 From b57363a2b9b6bbc6a4fa63d93681485b812ccc51 Mon Sep 17 00:00:00 2001 From: Jonas Karlman Date: Sat, 2 Aug 2025 22:07:22 +0000 Subject: rockchip: Move TEXT_BASE to 8 MiB offset from start of DRAM Drop SoC specific TEXT_BASE and use a common TEXT_BASE for all SoCs. Move the common TEXT_BASE to 8 MiB offset from start of DRAM to help support RAM boot from maskrom introduced in next patch. RAM boot from maskrom mode will expect the FIT payload to be located at 2 MiB offset from start or DRAM. Signed-off-by: Jonas Karlman Tested-by: Arnaud Patard Reviewed-by: Kever Yang --- arch/arm/mach-rockchip/Kconfig | 6 +++--- arch/arm/mach-rockchip/rk3308/Kconfig | 3 --- arch/arm/mach-rockchip/rk3568/Kconfig | 3 --- arch/arm/mach-rockchip/rk3588/Kconfig | 3 --- 4 files changed, 3 insertions(+), 12 deletions(-) diff --git a/arch/arm/mach-rockchip/Kconfig b/arch/arm/mach-rockchip/Kconfig index 342933ca509..c9ce3076029 100644 --- a/arch/arm/mach-rockchip/Kconfig +++ b/arch/arm/mach-rockchip/Kconfig @@ -768,9 +768,9 @@ config TPL_SYS_MALLOC_F_LEN default 0x4000 if CUSTOM_SYS_INIT_SP_ADDR = 0x03f00000 config TEXT_BASE - default 0x60200000 if SPL_TEXT_BASE = 0x60000000 - default 0x40200000 if SPL_TEXT_BASE = 0x40000000 - default 0x00200000 if SPL_TEXT_BASE = 0x00000000 + default 0x60800000 if SPL_TEXT_BASE = 0x60000000 + default 0x40800000 if SPL_TEXT_BASE = 0x40000000 + default 0x00800000 if SPL_TEXT_BASE = 0x00000000 config SPL_TEXT_BASE default 0x60000000 if ROCKCHIP_RK3036 || ROCKCHIP_RK3066 || \ diff --git a/arch/arm/mach-rockchip/rk3308/Kconfig b/arch/arm/mach-rockchip/rk3308/Kconfig index 06572d545f6..b8d25c52542 100644 --- a/arch/arm/mach-rockchip/rk3308/Kconfig +++ b/arch/arm/mach-rockchip/rk3308/Kconfig @@ -17,9 +17,6 @@ config ROCKCHIP_STIMER_BASE config SYS_SOC default "rk3308" -config TEXT_BASE - default 0x00600000 - source "board/rockchip/evb_rk3308/Kconfig" source "board/firefly/firefly-rk3308/Kconfig" diff --git a/arch/arm/mach-rockchip/rk3568/Kconfig b/arch/arm/mach-rockchip/rk3568/Kconfig index 01b53a47ddb..2730220a18e 100644 --- a/arch/arm/mach-rockchip/rk3568/Kconfig +++ b/arch/arm/mach-rockchip/rk3568/Kconfig @@ -70,9 +70,6 @@ config ROCKCHIP_STIMER_BASE config SYS_SOC default "rk3568" -config TEXT_BASE - default 0x00a00000 - source "board/rockchip/evb_rk3568/Kconfig" source "board/anbernic/rgxx3_rk3566/Kconfig" source "board/hardkernel/odroid_m1/Kconfig" diff --git a/arch/arm/mach-rockchip/rk3588/Kconfig b/arch/arm/mach-rockchip/rk3588/Kconfig index 9fbe3f225aa..60c16d2f32d 100644 --- a/arch/arm/mach-rockchip/rk3588/Kconfig +++ b/arch/arm/mach-rockchip/rk3588/Kconfig @@ -417,9 +417,6 @@ config ROCKCHIP_STIMER_BASE config SYS_SOC default "rk3588" -config TEXT_BASE - default 0x00a00000 - source "board/armsom/sige7-rk3588/Kconfig" source "board/coolpi/genbook_cm5_rk3588/Kconfig" source "board/edgeble/neural-compute-module-6/Kconfig" -- cgit v1.2.3 From e22335a221f88e7f61171e752ca195663f86d81f Mon Sep 17 00:00:00 2001 From: Jonas Karlman Date: Sat, 2 Aug 2025 22:07:23 +0000 Subject: rockchip: Add support for RAM boot from maskrom mode The BootROM in Rockchip SoCs will enter maskrom mode when boot firmware cannot be found in nand/spi/mmc storage. In maskrom mode the USB OTG port can accept one of two custom commands. Initially a 0x471 command to load TPL into SRAM. After TPL has been executed and it has returned back-to-BROM, a 0x472 command to load SPL into start of DRAM. Add two binman images that can be used to RAM boot from maskrom mode: - u-boot-rockchip-usb471.bin that contains TPL to init DRAM. - u-boot-rockchip-usb472.bin that contains SPL and the normal FIT payload with i.e. U-Boot proper, TF-A and FDT. A config fragment rockchip-ramboot.config can be used to enable building of these two binman images, e.g.: make generic-rk3588_defconfig rockchip-ramboot.config These binman images can be used with the proprietary rkbin boot_merger tool to create a special loader image that can be used with tools such as rkdeveloptool or rockusb tools to RAM boot from maskrom, e.g.: Create loader image: $ ../rkbin/tools/boot_merger ./RK3588MINIALL.ini Boot from maskrom: $ rkdeveloptool db u-boot-rockchip-rk3588-loader.bin or $ rockusb download-boot u-boot-rockchip-rk3588-loader.bin Another option that does not require use of proprietary tools is using open source tools such as rkflashtool or rkusbboot that can load the binman images directly without any need to first create a special loader image to RAM boot from maskrom, e.g.: $ rkflashtool l < u-boot-rockchip-usb471.bin $ rkflashtool L < u-boot-rockchip-usb472.bin or $ rkusbboot u-boot-rockchip-usb471.bin u-boot-rockchip-usb472.bin Signed-off-by: Jonas Karlman Tested-by: Arnaud Patard Reviewed-by: Kever Yang --- arch/arm/dts/rockchip-u-boot.dtsi | 33 +++++++++++++++++++++++++++++++++ arch/arm/mach-rockchip/Kconfig | 8 ++++++++ arch/arm/mach-rockchip/spl-boot-order.c | 14 +++++++++++--- board/rockchip/rockchip-ramboot.config | 1 + boot/Kconfig | 3 +++ 5 files changed, 56 insertions(+), 3 deletions(-) create mode 100644 board/rockchip/rockchip-ramboot.config diff --git a/arch/arm/dts/rockchip-u-boot.dtsi b/arch/arm/dts/rockchip-u-boot.dtsi index cc2feed6464..71d7623fe2c 100644 --- a/arch/arm/dts/rockchip-u-boot.dtsi +++ b/arch/arm/dts/rockchip-u-boot.dtsi @@ -226,5 +226,38 @@ }; }; #endif /* CONFIG_ROCKCHIP_SPI_IMAGE */ + +#ifdef CONFIG_ROCKCHIP_MASKROM_IMAGE + simple-bin-usb471 { + filename = "u-boot-rockchip-usb471.bin"; + +#ifdef CONFIG_ROCKCHIP_EXTERNAL_TPL + rockchip-tpl { + }; +#elif defined(CONFIG_TPL) + u-boot-tpl { + no-write-symbols; + }; +#endif + }; + + simple-bin-usb472 { + filename = "u-boot-rockchip-usb472.bin"; + pad-byte = <0x00>; + + u-boot-spl { + no-write-symbols; + }; + +#ifdef HAS_FIT + fit { + insert-template = <&fit_template>; +#else + u-boot-img { +#endif + offset = <(CONFIG_SPL_LOAD_FIT_ADDRESS - CFG_SYS_SDRAM_BASE)>; + }; + }; +#endif /* CONFIG_ROCKCHIP_MASKROM_IMAGE */ }; #endif /* CONFIG_SPL */ diff --git a/arch/arm/mach-rockchip/Kconfig b/arch/arm/mach-rockchip/Kconfig index c9ce3076029..e32e49ff59a 100644 --- a/arch/arm/mach-rockchip/Kconfig +++ b/arch/arm/mach-rockchip/Kconfig @@ -706,6 +706,14 @@ config ROCKCHIP_SPI_IMAGE option to produce a SPI-flash image containing U-Boot. The image is built by binman. U-Boot sits near the start of the image. +config ROCKCHIP_MASKROM_IMAGE + bool "Build a maskrom mode image for Rockchip" + depends on TPL || ROCKCHIP_EXTERNAL_TPL + select SPL_RAM_DEVICE + help + Rockchip SoCs support maskrom mode boot over USB. Enable this + option to produce maskrom mode boot images containing U-Boot. + config LNX_KRNL_IMG_TEXT_OFFSET_BASE default TEXT_BASE diff --git a/arch/arm/mach-rockchip/spl-boot-order.c b/arch/arm/mach-rockchip/spl-boot-order.c index 1ea1033b5ea..6572dde29f6 100644 --- a/arch/arm/mach-rockchip/spl-boot-order.c +++ b/arch/arm/mach-rockchip/spl-boot-order.c @@ -8,6 +8,7 @@ #include #include #include +#include #include #include @@ -98,15 +99,22 @@ __weak const char *board_spl_was_booted_from(void) void board_boot_order(u32 *spl_boot_list) { + int idx = 0; + + /* Add RAM boot for maskrom mode boot over USB */ + if (BROM_BOOTSOURCE_ID_ADDR && CONFIG_IS_ENABLED(RAM_DEVICE) && + read_brom_bootsource_id() == BROM_BOOTSOURCE_USB) { + spl_boot_list[idx++] = BOOT_DEVICE_RAM; + } + /* In case of no fdt (or only plat), use spl_boot_device() */ if (!CONFIG_IS_ENABLED(OF_CONTROL) || CONFIG_IS_ENABLED(OF_PLATDATA)) { - spl_boot_list[0] = spl_boot_device(); + spl_boot_list[idx++] = spl_boot_device(); return; } const void *blob = gd->fdt_blob; int chosen_node = fdt_path_offset(blob, "/chosen"); - int idx = 0; int elem; int boot_device; int node; @@ -115,7 +123,7 @@ void board_boot_order(u32 *spl_boot_list) if (chosen_node < 0) { debug("%s: /chosen not found, using spl_boot_device()\n", __func__); - spl_boot_list[0] = spl_boot_device(); + spl_boot_list[idx++] = spl_boot_device(); return; } diff --git a/board/rockchip/rockchip-ramboot.config b/board/rockchip/rockchip-ramboot.config new file mode 100644 index 00000000000..312363e542b --- /dev/null +++ b/board/rockchip/rockchip-ramboot.config @@ -0,0 +1 @@ +CONFIG_ROCKCHIP_MASKROM_IMAGE=y diff --git a/boot/Kconfig b/boot/Kconfig index 85f4d468069..245e120c70b 100644 --- a/boot/Kconfig +++ b/boot/Kconfig @@ -275,6 +275,9 @@ config SPL_LOAD_FIT_ADDRESS hex "load address of fit image" depends on SPL_LOAD_FIT default 0x44000000 if ARCH_IMX8M + default 0x60080000 if ARCH_ROCKCHIP && SPL_TEXT_BASE = 0x60000000 + default 0x40200000 if ARCH_ROCKCHIP && SPL_TEXT_BASE = 0x40000000 + default 0x00200000 if ARCH_ROCKCHIP && SPL_TEXT_BASE = 0x00000000 default 0x0 help Specify the load address of the fit image that will be loaded -- cgit v1.2.3 From 57dc75fb9be8f2508cb8c32dc5909c5b57876ace Mon Sep 17 00:00:00 2001 From: Jonas Karlman Date: Fri, 1 Aug 2025 17:09:27 +0000 Subject: rockchip: sdram: Add rockchip_sdram_type() helper Add a helper function based on rockchip_sdram_size() that return what DRAM type is used on current running board. Signed-off-by: Jonas Karlman Reviewed-by: Kever Yang --- arch/arm/include/asm/arch-rockchip/sdram.h | 3 +++ arch/arm/mach-rockchip/sdram.c | 15 +++++++++++++++ 2 files changed, 18 insertions(+) diff --git a/arch/arm/include/asm/arch-rockchip/sdram.h b/arch/arm/include/asm/arch-rockchip/sdram.h index 4fb45ac5c76..476fc1c4ee3 100644 --- a/arch/arm/include/asm/arch-rockchip/sdram.h +++ b/arch/arm/include/asm/arch-rockchip/sdram.h @@ -87,6 +87,9 @@ enum { #define SYS_REG_CS1_COL_SHIFT(ch) (0 + (ch) * 2) #define SYS_REG_CS1_COL_MASK 3 +/* Get sdram type decode from reg */ +u8 rockchip_sdram_type(phys_addr_t reg); + /* Get sdram size decode from reg */ size_t rockchip_sdram_size(phys_addr_t reg); diff --git a/arch/arm/mach-rockchip/sdram.c b/arch/arm/mach-rockchip/sdram.c index 3bc482331c7..d560f90e873 100644 --- a/arch/arm/mach-rockchip/sdram.c +++ b/arch/arm/mach-rockchip/sdram.c @@ -345,6 +345,21 @@ int dram_init_banksize(void) return 0; } +u8 rockchip_sdram_type(phys_addr_t reg) +{ + u32 dram_type, version; + u32 sys_reg2 = readl(reg); + u32 sys_reg3 = readl(reg + 4); + + dram_type = (sys_reg2 >> SYS_REG_DDRTYPE_SHIFT) & SYS_REG_DDRTYPE_MASK; + version = (sys_reg3 >> SYS_REG_VERSION_SHIFT) & SYS_REG_VERSION_MASK; + if (version >= 3) + dram_type |= ((sys_reg3 >> SYS_REG_EXTEND_DDRTYPE_SHIFT) & + SYS_REG_EXTEND_DDRTYPE_MASK) << 3; + + return dram_type; +} + size_t rockchip_sdram_size(phys_addr_t reg) { u32 rank, cs0_col, bk, cs0_row, cs1_row, bw, row_3_4; -- cgit v1.2.3 From 2df3666a241b706005ac8130c06188678c32ba39 Mon Sep 17 00:00:00 2001 From: Jonas Karlman Date: Fri, 1 Aug 2025 17:09:28 +0000 Subject: rockchip: rock5b-rk3588: Add support for ROCK 5B+ Include FDTs for both ROCK 5B and 5B+ in the FIT and add board selection code to load the 5B+ FDT when the DRAM type is LPDDR5 and ADC channel 5 value is close to 4095. U-Boot 2025.07 (Jul 14 2025 - 21:28:20 +0000) Model: Radxa ROCK 5B+ SoC: RK3588 DRAM: 8 GiB Features tested on a ROCK 5B+ v1.2: - SD-card boot - eMMC boot - SPI flash boot - PCIe/NVMe - Ethernet - USB/TCPM Signed-off-by: Jonas Karlman Reviewed-by: Kever Yang --- arch/arm/dts/rk3588-rock-5b-plus-u-boot.dtsi | 3 ++ arch/arm/dts/rk3588-rock-5b-u-boot.dtsi | 5 +++ board/radxa/rock5b-rk3588/Kconfig | 5 +++ board/radxa/rock5b-rk3588/MAINTAINERS | 3 +- board/radxa/rock5b-rk3588/rock5b-rk3588.c | 63 ++++++++++++++++++++++++++++ configs/rock5b-rk3588_defconfig | 1 + doc/board/rockchip/rockchip.rst | 2 +- 7 files changed, 79 insertions(+), 3 deletions(-) create mode 100644 arch/arm/dts/rk3588-rock-5b-plus-u-boot.dtsi diff --git a/arch/arm/dts/rk3588-rock-5b-plus-u-boot.dtsi b/arch/arm/dts/rk3588-rock-5b-plus-u-boot.dtsi new file mode 100644 index 00000000000..c07696c8391 --- /dev/null +++ b/arch/arm/dts/rk3588-rock-5b-plus-u-boot.dtsi @@ -0,0 +1,3 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) + +#include "rk3588-rock-5b-u-boot.dtsi" diff --git a/arch/arm/dts/rk3588-rock-5b-u-boot.dtsi b/arch/arm/dts/rk3588-rock-5b-u-boot.dtsi index d51fbf51cb8..e07b549c767 100644 --- a/arch/arm/dts/rk3588-rock-5b-u-boot.dtsi +++ b/arch/arm/dts/rk3588-rock-5b-u-boot.dtsi @@ -46,6 +46,11 @@ }; }; +&saradc { + bootph-pre-ram; + vdd-microvolts = <1800000>; +}; + &sdhci { cap-mmc-highspeed; mmc-hs200-1_8v; diff --git a/board/radxa/rock5b-rk3588/Kconfig b/board/radxa/rock5b-rk3588/Kconfig index 41dfe2402b1..98d63011783 100644 --- a/board/radxa/rock5b-rk3588/Kconfig +++ b/board/radxa/rock5b-rk3588/Kconfig @@ -9,4 +9,9 @@ config SYS_VENDOR config SYS_CONFIG_NAME default "rock5b-rk3588" +config BOARD_SPECIFIC_OPTIONS # dummy + def_bool y + select ADC + select SPL_ADC + endif diff --git a/board/radxa/rock5b-rk3588/MAINTAINERS b/board/radxa/rock5b-rk3588/MAINTAINERS index 4460c9971a9..c8a43769105 100644 --- a/board/radxa/rock5b-rk3588/MAINTAINERS +++ b/board/radxa/rock5b-rk3588/MAINTAINERS @@ -5,5 +5,4 @@ S: Maintained F: board/radxa/rock5b-rk3588 F: include/configs/rock5b-rk3588.h F: configs/rock5b-rk3588_defconfig -F: arch/arm/dts/rk3588-rock-5b.dts -F: arch/arm/dts/rk3588-rock-5b-u-boot.dtsi +F: arch/arm/dts/rk3588-rock-5b* diff --git a/board/radxa/rock5b-rk3588/rock5b-rk3588.c b/board/radxa/rock5b-rk3588/rock5b-rk3588.c index fc2f69db224..6bf4497ce3a 100644 --- a/board/radxa/rock5b-rk3588/rock5b-rk3588.c +++ b/board/radxa/rock5b-rk3588/rock5b-rk3588.c @@ -3,8 +3,71 @@ * Copyright (c) 2023-2024 Collabora Ltd. */ +#include +#include #include #include +#include +#include + +#define PMU1GRF_BASE 0xfd58a000 +#define OS_REG2_REG 0x208 + +#define HW_ID_CHANNEL 5 + +struct board_model { + unsigned int dram; + unsigned int low; + unsigned int high; + const char *fdtfile; +}; + +static const struct board_model board_models[] = { + { LPDDR5, 4005, 4185, "rockchip/rk3588-rock-5b-plus.dtb" }, +}; + +static const struct board_model *get_board_model(void) +{ + unsigned int val, dram_type; + int i, ret; + + dram_type = rockchip_sdram_type(PMU1GRF_BASE + OS_REG2_REG); + + ret = adc_channel_single_shot("adc@fec10000", HW_ID_CHANNEL, &val); + if (ret) + return NULL; + + for (i = 0; i < ARRAY_SIZE(board_models); i++) { + unsigned int dram = board_models[i].dram; + unsigned int min = board_models[i].low; + unsigned int max = board_models[i].high; + + if (dram == dram_type && min <= val && val <= max) + return &board_models[i]; + } + + return NULL; +} + +int rk_board_late_init(void) +{ + const struct board_model *model = get_board_model(); + + if (model) + env_set("fdtfile", model->fdtfile); + + return 0; +} + +int board_fit_config_name_match(const char *name) +{ + const struct board_model *model = get_board_model(); + + if (model && !strcmp(name, model->fdtfile)) + return 0; + + return -EINVAL; +} #ifdef CONFIG_OF_BOARD_SETUP int ft_board_setup(void *blob, struct bd_info *bd) diff --git a/configs/rock5b-rk3588_defconfig b/configs/rock5b-rk3588_defconfig index 6349e879145..967cebc2054 100644 --- a/configs/rock5b-rk3588_defconfig +++ b/configs/rock5b-rk3588_defconfig @@ -47,6 +47,7 @@ CONFIG_CMD_REGULATOR=y # CONFIG_SPL_DOS_PARTITION is not set CONFIG_SPL_OF_CONTROL=y CONFIG_OF_LIVE=y +CONFIG_OF_LIST="rockchip/rk3588-rock-5b rockchip/rk3588-rock-5b-plus" CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" CONFIG_SPL_DM_SEQ_ALIAS=y CONFIG_SPL_REGMAP=y diff --git a/doc/board/rockchip/rockchip.rst b/doc/board/rockchip/rockchip.rst index 0acccb51ad5..9af701feb5d 100644 --- a/doc/board/rockchip/rockchip.rst +++ b/doc/board/rockchip/rockchip.rst @@ -162,7 +162,7 @@ List of mainline supported Rockchip boards: - Pine64 QuartzPro64 (quartzpro64-rk3588) - Radxa ROCK 5 ITX (rock-5-itx-rk3588) - Radxa ROCK 5A (rock5a-rk3588s) - - Radxa ROCK 5B (rock5b-rk3588) + - Radxa ROCK 5B/5B+ (rock5b-rk3588) - Radxa ROCK 5C (rock-5c-rk3588s) - Rockchip Toybrick TB-RK3588X (toybrick-rk3588) - Theobroma Systems RK3588-SBC Jaguar (jaguar-rk3588) -- cgit v1.2.3 From 73159af02d023d01d9c4c08d319eb86cb10f1983 Mon Sep 17 00:00:00 2001 From: FUKAUMI Naoki Date: Fri, 7 Nov 2025 06:47:16 +0000 Subject: rockchip: rock5b-rk3588: Add support for Radxa ROCK 5T Include the FDT for Radxa ROCK 5T in the FIT, in addition to those for 5B and 5B+, and add board selection code to load the 5T FDT when the DRAM type is LPDDR5 and ADC channel 5 value is close to 1016. Signed-off-by: FUKAUMI Naoki Reviewed-by: Kever Yang --- arch/arm/dts/rk3588-rock-5t-u-boot.dtsi | 3 +++ board/radxa/rock5b-rk3588/rock5b-rk3588.c | 1 + configs/rock5b-rk3588_defconfig | 2 +- doc/board/rockchip/rockchip.rst | 2 +- 4 files changed, 6 insertions(+), 2 deletions(-) create mode 100644 arch/arm/dts/rk3588-rock-5t-u-boot.dtsi diff --git a/arch/arm/dts/rk3588-rock-5t-u-boot.dtsi b/arch/arm/dts/rk3588-rock-5t-u-boot.dtsi new file mode 100644 index 00000000000..c07696c8391 --- /dev/null +++ b/arch/arm/dts/rk3588-rock-5t-u-boot.dtsi @@ -0,0 +1,3 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) + +#include "rk3588-rock-5b-u-boot.dtsi" diff --git a/board/radxa/rock5b-rk3588/rock5b-rk3588.c b/board/radxa/rock5b-rk3588/rock5b-rk3588.c index 6bf4497ce3a..2c172d04499 100644 --- a/board/radxa/rock5b-rk3588/rock5b-rk3588.c +++ b/board/radxa/rock5b-rk3588/rock5b-rk3588.c @@ -23,6 +23,7 @@ struct board_model { }; static const struct board_model board_models[] = { + { LPDDR5, 926, 1106, "rockchip/rk3588-rock-5t.dtb" }, { LPDDR5, 4005, 4185, "rockchip/rk3588-rock-5b-plus.dtb" }, }; diff --git a/configs/rock5b-rk3588_defconfig b/configs/rock5b-rk3588_defconfig index 967cebc2054..567f649ea69 100644 --- a/configs/rock5b-rk3588_defconfig +++ b/configs/rock5b-rk3588_defconfig @@ -47,7 +47,7 @@ CONFIG_CMD_REGULATOR=y # CONFIG_SPL_DOS_PARTITION is not set CONFIG_SPL_OF_CONTROL=y CONFIG_OF_LIVE=y -CONFIG_OF_LIST="rockchip/rk3588-rock-5b rockchip/rk3588-rock-5b-plus" +CONFIG_OF_LIST="rockchip/rk3588-rock-5b rockchip/rk3588-rock-5b-plus rockchip/rk3588-rock-5t" CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" CONFIG_SPL_DM_SEQ_ALIAS=y CONFIG_SPL_REGMAP=y diff --git a/doc/board/rockchip/rockchip.rst b/doc/board/rockchip/rockchip.rst index 9af701feb5d..6ae4d4371ff 100644 --- a/doc/board/rockchip/rockchip.rst +++ b/doc/board/rockchip/rockchip.rst @@ -162,7 +162,7 @@ List of mainline supported Rockchip boards: - Pine64 QuartzPro64 (quartzpro64-rk3588) - Radxa ROCK 5 ITX (rock-5-itx-rk3588) - Radxa ROCK 5A (rock5a-rk3588s) - - Radxa ROCK 5B/5B+ (rock5b-rk3588) + - Radxa ROCK 5B/5B+/5T (rock5b-rk3588) - Radxa ROCK 5C (rock-5c-rk3588s) - Rockchip Toybrick TB-RK3588X (toybrick-rk3588) - Theobroma Systems RK3588-SBC Jaguar (jaguar-rk3588) -- cgit v1.2.3 From c9d27133159d0a84bf11052f588194a734cb48d4 Mon Sep 17 00:00:00 2001 From: Quentin Schulz Date: Fri, 7 Nov 2025 12:39:17 +0100 Subject: rockchip: i2c: fix incorrect STOP flag for the interrupt enable register I2C_CON_STOP is a flag to be used for the con register, where it is bit 4 to send the STOP condition. To enable the interrupt the controller sends to tell it's finished sending the STOP condition, it's the ien register at bit 5. Let's use the proper offset. My hunch is that enabling the interrupt is useless as the interrupt status register is always up-to-date and enabling the interrupt is just so that the interrupt is available via the GIC. However, U-Boot has no interrupt support and the logic was working well before this patch. This is just so people aren't side-tracked when debugging I2C issues on Rockchip by checking all writes are proper. Fixes: 3437469985df ("rockchip: Add I2C driver") Signed-off-by: Quentin Schulz Reviewed-by: Heiko Schocher Reviewed-by: Kever Yang --- drivers/i2c/rk_i2c.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/i2c/rk_i2c.c b/drivers/i2c/rk_i2c.c index fa167268ae7..fe09e75d3fb 100644 --- a/drivers/i2c/rk_i2c.c +++ b/drivers/i2c/rk_i2c.c @@ -137,7 +137,7 @@ static int rk_i2c_send_stop_bit(struct rk_i2c *i2c) writel(I2C_IPD_ALL_CLEAN, ®s->ipd); writel(I2C_CON_EN | I2C_CON_STOP, ®s->con); - writel(I2C_CON_STOP, ®s->ien); + writel(I2C_STOPIEN, ®s->ien); start = get_timer(0); while (1) { -- cgit v1.2.3 From 1cf8d0b68d6d853a2727bbb0a785fc7d93304ca4 Mon Sep 17 00:00:00 2001 From: Quentin Schulz Date: Fri, 7 Nov 2025 12:39:18 +0100 Subject: rockchip: i2c: move ACK comment where it applies The I2C_CON_LASTACK is kind of a misnomer as setting it means sending a NACK as last byte acknowledge when the controller is in receive mode. It should therefore be used only when there's no more data to transfer after this. Move the comment in the proper if block. Sync the comment with the Linux kernel's while at it so it's more explicit. Fixes: 5deaa530280f ("rockchip: i2c: fix >32 byte reads") Signed-off-by: Quentin Schulz Reviewed-by: Heiko Schocher Reviewed-by: Kever Yang --- drivers/i2c/rk_i2c.c | 9 +++++---- 1 file changed, 5 insertions(+), 4 deletions(-) diff --git a/drivers/i2c/rk_i2c.c b/drivers/i2c/rk_i2c.c index fe09e75d3fb..3c44d0e65f5 100644 --- a/drivers/i2c/rk_i2c.c +++ b/drivers/i2c/rk_i2c.c @@ -195,13 +195,14 @@ static int rk_i2c_read(struct rk_i2c *i2c, uchar chip, uint reg, uint r_len, while (bytes_remain_len) { if (bytes_remain_len > RK_I2C_FIFO_SIZE) { - con = I2C_CON_EN; - bytes_xferred = 32; - } else { /* * The hw can read up to 32 bytes at a time. If we need - * more than one chunk, send an ACK after the last byte. + * more than one chunk, send an ACK after the last byte + * of the current chunk. */ + con = I2C_CON_EN; + bytes_xferred = 32; + } else { con = I2C_CON_EN | I2C_CON_LASTACK; bytes_xferred = bytes_remain_len; } -- cgit v1.2.3 From 0e5e98081943586b20a45f711bf3f4801191e762 Mon Sep 17 00:00:00 2001 From: Quentin Schulz Date: Fri, 7 Nov 2025 12:39:19 +0100 Subject: rockchip: i2c: fix illegal I2C START/STOP condition In the last message sent in rockchip_i2c_xfer, the controller is disabled (see rk_i2c_disable() in rk_i2c_read()/rk_i2c_write()), then the STOP condition is sent (see rk_i2c_send_stop_bit() in rockchip_i2c_xfer()) and the controller is disabled once again (see rk_i2c_disable() right after). The issue is that re-enabling the controller just to send the STOP condition doesn't work. When, the controller is disabled, the SCL and SDA lanes are not driven anymore and thus enter the idle mode where they are kept high by the external HW pull-up. To send a STOP condition, one needs to drive the SDA line so that a rising edge happens while SCL is high. Experimentally (on PX30 and RK3399), when enabling the controller to send a STOP condition after it's been disabled, the controller only drives the SDA line to trigger the rising edge for the STOP condition, leaving SCL undriven (and thus, high). This means, that because SDA is high before this happens and that we need a rising edge, the controller drives the SDA line low and then releases it, meaning we trigger a START condition followed by a STOP condition: SCL _________ _____... __ _____ _____... \/ SDA ^ STOP ^ START This is illegal in I2C protocol[1]: 5. A START condition immediately followed by a STOP condition (void message) is an illegal format. Many devices however are designed to operate properly under this condition. My guess is that the I2C controller IP knows that it makes only sense to send a STOP condition after a START condition, meaning the controller is already driving the SCL line low and neither the device nor controller drive the SDA line after the last ACK/NACK as there's no need to, then it needs to drive SDA, release SCL to make it high and then release the SDA line. However, after it's been disabled, the SCL is already released so the controller only essentially drives SDA and then releases it. It happens that this seems to be breaking the SE050 Secure Element after a few transfers in the middle of a transfer where it starts clock stretching the bus forever. It may be related to Errata 3.2[2] but the description of the setup isn't an exact match to the current situation. It seems to be required to disable the I2C controller between messages as the Linux kernel states that "The HW is actually not capable of REPEATED START. But we can get the intended effect by resetting its internal state and issuing an ordinary START.". Between messages, this logic seems fine as I get an Sr (repeated START condition) before starting the next message in the transfer without a STOP condition. However, we should NOT disable the controller after the last message in the transfer otherwise we do this illegal START condition followed by the STOP condition, hence the added check. [1] https://www.nxp.com/docs/en/user-guide/UM10204.pdf 3.1.10 The target address and R/W bit point 5 [2] https://www.nxp.com/docs/en/errata/SE050_Erratasheet.pdf Fixes: c9fca5ec8849 ("rockchip: i2c: don't sent stop bit after each message") Signed-off-by: Quentin Schulz Reviewed-by: Heiko Schocher Reviewed-by: Kever Yang --- drivers/i2c/rk_i2c.c | 16 ++++++++++++---- 1 file changed, 12 insertions(+), 4 deletions(-) diff --git a/drivers/i2c/rk_i2c.c b/drivers/i2c/rk_i2c.c index 3c44d0e65f5..def07018148 100644 --- a/drivers/i2c/rk_i2c.c +++ b/drivers/i2c/rk_i2c.c @@ -255,8 +255,6 @@ static int rk_i2c_read(struct rk_i2c *i2c, uchar chip, uint reg, uint r_len, } i2c_exit: - rk_i2c_disable(i2c); - return err; } @@ -333,8 +331,6 @@ static int rk_i2c_write(struct rk_i2c *i2c, uchar chip, uint reg, uint r_len, } i2c_exit: - rk_i2c_disable(i2c); - return err; } @@ -359,6 +355,18 @@ static int rockchip_i2c_xfer(struct udevice *bus, struct i2c_msg *msg, ret = -EREMOTEIO; break; } + + /* + * The HW is actually not capable of REPEATED START. But we can + * get the intended effect by resetting its internal state + * and issuing an ordinary START. + * + * Do NOT disable the controller after the last message (before + * sending the STOP condition) as this triggers an illegal + * START condition followed by a STOP condition. + */ + if (nmsgs > 1) + rk_i2c_disable(i2c); } rk_i2c_send_stop_bit(i2c); -- cgit v1.2.3 From 0ed7abc85d1664a3d7432795a7126ff6a1d01147 Mon Sep 17 00:00:00 2001 From: Quentin Schulz Date: Wed, 12 Nov 2025 15:58:00 +0100 Subject: rockchip: mkimage: enhance comments for v1 header Improve the image header documentation for v1 header: - specify this applies to all MMC, not only SD cards, - specify the offset for SPI flashes, - specify the key used for RC4 encoding, - specify what "init" refers to, especially since some configs enable TPL, - specify what "init_boot_size" refers to, especially since some configs enable TPL, - specify the size of a block, - add documentation for init_size and init_boot_size, Note that the offset on the storage medium isn't necessarily 32KiB (64 blocks) for MMC or 0 for SPI flashes, it's just the first offset the BootROM checks. Barebox[1] lists a few options, though those are applicable to RK35xx which use the v2 header, so not guaranteed they can be shared. On RK3399, the binary can at least be stored at offset 0 and 32KiB on SPI flashes. [1] https://git.pengutronix.de/cgit/barebox/tree/arch/arm/mach-rockchip/bbu.c#n19 Signed-off-by: Quentin Schulz Reviewed-by: Kever Yang --- tools/rkcommon.c | 24 ++++++++++++++++++++---- 1 file changed, 20 insertions(+), 4 deletions(-) diff --git a/tools/rkcommon.c b/tools/rkcommon.c index d191ea72c63..e7e78ef7e5b 100644 --- a/tools/rkcommon.c +++ b/tools/rkcommon.c @@ -76,13 +76,29 @@ struct header0_info_v2 { /** * struct header0_info - header block for boot ROM * - * This is stored at SD card block 64 (where each block is 512 bytes, or at - * the start of SPI flash. It is encoded with RC4. + * This is stored at MMC block 64 (where each block is 512 bytes), or at + * the start of SPI flash. It is encoded with RC4 with the below rc4_key. + * + * In Rockchip terminology: + * + * "init" means the stage that is loaded into SRAM. TPL if there is one, SPL + * otherwise. + * + * "boot" means the next stages after "init" stage that are loaded by the + * BootROM into DRAM. Only applicable if "init" stage returns to BootROM (via + * the appropriate ROCKCHIP_BACK_TO_BROM symbol, BOOT_DEVICE_BOOTROM is used as + * boot device for the next stage and the "init" stage successfully booted) and + * if "init_boot_size" > "init_size". + * Basically, it is the content of "init" plus the SPL or even U-Boot proper if + * relevant. * * @magic: Magic (must be RK_MAGIC) * @disable_rc4: 0 to use rc4 for boot image, 1 to use plain binary - * @init_offset: Offset in blocks of the SPL code from this header - * block. E.g. 4 means 2KB after the start of this header. + * @init_offset: Offset in 512-byte blocks of the "init" code from the + * start of this header. For instance, 4 means 2KiB. + * @init_size: Size (in blocks) of the "init" code. + * @init_boot_size: Size (in blocks) of the "init" and "boot" code combined. + * * Other fields are not used by U-Boot */ struct header0_info { -- cgit v1.2.3