From 8f1b3334574bbc1a9a46db92a798f0aed968e858 Mon Sep 17 00:00:00 2001 From: Paweł Anikiel Date: Tue, 21 Feb 2023 16:17:01 +0100 Subject: socfpga: chameleonv3: Enable ext4 in SPL MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Allow SPL to boot from an ext4 filesystem. Signed-off-by: Paweł Anikiel Reviewed-by: Simon Glass --- configs/socfpga_chameleonv3_defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/configs/socfpga_chameleonv3_defconfig b/configs/socfpga_chameleonv3_defconfig index 4bbce3591da..5d08fd282b4 100644 --- a/configs/socfpga_chameleonv3_defconfig +++ b/configs/socfpga_chameleonv3_defconfig @@ -7,6 +7,7 @@ CONFIG_DEFAULT_DEVICE_TREE="socfpga_arria10_chameleonv3_480_2" CONFIG_SPL_TEXT_BASE=0xFFE00000 CONFIG_SPL_DRIVERS_MISC=y CONFIG_TARGET_SOCFPGA_CHAMELEONV3=y +CONFIG_SPL_FS_EXT4=y CONFIG_SPL_FS_FAT=y CONFIG_DISTRO_DEFAULTS=y CONFIG_FIT=y -- cgit v1.3.1 From 0f3c8fe392618fca29f2093be3ce771401bc6d56 Mon Sep 17 00:00:00 2001 From: Paweł Anikiel Date: Tue, 21 Feb 2023 16:17:02 +0100 Subject: socfpga: chameleonv3: Move environment to a text file MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Move the environment to an easily editable text file in the boot partition Signed-off-by: Paweł Anikiel Reviewed-by: Simon Glass --- board/google/chameleonv3/environment.txt | 13 +++++++++++++ include/configs/socfpga_chameleonv3.h | 9 ++++----- 2 files changed, 17 insertions(+), 5 deletions(-) create mode 100644 board/google/chameleonv3/environment.txt diff --git a/board/google/chameleonv3/environment.txt b/board/google/chameleonv3/environment.txt new file mode 100644 index 00000000000..52aedbb90a2 --- /dev/null +++ b/board/google/chameleonv3/environment.txt @@ -0,0 +1,13 @@ +# MMC boot command +bootcmd_mmc=load mmc 0:1 ${loadaddr} kernel.itb; bootm + +# Network boot command and vars +bootcmd_net=dhcp; tftpboot ${loadaddr} kernel.itb; bootm +autoload=no +serverip=192.168.0.1 + +# U-Boot will run this after loading this file +bootcmd_txt=run bootcmd_mmc + +# Kernel cmdline +bootargs=cma=256M console=ttyS1,115200 root=/dev/mmcblk0p3 rootflags=subvol=root rw rootwait diff --git a/include/configs/socfpga_chameleonv3.h b/include/configs/socfpga_chameleonv3.h index 2ce7011529a..fc08e74dba0 100644 --- a/include/configs/socfpga_chameleonv3.h +++ b/include/configs/socfpga_chameleonv3.h @@ -20,11 +20,10 @@ #define CFG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600, 115200} #define CFG_EXTRA_ENV_SETTINGS \ - "autoload=no\0" \ - "bootargs=cma=256M console=ttyS1,115200 root=/dev/mmcblk0p3 rw rootwait\0" \ - "distro_bootcmd=bridge enable; run bootcmd_mmc\0" \ - "bootcmd_mmc=load mmc 0:1 ${loadaddr} kernel.itb; bootm\0" \ - "bootcmd_net=dhcp; tftpboot ${loadaddr} kernel.itb; bootm\0" + "distro_bootcmd=bridge enable; " \ + "load mmc 0:1 ${loadaddr} u-boot.txt; " \ + "env import -t ${loadaddr}; " \ + "run bootcmd_txt\0" /* * L4 OSC1 Timer 0 -- cgit v1.3.1 From 1d222089f08af79585e2f1d2fceaa8033c877f9c Mon Sep 17 00:00:00 2001 From: Paweł Anikiel Date: Tue, 21 Feb 2023 16:17:03 +0100 Subject: arm: dts: chameleonv3: Override chameleonv3 bitstream names MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Set the bitstream name per Chameleon variant. This allows the same boot filesystem with all bitstream variants to be used on different boards. Signed-off-by: Paweł Anikiel Reviewed-by: Simon Glass --- arch/arm/dts/socfpga_arria10_chameleonv3_270_3-u-boot.dtsi | 4 ++++ arch/arm/dts/socfpga_arria10_chameleonv3_480_2-u-boot.dtsi | 4 ++++ 2 files changed, 8 insertions(+) diff --git a/arch/arm/dts/socfpga_arria10_chameleonv3_270_3-u-boot.dtsi b/arch/arm/dts/socfpga_arria10_chameleonv3_270_3-u-boot.dtsi index e789d49657b..a7aa17b220a 100644 --- a/arch/arm/dts/socfpga_arria10_chameleonv3_270_3-u-boot.dtsi +++ b/arch/arm/dts/socfpga_arria10_chameleonv3_270_3-u-boot.dtsi @@ -6,3 +6,7 @@ #include "socfpga_arria10-handoff.dtsi" #include "socfpga_arria10_handoff_u-boot.dtsi" #include "socfpga_arria10_mercury_aa1-u-boot.dtsi" + +&fpga_mgr { + altr,bitstream = "fpga-270-3.itb"; +}; diff --git a/arch/arm/dts/socfpga_arria10_chameleonv3_480_2-u-boot.dtsi b/arch/arm/dts/socfpga_arria10_chameleonv3_480_2-u-boot.dtsi index 7bbcc471c52..82a94894eaa 100644 --- a/arch/arm/dts/socfpga_arria10_chameleonv3_480_2-u-boot.dtsi +++ b/arch/arm/dts/socfpga_arria10_chameleonv3_480_2-u-boot.dtsi @@ -6,3 +6,7 @@ #include "socfpga_arria10-handoff.dtsi" #include "socfpga_arria10_handoff_u-boot.dtsi" #include "socfpga_arria10_mercury_aa1-u-boot.dtsi" + +&fpga_mgr { + altr,bitstream = "fpga-480-2.itb"; +}; -- cgit v1.3.1 From 9c107ab42bd44fc1902f51d118ad10007244f8d6 Mon Sep 17 00:00:00 2001 From: Paweł Anikiel Date: Tue, 21 Feb 2023 16:17:04 +0100 Subject: arm: dts: chameleonv3: Rename chameleonv3.dts to .dtsi MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This file is included by the different chameleonv3 variants. Change the name to .dtsi. Signed-off-by: Paweł Anikiel Reviewed-by: Simon Glass --- arch/arm/dts/socfpga_arria10_chameleonv3.dts | 90 ---------------------- arch/arm/dts/socfpga_arria10_chameleonv3.dtsi | 90 ++++++++++++++++++++++ arch/arm/dts/socfpga_arria10_chameleonv3_270_3.dts | 2 +- arch/arm/dts/socfpga_arria10_chameleonv3_480_2.dts | 2 +- 4 files changed, 92 insertions(+), 92 deletions(-) delete mode 100644 arch/arm/dts/socfpga_arria10_chameleonv3.dts create mode 100644 arch/arm/dts/socfpga_arria10_chameleonv3.dtsi diff --git a/arch/arm/dts/socfpga_arria10_chameleonv3.dts b/arch/arm/dts/socfpga_arria10_chameleonv3.dts deleted file mode 100644 index 988cc445438..00000000000 --- a/arch/arm/dts/socfpga_arria10_chameleonv3.dts +++ /dev/null @@ -1,90 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Copyright 2022 Google LLC - */ -/dts-v1/; -#include "socfpga_arria10_mercury_aa1.dtsi" - -/ { - model = "Google Chameleon V3"; - compatible = "google,chameleon-v3", - "altr,socfpga-arria10", "altr,socfpga"; - - aliases { - serial0 = &uart0; - i2c0 = &i2c0; - i2c1 = &i2c1; - }; -}; - -&gmac0 { - status = "okay"; -}; - -&gpio0 { - status = "okay"; -}; - -&gpio1 { - status = "okay"; -}; - -&gpio2 { - status = "okay"; -}; - -&i2c0 { - status = "okay"; - - ssm2603: ssm2603@1a { - compatible = "adi,ssm2603"; - reg = <0x1a>; - }; -}; - -&i2c1 { - status = "okay"; - - u80: u80@21 { - compatible = "nxp,pca9535"; - reg = <0x21>; - gpio-controller; - #gpio-cells = <2>; - - gpio-line-names = - "SOM_AUD_MUTE", - "DP1_OUT_CEC_EN", - "DP2_OUT_CEC_EN", - "DP1_SOM_PS8469_CAD", - "DPD_SOM_PS8469_CAD", - "DP_OUT_PWR_EN", - "STM32_RST_L", - "STM32_BOOT0", - - "FPGA_PROT", - "STM32_FPGA_COMM0", - "TP119", - "TP120", - "TP121", - "TP122", - "TP123", - "TP124"; - }; -}; - -&mmc { - status = "okay"; -}; - -&uart0 { - status = "okay"; -}; - -&uart1 { - status = "okay"; -}; - -&usb0 { - status = "okay"; - dr_mode = "host"; -}; diff --git a/arch/arm/dts/socfpga_arria10_chameleonv3.dtsi b/arch/arm/dts/socfpga_arria10_chameleonv3.dtsi new file mode 100644 index 00000000000..988cc445438 --- /dev/null +++ b/arch/arm/dts/socfpga_arria10_chameleonv3.dtsi @@ -0,0 +1,90 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright 2022 Google LLC + */ +/dts-v1/; +#include "socfpga_arria10_mercury_aa1.dtsi" + +/ { + model = "Google Chameleon V3"; + compatible = "google,chameleon-v3", + "altr,socfpga-arria10", "altr,socfpga"; + + aliases { + serial0 = &uart0; + i2c0 = &i2c0; + i2c1 = &i2c1; + }; +}; + +&gmac0 { + status = "okay"; +}; + +&gpio0 { + status = "okay"; +}; + +&gpio1 { + status = "okay"; +}; + +&gpio2 { + status = "okay"; +}; + +&i2c0 { + status = "okay"; + + ssm2603: ssm2603@1a { + compatible = "adi,ssm2603"; + reg = <0x1a>; + }; +}; + +&i2c1 { + status = "okay"; + + u80: u80@21 { + compatible = "nxp,pca9535"; + reg = <0x21>; + gpio-controller; + #gpio-cells = <2>; + + gpio-line-names = + "SOM_AUD_MUTE", + "DP1_OUT_CEC_EN", + "DP2_OUT_CEC_EN", + "DP1_SOM_PS8469_CAD", + "DPD_SOM_PS8469_CAD", + "DP_OUT_PWR_EN", + "STM32_RST_L", + "STM32_BOOT0", + + "FPGA_PROT", + "STM32_FPGA_COMM0", + "TP119", + "TP120", + "TP121", + "TP122", + "TP123", + "TP124"; + }; +}; + +&mmc { + status = "okay"; +}; + +&uart0 { + status = "okay"; +}; + +&uart1 { + status = "okay"; +}; + +&usb0 { + status = "okay"; + dr_mode = "host"; +}; diff --git a/arch/arm/dts/socfpga_arria10_chameleonv3_270_3.dts b/arch/arm/dts/socfpga_arria10_chameleonv3_270_3.dts index 5f40af6eb95..bef0280212d 100644 --- a/arch/arm/dts/socfpga_arria10_chameleonv3_270_3.dts +++ b/arch/arm/dts/socfpga_arria10_chameleonv3_270_3.dts @@ -2,4 +2,4 @@ /* * Copyright 2022 Google LLC */ -#include "socfpga_arria10_chameleonv3.dts" +#include "socfpga_arria10_chameleonv3.dtsi" diff --git a/arch/arm/dts/socfpga_arria10_chameleonv3_480_2.dts b/arch/arm/dts/socfpga_arria10_chameleonv3_480_2.dts index 5f40af6eb95..bef0280212d 100644 --- a/arch/arm/dts/socfpga_arria10_chameleonv3_480_2.dts +++ b/arch/arm/dts/socfpga_arria10_chameleonv3_480_2.dts @@ -2,4 +2,4 @@ /* * Copyright 2022 Google LLC */ -#include "socfpga_arria10_chameleonv3.dts" +#include "socfpga_arria10_chameleonv3.dtsi" -- cgit v1.3.1 From 48c172c2f8f4c10f9dbd7416866125a6a528fb88 Mon Sep 17 00:00:00 2001 From: Paweł Anikiel Date: Tue, 21 Feb 2023 16:17:05 +0100 Subject: arm: dts: chameleonv3: Add 270-2 variant MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Add devicetree for chameleonv3 with the 270-2I2-D11E variant of the Mercury+ AA1 module Signed-off-by: Paweł Anikiel Reviewed-by: Simon Glass --- arch/arm/dts/Makefile | 1 + arch/arm/dts/socfpga_arria10_chameleonv3_270_2-u-boot.dtsi | 12 ++++++++++++ arch/arm/dts/socfpga_arria10_chameleonv3_270_2.dts | 5 +++++ 3 files changed, 18 insertions(+) create mode 100644 arch/arm/dts/socfpga_arria10_chameleonv3_270_2-u-boot.dtsi create mode 100644 arch/arm/dts/socfpga_arria10_chameleonv3_270_2.dts diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index 9d647b96393..7a577deb502 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -442,6 +442,7 @@ dtb-$(CONFIG_ARCH_SOCFPGA) += \ socfpga_agilex_socdk.dtb \ socfpga_arria5_secu1.dtb \ socfpga_arria5_socdk.dtb \ + socfpga_arria10_chameleonv3_270_2.dtb \ socfpga_arria10_chameleonv3_270_3.dtb \ socfpga_arria10_chameleonv3_480_2.dtb \ socfpga_arria10_socdk_sdmmc.dtb \ diff --git a/arch/arm/dts/socfpga_arria10_chameleonv3_270_2-u-boot.dtsi b/arch/arm/dts/socfpga_arria10_chameleonv3_270_2-u-boot.dtsi new file mode 100644 index 00000000000..05b4485cf35 --- /dev/null +++ b/arch/arm/dts/socfpga_arria10_chameleonv3_270_2-u-boot.dtsi @@ -0,0 +1,12 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright 2022 Google LLC + */ +#include "socfpga_arria10_chameleonv3_480_2_handoff.h" +#include "socfpga_arria10-handoff.dtsi" +#include "socfpga_arria10_handoff_u-boot.dtsi" +#include "socfpga_arria10_mercury_aa1-u-boot.dtsi" + +&fpga_mgr { + altr,bitstream = "fpga-270-2.itb"; +}; diff --git a/arch/arm/dts/socfpga_arria10_chameleonv3_270_2.dts b/arch/arm/dts/socfpga_arria10_chameleonv3_270_2.dts new file mode 100644 index 00000000000..bef0280212d --- /dev/null +++ b/arch/arm/dts/socfpga_arria10_chameleonv3_270_2.dts @@ -0,0 +1,5 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright 2022 Google LLC + */ +#include "socfpga_arria10_chameleonv3.dtsi" -- cgit v1.3.1 From 52b8fca7178afdcacb31cfcdfea9429779d084a1 Mon Sep 17 00:00:00 2001 From: Paweł Anikiel Date: Tue, 21 Feb 2023 16:17:06 +0100 Subject: chameleonv3: Convert CONFIG_SPL_MAX_SIZE to Kconfig MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This file was missed during the conversion process. Add the symbol to defconfig. Signed-off-by: Paweł Anikiel Reviewed-by: Simon Glass --- configs/socfpga_chameleonv3_defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/configs/socfpga_chameleonv3_defconfig b/configs/socfpga_chameleonv3_defconfig index 5d08fd282b4..41231e23826 100644 --- a/configs/socfpga_chameleonv3_defconfig +++ b/configs/socfpga_chameleonv3_defconfig @@ -5,6 +5,7 @@ CONFIG_ENV_SIZE=0x10000 CONFIG_ENV_OFFSET=0x4400 CONFIG_DEFAULT_DEVICE_TREE="socfpga_arria10_chameleonv3_480_2" CONFIG_SPL_TEXT_BASE=0xFFE00000 +CONFIG_SPL_MAX_SIZE=0x40000 CONFIG_SPL_DRIVERS_MISC=y CONFIG_TARGET_SOCFPGA_CHAMELEONV3=y CONFIG_SPL_FS_EXT4=y -- cgit v1.3.1