From 8653e5d3b745925fced5fa6897c92f4a46ec2757 Mon Sep 17 00:00:00 2001 From: Jonas Karlman Date: Tue, 14 Mar 2023 00:38:21 +0000 Subject: rockchip: Fix early use of bootph props Running U-Boot on a ROCK 3 Model A result in the following: No serial driver found resetting ... no sysreset ### ERROR ### Please RESET the board ### Replace bootph- props with u-boot,dm- props to fix this. Signed-off-by: Jonas Karlman Reviewed-by: Kever Yang --- arch/arm/dts/rk3308-rock-pi-s-u-boot.dtsi | 2 +- arch/arm/dts/rk3566-radxa-cm3-io-u-boot.dtsi | 2 +- arch/arm/dts/rk3568-rock-3a-u-boot.dtsi | 2 +- arch/arm/dts/rk3588-edgeble-neu6a-io-u-boot.dtsi | 2 +- arch/arm/dts/rk3588s-u-boot.dtsi | 14 +++++++------- 5 files changed, 11 insertions(+), 11 deletions(-) diff --git a/arch/arm/dts/rk3308-rock-pi-s-u-boot.dtsi b/arch/arm/dts/rk3308-rock-pi-s-u-boot.dtsi index a27a3adc082..27735c49ddc 100644 --- a/arch/arm/dts/rk3308-rock-pi-s-u-boot.dtsi +++ b/arch/arm/dts/rk3308-rock-pi-s-u-boot.dtsi @@ -11,7 +11,7 @@ }; &uart0 { - bootph-all; + u-boot,dm-pre-reloc; clock-frequency = <24000000>; status = "okay"; }; diff --git a/arch/arm/dts/rk3566-radxa-cm3-io-u-boot.dtsi b/arch/arm/dts/rk3566-radxa-cm3-io-u-boot.dtsi index 4e791738335..589332503e7 100644 --- a/arch/arm/dts/rk3566-radxa-cm3-io-u-boot.dtsi +++ b/arch/arm/dts/rk3566-radxa-cm3-io-u-boot.dtsi @@ -13,6 +13,6 @@ &uart2 { clock-frequency = <24000000>; - bootph-all; + u-boot,dm-pre-reloc; status = "okay"; }; diff --git a/arch/arm/dts/rk3568-rock-3a-u-boot.dtsi b/arch/arm/dts/rk3568-rock-3a-u-boot.dtsi index ed47efa44bf..b5ca23a82a2 100644 --- a/arch/arm/dts/rk3568-rock-3a-u-boot.dtsi +++ b/arch/arm/dts/rk3568-rock-3a-u-boot.dtsi @@ -19,6 +19,6 @@ &uart2 { clock-frequency = <24000000>; - bootph-all; + u-boot,dm-pre-reloc; status = "okay"; }; diff --git a/arch/arm/dts/rk3588-edgeble-neu6a-io-u-boot.dtsi b/arch/arm/dts/rk3588-edgeble-neu6a-io-u-boot.dtsi index 3235bd36e4c..612966492b0 100644 --- a/arch/arm/dts/rk3588-edgeble-neu6a-io-u-boot.dtsi +++ b/arch/arm/dts/rk3588-edgeble-neu6a-io-u-boot.dtsi @@ -18,7 +18,7 @@ &sdmmc { bus-width = <4>; - bootph-all; + u-boot,dm-pre-reloc; u-boot,spl-fifo-mode; status = "okay"; }; diff --git a/arch/arm/dts/rk3588s-u-boot.dtsi b/arch/arm/dts/rk3588s-u-boot.dtsi index 1e225d71efc..f880f4a1674 100644 --- a/arch/arm/dts/rk3588s-u-boot.dtsi +++ b/arch/arm/dts/rk3588s-u-boot.dtsi @@ -8,12 +8,12 @@ / { dmc { compatible = "rockchip,rk3588-dmc"; - bootph-all; + u-boot,dm-pre-reloc; status = "okay"; }; pmu1_grf: syscon@fd58a000 { - bootph-all; + u-boot,dm-pre-reloc; compatible = "rockchip,rk3588-pmu1-grf", "syscon"; reg = <0x0 0xfd58a000 0x0 0x2000>; }; @@ -46,26 +46,26 @@ }; &xin24m { - bootph-all; + u-boot,dm-pre-reloc; status = "okay"; }; &cru { - bootph-pre-ram; + u-boot,dm-spl; status = "okay"; }; &sys_grf { - bootph-pre-ram; + u-boot,dm-spl; status = "okay"; }; &uart2 { clock-frequency = <24000000>; - bootph-pre-ram; + u-boot,dm-spl; status = "okay"; }; &ioc { - bootph-pre-ram; + u-boot,dm-spl; }; -- cgit v1.3.1 From 42f67fb51cb4f0aa84f39ea755f46686bec9f0b7 Mon Sep 17 00:00:00 2001 From: Jonas Karlman Date: Tue, 14 Mar 2023 00:38:23 +0000 Subject: rockchip: rk3568: Fix boot device detection The boot source node path for emmc is using the old sdhci name. Replace with correct mmc name and also add same-as-spl to boot order. Fixes: 0d61f8e5f1c0 ("rockchip: rk3568: add boot device detection") Signed-off-by: Jonas Karlman Reviewed-by: Kever Yang --- arch/arm/dts/rk356x-u-boot.dtsi | 2 +- arch/arm/mach-rockchip/rk3568/rk3568.c | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm/dts/rk356x-u-boot.dtsi b/arch/arm/dts/rk356x-u-boot.dtsi index 23316410496..04a7b0a0f66 100644 --- a/arch/arm/dts/rk356x-u-boot.dtsi +++ b/arch/arm/dts/rk356x-u-boot.dtsi @@ -12,7 +12,7 @@ }; chosen { - u-boot,spl-boot-order = &sdhci, &sdmmc0; + u-boot,spl-boot-order = "same-as-spl", &sdhci, &sdmmc0; }; dmc: dmc { diff --git a/arch/arm/mach-rockchip/rk3568/rk3568.c b/arch/arm/mach-rockchip/rk3568/rk3568.c index 4a08820a093..69ef19cc85a 100644 --- a/arch/arm/mach-rockchip/rk3568/rk3568.c +++ b/arch/arm/mach-rockchip/rk3568/rk3568.c @@ -82,7 +82,7 @@ static struct mm_region rk3568_mem_map[] = { }; const char * const boot_devices[BROM_LAST_BOOTSOURCE + 1] = { - [BROM_BOOTSOURCE_EMMC] = "/sdhci@fe310000", + [BROM_BOOTSOURCE_EMMC] = "/mmc@fe310000", [BROM_BOOTSOURCE_SPINOR] = "/spi@fe300000/flash@0", [BROM_BOOTSOURCE_SD] = "/mmc@fe2b0000", }; -- cgit v1.3.1 From 073d911ae64acc40fe67d88cb7a27876ffcf6e53 Mon Sep 17 00:00:00 2001 From: Jonas Karlman Date: Tue, 14 Mar 2023 00:38:24 +0000 Subject: rockchip: rk3568-rock-3a: Sync device tree from linux Running U-Boot from eMMC on a ROCK 3 Model A result in the following: U-Boot SPL 2023.04-rc3 (Mar 11 2023 - 17:24:48 +0000) Trying to boot from MMC1 Card did not respond to voltage select! : -110 spl: mmc init failed with error: -95 SPL: failed to boot from all boot devices ### ERROR ### Please RESET the board ### The sdhci node is missing in board device tree, sync device tree from linux v6.3-rc1 to fix booting from eMMC. Also disable sdmmc2 and uart1 nodes related to using a WiFi and BT module in the M2 slot. Fixes: b44c54f600ab ("arm64: dts: rockchip: rk3568: Add Radxa ROCK 3 Model A board support") Signed-off-by: Jonas Karlman Reviewed-by: Kever Yang --- arch/arm/dts/rk3568-rock-3a-u-boot.dtsi | 10 +- arch/arm/dts/rk3568-rock-3a.dts | 261 +++++++++++++++++++++++++++++++- 2 files changed, 262 insertions(+), 9 deletions(-) diff --git a/arch/arm/dts/rk3568-rock-3a-u-boot.dtsi b/arch/arm/dts/rk3568-rock-3a-u-boot.dtsi index b5ca23a82a2..04bbb01b5d5 100644 --- a/arch/arm/dts/rk3568-rock-3a-u-boot.dtsi +++ b/arch/arm/dts/rk3568-rock-3a-u-boot.dtsi @@ -9,12 +9,16 @@ / { chosen { stdout-path = &uart2; - u-boot,spl-boot-order = "same-as-spl", &sdmmc0; + u-boot,spl-boot-order = "same-as-spl", &sdmmc0, &sdhci; }; }; -&sdmmc0 { - status = "okay"; +&sdmmc2 { + status = "disabled"; +}; + +&uart1 { + status = "disabled"; }; &uart2 { diff --git a/arch/arm/dts/rk3568-rock-3a.dts b/arch/arm/dts/rk3568-rock-3a.dts index a2f2baa4ea9..917f5b2b8aa 100644 --- a/arch/arm/dts/rk3568-rock-3a.dts +++ b/arch/arm/dts/rk3568-rock-3a.dts @@ -1,22 +1,37 @@ // SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2021 Rockchip Electronics Co., Ltd. - * Copyright (c) 2023 Akash Gajjar - */ /dts-v1/; #include +#include #include +#include #include "rk3568.dtsi" / { model = "Radxa ROCK3 Model A"; compatible = "radxa,rock3a", "rockchip,rk3568"; + aliases { + ethernet0 = &gmac1; + mmc0 = &sdhci; + mmc1 = &sdmmc0; + }; + chosen: chosen { stdout-path = "serial2:1500000n8"; }; + hdmi-con { + compatible = "hdmi-connector"; + type = "a"; + + port { + hdmi_con_in: endpoint { + remote-endpoint = <&hdmi_out_con>; + }; + }; + }; + gmac1_clkin: external-gmac1-clock { compatible = "fixed-clock"; clock-frequency = <125000000>; @@ -24,13 +39,93 @@ #clock-cells = <0>; }; + leds { + compatible = "gpio-leds"; + + led_user: led-0 { + gpios = <&gpio0 RK_PB7 GPIO_ACTIVE_HIGH>; + function = LED_FUNCTION_HEARTBEAT; + color = ; + linux,default-trigger = "heartbeat"; + pinctrl-names = "default"; + pinctrl-0 = <&led_user_en>; + }; + }; + + rk809-sound { + compatible = "simple-audio-card"; + simple-audio-card,format = "i2s"; + simple-audio-card,name = "Analog RK809"; + simple-audio-card,mclk-fs = <256>; + + simple-audio-card,cpu { + sound-dai = <&i2s1_8ch>; + }; + + simple-audio-card,codec { + sound-dai = <&rk809>; + }; + }; + + sdio_pwrseq: sdio-pwrseq { + compatible = "mmc-pwrseq-simple"; + clocks = <&rk809 1>; + clock-names = "ext_clock"; + pinctrl-names = "default"; + pinctrl-0 = <&wifi_enable>; + post-power-on-delay-ms = <100>; + power-off-delay-us = <5000000>; + reset-gpios = <&gpio3 RK_PD4 GPIO_ACTIVE_LOW>; + }; + vcc12v_dcin: vcc12v-dcin-regulator { compatible = "regulator-fixed"; regulator-name = "vcc12v_dcin"; regulator-always-on; regulator-boot-on; - regulator-min-microvolt = <12000000>; - regulator-max-microvolt = <12000000>; + }; + + pcie30_avdd0v9: pcie30-avdd0v9-regulator { + compatible = "regulator-fixed"; + regulator-name = "pcie30_avdd0v9"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <900000>; + vin-supply = <&vcc3v3_sys>; + }; + + pcie30_avdd1v8: pcie30-avdd1v8-regulator { + compatible = "regulator-fixed"; + regulator-name = "pcie30_avdd1v8"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + vin-supply = <&vcc3v3_sys>; + }; + + /* pi6c pcie clock generator */ + vcc3v3_pi6c_03: vcc3v3-pi6c-03-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3_pi6c_03"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&vcc5v0_sys>; + }; + + vcc3v3_pcie: vcc3v3-pcie-regulator { + compatible = "regulator-fixed"; + enable-active-high; + gpios = <&gpio0 RK_PD4 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&pcie_enable_h>; + regulator-name = "vcc3v3_pcie"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&vcc5v0_sys>; }; vcc3v3_sys: vcc3v3-sys-regulator { @@ -91,6 +186,7 @@ enable-active-high; gpio = <&gpio0 RK_PA5 GPIO_ACTIVE_HIGH>; pinctrl-names = "default"; + pinctrl-0 = <&vcc5v0_usb_otg_en>; regulator-name = "vcc5v0_usb_otg"; regulator-min-microvolt = <5000000>; regulator-max-microvolt = <5000000>; @@ -164,7 +260,43 @@ clock_in_out = "input"; phy-handle = <&rgmii_phy1>; phy-mode = "rgmii-id"; + phy-supply = <&vcc_3v3>; + pinctrl-names = "default"; + pinctrl-0 = <&gmac1m1_miim + &gmac1m1_tx_bus2 + &gmac1m1_rx_bus2 + &gmac1m1_rgmii_clk + &gmac1m1_clkinout + &gmac1m1_rgmii_bus>; + status = "okay"; +}; + +&gpu { + mali-supply = <&vdd_gpu>; + status = "okay"; +}; + +&hdmi { + avdd-0v9-supply = <&vdda0v9_image>; + avdd-1v8-supply = <&vcca1v8_image>; pinctrl-names = "default"; + pinctrl-0 = <&hdmitx_scl &hdmitx_sda &hdmitxm1_cec>; + status = "okay"; +}; + +&hdmi_in { + hdmi_in_vp0: endpoint { + remote-endpoint = <&vp0_out_hdmi>; + }; +}; + +&hdmi_out { + hdmi_out_con: endpoint { + remote-endpoint = <&hdmi_con_in>; + }; +}; + +&hdmi_sound { status = "okay"; }; @@ -441,6 +573,13 @@ }; &i2s1_8ch { + pinctrl-names = "default"; + pinctrl-0 = <&i2s1m0_sclktx &i2s1m0_lrcktx &i2s1m0_sdi0 &i2s1m0_sdo0>; + rockchip,trcm-sync-tx-only; + status = "okay"; +}; + +&i2s2_2ch { rockchip,trcm-sync-tx-only; status = "okay"; }; @@ -457,6 +596,27 @@ }; }; +&pcie2x1 { + pinctrl-names = "default"; + pinctrl-0 = <&pcie_reset_h>; + reset-gpios = <&gpio3 RK_PC1 GPIO_ACTIVE_HIGH>; + vpcie3v3-supply = <&vcc3v3_pcie>; + status = "okay"; +}; + +&pcie30phy { + phy-supply = <&vcc3v3_pi6c_03>; + status = "okay"; +}; + +&pcie3x2 { + pinctrl-names = "default"; + pinctrl-0 = <&pcie30x2m1_pins>; + reset-gpios = <&gpio2 RK_PD6 GPIO_ACTIVE_HIGH>; + vpcie3v3-supply = <&vcc3v3_pcie>; + status = "okay"; +}; + &pinctrl { cam { vcc_cam_en: vcc_cam_en { @@ -551,6 +711,78 @@ status = "okay"; }; +&saradc { + vref-supply = <&vcca_1v8>; + status = "okay"; +}; + +&sdhci { + bus-width = <8>; + max-frequency = <200000000>; + non-removable; + pinctrl-names = "default"; + pinctrl-0 = <&emmc_bus8 &emmc_clk &emmc_cmd &emmc_datastrobe>; + vmmc-supply = <&vcc_3v3>; + vqmmc-supply = <&vcc_1v8>; + status = "okay"; +}; + +&sdmmc0 { + bus-width = <4>; + cap-sd-highspeed; + cd-gpios = <&gpio0 RK_PA4 GPIO_ACTIVE_LOW>; + disable-wp; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc0_bus4 &sdmmc0_clk &sdmmc0_cmd &sdmmc0_det>; + sd-uhs-sdr50; + vmmc-supply = <&vcc3v3_sd>; + vqmmc-supply = <&vccio_sd>; + status = "okay"; +}; + +&sdmmc2 { + bus-width = <4>; + disable-wp; + cap-sd-highspeed; + cap-sdio-irq; + keep-power-in-suspend; + mmc-pwrseq = <&sdio_pwrseq>; + non-removable; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc2m0_bus4 &sdmmc2m0_cmd &sdmmc2m0_clk>; + sd-uhs-sdr104; + vmmc-supply = <&vcc3v3_sys>; + vqmmc-supply = <&vcc_1v8>; + status = "okay"; +}; + +&tsadc { + rockchip,hw-tshut-mode = <1>; + rockchip,hw-tshut-polarity = <0>; + status = "okay"; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&uart1m0_xfer &uart1m0_ctsn &uart1m0_rtsn>; + uart-has-rtscts; + status = "okay"; + + bluetooth { + compatible = "brcm,bcm43438-bt"; + clocks = <&rk809 1>; + clock-names = "lpo"; + device-wakeup-gpios = <&gpio4 RK_PB5 GPIO_ACTIVE_HIGH>; + host-wakeup-gpios = <&gpio4 RK_PB4 GPIO_ACTIVE_HIGH>; + shutdown-gpios = <&gpio4 RK_PB2 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&bt_host_wake &bt_wake &bt_enable>; + vbat-supply = <&vcc3v3_sys>; + vddio-supply = <&vcc_1v8>; + /* vddio comes from regulator on module, use IO bank voltage instead */ + }; +}; + &uart2 { status = "okay"; }; @@ -607,3 +839,20 @@ phy-supply = <&vcc5v0_usb_host>; status = "okay"; }; + +&vop { + assigned-clocks = <&cru DCLK_VOP0>, <&cru DCLK_VOP1>; + assigned-clock-parents = <&pmucru PLL_HPLL>, <&cru PLL_VPLL>; + status = "okay"; +}; + +&vop_mmu { + status = "okay"; +}; + +&vp0 { + vp0_out_hdmi: endpoint@ROCKCHIP_VOP2_EP_HDMI0 { + reg = ; + remote-endpoint = <&hdmi_in_vp0>; + }; +}; -- cgit v1.3.1 From a67e219d0ca1b4b45ddb0cfb0afa2d1781262f62 Mon Sep 17 00:00:00 2001 From: Peter Geis Date: Tue, 14 Mar 2023 00:38:26 +0000 Subject: clk: rockchip: rk3568: Fix reset handler The reset handler for rk3568 is missing its private data. This leads to an abort when a reset is triggered. => reset resetting ... "Synchronous Abort" handler, esr 0x96000045 elr: 0000000000a2bc04 lr : 0000000000a2bbd4 (reloc) elr: 00000000eff9bc04 lr : 00000000eff9bbd4 x0 : 00000000fdd20000 x1 : 0000000014000001 x2 : 000000000000fdb9 x3 : 00000000edf77e88 x4 : 00000000edf50e78 x5 : 00000000edf77530 x6 : 000000000000001d x7 : 00000000edf8a1d0 x8 : 00000000ffffffd8 x9 : 0000000000000008 x10: 000000000000000d x11: 0000000000000006 x12: 000000000001869f x13: 0000000086c290c5 x14: 000000009118e878 x15: 0000000000000000 x16: 00000000eff9bbb8 x17: 0000000012f8c119 x18: 00000000edf50dc0 x19: 0000000000000000 x20: 0000000000000001 x21: 0000000000000000 x22: 00000000edf85900 x23: 0000000000000001 x24: 00000000effe8bbc x25: 0000000000000000 x26: 00000000edf85940 x27: 0000000000000000 x28: 0000000000000000 x29: 00000000edf3c8e0 Code: d65f03c0 d5033fbf b9400661 529d9502 (b8216802) Resetting CPU ... Add the missing dev_set_priv to the rk3568 clk driver to fix this. Fixes: 4a262feba3a5 ("rockchip: rk3568: add clock driver") Signed-off-by: Peter Geis Reviewed-by: Kever Yang Reviewed-by: Jagan Teki Tested-by: Jagan Teki # radxa-cm3 Signed-off-by: Jonas Karlman --- drivers/clk/rockchip/clk_rk3568.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/clk/rockchip/clk_rk3568.c b/drivers/clk/rockchip/clk_rk3568.c index 99c195b3afe..253b69504f9 100644 --- a/drivers/clk/rockchip/clk_rk3568.c +++ b/drivers/clk/rockchip/clk_rk3568.c @@ -14,6 +14,7 @@ #include #include #include +#include #include #include @@ -2937,6 +2938,7 @@ static int rk3568_clk_bind(struct udevice *dev) glb_srst_fst); priv->glb_srst_snd_value = offsetof(struct rk3568_cru, glb_srsr_snd); + dev_set_priv(sys_child, priv); } #if CONFIG_IS_ENABLED(RESET_ROCKCHIP) -- cgit v1.3.1 From 67a1d773e7ed1bbfe05ff02d13e56558e7203af5 Mon Sep 17 00:00:00 2001 From: Jonas Karlman Date: Tue, 14 Mar 2023 00:38:27 +0000 Subject: clk: rockchip: rk3588: Fix clk_aux16m in clock driver The rate and error value is not returned for aux16m clocks, fix this. Fixes: 7a474df74023 ("clk: rockchip: Add rk3588 clk support") Signed-off-by: Jonas Karlman Reviewed-by: Kever Yang --- drivers/clk/rockchip/clk_rk3588.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/clk/rockchip/clk_rk3588.c b/drivers/clk/rockchip/clk_rk3588.c index 5271d943483..a7df553e875 100644 --- a/drivers/clk/rockchip/clk_rk3588.c +++ b/drivers/clk/rockchip/clk_rk3588.c @@ -1558,7 +1558,7 @@ static ulong rk3588_clk_get_rate(struct clk *clk) #ifndef CONFIG_SPL_BUILD case CLK_AUX16M_0: case CLK_AUX16M_1: - rk3588_aux16m_get_clk(priv, clk->id); + rate = rk3588_aux16m_get_clk(priv, clk->id); break; case ACLK_VOP_ROOT: case ACLK_VOP: @@ -1707,7 +1707,7 @@ static ulong rk3588_clk_set_rate(struct clk *clk, ulong rate) #ifndef CONFIG_SPL_BUILD case CLK_AUX16M_0: case CLK_AUX16M_1: - rk3588_aux16m_set_clk(priv, clk->id, rate); + ret = rk3588_aux16m_set_clk(priv, clk->id, rate); break; case ACLK_VOP_ROOT: case ACLK_VOP: -- cgit v1.3.1 From e259f39a1282bb9a068ea497033487cb9b3800fa Mon Sep 17 00:00:00 2001 From: Jonas Karlman Date: Tue, 14 Mar 2023 00:38:30 +0000 Subject: rockchip: rk3588: Add boot device detection Enable SPL on RK3588 to detect which device it was booted from. Fixes use of same-as-spl in u-boot,spl-boot-order prop. Signed-off-by: Jonas Karlman Reviewed-by: Kever Yang --- arch/arm/mach-rockchip/rk3588/rk3588.c | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/arch/arm/mach-rockchip/rk3588/rk3588.c b/arch/arm/mach-rockchip/rk3588/rk3588.c index 2ee1db47671..18e67b5ca9b 100644 --- a/arch/arm/mach-rockchip/rk3588/rk3588.c +++ b/arch/arm/mach-rockchip/rk3588/rk3588.c @@ -8,6 +8,7 @@ #include #include #include +#include #include #include @@ -36,6 +37,12 @@ DECLARE_GLOBAL_DATA_PTR; #define BUS_IOC_GPIO2D_IOMUX_SEL_H 0x5c #define BUS_IOC_GPIO3A_IOMUX_SEL_L 0x60 +const char * const boot_devices[BROM_LAST_BOOTSOURCE + 1] = { + [BROM_BOOTSOURCE_EMMC] = "/mmc@fe2e0000", + [BROM_BOOTSOURCE_SPINOR] = "/spi@fe2b0000/flash@0", + [BROM_BOOTSOURCE_SD] = "/mmc@fe2c0000", +}; + static struct mm_region rk3588_mem_map[] = { { .virt = 0x0UL, -- cgit v1.3.1 From 42a502ad1ae23b923dfcf8c5caa0aa727efd4062 Mon Sep 17 00:00:00 2001 From: Jonas Karlman Date: Tue, 14 Mar 2023 00:38:31 +0000 Subject: rockchip: tinker-rk3288: Use common BOOT_TARGET_DEVICES Building U-Boot for Tinker Board with USB or NET Kconfig option disabled result in the following build error: In file included from include/configs/rk3288_common.h:29, from include/configs/tinker_rk3288.h:14, from include/config.h:3, from include/common.h:16, from env/common.c:10: include/config_distro_bootcmd.h:302:9: error: expected '}' before 'BOOT_TARGET_DEVICES_references_USB_without_CONFIG_CMD_USB' 302 | BOOT_TARGET_DEVICES_references_USB_without_CONFIG_CMD_USB | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ include/config_distro_bootcmd.h:302:9: note: in definition of macro 'BOOTENV_DEV_NAME_USB' 302 | BOOT_TARGET_DEVICES_references_USB_without_CONFIG_CMD_USB | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ include/configs/tinker_rk3288.h:21:9: note: in expansion of macro 'BOOTENV_DEV_NAME' 21 | func(USB, usb, 0) \ | ^~~~ include/config_distro_bootcmd.h:454:25: note: in expansion of macro 'BOOT_TARGET_DEVICES' 454 | "boot_targets=" BOOT_TARGET_DEVICES(BOOTENV_DEV_NAME) "\0" | ^~~~~~~~~~~~~~~~~~~ include/config_distro_bootcmd.h:474:9: note: in expansion of macro 'BOOTENV_BOOT_TARGETS' 474 | BOOTENV_BOOT_TARGETS \ | ^~~~~~~~~~~~~~~~~~~~ include/configs/rk3288_common.h:40:9: note: in expansion of macro 'BOOTENV' 40 | BOOTENV | ^~~~~~~ include/env_default.h:122:9: note: in expansion of macro 'CFG_EXTRA_ENV_SETTINGS' 122 | CFG_EXTRA_ENV_SETTINGS | ^~~~~~~~~~~~~~~~~~~~~~ In file included from env/common.c:32: include/env_default.h:29:36: note: to match this '{' 29 | const char default_environment[] = { | ^ make[2]: *** [scripts/Makefile.build:256: env/common.o] Error 1 The BOOT_TARGET_DEVICES defined in rockchip-common.h include the same devices as defined in tinker_rk3288.h, remove the board specific one to fix building with USB or NET option disabled. Signed-off-by: Jonas Karlman Reviewed-by: Kever Yang --- include/configs/tinker_rk3288.h | 9 --------- 1 file changed, 9 deletions(-) diff --git a/include/configs/tinker_rk3288.h b/include/configs/tinker_rk3288.h index 269ec529a34..053c9032e2d 100644 --- a/include/configs/tinker_rk3288.h +++ b/include/configs/tinker_rk3288.h @@ -13,13 +13,4 @@ #include -#undef BOOT_TARGET_DEVICES - -#define BOOT_TARGET_DEVICES(func) \ - func(MMC, mmc, 0) \ - func(MMC, mmc, 1) \ - func(USB, usb, 0) \ - func(PXE, pxe, na) \ - func(DHCP, dchp, na) - #endif -- cgit v1.3.1 From d11f0dac30215361aa046f593d003a7ea094e8a1 Mon Sep 17 00:00:00 2001 From: Jonas Karlman Date: Tue, 14 Mar 2023 00:38:32 +0000 Subject: mmc: rockchip_dw_mmc: Fix get_mmc_clk return value The get_mmc_clk ops is expected to set a clock rate and return the configured rate as an unsigned value. However, if clk_set_rate fails, e.g. using a fixed rate clock, a negative error value is returned. The mmc core will treat this as a valid unsigned rate and tries to configure a divider based on this bogus clock rate. Use 0 as the return value when setting clock rate fails, the mmc core will configure to use bypass mode instead of using a bogus divider. Signed-off-by: Jonas Karlman Reviewed-by: Kever Yang --- drivers/mmc/rockchip_dw_mmc.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/mmc/rockchip_dw_mmc.c b/drivers/mmc/rockchip_dw_mmc.c index 3661ce33143..72c820ee633 100644 --- a/drivers/mmc/rockchip_dw_mmc.c +++ b/drivers/mmc/rockchip_dw_mmc.c @@ -52,7 +52,7 @@ static uint rockchip_dwmmc_get_mmc_clk(struct dwmci_host *host, uint freq) ret = clk_set_rate(&priv->clk, freq); if (ret < 0) { debug("%s: err=%d\n", __func__, ret); - return ret; + return 0; } return freq; -- cgit v1.3.1 From 85db421cdbbc2ab60159d1477f24b80a941715b2 Mon Sep 17 00:00:00 2001 From: Jonas Karlman Date: Tue, 14 Mar 2023 00:38:34 +0000 Subject: rockchip: include: configs: Remove dangling comments This removes dangling comments that no longer serve a purpose and has been left after conversion of defines to Kconfig option. Signed-off-by: Jonas Karlman Reviewed-by: Kever Yang --- include/configs/rk3128_common.h | 4 ---- include/configs/rk3188_common.h | 5 ----- include/configs/rk3288_common.h | 2 -- include/configs/rk3328_common.h | 1 - include/configs/rk3399_common.h | 1 - include/configs/rockchip-common.h | 2 -- include/configs/rv1108_common.h | 2 -- include/configs/vyasa-rk3288.h | 6 ------ 8 files changed, 23 deletions(-) diff --git a/include/configs/rk3128_common.h b/include/configs/rk3128_common.h index 8aa17bfbd36..8736b14d101 100644 --- a/include/configs/rk3128_common.h +++ b/include/configs/rk3128_common.h @@ -12,13 +12,9 @@ #define CFG_IRAM_BASE 0x10080000 -/* RAW SD card / eMMC locations. */ - #define CFG_SYS_SDRAM_BASE 0x60000000 #define SDRAM_MAX_SIZE 0x80000000 -/* usb mass storage */ - #define ENV_MEM_LAYOUT_SETTINGS \ "scriptaddr=0x60500000\0" \ "pxefile_addr_r=0x60600000\0" \ diff --git a/include/configs/rk3188_common.h b/include/configs/rk3188_common.h index ac9195672fb..ebb421c6929 100644 --- a/include/configs/rk3188_common.h +++ b/include/configs/rk3188_common.h @@ -11,15 +11,10 @@ #define CFG_IRAM_BASE 0x10080000 -/* spl size 32kb sram - 2kb bootrom */ - #define CFG_SYS_SDRAM_BASE 0x60000000 #define SDRAM_BANK_SIZE (2UL << 30) #define SDRAM_MAX_SIZE 0x80000000 -/* usb otg */ - -/* usb host support */ #define ENV_MEM_LAYOUT_SETTINGS \ "scriptaddr=0x60000000\0" \ "pxefile_addr_r=0x60100000\0" \ diff --git a/include/configs/rk3288_common.h b/include/configs/rk3288_common.h index 5f29432be10..fa409c70c93 100644 --- a/include/configs/rk3288_common.h +++ b/include/configs/rk3288_common.h @@ -13,8 +13,6 @@ #define CFG_IRAM_BASE 0xff700000 -/* RAW SD card / eMMC locations. */ - #define CFG_SYS_SDRAM_BASE 0 #define SDRAM_BANK_SIZE (2UL << 30) #define SDRAM_MAX_SIZE 0xfe000000 diff --git a/include/configs/rk3328_common.h b/include/configs/rk3328_common.h index 24b21c024de..e565ccff897 100644 --- a/include/configs/rk3328_common.h +++ b/include/configs/rk3328_common.h @@ -10,7 +10,6 @@ #define CFG_IRAM_BASE 0xff090000 -/* FAT sd card locations. */ #define CFG_SYS_SDRAM_BASE 0 #define SDRAM_MAX_SIZE 0xff000000 diff --git a/include/configs/rk3399_common.h b/include/configs/rk3399_common.h index 3ef9ffa2e9c..04dcbf20bcb 100644 --- a/include/configs/rk3399_common.h +++ b/include/configs/rk3399_common.h @@ -10,7 +10,6 @@ #define CFG_IRAM_BASE 0xff8c0000 -/* FAT sd card locations. */ #define CFG_SYS_SDRAM_BASE 0 #define SDRAM_MAX_SIZE 0xf8000000 diff --git a/include/configs/rockchip-common.h b/include/configs/rockchip-common.h index b7c5c663439..18544d75acc 100644 --- a/include/configs/rockchip-common.h +++ b/include/configs/rockchip-common.h @@ -11,8 +11,6 @@ #define CFG_CPUID_OFFSET 0x7 #endif -/* ((CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR - 64) * 512) */ - #ifndef CONFIG_SPL_BUILD /* First try to boot from SD (index 1), then eMMC (index 0) */ diff --git a/include/configs/rv1108_common.h b/include/configs/rv1108_common.h index 63551b47e20..050d37bff0b 100644 --- a/include/configs/rv1108_common.h +++ b/include/configs/rv1108_common.h @@ -17,8 +17,6 @@ #define CFG_SYS_SDRAM_BASE 0x60000000 -/* rockchip ohci host driver */ - #define ENV_MEM_LAYOUT_SETTINGS \ "scriptaddr=0x60000000\0" \ "fdt_addr_r=0x61f00000\0" \ diff --git a/include/configs/vyasa-rk3288.h b/include/configs/vyasa-rk3288.h index e8c1013a71a..81ff61bf7a6 100644 --- a/include/configs/vyasa-rk3288.h +++ b/include/configs/vyasa-rk3288.h @@ -20,10 +20,4 @@ #define BOOT_TARGET_DEVICES(func) \ func(MMC, mmc, 1) \ -#ifndef CONFIG_TPL_BUILD -/* Falcon Mode */ - -/* Falcon Mode - MMC support: args@16MB kernel@17MB */ -#endif - #endif -- cgit v1.3.1 From 981f0545d328b4b757c02465792b499c94bcbc00 Mon Sep 17 00:00:00 2001 From: Jonas Karlman Date: Tue, 14 Mar 2023 00:38:37 +0000 Subject: rockchip: include: configs: Remove unused SDRAM_BANK_SIZE Remove unused SDRAM_BANK_SIZE define. Signed-off-by: Jonas Karlman Reviewed-by: Kever Yang --- include/configs/evb_rk3328.h | 2 -- include/configs/evb_rk3399.h | 2 -- include/configs/pinebook-pro-rk3399.h | 2 -- include/configs/pinephone-pro-rk3399.h | 2 -- include/configs/puma_rk3399.h | 2 -- include/configs/px30_common.h | 1 - include/configs/rk3188_common.h | 1 - include/configs/rk322x_common.h | 1 - include/configs/rk3288_common.h | 1 - include/configs/rk3308_common.h | 1 - include/configs/roc-pc-rk3399.h | 2 -- include/configs/rock960_rk3399.h | 1 - include/configs/rockpro64_rk3399.h | 1 - 13 files changed, 19 deletions(-) diff --git a/include/configs/evb_rk3328.h b/include/configs/evb_rk3328.h index cac613d021a..d10e5b1d2e0 100644 --- a/include/configs/evb_rk3328.h +++ b/include/configs/evb_rk3328.h @@ -8,6 +8,4 @@ #include -#define SDRAM_BANK_SIZE (2UL << 30) - #endif diff --git a/include/configs/evb_rk3399.h b/include/configs/evb_rk3399.h index b7e850370b3..70ab587795e 100644 --- a/include/configs/evb_rk3399.h +++ b/include/configs/evb_rk3399.h @@ -13,6 +13,4 @@ #include -#define SDRAM_BANK_SIZE (2UL << 30) - #endif diff --git a/include/configs/pinebook-pro-rk3399.h b/include/configs/pinebook-pro-rk3399.h index 241dc39be00..141ffcd036b 100644 --- a/include/configs/pinebook-pro-rk3399.h +++ b/include/configs/pinebook-pro-rk3399.h @@ -14,6 +14,4 @@ #include -#define SDRAM_BANK_SIZE (2UL << 30) - #endif diff --git a/include/configs/pinephone-pro-rk3399.h b/include/configs/pinephone-pro-rk3399.h index 78017d6bcc3..9cd44473439 100644 --- a/include/configs/pinephone-pro-rk3399.h +++ b/include/configs/pinephone-pro-rk3399.h @@ -14,6 +14,4 @@ #include -#define SDRAM_BANK_SIZE (2UL << 30) - #endif diff --git a/include/configs/puma_rk3399.h b/include/configs/puma_rk3399.h index 23de326e720..969acc89b93 100644 --- a/include/configs/puma_rk3399.h +++ b/include/configs/puma_rk3399.h @@ -8,6 +8,4 @@ #include -#define SDRAM_BANK_SIZE (2UL << 30) - #endif diff --git a/include/configs/px30_common.h b/include/configs/px30_common.h index c0896e5f628..8df481b0978 100644 --- a/include/configs/px30_common.h +++ b/include/configs/px30_common.h @@ -15,7 +15,6 @@ #define CFG_SYS_SDRAM_BASE 0 #define SDRAM_MAX_SIZE 0xff000000 -#define SDRAM_BANK_SIZE (2UL << 30) #define ENV_MEM_LAYOUT_SETTINGS \ "scriptaddr=0x00500000\0" \ diff --git a/include/configs/rk3188_common.h b/include/configs/rk3188_common.h index ebb421c6929..fcb274565e9 100644 --- a/include/configs/rk3188_common.h +++ b/include/configs/rk3188_common.h @@ -12,7 +12,6 @@ #define CFG_IRAM_BASE 0x10080000 #define CFG_SYS_SDRAM_BASE 0x60000000 -#define SDRAM_BANK_SIZE (2UL << 30) #define SDRAM_MAX_SIZE 0x80000000 #define ENV_MEM_LAYOUT_SETTINGS \ diff --git a/include/configs/rk322x_common.h b/include/configs/rk322x_common.h index fcaf9c52c4b..39a40f4e2d1 100644 --- a/include/configs/rk322x_common.h +++ b/include/configs/rk322x_common.h @@ -13,7 +13,6 @@ #define CFG_IRAM_BASE 0x10080000 #define CFG_SYS_SDRAM_BASE 0x60000000 -#define SDRAM_BANK_SIZE (512UL << 20UL) #define SDRAM_MAX_SIZE 0x80000000 #define ENV_MEM_LAYOUT_SETTINGS \ diff --git a/include/configs/rk3288_common.h b/include/configs/rk3288_common.h index fa409c70c93..71d2426d72a 100644 --- a/include/configs/rk3288_common.h +++ b/include/configs/rk3288_common.h @@ -14,7 +14,6 @@ #define CFG_IRAM_BASE 0xff700000 #define CFG_SYS_SDRAM_BASE 0 -#define SDRAM_BANK_SIZE (2UL << 30) #define SDRAM_MAX_SIZE 0xfe000000 #define ENV_MEM_LAYOUT_SETTINGS \ diff --git a/include/configs/rk3308_common.h b/include/configs/rk3308_common.h index 55a0dfecb21..ba9ee112e2d 100644 --- a/include/configs/rk3308_common.h +++ b/include/configs/rk3308_common.h @@ -12,7 +12,6 @@ #define CFG_SYS_SDRAM_BASE 0 #define SDRAM_MAX_SIZE 0xff000000 -#define SDRAM_BANK_SIZE (2UL << 30) #define ENV_MEM_LAYOUT_SETTINGS \ "scriptaddr=0x00500000\0" \ diff --git a/include/configs/roc-pc-rk3399.h b/include/configs/roc-pc-rk3399.h index 59fe22289cf..f99871cb9fc 100644 --- a/include/configs/roc-pc-rk3399.h +++ b/include/configs/roc-pc-rk3399.h @@ -13,6 +13,4 @@ #include -#define SDRAM_BANK_SIZE (2UL << 30) - #endif diff --git a/include/configs/rock960_rk3399.h b/include/configs/rock960_rk3399.h index 6099d2fa55a..b85978115f5 100644 --- a/include/configs/rock960_rk3399.h +++ b/include/configs/rock960_rk3399.h @@ -13,5 +13,4 @@ #include -#define SDRAM_BANK_SIZE (2UL << 30) #endif diff --git a/include/configs/rockpro64_rk3399.h b/include/configs/rockpro64_rk3399.h index 9195b9b99e4..5381efac3f6 100644 --- a/include/configs/rockpro64_rk3399.h +++ b/include/configs/rockpro64_rk3399.h @@ -13,5 +13,4 @@ #include -#define SDRAM_BANK_SIZE (2UL << 30) #endif -- cgit v1.3.1 From 4340771323fc8cc9eee5508ffabbd48d0d83c27a Mon Sep 17 00:00:00 2001 From: Vasily Khoruzhick Date: Tue, 7 Mar 2023 21:16:10 -0800 Subject: clk: rockchip: rk3568: add stubs for CLK_PCIEPHY_REF clocks Device tree contains assigned-clock-rates property for these, but default value will work just fine Reviewed-by: Kever Yang Signed-off-by: Vasily Khoruzhick --- drivers/clk/rockchip/clk_rk3568.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/clk/rockchip/clk_rk3568.c b/drivers/clk/rockchip/clk_rk3568.c index 253b69504f9..1c6adc56f91 100644 --- a/drivers/clk/rockchip/clk_rk3568.c +++ b/drivers/clk/rockchip/clk_rk3568.c @@ -425,6 +425,9 @@ static ulong rk3568_pmuclk_set_rate(struct clk *clk, ulong rate) case PCLK_PMU: ret = rk3568_pmu_set_pmuclk(priv, rate); break; + case CLK_PCIEPHY0_REF: + case CLK_PCIEPHY1_REF: + return 0; default: return -ENOENT; } -- cgit v1.3.1 From 9fe2e4ab93ea34706dad615084ba9699a81fbcf8 Mon Sep 17 00:00:00 2001 From: Vasily Khoruzhick Date: Tue, 7 Mar 2023 14:08:27 -0800 Subject: Revert "arm64: dts: rk356x-u-boot: Drop combphy1 assigned-clocks/rates" This reverts commit 5bec4b0de7851a254fb4447b3599a60f95550141. Signed-off-by: Vasily Khoruzhick Reviewed-by: Kever Yang --- arch/arm/dts/rk356x-u-boot.dtsi | 5 ----- 1 file changed, 5 deletions(-) diff --git a/arch/arm/dts/rk356x-u-boot.dtsi b/arch/arm/dts/rk356x-u-boot.dtsi index 04a7b0a0f66..6eef99e6f75 100644 --- a/arch/arm/dts/rk356x-u-boot.dtsi +++ b/arch/arm/dts/rk356x-u-boot.dtsi @@ -34,11 +34,6 @@ }; }; -&combphy1 { - /delete-property/ assigned-clocks; - /delete-property/ assigned-clock-rates; -}; - &cru { u-boot,dm-pre-reloc; status = "okay"; -- cgit v1.3.1 From 2321a991bbb5f0de0781df09d332ee068426e264 Mon Sep 17 00:00:00 2001 From: Vasily Khoruzhick Date: Wed, 8 Mar 2023 17:28:30 -0800 Subject: rockchip: sdhci: rk3568: bypass DLL when clk <= 52 MHz For Rockchip platform, DLL bypass bit and start bit need to be set if DLL is not locked. With this change applied eMMC in my NanoPi R5S can run at 52 MHz. Based on linux commit b75a52b0dda3 ("mmc: sdhci-of-dwcmshc: Update DLL and pre-change delay for rockchip platform") Signed-off-by: Vasily Khoruzhick Reviewed-by: Kever Yang --- drivers/mmc/rockchip_sdhci.c | 15 +++++++++++---- 1 file changed, 11 insertions(+), 4 deletions(-) diff --git a/drivers/mmc/rockchip_sdhci.c b/drivers/mmc/rockchip_sdhci.c index 9608770d4ec..e1409dd2c74 100644 --- a/drivers/mmc/rockchip_sdhci.c +++ b/drivers/mmc/rockchip_sdhci.c @@ -61,6 +61,7 @@ #define DWCMSHC_EMMC_DLL_RXCLK 0x804 #define DWCMSHC_EMMC_DLL_TXCLK 0x808 #define DWCMSHC_EMMC_DLL_STRBIN 0x80c +#define DECMSHC_EMMC_DLL_CMDOUT 0x810 #define DWCMSHC_EMMC_DLL_STATUS0 0x840 #define DWCMSHC_EMMC_DLL_STATUS1 0x844 #define DWCMSHC_EMMC_DLL_START BIT(0) @@ -69,6 +70,7 @@ #define DWCMSHC_EMMC_DLL_START_DEFAULT 5 #define DWCMSHC_EMMC_DLL_INC_VALUE 2 #define DWCMSHC_EMMC_DLL_INC 8 +#define DWCMSHC_EMMC_DLL_BYPASS BIT(24) #define DWCMSHC_EMMC_DLL_DLYENA BIT(27) #define DLL_TXCLK_TAPNUM_DEFAULT 0xA @@ -83,6 +85,7 @@ #define DWCMSHC_EMMC_DLL_TIMEOUT BIT(9) #define DLL_RXCLK_NO_INVERTER 1 #define DLL_RXCLK_INVERTER 0 +#define DLL_RXCLK_ORI_GATE BIT(31) #define DWCMSHC_ENHANCED_STROBE BIT(8) #define DLL_LOCK_WO_TMOUT(x) \ ((((x) & DWCMSHC_EMMC_DLL_LOCKED) == DWCMSHC_EMMC_DLL_LOCKED) && \ @@ -348,10 +351,14 @@ static int rk3568_sdhci_emmc_set_clock(struct sdhci_host *host, unsigned int clo DLL_STRBIN_TAPNUM_FROM_SW; sdhci_writel(host, extra, DWCMSHC_EMMC_DLL_STRBIN); } else { - /* reset the clock phase when the frequency is lower than 100MHz */ - sdhci_writel(host, 0, DWCMSHC_EMMC_DLL_CTRL); - extra = DLL_RXCLK_NO_INVERTER << DWCMSHC_EMMC_DLL_RXCLK_SRCSEL; - sdhci_writel(host, extra, DWCMSHC_EMMC_DLL_RXCLK); + /* + * Disable DLL and reset both of sample and drive clock. + * The bypass bit and start bit need to be set if DLL is not locked. + */ + sdhci_writel(host, DWCMSHC_EMMC_DLL_BYPASS | DWCMSHC_EMMC_DLL_START, + DWCMSHC_EMMC_DLL_CTRL); + sdhci_writel(host, DLL_RXCLK_ORI_GATE, DWCMSHC_EMMC_DLL_RXCLK); + sdhci_writel(host, 0, DECMSHC_EMMC_DLL_CMDOUT); sdhci_writel(host, 0, DWCMSHC_EMMC_DLL_TXCLK); /* * Before switching to hs400es mode, the driver will enable -- cgit v1.3.1 From 791c7ac79274e2c3aa316da90fb3cc2411d5c5e8 Mon Sep 17 00:00:00 2001 From: Johan Jonker Date: Tue, 7 Mar 2023 16:30:58 +0100 Subject: rockchip: timer: rockchip_timer: fix compatible and driver name In the binding for the Rockchip timer the compatible string consists of a SoC orientated string and a fall back string "rockchip,rk3288-timer", so remove all unneeded ones and fix driver name. Signed-off-by: Johan Jonker Reviewed-by: Kever Yang --- drivers/timer/rockchip_timer.c | 8 +++----- 1 file changed, 3 insertions(+), 5 deletions(-) diff --git a/drivers/timer/rockchip_timer.c b/drivers/timer/rockchip_timer.c index 62eacb98689..e66c49aa6bb 100644 --- a/drivers/timer/rockchip_timer.c +++ b/drivers/timer/rockchip_timer.c @@ -20,7 +20,7 @@ DECLARE_GLOBAL_DATA_PTR; #if CONFIG_IS_ENABLED(OF_PLATDATA) struct rockchip_timer_plat { - struct dtd_rockchip_rk3368_timer dtd; + struct dtd_rockchip_rk3288_timer dtd; }; #endif @@ -152,14 +152,12 @@ static const struct timer_ops rockchip_timer_ops = { }; static const struct udevice_id rockchip_timer_ids[] = { - { .compatible = "rockchip,rk3188-timer" }, { .compatible = "rockchip,rk3288-timer" }, - { .compatible = "rockchip,rk3368-timer" }, {} }; -U_BOOT_DRIVER(rockchip_rk3368_timer) = { - .name = "rockchip_rk3368_timer", +U_BOOT_DRIVER(rockchip_rk3288_timer) = { + .name = "rockchip_rk3288_timer", .id = UCLASS_TIMER, .of_match = rockchip_timer_ids, .probe = rockchip_timer_probe, -- cgit v1.3.1 From d35a1392c5d17e067d16b7b096565b16af495f34 Mon Sep 17 00:00:00 2001 From: Johan Jonker Date: Tue, 7 Mar 2023 16:32:00 +0100 Subject: arm: dts: rockchip: rk3188-radxarock-u-boot: remove timer compatible replacement The Rockchip timer driver has been renamed after the fall back compatible. There's no need to replace the timer compatible in rk3188-radxarock-u-boot.dtsi anymore, so remove. Signed-off-by: Johan Jonker Reviewed-by: Kever Yang --- arch/arm/dts/rk3188-radxarock-u-boot.dtsi | 1 - 1 file changed, 1 deletion(-) diff --git a/arch/arm/dts/rk3188-radxarock-u-boot.dtsi b/arch/arm/dts/rk3188-radxarock-u-boot.dtsi index 9c9016de1bc..de29959827c 100644 --- a/arch/arm/dts/rk3188-radxarock-u-boot.dtsi +++ b/arch/arm/dts/rk3188-radxarock-u-boot.dtsi @@ -52,7 +52,6 @@ }; &timer3 { - compatible = "rockchip,rk3368-timer", "rockchip,rk3288-timer"; clock-frequency = <24000000>; u-boot,dm-spl; }; -- cgit v1.3.1