From 85c9a7ba8c8dcac3fc01bd6af21a93b65d496621 Mon Sep 17 00:00:00 2001 From: Jaehoon Chung Date: Fri, 6 Nov 2020 14:57:47 +0900 Subject: phy: meson-g12a-usb2: fix the potential build warning Fix the potential build warning. Signed-off-by: Jaehoon Chung Signed-off-by: Neil Armstrong --- drivers/phy/meson-g12a-usb2.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/phy/meson-g12a-usb2.c b/drivers/phy/meson-g12a-usb2.c index a1e62197586..447ce7283db 100644 --- a/drivers/phy/meson-g12a-usb2.c +++ b/drivers/phy/meson-g12a-usb2.c @@ -66,10 +66,10 @@ struct phy_meson_g12a_usb2_priv { static int phy_meson_g12a_usb2_power_on(struct phy *phy) { +#if CONFIG_IS_ENABLED(DM_REGULATOR) struct udevice *dev = phy->dev; struct phy_meson_g12a_usb2_priv *priv = dev_get_priv(dev); -#if CONFIG_IS_ENABLED(DM_REGULATOR) if (priv->phy_supply) { int ret = regulator_set_enable(priv->phy_supply, true); if (ret) @@ -82,10 +82,10 @@ static int phy_meson_g12a_usb2_power_on(struct phy *phy) static int phy_meson_g12a_usb2_power_off(struct phy *phy) { +#if CONFIG_IS_ENABLED(DM_REGULATOR) struct udevice *dev = phy->dev; struct phy_meson_g12a_usb2_priv *priv = dev_get_priv(dev); -#if CONFIG_IS_ENABLED(DM_REGULATOR) if (priv->phy_supply) { int ret = regulator_set_enable(priv->phy_supply, false); if (ret) { -- cgit v1.3.1 From fe76c4207e4c0d63262896e31123c40d61ce98b5 Mon Sep 17 00:00:00 2001 From: Jaehoon Chung Date: Fri, 6 Nov 2020 14:57:48 +0900 Subject: video: meson: meson_dw_hdmi: fix the potential build warning Fix the potential build warning. Signed-off-by: Jaehoon Chung Signed-off-by: Neil Armstrong --- drivers/video/meson/meson_dw_hdmi.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/video/meson/meson_dw_hdmi.c b/drivers/video/meson/meson_dw_hdmi.c index 7b2ff94eba5..5d74f7f1a74 100644 --- a/drivers/video/meson/meson_dw_hdmi.c +++ b/drivers/video/meson/meson_dw_hdmi.c @@ -379,7 +379,9 @@ static int meson_dw_hdmi_probe(struct udevice *dev) struct meson_dw_hdmi *priv = dev_get_priv(dev); struct reset_ctl_bulk resets; struct clk_bulk clocks; +#if CONFIG_IS_ENABLED(DM_REGULATOR) struct udevice *supply; +#endif int ret; priv->dev = dev; -- cgit v1.3.1 From b6a71e26c9caf0d2adbdbbd823498a006b994179 Mon Sep 17 00:00:00 2001 From: Neil Armstrong Date: Mon, 9 Nov 2020 14:30:01 +0100 Subject: ARM: mach-meson: update SoC IDs Update From Linux commits - 240051cb833b ("soc: amlogic: meson-gx-socinfo: Add A1 and A113L IDs") - 1d7c541b8a5b ("soc: amlogic: meson-gx-socinfo: Add S905X3 ID for VIM3L") - fdfc6997bd08 ("soc: amlogic: meson-gx-socinfo: Fix S905D3 ID for VIM3L") - d16d0481e6ba ("soc: amlogic: meson-gx-socinfo: Fix S905X3 and S905D3 ID's") Signed-off-by: Neil Armstrong --- arch/arm/mach-meson/board-info.c | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/arch/arm/mach-meson/board-info.c b/arch/arm/mach-meson/board-info.c index 3abb27e03b4..e61d1adb10f 100644 --- a/arch/arm/mach-meson/board-info.c +++ b/arch/arm/mach-meson/board-info.c @@ -38,6 +38,7 @@ static const struct meson_gx_soc_id { { "G12A", 0x28 }, { "G12B", 0x29 }, { "SM1", 0x2b }, + { "A1", 0x2c }, }; static const struct meson_gx_package_id { @@ -65,7 +66,11 @@ static const struct meson_gx_package_id { { "S905X2", 0x28, 0x40, 0xf0 }, { "A311D", 0x29, 0x10, 0xf0 }, { "S922X", 0x29, 0x40, 0xf0 }, - { "S905X3", 0x2b, 0x5, 0xf }, + { "S905D3", 0x2b, 0x4, 0xf5 }, + { "S905X3", 0x2b, 0x5, 0xf5 }, + { "S905X3", 0x2b, 0x10, 0x3f }, + { "S905D3", 0x2b, 0x30, 0x3f }, + { "A113L", 0x2c, 0x0, 0xf8 }, }; DECLARE_GLOBAL_DATA_PTR; -- cgit v1.3.1 From 77863d43eb2b40319619bbb4f781270d8f027189 Mon Sep 17 00:00:00 2001 From: Neil Armstrong Date: Wed, 11 Nov 2020 08:22:09 +0900 Subject: mmc: meson-gx: move arch header to local header Move the asm/arch-meson/sd_emmc.h to a local meson_gx_mmc.h, remove the useless if/then and fix the meson_gx_mmc.c include. Signed-off-by: Neil Armstrong --- arch/arm/include/asm/arch-meson/sd_emmc.h | 92 ------------------------------- drivers/mmc/meson_gx_mmc.c | 2 +- drivers/mmc/meson_gx_mmc.h | 89 ++++++++++++++++++++++++++++++ 3 files changed, 90 insertions(+), 93 deletions(-) delete mode 100644 arch/arm/include/asm/arch-meson/sd_emmc.h create mode 100644 drivers/mmc/meson_gx_mmc.h diff --git a/arch/arm/include/asm/arch-meson/sd_emmc.h b/arch/arm/include/asm/arch-meson/sd_emmc.h deleted file mode 100644 index 1e9f8cf498b..00000000000 --- a/arch/arm/include/asm/arch-meson/sd_emmc.h +++ /dev/null @@ -1,92 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2016 Carlo Caione - */ - -#ifndef __SD_EMMC_H__ -#define __SD_EMMC_H__ - -#include -#ifndef __ASSEMBLY__ -#include -#endif - - -#define SDIO_PORT_A 0 -#define SDIO_PORT_B 1 -#define SDIO_PORT_C 2 - -#define SD_EMMC_CLKSRC_24M 24000000 /* 24 MHz */ -#define SD_EMMC_CLKSRC_DIV2 1000000000 /* 1 GHz */ - -#define MESON_SD_EMMC_CLOCK 0x00 -#define CLK_MAX_DIV 63 -#define CLK_SRC_24M (0 << 6) -#define CLK_SRC_DIV2 (1 << 6) -#define CLK_CO_PHASE_000 (0 << 8) -#define CLK_CO_PHASE_090 (1 << 8) -#define CLK_CO_PHASE_180 (2 << 8) -#define CLK_CO_PHASE_270 (3 << 8) -#define CLK_TX_PHASE_000 (0 << 10) -#define CLK_TX_PHASE_090 (1 << 10) -#define CLK_TX_PHASE_180 (2 << 10) -#define CLK_TX_PHASE_270 (3 << 10) -#define CLK_ALWAYS_ON BIT(24) - -#define MESON_SD_EMMC_CFG 0x44 -#define CFG_BUS_WIDTH_MASK GENMASK(1, 0) -#define CFG_BUS_WIDTH_1 0 -#define CFG_BUS_WIDTH_4 1 -#define CFG_BUS_WIDTH_8 2 -#define CFG_BL_LEN_MASK GENMASK(7, 4) -#define CFG_BL_LEN_SHIFT 4 -#define CFG_BL_LEN_512 (9 << 4) -#define CFG_RESP_TIMEOUT_MASK GENMASK(11, 8) -#define CFG_RESP_TIMEOUT_256 (8 << 8) -#define CFG_RC_CC_MASK GENMASK(15, 12) -#define CFG_RC_CC_16 (4 << 12) -#define CFG_SDCLK_ALWAYS_ON BIT(18) -#define CFG_AUTO_CLK BIT(23) - -#define MESON_SD_EMMC_STATUS 0x48 -#define STATUS_MASK GENMASK(15, 0) -#define STATUS_ERR_MASK GENMASK(12, 0) -#define STATUS_RXD_ERR_MASK GENMASK(7, 0) -#define STATUS_TXD_ERR BIT(8) -#define STATUS_DESC_ERR BIT(9) -#define STATUS_RESP_ERR BIT(10) -#define STATUS_RESP_TIMEOUT BIT(11) -#define STATUS_DESC_TIMEOUT BIT(12) -#define STATUS_END_OF_CHAIN BIT(13) - -#define MESON_SD_EMMC_IRQ_EN 0x4c - -#define MESON_SD_EMMC_CMD_CFG 0x50 -#define CMD_CFG_LENGTH_MASK GENMASK(8, 0) -#define CMD_CFG_BLOCK_MODE BIT(9) -#define CMD_CFG_R1B BIT(10) -#define CMD_CFG_END_OF_CHAIN BIT(11) -#define CMD_CFG_TIMEOUT_4S (12 << 12) -#define CMD_CFG_NO_RESP BIT(16) -#define CMD_CFG_DATA_IO BIT(18) -#define CMD_CFG_DATA_WR BIT(19) -#define CMD_CFG_RESP_NOCRC BIT(20) -#define CMD_CFG_RESP_128 BIT(21) -#define CMD_CFG_CMD_INDEX_SHIFT 24 -#define CMD_CFG_OWNER BIT(31) - -#define MESON_SD_EMMC_CMD_ARG 0x54 -#define MESON_SD_EMMC_CMD_DAT 0x58 -#define MESON_SD_EMMC_CMD_RSP 0x5c -#define MESON_SD_EMMC_CMD_RSP1 0x60 -#define MESON_SD_EMMC_CMD_RSP2 0x64 -#define MESON_SD_EMMC_CMD_RSP3 0x68 - -struct meson_mmc_platdata { - struct mmc_config cfg; - struct mmc mmc; - void *regbase; - void *w_buf; -}; - -#endif diff --git a/drivers/mmc/meson_gx_mmc.c b/drivers/mmc/meson_gx_mmc.c index 719dd1e5e57..eedebb317b5 100644 --- a/drivers/mmc/meson_gx_mmc.c +++ b/drivers/mmc/meson_gx_mmc.c @@ -13,9 +13,9 @@ #include #include #include -#include #include #include +#include "meson_gx_mmc.h" static inline void *get_regbase(const struct mmc *mmc) { diff --git a/drivers/mmc/meson_gx_mmc.h b/drivers/mmc/meson_gx_mmc.h new file mode 100644 index 00000000000..b4544b55628 --- /dev/null +++ b/drivers/mmc/meson_gx_mmc.h @@ -0,0 +1,89 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * (C) Copyright 2016 Carlo Caione + */ + +#ifndef __MESON_GX_MMC_H__ +#define __MESON_GX_MMC_H__ + +#include +#include + +#define SDIO_PORT_A 0 +#define SDIO_PORT_B 1 +#define SDIO_PORT_C 2 + +#define SD_EMMC_CLKSRC_24M 24000000 /* 24 MHz */ +#define SD_EMMC_CLKSRC_DIV2 1000000000 /* 1 GHz */ + +#define MESON_SD_EMMC_CLOCK 0x00 +#define CLK_MAX_DIV 63 +#define CLK_SRC_24M (0 << 6) +#define CLK_SRC_DIV2 (1 << 6) +#define CLK_CO_PHASE_000 (0 << 8) +#define CLK_CO_PHASE_090 (1 << 8) +#define CLK_CO_PHASE_180 (2 << 8) +#define CLK_CO_PHASE_270 (3 << 8) +#define CLK_TX_PHASE_000 (0 << 10) +#define CLK_TX_PHASE_090 (1 << 10) +#define CLK_TX_PHASE_180 (2 << 10) +#define CLK_TX_PHASE_270 (3 << 10) +#define CLK_ALWAYS_ON BIT(24) + +#define MESON_SD_EMMC_CFG 0x44 +#define CFG_BUS_WIDTH_MASK GENMASK(1, 0) +#define CFG_BUS_WIDTH_1 0 +#define CFG_BUS_WIDTH_4 1 +#define CFG_BUS_WIDTH_8 2 +#define CFG_BL_LEN_MASK GENMASK(7, 4) +#define CFG_BL_LEN_SHIFT 4 +#define CFG_BL_LEN_512 (9 << 4) +#define CFG_RESP_TIMEOUT_MASK GENMASK(11, 8) +#define CFG_RESP_TIMEOUT_256 (8 << 8) +#define CFG_RC_CC_MASK GENMASK(15, 12) +#define CFG_RC_CC_16 (4 << 12) +#define CFG_SDCLK_ALWAYS_ON BIT(18) +#define CFG_AUTO_CLK BIT(23) + +#define MESON_SD_EMMC_STATUS 0x48 +#define STATUS_MASK GENMASK(15, 0) +#define STATUS_ERR_MASK GENMASK(12, 0) +#define STATUS_RXD_ERR_MASK GENMASK(7, 0) +#define STATUS_TXD_ERR BIT(8) +#define STATUS_DESC_ERR BIT(9) +#define STATUS_RESP_ERR BIT(10) +#define STATUS_RESP_TIMEOUT BIT(11) +#define STATUS_DESC_TIMEOUT BIT(12) +#define STATUS_END_OF_CHAIN BIT(13) + +#define MESON_SD_EMMC_IRQ_EN 0x4c + +#define MESON_SD_EMMC_CMD_CFG 0x50 +#define CMD_CFG_LENGTH_MASK GENMASK(8, 0) +#define CMD_CFG_BLOCK_MODE BIT(9) +#define CMD_CFG_R1B BIT(10) +#define CMD_CFG_END_OF_CHAIN BIT(11) +#define CMD_CFG_TIMEOUT_4S (12 << 12) +#define CMD_CFG_NO_RESP BIT(16) +#define CMD_CFG_DATA_IO BIT(18) +#define CMD_CFG_DATA_WR BIT(19) +#define CMD_CFG_RESP_NOCRC BIT(20) +#define CMD_CFG_RESP_128 BIT(21) +#define CMD_CFG_CMD_INDEX_SHIFT 24 +#define CMD_CFG_OWNER BIT(31) + +#define MESON_SD_EMMC_CMD_ARG 0x54 +#define MESON_SD_EMMC_CMD_DAT 0x58 +#define MESON_SD_EMMC_CMD_RSP 0x5c +#define MESON_SD_EMMC_CMD_RSP1 0x60 +#define MESON_SD_EMMC_CMD_RSP2 0x64 +#define MESON_SD_EMMC_CMD_RSP3 0x68 + +struct meson_mmc_platdata { + struct mmc_config cfg; + struct mmc mmc; + void *regbase; + void *w_buf; +}; + +#endif -- cgit v1.3.1 From 0dbb54eb3257c243c7968f967a6b183b1edb56c8 Mon Sep 17 00:00:00 2001 From: Neil Armstrong Date: Wed, 11 Nov 2020 08:22:10 +0900 Subject: mmc: meson-gx: change clock phase value on SM1 SoCs Amlogic SM1 SoCs doesn't work over 50MHz. When phase sets to 270', it's working fine over 50MHz on Amlogic SM1 SoCs. Since Other Amlogic SoCs doens't report an issue, phase value is using to 180' by default. To distinguish which value is used adds an u-boot only sm1 compatible. In future, it needs to find what value is a proper about each SoCs. Signed-off-by: Neil Armstrong Signed-off-by: Jaehoon Chung Tested-by: Anand Moon --- drivers/mmc/meson_gx_mmc.c | 27 +++++++++++++++++++++++---- drivers/mmc/meson_gx_mmc.h | 5 +++++ 2 files changed, 28 insertions(+), 4 deletions(-) diff --git a/drivers/mmc/meson_gx_mmc.c b/drivers/mmc/meson_gx_mmc.c index eedebb317b5..a5e9ac5637b 100644 --- a/drivers/mmc/meson_gx_mmc.c +++ b/drivers/mmc/meson_gx_mmc.c @@ -17,6 +17,14 @@ #include #include "meson_gx_mmc.h" +bool meson_gx_mmc_is_compatible(struct udevice *dev, + enum meson_gx_mmc_compatible family) +{ + enum meson_gx_mmc_compatible compat = dev_get_driver_data(dev); + + return compat == family; +} + static inline void *get_regbase(const struct mmc *mmc) { struct meson_mmc_platdata *pdata = mmc->priv; @@ -42,6 +50,8 @@ static void meson_mmc_config_clock(struct mmc *mmc) if (!mmc->clock) return; + /* TOFIX This should use the proper clock taken from DT */ + /* 1GHz / CLK_MAX_DIV = 15,9 MHz */ if (mmc->clock > 16000000) { clk = SD_EMMC_CLKSRC_DIV2; @@ -52,8 +62,16 @@ static void meson_mmc_config_clock(struct mmc *mmc) } clk_div = DIV_ROUND_UP(clk, mmc->clock); - /* 180 phase core clock */ - meson_mmc_clk |= CLK_CO_PHASE_180; + /* + * SM1 SoCs doesn't work fine over 50MHz with CLK_CO_PHASE_180 + * If CLK_CO_PHASE_270 is used, it's more stable than other. + * Other SoCs use CLK_CO_PHASE_180 by default. + * It needs to find what is a proper value about each SoCs. + */ + if (meson_gx_mmc_is_compatible(mmc->dev, MMC_COMPATIBLE_SM1)) + meson_mmc_clk |= CLK_CO_PHASE_270; + else + meson_mmc_clk |= CLK_CO_PHASE_180; /* 180 phase tx clock */ meson_mmc_clk |= CLK_TX_PHASE_000; @@ -308,8 +326,9 @@ int meson_mmc_bind(struct udevice *dev) } static const struct udevice_id meson_mmc_match[] = { - { .compatible = "amlogic,meson-gx-mmc" }, - { .compatible = "amlogic,meson-axg-mmc" }, + { .compatible = "amlogic,meson-gx-mmc", .data = MMC_COMPATIBLE_GX }, + { .compatible = "amlogic,meson-axg-mmc", .data = MMC_COMPATIBLE_GX }, + { .compatible = "amlogic,meson-sm1-mmc", .data = MMC_COMPATIBLE_SM1 }, { /* sentinel */ } }; diff --git a/drivers/mmc/meson_gx_mmc.h b/drivers/mmc/meson_gx_mmc.h index b4544b55628..92aec5329f6 100644 --- a/drivers/mmc/meson_gx_mmc.h +++ b/drivers/mmc/meson_gx_mmc.h @@ -9,6 +9,11 @@ #include #include +enum meson_gx_mmc_compatible { + MMC_COMPATIBLE_GX, + MMC_COMPATIBLE_SM1, +}; + #define SDIO_PORT_A 0 #define SDIO_PORT_B 1 #define SDIO_PORT_C 2 -- cgit v1.3.1 From c87eab81616d671a6004ffc95847bad21b7eb005 Mon Sep 17 00:00:00 2001 From: Neil Armstrong Date: Wed, 11 Nov 2020 08:22:11 +0900 Subject: ARM: dts: meson-sm1: add u-boot specific MMC controller compatible In order to enable the Amlogic SM1 MMC controller fix, we need to add a u-boot specific MMC controller compatible. This adds a new meson-sm1-u-boot.dtsi and reworks the other -u-boot.dtsi to use this for SM1 based boards. Signed-off-by: Neil Armstrong --- .../arm/dts/meson-g12b-a311d-khadas-vim3-u-boot.dtsi | 1 + arch/arm/dts/meson-khadas-vim3-u-boot.dtsi | 2 -- arch/arm/dts/meson-sm1-khadas-vim3l-u-boot.dtsi | 1 + arch/arm/dts/meson-sm1-odroid-c4-u-boot.dtsi | 2 +- arch/arm/dts/meson-sm1-sei610-u-boot.dtsi | 2 +- arch/arm/dts/meson-sm1-u-boot.dtsi | 20 ++++++++++++++++++++ 6 files changed, 24 insertions(+), 4 deletions(-) create mode 100644 arch/arm/dts/meson-sm1-u-boot.dtsi diff --git a/arch/arm/dts/meson-g12b-a311d-khadas-vim3-u-boot.dtsi b/arch/arm/dts/meson-g12b-a311d-khadas-vim3-u-boot.dtsi index f66eca14b12..489efa150a6 100644 --- a/arch/arm/dts/meson-g12b-a311d-khadas-vim3-u-boot.dtsi +++ b/arch/arm/dts/meson-g12b-a311d-khadas-vim3-u-boot.dtsi @@ -4,4 +4,5 @@ * Author: Neil Armstrong */ +#include "meson-g12-common-u-boot.dtsi" #include "meson-khadas-vim3-u-boot.dtsi" diff --git a/arch/arm/dts/meson-khadas-vim3-u-boot.dtsi b/arch/arm/dts/meson-khadas-vim3-u-boot.dtsi index b5da4fdfc3e..81fd5be3783 100644 --- a/arch/arm/dts/meson-khadas-vim3-u-boot.dtsi +++ b/arch/arm/dts/meson-khadas-vim3-u-boot.dtsi @@ -4,8 +4,6 @@ * Author: Neil Armstrong */ -#include "meson-g12-common-u-boot.dtsi" - / { aliases { spi0 = &spifc; diff --git a/arch/arm/dts/meson-sm1-khadas-vim3l-u-boot.dtsi b/arch/arm/dts/meson-sm1-khadas-vim3l-u-boot.dtsi index f66eca14b12..a591c0c9f23 100644 --- a/arch/arm/dts/meson-sm1-khadas-vim3l-u-boot.dtsi +++ b/arch/arm/dts/meson-sm1-khadas-vim3l-u-boot.dtsi @@ -4,4 +4,5 @@ * Author: Neil Armstrong */ +#include "meson-sm1-u-boot.dtsi" #include "meson-khadas-vim3-u-boot.dtsi" diff --git a/arch/arm/dts/meson-sm1-odroid-c4-u-boot.dtsi b/arch/arm/dts/meson-sm1-odroid-c4-u-boot.dtsi index 2a8f0545b1a..c4319880759 100644 --- a/arch/arm/dts/meson-sm1-odroid-c4-u-boot.dtsi +++ b/arch/arm/dts/meson-sm1-odroid-c4-u-boot.dtsi @@ -4,7 +4,7 @@ * Author: Neil Armstrong */ -#include "meson-g12-common-u-boot.dtsi" +#include "meson-sm1-u-boot.dtsi" ðmac { snps,reset-gpio = <&gpio GPIOZ_15 (GPIO_ACTIVE_LOW | GPIO_OPEN_DRAIN)>; diff --git a/arch/arm/dts/meson-sm1-sei610-u-boot.dtsi b/arch/arm/dts/meson-sm1-sei610-u-boot.dtsi index 236f2468dc2..8ebc1caa4a7 100644 --- a/arch/arm/dts/meson-sm1-sei610-u-boot.dtsi +++ b/arch/arm/dts/meson-sm1-sei610-u-boot.dtsi @@ -4,4 +4,4 @@ * Author: Neil Armstrong */ -#include "meson-g12-common-u-boot.dtsi" +#include "meson-sm1-u-boot.dtsi" diff --git a/arch/arm/dts/meson-sm1-u-boot.dtsi b/arch/arm/dts/meson-sm1-u-boot.dtsi new file mode 100644 index 00000000000..e05d4c369ad --- /dev/null +++ b/arch/arm/dts/meson-sm1-u-boot.dtsi @@ -0,0 +1,20 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2020 BayLibre, SAS. + * Author: Neil Armstrong + */ + +#include "meson-g12-common-u-boot.dtsi" + +&sd_emmc_a { + compatible = "amlogic,meson-sm1-mmc"; +}; + +&sd_emmc_b { + compatible = "amlogic,meson-sm1-mmc"; +}; + +&sd_emmc_c { + compatible = "amlogic,meson-sm1-mmc"; +}; + -- cgit v1.3.1