From d62f1c98c5e78f4092510992f8174c284e3d1778 Mon Sep 17 00:00:00 2001 From: Siddharth Vadapalli Date: Fri, 27 Feb 2026 17:28:29 +0530 Subject: arm: mach-k3: arm64-mmu: add mapping for PCIe 4 GB Address Windows The PCIe Controllers in the K3 SoCs have 4 GB Address Windows in the 64-bit address space to map System (CPU) Addresses to PCIe Bus Addresses. The physical addresses for these Address Windows across PCIe instances across SoCs is as follows: +--------+----------------+----------------+----------------+----------------+ | SoC | PCIe0 | PCIe1 | PCIe2 | PCIe3 | +--------+----------------+----------------+----------------+----------------+ | AM64 | 0x6_0000_0000 | NA | NA | NA | | J722S | 0x6_0000_0000 | NA | NA | NA | | AM68 | NA | 0x41_0000_0000 | NA | NA | | J7200 | NA | 0x41_0000_0000 | NA | NA | | J721S2 | NA | 0x41_0000_0000 | NA | NA | | J742S2 | 0x40_0000_0000 | 0x41_0000_0000 | NA | NA | | AM69 | 0x40_0000_0000 | 0x41_0000_0000 | 0x42_0000_0000 | 0x43_0000_0000 | | J721E | 0x40_0000_0000 | 0x41_0000_0000 | 0x42_0000_0000 | 0x43_0000_0000 | | J784S4 | 0x40_0000_0000 | 0x41_0000_0000 | 0x42_0000_0000 | 0x43_0000_0000 | +--------+----------------+----------------+----------------+----------------+ Two regions for a 1:1 mapping from virtual addresses to physical addresses catering to all of the above will be required, which are: 1. For AM64 and J722S SoCs => Start: 0x6_0000_0000 Size: 0x1_0000_0000 2. For AM68, AM69, J7200, J721E, J721S2, J742S2 and J784S4 SoCs => Start: 0x40_0000_0000 Size: 0x4_0000_0000 Since the 'Flash Peripherals' region from 0x5_0000_0000 to 0x8_7FFF_FFFF includes the mapping for AM64 and J722S SoCs, only the second region mentioned above needs to be added. Hence, add the region to support 64-bit address space for PCIe. Signed-off-by: Siddharth Vadapalli Fixes: 79f3e77133bd ("Subtree merge tag 'v6.16-dts' of dts repo [1] into dts/upstream") --- arch/arm/mach-k3/arm64/arm64-mmu.c | 16 ++++++++++++++++ arch/arm/mach-k3/include/mach/k3-ddr.h | 11 +++++++---- 2 files changed, 23 insertions(+), 4 deletions(-) diff --git a/arch/arm/mach-k3/arm64/arm64-mmu.c b/arch/arm/mach-k3/arm64/arm64-mmu.c index f999af143fb..e032755db0d 100644 --- a/arch/arm/mach-k3/arm64/arm64-mmu.c +++ b/arch/arm/mach-k3/arm64/arm64-mmu.c @@ -29,6 +29,22 @@ struct mm_region k3_mem_map[K3_MEM_MAP_LEN] = { .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN + }, { /* + * PCIe 4 GB Address Window for AM64 and J722S SoCs starts + * from 0x6_0000_0000 and has a size of 0x1_0000_0000. + * Since this is already enabled by the 'Flash Peripherals' + * region above, we don't need to add it again. + * + * The PCIe 4 GB Address Windows for AM68, AM69, J7200, J721E, + * J721S2, J742S2 and J784S4 SoCs are enabled by the following + * region. + */ + .virt = 0x4000000000UL, + .phys = 0x4000000000UL, + .size = 0x400000000UL, + .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | + PTE_BLOCK_NON_SHARE | + PTE_BLOCK_PXN | PTE_BLOCK_UXN }, [K3_MEM_MAP_FIRST_BANK_IDX] = { /* First DRAM Bank of size 2G */ .virt = CFG_SYS_SDRAM_BASE, .phys = CFG_SYS_SDRAM_BASE, diff --git a/arch/arm/mach-k3/include/mach/k3-ddr.h b/arch/arm/mach-k3/include/mach/k3-ddr.h index 207e60b2763..6ac7f682fb8 100644 --- a/arch/arm/mach-k3/include/mach/k3-ddr.h +++ b/arch/arm/mach-k3/include/mach/k3-ddr.h @@ -8,11 +8,14 @@ #include -/* We need 3 extra entries for: - * SoC peripherals, flash and the sentinel value. +/* We need 4 extra entries for: + * 1. SoC peripherals + * 2. Flash + * 3. PCIe 4GB Windows for AM68, AM69, J7200, J721E, J721S2, J742S2 and J784S4 SoCs + * 4. Sentinel value */ -#define K3_MEM_MAP_LEN ((CONFIG_NR_DRAM_BANKS) + 3) -#define K3_MEM_MAP_FIRST_BANK_IDX 2 +#define K3_MEM_MAP_LEN ((CONFIG_NR_DRAM_BANKS) + 4) +#define K3_MEM_MAP_FIRST_BANK_IDX 3 int dram_init(void); int dram_init_banksize(void); -- cgit v1.3.1 From 068d05ad5f82a58316e895fd1497cf10898b3beb Mon Sep 17 00:00:00 2001 From: Siddharth Vadapalli Date: Fri, 27 Feb 2026 17:28:30 +0530 Subject: pci: pcie_cdns_ti: enable PCIe root-complex mode for J784S4 SoC The PCIe Controllers on the J784S4 SoC support Root-Complex mode of operation. Hence, enable it. Signed-off-by: Siddharth Vadapalli Fixes: 79f3e77133bd ("Subtree merge tag 'v6.16-dts' of dts repo [1] into dts/upstream") --- drivers/pci/pcie_cdns_ti.c | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/drivers/pci/pcie_cdns_ti.c b/drivers/pci/pcie_cdns_ti.c index 38804f1c09c..63d249c2506 100644 --- a/drivers/pci/pcie_cdns_ti.c +++ b/drivers/pci/pcie_cdns_ti.c @@ -860,6 +860,12 @@ static const struct pcie_cdns_ti_data j722s_pcie_rc_data = { .max_lanes = 1, }; +static const struct pcie_cdns_ti_data j784s4_pcie_rc_data = { + .mode = PCIE_MODE_RC, + .quirk_detect_quiet_flag = true, + .max_lanes = 4, +}; + static const struct udevice_id pcie_cdns_ti_ids[] = { { .compatible = "ti,j7200-pcie-host", @@ -873,6 +879,10 @@ static const struct udevice_id pcie_cdns_ti_ids[] = { .compatible = "ti,j722s-pcie-host", .data = (ulong)&j722s_pcie_rc_data, }, + { + .compatible = "ti,j784s4-pcie-host", + .data = (ulong)&j784s4_pcie_rc_data, + }, {}, }; -- cgit v1.3.1 From 724952ac41c144a8528a273aeed23422b1e2330e Mon Sep 17 00:00:00 2001 From: Siddharth Vadapalli Date: Fri, 27 Feb 2026 17:28:31 +0530 Subject: configs: {am69_sk, j784s4_evm}_a72_defconfig: enable PCIe Root-Complex mode The PCIe Controllers on the J784S4 and AM69 SoCs support Root-Complex mode of operation. PCIe0 instance of PCIe on both of the SoCs is brought out on the Starter-Kit (AM69) and EVM (J784S4) boards. Hence, enable the configs required for Root-Complex mode of operation. Signed-off-by: Siddharth Vadapalli Fixes: 79f3e77133bd ("Subtree merge tag 'v6.16-dts' of dts repo [1] into dts/upstream") --- configs/j784s4_evm_a72_defconfig | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/configs/j784s4_evm_a72_defconfig b/configs/j784s4_evm_a72_defconfig index f440b18c6fc..1d2043aeba0 100644 --- a/configs/j784s4_evm_a72_defconfig +++ b/configs/j784s4_evm_a72_defconfig @@ -28,6 +28,8 @@ CONFIG_SPL_FS_FAT=y CONFIG_SPL_LIBDISK_SUPPORT=y CONFIG_SPL_SPI_FLASH_SUPPORT=y CONFIG_SPL_SPI=y +CONFIG_SYS_PCI_64BIT=y +CONFIG_PCI=y CONFIG_EFI_SET_TIME=y CONFIG_BOOTSTD_FULL=y CONFIG_BOOTCOMMAND="run envboot; bootflow scan -lb" @@ -56,6 +58,7 @@ CONFIG_SPL_YMODEM_SUPPORT=y CONFIG_CMD_BOOTEFI_SELFTEST=y CONFIG_CMD_NVEDIT_EFI=y CONFIG_CMD_MTD=y +CONFIG_CMD_PCI=y CONFIG_CMD_USB_MASS_STORAGE=y CONFIG_CMD_EFIDEBUG=y CONFIG_OF_CONTROL=y @@ -123,6 +126,9 @@ CONFIG_MUX_MMIO=y CONFIG_PHY_TI_DP83867=y CONFIG_PHY_FIXED=y CONFIG_TI_AM65_CPSW_NUSS=y +CONFIG_NVME_PCI=y +CONFIG_PCI_CONFIG_HOST_BRIDGE=y +CONFIG_PCIE_CDNS_TI=y CONFIG_PCI_ENDPOINT=y CONFIG_PCIE_CDNS_TI_EP=y CONFIG_PHY=y -- cgit v1.3.1 From 430874ce20c78c4d2f427dac34860642f044c5fd Mon Sep 17 00:00:00 2001 From: Siddharth Vadapalli Date: Fri, 27 Feb 2026 17:28:32 +0530 Subject: configs: am64x_evm_a53_defconfig: enable 64-bit addressing for PCIe The PCIe0 instance of PCIe on the AM64x SoC uses the 4 GB Address Window starting from 0x6_0000_0000 to map System Addresses to PCIe Bus Addresses. Hence, enable CONFIG_SYS_PCI_64BIT. Signed-off-by: Siddharth Vadapalli Fixes: 79f3e77133bd ("Subtree merge tag 'v6.16-dts' of dts repo [1] into dts/upstream") --- configs/am64x_evm_a53_defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/configs/am64x_evm_a53_defconfig b/configs/am64x_evm_a53_defconfig index e576012b3f6..3a35df830e3 100644 --- a/configs/am64x_evm_a53_defconfig +++ b/configs/am64x_evm_a53_defconfig @@ -31,6 +31,7 @@ CONFIG_SPL_FS_FAT=y CONFIG_SPL_LIBDISK_SUPPORT=y CONFIG_SPL_SPI_FLASH_SUPPORT=y CONFIG_SPL_SPI=y +CONFIG_SYS_PCI_64BIT=y CONFIG_PCI=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set CONFIG_BOOTSTD_FULL=y -- cgit v1.3.1 From b04d709459073c6dc48cafd8eed9d14f552fdaa7 Mon Sep 17 00:00:00 2001 From: Siddharth Vadapalli Date: Fri, 27 Feb 2026 17:28:33 +0530 Subject: configs: j7200_evm_a72_defconfig: enable 64-bit addressing for PCIe The PCIe1 instance of PCIe on the J7200 SoC uses the 4 GB Address Window starting from 0x41_0000_0000 to map System Addresses to PCIe Bus Addresses. Hence, enable CONFIG_SYS_PCI_64BIT. Signed-off-by: Siddharth Vadapalli Fixes: 79f3e77133bd ("Subtree merge tag 'v6.16-dts' of dts repo [1] into dts/upstream") --- configs/j7200_evm_a72_defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/configs/j7200_evm_a72_defconfig b/configs/j7200_evm_a72_defconfig index 27a9db72fb5..5c5abd94eb0 100644 --- a/configs/j7200_evm_a72_defconfig +++ b/configs/j7200_evm_a72_defconfig @@ -30,6 +30,7 @@ CONFIG_SPL_LIBDISK_SUPPORT=y CONFIG_SPL_SPI_FLASH_SUPPORT=y CONFIG_SPL_SPI=y # CONFIG_PSCI_RESET is not set +CONFIG_SYS_PCI_64BIT=y CONFIG_PCI=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set CONFIG_BOOTSTD_FULL=y -- cgit v1.3.1 From f0bb3940b132d039a249815d34eea6fae5be60d6 Mon Sep 17 00:00:00 2001 From: Siddharth Vadapalli Date: Fri, 27 Feb 2026 17:28:34 +0530 Subject: configs: j722s_evm_a53_defconfig: enable 64-bit addressing for PCIe The PCIe0 instance of PCIe on the J722S SoC uses the 4 GB Address Window starting from 0x6_0000_0000 to map System Addresses to PCIe Bus Addresses. Hence, enable CONFIG_SYS_PCI_64BIT. Signed-off-by: Siddharth Vadapalli Fixes: 79f3e77133bd ("Subtree merge tag 'v6.16-dts' of dts repo [1] into dts/upstream") --- configs/j722s_evm_a53_defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/configs/j722s_evm_a53_defconfig b/configs/j722s_evm_a53_defconfig index e84670c75ed..dc4b6b93803 100644 --- a/configs/j722s_evm_a53_defconfig +++ b/configs/j722s_evm_a53_defconfig @@ -27,6 +27,7 @@ CONFIG_SPL_FS_FAT=y CONFIG_SPL_LIBDISK_SUPPORT=y CONFIG_SPL_SPI_FLASH_SUPPORT=y CONFIG_SPL_SPI=y +CONFIG_SYS_PCI_64BIT=y CONFIG_PCI=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set CONFIG_BOOTSTD_FULL=y -- cgit v1.3.1