From 10fad1f943ee6b42b954b06a64fdc7cad9014e32 Mon Sep 17 00:00:00 2001 From: Yanhong Wang Date: Fri, 28 Apr 2023 09:28:20 +0800 Subject: board: starfive: Fixed errors reported when executing get_maintainer.pl Fixed errors reported when executing 'scripts/get_maintainer.pl -f configs/starfive_visionfive2_defconfig'. Invalid MAINTAINERS address: 'startfive' Signed-off-by: Yanhong Wang Reviewed-by: Leo Yu-Chi Liang --- board/starfive/visionfive2/MAINTAINERS | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/board/starfive/visionfive2/MAINTAINERS b/board/starfive/visionfive2/MAINTAINERS index c5369086d8e..600ff9575b8 100644 --- a/board/starfive/visionfive2/MAINTAINERS +++ b/board/starfive/visionfive2/MAINTAINERS @@ -1,5 +1,5 @@ STARFIVE JH7110 VISIONFIVE2 BOARD -M: startfive +M: Yanhong Wang S: Maintained F: arch/riscv/include/asm/arch-jh7110/ F: board/starfive/visionfive2/ -- cgit v1.2.3 From 217b6373b57ce815b79f05dddd3203984994ad96 Mon Sep 17 00:00:00 2001 From: Heinrich Schuchardt Date: Mon, 1 May 2023 14:57:08 +0200 Subject: MAINTAINERS: update SiFive HiFive Unmatched maintainers Email account pragnesh.patel@sifive.com does not exist anymore. Signed-off-by: Heinrich Schuchardt --- board/sifive/unmatched/MAINTAINERS | 1 - 1 file changed, 1 deletion(-) diff --git a/board/sifive/unmatched/MAINTAINERS b/board/sifive/unmatched/MAINTAINERS index 94c9510bfae..e601a0f3288 100644 --- a/board/sifive/unmatched/MAINTAINERS +++ b/board/sifive/unmatched/MAINTAINERS @@ -1,6 +1,5 @@ SiFive HiFive Unmatched FU740 BOARD M: Paul Walmsley -M: Pragnesh Patel M: Green Wan S: Maintained F: board/sifive/unmatched/ -- cgit v1.2.3 From 4a3efd71cd858b87527e9478ff51529d39329819 Mon Sep 17 00:00:00 2001 From: Bin Meng Date: Tue, 27 Jun 2023 09:24:56 +0800 Subject: riscv: Fix alignment of RELA sections in the linker scripts In current linker script both .efi_runtime_rel and .rela.dyn sections are of RELA type whose entry size is either 12 (RV32) or 24 (RV64). These two are arranged as a continuous region on purpose so that the prelink-riscv executable can fix up the PIE addresses in one loop. However there is an 'ALIGN(8)' between these 2 sections which might cause a gap to be inserted between these 2 sections to satisfy the alignment requirement on RV32. This would break the assumption of the prelink process and generate an unbootable image. Fixes: 9a6569a043d3 ("riscv: Update alignment for some sections in linker scripts") Signed-off-by: Bin Meng Reviewed-by: Rick Chen --- arch/riscv/cpu/u-boot.lds | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) diff --git a/arch/riscv/cpu/u-boot.lds b/arch/riscv/cpu/u-boot.lds index 15b5cbc585d..2ffe6ba3c8f 100644 --- a/arch/riscv/cpu/u-boot.lds +++ b/arch/riscv/cpu/u-boot.lds @@ -48,7 +48,7 @@ SECTIONS KEEP(*(SORT(__u_boot_list*))); } - . = ALIGN(4); + . = ALIGN(8); .efi_runtime_rel : { __efi_runtime_rel_start = .; @@ -57,8 +57,6 @@ SECTIONS __efi_runtime_rel_stop = .; } - . = ALIGN(8); - /DISCARD/ : { *(.rela.plt*) } .rela.dyn : { __rel_dyn_start = .; -- cgit v1.2.3