From c4173429dbde088fb9d958688fadddaff3ed9a5a Mon Sep 17 00:00:00 2001 From: David Lechner Date: Tue, 17 Mar 2026 18:23:14 -0500 Subject: clk: mediatek: mt7622: convert to struct mtk_parent Convert all parent clock arrays to use struct mtk_parent. This will allow us to simplify core code later by having only one possible data type for mux parent arrays. Reviewed-by: Macpaul Lin Reviewed-by: Julien Stephan Link: https://patch.msgid.link/20260317-clk-mtk-unify-mux-parents-v3-1-a4760f5b0a80@baylibre.com Signed-off-by: David Lechner --- drivers/clk/mediatek/clk-mt7622.c | 359 +++++++++++++++++++------------------- 1 file changed, 178 insertions(+), 181 deletions(-) diff --git a/drivers/clk/mediatek/clk-mt7622.c b/drivers/clk/mediatek/clk-mt7622.c index 44d2836710e..8a7d446ad79 100644 --- a/drivers/clk/mediatek/clk-mt7622.c +++ b/drivers/clk/mediatek/clk-mt7622.c @@ -159,231 +159,231 @@ static const struct mtk_fixed_factor top_fixed_divs[] = { FACTOR0(CLK_TOP_ETH_500M, CLK_APMIXED_ETH1PLL, 1, 1), }; -static const int axi_parents[] = { - CLK_XTAL, - CLK_TOP_SYSPLL1_D2, - CLK_TOP_SYSPLL_D5, - CLK_TOP_SYSPLL1_D4, - CLK_TOP_UNIVPLL_D5, - CLK_TOP_UNIVPLL2_D2, - CLK_TOP_UNIVPLL_D7 -}; - -static const int mem_parents[] = { - CLK_XTAL, - CLK_TOP_DMPLL -}; - -static const int ddrphycfg_parents[] = { - CLK_XTAL, - CLK_TOP_SYSPLL1_D8 -}; - -static const int eth_parents[] = { - CLK_XTAL, - CLK_TOP_SYSPLL1_D2, - CLK_TOP_UNIVPLL1_D2, - CLK_TOP_SYSPLL1_D4, - CLK_TOP_UNIVPLL_D5, - -1, - CLK_TOP_UNIVPLL_D7 -}; - -static const int pwm_parents[] = { - CLK_XTAL, - CLK_TOP_UNIVPLL2_D4 -}; - -static const int f10m_ref_parents[] = { - CLK_XTAL, - CLK_TOP_SYSPLL4_D16 +static const struct mtk_parent axi_parents[] = { + XTAL_PARENT(CLK_XTAL), + TOP_PARENT(CLK_TOP_SYSPLL1_D2), + TOP_PARENT(CLK_TOP_SYSPLL_D5), + TOP_PARENT(CLK_TOP_SYSPLL1_D4), + TOP_PARENT(CLK_TOP_UNIVPLL_D5), + TOP_PARENT(CLK_TOP_UNIVPLL2_D2), + TOP_PARENT(CLK_TOP_UNIVPLL_D7), +}; + +static const struct mtk_parent mem_parents[] = { + XTAL_PARENT(CLK_XTAL), + TOP_PARENT(CLK_TOP_DMPLL), +}; + +static const struct mtk_parent ddrphycfg_parents[] = { + XTAL_PARENT(CLK_XTAL), + TOP_PARENT(CLK_TOP_SYSPLL1_D8), +}; + +static const struct mtk_parent eth_parents[] = { + XTAL_PARENT(CLK_XTAL), + TOP_PARENT(CLK_TOP_SYSPLL1_D2), + TOP_PARENT(CLK_TOP_UNIVPLL1_D2), + TOP_PARENT(CLK_TOP_SYSPLL1_D4), + TOP_PARENT(CLK_TOP_UNIVPLL_D5), + VOID_PARENT, + TOP_PARENT(CLK_TOP_UNIVPLL_D7), }; - -static const int nfi_infra_parents[] = { - CLK_XTAL, - CLK_XTAL, - CLK_XTAL, - CLK_XTAL, - CLK_XTAL, - CLK_XTAL, - CLK_XTAL, - CLK_XTAL, - CLK_TOP_UNIVPLL2_D8, - CLK_TOP_SYSPLL1_D8, - CLK_TOP_UNIVPLL1_D8, - CLK_TOP_SYSPLL4_D2, - CLK_TOP_UNIVPLL2_D4, - CLK_TOP_UNIVPLL3_D2, - CLK_TOP_SYSPLL1_D4 + +static const struct mtk_parent pwm_parents[] = { + XTAL_PARENT(CLK_XTAL), + TOP_PARENT(CLK_TOP_UNIVPLL2_D4), +}; + +static const struct mtk_parent f10m_ref_parents[] = { + XTAL_PARENT(CLK_XTAL), + TOP_PARENT(CLK_TOP_SYSPLL4_D16), +}; + +static const struct mtk_parent nfi_infra_parents[] = { + XTAL_PARENT(CLK_XTAL), + XTAL_PARENT(CLK_XTAL), + XTAL_PARENT(CLK_XTAL), + XTAL_PARENT(CLK_XTAL), + XTAL_PARENT(CLK_XTAL), + XTAL_PARENT(CLK_XTAL), + XTAL_PARENT(CLK_XTAL), + XTAL_PARENT(CLK_XTAL), + TOP_PARENT(CLK_TOP_UNIVPLL2_D8), + TOP_PARENT(CLK_TOP_SYSPLL1_D8), + TOP_PARENT(CLK_TOP_UNIVPLL1_D8), + TOP_PARENT(CLK_TOP_SYSPLL4_D2), + TOP_PARENT(CLK_TOP_UNIVPLL2_D4), + TOP_PARENT(CLK_TOP_UNIVPLL3_D2), + TOP_PARENT(CLK_TOP_SYSPLL1_D4), }; -static const int flash_parents[] = { - CLK_XTAL, - CLK_TOP_UNIVPLL_D80_D4, - CLK_TOP_SYSPLL2_D8, - CLK_TOP_SYSPLL3_D4, - CLK_TOP_UNIVPLL3_D4, - CLK_TOP_UNIVPLL1_D8, - CLK_TOP_SYSPLL2_D4, - CLK_TOP_UNIVPLL2_D4 +static const struct mtk_parent flash_parents[] = { + XTAL_PARENT(CLK_XTAL), + TOP_PARENT(CLK_TOP_UNIVPLL_D80_D4), + TOP_PARENT(CLK_TOP_SYSPLL2_D8), + TOP_PARENT(CLK_TOP_SYSPLL3_D4), + TOP_PARENT(CLK_TOP_UNIVPLL3_D4), + TOP_PARENT(CLK_TOP_UNIVPLL1_D8), + TOP_PARENT(CLK_TOP_SYSPLL2_D4), + TOP_PARENT(CLK_TOP_UNIVPLL2_D4), }; -static const int uart_parents[] = { - CLK_XTAL, - CLK_TOP_UNIVPLL2_D8 +static const struct mtk_parent uart_parents[] = { + XTAL_PARENT(CLK_XTAL), + TOP_PARENT(CLK_TOP_UNIVPLL2_D8), }; -static const int spi0_parents[] = { - CLK_XTAL, - CLK_TOP_SYSPLL3_D2, - CLK_XTAL, - CLK_TOP_SYSPLL2_D4, - CLK_TOP_SYSPLL4_D2, - CLK_TOP_UNIVPLL2_D4, - CLK_TOP_UNIVPLL1_D8, - CLK_XTAL +static const struct mtk_parent spi0_parents[] = { + XTAL_PARENT(CLK_XTAL), + TOP_PARENT(CLK_TOP_SYSPLL3_D2), + XTAL_PARENT(CLK_XTAL), + TOP_PARENT(CLK_TOP_SYSPLL2_D4), + TOP_PARENT(CLK_TOP_SYSPLL4_D2), + TOP_PARENT(CLK_TOP_UNIVPLL2_D4), + TOP_PARENT(CLK_TOP_UNIVPLL1_D8), + XTAL_PARENT(CLK_XTAL), }; -static const int spi1_parents[] = { - CLK_XTAL, - CLK_TOP_SYSPLL3_D2, - CLK_XTAL, - CLK_TOP_SYSPLL4_D4, - CLK_TOP_SYSPLL4_D2, - CLK_TOP_UNIVPLL2_D4, - CLK_TOP_UNIVPLL1_D8, - CLK_XTAL +static const struct mtk_parent spi1_parents[] = { + XTAL_PARENT(CLK_XTAL), + TOP_PARENT(CLK_TOP_SYSPLL3_D2), + XTAL_PARENT(CLK_XTAL), + TOP_PARENT(CLK_TOP_SYSPLL4_D4), + TOP_PARENT(CLK_TOP_SYSPLL4_D2), + TOP_PARENT(CLK_TOP_UNIVPLL2_D4), + TOP_PARENT(CLK_TOP_UNIVPLL1_D8), + XTAL_PARENT(CLK_XTAL), }; -static const int msdc30_0_parents[] = { - CLK_XTAL, - CLK_TOP_UNIVPLL2_D16, - CLK_TOP_UNIV48M +static const struct mtk_parent msdc30_0_parents[] = { + XTAL_PARENT(CLK_XTAL), + TOP_PARENT(CLK_TOP_UNIVPLL2_D16), + TOP_PARENT(CLK_TOP_UNIV48M), }; -static const int a1sys_hp_parents[] = { - CLK_XTAL, - CLK_TOP_AUD1PLL, - CLK_TOP_AUD2PLL, - CLK_XTAL +static const struct mtk_parent a1sys_hp_parents[] = { + XTAL_PARENT(CLK_XTAL), + TOP_PARENT(CLK_TOP_AUD1PLL), + TOP_PARENT(CLK_TOP_AUD2PLL), + XTAL_PARENT(CLK_XTAL), }; -static const int intdir_parents[] = { - CLK_XTAL, - CLK_TOP_SYSPLL1_D2, - CLK_TOP_UNIVPLL_D2, - CLK_TOP_SGMIIPLL +static const struct mtk_parent intdir_parents[] = { + XTAL_PARENT(CLK_XTAL), + TOP_PARENT(CLK_TOP_SYSPLL1_D2), + TOP_PARENT(CLK_TOP_UNIVPLL_D2), + TOP_PARENT(CLK_TOP_SGMIIPLL), }; -static const int aud_intbus_parents[] = { - CLK_XTAL, - CLK_TOP_SYSPLL1_D4, - CLK_TOP_SYSPLL4_D2, - CLK_TOP_SYSPLL3_D2 +static const struct mtk_parent aud_intbus_parents[] = { + XTAL_PARENT(CLK_XTAL), + TOP_PARENT(CLK_TOP_SYSPLL1_D4), + TOP_PARENT(CLK_TOP_SYSPLL4_D2), + TOP_PARENT(CLK_TOP_SYSPLL3_D2), }; -static const int pmicspi_parents[] = { - CLK_XTAL, - -1, - -1, - -1, - -1, - CLK_TOP_UNIVPLL2_D16 +static const struct mtk_parent pmicspi_parents[] = { + XTAL_PARENT(CLK_XTAL), + VOID_PARENT, + VOID_PARENT, + VOID_PARENT, + VOID_PARENT, + TOP_PARENT(CLK_TOP_UNIVPLL2_D16), }; -static const int atb_parents[] = { - CLK_XTAL, - CLK_TOP_SYSPLL1_D2, - CLK_TOP_SYSPLL_D5 +static const struct mtk_parent atb_parents[] = { + XTAL_PARENT(CLK_XTAL), + TOP_PARENT(CLK_TOP_SYSPLL1_D2), + TOP_PARENT(CLK_TOP_SYSPLL_D5), }; -static const int audio_parents[] = { - CLK_XTAL, - CLK_TOP_SYSPLL3_D4, - CLK_TOP_SYSPLL4_D4, - CLK_TOP_UNIVPLL1_D16 +static const struct mtk_parent audio_parents[] = { + XTAL_PARENT(CLK_XTAL), + TOP_PARENT(CLK_TOP_SYSPLL3_D4), + TOP_PARENT(CLK_TOP_SYSPLL4_D4), + TOP_PARENT(CLK_TOP_UNIVPLL1_D16), }; -static const int usb20_parents[] = { - CLK_XTAL, - CLK_TOP_UNIVPLL3_D4, - CLK_TOP_SYSPLL1_D8, - CLK_XTAL +static const struct mtk_parent usb20_parents[] = { + XTAL_PARENT(CLK_XTAL), + TOP_PARENT(CLK_TOP_UNIVPLL3_D4), + TOP_PARENT(CLK_TOP_SYSPLL1_D8), + XTAL_PARENT(CLK_XTAL), }; -static const int aud1_parents[] = { - CLK_XTAL, - CLK_TOP_AUD1PLL +static const struct mtk_parent aud1_parents[] = { + XTAL_PARENT(CLK_XTAL), + TOP_PARENT(CLK_TOP_AUD1PLL), }; -static const int asm_l_parents[] = { - CLK_XTAL, - CLK_TOP_SYSPLL_D5, - CLK_TOP_UNIVPLL2_D2, - CLK_TOP_UNIVPLL2_D4 +static const struct mtk_parent asm_l_parents[] = { + XTAL_PARENT(CLK_XTAL), + TOP_PARENT(CLK_TOP_SYSPLL_D5), + TOP_PARENT(CLK_TOP_UNIVPLL2_D2), + TOP_PARENT(CLK_TOP_UNIVPLL2_D4), }; -static const int apll1_ck_parents[] = { - CLK_TOP_AUD1_SEL, - CLK_TOP_AUD2_SEL +static const struct mtk_parent apll1_ck_parents[] = { + TOP_PARENT(CLK_TOP_AUD1_SEL), + TOP_PARENT(CLK_TOP_AUD2_SEL), }; static const struct mtk_composite top_muxes[] = { /* CLK_CFG_0 */ - MUX_GATE(CLK_TOP_AXI_SEL, axi_parents, 0x40, 0, 3, 7), - MUX_GATE(CLK_TOP_MEM_SEL, mem_parents, 0x40, 8, 1, 15), - MUX_GATE(CLK_TOP_DDRPHYCFG_SEL, ddrphycfg_parents, 0x40, 16, 1, 23), - MUX_GATE(CLK_TOP_ETH_SEL, eth_parents, 0x40, 24, 3, 31), + MUX_GATE_MIXED(CLK_TOP_AXI_SEL, axi_parents, 0x40, 0, 3, 7), + MUX_GATE_MIXED(CLK_TOP_MEM_SEL, mem_parents, 0x40, 8, 1, 15), + MUX_GATE_MIXED(CLK_TOP_DDRPHYCFG_SEL, ddrphycfg_parents, 0x40, 16, 1, 23), + MUX_GATE_MIXED(CLK_TOP_ETH_SEL, eth_parents, 0x40, 24, 3, 31), /* CLK_CFG_1 */ - MUX_GATE(CLK_TOP_PWM_SEL, pwm_parents, 0x50, 0, 2, 7), - MUX_GATE(CLK_TOP_F10M_REF_SEL, f10m_ref_parents, 0x50, 8, 1, 15), - MUX_GATE(CLK_TOP_NFI_INFRA_SEL, nfi_infra_parents, 0x50, 16, 4, 23), - MUX_GATE(CLK_TOP_FLASH_SEL, flash_parents, 0x50, 24, 3, 31), + MUX_GATE_MIXED(CLK_TOP_PWM_SEL, pwm_parents, 0x50, 0, 2, 7), + MUX_GATE_MIXED(CLK_TOP_F10M_REF_SEL, f10m_ref_parents, 0x50, 8, 1, 15), + MUX_GATE_MIXED(CLK_TOP_NFI_INFRA_SEL, nfi_infra_parents, 0x50, 16, 4, 23), + MUX_GATE_MIXED(CLK_TOP_FLASH_SEL, flash_parents, 0x50, 24, 3, 31), /* CLK_CFG_2 */ - MUX_GATE(CLK_TOP_UART_SEL, uart_parents, 0x60, 0, 1, 7), - MUX_GATE(CLK_TOP_SPI0_SEL, spi0_parents, 0x60, 8, 3, 15), - MUX_GATE(CLK_TOP_SPI1_SEL, spi1_parents, 0x60, 16, 3, 23), - MUX_GATE(CLK_TOP_MSDC50_0_SEL, uart_parents, 0x60, 24, 3, 31), + MUX_GATE_MIXED(CLK_TOP_UART_SEL, uart_parents, 0x60, 0, 1, 7), + MUX_GATE_MIXED(CLK_TOP_SPI0_SEL, spi0_parents, 0x60, 8, 3, 15), + MUX_GATE_MIXED(CLK_TOP_SPI1_SEL, spi1_parents, 0x60, 16, 3, 23), + MUX_GATE_MIXED(CLK_TOP_MSDC50_0_SEL, uart_parents, 0x60, 24, 3, 31), /* CLK_CFG_3 */ - MUX_GATE(CLK_TOP_MSDC30_0_SEL, msdc30_0_parents, 0x70, 0, 3, 7), - MUX_GATE(CLK_TOP_MSDC30_1_SEL, msdc30_0_parents, 0x70, 8, 3, 15), - MUX_GATE(CLK_TOP_A1SYS_HP_SEL, a1sys_hp_parents, 0x70, 16, 3, 23), - MUX_GATE(CLK_TOP_A2SYS_HP_SEL, a1sys_hp_parents, 0x70, 24, 3, 31), + MUX_GATE_MIXED(CLK_TOP_MSDC30_0_SEL, msdc30_0_parents, 0x70, 0, 3, 7), + MUX_GATE_MIXED(CLK_TOP_MSDC30_1_SEL, msdc30_0_parents, 0x70, 8, 3, 15), + MUX_GATE_MIXED(CLK_TOP_A1SYS_HP_SEL, a1sys_hp_parents, 0x70, 16, 3, 23), + MUX_GATE_MIXED(CLK_TOP_A2SYS_HP_SEL, a1sys_hp_parents, 0x70, 24, 3, 31), /* CLK_CFG_4 */ - MUX_GATE(CLK_TOP_INTDIR_SEL, intdir_parents, 0x80, 0, 2, 7), - MUX_GATE(CLK_TOP_AUD_INTBUS_SEL, aud_intbus_parents, 0x80, 8, 2, 15), - MUX_GATE(CLK_TOP_PMICSPI_SEL, pmicspi_parents, 0x80, 16, 3, 23), - MUX_GATE(CLK_TOP_SCP_SEL, ddrphycfg_parents, 0x80, 24, 2, 31), + MUX_GATE_MIXED(CLK_TOP_INTDIR_SEL, intdir_parents, 0x80, 0, 2, 7), + MUX_GATE_MIXED(CLK_TOP_AUD_INTBUS_SEL, aud_intbus_parents, 0x80, 8, 2, 15), + MUX_GATE_MIXED(CLK_TOP_PMICSPI_SEL, pmicspi_parents, 0x80, 16, 3, 23), + MUX_GATE_MIXED(CLK_TOP_SCP_SEL, ddrphycfg_parents, 0x80, 24, 2, 31), /* CLK_CFG_5 */ - MUX_GATE(CLK_TOP_ATB_SEL, atb_parents, 0x90, 0, 2, 7), - MUX_GATE_FLAGS(CLK_TOP_HIF_SEL, eth_parents, 0x90, 8, 3, 15, - CLK_MUX_DOMAIN_SCPSYS), - MUX_GATE(CLK_TOP_AUDIO_SEL, audio_parents, 0x90, 16, 2, 23), - MUX_GATE(CLK_TOP_U2_SEL, usb20_parents, 0x90, 24, 2, 31), + MUX_GATE_MIXED(CLK_TOP_ATB_SEL, atb_parents, 0x90, 0, 2, 7), + MUX_GATE_MIXED_FLAGS(CLK_TOP_HIF_SEL, eth_parents, 0x90, 8, 3, 15, + CLK_MUX_DOMAIN_SCPSYS), + MUX_GATE_MIXED(CLK_TOP_AUDIO_SEL, audio_parents, 0x90, 16, 2, 23), + MUX_GATE_MIXED(CLK_TOP_U2_SEL, usb20_parents, 0x90, 24, 2, 31), /* CLK_CFG_6 */ - MUX_GATE(CLK_TOP_AUD1_SEL, aud1_parents, 0xA0, 0, 1, 7), - MUX_GATE(CLK_TOP_AUD2_SEL, aud1_parents, 0xA0, 8, 1, 15), - MUX_GATE(CLK_TOP_IRRX_SEL, f10m_ref_parents, 0xA0, 16, 1, 23), - MUX_GATE(CLK_TOP_IRTX_SEL, f10m_ref_parents, 0xA0, 24, 1, 31), + MUX_GATE_MIXED(CLK_TOP_AUD1_SEL, aud1_parents, 0xA0, 0, 1, 7), + MUX_GATE_MIXED(CLK_TOP_AUD2_SEL, aud1_parents, 0xA0, 8, 1, 15), + MUX_GATE_MIXED(CLK_TOP_IRRX_SEL, f10m_ref_parents, 0xA0, 16, 1, 23), + MUX_GATE_MIXED(CLK_TOP_IRTX_SEL, f10m_ref_parents, 0xA0, 24, 1, 31), /* CLK_CFG_7 */ - MUX_GATE(CLK_TOP_ASM_L_SEL, asm_l_parents, 0xB0, 0, 2, 7), - MUX_GATE(CLK_TOP_ASM_M_SEL, asm_l_parents, 0xB0, 8, 2, 15), - MUX_GATE(CLK_TOP_ASM_H_SEL, asm_l_parents, 0xB0, 16, 2, 23), + MUX_GATE_MIXED(CLK_TOP_ASM_L_SEL, asm_l_parents, 0xB0, 0, 2, 7), + MUX_GATE_MIXED(CLK_TOP_ASM_M_SEL, asm_l_parents, 0xB0, 8, 2, 15), + MUX_GATE_MIXED(CLK_TOP_ASM_H_SEL, asm_l_parents, 0xB0, 16, 2, 23), /* CLK_AUDDIV_0 */ - MUX(CLK_TOP_APLL1_SEL, apll1_ck_parents, 0x120, 6, 1), - MUX(CLK_TOP_APLL2_SEL, apll1_ck_parents, 0x120, 7, 1), - MUX(CLK_TOP_I2S0_MCK_SEL, apll1_ck_parents, 0x120, 8, 1), - MUX(CLK_TOP_I2S1_MCK_SEL, apll1_ck_parents, 0x120, 9, 1), - MUX(CLK_TOP_I2S2_MCK_SEL, apll1_ck_parents, 0x120, 10, 1), - MUX(CLK_TOP_I2S3_MCK_SEL, apll1_ck_parents, 0x120, 161, 1), + MUX_MIXED(CLK_TOP_APLL1_SEL, apll1_ck_parents, 0x120, 6, 1), + MUX_MIXED(CLK_TOP_APLL2_SEL, apll1_ck_parents, 0x120, 7, 1), + MUX_MIXED(CLK_TOP_I2S0_MCK_SEL, apll1_ck_parents, 0x120, 8, 1), + MUX_MIXED(CLK_TOP_I2S1_MCK_SEL, apll1_ck_parents, 0x120, 9, 1), + MUX_MIXED(CLK_TOP_I2S2_MCK_SEL, apll1_ck_parents, 0x120, 10, 1), + MUX_MIXED(CLK_TOP_I2S3_MCK_SEL, apll1_ck_parents, 0x120, 161, 1), }; /* infracfg */ @@ -423,16 +423,13 @@ static const struct mtk_gate infra_cgs[] = { }; /* pericfg */ -static const int peribus_ck_parents[] = { - CLK_TOP_SYSPLL1_D8, - CLK_TOP_SYSPLL1_D4, +static const struct mtk_parent peribus_ck_parents[] = { + TOP_PARENT(CLK_TOP_SYSPLL1_D8), + TOP_PARENT(CLK_TOP_SYSPLL1_D4), }; -#define PERI_MUX(_id, _parents, _reg, _shift, _width) \ - MUX_FLAGS(_id, _parents, _reg, _shift, _width, CLK_PARENT_TOPCKGEN) - static const struct mtk_composite peri_muxes[] = { - PERI_MUX(CLK_PERIBUS_SEL, peribus_ck_parents, 0x05c, 0, 1), + MUX_MIXED(CLK_PERIBUS_SEL, peribus_ck_parents, 0x05c, 0, 1), }; static const struct mtk_gate_regs peri0_cg_regs = { -- cgit v1.3.1 From b3455b3986dc510861d959739b31e65ab7d16814 Mon Sep 17 00:00:00 2001 From: David Lechner Date: Tue, 17 Mar 2026 18:23:15 -0500 Subject: clk: mediatek: mt7623: convert to struct mtk_parent Convert all parent clock arrays to use struct mtk_parent. This will allow us to simplify core code later by having only one possible data type for mux parent arrays. Reviewed-by: Julien Stephan Link: https://patch.msgid.link/20260317-clk-mtk-unify-mux-parents-v3-2-a4760f5b0a80@baylibre.com Signed-off-by: David Lechner --- drivers/clk/mediatek/clk-mt7623.c | 774 +++++++++++++++++++------------------- 1 file changed, 387 insertions(+), 387 deletions(-) diff --git a/drivers/clk/mediatek/clk-mt7623.c b/drivers/clk/mediatek/clk-mt7623.c index d52555283d2..9bb2a1af734 100644 --- a/drivers/clk/mediatek/clk-mt7623.c +++ b/drivers/clk/mediatek/clk-mt7623.c @@ -375,399 +375,399 @@ static const struct mtk_fixed_factor top_fixed_divs[] = { FACTOR1(CLK_TOP_8BDAC, CLK_TOP_UNIVPLL_D2, 1, 1), }; -static const int axi_parents[] = { - CLK_XTAL, - CLK_TOP_SYSPLL1_D2, - CLK_TOP_SYSPLL_D5, - CLK_TOP_SYSPLL1_D4, - CLK_TOP_UNIVPLL_D5, - CLK_TOP_UNIVPLL2_D2, - CLK_TOP_MMPLL_D2, - CLK_TOP_DMPLL_D2 -}; - -static const int mem_parents[] = { - CLK_XTAL, - CLK_TOP_DMPLL -}; - -static const int ddrphycfg_parents[] = { - CLK_XTAL, - CLK_TOP_SYSPLL1_D8 -}; - -static const int mm_parents[] = { - CLK_XTAL, - CLK_TOP_VENCPLL, - CLK_TOP_SYSPLL1_D2, - CLK_TOP_SYSPLL1_D4, - CLK_TOP_UNIVPLL_D5, - CLK_TOP_UNIVPLL1_D2, - CLK_TOP_UNIVPLL2_D2, - CLK_TOP_DMPLL -}; - -static const int pwm_parents[] = { - CLK_XTAL, - CLK_TOP_UNIVPLL2_D4, - CLK_TOP_UNIVPLL3_D2, - CLK_TOP_UNIVPLL1_D4 -}; - -static const int vdec_parents[] = { - CLK_XTAL, - CLK_TOP_VDECPLL, - CLK_TOP_SYSPLL_D5, - CLK_TOP_SYSPLL1_D4, - CLK_TOP_UNIVPLL_D5, - CLK_TOP_UNIVPLL2_D2, - CLK_TOP_VENCPLL, - CLK_TOP_MSDCPLL_D2, - CLK_TOP_MMPLL_D2 -}; - -static const int mfg_parents[] = { - CLK_XTAL, - CLK_TOP_MMPLL, - CLK_TOP_DMPLL_X2, - CLK_TOP_MSDCPLL, - CLK_XTAL, - CLK_TOP_SYSPLL_D3, - CLK_TOP_UNIVPLL_D3, - CLK_TOP_UNIVPLL1_D2 -}; - -static const int camtg_parents[] = { - CLK_XTAL, - CLK_TOP_UNIVPLL_D26, - CLK_TOP_UNIVPLL2_D2, - CLK_TOP_SYSPLL3_D2, - CLK_TOP_SYSPLL3_D4, - CLK_TOP_MSDCPLL_D2, - CLK_TOP_MMPLL_D2 -}; - -static const int uart_parents[] = { - CLK_XTAL, - CLK_TOP_UNIVPLL2_D8 -}; - -static const int spi_parents[] = { - CLK_XTAL, - CLK_TOP_SYSPLL3_D2, - CLK_TOP_SYSPLL4_D2, - CLK_TOP_UNIVPLL2_D4, - CLK_TOP_UNIVPLL1_D8 -}; - -static const int usb20_parents[] = { - CLK_XTAL, - CLK_TOP_UNIVPLL1_D8, - CLK_TOP_UNIVPLL3_D4 -}; - -static const int msdc30_parents[] = { - CLK_XTAL, - CLK_TOP_MSDCPLL_D2, - CLK_TOP_SYSPLL2_D2, - CLK_TOP_SYSPLL1_D4, - CLK_TOP_UNIVPLL1_D4, - CLK_TOP_UNIVPLL2_D4, -}; - -static const int aud_intbus_parents[] = { - CLK_XTAL, - CLK_TOP_SYSPLL1_D4, - CLK_TOP_SYSPLL3_D2, - CLK_TOP_SYSPLL4_D2, - CLK_TOP_UNIVPLL3_D2, - CLK_TOP_UNIVPLL2_D4 -}; - -static const int pmicspi_parents[] = { - CLK_XTAL, - CLK_TOP_SYSPLL1_D8, - CLK_TOP_SYSPLL2_D4, - CLK_TOP_SYSPLL4_D2, - CLK_TOP_SYSPLL3_D4, - CLK_TOP_SYSPLL2_D8, - CLK_TOP_SYSPLL1_D16, - CLK_TOP_UNIVPLL3_D4, - CLK_TOP_UNIVPLL_D26, - CLK_TOP_DMPLL_D2, - CLK_TOP_DMPLL_D4 -}; - -static const int scp_parents[] = { - CLK_XTAL, - CLK_TOP_SYSPLL1_D8, - CLK_TOP_DMPLL_D2, - CLK_TOP_DMPLL_D4 -}; - -static const int dpi0_tve_parents[] = { - CLK_XTAL, - CLK_TOP_MIPIPLL, - CLK_TOP_MIPIPLL_D2, - CLK_TOP_MIPIPLL_D4, - CLK_XTAL, - CLK_TOP_TVDPLL, - CLK_TOP_TVDPLL_D2, - CLK_TOP_TVDPLL_D4 -}; - -static const int dpi1_parents[] = { - CLK_XTAL, - CLK_TOP_TVDPLL, - CLK_TOP_TVDPLL_D2, - CLK_TOP_TVDPLL_D4 -}; - -static const int hdmi_parents[] = { - CLK_XTAL, - CLK_TOP_HDMIPLL, - CLK_TOP_HDMIPLL_D2, - CLK_TOP_HDMIPLL_D3 -}; - -static const int apll_parents[] = { - CLK_XTAL, - CLK_TOP_AUDPLL, - CLK_TOP_AUDPLL_D4, - CLK_TOP_AUDPLL_D8, - CLK_TOP_AUDPLL_D16, - CLK_TOP_AUDPLL_D24, - CLK_XTAL, - CLK_XTAL -}; - -static const int rtc_parents[] = { - CLK_TOP_32K_INTERNAL, - CLK_TOP_32K_EXTERNAL, - CLK_XTAL, - CLK_TOP_UNIVPLL3_D8 -}; - -static const int nfi2x_parents[] = { - CLK_XTAL, - CLK_TOP_SYSPLL2_D2, - CLK_TOP_SYSPLL_D7, - CLK_TOP_UNIVPLL3_D2, - CLK_TOP_SYSPLL2_D4, - CLK_TOP_UNIVPLL3_D4, - CLK_TOP_SYSPLL4_D4, - CLK_XTAL -}; - -static const int emmc_hclk_parents[] = { - CLK_XTAL, - CLK_TOP_SYSPLL1_D2, - CLK_TOP_SYSPLL1_D4, - CLK_TOP_SYSPLL2_D2 -}; - -static const int flash_parents[] = { - CLK_TOP_CLK26M_D8, - CLK_XTAL, - CLK_TOP_SYSPLL2_D8, - CLK_TOP_SYSPLL3_D4, - CLK_TOP_UNIVPLL3_D4, - CLK_TOP_SYSPLL4_D2, - CLK_TOP_SYSPLL2_D4, - CLK_TOP_UNIVPLL2_D4 -}; - -static const int di_parents[] = { - CLK_XTAL, - CLK_TOP_TVD2PLL, - CLK_TOP_TVD2PLL_D2, - CLK_XTAL -}; - -static const int nr_osd_parents[] = { - CLK_XTAL, - CLK_TOP_VENCPLL, - CLK_TOP_SYSPLL1_D2, - CLK_TOP_SYSPLL1_D4, - CLK_TOP_UNIVPLL_D5, - CLK_TOP_UNIVPLL1_D2, - CLK_TOP_UNIVPLL2_D2, - CLK_TOP_DMPLL -}; - -static const int hdmirx_bist_parents[] = { - CLK_XTAL, - CLK_TOP_SYSPLL_D3, - CLK_XTAL, - CLK_TOP_SYSPLL1_D16, - CLK_TOP_SYSPLL4_D2, - CLK_TOP_SYSPLL1_D4, - CLK_TOP_VENCPLL, - CLK_XTAL -}; - -static const int intdir_parents[] = { - CLK_XTAL, - CLK_TOP_MMPLL, - CLK_TOP_SYSPLL_D2, - CLK_TOP_UNIVPLL_D2 -}; - -static const int asm_parents[] = { - CLK_XTAL, - CLK_TOP_UNIVPLL2_D4, - CLK_TOP_UNIVPLL2_D2, - CLK_TOP_SYSPLL_D5 -}; - -static const int ms_card_parents[] = { - CLK_XTAL, - CLK_TOP_UNIVPLL3_D8, - CLK_TOP_SYSPLL4_D4 -}; - -static const int ethif_parents[] = { - CLK_XTAL, - CLK_TOP_SYSPLL1_D2, - CLK_TOP_SYSPLL_D5, - CLK_TOP_SYSPLL1_D4, - CLK_TOP_UNIVPLL_D5, - CLK_TOP_UNIVPLL1_D2, - CLK_TOP_DMPLL, - CLK_TOP_DMPLL_D2 -}; - -static const int hdmirx_parents[] = { - CLK_XTAL, - CLK_TOP_UNIVPLL_D52 -}; - -static const int cmsys_parents[] = { - CLK_XTAL, - CLK_TOP_SYSPLL1_D2, - CLK_TOP_UNIVPLL1_D2, - CLK_TOP_UNIVPLL_D5, - CLK_TOP_SYSPLL_D5, - CLK_TOP_SYSPLL2_D2, - CLK_TOP_SYSPLL1_D4, - CLK_TOP_SYSPLL3_D2, - CLK_TOP_SYSPLL2_D4, - CLK_TOP_SYSPLL1_D8, - CLK_XTAL, - CLK_XTAL, - CLK_XTAL, - CLK_XTAL, - CLK_XTAL -}; - -static const int clk_8bdac_parents[] = { - CLK_TOP_32K_INTERNAL, - CLK_TOP_8BDAC, - CLK_XTAL, - CLK_XTAL -}; - -static const int aud2dvd_parents[] = { - CLK_TOP_AUD_48K_TIMING, - CLK_TOP_AUD_44K_TIMING -}; - -static const int padmclk_parents[] = { - CLK_XTAL, - CLK_TOP_UNIVPLL_D26, - CLK_TOP_UNIVPLL_D52, - CLK_TOP_UNIVPLL_D108, - CLK_TOP_UNIVPLL2_D8, - CLK_TOP_UNIVPLL2_D16, - CLK_TOP_UNIVPLL2_D32 -}; +static const struct mtk_parent axi_parents[] = { + XTAL_PARENT(CLK_XTAL), + TOP_PARENT(CLK_TOP_SYSPLL1_D2), + TOP_PARENT(CLK_TOP_SYSPLL_D5), + TOP_PARENT(CLK_TOP_SYSPLL1_D4), + TOP_PARENT(CLK_TOP_UNIVPLL_D5), + TOP_PARENT(CLK_TOP_UNIVPLL2_D2), + TOP_PARENT(CLK_TOP_MMPLL_D2), + TOP_PARENT(CLK_TOP_DMPLL_D2), +}; + +static const struct mtk_parent mem_parents[] = { + XTAL_PARENT(CLK_XTAL), + TOP_PARENT(CLK_TOP_DMPLL), +}; + +static const struct mtk_parent ddrphycfg_parents[] = { + XTAL_PARENT(CLK_XTAL), + TOP_PARENT(CLK_TOP_SYSPLL1_D8), +}; + +static const struct mtk_parent mm_parents[] = { + XTAL_PARENT(CLK_XTAL), + TOP_PARENT(CLK_TOP_VENCPLL), + TOP_PARENT(CLK_TOP_SYSPLL1_D2), + TOP_PARENT(CLK_TOP_SYSPLL1_D4), + TOP_PARENT(CLK_TOP_UNIVPLL_D5), + TOP_PARENT(CLK_TOP_UNIVPLL1_D2), + TOP_PARENT(CLK_TOP_UNIVPLL2_D2), + TOP_PARENT(CLK_TOP_DMPLL), +}; + +static const struct mtk_parent pwm_parents[] = { + XTAL_PARENT(CLK_XTAL), + TOP_PARENT(CLK_TOP_UNIVPLL2_D4), + TOP_PARENT(CLK_TOP_UNIVPLL3_D2), + TOP_PARENT(CLK_TOP_UNIVPLL1_D4), +}; + +static const struct mtk_parent vdec_parents[] = { + XTAL_PARENT(CLK_XTAL), + TOP_PARENT(CLK_TOP_VDECPLL), + TOP_PARENT(CLK_TOP_SYSPLL_D5), + TOP_PARENT(CLK_TOP_SYSPLL1_D4), + TOP_PARENT(CLK_TOP_UNIVPLL_D5), + TOP_PARENT(CLK_TOP_UNIVPLL2_D2), + TOP_PARENT(CLK_TOP_VENCPLL), + TOP_PARENT(CLK_TOP_MSDCPLL_D2), + TOP_PARENT(CLK_TOP_MMPLL_D2), +}; + +static const struct mtk_parent mfg_parents[] = { + XTAL_PARENT(CLK_XTAL), + TOP_PARENT(CLK_TOP_MMPLL), + TOP_PARENT(CLK_TOP_DMPLL_X2), + TOP_PARENT(CLK_TOP_MSDCPLL), + XTAL_PARENT(CLK_XTAL), + TOP_PARENT(CLK_TOP_SYSPLL_D3), + TOP_PARENT(CLK_TOP_UNIVPLL_D3), + TOP_PARENT(CLK_TOP_UNIVPLL1_D2), +}; + +static const struct mtk_parent camtg_parents[] = { + XTAL_PARENT(CLK_XTAL), + TOP_PARENT(CLK_TOP_UNIVPLL_D26), + TOP_PARENT(CLK_TOP_UNIVPLL2_D2), + TOP_PARENT(CLK_TOP_SYSPLL3_D2), + TOP_PARENT(CLK_TOP_SYSPLL3_D4), + TOP_PARENT(CLK_TOP_MSDCPLL_D2), + TOP_PARENT(CLK_TOP_MMPLL_D2), +}; + +static const struct mtk_parent uart_parents[] = { + XTAL_PARENT(CLK_XTAL), + TOP_PARENT(CLK_TOP_UNIVPLL2_D8), +}; + +static const struct mtk_parent spi_parents[] = { + XTAL_PARENT(CLK_XTAL), + TOP_PARENT(CLK_TOP_SYSPLL3_D2), + TOP_PARENT(CLK_TOP_SYSPLL4_D2), + TOP_PARENT(CLK_TOP_UNIVPLL2_D4), + TOP_PARENT(CLK_TOP_UNIVPLL1_D8), +}; + +static const struct mtk_parent usb20_parents[] = { + XTAL_PARENT(CLK_XTAL), + TOP_PARENT(CLK_TOP_UNIVPLL1_D8), + TOP_PARENT(CLK_TOP_UNIVPLL3_D4), +}; + +static const struct mtk_parent msdc30_parents[] = { + XTAL_PARENT(CLK_XTAL), + TOP_PARENT(CLK_TOP_MSDCPLL_D2), + TOP_PARENT(CLK_TOP_SYSPLL2_D2), + TOP_PARENT(CLK_TOP_SYSPLL1_D4), + TOP_PARENT(CLK_TOP_UNIVPLL1_D4), + TOP_PARENT(CLK_TOP_UNIVPLL2_D4), +}; + +static const struct mtk_parent aud_intbus_parents[] = { + XTAL_PARENT(CLK_XTAL), + TOP_PARENT(CLK_TOP_SYSPLL1_D4), + TOP_PARENT(CLK_TOP_SYSPLL3_D2), + TOP_PARENT(CLK_TOP_SYSPLL4_D2), + TOP_PARENT(CLK_TOP_UNIVPLL3_D2), + TOP_PARENT(CLK_TOP_UNIVPLL2_D4), +}; + +static const struct mtk_parent pmicspi_parents[] = { + XTAL_PARENT(CLK_XTAL), + TOP_PARENT(CLK_TOP_SYSPLL1_D8), + TOP_PARENT(CLK_TOP_SYSPLL2_D4), + TOP_PARENT(CLK_TOP_SYSPLL4_D2), + TOP_PARENT(CLK_TOP_SYSPLL3_D4), + TOP_PARENT(CLK_TOP_SYSPLL2_D8), + TOP_PARENT(CLK_TOP_SYSPLL1_D16), + TOP_PARENT(CLK_TOP_UNIVPLL3_D4), + TOP_PARENT(CLK_TOP_UNIVPLL_D26), + TOP_PARENT(CLK_TOP_DMPLL_D2), + TOP_PARENT(CLK_TOP_DMPLL_D4), +}; + +static const struct mtk_parent scp_parents[] = { + XTAL_PARENT(CLK_XTAL), + TOP_PARENT(CLK_TOP_SYSPLL1_D8), + TOP_PARENT(CLK_TOP_DMPLL_D2), + TOP_PARENT(CLK_TOP_DMPLL_D4), +}; + +static const struct mtk_parent dpi0_tve_parents[] = { + XTAL_PARENT(CLK_XTAL), + TOP_PARENT(CLK_TOP_MIPIPLL), + TOP_PARENT(CLK_TOP_MIPIPLL_D2), + TOP_PARENT(CLK_TOP_MIPIPLL_D4), + XTAL_PARENT(CLK_XTAL), + TOP_PARENT(CLK_TOP_TVDPLL), + TOP_PARENT(CLK_TOP_TVDPLL_D2), + TOP_PARENT(CLK_TOP_TVDPLL_D4), +}; + +static const struct mtk_parent dpi1_parents[] = { + XTAL_PARENT(CLK_XTAL), + TOP_PARENT(CLK_TOP_TVDPLL), + TOP_PARENT(CLK_TOP_TVDPLL_D2), + TOP_PARENT(CLK_TOP_TVDPLL_D4), +}; + +static const struct mtk_parent hdmi_parents[] = { + XTAL_PARENT(CLK_XTAL), + TOP_PARENT(CLK_TOP_HDMIPLL), + TOP_PARENT(CLK_TOP_HDMIPLL_D2), + TOP_PARENT(CLK_TOP_HDMIPLL_D3), +}; + +static const struct mtk_parent apll_parents[] = { + XTAL_PARENT(CLK_XTAL), + TOP_PARENT(CLK_TOP_AUDPLL), + TOP_PARENT(CLK_TOP_AUDPLL_D4), + TOP_PARENT(CLK_TOP_AUDPLL_D8), + TOP_PARENT(CLK_TOP_AUDPLL_D16), + TOP_PARENT(CLK_TOP_AUDPLL_D24), + XTAL_PARENT(CLK_XTAL), + XTAL_PARENT(CLK_XTAL), +}; -static const int aud_mux_parents[] = { - CLK_XTAL, - CLK_TOP_AUD1PLL_98M, - CLK_TOP_AUD2PLL_90M, - CLK_TOP_HADDS2PLL_98M, - CLK_TOP_AUD_EXTCK1_DIV, - CLK_TOP_AUD_EXTCK2_DIV +static const struct mtk_parent rtc_parents[] = { + TOP_PARENT(CLK_TOP_32K_INTERNAL), + TOP_PARENT(CLK_TOP_32K_EXTERNAL), + XTAL_PARENT(CLK_XTAL), + TOP_PARENT(CLK_TOP_UNIVPLL3_D8), +}; + +static const struct mtk_parent nfi2x_parents[] = { + XTAL_PARENT(CLK_XTAL), + TOP_PARENT(CLK_TOP_SYSPLL2_D2), + TOP_PARENT(CLK_TOP_SYSPLL_D7), + TOP_PARENT(CLK_TOP_UNIVPLL3_D2), + TOP_PARENT(CLK_TOP_SYSPLL2_D4), + TOP_PARENT(CLK_TOP_UNIVPLL3_D4), + TOP_PARENT(CLK_TOP_SYSPLL4_D4), + XTAL_PARENT(CLK_XTAL), +}; + +static const struct mtk_parent emmc_hclk_parents[] = { + XTAL_PARENT(CLK_XTAL), + TOP_PARENT(CLK_TOP_SYSPLL1_D2), + TOP_PARENT(CLK_TOP_SYSPLL1_D4), + TOP_PARENT(CLK_TOP_SYSPLL2_D2), +}; + +static const struct mtk_parent flash_parents[] = { + TOP_PARENT(CLK_TOP_CLK26M_D8), + XTAL_PARENT(CLK_XTAL), + TOP_PARENT(CLK_TOP_SYSPLL2_D8), + TOP_PARENT(CLK_TOP_SYSPLL3_D4), + TOP_PARENT(CLK_TOP_UNIVPLL3_D4), + TOP_PARENT(CLK_TOP_SYSPLL4_D2), + TOP_PARENT(CLK_TOP_SYSPLL2_D4), + TOP_PARENT(CLK_TOP_UNIVPLL2_D4), +}; + +static const struct mtk_parent di_parents[] = { + XTAL_PARENT(CLK_XTAL), + TOP_PARENT(CLK_TOP_TVD2PLL), + TOP_PARENT(CLK_TOP_TVD2PLL_D2), + XTAL_PARENT(CLK_XTAL), +}; + +static const struct mtk_parent nr_osd_parents[] = { + XTAL_PARENT(CLK_XTAL), + TOP_PARENT(CLK_TOP_VENCPLL), + TOP_PARENT(CLK_TOP_SYSPLL1_D2), + TOP_PARENT(CLK_TOP_SYSPLL1_D4), + TOP_PARENT(CLK_TOP_UNIVPLL_D5), + TOP_PARENT(CLK_TOP_UNIVPLL1_D2), + TOP_PARENT(CLK_TOP_UNIVPLL2_D2), + TOP_PARENT(CLK_TOP_DMPLL), +}; + +static const struct mtk_parent hdmirx_bist_parents[] = { + XTAL_PARENT(CLK_XTAL), + TOP_PARENT(CLK_TOP_SYSPLL_D3), + XTAL_PARENT(CLK_XTAL), + TOP_PARENT(CLK_TOP_SYSPLL1_D16), + TOP_PARENT(CLK_TOP_SYSPLL4_D2), + TOP_PARENT(CLK_TOP_SYSPLL1_D4), + TOP_PARENT(CLK_TOP_VENCPLL), + XTAL_PARENT(CLK_XTAL), +}; + +static const struct mtk_parent intdir_parents[] = { + XTAL_PARENT(CLK_XTAL), + TOP_PARENT(CLK_TOP_MMPLL), + TOP_PARENT(CLK_TOP_SYSPLL_D2), + TOP_PARENT(CLK_TOP_UNIVPLL_D2), +}; + +static const struct mtk_parent asm_parents[] = { + XTAL_PARENT(CLK_XTAL), + TOP_PARENT(CLK_TOP_UNIVPLL2_D4), + TOP_PARENT(CLK_TOP_UNIVPLL2_D2), + TOP_PARENT(CLK_TOP_SYSPLL_D5), +}; + +static const struct mtk_parent ms_card_parents[] = { + XTAL_PARENT(CLK_XTAL), + TOP_PARENT(CLK_TOP_UNIVPLL3_D8), + TOP_PARENT(CLK_TOP_SYSPLL4_D4), +}; + +static const struct mtk_parent ethif_parents[] = { + XTAL_PARENT(CLK_XTAL), + TOP_PARENT(CLK_TOP_SYSPLL1_D2), + TOP_PARENT(CLK_TOP_SYSPLL_D5), + TOP_PARENT(CLK_TOP_SYSPLL1_D4), + TOP_PARENT(CLK_TOP_UNIVPLL_D5), + TOP_PARENT(CLK_TOP_UNIVPLL1_D2), + TOP_PARENT(CLK_TOP_DMPLL), + TOP_PARENT(CLK_TOP_DMPLL_D2), +}; + +static const struct mtk_parent hdmirx_parents[] = { + XTAL_PARENT(CLK_XTAL), + TOP_PARENT(CLK_TOP_UNIVPLL_D52), +}; + +static const struct mtk_parent cmsys_parents[] = { + XTAL_PARENT(CLK_XTAL), + TOP_PARENT(CLK_TOP_SYSPLL1_D2), + TOP_PARENT(CLK_TOP_UNIVPLL1_D2), + TOP_PARENT(CLK_TOP_UNIVPLL_D5), + TOP_PARENT(CLK_TOP_SYSPLL_D5), + TOP_PARENT(CLK_TOP_SYSPLL2_D2), + TOP_PARENT(CLK_TOP_SYSPLL1_D4), + TOP_PARENT(CLK_TOP_SYSPLL3_D2), + TOP_PARENT(CLK_TOP_SYSPLL2_D4), + TOP_PARENT(CLK_TOP_SYSPLL1_D8), + XTAL_PARENT(CLK_XTAL), + XTAL_PARENT(CLK_XTAL), + XTAL_PARENT(CLK_XTAL), + XTAL_PARENT(CLK_XTAL), + XTAL_PARENT(CLK_XTAL), +}; + +static const struct mtk_parent clk_8bdac_parents[] = { + TOP_PARENT(CLK_TOP_32K_INTERNAL), + TOP_PARENT(CLK_TOP_8BDAC), + XTAL_PARENT(CLK_XTAL), + XTAL_PARENT(CLK_XTAL), +}; + +static const struct mtk_parent aud2dvd_parents[] = { + TOP_PARENT(CLK_TOP_AUD_48K_TIMING), + TOP_PARENT(CLK_TOP_AUD_44K_TIMING), +}; + +static const struct mtk_parent padmclk_parents[] = { + XTAL_PARENT(CLK_XTAL), + TOP_PARENT(CLK_TOP_UNIVPLL_D26), + TOP_PARENT(CLK_TOP_UNIVPLL_D52), + TOP_PARENT(CLK_TOP_UNIVPLL_D108), + TOP_PARENT(CLK_TOP_UNIVPLL2_D8), + TOP_PARENT(CLK_TOP_UNIVPLL2_D16), + TOP_PARENT(CLK_TOP_UNIVPLL2_D32), +}; + +static const struct mtk_parent aud_mux_parents[] = { + XTAL_PARENT(CLK_XTAL), + TOP_PARENT(CLK_TOP_AUD1PLL_98M), + TOP_PARENT(CLK_TOP_AUD2PLL_90M), + TOP_PARENT(CLK_TOP_HADDS2PLL_98M), + TOP_PARENT(CLK_TOP_AUD_EXTCK1_DIV), + TOP_PARENT(CLK_TOP_AUD_EXTCK2_DIV), }; -static const int aud_src_parents[] = { - CLK_TOP_AUD_MUX1_SEL, - CLK_TOP_AUD_MUX2_SEL +static const struct mtk_parent aud_src_parents[] = { + TOP_PARENT(CLK_TOP_AUD_MUX1_SEL), + TOP_PARENT(CLK_TOP_AUD_MUX2_SEL), }; static const struct mtk_composite top_muxes[] = { - MUX_GATE(CLK_TOP_AXI_SEL, axi_parents, 0x40, 0, 3, 7), - MUX_GATE(CLK_TOP_MEM_SEL, mem_parents, 0x40, 8, 1, 15), - MUX_GATE(CLK_TOP_DDRPHYCFG_SEL, ddrphycfg_parents, 0x40, 16, 1, 23), - MUX_GATE_FLAGS(CLK_TOP_MM_SEL, mm_parents, 0x40, 24, 3, 31, - CLK_MUX_DOMAIN_SCPSYS), - - MUX_GATE(CLK_TOP_PWM_SEL, pwm_parents, 0x50, 0, 2, 7), - MUX_GATE(CLK_TOP_VDEC_SEL, vdec_parents, 0x50, 8, 4, 15), - MUX_GATE_FLAGS(CLK_TOP_MFG_SEL, mfg_parents, 0x50, 16, 3, 23, - CLK_MUX_DOMAIN_SCPSYS), - MUX_GATE(CLK_TOP_CAMTG_SEL, camtg_parents, 0x50, 24, 3, 31), - - MUX_GATE(CLK_TOP_UART_SEL, uart_parents, 0x60, 0, 1, 7), - MUX_GATE(CLK_TOP_SPI0_SEL, spi_parents, 0x60, 8, 3, 15), - MUX_GATE(CLK_TOP_USB20_SEL, usb20_parents, 0x60, 16, 2, 23), - MUX_GATE(CLK_TOP_MSDC30_0_SEL, msdc30_parents, 0x60, 24, 3, 31), - - MUX_GATE(CLK_TOP_MSDC30_1_SEL, msdc30_parents, 0x70, 0, 3, 7), - MUX_GATE(CLK_TOP_MSDC30_2_SEL, msdc30_parents, 0x70, 8, 3, 15), - MUX_GATE(CLK_TOP_AUDIO_SEL, msdc30_parents, 0x70, 16, 1, 23), - MUX_GATE(CLK_TOP_AUDINTBUS_SEL, aud_intbus_parents, 0x70, 24, 3, 31), - - MUX_GATE(CLK_TOP_PMICSPI_SEL, pmicspi_parents, 0x80, 0, 4, 7), - MUX_GATE(CLK_TOP_SCP_SEL, scp_parents, 0x80, 8, 2, 15), - MUX_GATE(CLK_TOP_DPI0_SEL, dpi0_tve_parents, 0x80, 16, 3, 23), - MUX_GATE(CLK_TOP_DPI1_SEL, dpi1_parents, 0x80, 24, 2, 31), - - MUX_GATE(CLK_TOP_TVE_SEL, dpi0_tve_parents, 0x90, 0, 3, 7), - MUX_GATE(CLK_TOP_HDMI_SEL, hdmi_parents, 0x90, 8, 2, 15), - MUX_GATE(CLK_TOP_APLL_SEL, apll_parents, 0x90, 16, 3, 23), - - MUX_GATE(CLK_TOP_RTC_SEL, rtc_parents, 0xA0, 0, 2, 7), - MUX_GATE(CLK_TOP_NFI2X_SEL, nfi2x_parents, 0xA0, 8, 3, 15), - MUX_GATE(CLK_TOP_EMMC_HCLK_SEL, emmc_hclk_parents, 0xA0, 24, 2, 31), - - MUX_GATE(CLK_TOP_FLASH_SEL, flash_parents, 0xB0, 0, 3, 7), - MUX_GATE(CLK_TOP_DI_SEL, di_parents, 0xB0, 8, 2, 15), - MUX_GATE(CLK_TOP_NR_SEL, nr_osd_parents, 0xB0, 16, 3, 23), - MUX_GATE(CLK_TOP_OSD_SEL, nr_osd_parents, 0xB0, 24, 3, 31), - - MUX_GATE(CLK_TOP_HDMIRX_BIST_SEL, hdmirx_bist_parents, 0xC0, 0, 3, 7), - MUX_GATE(CLK_TOP_INTDIR_SEL, intdir_parents, 0xC0, 8, 2, 15), - MUX_GATE(CLK_TOP_ASM_I_SEL, asm_parents, 0xC0, 16, 2, 23), - MUX_GATE(CLK_TOP_ASM_M_SEL, asm_parents, 0xC0, 24, 3, 31), - - MUX_GATE(CLK_TOP_ASM_H_SEL, asm_parents, 0xD0, 0, 2, 7), - MUX_GATE(CLK_TOP_MS_CARD_SEL, ms_card_parents, 0xD0, 16, 2, 23), - MUX_GATE_FLAGS(CLK_TOP_ETHIF_SEL, ethif_parents, 0xD0, 24, 3, 31, - CLK_MUX_DOMAIN_SCPSYS), - - MUX_GATE(CLK_TOP_HDMIRX26_24_SEL, hdmirx_parents, 0xE0, 0, 1, 7), - MUX_GATE(CLK_TOP_MSDC30_3_SEL, msdc30_parents, 0xE0, 8, 3, 15), - MUX_GATE(CLK_TOP_CMSYS_SEL, cmsys_parents, 0xE0, 16, 4, 23), - - MUX_GATE(CLK_TOP_SPI1_SEL, spi_parents, 0xE0, 24, 3, 31), - MUX_GATE(CLK_TOP_SPI2_SEL, spi_parents, 0xF0, 0, 3, 7), - MUX_GATE(CLK_TOP_8BDAC_SEL, clk_8bdac_parents, 0xF0, 8, 2, 15), - MUX_GATE(CLK_TOP_AUD2DVD_SEL, aud2dvd_parents, 0xF0, 16, 1, 23), - - MUX(CLK_TOP_PADMCLK_SEL, padmclk_parents, 0x100, 0, 3), - - MUX(CLK_TOP_AUD_MUX1_SEL, aud_mux_parents, 0x12c, 0, 3), - MUX(CLK_TOP_AUD_MUX2_SEL, aud_mux_parents, 0x12c, 3, 3), - MUX(CLK_TOP_AUDPLL_MUX_SEL, aud_mux_parents, 0x12c, 6, 3), - - MUX_GATE(CLK_TOP_AUD_K1_SRC_SEL, aud_src_parents, 0x12c, 15, 1, 23), - MUX_GATE(CLK_TOP_AUD_K2_SRC_SEL, aud_src_parents, 0x12c, 16, 1, 24), - MUX_GATE(CLK_TOP_AUD_K3_SRC_SEL, aud_src_parents, 0x12c, 17, 1, 25), - MUX_GATE(CLK_TOP_AUD_K4_SRC_SEL, aud_src_parents, 0x12c, 18, 1, 26), - MUX_GATE(CLK_TOP_AUD_K5_SRC_SEL, aud_src_parents, 0x12c, 19, 1, 27), - MUX_GATE(CLK_TOP_AUD_K6_SRC_SEL, aud_src_parents, 0x12c, 20, 1, 28), + MUX_GATE_MIXED(CLK_TOP_AXI_SEL, axi_parents, 0x40, 0, 3, 7), + MUX_GATE_MIXED(CLK_TOP_MEM_SEL, mem_parents, 0x40, 8, 1, 15), + MUX_GATE_MIXED(CLK_TOP_DDRPHYCFG_SEL, ddrphycfg_parents, 0x40, 16, 1, 23), + MUX_GATE_MIXED_FLAGS(CLK_TOP_MM_SEL, mm_parents, 0x40, 24, 3, 31, + CLK_MUX_DOMAIN_SCPSYS), + + MUX_GATE_MIXED(CLK_TOP_PWM_SEL, pwm_parents, 0x50, 0, 2, 7), + MUX_GATE_MIXED(CLK_TOP_VDEC_SEL, vdec_parents, 0x50, 8, 4, 15), + MUX_GATE_MIXED_FLAGS(CLK_TOP_MFG_SEL, mfg_parents, 0x50, 16, 3, 23, + CLK_MUX_DOMAIN_SCPSYS), + MUX_GATE_MIXED(CLK_TOP_CAMTG_SEL, camtg_parents, 0x50, 24, 3, 31), + + MUX_GATE_MIXED(CLK_TOP_UART_SEL, uart_parents, 0x60, 0, 1, 7), + MUX_GATE_MIXED(CLK_TOP_SPI0_SEL, spi_parents, 0x60, 8, 3, 15), + MUX_GATE_MIXED(CLK_TOP_USB20_SEL, usb20_parents, 0x60, 16, 2, 23), + MUX_GATE_MIXED(CLK_TOP_MSDC30_0_SEL, msdc30_parents, 0x60, 24, 3, 31), + + MUX_GATE_MIXED(CLK_TOP_MSDC30_1_SEL, msdc30_parents, 0x70, 0, 3, 7), + MUX_GATE_MIXED(CLK_TOP_MSDC30_2_SEL, msdc30_parents, 0x70, 8, 3, 15), + MUX_GATE_MIXED(CLK_TOP_AUDIO_SEL, msdc30_parents, 0x70, 16, 1, 23), + MUX_GATE_MIXED(CLK_TOP_AUDINTBUS_SEL, aud_intbus_parents, 0x70, 24, 3, 31), + + MUX_GATE_MIXED(CLK_TOP_PMICSPI_SEL, pmicspi_parents, 0x80, 0, 4, 7), + MUX_GATE_MIXED(CLK_TOP_SCP_SEL, scp_parents, 0x80, 8, 2, 15), + MUX_GATE_MIXED(CLK_TOP_DPI0_SEL, dpi0_tve_parents, 0x80, 16, 3, 23), + MUX_GATE_MIXED(CLK_TOP_DPI1_SEL, dpi1_parents, 0x80, 24, 2, 31), + + MUX_GATE_MIXED(CLK_TOP_TVE_SEL, dpi0_tve_parents, 0x90, 0, 3, 7), + MUX_GATE_MIXED(CLK_TOP_HDMI_SEL, hdmi_parents, 0x90, 8, 2, 15), + MUX_GATE_MIXED(CLK_TOP_APLL_SEL, apll_parents, 0x90, 16, 3, 23), + + MUX_GATE_MIXED(CLK_TOP_RTC_SEL, rtc_parents, 0xA0, 0, 2, 7), + MUX_GATE_MIXED(CLK_TOP_NFI2X_SEL, nfi2x_parents, 0xA0, 8, 3, 15), + MUX_GATE_MIXED(CLK_TOP_EMMC_HCLK_SEL, emmc_hclk_parents, 0xA0, 24, 2, 31), + + MUX_GATE_MIXED(CLK_TOP_FLASH_SEL, flash_parents, 0xB0, 0, 3, 7), + MUX_GATE_MIXED(CLK_TOP_DI_SEL, di_parents, 0xB0, 8, 2, 15), + MUX_GATE_MIXED(CLK_TOP_NR_SEL, nr_osd_parents, 0xB0, 16, 3, 23), + MUX_GATE_MIXED(CLK_TOP_OSD_SEL, nr_osd_parents, 0xB0, 24, 3, 31), + + MUX_GATE_MIXED(CLK_TOP_HDMIRX_BIST_SEL, hdmirx_bist_parents, 0xC0, 0, 3, 7), + MUX_GATE_MIXED(CLK_TOP_INTDIR_SEL, intdir_parents, 0xC0, 8, 2, 15), + MUX_GATE_MIXED(CLK_TOP_ASM_I_SEL, asm_parents, 0xC0, 16, 2, 23), + MUX_GATE_MIXED(CLK_TOP_ASM_M_SEL, asm_parents, 0xC0, 24, 3, 31), + + MUX_GATE_MIXED(CLK_TOP_ASM_H_SEL, asm_parents, 0xD0, 0, 2, 7), + MUX_GATE_MIXED(CLK_TOP_MS_CARD_SEL, ms_card_parents, 0xD0, 16, 2, 23), + MUX_GATE_MIXED_FLAGS(CLK_TOP_ETHIF_SEL, ethif_parents, 0xD0, 24, 3, 31, + CLK_MUX_DOMAIN_SCPSYS), + + MUX_GATE_MIXED(CLK_TOP_HDMIRX26_24_SEL, hdmirx_parents, 0xE0, 0, 1, 7), + MUX_GATE_MIXED(CLK_TOP_MSDC30_3_SEL, msdc30_parents, 0xE0, 8, 3, 15), + MUX_GATE_MIXED(CLK_TOP_CMSYS_SEL, cmsys_parents, 0xE0, 16, 4, 23), + + MUX_GATE_MIXED(CLK_TOP_SPI1_SEL, spi_parents, 0xE0, 24, 3, 31), + MUX_GATE_MIXED(CLK_TOP_SPI2_SEL, spi_parents, 0xF0, 0, 3, 7), + MUX_GATE_MIXED(CLK_TOP_8BDAC_SEL, clk_8bdac_parents, 0xF0, 8, 2, 15), + MUX_GATE_MIXED(CLK_TOP_AUD2DVD_SEL, aud2dvd_parents, 0xF0, 16, 1, 23), + + MUX_MIXED(CLK_TOP_PADMCLK_SEL, padmclk_parents, 0x100, 0, 3), + + MUX_MIXED(CLK_TOP_AUD_MUX1_SEL, aud_mux_parents, 0x12c, 0, 3), + MUX_MIXED(CLK_TOP_AUD_MUX2_SEL, aud_mux_parents, 0x12c, 3, 3), + MUX_MIXED(CLK_TOP_AUDPLL_MUX_SEL, aud_mux_parents, 0x12c, 6, 3), + + MUX_GATE_MIXED(CLK_TOP_AUD_K1_SRC_SEL, aud_src_parents, 0x12c, 15, 1, 23), + MUX_GATE_MIXED(CLK_TOP_AUD_K2_SRC_SEL, aud_src_parents, 0x12c, 16, 1, 24), + MUX_GATE_MIXED(CLK_TOP_AUD_K3_SRC_SEL, aud_src_parents, 0x12c, 17, 1, 25), + MUX_GATE_MIXED(CLK_TOP_AUD_K4_SRC_SEL, aud_src_parents, 0x12c, 18, 1, 26), + MUX_GATE_MIXED(CLK_TOP_AUD_K5_SRC_SEL, aud_src_parents, 0x12c, 19, 1, 27), + MUX_GATE_MIXED(CLK_TOP_AUD_K6_SRC_SEL, aud_src_parents, 0x12c, 20, 1, 28), }; /* infracfg */ -- cgit v1.3.1 From 5e145c044811e0b46f3e9b82d87d7e771e5fbc6e Mon Sep 17 00:00:00 2001 From: David Lechner Date: Tue, 17 Mar 2026 18:23:16 -0500 Subject: clk: mediatek: mt7629: convert to struct mtk_parent Convert all parent clock arrays to use struct mtk_parent. This will allow us to simplify core code later by having only one possible data type for mux parent arrays. Reviewed-by: Julien Stephan Link: https://patch.msgid.link/20260317-clk-mtk-unify-mux-parents-v3-3-a4760f5b0a80@baylibre.com Signed-off-by: David Lechner --- drivers/clk/mediatek/clk-mt7629.c | 440 +++++++++++++++++++------------------- 1 file changed, 220 insertions(+), 220 deletions(-) diff --git a/drivers/clk/mediatek/clk-mt7629.c b/drivers/clk/mediatek/clk-mt7629.c index 1d697539ce2..c675104d573 100644 --- a/drivers/clk/mediatek/clk-mt7629.c +++ b/drivers/clk/mediatek/clk-mt7629.c @@ -152,271 +152,271 @@ static const struct mtk_fixed_factor top_fixed_divs[] = { FACTOR1(CLK_TOP_PCIE0_MAC_EN, CLK_TOP_UNIVPLL1_D4, 1, 1), }; -static const int axi_parents[] = { - CLK_XTAL, - CLK_TOP_SYSPLL1_D2, - CLK_TOP_SYSPLL_D5, - CLK_TOP_SYSPLL1_D4, - CLK_TOP_UNIVPLL_D5, - CLK_TOP_UNIVPLL2_D2, - CLK_TOP_UNIVPLL_D7, - CLK_TOP_DMPLL -}; - -static const int mem_parents[] = { - CLK_XTAL, - CLK_TOP_DMPLL -}; - -static const int ddrphycfg_parents[] = { - CLK_XTAL, - CLK_TOP_SYSPLL1_D8 -}; - -static const int eth_parents[] = { - CLK_XTAL, - CLK_TOP_SYSPLL1_D2, - CLK_TOP_UNIVPLL1_D2, - CLK_TOP_SYSPLL1_D4, - CLK_TOP_UNIVPLL_D5, - CLK_TOP_SGMIIPLL_D2, - CLK_TOP_UNIVPLL_D7, - CLK_TOP_DMPLL -}; - -static const int pwm_parents[] = { - CLK_XTAL, - CLK_TOP_UNIVPLL2_D4 -}; - -static const int sgmii_ref_1_parents[] = { - CLK_XTAL, - CLK_TOP_SGMIIPLL_D2 -}; - -static const int nfi_infra_parents[] = { - CLK_XTAL, - CLK_XTAL, - CLK_XTAL, - CLK_XTAL, - CLK_XTAL, - CLK_XTAL, - CLK_TOP_UNIVPLL2_D8, - CLK_TOP_UNIVPLL3_D4, - CLK_TOP_SYSPLL1_D8, - CLK_TOP_UNIVPLL1_D8, - CLK_TOP_SYSPLL4_D2, - CLK_TOP_SYSPLL2_D4, - CLK_TOP_UNIVPLL2_D4, - CLK_TOP_UNIVPLL3_D2, - CLK_TOP_SYSPLL1_D4, - CLK_TOP_SYSPLL_D7 -}; - -static const int flash_parents[] = { - CLK_XTAL, - CLK_TOP_UNIVPLL_D80_D4, - CLK_TOP_SYSPLL2_D8, - CLK_TOP_SYSPLL3_D4, - CLK_TOP_UNIVPLL3_D4, - CLK_TOP_UNIVPLL1_D8, - CLK_TOP_SYSPLL2_D4, - CLK_TOP_UNIVPLL2_D4 -}; - -static const int uart_parents[] = { - CLK_XTAL, - CLK_TOP_UNIVPLL2_D8 -}; - -static const int spi0_parents[] = { - CLK_XTAL, - CLK_TOP_SYSPLL3_D2, - CLK_XTAL, - CLK_TOP_SYSPLL2_D4, - CLK_TOP_SYSPLL4_D2, - CLK_TOP_UNIVPLL2_D4, - CLK_TOP_UNIVPLL1_D8, - CLK_XTAL -}; - -static const int spi1_parents[] = { - CLK_XTAL, - CLK_TOP_SYSPLL3_D2, - CLK_XTAL, - CLK_TOP_SYSPLL4_D4, - CLK_TOP_SYSPLL4_D2, - CLK_TOP_UNIVPLL2_D4, - CLK_TOP_UNIVPLL1_D8, - CLK_XTAL -}; - -static const int msdc30_0_parents[] = { - CLK_XTAL, - CLK_TOP_UNIVPLL2_D16, - CLK_TOP_UNIV48M -}; - -static const int msdc30_1_parents[] = { - CLK_XTAL, - CLK_TOP_UNIVPLL2_D16, - CLK_TOP_UNIV48M, - CLK_TOP_SYSPLL2_D4, - CLK_TOP_UNIVPLL2_D4, - CLK_TOP_SYSPLL_D7, - CLK_TOP_SYSPLL2_D2, - CLK_TOP_UNIVPLL2_D2 +static const struct mtk_parent axi_parents[] = { + XTAL_PARENT(CLK_XTAL), + TOP_PARENT(CLK_TOP_SYSPLL1_D2), + TOP_PARENT(CLK_TOP_SYSPLL_D5), + TOP_PARENT(CLK_TOP_SYSPLL1_D4), + TOP_PARENT(CLK_TOP_UNIVPLL_D5), + TOP_PARENT(CLK_TOP_UNIVPLL2_D2), + TOP_PARENT(CLK_TOP_UNIVPLL_D7), + TOP_PARENT(CLK_TOP_DMPLL), +}; + +static const struct mtk_parent mem_parents[] = { + XTAL_PARENT(CLK_XTAL), + TOP_PARENT(CLK_TOP_DMPLL), +}; + +static const struct mtk_parent ddrphycfg_parents[] = { + XTAL_PARENT(CLK_XTAL), + TOP_PARENT(CLK_TOP_SYSPLL1_D8), +}; + +static const struct mtk_parent eth_parents[] = { + XTAL_PARENT(CLK_XTAL), + TOP_PARENT(CLK_TOP_SYSPLL1_D2), + TOP_PARENT(CLK_TOP_UNIVPLL1_D2), + TOP_PARENT(CLK_TOP_SYSPLL1_D4), + TOP_PARENT(CLK_TOP_UNIVPLL_D5), + TOP_PARENT(CLK_TOP_SGMIIPLL_D2), + TOP_PARENT(CLK_TOP_UNIVPLL_D7), + TOP_PARENT(CLK_TOP_DMPLL), +}; + +static const struct mtk_parent pwm_parents[] = { + XTAL_PARENT(CLK_XTAL), + TOP_PARENT(CLK_TOP_UNIVPLL2_D4), +}; + +static const struct mtk_parent sgmii_ref_1_parents[] = { + XTAL_PARENT(CLK_XTAL), + TOP_PARENT(CLK_TOP_SGMIIPLL_D2), +}; + +static const struct mtk_parent nfi_infra_parents[] = { + XTAL_PARENT(CLK_XTAL), + XTAL_PARENT(CLK_XTAL), + XTAL_PARENT(CLK_XTAL), + XTAL_PARENT(CLK_XTAL), + XTAL_PARENT(CLK_XTAL), + XTAL_PARENT(CLK_XTAL), + TOP_PARENT(CLK_TOP_UNIVPLL2_D8), + TOP_PARENT(CLK_TOP_UNIVPLL3_D4), + TOP_PARENT(CLK_TOP_SYSPLL1_D8), + TOP_PARENT(CLK_TOP_UNIVPLL1_D8), + TOP_PARENT(CLK_TOP_SYSPLL4_D2), + TOP_PARENT(CLK_TOP_SYSPLL2_D4), + TOP_PARENT(CLK_TOP_UNIVPLL2_D4), + TOP_PARENT(CLK_TOP_UNIVPLL3_D2), + TOP_PARENT(CLK_TOP_SYSPLL1_D4), + TOP_PARENT(CLK_TOP_SYSPLL_D7), +}; + +static const struct mtk_parent flash_parents[] = { + XTAL_PARENT(CLK_XTAL), + TOP_PARENT(CLK_TOP_UNIVPLL_D80_D4), + TOP_PARENT(CLK_TOP_SYSPLL2_D8), + TOP_PARENT(CLK_TOP_SYSPLL3_D4), + TOP_PARENT(CLK_TOP_UNIVPLL3_D4), + TOP_PARENT(CLK_TOP_UNIVPLL1_D8), + TOP_PARENT(CLK_TOP_SYSPLL2_D4), + TOP_PARENT(CLK_TOP_UNIVPLL2_D4), +}; + +static const struct mtk_parent uart_parents[] = { + XTAL_PARENT(CLK_XTAL), + TOP_PARENT(CLK_TOP_UNIVPLL2_D8), +}; + +static const struct mtk_parent spi0_parents[] = { + XTAL_PARENT(CLK_XTAL), + TOP_PARENT(CLK_TOP_SYSPLL3_D2), + XTAL_PARENT(CLK_XTAL), + TOP_PARENT(CLK_TOP_SYSPLL2_D4), + TOP_PARENT(CLK_TOP_SYSPLL4_D2), + TOP_PARENT(CLK_TOP_UNIVPLL2_D4), + TOP_PARENT(CLK_TOP_UNIVPLL1_D8), + XTAL_PARENT(CLK_XTAL), +}; + +static const struct mtk_parent spi1_parents[] = { + XTAL_PARENT(CLK_XTAL), + TOP_PARENT(CLK_TOP_SYSPLL3_D2), + XTAL_PARENT(CLK_XTAL), + TOP_PARENT(CLK_TOP_SYSPLL4_D4), + TOP_PARENT(CLK_TOP_SYSPLL4_D2), + TOP_PARENT(CLK_TOP_UNIVPLL2_D4), + TOP_PARENT(CLK_TOP_UNIVPLL1_D8), + XTAL_PARENT(CLK_XTAL), +}; + +static const struct mtk_parent msdc30_0_parents[] = { + XTAL_PARENT(CLK_XTAL), + TOP_PARENT(CLK_TOP_UNIVPLL2_D16), + TOP_PARENT(CLK_TOP_UNIV48M), +}; + +static const struct mtk_parent msdc30_1_parents[] = { + XTAL_PARENT(CLK_XTAL), + TOP_PARENT(CLK_TOP_UNIVPLL2_D16), + TOP_PARENT(CLK_TOP_UNIV48M), + TOP_PARENT(CLK_TOP_SYSPLL2_D4), + TOP_PARENT(CLK_TOP_UNIVPLL2_D4), + TOP_PARENT(CLK_TOP_SYSPLL_D7), + TOP_PARENT(CLK_TOP_SYSPLL2_D2), + TOP_PARENT(CLK_TOP_UNIVPLL2_D2), }; -static const int ap2wbmcu_parents[] = { - CLK_XTAL, - CLK_TOP_SYSPLL1_D2, - CLK_TOP_UNIV48M, - CLK_TOP_SYSPLL1_D8, - CLK_TOP_UNIVPLL2_D4, - CLK_TOP_SYSPLL_D7, - CLK_TOP_SYSPLL2_D2, - CLK_TOP_UNIVPLL2_D2 +static const struct mtk_parent ap2wbmcu_parents[] = { + XTAL_PARENT(CLK_XTAL), + TOP_PARENT(CLK_TOP_SYSPLL1_D2), + TOP_PARENT(CLK_TOP_UNIV48M), + TOP_PARENT(CLK_TOP_SYSPLL1_D8), + TOP_PARENT(CLK_TOP_UNIVPLL2_D4), + TOP_PARENT(CLK_TOP_SYSPLL_D7), + TOP_PARENT(CLK_TOP_SYSPLL2_D2), + TOP_PARENT(CLK_TOP_UNIVPLL2_D2), }; -static const int audio_parents[] = { - CLK_XTAL, - CLK_TOP_SYSPLL3_D4, - CLK_TOP_SYSPLL4_D4, - CLK_TOP_SYSPLL1_D16 +static const struct mtk_parent audio_parents[] = { + XTAL_PARENT(CLK_XTAL), + TOP_PARENT(CLK_TOP_SYSPLL3_D4), + TOP_PARENT(CLK_TOP_SYSPLL4_D4), + TOP_PARENT(CLK_TOP_SYSPLL1_D16), }; -static const int aud_intbus_parents[] = { - CLK_XTAL, - CLK_TOP_SYSPLL1_D4, - CLK_TOP_SYSPLL4_D2, - CLK_TOP_DMPLL_D4 -}; +static const struct mtk_parent aud_intbus_parents[] = { + XTAL_PARENT(CLK_XTAL), + TOP_PARENT(CLK_TOP_SYSPLL1_D4), + TOP_PARENT(CLK_TOP_SYSPLL4_D2), + TOP_PARENT(CLK_TOP_DMPLL_D4), +}; -static const int pmicspi_parents[] = { - CLK_XTAL, - CLK_TOP_SYSPLL1_D8, - CLK_TOP_SYSPLL3_D4, - CLK_TOP_SYSPLL1_D16, - CLK_TOP_UNIVPLL3_D4, - CLK_XTAL, - CLK_TOP_UNIVPLL2_D4, - CLK_TOP_DMPLL_D8 +static const struct mtk_parent pmicspi_parents[] = { + XTAL_PARENT(CLK_XTAL), + TOP_PARENT(CLK_TOP_SYSPLL1_D8), + TOP_PARENT(CLK_TOP_SYSPLL3_D4), + TOP_PARENT(CLK_TOP_SYSPLL1_D16), + TOP_PARENT(CLK_TOP_UNIVPLL3_D4), + XTAL_PARENT(CLK_XTAL), + TOP_PARENT(CLK_TOP_UNIVPLL2_D4), + TOP_PARENT(CLK_TOP_DMPLL_D8), }; -static const int scp_parents[] = { - CLK_XTAL, - CLK_TOP_SYSPLL1_D8, - CLK_TOP_UNIVPLL2_D2, - CLK_TOP_UNIVPLL2_D4 +static const struct mtk_parent scp_parents[] = { + XTAL_PARENT(CLK_XTAL), + TOP_PARENT(CLK_TOP_SYSPLL1_D8), + TOP_PARENT(CLK_TOP_UNIVPLL2_D2), + TOP_PARENT(CLK_TOP_UNIVPLL2_D4), }; -static const int atb_parents[] = { - CLK_XTAL, - CLK_TOP_SYSPLL1_D2, - CLK_TOP_SYSPLL_D5 +static const struct mtk_parent atb_parents[] = { + XTAL_PARENT(CLK_XTAL), + TOP_PARENT(CLK_TOP_SYSPLL1_D2), + TOP_PARENT(CLK_TOP_SYSPLL_D5), }; -static const int hif_parents[] = { - CLK_XTAL, - CLK_TOP_SYSPLL1_D2, - CLK_TOP_UNIVPLL1_D2, - CLK_TOP_SYSPLL1_D4, - CLK_TOP_UNIVPLL_D5, - -1, - CLK_TOP_UNIVPLL_D7 +static const struct mtk_parent hif_parents[] = { + XTAL_PARENT(CLK_XTAL), + TOP_PARENT(CLK_TOP_SYSPLL1_D2), + TOP_PARENT(CLK_TOP_UNIVPLL1_D2), + TOP_PARENT(CLK_TOP_SYSPLL1_D4), + TOP_PARENT(CLK_TOP_UNIVPLL_D5), + VOID_PARENT, + TOP_PARENT(CLK_TOP_UNIVPLL_D7), }; -static const int sata_parents[] = { - CLK_XTAL, - CLK_TOP_UNIVPLL2_D4 +static const struct mtk_parent sata_parents[] = { + XTAL_PARENT(CLK_XTAL), + TOP_PARENT(CLK_TOP_UNIVPLL2_D4), }; -static const int usb20_parents[] = { - CLK_XTAL, - CLK_TOP_UNIVPLL3_D4, - CLK_TOP_SYSPLL1_D8 +static const struct mtk_parent usb20_parents[] = { + XTAL_PARENT(CLK_XTAL), + TOP_PARENT(CLK_TOP_UNIVPLL3_D4), + TOP_PARENT(CLK_TOP_SYSPLL1_D8), }; -static const int aud1_parents[] = { - CLK_XTAL +static const struct mtk_parent aud1_parents[] = { + XTAL_PARENT(CLK_XTAL), }; -static const int irrx_parents[] = { - CLK_XTAL, - CLK_TOP_SYSPLL4_D16 +static const struct mtk_parent irrx_parents[] = { + XTAL_PARENT(CLK_XTAL), + TOP_PARENT(CLK_TOP_SYSPLL4_D16), }; -static const int crypto_parents[] = { - CLK_XTAL, - CLK_TOP_UNIVPLL_D3, - CLK_TOP_UNIVPLL1_D2, - CLK_TOP_SYSPLL1_D2, - CLK_TOP_UNIVPLL_D5, - CLK_TOP_SYSPLL_D5, - CLK_TOP_UNIVPLL2_D2, - CLK_TOP_SYSPLL_D2 +static const struct mtk_parent crypto_parents[] = { + XTAL_PARENT(CLK_XTAL), + TOP_PARENT(CLK_TOP_UNIVPLL_D3), + TOP_PARENT(CLK_TOP_UNIVPLL1_D2), + TOP_PARENT(CLK_TOP_SYSPLL1_D2), + TOP_PARENT(CLK_TOP_UNIVPLL_D5), + TOP_PARENT(CLK_TOP_SYSPLL_D5), + TOP_PARENT(CLK_TOP_UNIVPLL2_D2), + TOP_PARENT(CLK_TOP_SYSPLL_D2), }; -static const int gpt10m_parents[] = { - CLK_XTAL, - CLK_TOP_CLKXTAL_D4 +static const struct mtk_parent gpt10m_parents[] = { + XTAL_PARENT(CLK_XTAL), + TOP_PARENT(CLK_TOP_CLKXTAL_D4), }; static const struct mtk_composite top_muxes[] = { /* CLK_CFG_0 */ - MUX_GATE(CLK_TOP_AXI_SEL, axi_parents, 0x40, 0, 3, 7), - MUX_GATE(CLK_TOP_MEM_SEL, mem_parents, 0x40, 8, 1, 15), - MUX_GATE(CLK_TOP_DDRPHYCFG_SEL, ddrphycfg_parents, 0x40, 16, 1, 23), - MUX_GATE(CLK_TOP_ETH_SEL, eth_parents, 0x40, 24, 3, 31), + MUX_GATE_MIXED(CLK_TOP_AXI_SEL, axi_parents, 0x40, 0, 3, 7), + MUX_GATE_MIXED(CLK_TOP_MEM_SEL, mem_parents, 0x40, 8, 1, 15), + MUX_GATE_MIXED(CLK_TOP_DDRPHYCFG_SEL, ddrphycfg_parents, 0x40, 16, 1, 23), + MUX_GATE_MIXED(CLK_TOP_ETH_SEL, eth_parents, 0x40, 24, 3, 31), /* CLK_CFG_1 */ - MUX_GATE(CLK_TOP_PWM_SEL, pwm_parents, 0x50, 0, 2, 7), - MUX_GATE(CLK_TOP_F10M_REF_SEL, irrx_parents, 0x50, 8, 1, 15), - MUX_GATE(CLK_TOP_NFI_INFRA_SEL, nfi_infra_parents, 0x50, 16, 4, 23), - MUX_GATE(CLK_TOP_FLASH_SEL, flash_parents, 0x50, 24, 3, 31), + MUX_GATE_MIXED(CLK_TOP_PWM_SEL, pwm_parents, 0x50, 0, 2, 7), + MUX_GATE_MIXED(CLK_TOP_F10M_REF_SEL, irrx_parents, 0x50, 8, 1, 15), + MUX_GATE_MIXED(CLK_TOP_NFI_INFRA_SEL, nfi_infra_parents, 0x50, 16, 4, 23), + MUX_GATE_MIXED(CLK_TOP_FLASH_SEL, flash_parents, 0x50, 24, 3, 31), /* CLK_CFG_2 */ - MUX_GATE(CLK_TOP_UART_SEL, uart_parents, 0x60, 0, 1, 7), - MUX_GATE(CLK_TOP_SPI0_SEL, spi0_parents, 0x60, 8, 3, 15), - MUX_GATE(CLK_TOP_SPI1_SEL, spi1_parents, 0x60, 16, 3, 23), - MUX_GATE(CLK_TOP_MSDC50_0_SEL, uart_parents, 0x60, 24, 3, 31), + MUX_GATE_MIXED(CLK_TOP_UART_SEL, uart_parents, 0x60, 0, 1, 7), + MUX_GATE_MIXED(CLK_TOP_SPI0_SEL, spi0_parents, 0x60, 8, 3, 15), + MUX_GATE_MIXED(CLK_TOP_SPI1_SEL, spi1_parents, 0x60, 16, 3, 23), + MUX_GATE_MIXED(CLK_TOP_MSDC50_0_SEL, uart_parents, 0x60, 24, 3, 31), /* CLK_CFG_3 */ - MUX_GATE(CLK_TOP_MSDC30_0_SEL, msdc30_0_parents, 0x70, 0, 3, 7), - MUX_GATE(CLK_TOP_MSDC30_1_SEL, msdc30_1_parents, 0x70, 8, 3, 15), - MUX_GATE(CLK_TOP_AP2WBMCU_SEL, ap2wbmcu_parents, 0x70, 16, 3, 23), - MUX_GATE(CLK_TOP_AP2WBHIF_SEL, ap2wbmcu_parents, 0x70, 24, 3, 31), + MUX_GATE_MIXED(CLK_TOP_MSDC30_0_SEL, msdc30_0_parents, 0x70, 0, 3, 7), + MUX_GATE_MIXED(CLK_TOP_MSDC30_1_SEL, msdc30_1_parents, 0x70, 8, 3, 15), + MUX_GATE_MIXED(CLK_TOP_AP2WBMCU_SEL, ap2wbmcu_parents, 0x70, 16, 3, 23), + MUX_GATE_MIXED(CLK_TOP_AP2WBHIF_SEL, ap2wbmcu_parents, 0x70, 24, 3, 31), /* CLK_CFG_4 */ - MUX_GATE(CLK_TOP_AUDIO_SEL, audio_parents, 0x80, 0, 2, 7), - MUX_GATE(CLK_TOP_AUD_INTBUS_SEL, aud_intbus_parents, 0x80, 8, 2, 15), - MUX_GATE(CLK_TOP_PMICSPI_SEL, pmicspi_parents, 0x80, 16, 3, 23), - MUX_GATE(CLK_TOP_SCP_SEL, scp_parents, 0x80, 24, 2, 31), + MUX_GATE_MIXED(CLK_TOP_AUDIO_SEL, audio_parents, 0x80, 0, 2, 7), + MUX_GATE_MIXED(CLK_TOP_AUD_INTBUS_SEL, aud_intbus_parents, 0x80, 8, 2, 15), + MUX_GATE_MIXED(CLK_TOP_PMICSPI_SEL, pmicspi_parents, 0x80, 16, 3, 23), + MUX_GATE_MIXED(CLK_TOP_SCP_SEL, scp_parents, 0x80, 24, 2, 31), /* CLK_CFG_5 */ - MUX_GATE(CLK_TOP_ATB_SEL, atb_parents, 0x90, 0, 2, 7), - MUX_GATE_FLAGS(CLK_TOP_HIF_SEL, hif_parents, 0x90, 8, 3, 15, - CLK_MUX_DOMAIN_SCPSYS), - MUX_GATE(CLK_TOP_SATA_SEL, sata_parents, 0x90, 16, 1, 23), - MUX_GATE(CLK_TOP_U2_SEL, usb20_parents, 0x90, 24, 2, 31), + MUX_GATE_MIXED(CLK_TOP_ATB_SEL, atb_parents, 0x90, 0, 2, 7), + MUX_GATE_MIXED_FLAGS(CLK_TOP_HIF_SEL, hif_parents, 0x90, 8, 3, 15, + CLK_MUX_DOMAIN_SCPSYS), + MUX_GATE_MIXED(CLK_TOP_SATA_SEL, sata_parents, 0x90, 16, 1, 23), + MUX_GATE_MIXED(CLK_TOP_U2_SEL, usb20_parents, 0x90, 24, 2, 31), /* CLK_CFG_6 */ - MUX_GATE(CLK_TOP_AUD1_SEL, aud1_parents, 0xA0, 0, 1, 7), - MUX_GATE(CLK_TOP_AUD2_SEL, aud1_parents, 0xA0, 8, 1, 15), - MUX_GATE(CLK_TOP_IRRX_SEL, irrx_parents, 0xA0, 16, 1, 23), - MUX_GATE(CLK_TOP_IRTX_SEL, irrx_parents, 0xA0, 24, 1, 31), + MUX_GATE_MIXED(CLK_TOP_AUD1_SEL, aud1_parents, 0xA0, 0, 1, 7), + MUX_GATE_MIXED(CLK_TOP_AUD2_SEL, aud1_parents, 0xA0, 8, 1, 15), + MUX_GATE_MIXED(CLK_TOP_IRRX_SEL, irrx_parents, 0xA0, 16, 1, 23), + MUX_GATE_MIXED(CLK_TOP_IRTX_SEL, irrx_parents, 0xA0, 24, 1, 31), /* CLK_CFG_7 */ - MUX_GATE(CLK_TOP_SATA_MCU_SEL, scp_parents, 0xB0, 0, 2, 7), - MUX_GATE(CLK_TOP_PCIE0_MCU_SEL, scp_parents, 0xB0, 8, 2, 15), - MUX_GATE(CLK_TOP_PCIE1_MCU_SEL, scp_parents, 0xB0, 16, 2, 23), - MUX_GATE(CLK_TOP_SSUSB_MCU_SEL, scp_parents, 0xB0, 24, 2, 31), + MUX_GATE_MIXED(CLK_TOP_SATA_MCU_SEL, scp_parents, 0xB0, 0, 2, 7), + MUX_GATE_MIXED(CLK_TOP_PCIE0_MCU_SEL, scp_parents, 0xB0, 8, 2, 15), + MUX_GATE_MIXED(CLK_TOP_PCIE1_MCU_SEL, scp_parents, 0xB0, 16, 2, 23), + MUX_GATE_MIXED(CLK_TOP_SSUSB_MCU_SEL, scp_parents, 0xB0, 24, 2, 31), /* CLK_CFG_8 */ - MUX_GATE(CLK_TOP_CRYPTO_SEL, crypto_parents, 0xC0, 0, 3, 7), - MUX_GATE(CLK_TOP_SGMII_REF_1_SEL, sgmii_ref_1_parents, 0xC0, 8, 1, 15), - MUX_GATE(CLK_TOP_10M_SEL, gpt10m_parents, 0xC0, 16, 1, 23), + MUX_GATE_MIXED(CLK_TOP_CRYPTO_SEL, crypto_parents, 0xC0, 0, 3, 7), + MUX_GATE_MIXED(CLK_TOP_SGMII_REF_1_SEL, sgmii_ref_1_parents, 0xC0, 8, 1, 15), + MUX_GATE_MIXED(CLK_TOP_10M_SEL, gpt10m_parents, 0xC0, 16, 1, 23), }; /* infracfg */ -- cgit v1.3.1 From 8fd90b148f265beaa4ef768dbebf624c07c5088a Mon Sep 17 00:00:00 2001 From: David Lechner Date: Tue, 17 Mar 2026 18:23:17 -0500 Subject: clk: mediatek: mt7981: convert to struct mtk_parent Convert all parent clock arrays to use struct mtk_parent. This will allow us to simplify core code later by having only one possible data type for mux parent arrays. Reviewed-by: Julien Stephan Link: https://patch.msgid.link/20260317-clk-mtk-unify-mux-parents-v3-4-a4760f5b0a80@baylibre.com Signed-off-by: David Lechner --- drivers/clk/mediatek/clk-mt7981.c | 226 +++++++++++++++++++++++++++----------- 1 file changed, 162 insertions(+), 64 deletions(-) diff --git a/drivers/clk/mediatek/clk-mt7981.c b/drivers/clk/mediatek/clk-mt7981.c index 40e8429521a..0c770a0bd93 100644 --- a/drivers/clk/mediatek/clk-mt7981.c +++ b/drivers/clk/mediatek/clk-mt7981.c @@ -139,97 +139,194 @@ static const struct mtk_fixed_factor top_fixed_divs[] = { }; /* TOPCKGEN MUX PARENTS */ -static const int nfi1x_parents[] = { CLK_TOP_CB_CKSQ_40M, CLK_TOP_CB_MM_D4, - CLK_TOP_NET1_D8_D2, CLK_TOP_CB_NET2_D6, - CLK_TOP_CB_M_D4, CLK_TOP_CB_MM_D8, - CLK_TOP_NET1_D8_D4, CLK_TOP_CB_M_D8 }; +static const struct mtk_parent nfi1x_parents[] = { + TOP_PARENT(CLK_TOP_CB_CKSQ_40M), + TOP_PARENT(CLK_TOP_CB_MM_D4), + TOP_PARENT(CLK_TOP_NET1_D8_D2), + TOP_PARENT(CLK_TOP_CB_NET2_D6), + TOP_PARENT(CLK_TOP_CB_M_D4), + TOP_PARENT(CLK_TOP_CB_MM_D8), + TOP_PARENT(CLK_TOP_NET1_D8_D4), + TOP_PARENT(CLK_TOP_CB_M_D8), +}; -static const int spinfi_parents[] = { CLK_TOP_CKSQ_40M_D2, CLK_TOP_CB_CKSQ_40M, - CLK_TOP_NET1_D5_D4, CLK_TOP_CB_M_D4, - CLK_TOP_CB_MM_D8, CLK_TOP_NET1_D8_D4, - CLK_TOP_MM_D6_D2, CLK_TOP_CB_M_D8 }; +static const struct mtk_parent spinfi_parents[] = { + TOP_PARENT(CLK_TOP_CKSQ_40M_D2), + TOP_PARENT(CLK_TOP_CB_CKSQ_40M), + TOP_PARENT(CLK_TOP_NET1_D5_D4), + TOP_PARENT(CLK_TOP_CB_M_D4), + TOP_PARENT(CLK_TOP_CB_MM_D8), + TOP_PARENT(CLK_TOP_NET1_D8_D4), + TOP_PARENT(CLK_TOP_MM_D6_D2), + TOP_PARENT(CLK_TOP_CB_M_D8), +}; -static const int spi_parents[] = { CLK_TOP_CB_CKSQ_40M, CLK_TOP_CB_M_D2, - CLK_TOP_CB_MM_D4, CLK_TOP_NET1_D8_D2, - CLK_TOP_CB_NET2_D6, CLK_TOP_NET1_D5_D4, - CLK_TOP_CB_M_D4, CLK_TOP_NET1_D8_D4 }; +static const struct mtk_parent spi_parents[] = { + TOP_PARENT(CLK_TOP_CB_CKSQ_40M), + TOP_PARENT(CLK_TOP_CB_M_D2), + TOP_PARENT(CLK_TOP_CB_MM_D4), + TOP_PARENT(CLK_TOP_NET1_D8_D2), + TOP_PARENT(CLK_TOP_CB_NET2_D6), + TOP_PARENT(CLK_TOP_NET1_D5_D4), + TOP_PARENT(CLK_TOP_CB_M_D4), + TOP_PARENT(CLK_TOP_NET1_D8_D4), +}; -static const int uart_parents[] = { CLK_TOP_CB_CKSQ_40M, CLK_TOP_CB_M_D8, - CLK_TOP_M_D8_D2 }; +static const struct mtk_parent uart_parents[] = { + TOP_PARENT(CLK_TOP_CB_CKSQ_40M), + TOP_PARENT(CLK_TOP_CB_M_D8), + TOP_PARENT(CLK_TOP_M_D8_D2), +}; -static const int pwm_parents[] = { CLK_TOP_CB_CKSQ_40M, CLK_TOP_NET1_D8_D2, - CLK_TOP_NET1_D5_D4, CLK_TOP_CB_M_D4, - CLK_TOP_M_D8_D2, CLK_TOP_CB_RTC_32K }; +static const struct mtk_parent pwm_parents[] = { + TOP_PARENT(CLK_TOP_CB_CKSQ_40M), + TOP_PARENT(CLK_TOP_NET1_D8_D2), + TOP_PARENT(CLK_TOP_NET1_D5_D4), + TOP_PARENT(CLK_TOP_CB_M_D4), + TOP_PARENT(CLK_TOP_M_D8_D2), + TOP_PARENT(CLK_TOP_CB_RTC_32K), +}; -static const int i2c_parents[] = { CLK_TOP_CB_CKSQ_40M, CLK_TOP_NET1_D5_D4, - CLK_TOP_CB_M_D4, CLK_TOP_NET1_D8_D4 }; +static const struct mtk_parent i2c_parents[] = { + TOP_PARENT(CLK_TOP_CB_CKSQ_40M), + TOP_PARENT(CLK_TOP_NET1_D5_D4), + TOP_PARENT(CLK_TOP_CB_M_D4), + TOP_PARENT(CLK_TOP_NET1_D8_D4), +}; -static const int pextp_tl_ck_parents[] = { CLK_TOP_CB_CKSQ_40M, - CLK_TOP_NET1_D5_D4, CLK_TOP_CB_M_D4, - CLK_TOP_CB_RTC_32K }; +static const struct mtk_parent pextp_tl_ck_parents[] = { + TOP_PARENT(CLK_TOP_CB_CKSQ_40M), + TOP_PARENT(CLK_TOP_NET1_D5_D4), + TOP_PARENT(CLK_TOP_CB_M_D4), + TOP_PARENT(CLK_TOP_CB_RTC_32K), +}; -static const int emmc_208m_parents[] = { - CLK_TOP_CB_CKSQ_40M, CLK_TOP_CB_M_D2, CLK_TOP_CB_NET2_D4, - CLK_TOP_CB_APLL2_196M, CLK_TOP_CB_MM_D4, CLK_TOP_NET1_D8_D2, - CLK_TOP_CB_MM_D6 +static const struct mtk_parent emmc_208m_parents[] = { + TOP_PARENT(CLK_TOP_CB_CKSQ_40M), + TOP_PARENT(CLK_TOP_CB_M_D2), + TOP_PARENT(CLK_TOP_CB_NET2_D4), + TOP_PARENT(CLK_TOP_CB_APLL2_196M), + TOP_PARENT(CLK_TOP_CB_MM_D4), + TOP_PARENT(CLK_TOP_NET1_D8_D2), + TOP_PARENT(CLK_TOP_CB_MM_D6), }; -static const int emmc_400m_parents[] = { CLK_TOP_CB_CKSQ_40M, CLK_TOP_CB_NET2_D2, - CLK_TOP_CB_MM_D2, CLK_TOP_CB_NET2_D2 }; +static const struct mtk_parent emmc_400m_parents[] = { + TOP_PARENT(CLK_TOP_CB_CKSQ_40M), + TOP_PARENT(CLK_TOP_CB_NET2_D2), + TOP_PARENT(CLK_TOP_CB_MM_D2), + TOP_PARENT(CLK_TOP_CB_NET2_D2), +}; -static const int csw_f26m_parents[] = { CLK_TOP_CKSQ_40M_D2, CLK_TOP_M_D8_D2 }; +static const struct mtk_parent csw_f26m_parents[] = { + TOP_PARENT(CLK_TOP_CKSQ_40M_D2), + TOP_PARENT(CLK_TOP_M_D8_D2), +}; -static const int dramc_md32_parents[] = { CLK_TOP_CB_CKSQ_40M, CLK_TOP_CB_M_D2, - CLK_TOP_CB_WEDMCU_208M }; +static const struct mtk_parent dramc_md32_parents[] = { + TOP_PARENT(CLK_TOP_CB_CKSQ_40M), + TOP_PARENT(CLK_TOP_CB_M_D2), + TOP_PARENT(CLK_TOP_CB_WEDMCU_208M), +}; -static const int sysaxi_parents[] = { CLK_TOP_CB_CKSQ_40M, CLK_TOP_NET1_D8_D2 }; +static const struct mtk_parent sysaxi_parents[] = { + TOP_PARENT(CLK_TOP_CB_CKSQ_40M), + TOP_PARENT(CLK_TOP_NET1_D8_D2), +}; -static const int sysapb_parents[] = { CLK_TOP_CB_CKSQ_40M, CLK_TOP_M_D3_D2 }; +static const struct mtk_parent sysapb_parents[] = { + TOP_PARENT(CLK_TOP_CB_CKSQ_40M), + TOP_PARENT(CLK_TOP_M_D3_D2), +}; -static const int arm_db_main_parents[] = { CLK_TOP_CB_CKSQ_40M, - CLK_TOP_CB_NET2_D6 }; +static const struct mtk_parent arm_db_main_parents[] = { + TOP_PARENT(CLK_TOP_CB_CKSQ_40M), + TOP_PARENT(CLK_TOP_CB_NET2_D6), +}; -static const int ap2cnn_host_parents[] = { CLK_TOP_CB_CKSQ_40M, - CLK_TOP_NET1_D8_D4 }; +static const struct mtk_parent ap2cnn_host_parents[] = { + TOP_PARENT(CLK_TOP_CB_CKSQ_40M), + TOP_PARENT(CLK_TOP_NET1_D8_D4), +}; -static const int netsys_parents[] = { CLK_TOP_CB_CKSQ_40M, CLK_TOP_CB_MM_D2 }; +static const struct mtk_parent netsys_parents[] = { + TOP_PARENT(CLK_TOP_CB_CKSQ_40M), + TOP_PARENT(CLK_TOP_CB_MM_D2), +}; -static const int netsys_500m_parents[] = { CLK_TOP_CB_CKSQ_40M, - CLK_TOP_CB_NET1_D5 }; +static const struct mtk_parent netsys_500m_parents[] = { + TOP_PARENT(CLK_TOP_CB_CKSQ_40M), + TOP_PARENT(CLK_TOP_CB_NET1_D5), +}; -static const int netsys_mcu_parents[] = { CLK_TOP_CB_CKSQ_40M, CLK_TOP_CB_MM_720M, - CLK_TOP_CB_NET1_D4, CLK_TOP_CB_NET1_D5, - CLK_TOP_CB_M_416M }; +static const struct mtk_parent netsys_mcu_parents[] = { + TOP_PARENT(CLK_TOP_CB_CKSQ_40M), + TOP_PARENT(CLK_TOP_CB_MM_720M), + TOP_PARENT(CLK_TOP_CB_NET1_D4), + TOP_PARENT(CLK_TOP_CB_NET1_D5), + TOP_PARENT(CLK_TOP_CB_M_416M), +}; -static const int netsys_2x_parents[] = { CLK_TOP_CB_CKSQ_40M, - CLK_TOP_CB_NET2_800M, - CLK_TOP_CB_MM_720M }; +static const struct mtk_parent netsys_2x_parents[] = { + TOP_PARENT(CLK_TOP_CB_CKSQ_40M), + TOP_PARENT(CLK_TOP_CB_NET2_800M), + TOP_PARENT(CLK_TOP_CB_MM_720M), +}; -static const int sgm_325m_parents[] = { CLK_TOP_CB_CKSQ_40M, - CLK_TOP_CB_SGM_325M }; +static const struct mtk_parent sgm_325m_parents[] = { + TOP_PARENT(CLK_TOP_CB_CKSQ_40M), + TOP_PARENT(CLK_TOP_CB_SGM_325M), +}; -static const int sgm_reg_parents[] = { CLK_TOP_CB_CKSQ_40M, CLK_TOP_CB_NET2_D4 }; +static const struct mtk_parent sgm_reg_parents[] = { + TOP_PARENT(CLK_TOP_CB_CKSQ_40M), + TOP_PARENT(CLK_TOP_CB_NET2_D4), +}; -static const int eip97b_parents[] = { CLK_TOP_CB_CKSQ_40M, CLK_TOP_CB_NET1_D5, - CLK_TOP_CB_M_416M, CLK_TOP_CB_MM_D2, - CLK_TOP_NET1_D5_D2 }; +static const struct mtk_parent eip97b_parents[] = { + TOP_PARENT(CLK_TOP_CB_CKSQ_40M), + TOP_PARENT(CLK_TOP_CB_NET1_D5), + TOP_PARENT(CLK_TOP_CB_M_416M), + TOP_PARENT(CLK_TOP_CB_MM_D2), + TOP_PARENT(CLK_TOP_NET1_D5_D2), +}; -static const int aud_parents[] = { CLK_TOP_CB_CKSQ_40M, CLK_TOP_CB_APLL2_196M }; +static const struct mtk_parent aud_parents[] = { + TOP_PARENT(CLK_TOP_CB_CKSQ_40M), + TOP_PARENT(CLK_TOP_CB_APLL2_196M), +}; -static const int a1sys_parents[] = { CLK_TOP_CB_CKSQ_40M, CLK_TOP_APLL2_D4 }; +static const struct mtk_parent a1sys_parents[] = { + TOP_PARENT(CLK_TOP_CB_CKSQ_40M), + TOP_PARENT(CLK_TOP_APLL2_D4), +}; -static const int aud_l_parents[] = { CLK_TOP_CB_CKSQ_40M, CLK_TOP_CB_APLL2_196M, - CLK_TOP_M_D8_D2 }; +static const struct mtk_parent aud_l_parents[] = { + TOP_PARENT(CLK_TOP_CB_CKSQ_40M), + TOP_PARENT(CLK_TOP_CB_APLL2_196M), + TOP_PARENT(CLK_TOP_M_D8_D2), +}; -static const int a_tuner_parents[] = { CLK_TOP_CB_CKSQ_40M, CLK_TOP_APLL2_D4, - CLK_TOP_M_D8_D2 }; +static const struct mtk_parent a_tuner_parents[] = { + TOP_PARENT(CLK_TOP_CB_CKSQ_40M), + TOP_PARENT(CLK_TOP_APLL2_D4), + TOP_PARENT(CLK_TOP_M_D8_D2), +}; -static const int u2u3_parents[] = { CLK_TOP_CB_CKSQ_40M, CLK_TOP_M_D8_D2 }; +static const struct mtk_parent u2u3_parents[] = { + TOP_PARENT(CLK_TOP_CB_CKSQ_40M), + TOP_PARENT(CLK_TOP_M_D8_D2), +}; -static const int u2u3_sys_parents[] = { CLK_TOP_CB_CKSQ_40M, CLK_TOP_NET1_D5_D4 }; +static const struct mtk_parent u2u3_sys_parents[] = { + TOP_PARENT(CLK_TOP_CB_CKSQ_40M), + TOP_PARENT(CLK_TOP_NET1_D5_D4), +}; -static const int usb_frmcnt_parents[] = { CLK_TOP_CB_CKSQ_40M, - CLK_TOP_CB_MM_D3_D5 }; +static const struct mtk_parent usb_frmcnt_parents[] = { + TOP_PARENT(CLK_TOP_CB_CKSQ_40M), + TOP_PARENT(CLK_TOP_CB_MM_D3_D5), +}; #define TOP_MUX(_id, _name, _parents, _mux_ofs, _mux_set_ofs, _mux_clr_ofs, \ _shift, _width, _gate, _upd_ofs, _upd) \ @@ -238,9 +335,10 @@ static const int usb_frmcnt_parents[] = { CLK_TOP_CB_CKSQ_40M, .mux_clr_reg = _mux_clr_ofs, .upd_reg = _upd_ofs, \ .upd_shift = _upd, .mux_shift = _shift, \ .mux_mask = BIT(_width) - 1, .gate_reg = _mux_ofs, \ - .gate_shift = _gate, .parent = _parents, \ + .gate_shift = _gate, \ + .parent_flags = _parents, \ .num_parents = ARRAY_SIZE(_parents), \ - .flags = CLK_MUX_SETCLR_UPD, \ + .flags = CLK_MUX_SETCLR_UPD | CLK_PARENT_MIXED, \ } /* TOPCKGEN MUX_GATE */ -- cgit v1.3.1 From 1ed05de4abd5ecdd89469430b86af395f3d5ecc0 Mon Sep 17 00:00:00 2001 From: David Lechner Date: Tue, 17 Mar 2026 18:23:18 -0500 Subject: clk: mediatek: mt7987: convert to struct mtk_parent Convert all parent clock arrays to use struct mtk_parent. This will allow us to simplify core code later by having only one possible data type for mux parent arrays. Reviewed-by: Julien Stephan Link: https://patch.msgid.link/20260317-clk-mtk-unify-mux-parents-v3-5-a4760f5b0a80@baylibre.com Signed-off-by: David Lechner --- drivers/clk/mediatek/clk-mt7987.c | 71 ++++++++++++++++++++------------------- 1 file changed, 36 insertions(+), 35 deletions(-) diff --git a/drivers/clk/mediatek/clk-mt7987.c b/drivers/clk/mediatek/clk-mt7987.c index 641881fcb28..2f3e314b648 100644 --- a/drivers/clk/mediatek/clk-mt7987.c +++ b/drivers/clk/mediatek/clk-mt7987.c @@ -480,63 +480,63 @@ U_BOOT_DRIVER(mtk_clk_topckgen) = { /* INFRASYS MUX PARENTS */ /* CLK_INFRA_MUX_UART0_SEL (infra_mux_uart0_sel) in infracfg */ -static const int infra_mux_uart0_parents[] = { - CLK_TOP_INFRA_F26M_SEL, - CLK_TOP_UART_SEL +static const struct mtk_parent infra_mux_uart0_parents[] = { + TOP_PARENT(CLK_TOP_INFRA_F26M_SEL), + TOP_PARENT(CLK_TOP_UART_SEL), }; /* CLK_INFRA_MUX_UART1_SEL (infra_mux_uart1_sel) in infracfg */ -static const int infra_mux_uart1_parents[] = { - CLK_TOP_INFRA_F26M_SEL, - CLK_TOP_UART_SEL +static const struct mtk_parent infra_mux_uart1_parents[] = { + TOP_PARENT(CLK_TOP_INFRA_F26M_SEL), + TOP_PARENT(CLK_TOP_UART_SEL), }; /* CLK_INFRA_MUX_UART2_SEL (infra_mux_uart2_sel) in infracfg */ -static const int infra_mux_uart2_parents[] = { - CLK_TOP_INFRA_F26M_SEL, - CLK_TOP_UART_SEL +static const struct mtk_parent infra_mux_uart2_parents[] = { + TOP_PARENT(CLK_TOP_INFRA_F26M_SEL), + TOP_PARENT(CLK_TOP_UART_SEL), }; /* CLK_INFRA_MUX_SPI0_SEL (infra_mux_spi0_sel) in infracfg */ -static const int infra_mux_spi0_parents[] = { - CLK_TOP_I2C_SEL, - CLK_TOP_SPI_SEL +static const struct mtk_parent infra_mux_spi0_parents[] = { + TOP_PARENT(CLK_TOP_I2C_SEL), + TOP_PARENT(CLK_TOP_SPI_SEL), }; /* CLK_INFRA_MUX_SPI1_SEL (infra_mux_spi1_sel) in infracfg */ -static const int infra_mux_spi1_parents[] = { - CLK_TOP_I2C_SEL, - CLK_TOP_SPIM_MST_SEL +static const struct mtk_parent infra_mux_spi1_parents[] = { + TOP_PARENT(CLK_TOP_I2C_SEL), + TOP_PARENT(CLK_TOP_SPIM_MST_SEL), }; /* CLK_INFRA_MUX_SPI2_BCK_SEL (infra_mux_spi2_bck_sel) in infracfg */ -static const int infra_mux_spi2_bck_parents[] = { - CLK_TOP_I2C_SEL, - CLK_TOP_SPI_SEL +static const struct mtk_parent infra_mux_spi2_bck_parents[] = { + TOP_PARENT(CLK_TOP_I2C_SEL), + TOP_PARENT(CLK_TOP_SPI_SEL), }; /* CLK_INFRA_PWM_BCK_SEL (infra_pwm_bck_sel) in infracfg */ -static const int infra_pwm_bck_parents[] = { - CLK_TOP_CB_RTC_32P7K, - CLK_TOP_INFRA_F26M_SEL, - CLK_TOP_SYSAXI_SEL, - CLK_TOP_PWM_SEL +static const struct mtk_parent infra_pwm_bck_parents[] = { + TOP_PARENT(CLK_TOP_CB_RTC_32P7K), + TOP_PARENT(CLK_TOP_INFRA_F26M_SEL), + TOP_PARENT(CLK_TOP_SYSAXI_SEL), + TOP_PARENT(CLK_TOP_PWM_SEL), }; /* CLK_INFRA_PCIE_GFMUX_TL_O_P0_SEL (infra_pcie_gfmux_tl_ck_o_p0_sel) in infracfg */ -static const int infra_pcie_gfmux_tl_ck_o_p0_parents[] = { - CLK_TOP_CB_RTC_32P7K, - CLK_TOP_INFRA_F26M_SEL, - CLK_TOP_INFRA_F26M_SEL, - CLK_TOP_PEXTP_TL_SEL +static const struct mtk_parent infra_pcie_gfmux_tl_ck_o_p0_parents[] = { + TOP_PARENT(CLK_TOP_CB_RTC_32P7K), + TOP_PARENT(CLK_TOP_INFRA_F26M_SEL), + TOP_PARENT(CLK_TOP_INFRA_F26M_SEL), + TOP_PARENT(CLK_TOP_PEXTP_TL_SEL), }; /* CLK_INFRA_PCIE_GFMUX_TL_O_P1_SEL (infra_pcie_gfmux_tl_ck_o_p1_sel) in infracfg */ -static const int infra_pcie_gfmux_tl_ck_o_p1_parents[] = { - CLK_TOP_CB_RTC_32P7K, - CLK_TOP_INFRA_F26M_SEL, - CLK_TOP_INFRA_F26M_SEL, - CLK_TOP_PEXTP_TL_P1_SEL +static const struct mtk_parent infra_pcie_gfmux_tl_ck_o_p1_parents[] = { + TOP_PARENT(CLK_TOP_CB_RTC_32P7K), + TOP_PARENT(CLK_TOP_INFRA_F26M_SEL), + TOP_PARENT(CLK_TOP_INFRA_F26M_SEL), + TOP_PARENT(CLK_TOP_PEXTP_TL_P1_SEL), }; #define INFRA_MUX(_id, _name, _parents, _reg, _shift, _width) \ @@ -545,8 +545,9 @@ static const int infra_pcie_gfmux_tl_ck_o_p1_parents[] = { .mux_clr_reg = (_reg) + 0x4, .mux_set_reg = (_reg) + 0x0, \ .mux_shift = (_shift), .mux_mask = BIT(_width) - 1, \ .gate_shift = -1, .upd_shift = -1, \ - .parent = (_parents), .num_parents = ARRAY_SIZE(_parents), \ - .flags = CLK_MUX_SETCLR_UPD | CLK_PARENT_TOPCKGEN, \ + .parent_flags = (_parents), \ + .num_parents = ARRAY_SIZE(_parents), \ + .flags = CLK_MUX_SETCLR_UPD | CLK_PARENT_MIXED, \ } /* INFRA MUX */ -- cgit v1.3.1 From a2d600dba36ed487bd380197d3e197e74305099b Mon Sep 17 00:00:00 2001 From: David Lechner Date: Tue, 17 Mar 2026 18:23:19 -0500 Subject: clk: mediatek: mt7988: convert to struct mtk_parent Convert all parent clock arrays to use struct mtk_parent. This will allow us to simplify core code later by having only one possible data type for mux parent arrays. Reviewed-by: Julien Stephan Link: https://patch.msgid.link/20260317-clk-mtk-unify-mux-parents-v3-6-a4760f5b0a80@baylibre.com Signed-off-by: David Lechner --- drivers/clk/mediatek/clk-mt7988.c | 74 ++++++++++++++++++++++++++------------- 1 file changed, 49 insertions(+), 25 deletions(-) diff --git a/drivers/clk/mediatek/clk-mt7988.c b/drivers/clk/mediatek/clk-mt7988.c index 83f7c559e31..21d194ed807 100644 --- a/drivers/clk/mediatek/clk-mt7988.c +++ b/drivers/clk/mediatek/clk-mt7988.c @@ -444,51 +444,75 @@ static const struct mtk_composite topckgen_mtk_muxes[] = { }; /* INFRASYS MUX PARENTS */ -static const int infra_mux_uart0_parents[] = { CLK_TOP_INFRA_F26M_SEL, - CLK_TOP_UART_SEL }; +static const struct mtk_parent infra_mux_uart0_parents[] = { + TOP_PARENT(CLK_TOP_INFRA_F26M_SEL), + TOP_PARENT(CLK_TOP_UART_SEL), +}; -static const int infra_mux_uart1_parents[] = { CLK_TOP_INFRA_F26M_SEL, - CLK_TOP_UART_SEL }; +static const struct mtk_parent infra_mux_uart1_parents[] = { + TOP_PARENT(CLK_TOP_INFRA_F26M_SEL), + TOP_PARENT(CLK_TOP_UART_SEL), +}; -static const int infra_mux_uart2_parents[] = { CLK_TOP_INFRA_F26M_SEL, - CLK_TOP_UART_SEL }; +static const struct mtk_parent infra_mux_uart2_parents[] = { + TOP_PARENT(CLK_TOP_INFRA_F26M_SEL), + TOP_PARENT(CLK_TOP_UART_SEL), +}; -static const int infra_mux_spi0_parents[] = { CLK_TOP_I2C_SEL, CLK_TOP_SPI_SEL }; +static const struct mtk_parent infra_mux_spi0_parents[] = { + TOP_PARENT(CLK_TOP_I2C_SEL), + TOP_PARENT(CLK_TOP_SPI_SEL), +}; -static const int infra_mux_spi1_parents[] = { CLK_TOP_I2C_SEL, CLK_TOP_SPIM_MST_SEL }; +static const struct mtk_parent infra_mux_spi1_parents[] = { + TOP_PARENT(CLK_TOP_I2C_SEL), + TOP_PARENT(CLK_TOP_SPIM_MST_SEL), +}; -static const int infra_pwm_bck_parents[] = { CLK_TOP_RTC_32P7K, - CLK_TOP_INFRA_F26M_SEL, CLK_TOP_SYSAXI_SEL, - CLK_TOP_PWM_SEL }; +static const struct mtk_parent infra_pwm_bck_parents[] = { + TOP_PARENT(CLK_TOP_RTC_32P7K), + TOP_PARENT(CLK_TOP_INFRA_F26M_SEL), + TOP_PARENT(CLK_TOP_SYSAXI_SEL), + TOP_PARENT(CLK_TOP_PWM_SEL), +}; -static const int infra_pcie_gfmux_tl_ck_o_p0_parents[] = { - CLK_TOP_RTC_32P7K, CLK_TOP_INFRA_F26M_SEL, CLK_TOP_INFRA_F26M_SEL, - CLK_TOP_PEXTP_TL_SEL +static const struct mtk_parent infra_pcie_gfmux_tl_ck_o_p0_parents[] = { + TOP_PARENT(CLK_TOP_RTC_32P7K), + TOP_PARENT(CLK_TOP_INFRA_F26M_SEL), + TOP_PARENT(CLK_TOP_INFRA_F26M_SEL), + TOP_PARENT(CLK_TOP_PEXTP_TL_SEL), }; -static const int infra_pcie_gfmux_tl_ck_o_p1_parents[] = { - CLK_TOP_RTC_32P7K, CLK_TOP_INFRA_F26M_SEL, CLK_TOP_INFRA_F26M_SEL, - CLK_TOP_PEXTP_TL_P1_SEL +static const struct mtk_parent infra_pcie_gfmux_tl_ck_o_p1_parents[] = { + TOP_PARENT(CLK_TOP_RTC_32P7K), + TOP_PARENT(CLK_TOP_INFRA_F26M_SEL), + TOP_PARENT(CLK_TOP_INFRA_F26M_SEL), + TOP_PARENT(CLK_TOP_PEXTP_TL_P1_SEL), }; -static const int infra_pcie_gfmux_tl_ck_o_p2_parents[] = { - CLK_TOP_RTC_32P7K, CLK_TOP_INFRA_F26M_SEL, CLK_TOP_INFRA_F26M_SEL, - CLK_TOP_PEXTP_TL_P2_SEL +static const struct mtk_parent infra_pcie_gfmux_tl_ck_o_p2_parents[] = { + TOP_PARENT(CLK_TOP_RTC_32P7K), + TOP_PARENT(CLK_TOP_INFRA_F26M_SEL), + TOP_PARENT(CLK_TOP_INFRA_F26M_SEL), + TOP_PARENT(CLK_TOP_PEXTP_TL_P2_SEL), }; -static const int infra_pcie_gfmux_tl_ck_o_p3_parents[] = { - CLK_TOP_RTC_32P7K, CLK_TOP_INFRA_F26M_SEL, CLK_TOP_INFRA_F26M_SEL, - CLK_TOP_PEXTP_TL_P3_SEL +static const struct mtk_parent infra_pcie_gfmux_tl_ck_o_p3_parents[] = { + TOP_PARENT(CLK_TOP_RTC_32P7K), + TOP_PARENT(CLK_TOP_INFRA_F26M_SEL), + TOP_PARENT(CLK_TOP_INFRA_F26M_SEL), + TOP_PARENT(CLK_TOP_PEXTP_TL_P3_SEL), }; #define INFRA_MUX(_id, _name, _parents, _reg, _shift, _width) \ { \ .id = _id, .mux_reg = _reg + 0x8, .mux_set_reg = _reg + 0x0, \ .mux_clr_reg = _reg + 0x4, .mux_shift = _shift, \ - .mux_mask = BIT(_width) - 1, .parent = _parents, \ + .mux_mask = BIT(_width) - 1, \ + .parent_flags = _parents, \ .gate_shift = -1, .upd_shift = -1, \ .num_parents = ARRAY_SIZE(_parents), \ - .flags = CLK_MUX_SETCLR_UPD | CLK_PARENT_TOPCKGEN, \ + .flags = CLK_MUX_SETCLR_UPD | CLK_PARENT_MIXED, \ } /* INFRA MUX */ -- cgit v1.3.1 From 326d9c01f81f9b111f9643826d6560bcdffc6ffc Mon Sep 17 00:00:00 2001 From: David Lechner Date: Tue, 17 Mar 2026 18:23:20 -0500 Subject: clk: mediatek: mt8183: convert to struct mtk_parent Convert all parent clock arrays to use struct mtk_parent. This will allow us to simplify core code later by having only one possible data type for mux parent arrays. Reviewed-by: Julien Stephan Link: https://patch.msgid.link/20260317-clk-mtk-unify-mux-parents-v3-7-a4760f5b0a80@baylibre.com Signed-off-by: David Lechner --- drivers/clk/mediatek/clk-mt8183.c | 668 +++++++++++++++++++------------------- 1 file changed, 334 insertions(+), 334 deletions(-) diff --git a/drivers/clk/mediatek/clk-mt8183.c b/drivers/clk/mediatek/clk-mt8183.c index 752cb1c61ab..d98614d8da6 100644 --- a/drivers/clk/mediatek/clk-mt8183.c +++ b/drivers/clk/mediatek/clk-mt8183.c @@ -197,403 +197,403 @@ static const struct mtk_fixed_factor top_fixed_divs[] = { 16, CLK_PARENT_TOPCKGEN), }; -static const int axi_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_SYSPLL_D2_D4, - CLK_TOP_SYSPLL_D7, - CLK_TOP_OSC_D4 -}; - -static const int mm_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_MMPLL_D7, - CLK_TOP_SYSPLL_D3, - CLK_TOP_UNIVPLL_D2_D2, - CLK_TOP_SYSPLL_D2_D2, - CLK_TOP_SYSPLL_D3_D2 -}; - -static const int img_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_MMPLL_D6, - CLK_TOP_UNIVPLL_D3, - CLK_TOP_SYSPLL_D3, - CLK_TOP_UNIVPLL_D2_D2, - CLK_TOP_SYSPLL_D2_D2, - CLK_TOP_UNIVPLL_D3_D2, - CLK_TOP_SYSPLL_D3_D2 -}; - -static const int cam_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_SYSPLL_D2, - CLK_TOP_MMPLL_D6, - CLK_TOP_SYSPLL_D3, - CLK_TOP_MMPLL_D7, - CLK_TOP_UNIVPLL_D3, - CLK_TOP_UNIVPLL_D2_D2, - CLK_TOP_SYSPLL_D2_D2, - CLK_TOP_SYSPLL_D3_D2, - CLK_TOP_UNIVPLL_D3_D2 -}; - -static const int dsp_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_MMPLL_D6, - CLK_TOP_MMPLL_D7, - CLK_TOP_UNIVPLL_D3, - CLK_TOP_SYSPLL_D3, - CLK_TOP_UNIVPLL_D2_D2, - CLK_TOP_SYSPLL_D2_D2, - CLK_TOP_UNIVPLL_D3_D2, - CLK_TOP_SYSPLL_D3_D2 -}; - -static const int dsp1_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_MMPLL_D6, - CLK_TOP_MMPLL_D7, - CLK_TOP_UNIVPLL_D3, - CLK_TOP_SYSPLL_D3, - CLK_TOP_UNIVPLL_D2_D2, - CLK_TOP_SYSPLL_D2_D2, - CLK_TOP_UNIVPLL_D3_D2, - CLK_TOP_SYSPLL_D3_D2 -}; - -static const int dsp2_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_MMPLL_D6, - CLK_TOP_MMPLL_D7, - CLK_TOP_UNIVPLL_D3, - CLK_TOP_SYSPLL_D3, - CLK_TOP_UNIVPLL_D2_D2, - CLK_TOP_SYSPLL_D2_D2, - CLK_TOP_UNIVPLL_D3_D2, - CLK_TOP_SYSPLL_D3_D2 -}; - -static const int ipu_if_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_MMPLL_D6, - CLK_TOP_MMPLL_D7, - CLK_TOP_UNIVPLL_D3, - CLK_TOP_SYSPLL_D3, - CLK_TOP_UNIVPLL_D2_D2, - CLK_TOP_SYSPLL_D2_D2, - CLK_TOP_UNIVPLL_D3_D2, - CLK_TOP_SYSPLL_D3_D2 -}; - -static const int mfg_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_MFGPLL_CK, - CLK_TOP_UNIVPLL_D3, - CLK_TOP_SYSPLL_D3 -}; - -static const int f52m_mfg_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_UNIVPLL_D3_D2, - CLK_TOP_UNIVPLL_D3_D4, - CLK_TOP_UNIVPLL_D3_D8 -}; - -static const int camtg_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_UNIVP_192M_D8, - CLK_TOP_UNIVPLL_D3_D8, - CLK_TOP_UNIVP_192M_D4, - CLK_TOP_UNIVPLL_D3_D16, - CLK_TOP_F26M_CK_D2, - CLK_TOP_UNIVP_192M_D16, - CLK_TOP_UNIVP_192M_D32 -}; - -static const int camtg2_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_UNIVP_192M_D8, - CLK_TOP_UNIVPLL_D3_D8, - CLK_TOP_UNIVP_192M_D4, - CLK_TOP_UNIVPLL_D3_D16, - CLK_TOP_F26M_CK_D2, - CLK_TOP_UNIVP_192M_D16, - CLK_TOP_UNIVP_192M_D32 -}; - -static const int camtg3_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_UNIVP_192M_D8, - CLK_TOP_UNIVPLL_D3_D8, - CLK_TOP_UNIVP_192M_D4, - CLK_TOP_UNIVPLL_D3_D16, - CLK_TOP_F26M_CK_D2, - CLK_TOP_UNIVP_192M_D16, - CLK_TOP_UNIVP_192M_D32 -}; - -static const int camtg4_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_UNIVP_192M_D8, - CLK_TOP_UNIVPLL_D3_D8, - CLK_TOP_UNIVP_192M_D4, - CLK_TOP_UNIVPLL_D3_D16, - CLK_TOP_F26M_CK_D2, - CLK_TOP_UNIVP_192M_D16, - CLK_TOP_UNIVP_192M_D32 -}; - -static const int uart_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_UNIVPLL_D3_D8 -}; - -static const int spi_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_SYSPLL_D5_D2, - CLK_TOP_SYSPLL_D3_D4, - CLK_TOP_MSDCPLL_D4 -}; - -static const int msdc50_hclk_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_SYSPLL_D2_D2, - CLK_TOP_SYSPLL_D3_D2 +static const struct mtk_parent axi_parents[] = { + TOP_PARENT(CLK_TOP_CLK26M), + TOP_PARENT(CLK_TOP_SYSPLL_D2_D4), + TOP_PARENT(CLK_TOP_SYSPLL_D7), + TOP_PARENT(CLK_TOP_OSC_D4), +}; + +static const struct mtk_parent mm_parents[] = { + TOP_PARENT(CLK_TOP_CLK26M), + TOP_PARENT(CLK_TOP_MMPLL_D7), + TOP_PARENT(CLK_TOP_SYSPLL_D3), + TOP_PARENT(CLK_TOP_UNIVPLL_D2_D2), + TOP_PARENT(CLK_TOP_SYSPLL_D2_D2), + TOP_PARENT(CLK_TOP_SYSPLL_D3_D2), +}; + +static const struct mtk_parent img_parents[] = { + TOP_PARENT(CLK_TOP_CLK26M), + TOP_PARENT(CLK_TOP_MMPLL_D6), + TOP_PARENT(CLK_TOP_UNIVPLL_D3), + TOP_PARENT(CLK_TOP_SYSPLL_D3), + TOP_PARENT(CLK_TOP_UNIVPLL_D2_D2), + TOP_PARENT(CLK_TOP_SYSPLL_D2_D2), + TOP_PARENT(CLK_TOP_UNIVPLL_D3_D2), + TOP_PARENT(CLK_TOP_SYSPLL_D3_D2), +}; + +static const struct mtk_parent cam_parents[] = { + TOP_PARENT(CLK_TOP_CLK26M), + TOP_PARENT(CLK_TOP_SYSPLL_D2), + TOP_PARENT(CLK_TOP_MMPLL_D6), + TOP_PARENT(CLK_TOP_SYSPLL_D3), + TOP_PARENT(CLK_TOP_MMPLL_D7), + TOP_PARENT(CLK_TOP_UNIVPLL_D3), + TOP_PARENT(CLK_TOP_UNIVPLL_D2_D2), + TOP_PARENT(CLK_TOP_SYSPLL_D2_D2), + TOP_PARENT(CLK_TOP_SYSPLL_D3_D2), + TOP_PARENT(CLK_TOP_UNIVPLL_D3_D2), +}; + +static const struct mtk_parent dsp_parents[] = { + TOP_PARENT(CLK_TOP_CLK26M), + TOP_PARENT(CLK_TOP_MMPLL_D6), + TOP_PARENT(CLK_TOP_MMPLL_D7), + TOP_PARENT(CLK_TOP_UNIVPLL_D3), + TOP_PARENT(CLK_TOP_SYSPLL_D3), + TOP_PARENT(CLK_TOP_UNIVPLL_D2_D2), + TOP_PARENT(CLK_TOP_SYSPLL_D2_D2), + TOP_PARENT(CLK_TOP_UNIVPLL_D3_D2), + TOP_PARENT(CLK_TOP_SYSPLL_D3_D2), +}; + +static const struct mtk_parent dsp1_parents[] = { + TOP_PARENT(CLK_TOP_CLK26M), + TOP_PARENT(CLK_TOP_MMPLL_D6), + TOP_PARENT(CLK_TOP_MMPLL_D7), + TOP_PARENT(CLK_TOP_UNIVPLL_D3), + TOP_PARENT(CLK_TOP_SYSPLL_D3), + TOP_PARENT(CLK_TOP_UNIVPLL_D2_D2), + TOP_PARENT(CLK_TOP_SYSPLL_D2_D2), + TOP_PARENT(CLK_TOP_UNIVPLL_D3_D2), + TOP_PARENT(CLK_TOP_SYSPLL_D3_D2), +}; + +static const struct mtk_parent dsp2_parents[] = { + TOP_PARENT(CLK_TOP_CLK26M), + TOP_PARENT(CLK_TOP_MMPLL_D6), + TOP_PARENT(CLK_TOP_MMPLL_D7), + TOP_PARENT(CLK_TOP_UNIVPLL_D3), + TOP_PARENT(CLK_TOP_SYSPLL_D3), + TOP_PARENT(CLK_TOP_UNIVPLL_D2_D2), + TOP_PARENT(CLK_TOP_SYSPLL_D2_D2), + TOP_PARENT(CLK_TOP_UNIVPLL_D3_D2), + TOP_PARENT(CLK_TOP_SYSPLL_D3_D2), +}; + +static const struct mtk_parent ipu_if_parents[] = { + TOP_PARENT(CLK_TOP_CLK26M), + TOP_PARENT(CLK_TOP_MMPLL_D6), + TOP_PARENT(CLK_TOP_MMPLL_D7), + TOP_PARENT(CLK_TOP_UNIVPLL_D3), + TOP_PARENT(CLK_TOP_SYSPLL_D3), + TOP_PARENT(CLK_TOP_UNIVPLL_D2_D2), + TOP_PARENT(CLK_TOP_SYSPLL_D2_D2), + TOP_PARENT(CLK_TOP_UNIVPLL_D3_D2), + TOP_PARENT(CLK_TOP_SYSPLL_D3_D2), +}; + +static const struct mtk_parent mfg_parents[] = { + TOP_PARENT(CLK_TOP_CLK26M), + TOP_PARENT(CLK_TOP_MFGPLL_CK), + TOP_PARENT(CLK_TOP_UNIVPLL_D3), + TOP_PARENT(CLK_TOP_SYSPLL_D3), +}; + +static const struct mtk_parent f52m_mfg_parents[] = { + TOP_PARENT(CLK_TOP_CLK26M), + TOP_PARENT(CLK_TOP_UNIVPLL_D3_D2), + TOP_PARENT(CLK_TOP_UNIVPLL_D3_D4), + TOP_PARENT(CLK_TOP_UNIVPLL_D3_D8), +}; + +static const struct mtk_parent camtg_parents[] = { + TOP_PARENT(CLK_TOP_CLK26M), + TOP_PARENT(CLK_TOP_UNIVP_192M_D8), + TOP_PARENT(CLK_TOP_UNIVPLL_D3_D8), + TOP_PARENT(CLK_TOP_UNIVP_192M_D4), + TOP_PARENT(CLK_TOP_UNIVPLL_D3_D16), + TOP_PARENT(CLK_TOP_F26M_CK_D2), + TOP_PARENT(CLK_TOP_UNIVP_192M_D16), + TOP_PARENT(CLK_TOP_UNIVP_192M_D32), +}; + +static const struct mtk_parent camtg2_parents[] = { + TOP_PARENT(CLK_TOP_CLK26M), + TOP_PARENT(CLK_TOP_UNIVP_192M_D8), + TOP_PARENT(CLK_TOP_UNIVPLL_D3_D8), + TOP_PARENT(CLK_TOP_UNIVP_192M_D4), + TOP_PARENT(CLK_TOP_UNIVPLL_D3_D16), + TOP_PARENT(CLK_TOP_F26M_CK_D2), + TOP_PARENT(CLK_TOP_UNIVP_192M_D16), + TOP_PARENT(CLK_TOP_UNIVP_192M_D32), +}; + +static const struct mtk_parent camtg3_parents[] = { + TOP_PARENT(CLK_TOP_CLK26M), + TOP_PARENT(CLK_TOP_UNIVP_192M_D8), + TOP_PARENT(CLK_TOP_UNIVPLL_D3_D8), + TOP_PARENT(CLK_TOP_UNIVP_192M_D4), + TOP_PARENT(CLK_TOP_UNIVPLL_D3_D16), + TOP_PARENT(CLK_TOP_F26M_CK_D2), + TOP_PARENT(CLK_TOP_UNIVP_192M_D16), + TOP_PARENT(CLK_TOP_UNIVP_192M_D32), +}; + +static const struct mtk_parent camtg4_parents[] = { + TOP_PARENT(CLK_TOP_CLK26M), + TOP_PARENT(CLK_TOP_UNIVP_192M_D8), + TOP_PARENT(CLK_TOP_UNIVPLL_D3_D8), + TOP_PARENT(CLK_TOP_UNIVP_192M_D4), + TOP_PARENT(CLK_TOP_UNIVPLL_D3_D16), + TOP_PARENT(CLK_TOP_F26M_CK_D2), + TOP_PARENT(CLK_TOP_UNIVP_192M_D16), + TOP_PARENT(CLK_TOP_UNIVP_192M_D32), +}; + +static const struct mtk_parent uart_parents[] = { + TOP_PARENT(CLK_TOP_CLK26M), + TOP_PARENT(CLK_TOP_UNIVPLL_D3_D8), +}; + +static const struct mtk_parent spi_parents[] = { + TOP_PARENT(CLK_TOP_CLK26M), + TOP_PARENT(CLK_TOP_SYSPLL_D5_D2), + TOP_PARENT(CLK_TOP_SYSPLL_D3_D4), + TOP_PARENT(CLK_TOP_MSDCPLL_D4), +}; + +static const struct mtk_parent msdc50_hclk_parents[] = { + TOP_PARENT(CLK_TOP_CLK26M), + TOP_PARENT(CLK_TOP_SYSPLL_D2_D2), + TOP_PARENT(CLK_TOP_SYSPLL_D3_D2), }; - -static const int msdc50_0_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_MSDCPLL_CK, - CLK_TOP_MSDCPLL_D2, - CLK_TOP_UNIVPLL_D2_D4, - CLK_TOP_SYSPLL_D3_D2, - CLK_TOP_UNIVPLL_D2_D2 + +static const struct mtk_parent msdc50_0_parents[] = { + TOP_PARENT(CLK_TOP_CLK26M), + TOP_PARENT(CLK_TOP_MSDCPLL_CK), + TOP_PARENT(CLK_TOP_MSDCPLL_D2), + TOP_PARENT(CLK_TOP_UNIVPLL_D2_D4), + TOP_PARENT(CLK_TOP_SYSPLL_D3_D2), + TOP_PARENT(CLK_TOP_UNIVPLL_D2_D2), }; -static const int msdc30_1_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_UNIVPLL_D3_D2, - CLK_TOP_SYSPLL_D3_D2, - CLK_TOP_SYSPLL_D7, - CLK_TOP_MSDCPLL_D2 +static const struct mtk_parent msdc30_1_parents[] = { + TOP_PARENT(CLK_TOP_CLK26M), + TOP_PARENT(CLK_TOP_UNIVPLL_D3_D2), + TOP_PARENT(CLK_TOP_SYSPLL_D3_D2), + TOP_PARENT(CLK_TOP_SYSPLL_D7), + TOP_PARENT(CLK_TOP_MSDCPLL_D2), }; -static const int msdc30_2_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_UNIVPLL_D3_D2, - CLK_TOP_SYSPLL_D3_D2, - CLK_TOP_SYSPLL_D7, - CLK_TOP_MSDCPLL_D2 +static const struct mtk_parent msdc30_2_parents[] = { + TOP_PARENT(CLK_TOP_CLK26M), + TOP_PARENT(CLK_TOP_UNIVPLL_D3_D2), + TOP_PARENT(CLK_TOP_SYSPLL_D3_D2), + TOP_PARENT(CLK_TOP_SYSPLL_D7), + TOP_PARENT(CLK_TOP_MSDCPLL_D2), }; -static const int audio_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_SYSPLL_D5_D4, - CLK_TOP_SYSPLL_D7_D4, - CLK_TOP_SYSPLL_D2_D16 +static const struct mtk_parent audio_parents[] = { + TOP_PARENT(CLK_TOP_CLK26M), + TOP_PARENT(CLK_TOP_SYSPLL_D5_D4), + TOP_PARENT(CLK_TOP_SYSPLL_D7_D4), + TOP_PARENT(CLK_TOP_SYSPLL_D2_D16), }; -static const int aud_intbus_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_SYSPLL_D2_D4, - CLK_TOP_SYSPLL_D7_D2 +static const struct mtk_parent aud_intbus_parents[] = { + TOP_PARENT(CLK_TOP_CLK26M), + TOP_PARENT(CLK_TOP_SYSPLL_D2_D4), + TOP_PARENT(CLK_TOP_SYSPLL_D7_D2), }; -static const int pmicspi_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_SYSPLL_D2_D8, - CLK_TOP_OSC_D8 +static const struct mtk_parent pmicspi_parents[] = { + TOP_PARENT(CLK_TOP_CLK26M), + TOP_PARENT(CLK_TOP_SYSPLL_D2_D8), + TOP_PARENT(CLK_TOP_OSC_D8), }; -static const int fpwrap_ulposc_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_OSC_D16, - CLK_TOP_OSC_D4, - CLK_TOP_OSC_D8 +static const struct mtk_parent fpwrap_ulposc_parents[] = { + TOP_PARENT(CLK_TOP_CLK26M), + TOP_PARENT(CLK_TOP_OSC_D16), + TOP_PARENT(CLK_TOP_OSC_D4), + TOP_PARENT(CLK_TOP_OSC_D8), }; -static const int atb_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_SYSPLL_D2_D2, - CLK_TOP_SYSPLL_D5 +static const struct mtk_parent atb_parents[] = { + TOP_PARENT(CLK_TOP_CLK26M), + TOP_PARENT(CLK_TOP_SYSPLL_D2_D2), + TOP_PARENT(CLK_TOP_SYSPLL_D5), }; -static const int sspm_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_UNIVPLL_D2_D4, - CLK_TOP_SYSPLL_D2_D2, - CLK_TOP_UNIVPLL_D2_D2, - CLK_TOP_SYSPLL_D3 +static const struct mtk_parent sspm_parents[] = { + TOP_PARENT(CLK_TOP_CLK26M), + TOP_PARENT(CLK_TOP_UNIVPLL_D2_D4), + TOP_PARENT(CLK_TOP_SYSPLL_D2_D2), + TOP_PARENT(CLK_TOP_UNIVPLL_D2_D2), + TOP_PARENT(CLK_TOP_SYSPLL_D3), }; -static const int dpi0_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_TVDPLL_D2, - CLK_TOP_TVDPLL_D4, - CLK_TOP_TVDPLL_D8, - CLK_TOP_TVDPLL_D16, - CLK_TOP_UNIVPLL_D5_D2, - CLK_TOP_UNIVPLL_D3_D4, - CLK_TOP_SYSPLL_D3_D4, - CLK_TOP_UNIVPLL_D3_D8 +static const struct mtk_parent dpi0_parents[] = { + TOP_PARENT(CLK_TOP_CLK26M), + TOP_PARENT(CLK_TOP_TVDPLL_D2), + TOP_PARENT(CLK_TOP_TVDPLL_D4), + TOP_PARENT(CLK_TOP_TVDPLL_D8), + TOP_PARENT(CLK_TOP_TVDPLL_D16), + TOP_PARENT(CLK_TOP_UNIVPLL_D5_D2), + TOP_PARENT(CLK_TOP_UNIVPLL_D3_D4), + TOP_PARENT(CLK_TOP_SYSPLL_D3_D4), + TOP_PARENT(CLK_TOP_UNIVPLL_D3_D8), }; -static const int scam_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_SYSPLL_D5_D2 +static const struct mtk_parent scam_parents[] = { + TOP_PARENT(CLK_TOP_CLK26M), + TOP_PARENT(CLK_TOP_SYSPLL_D5_D2), }; -static const int disppwm_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_UNIVPLL_D3_D4, - CLK_TOP_OSC_D2, - CLK_TOP_OSC_D4, - CLK_TOP_OSC_D16 +static const struct mtk_parent disppwm_parents[] = { + TOP_PARENT(CLK_TOP_CLK26M), + TOP_PARENT(CLK_TOP_UNIVPLL_D3_D4), + TOP_PARENT(CLK_TOP_OSC_D2), + TOP_PARENT(CLK_TOP_OSC_D4), + TOP_PARENT(CLK_TOP_OSC_D16), }; -static const int usb_top_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_UNIVPLL_D5_D4, - CLK_TOP_UNIVPLL_D3_D4, - CLK_TOP_UNIVPLL_D5_D2 +static const struct mtk_parent usb_top_parents[] = { + TOP_PARENT(CLK_TOP_CLK26M), + TOP_PARENT(CLK_TOP_UNIVPLL_D5_D4), + TOP_PARENT(CLK_TOP_UNIVPLL_D3_D4), + TOP_PARENT(CLK_TOP_UNIVPLL_D5_D2), }; -static const int ssusb_top_xhci_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_UNIVPLL_D5_D4, - CLK_TOP_UNIVPLL_D3_D4, - CLK_TOP_UNIVPLL_D5_D2 +static const struct mtk_parent ssusb_top_xhci_parents[] = { + TOP_PARENT(CLK_TOP_CLK26M), + TOP_PARENT(CLK_TOP_UNIVPLL_D5_D4), + TOP_PARENT(CLK_TOP_UNIVPLL_D3_D4), + TOP_PARENT(CLK_TOP_UNIVPLL_D5_D2), }; -static const int spm_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_SYSPLL_D2_D8 +static const struct mtk_parent spm_parents[] = { + TOP_PARENT(CLK_TOP_CLK26M), + TOP_PARENT(CLK_TOP_SYSPLL_D2_D8), }; -static const int i2c_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_SYSPLL_D2_D8, - CLK_TOP_UNIVPLL_D5_D2 +static const struct mtk_parent i2c_parents[] = { + TOP_PARENT(CLK_TOP_CLK26M), + TOP_PARENT(CLK_TOP_SYSPLL_D2_D8), + TOP_PARENT(CLK_TOP_UNIVPLL_D5_D2), }; -static const int scp_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_UNIVPLL_D2_D8, - CLK_TOP_SYSPLL_D5, - CLK_TOP_SYSPLL_D2_D2, - CLK_TOP_UNIVPLL_D2_D2, - CLK_TOP_SYSPLL_D3, - CLK_TOP_UNIVPLL_D3 +static const struct mtk_parent scp_parents[] = { + TOP_PARENT(CLK_TOP_CLK26M), + TOP_PARENT(CLK_TOP_UNIVPLL_D2_D8), + TOP_PARENT(CLK_TOP_SYSPLL_D5), + TOP_PARENT(CLK_TOP_SYSPLL_D2_D2), + TOP_PARENT(CLK_TOP_UNIVPLL_D2_D2), + TOP_PARENT(CLK_TOP_SYSPLL_D3), + TOP_PARENT(CLK_TOP_UNIVPLL_D3), }; -static const int seninf_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_UNIVPLL_D2_D2, - CLK_TOP_UNIVPLL_D3_D2, - CLK_TOP_UNIVPLL_D2_D4 +static const struct mtk_parent seninf_parents[] = { + TOP_PARENT(CLK_TOP_CLK26M), + TOP_PARENT(CLK_TOP_UNIVPLL_D2_D2), + TOP_PARENT(CLK_TOP_UNIVPLL_D3_D2), + TOP_PARENT(CLK_TOP_UNIVPLL_D2_D4), }; -static const int dxcc_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_SYSPLL_D2_D2, - CLK_TOP_SYSPLL_D2_D4, - CLK_TOP_SYSPLL_D2_D8 +static const struct mtk_parent dxcc_parents[] = { + TOP_PARENT(CLK_TOP_CLK26M), + TOP_PARENT(CLK_TOP_SYSPLL_D2_D2), + TOP_PARENT(CLK_TOP_SYSPLL_D2_D4), + TOP_PARENT(CLK_TOP_SYSPLL_D2_D8), }; -static const int aud_engen1_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_APLL1_D2, - CLK_TOP_APLL1_D4, - CLK_TOP_APLL1_D8 +static const struct mtk_parent aud_engen1_parents[] = { + TOP_PARENT(CLK_TOP_CLK26M), + TOP_PARENT(CLK_TOP_APLL1_D2), + TOP_PARENT(CLK_TOP_APLL1_D4), + TOP_PARENT(CLK_TOP_APLL1_D8), }; -static const int aud_engen2_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_APLL2_D2, - CLK_TOP_APLL2_D4, - CLK_TOP_APLL2_D8 +static const struct mtk_parent aud_engen2_parents[] = { + TOP_PARENT(CLK_TOP_CLK26M), + TOP_PARENT(CLK_TOP_APLL2_D2), + TOP_PARENT(CLK_TOP_APLL2_D4), + TOP_PARENT(CLK_TOP_APLL2_D8), }; -static const int faes_ufsfde_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_SYSPLL_D2, - CLK_TOP_SYSPLL_D2_D2, - CLK_TOP_SYSPLL_D3, - CLK_TOP_SYSPLL_D2_D4, - CLK_TOP_UNIVPLL_D3 +static const struct mtk_parent faes_ufsfde_parents[] = { + TOP_PARENT(CLK_TOP_CLK26M), + TOP_PARENT(CLK_TOP_SYSPLL_D2), + TOP_PARENT(CLK_TOP_SYSPLL_D2_D2), + TOP_PARENT(CLK_TOP_SYSPLL_D3), + TOP_PARENT(CLK_TOP_SYSPLL_D2_D4), + TOP_PARENT(CLK_TOP_UNIVPLL_D3), }; -static const int fufs_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_SYSPLL_D2_D4, - CLK_TOP_SYSPLL_D2_D8, - CLK_TOP_SYSPLL_D2_D16 +static const struct mtk_parent fufs_parents[] = { + TOP_PARENT(CLK_TOP_CLK26M), + TOP_PARENT(CLK_TOP_SYSPLL_D2_D4), + TOP_PARENT(CLK_TOP_SYSPLL_D2_D8), + TOP_PARENT(CLK_TOP_SYSPLL_D2_D16), }; -static const int aud_1_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_APLL1_CK +static const struct mtk_parent aud_1_parents[] = { + TOP_PARENT(CLK_TOP_CLK26M), + TOP_PARENT(CLK_TOP_APLL1_CK), }; -static const int aud_2_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_APLL2_CK +static const struct mtk_parent aud_2_parents[] = { + TOP_PARENT(CLK_TOP_CLK26M), + TOP_PARENT(CLK_TOP_APLL2_CK), }; static const struct mtk_composite top_muxes[] = { /* CLK_CFG_0 */ - MUX(CLK_TOP_MUX_AXI, axi_parents, 0x40, 0, 2), - MUX(CLK_TOP_MUX_MM, mm_parents, 0x40, 8, 3), - MUX(CLK_TOP_MUX_IMG, img_parents, 0x40, 16, 3), - MUX(CLK_TOP_MUX_CAM, cam_parents, 0x40, 24, 4), + MUX_MIXED(CLK_TOP_MUX_AXI, axi_parents, 0x40, 0, 2), + MUX_MIXED(CLK_TOP_MUX_MM, mm_parents, 0x40, 8, 3), + MUX_MIXED(CLK_TOP_MUX_IMG, img_parents, 0x40, 16, 3), + MUX_MIXED(CLK_TOP_MUX_CAM, cam_parents, 0x40, 24, 4), /* CLK_CFG_1 */ - MUX(CLK_TOP_MUX_DSP, dsp_parents, 0x50, 0, 4), - MUX(CLK_TOP_MUX_DSP1, dsp1_parents, 0x50, 8, 4), - MUX(CLK_TOP_MUX_DSP2, dsp2_parents, 0x50, 16, 4), - MUX(CLK_TOP_MUX_IPU_IF, ipu_if_parents, 0x50, 24, 4), + MUX_MIXED(CLK_TOP_MUX_DSP, dsp_parents, 0x50, 0, 4), + MUX_MIXED(CLK_TOP_MUX_DSP1, dsp1_parents, 0x50, 8, 4), + MUX_MIXED(CLK_TOP_MUX_DSP2, dsp2_parents, 0x50, 16, 4), + MUX_MIXED(CLK_TOP_MUX_IPU_IF, ipu_if_parents, 0x50, 24, 4), /* CLK_CFG_2 */ - MUX(CLK_TOP_MUX_MFG, mfg_parents, 0x60, 0, 2), - MUX(CLK_TOP_MUX_F52M_MFG, f52m_mfg_parents, 0x60, 8, 2), - MUX(CLK_TOP_MUX_CAMTG, camtg_parents, 0x60, 16, 3), - MUX(CLK_TOP_MUX_CAMTG2, camtg2_parents, 0x60, 24, 3), + MUX_MIXED(CLK_TOP_MUX_MFG, mfg_parents, 0x60, 0, 2), + MUX_MIXED(CLK_TOP_MUX_F52M_MFG, f52m_mfg_parents, 0x60, 8, 2), + MUX_MIXED(CLK_TOP_MUX_CAMTG, camtg_parents, 0x60, 16, 3), + MUX_MIXED(CLK_TOP_MUX_CAMTG2, camtg2_parents, 0x60, 24, 3), /* CLK_CFG_3 */ - MUX(CLK_TOP_MUX_CAMTG3, camtg3_parents, 0x70, 0, 3), - MUX(CLK_TOP_MUX_CAMTG4, camtg4_parents, 0x70, 8, 3), - MUX(CLK_TOP_MUX_UART, uart_parents, 0x70, 16, 1), - MUX(CLK_TOP_MUX_SPI, spi_parents, 0x70, 24, 2), + MUX_MIXED(CLK_TOP_MUX_CAMTG3, camtg3_parents, 0x70, 0, 3), + MUX_MIXED(CLK_TOP_MUX_CAMTG4, camtg4_parents, 0x70, 8, 3), + MUX_MIXED(CLK_TOP_MUX_UART, uart_parents, 0x70, 16, 1), + MUX_MIXED(CLK_TOP_MUX_SPI, spi_parents, 0x70, 24, 2), /* CLK_CFG_4 */ - MUX(CLK_TOP_MUX_MSDC50_0_HCLK, msdc50_hclk_parents, 0x80, 0, 2), - MUX(CLK_TOP_MUX_MSDC50_0, msdc50_0_parents, 0x80, 8, 3), - MUX(CLK_TOP_MUX_MSDC30_1, msdc30_1_parents, 0x80, 16, 3), - MUX(CLK_TOP_MUX_MSDC30_2, msdc30_2_parents, 0x80, 24, 3), + MUX_MIXED(CLK_TOP_MUX_MSDC50_0_HCLK, msdc50_hclk_parents, 0x80, 0, 2), + MUX_MIXED(CLK_TOP_MUX_MSDC50_0, msdc50_0_parents, 0x80, 8, 3), + MUX_MIXED(CLK_TOP_MUX_MSDC30_1, msdc30_1_parents, 0x80, 16, 3), + MUX_MIXED(CLK_TOP_MUX_MSDC30_2, msdc30_2_parents, 0x80, 24, 3), /* CLK_CFG_5 */ - MUX(CLK_TOP_MUX_AUDIO, audio_parents, 0x90, 0, 2), - MUX(CLK_TOP_MUX_AUD_INTBUS, aud_intbus_parents, 0x90, 8, 2), - MUX(CLK_TOP_MUX_PMICSPI, pmicspi_parents, 0x90, 16, 2), - MUX(CLK_TOP_MUX_FPWRAP_ULPOSC, fpwrap_ulposc_parents, 0x90, 24, 2), + MUX_MIXED(CLK_TOP_MUX_AUDIO, audio_parents, 0x90, 0, 2), + MUX_MIXED(CLK_TOP_MUX_AUD_INTBUS, aud_intbus_parents, 0x90, 8, 2), + MUX_MIXED(CLK_TOP_MUX_PMICSPI, pmicspi_parents, 0x90, 16, 2), + MUX_MIXED(CLK_TOP_MUX_FPWRAP_ULPOSC, fpwrap_ulposc_parents, 0x90, 24, 2), /* CLK_CFG_6 */ - MUX(CLK_TOP_MUX_ATB, atb_parents, 0xa0, 0, 2), - MUX(CLK_TOP_MUX_SSPM, sspm_parents, 0xa0, 8, 3), - MUX(CLK_TOP_MUX_DPI0, dpi0_parents, 0xa0, 16, 4), - MUX(CLK_TOP_MUX_SCAM, scam_parents, 0xa0, 24, 1), + MUX_MIXED(CLK_TOP_MUX_ATB, atb_parents, 0xa0, 0, 2), + MUX_MIXED(CLK_TOP_MUX_SSPM, sspm_parents, 0xa0, 8, 3), + MUX_MIXED(CLK_TOP_MUX_DPI0, dpi0_parents, 0xa0, 16, 4), + MUX_MIXED(CLK_TOP_MUX_SCAM, scam_parents, 0xa0, 24, 1), /* CLK_CFG_7 */ - MUX(CLK_TOP_MUX_DISP_PWM, disppwm_parents, 0xb0, 0, 3), - MUX(CLK_TOP_MUX_USB_TOP, usb_top_parents, 0xb0, 8, 2), - MUX(CLK_TOP_MUX_SSUSB_TOP_XHCI, ssusb_top_xhci_parents, 0xb0, 16, 2), - MUX(CLK_TOP_MUX_SPM, spm_parents, 0xb0, 24, 1), + MUX_MIXED(CLK_TOP_MUX_DISP_PWM, disppwm_parents, 0xb0, 0, 3), + MUX_MIXED(CLK_TOP_MUX_USB_TOP, usb_top_parents, 0xb0, 8, 2), + MUX_MIXED(CLK_TOP_MUX_SSUSB_TOP_XHCI, ssusb_top_xhci_parents, 0xb0, 16, 2), + MUX_MIXED(CLK_TOP_MUX_SPM, spm_parents, 0xb0, 24, 1), /* CLK_CFG_8 */ - MUX(CLK_TOP_MUX_I2C, i2c_parents, 0xc0, 0, 2), - MUX(CLK_TOP_MUX_SCP, scp_parents, 0xc0, 8, 3), - MUX(CLK_TOP_MUX_SENINF, seninf_parents, 0xc0, 16, 2), - MUX(CLK_TOP_MUX_DXCC, dxcc_parents, 0xc0, 24, 2), + MUX_MIXED(CLK_TOP_MUX_I2C, i2c_parents, 0xc0, 0, 2), + MUX_MIXED(CLK_TOP_MUX_SCP, scp_parents, 0xc0, 8, 3), + MUX_MIXED(CLK_TOP_MUX_SENINF, seninf_parents, 0xc0, 16, 2), + MUX_MIXED(CLK_TOP_MUX_DXCC, dxcc_parents, 0xc0, 24, 2), /* CLK_CFG_9 */ - MUX(CLK_TOP_MUX_AUD_ENG1, aud_engen1_parents, 0xd0, 0, 2), - MUX(CLK_TOP_MUX_AUD_ENG2, aud_engen2_parents, 0xd0, 8, 2), - MUX(CLK_TOP_MUX_FAES_UFSFDE, faes_ufsfde_parents, 0xd0, 16, 3), - MUX(CLK_TOP_MUX_FUFS, fufs_parents, 0xd0, 24, 2), + MUX_MIXED(CLK_TOP_MUX_AUD_ENG1, aud_engen1_parents, 0xd0, 0, 2), + MUX_MIXED(CLK_TOP_MUX_AUD_ENG2, aud_engen2_parents, 0xd0, 8, 2), + MUX_MIXED(CLK_TOP_MUX_FAES_UFSFDE, faes_ufsfde_parents, 0xd0, 16, 3), + MUX_MIXED(CLK_TOP_MUX_FUFS, fufs_parents, 0xd0, 24, 2), /* CLK_CFG_10 */ - MUX(CLK_TOP_MUX_AUD_1, aud_1_parents, 0xe0, 0, 1), - MUX(CLK_TOP_MUX_AUD_2, aud_2_parents, 0xe0, 8, 1), + MUX_MIXED(CLK_TOP_MUX_AUD_1, aud_1_parents, 0xe0, 0, 1), + MUX_MIXED(CLK_TOP_MUX_AUD_2, aud_2_parents, 0xe0, 8, 1), }; static const struct mtk_clk_tree mt8183_clk_tree = { -- cgit v1.3.1 From d632daabdce6712239e423c4d71f49789dcb858d Mon Sep 17 00:00:00 2001 From: David Lechner Date: Tue, 17 Mar 2026 18:23:21 -0500 Subject: clk: mediatek: mt8188: convert to struct mtk_parent Convert all parent clock arrays to use struct mtk_parent. This will allow us to simplify core code later by having only one possible data type for mux parent arrays. Reviewed-by: Macpaul Lin Reviewed-by: Julien Stephan Link: https://patch.msgid.link/20260317-clk-mtk-unify-mux-parents-v3-8-a4760f5b0a80@baylibre.com Signed-off-by: David Lechner --- drivers/clk/mediatek/clk-mt8188.c | 1704 ++++++++++++++++++------------------- 1 file changed, 852 insertions(+), 852 deletions(-) diff --git a/drivers/clk/mediatek/clk-mt8188.c b/drivers/clk/mediatek/clk-mt8188.c index 3d20d2d93fc..1db5350763e 100644 --- a/drivers/clk/mediatek/clk-mt8188.c +++ b/drivers/clk/mediatek/clk-mt8188.c @@ -190,375 +190,375 @@ static const struct mtk_fixed_factor top_fixed_divs[] = { FACTOR1(CLK_TOP_ULPOSC1_D16, CLK_TOP_ULPOSC1, 1, 16), }; -static const int axi_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_MAINPLL_D4_D4, - CLK_TOP_MAINPLL_D7_D2, - CLK_TOP_MAINPLL_D4_D2, - CLK_TOP_MAINPLL_D5_D2, - CLK_TOP_MAINPLL_D6_D2, - CLK_TOP_ULPOSC1_D4 -}; - -static const int spm_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_ULPOSC1_D10, - CLK_TOP_MAINPLL_D7_D4, - CLK_TOP_CLK32K -}; - -static const int scp_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_UNIVPLL_D4, - CLK_TOP_MAINPLL_D6, - CLK_TOP_UNIVPLL_D6, - CLK_TOP_UNIVPLL_D4_D2, - CLK_TOP_MAINPLL_D4_D2, - CLK_TOP_UNIVPLL_D3, - CLK_TOP_MAINPLL_D3 -}; - -static const int bus_aximem_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_MAINPLL_D7_D2, - CLK_TOP_MAINPLL_D4_D2, - CLK_TOP_MAINPLL_D5_D2, - CLK_TOP_MAINPLL_D6 -}; - -static const int vpp_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_UNIVPLL_D6_D2, - CLK_TOP_MAINPLL_D5_D2, - CLK_TOP_MMPLL_D6_D2, - CLK_TOP_UNIVPLL_D5_D2, - CLK_TOP_UNIVPLL_D4_D2, - CLK_TOP_MMPLL_D4_D2, - CLK_TOP_MMPLL_D7, - CLK_TOP_UNIVPLL_D6, - CLK_TOP_MAINPLL_D4, - CLK_TOP_MMPLL_D5, - CLK_TOP_TVDPLL1, - CLK_TOP_TVDPLL2, - CLK_TOP_UNIVPLL_D4, - CLK_TOP_MMPLL_D4 -}; - -static const int ethdr_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_UNIVPLL_D6_D2, - CLK_TOP_MAINPLL_D5_D2, - CLK_TOP_MMPLL_D6_D2, - CLK_TOP_UNIVPLL_D5_D2, - CLK_TOP_UNIVPLL_D4_D2, - CLK_TOP_MMPLL_D4_D2, - CLK_TOP_MMPLL_D7, - CLK_TOP_UNIVPLL_D6, - CLK_TOP_MAINPLL_D4, - CLK_TOP_MMPLL_D5_D4, - CLK_TOP_TVDPLL1, - CLK_TOP_TVDPLL2, - CLK_TOP_UNIVPLL_D4, - CLK_TOP_MMPLL_D4 -}; - -static const int ipe_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_IMGPLL, - CLK_TOP_MAINPLL_D4, - CLK_TOP_MMPLL_D6, - CLK_TOP_UNIVPLL_D6, - CLK_TOP_MAINPLL_D6, - CLK_TOP_MMPLL_D4_D2, - CLK_TOP_UNIVPLL_D4_D2, - CLK_TOP_MAINPLL_D4_D2, - CLK_TOP_MMPLL_D6_D2, - CLK_TOP_UNIVPLL_D5_D2, - CLK_TOP_MAINPLL_D7 -}; - -static const int cam_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_TVDPLL1, - CLK_TOP_MAINPLL_D4, - CLK_TOP_MMPLL_D4, - CLK_TOP_UNIVPLL_D4, - CLK_TOP_UNIVPLL_D5, - CLK_TOP_UNIVPLL_D6, - CLK_TOP_MMPLL_D7, - CLK_TOP_UNIVPLL_D4_D2, - CLK_TOP_MAINPLL_D4_D2, - CLK_TOP_IMGPLL -}; - -static const int ccu_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_UNIVPLL_D6, - CLK_TOP_MAINPLL_D4_D2, - CLK_TOP_MAINPLL_D4, - CLK_TOP_UNIVPLL_D5, - CLK_TOP_MAINPLL_D6, - CLK_TOP_MMPLL_D6, - CLK_TOP_MMPLL_D7, - CLK_TOP_UNIVPLL_D4_D2, - CLK_TOP_UNIVPLL_D7 -}; - -static const int ccu_ahb_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_UNIVPLL_D6, - CLK_TOP_MAINPLL_D4_D2, - CLK_TOP_MAINPLL_D4, - CLK_TOP_UNIVPLL_D5, - CLK_TOP_MAINPLL_D6, - CLK_TOP_MMPLL_D6, - CLK_TOP_MMPLL_D7, - CLK_TOP_UNIVPLL_D4_D2, - CLK_TOP_UNIVPLL_D7 -}; - -static const int img_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_IMGPLL, - CLK_TOP_UNIVPLL_D4, - CLK_TOP_MAINPLL_D4, - CLK_TOP_UNIVPLL_D5, - CLK_TOP_MMPLL_D6, - CLK_TOP_MMPLL_D7, - CLK_TOP_UNIVPLL_D6, - CLK_TOP_MAINPLL_D6, - CLK_TOP_MMPLL_D4_D2, - CLK_TOP_UNIVPLL_D4_D2, - CLK_TOP_MAINPLL_D4_D2, - CLK_TOP_UNIVPLL_D5_D2 -}; - -static const int camtm_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_UNIVPLL_D4_D4, - CLK_TOP_UNIVPLL_D6_D2, - CLK_TOP_UNIVPLL_D6_D4 -}; - -static const int dsp_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_UNIVPLL_D6_D2, - CLK_TOP_UNIVPLL_D4_D2, - CLK_TOP_UNIVPLL_D5, - CLK_TOP_UNIVPLL_D4, - CLK_TOP_MMPLL_D4, - CLK_TOP_MAINPLL_D3, - CLK_TOP_UNIVPLL_D3 -}; - -static const int dsp1_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_UNIVPLL_D6_D2, - CLK_TOP_MAINPLL_D4_D2, - CLK_TOP_UNIVPLL_D5, - CLK_TOP_MMPLL_D5, - CLK_TOP_UNIVPLL_D4, - CLK_TOP_MAINPLL_D3, - CLK_TOP_UNIVPLL_D3 -}; - -static const int dsp2_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_UNIVPLL_D6_D2, - CLK_TOP_MAINPLL_D4_D2, - CLK_TOP_UNIVPLL_D5, - CLK_TOP_MMPLL_D5, - CLK_TOP_UNIVPLL_D4, - CLK_TOP_MAINPLL_D3, - CLK_TOP_UNIVPLL_D3 -}; - -static const int dsp3_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_UNIVPLL_D6_D2, - CLK_TOP_MAINPLL_D4_D2, - CLK_TOP_UNIVPLL_D5, - CLK_TOP_MMPLL_D5, - CLK_TOP_UNIVPLL_D4, - CLK_TOP_MAINPLL_D3, - CLK_TOP_UNIVPLL_D3 -}; - -static const int dsp4_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_UNIVPLL_D6_D2, - CLK_TOP_UNIVPLL_D4_D2, - CLK_TOP_MAINPLL_D4, - CLK_TOP_UNIVPLL_D4, - CLK_TOP_MMPLL_D4, - CLK_TOP_MAINPLL_D3, - CLK_TOP_UNIVPLL_D3 -}; - -static const int dsp5_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_UNIVPLL_D6_D2, - CLK_TOP_UNIVPLL_D4_D2, - CLK_TOP_MAINPLL_D4, - CLK_TOP_UNIVPLL_D4, - CLK_TOP_MMPLL_D4, - CLK_TOP_MAINPLL_D3, - CLK_TOP_UNIVPLL_D3 -}; - -static const int dsp6_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_UNIVPLL_D6_D2, - CLK_TOP_UNIVPLL_D4_D2, - CLK_TOP_MAINPLL_D4, - CLK_TOP_UNIVPLL_D4, - CLK_TOP_MMPLL_D4, - CLK_TOP_MAINPLL_D3, - CLK_TOP_UNIVPLL_D3 -}; - -static const int dsp7_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_UNIVPLL_D6_D2, - CLK_TOP_UNIVPLL_D4_D2, - CLK_TOP_UNIVPLL_D5, - CLK_TOP_UNIVPLL_D4, - CLK_TOP_MMPLL_D4, - CLK_TOP_MAINPLL_D3, - CLK_TOP_UNIVPLL_D3 -}; - -static const int mfg_core_tmp_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_MAINPLL_D5_D2, - CLK_TOP_UNIVPLL_D6, - CLK_TOP_UNIVPLL_D7 -}; - -static const int camtg_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_UNIVPLL_192M_D8, - CLK_TOP_UNIVPLL_D6_D8, - CLK_TOP_UNIVPLL_192M_D4, - CLK_TOP_UNIVPLL_192M_D10, - CLK_TOP_CLK13M, - CLK_TOP_UNIVPLL_192M_D16, - CLK_TOP_UNIVPLL_192M_D32 -}; - -static const int camtg2_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_UNIVPLL_192M_D8, - CLK_TOP_UNIVPLL_D6_D8, - CLK_TOP_UNIVPLL_192M_D4, - CLK_TOP_UNIVPLL_192M_D10, - CLK_TOP_CLK13M, - CLK_TOP_UNIVPLL_192M_D16, - CLK_TOP_UNIVPLL_192M_D32 -}; - -static const int camtg3_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_UNIVPLL_192M_D8, - CLK_TOP_UNIVPLL_D6_D8, - CLK_TOP_UNIVPLL_192M_D4, - CLK_TOP_UNIVPLL_192M_D10, - CLK_TOP_CLK13M, - CLK_TOP_UNIVPLL_192M_D16, - CLK_TOP_UNIVPLL_192M_D32 -}; - -static const int uart_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_UNIVPLL_D6_D8 -}; - -static const int spi_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_MAINPLL_D5_D4, - CLK_TOP_MAINPLL_D6_D4, - CLK_TOP_UNIVPLL_D6_D4, - CLK_TOP_UNIVPLL_D6_D2, - CLK_TOP_MAINPLL_D6_D2, - CLK_TOP_MAINPLL_D4_D4, - CLK_TOP_UNIVPLL_D5_D4 -}; - -static const int msdc5hclk_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_MAINPLL_D4_D2, - CLK_TOP_MAINPLL_D6_D2 -}; - -static const int msdc50_0_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_MSDCPLL, - CLK_TOP_MSDCPLL_D2, - CLK_TOP_UNIVPLL_D4_D4, - CLK_TOP_MAINPLL_D6_D2, - CLK_TOP_UNIVPLL_D4_D2 -}; - -static const int msdc30_1_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_UNIVPLL_D6_D2, - CLK_TOP_MAINPLL_D6_D2, - CLK_TOP_MAINPLL_D7_D2, - CLK_TOP_MSDCPLL_D2 -}; - -static const int msdc30_2_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_UNIVPLL_D6_D2, - CLK_TOP_MAINPLL_D6_D2, - CLK_TOP_MAINPLL_D7_D2, - CLK_TOP_MSDCPLL_D2 -}; +static const struct mtk_parent axi_parents[] = { + TOP_PARENT(CLK_TOP_CLK26M), + TOP_PARENT(CLK_TOP_MAINPLL_D4_D4), + TOP_PARENT(CLK_TOP_MAINPLL_D7_D2), + TOP_PARENT(CLK_TOP_MAINPLL_D4_D2), + TOP_PARENT(CLK_TOP_MAINPLL_D5_D2), + TOP_PARENT(CLK_TOP_MAINPLL_D6_D2), + TOP_PARENT(CLK_TOP_ULPOSC1_D4), +}; + +static const struct mtk_parent spm_parents[] = { + TOP_PARENT(CLK_TOP_CLK26M), + TOP_PARENT(CLK_TOP_ULPOSC1_D10), + TOP_PARENT(CLK_TOP_MAINPLL_D7_D4), + TOP_PARENT(CLK_TOP_CLK32K), +}; + +static const struct mtk_parent scp_parents[] = { + TOP_PARENT(CLK_TOP_CLK26M), + TOP_PARENT(CLK_TOP_UNIVPLL_D4), + TOP_PARENT(CLK_TOP_MAINPLL_D6), + TOP_PARENT(CLK_TOP_UNIVPLL_D6), + TOP_PARENT(CLK_TOP_UNIVPLL_D4_D2), + TOP_PARENT(CLK_TOP_MAINPLL_D4_D2), + TOP_PARENT(CLK_TOP_UNIVPLL_D3), + TOP_PARENT(CLK_TOP_MAINPLL_D3), +}; + +static const struct mtk_parent bus_aximem_parents[] = { + TOP_PARENT(CLK_TOP_CLK26M), + TOP_PARENT(CLK_TOP_MAINPLL_D7_D2), + TOP_PARENT(CLK_TOP_MAINPLL_D4_D2), + TOP_PARENT(CLK_TOP_MAINPLL_D5_D2), + TOP_PARENT(CLK_TOP_MAINPLL_D6), +}; + +static const struct mtk_parent vpp_parents[] = { + TOP_PARENT(CLK_TOP_CLK26M), + TOP_PARENT(CLK_TOP_UNIVPLL_D6_D2), + TOP_PARENT(CLK_TOP_MAINPLL_D5_D2), + TOP_PARENT(CLK_TOP_MMPLL_D6_D2), + TOP_PARENT(CLK_TOP_UNIVPLL_D5_D2), + TOP_PARENT(CLK_TOP_UNIVPLL_D4_D2), + TOP_PARENT(CLK_TOP_MMPLL_D4_D2), + TOP_PARENT(CLK_TOP_MMPLL_D7), + TOP_PARENT(CLK_TOP_UNIVPLL_D6), + TOP_PARENT(CLK_TOP_MAINPLL_D4), + TOP_PARENT(CLK_TOP_MMPLL_D5), + TOP_PARENT(CLK_TOP_TVDPLL1), + TOP_PARENT(CLK_TOP_TVDPLL2), + TOP_PARENT(CLK_TOP_UNIVPLL_D4), + TOP_PARENT(CLK_TOP_MMPLL_D4), +}; + +static const struct mtk_parent ethdr_parents[] = { + TOP_PARENT(CLK_TOP_CLK26M), + TOP_PARENT(CLK_TOP_UNIVPLL_D6_D2), + TOP_PARENT(CLK_TOP_MAINPLL_D5_D2), + TOP_PARENT(CLK_TOP_MMPLL_D6_D2), + TOP_PARENT(CLK_TOP_UNIVPLL_D5_D2), + TOP_PARENT(CLK_TOP_UNIVPLL_D4_D2), + TOP_PARENT(CLK_TOP_MMPLL_D4_D2), + TOP_PARENT(CLK_TOP_MMPLL_D7), + TOP_PARENT(CLK_TOP_UNIVPLL_D6), + TOP_PARENT(CLK_TOP_MAINPLL_D4), + TOP_PARENT(CLK_TOP_MMPLL_D5_D4), + TOP_PARENT(CLK_TOP_TVDPLL1), + TOP_PARENT(CLK_TOP_TVDPLL2), + TOP_PARENT(CLK_TOP_UNIVPLL_D4), + TOP_PARENT(CLK_TOP_MMPLL_D4), +}; + +static const struct mtk_parent ipe_parents[] = { + TOP_PARENT(CLK_TOP_CLK26M), + TOP_PARENT(CLK_TOP_IMGPLL), + TOP_PARENT(CLK_TOP_MAINPLL_D4), + TOP_PARENT(CLK_TOP_MMPLL_D6), + TOP_PARENT(CLK_TOP_UNIVPLL_D6), + TOP_PARENT(CLK_TOP_MAINPLL_D6), + TOP_PARENT(CLK_TOP_MMPLL_D4_D2), + TOP_PARENT(CLK_TOP_UNIVPLL_D4_D2), + TOP_PARENT(CLK_TOP_MAINPLL_D4_D2), + TOP_PARENT(CLK_TOP_MMPLL_D6_D2), + TOP_PARENT(CLK_TOP_UNIVPLL_D5_D2), + TOP_PARENT(CLK_TOP_MAINPLL_D7), +}; + +static const struct mtk_parent cam_parents[] = { + TOP_PARENT(CLK_TOP_CLK26M), + TOP_PARENT(CLK_TOP_TVDPLL1), + TOP_PARENT(CLK_TOP_MAINPLL_D4), + TOP_PARENT(CLK_TOP_MMPLL_D4), + TOP_PARENT(CLK_TOP_UNIVPLL_D4), + TOP_PARENT(CLK_TOP_UNIVPLL_D5), + TOP_PARENT(CLK_TOP_UNIVPLL_D6), + TOP_PARENT(CLK_TOP_MMPLL_D7), + TOP_PARENT(CLK_TOP_UNIVPLL_D4_D2), + TOP_PARENT(CLK_TOP_MAINPLL_D4_D2), + TOP_PARENT(CLK_TOP_IMGPLL), +}; + +static const struct mtk_parent ccu_parents[] = { + TOP_PARENT(CLK_TOP_CLK26M), + TOP_PARENT(CLK_TOP_UNIVPLL_D6), + TOP_PARENT(CLK_TOP_MAINPLL_D4_D2), + TOP_PARENT(CLK_TOP_MAINPLL_D4), + TOP_PARENT(CLK_TOP_UNIVPLL_D5), + TOP_PARENT(CLK_TOP_MAINPLL_D6), + TOP_PARENT(CLK_TOP_MMPLL_D6), + TOP_PARENT(CLK_TOP_MMPLL_D7), + TOP_PARENT(CLK_TOP_UNIVPLL_D4_D2), + TOP_PARENT(CLK_TOP_UNIVPLL_D7), +}; + +static const struct mtk_parent ccu_ahb_parents[] = { + TOP_PARENT(CLK_TOP_CLK26M), + TOP_PARENT(CLK_TOP_UNIVPLL_D6), + TOP_PARENT(CLK_TOP_MAINPLL_D4_D2), + TOP_PARENT(CLK_TOP_MAINPLL_D4), + TOP_PARENT(CLK_TOP_UNIVPLL_D5), + TOP_PARENT(CLK_TOP_MAINPLL_D6), + TOP_PARENT(CLK_TOP_MMPLL_D6), + TOP_PARENT(CLK_TOP_MMPLL_D7), + TOP_PARENT(CLK_TOP_UNIVPLL_D4_D2), + TOP_PARENT(CLK_TOP_UNIVPLL_D7), +}; + +static const struct mtk_parent img_parents[] = { + TOP_PARENT(CLK_TOP_CLK26M), + TOP_PARENT(CLK_TOP_IMGPLL), + TOP_PARENT(CLK_TOP_UNIVPLL_D4), + TOP_PARENT(CLK_TOP_MAINPLL_D4), + TOP_PARENT(CLK_TOP_UNIVPLL_D5), + TOP_PARENT(CLK_TOP_MMPLL_D6), + TOP_PARENT(CLK_TOP_MMPLL_D7), + TOP_PARENT(CLK_TOP_UNIVPLL_D6), + TOP_PARENT(CLK_TOP_MAINPLL_D6), + TOP_PARENT(CLK_TOP_MMPLL_D4_D2), + TOP_PARENT(CLK_TOP_UNIVPLL_D4_D2), + TOP_PARENT(CLK_TOP_MAINPLL_D4_D2), + TOP_PARENT(CLK_TOP_UNIVPLL_D5_D2), +}; + +static const struct mtk_parent camtm_parents[] = { + TOP_PARENT(CLK_TOP_CLK26M), + TOP_PARENT(CLK_TOP_UNIVPLL_D4_D4), + TOP_PARENT(CLK_TOP_UNIVPLL_D6_D2), + TOP_PARENT(CLK_TOP_UNIVPLL_D6_D4), +}; + +static const struct mtk_parent dsp_parents[] = { + TOP_PARENT(CLK_TOP_CLK26M), + TOP_PARENT(CLK_TOP_UNIVPLL_D6_D2), + TOP_PARENT(CLK_TOP_UNIVPLL_D4_D2), + TOP_PARENT(CLK_TOP_UNIVPLL_D5), + TOP_PARENT(CLK_TOP_UNIVPLL_D4), + TOP_PARENT(CLK_TOP_MMPLL_D4), + TOP_PARENT(CLK_TOP_MAINPLL_D3), + TOP_PARENT(CLK_TOP_UNIVPLL_D3), +}; + +static const struct mtk_parent dsp1_parents[] = { + TOP_PARENT(CLK_TOP_CLK26M), + TOP_PARENT(CLK_TOP_UNIVPLL_D6_D2), + TOP_PARENT(CLK_TOP_MAINPLL_D4_D2), + TOP_PARENT(CLK_TOP_UNIVPLL_D5), + TOP_PARENT(CLK_TOP_MMPLL_D5), + TOP_PARENT(CLK_TOP_UNIVPLL_D4), + TOP_PARENT(CLK_TOP_MAINPLL_D3), + TOP_PARENT(CLK_TOP_UNIVPLL_D3), +}; + +static const struct mtk_parent dsp2_parents[] = { + TOP_PARENT(CLK_TOP_CLK26M), + TOP_PARENT(CLK_TOP_UNIVPLL_D6_D2), + TOP_PARENT(CLK_TOP_MAINPLL_D4_D2), + TOP_PARENT(CLK_TOP_UNIVPLL_D5), + TOP_PARENT(CLK_TOP_MMPLL_D5), + TOP_PARENT(CLK_TOP_UNIVPLL_D4), + TOP_PARENT(CLK_TOP_MAINPLL_D3), + TOP_PARENT(CLK_TOP_UNIVPLL_D3), +}; + +static const struct mtk_parent dsp3_parents[] = { + TOP_PARENT(CLK_TOP_CLK26M), + TOP_PARENT(CLK_TOP_UNIVPLL_D6_D2), + TOP_PARENT(CLK_TOP_MAINPLL_D4_D2), + TOP_PARENT(CLK_TOP_UNIVPLL_D5), + TOP_PARENT(CLK_TOP_MMPLL_D5), + TOP_PARENT(CLK_TOP_UNIVPLL_D4), + TOP_PARENT(CLK_TOP_MAINPLL_D3), + TOP_PARENT(CLK_TOP_UNIVPLL_D3), +}; + +static const struct mtk_parent dsp4_parents[] = { + TOP_PARENT(CLK_TOP_CLK26M), + TOP_PARENT(CLK_TOP_UNIVPLL_D6_D2), + TOP_PARENT(CLK_TOP_UNIVPLL_D4_D2), + TOP_PARENT(CLK_TOP_MAINPLL_D4), + TOP_PARENT(CLK_TOP_UNIVPLL_D4), + TOP_PARENT(CLK_TOP_MMPLL_D4), + TOP_PARENT(CLK_TOP_MAINPLL_D3), + TOP_PARENT(CLK_TOP_UNIVPLL_D3), +}; + +static const struct mtk_parent dsp5_parents[] = { + TOP_PARENT(CLK_TOP_CLK26M), + TOP_PARENT(CLK_TOP_UNIVPLL_D6_D2), + TOP_PARENT(CLK_TOP_UNIVPLL_D4_D2), + TOP_PARENT(CLK_TOP_MAINPLL_D4), + TOP_PARENT(CLK_TOP_UNIVPLL_D4), + TOP_PARENT(CLK_TOP_MMPLL_D4), + TOP_PARENT(CLK_TOP_MAINPLL_D3), + TOP_PARENT(CLK_TOP_UNIVPLL_D3), +}; + +static const struct mtk_parent dsp6_parents[] = { + TOP_PARENT(CLK_TOP_CLK26M), + TOP_PARENT(CLK_TOP_UNIVPLL_D6_D2), + TOP_PARENT(CLK_TOP_UNIVPLL_D4_D2), + TOP_PARENT(CLK_TOP_MAINPLL_D4), + TOP_PARENT(CLK_TOP_UNIVPLL_D4), + TOP_PARENT(CLK_TOP_MMPLL_D4), + TOP_PARENT(CLK_TOP_MAINPLL_D3), + TOP_PARENT(CLK_TOP_UNIVPLL_D3), +}; + +static const struct mtk_parent dsp7_parents[] = { + TOP_PARENT(CLK_TOP_CLK26M), + TOP_PARENT(CLK_TOP_UNIVPLL_D6_D2), + TOP_PARENT(CLK_TOP_UNIVPLL_D4_D2), + TOP_PARENT(CLK_TOP_UNIVPLL_D5), + TOP_PARENT(CLK_TOP_UNIVPLL_D4), + TOP_PARENT(CLK_TOP_MMPLL_D4), + TOP_PARENT(CLK_TOP_MAINPLL_D3), + TOP_PARENT(CLK_TOP_UNIVPLL_D3), +}; + +static const struct mtk_parent mfg_core_tmp_parents[] = { + TOP_PARENT(CLK_TOP_CLK26M), + TOP_PARENT(CLK_TOP_MAINPLL_D5_D2), + TOP_PARENT(CLK_TOP_UNIVPLL_D6), + TOP_PARENT(CLK_TOP_UNIVPLL_D7), +}; + +static const struct mtk_parent camtg_parents[] = { + TOP_PARENT(CLK_TOP_CLK26M), + TOP_PARENT(CLK_TOP_UNIVPLL_192M_D8), + TOP_PARENT(CLK_TOP_UNIVPLL_D6_D8), + TOP_PARENT(CLK_TOP_UNIVPLL_192M_D4), + TOP_PARENT(CLK_TOP_UNIVPLL_192M_D10), + TOP_PARENT(CLK_TOP_CLK13M), + TOP_PARENT(CLK_TOP_UNIVPLL_192M_D16), + TOP_PARENT(CLK_TOP_UNIVPLL_192M_D32), +}; + +static const struct mtk_parent camtg2_parents[] = { + TOP_PARENT(CLK_TOP_CLK26M), + TOP_PARENT(CLK_TOP_UNIVPLL_192M_D8), + TOP_PARENT(CLK_TOP_UNIVPLL_D6_D8), + TOP_PARENT(CLK_TOP_UNIVPLL_192M_D4), + TOP_PARENT(CLK_TOP_UNIVPLL_192M_D10), + TOP_PARENT(CLK_TOP_CLK13M), + TOP_PARENT(CLK_TOP_UNIVPLL_192M_D16), + TOP_PARENT(CLK_TOP_UNIVPLL_192M_D32), +}; + +static const struct mtk_parent camtg3_parents[] = { + TOP_PARENT(CLK_TOP_CLK26M), + TOP_PARENT(CLK_TOP_UNIVPLL_192M_D8), + TOP_PARENT(CLK_TOP_UNIVPLL_D6_D8), + TOP_PARENT(CLK_TOP_UNIVPLL_192M_D4), + TOP_PARENT(CLK_TOP_UNIVPLL_192M_D10), + TOP_PARENT(CLK_TOP_CLK13M), + TOP_PARENT(CLK_TOP_UNIVPLL_192M_D16), + TOP_PARENT(CLK_TOP_UNIVPLL_192M_D32), +}; + +static const struct mtk_parent uart_parents[] = { + TOP_PARENT(CLK_TOP_CLK26M), + TOP_PARENT(CLK_TOP_UNIVPLL_D6_D8), +}; + +static const struct mtk_parent spi_parents[] = { + TOP_PARENT(CLK_TOP_CLK26M), + TOP_PARENT(CLK_TOP_MAINPLL_D5_D4), + TOP_PARENT(CLK_TOP_MAINPLL_D6_D4), + TOP_PARENT(CLK_TOP_UNIVPLL_D6_D4), + TOP_PARENT(CLK_TOP_UNIVPLL_D6_D2), + TOP_PARENT(CLK_TOP_MAINPLL_D6_D2), + TOP_PARENT(CLK_TOP_MAINPLL_D4_D4), + TOP_PARENT(CLK_TOP_UNIVPLL_D5_D4), +}; + +static const struct mtk_parent msdc5hclk_parents[] = { + TOP_PARENT(CLK_TOP_CLK26M), + TOP_PARENT(CLK_TOP_MAINPLL_D4_D2), + TOP_PARENT(CLK_TOP_MAINPLL_D6_D2), +}; + +static const struct mtk_parent msdc50_0_parents[] = { + TOP_PARENT(CLK_TOP_CLK26M), + TOP_PARENT(CLK_TOP_MSDCPLL), + TOP_PARENT(CLK_TOP_MSDCPLL_D2), + TOP_PARENT(CLK_TOP_UNIVPLL_D4_D4), + TOP_PARENT(CLK_TOP_MAINPLL_D6_D2), + TOP_PARENT(CLK_TOP_UNIVPLL_D4_D2), +}; + +static const struct mtk_parent msdc30_1_parents[] = { + TOP_PARENT(CLK_TOP_CLK26M), + TOP_PARENT(CLK_TOP_UNIVPLL_D6_D2), + TOP_PARENT(CLK_TOP_MAINPLL_D6_D2), + TOP_PARENT(CLK_TOP_MAINPLL_D7_D2), + TOP_PARENT(CLK_TOP_MSDCPLL_D2), +}; + +static const struct mtk_parent msdc30_2_parents[] = { + TOP_PARENT(CLK_TOP_CLK26M), + TOP_PARENT(CLK_TOP_UNIVPLL_D6_D2), + TOP_PARENT(CLK_TOP_MAINPLL_D6_D2), + TOP_PARENT(CLK_TOP_MAINPLL_D7_D2), + TOP_PARENT(CLK_TOP_MSDCPLL_D2), +}; -static const int intdir_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_UNIVPLL_D6, - CLK_TOP_MAINPLL_D4, - CLK_TOP_UNIVPLL_D4 -}; - -static const int aud_intbus_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_MAINPLL_D4_D4, - CLK_TOP_MAINPLL_D7_D4 +static const struct mtk_parent intdir_parents[] = { + TOP_PARENT(CLK_TOP_CLK26M), + TOP_PARENT(CLK_TOP_UNIVPLL_D6), + TOP_PARENT(CLK_TOP_MAINPLL_D4), + TOP_PARENT(CLK_TOP_UNIVPLL_D4), +}; + +static const struct mtk_parent aud_intbus_parents[] = { + TOP_PARENT(CLK_TOP_CLK26M), + TOP_PARENT(CLK_TOP_MAINPLL_D4_D4), + TOP_PARENT(CLK_TOP_MAINPLL_D7_D4), }; -static const int audio_h_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_UNIVPLL_D7, - CLK_TOP_APLL1, - CLK_TOP_APLL2 +static const struct mtk_parent audio_h_parents[] = { + TOP_PARENT(CLK_TOP_CLK26M), + TOP_PARENT(CLK_TOP_UNIVPLL_D7), + TOP_PARENT(CLK_TOP_APLL1), + TOP_PARENT(CLK_TOP_APLL2), }; -static const int pwrap_ulposc_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_ULPOSC1_D10, - CLK_TOP_ULPOSC1_D7, - CLK_TOP_ULPOSC1_D8, - CLK_TOP_ULPOSC1_D16, - CLK_TOP_MAINPLL_D4_D8, - CLK_TOP_UNIVPLL_D5_D8, - CLK_TOP_TVDPLL1_D16 +static const struct mtk_parent pwrap_ulposc_parents[] = { + TOP_PARENT(CLK_TOP_CLK26M), + TOP_PARENT(CLK_TOP_ULPOSC1_D10), + TOP_PARENT(CLK_TOP_ULPOSC1_D7), + TOP_PARENT(CLK_TOP_ULPOSC1_D8), + TOP_PARENT(CLK_TOP_ULPOSC1_D16), + TOP_PARENT(CLK_TOP_MAINPLL_D4_D8), + TOP_PARENT(CLK_TOP_UNIVPLL_D5_D8), + TOP_PARENT(CLK_TOP_TVDPLL1_D16), }; -static const int atb_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_MAINPLL_D4_D2, - CLK_TOP_MAINPLL_D5_D2 +static const struct mtk_parent atb_parents[] = { + TOP_PARENT(CLK_TOP_CLK26M), + TOP_PARENT(CLK_TOP_MAINPLL_D4_D2), + TOP_PARENT(CLK_TOP_MAINPLL_D5_D2), }; -static const int sspm_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_MAINPLL_D7_D2, - CLK_TOP_MAINPLL_D6_D2, - CLK_TOP_MAINPLL_D5_D2, - CLK_TOP_MAINPLL_D9, - CLK_TOP_MAINPLL_D4_D2 +static const struct mtk_parent sspm_parents[] = { + TOP_PARENT(CLK_TOP_CLK26M), + TOP_PARENT(CLK_TOP_MAINPLL_D7_D2), + TOP_PARENT(CLK_TOP_MAINPLL_D6_D2), + TOP_PARENT(CLK_TOP_MAINPLL_D5_D2), + TOP_PARENT(CLK_TOP_MAINPLL_D9), + TOP_PARENT(CLK_TOP_MAINPLL_D4_D2), }; /* @@ -566,580 +566,580 @@ static const int sspm_parents[] = { * TVDPLL1 on eDP and TVDPLL2 on DP to avoid changing the "other" PLL rate * in dual output case, which would lead to corruption of functionality loss. */ -static const int dp_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_TVDPLL2_D2, - CLK_TOP_TVDPLL2_D4, - CLK_TOP_TVDPLL2_D8, - CLK_TOP_TVDPLL2_D16 +static const struct mtk_parent dp_parents[] = { + TOP_PARENT(CLK_TOP_CLK26M), + TOP_PARENT(CLK_TOP_TVDPLL2_D2), + TOP_PARENT(CLK_TOP_TVDPLL2_D4), + TOP_PARENT(CLK_TOP_TVDPLL2_D8), + TOP_PARENT(CLK_TOP_TVDPLL2_D16), }; - -static const int edp_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_TVDPLL1_D2, - CLK_TOP_TVDPLL1_D4, - CLK_TOP_TVDPLL1_D8, - CLK_TOP_TVDPLL1_D16 + +static const struct mtk_parent edp_parents[] = { + TOP_PARENT(CLK_TOP_CLK26M), + TOP_PARENT(CLK_TOP_TVDPLL1_D2), + TOP_PARENT(CLK_TOP_TVDPLL1_D4), + TOP_PARENT(CLK_TOP_TVDPLL1_D8), + TOP_PARENT(CLK_TOP_TVDPLL1_D16), }; - -static const int dpi_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_TVDPLL1_D2, - CLK_TOP_TVDPLL2_D2, - CLK_TOP_TVDPLL1_D4, - CLK_TOP_TVDPLL2_D4, - CLK_TOP_TVDPLL1_D8, - CLK_TOP_TVDPLL2_D8, - CLK_TOP_TVDPLL1_D16, - CLK_TOP_TVDPLL2_D16 -}; - -static const int disp_pwm0_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_UNIVPLL_D6_D4, - CLK_TOP_ULPOSC1_D2, - CLK_TOP_ULPOSC1_D4, - CLK_TOP_ULPOSC1_D16, - CLK_TOP_ETHPLL_D4 -}; - -static const int disp_pwm1_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_UNIVPLL_D6_D4, - CLK_TOP_ULPOSC1_D2, - CLK_TOP_ULPOSC1_D4, - CLK_TOP_ULPOSC1_D16 -}; - -static const int usb_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_UNIVPLL_D5_D4, - CLK_TOP_UNIVPLL_D6_D4, - CLK_TOP_UNIVPLL_D5_D2 -}; - -static const int ssusb_xhci_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_UNIVPLL_D5_D4, - CLK_TOP_UNIVPLL_D6_D4, - CLK_TOP_UNIVPLL_D5_D2 -}; - -static const int usb_2p_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_UNIVPLL_D5_D4, - CLK_TOP_UNIVPLL_D6_D4, - CLK_TOP_UNIVPLL_D5_D2 -}; - -static const int ssusb_xhci_2p_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_UNIVPLL_D5_D4, - CLK_TOP_UNIVPLL_D6_D4, - CLK_TOP_UNIVPLL_D5_D2 -}; - -static const int usb_3p_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_UNIVPLL_D5_D4, - CLK_TOP_UNIVPLL_D6_D4, - CLK_TOP_UNIVPLL_D5_D2 -}; - -static const int ssusb_xhci_3p_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_UNIVPLL_D5_D4, - CLK_TOP_UNIVPLL_D6_D4, - CLK_TOP_UNIVPLL_D5_D2 -}; - -static const int i2c_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_MAINPLL_D4_D8, - CLK_TOP_UNIVPLL_D5_D4 -}; - -static const int seninf_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_UNIVPLL_D4_D4, - CLK_TOP_UNIVPLL_D6_D2, - CLK_TOP_MAINPLL_D4_D2, - CLK_TOP_UNIVPLL_D7, - CLK_TOP_UNIVPLL_D6, - CLK_TOP_MMPLL_D6, - CLK_TOP_UNIVPLL_D5 -}; - -static const int seninf1_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_UNIVPLL_D4_D4, - CLK_TOP_UNIVPLL_D6_D2, - CLK_TOP_MAINPLL_D4_D2, - CLK_TOP_UNIVPLL_D7, - CLK_TOP_UNIVPLL_D6, - CLK_TOP_MMPLL_D6, - CLK_TOP_UNIVPLL_D5 -}; - -static const int gcpu_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_MAINPLL_D6, - CLK_TOP_UNIVPLL_D4_D2, - CLK_TOP_MMPLL_D5_D2, - CLK_TOP_UNIVPLL_D5_D2 -}; - -static const int venc_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_MMPLL_D4_D2, - CLK_TOP_MAINPLL_D6, - CLK_TOP_UNIVPLL_D4_D2, - CLK_TOP_MAINPLL_D4_D2, - CLK_TOP_UNIVPLL_D6, - CLK_TOP_MMPLL_D6, - CLK_TOP_MAINPLL_D5_D2, - CLK_TOP_MAINPLL_D6_D2, - CLK_TOP_MMPLL_D9, - CLK_TOP_UNIVPLL_D4_D4, - CLK_TOP_MAINPLL_D4, - CLK_TOP_UNIVPLL_D4, - CLK_TOP_UNIVPLL_D5, - CLK_TOP_UNIVPLL_D5_D2, - CLK_TOP_MAINPLL_D5 -}; - -static const int vdec_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_MAINPLL_D5_D2, - CLK_TOP_MMPLL_D6_D2, - CLK_TOP_UNIVPLL_D5_D2, - CLK_TOP_UNIVPLL_D4_D2, - CLK_TOP_MMPLL_D4_D2, - CLK_TOP_UNIVPLL_D6, - CLK_TOP_MAINPLL_D5, - CLK_TOP_UNIVPLL_D5, - CLK_TOP_MMPLL_D6, - CLK_TOP_MAINPLL_D4, - CLK_TOP_TVDPLL2, - CLK_TOP_UNIVPLL_D4, - CLK_TOP_IMGPLL, - CLK_TOP_UNIVPLL_D6_D2, - CLK_TOP_MMPLL_D9 -}; - -static const int pwm_parents[] = { - CLK_TOP_CLK32K, - CLK_TOP_CLK26M, - CLK_TOP_UNIVPLL_D4_D8, - CLK_TOP_UNIVPLL_D6_D4 -}; - -static const int mcupm_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_MAINPLL_D6_D2, - CLK_TOP_MAINPLL_D7_D4 -}; - -static const int spmi_p_mst_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_CLK13M, - CLK_TOP_ULPOSC1_D8, - CLK_TOP_ULPOSC1_D10, - CLK_TOP_ULPOSC1_D16, - CLK_TOP_ULPOSC1_D7, - CLK_TOP_CLK32K, - CLK_TOP_MAINPLL_D7_D8, - CLK_TOP_MAINPLL_D6_D8, - CLK_TOP_MAINPLL_D5_D8 -}; - -static const int spmi_m_mst_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_CLK13M, - CLK_TOP_ULPOSC1_D8, - CLK_TOP_ULPOSC1_D10, - CLK_TOP_ULPOSC1_D16, - CLK_TOP_ULPOSC1_D7, - CLK_TOP_CLK32K, - CLK_TOP_MAINPLL_D7_D8, - CLK_TOP_MAINPLL_D6_D8, - CLK_TOP_MAINPLL_D5_D8 -}; - -static const int dvfsrc_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_ULPOSC1_D10, - CLK_TOP_UNIVPLL_D6_D8, - CLK_TOP_MSDCPLL_D16 -}; - -static const int tl_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_UNIVPLL_D5_D4, - CLK_TOP_MAINPLL_D4_D4 -}; - -static const int aes_msdcfde_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_MAINPLL_D4_D2, - CLK_TOP_MAINPLL_D6, - CLK_TOP_MAINPLL_D4_D4, - CLK_TOP_UNIVPLL_D4_D2, - CLK_TOP_UNIVPLL_D6 -}; - -static const int dsi_occ_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_UNIVPLL_D6_D2, - CLK_TOP_UNIVPLL_D5_D2, - CLK_TOP_UNIVPLL_D4_D2 -}; - -static const int wpe_vpp_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_MAINPLL_D5_D2, - CLK_TOP_MMPLL_D6_D2, - CLK_TOP_UNIVPLL_D5_D2, - CLK_TOP_MAINPLL_D4_D2, - CLK_TOP_UNIVPLL_D4_D2, - CLK_TOP_MMPLL_D4_D2, - CLK_TOP_MAINPLL_D6, - CLK_TOP_MMPLL_D7, - CLK_TOP_UNIVPLL_D6, - CLK_TOP_MAINPLL_D5, - CLK_TOP_UNIVPLL_D5, - CLK_TOP_MAINPLL_D4, - CLK_TOP_TVDPLL1, - CLK_TOP_UNIVPLL_D4 -}; - -static const int hdcp_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_UNIVPLL_D4_D8, - CLK_TOP_MAINPLL_D5_D8, - CLK_TOP_UNIVPLL_D6_D4 + +static const struct mtk_parent dpi_parents[] = { + TOP_PARENT(CLK_TOP_CLK26M), + TOP_PARENT(CLK_TOP_TVDPLL1_D2), + TOP_PARENT(CLK_TOP_TVDPLL2_D2), + TOP_PARENT(CLK_TOP_TVDPLL1_D4), + TOP_PARENT(CLK_TOP_TVDPLL2_D4), + TOP_PARENT(CLK_TOP_TVDPLL1_D8), + TOP_PARENT(CLK_TOP_TVDPLL2_D8), + TOP_PARENT(CLK_TOP_TVDPLL1_D16), + TOP_PARENT(CLK_TOP_TVDPLL2_D16), +}; + +static const struct mtk_parent disp_pwm0_parents[] = { + TOP_PARENT(CLK_TOP_CLK26M), + TOP_PARENT(CLK_TOP_UNIVPLL_D6_D4), + TOP_PARENT(CLK_TOP_ULPOSC1_D2), + TOP_PARENT(CLK_TOP_ULPOSC1_D4), + TOP_PARENT(CLK_TOP_ULPOSC1_D16), + TOP_PARENT(CLK_TOP_ETHPLL_D4), +}; + +static const struct mtk_parent disp_pwm1_parents[] = { + TOP_PARENT(CLK_TOP_CLK26M), + TOP_PARENT(CLK_TOP_UNIVPLL_D6_D4), + TOP_PARENT(CLK_TOP_ULPOSC1_D2), + TOP_PARENT(CLK_TOP_ULPOSC1_D4), + TOP_PARENT(CLK_TOP_ULPOSC1_D16), +}; + +static const struct mtk_parent usb_parents[] = { + TOP_PARENT(CLK_TOP_CLK26M), + TOP_PARENT(CLK_TOP_UNIVPLL_D5_D4), + TOP_PARENT(CLK_TOP_UNIVPLL_D6_D4), + TOP_PARENT(CLK_TOP_UNIVPLL_D5_D2), +}; + +static const struct mtk_parent ssusb_xhci_parents[] = { + TOP_PARENT(CLK_TOP_CLK26M), + TOP_PARENT(CLK_TOP_UNIVPLL_D5_D4), + TOP_PARENT(CLK_TOP_UNIVPLL_D6_D4), + TOP_PARENT(CLK_TOP_UNIVPLL_D5_D2), +}; + +static const struct mtk_parent usb_2p_parents[] = { + TOP_PARENT(CLK_TOP_CLK26M), + TOP_PARENT(CLK_TOP_UNIVPLL_D5_D4), + TOP_PARENT(CLK_TOP_UNIVPLL_D6_D4), + TOP_PARENT(CLK_TOP_UNIVPLL_D5_D2), +}; + +static const struct mtk_parent ssusb_xhci_2p_parents[] = { + TOP_PARENT(CLK_TOP_CLK26M), + TOP_PARENT(CLK_TOP_UNIVPLL_D5_D4), + TOP_PARENT(CLK_TOP_UNIVPLL_D6_D4), + TOP_PARENT(CLK_TOP_UNIVPLL_D5_D2), +}; + +static const struct mtk_parent usb_3p_parents[] = { + TOP_PARENT(CLK_TOP_CLK26M), + TOP_PARENT(CLK_TOP_UNIVPLL_D5_D4), + TOP_PARENT(CLK_TOP_UNIVPLL_D6_D4), + TOP_PARENT(CLK_TOP_UNIVPLL_D5_D2), +}; + +static const struct mtk_parent ssusb_xhci_3p_parents[] = { + TOP_PARENT(CLK_TOP_CLK26M), + TOP_PARENT(CLK_TOP_UNIVPLL_D5_D4), + TOP_PARENT(CLK_TOP_UNIVPLL_D6_D4), + TOP_PARENT(CLK_TOP_UNIVPLL_D5_D2), +}; + +static const struct mtk_parent i2c_parents[] = { + TOP_PARENT(CLK_TOP_CLK26M), + TOP_PARENT(CLK_TOP_MAINPLL_D4_D8), + TOP_PARENT(CLK_TOP_UNIVPLL_D5_D4), +}; + +static const struct mtk_parent seninf_parents[] = { + TOP_PARENT(CLK_TOP_CLK26M), + TOP_PARENT(CLK_TOP_UNIVPLL_D4_D4), + TOP_PARENT(CLK_TOP_UNIVPLL_D6_D2), + TOP_PARENT(CLK_TOP_MAINPLL_D4_D2), + TOP_PARENT(CLK_TOP_UNIVPLL_D7), + TOP_PARENT(CLK_TOP_UNIVPLL_D6), + TOP_PARENT(CLK_TOP_MMPLL_D6), + TOP_PARENT(CLK_TOP_UNIVPLL_D5), +}; + +static const struct mtk_parent seninf1_parents[] = { + TOP_PARENT(CLK_TOP_CLK26M), + TOP_PARENT(CLK_TOP_UNIVPLL_D4_D4), + TOP_PARENT(CLK_TOP_UNIVPLL_D6_D2), + TOP_PARENT(CLK_TOP_MAINPLL_D4_D2), + TOP_PARENT(CLK_TOP_UNIVPLL_D7), + TOP_PARENT(CLK_TOP_UNIVPLL_D6), + TOP_PARENT(CLK_TOP_MMPLL_D6), + TOP_PARENT(CLK_TOP_UNIVPLL_D5), +}; + +static const struct mtk_parent gcpu_parents[] = { + TOP_PARENT(CLK_TOP_CLK26M), + TOP_PARENT(CLK_TOP_MAINPLL_D6), + TOP_PARENT(CLK_TOP_UNIVPLL_D4_D2), + TOP_PARENT(CLK_TOP_MMPLL_D5_D2), + TOP_PARENT(CLK_TOP_UNIVPLL_D5_D2), +}; + +static const struct mtk_parent venc_parents[] = { + TOP_PARENT(CLK_TOP_CLK26M), + TOP_PARENT(CLK_TOP_MMPLL_D4_D2), + TOP_PARENT(CLK_TOP_MAINPLL_D6), + TOP_PARENT(CLK_TOP_UNIVPLL_D4_D2), + TOP_PARENT(CLK_TOP_MAINPLL_D4_D2), + TOP_PARENT(CLK_TOP_UNIVPLL_D6), + TOP_PARENT(CLK_TOP_MMPLL_D6), + TOP_PARENT(CLK_TOP_MAINPLL_D5_D2), + TOP_PARENT(CLK_TOP_MAINPLL_D6_D2), + TOP_PARENT(CLK_TOP_MMPLL_D9), + TOP_PARENT(CLK_TOP_UNIVPLL_D4_D4), + TOP_PARENT(CLK_TOP_MAINPLL_D4), + TOP_PARENT(CLK_TOP_UNIVPLL_D4), + TOP_PARENT(CLK_TOP_UNIVPLL_D5), + TOP_PARENT(CLK_TOP_UNIVPLL_D5_D2), + TOP_PARENT(CLK_TOP_MAINPLL_D5), +}; + +static const struct mtk_parent vdec_parents[] = { + TOP_PARENT(CLK_TOP_CLK26M), + TOP_PARENT(CLK_TOP_MAINPLL_D5_D2), + TOP_PARENT(CLK_TOP_MMPLL_D6_D2), + TOP_PARENT(CLK_TOP_UNIVPLL_D5_D2), + TOP_PARENT(CLK_TOP_UNIVPLL_D4_D2), + TOP_PARENT(CLK_TOP_MMPLL_D4_D2), + TOP_PARENT(CLK_TOP_UNIVPLL_D6), + TOP_PARENT(CLK_TOP_MAINPLL_D5), + TOP_PARENT(CLK_TOP_UNIVPLL_D5), + TOP_PARENT(CLK_TOP_MMPLL_D6), + TOP_PARENT(CLK_TOP_MAINPLL_D4), + TOP_PARENT(CLK_TOP_TVDPLL2), + TOP_PARENT(CLK_TOP_UNIVPLL_D4), + TOP_PARENT(CLK_TOP_IMGPLL), + TOP_PARENT(CLK_TOP_UNIVPLL_D6_D2), + TOP_PARENT(CLK_TOP_MMPLL_D9), +}; + +static const struct mtk_parent pwm_parents[] = { + TOP_PARENT(CLK_TOP_CLK32K), + TOP_PARENT(CLK_TOP_CLK26M), + TOP_PARENT(CLK_TOP_UNIVPLL_D4_D8), + TOP_PARENT(CLK_TOP_UNIVPLL_D6_D4), +}; + +static const struct mtk_parent mcupm_parents[] = { + TOP_PARENT(CLK_TOP_CLK26M), + TOP_PARENT(CLK_TOP_MAINPLL_D6_D2), + TOP_PARENT(CLK_TOP_MAINPLL_D7_D4), +}; + +static const struct mtk_parent spmi_p_mst_parents[] = { + TOP_PARENT(CLK_TOP_CLK26M), + TOP_PARENT(CLK_TOP_CLK13M), + TOP_PARENT(CLK_TOP_ULPOSC1_D8), + TOP_PARENT(CLK_TOP_ULPOSC1_D10), + TOP_PARENT(CLK_TOP_ULPOSC1_D16), + TOP_PARENT(CLK_TOP_ULPOSC1_D7), + TOP_PARENT(CLK_TOP_CLK32K), + TOP_PARENT(CLK_TOP_MAINPLL_D7_D8), + TOP_PARENT(CLK_TOP_MAINPLL_D6_D8), + TOP_PARENT(CLK_TOP_MAINPLL_D5_D8), +}; + +static const struct mtk_parent spmi_m_mst_parents[] = { + TOP_PARENT(CLK_TOP_CLK26M), + TOP_PARENT(CLK_TOP_CLK13M), + TOP_PARENT(CLK_TOP_ULPOSC1_D8), + TOP_PARENT(CLK_TOP_ULPOSC1_D10), + TOP_PARENT(CLK_TOP_ULPOSC1_D16), + TOP_PARENT(CLK_TOP_ULPOSC1_D7), + TOP_PARENT(CLK_TOP_CLK32K), + TOP_PARENT(CLK_TOP_MAINPLL_D7_D8), + TOP_PARENT(CLK_TOP_MAINPLL_D6_D8), + TOP_PARENT(CLK_TOP_MAINPLL_D5_D8), +}; + +static const struct mtk_parent dvfsrc_parents[] = { + TOP_PARENT(CLK_TOP_CLK26M), + TOP_PARENT(CLK_TOP_ULPOSC1_D10), + TOP_PARENT(CLK_TOP_UNIVPLL_D6_D8), + TOP_PARENT(CLK_TOP_MSDCPLL_D16), +}; + +static const struct mtk_parent tl_parents[] = { + TOP_PARENT(CLK_TOP_CLK26M), + TOP_PARENT(CLK_TOP_UNIVPLL_D5_D4), + TOP_PARENT(CLK_TOP_MAINPLL_D4_D4), +}; + +static const struct mtk_parent aes_msdcfde_parents[] = { + TOP_PARENT(CLK_TOP_CLK26M), + TOP_PARENT(CLK_TOP_MAINPLL_D4_D2), + TOP_PARENT(CLK_TOP_MAINPLL_D6), + TOP_PARENT(CLK_TOP_MAINPLL_D4_D4), + TOP_PARENT(CLK_TOP_UNIVPLL_D4_D2), + TOP_PARENT(CLK_TOP_UNIVPLL_D6), +}; + +static const struct mtk_parent dsi_occ_parents[] = { + TOP_PARENT(CLK_TOP_CLK26M), + TOP_PARENT(CLK_TOP_UNIVPLL_D6_D2), + TOP_PARENT(CLK_TOP_UNIVPLL_D5_D2), + TOP_PARENT(CLK_TOP_UNIVPLL_D4_D2), +}; + +static const struct mtk_parent wpe_vpp_parents[] = { + TOP_PARENT(CLK_TOP_CLK26M), + TOP_PARENT(CLK_TOP_MAINPLL_D5_D2), + TOP_PARENT(CLK_TOP_MMPLL_D6_D2), + TOP_PARENT(CLK_TOP_UNIVPLL_D5_D2), + TOP_PARENT(CLK_TOP_MAINPLL_D4_D2), + TOP_PARENT(CLK_TOP_UNIVPLL_D4_D2), + TOP_PARENT(CLK_TOP_MMPLL_D4_D2), + TOP_PARENT(CLK_TOP_MAINPLL_D6), + TOP_PARENT(CLK_TOP_MMPLL_D7), + TOP_PARENT(CLK_TOP_UNIVPLL_D6), + TOP_PARENT(CLK_TOP_MAINPLL_D5), + TOP_PARENT(CLK_TOP_UNIVPLL_D5), + TOP_PARENT(CLK_TOP_MAINPLL_D4), + TOP_PARENT(CLK_TOP_TVDPLL1), + TOP_PARENT(CLK_TOP_UNIVPLL_D4), +}; + +static const struct mtk_parent hdcp_parents[] = { + TOP_PARENT(CLK_TOP_CLK26M), + TOP_PARENT(CLK_TOP_UNIVPLL_D4_D8), + TOP_PARENT(CLK_TOP_MAINPLL_D5_D8), + TOP_PARENT(CLK_TOP_UNIVPLL_D6_D4), }; -static const int hdcp_24m_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_UNIVPLL_192M_D4, - CLK_TOP_UNIVPLL_192M_D8, - CLK_TOP_UNIVPLL_D6_D8 +static const struct mtk_parent hdcp_24m_parents[] = { + TOP_PARENT(CLK_TOP_CLK26M), + TOP_PARENT(CLK_TOP_UNIVPLL_192M_D4), + TOP_PARENT(CLK_TOP_UNIVPLL_192M_D8), + TOP_PARENT(CLK_TOP_UNIVPLL_D6_D8), }; -static const int hdmi_apb_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_UNIVPLL_D6_D4, - CLK_TOP_MSDCPLL_D2 +static const struct mtk_parent hdmi_apb_parents[] = { + TOP_PARENT(CLK_TOP_CLK26M), + TOP_PARENT(CLK_TOP_UNIVPLL_D6_D4), + TOP_PARENT(CLK_TOP_MSDCPLL_D2), }; -static const int snps_eth_250m_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_ETHPLL_D2 +static const struct mtk_parent snps_eth_250m_parents[] = { + TOP_PARENT(CLK_TOP_CLK26M), + TOP_PARENT(CLK_TOP_ETHPLL_D2), }; -static const int snps_eth_62p4m_ptp_parents[] = { - CLK_TOP_APLL2_D3, - CLK_TOP_APLL1_D3, - CLK_TOP_CLK26M, - CLK_TOP_ETHPLL_D8 -}; - -static const int snps_eth_50m_rmii_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_ETHPLL_D10 +static const struct mtk_parent snps_eth_62p4m_ptp_parents[] = { + TOP_PARENT(CLK_TOP_APLL2_D3), + TOP_PARENT(CLK_TOP_APLL1_D3), + TOP_PARENT(CLK_TOP_CLK26M), + TOP_PARENT(CLK_TOP_ETHPLL_D8), +}; + +static const struct mtk_parent snps_eth_50m_rmii_parents[] = { + TOP_PARENT(CLK_TOP_CLK26M), + TOP_PARENT(CLK_TOP_ETHPLL_D10), }; -static const int adsp_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_CLK13M, - CLK_TOP_MAINPLL_D6, - CLK_TOP_MAINPLL_D5_D2, - CLK_TOP_UNIVPLL_D4_D4, - CLK_TOP_UNIVPLL_D4, - CLK_TOP_ULPOSC1_D2, - CLK_TOP_ULPOSC1, - CLK_TOP_ADSPPLL, - CLK_TOP_ADSPPLL_D2, - CLK_TOP_ADSPPLL_D4, - CLK_TOP_ADSPPLL_D8 +static const struct mtk_parent adsp_parents[] = { + TOP_PARENT(CLK_TOP_CLK26M), + TOP_PARENT(CLK_TOP_CLK13M), + TOP_PARENT(CLK_TOP_MAINPLL_D6), + TOP_PARENT(CLK_TOP_MAINPLL_D5_D2), + TOP_PARENT(CLK_TOP_UNIVPLL_D4_D4), + TOP_PARENT(CLK_TOP_UNIVPLL_D4), + TOP_PARENT(CLK_TOP_ULPOSC1_D2), + TOP_PARENT(CLK_TOP_ULPOSC1), + TOP_PARENT(CLK_TOP_ADSPPLL), + TOP_PARENT(CLK_TOP_ADSPPLL_D2), + TOP_PARENT(CLK_TOP_ADSPPLL_D4), + TOP_PARENT(CLK_TOP_ADSPPLL_D8), }; -static const int audio_local_bus_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_CLK13M, - CLK_TOP_MAINPLL_D4_D4, - CLK_TOP_MAINPLL_D7_D2, - CLK_TOP_MAINPLL_D5_D2, - CLK_TOP_MAINPLL_D4_D2, - CLK_TOP_MAINPLL_D7, - CLK_TOP_MAINPLL_D4, - CLK_TOP_UNIVPLL_D6, - CLK_TOP_ULPOSC1, - CLK_TOP_ULPOSC1_D4, - CLK_TOP_ULPOSC1_D2 +static const struct mtk_parent audio_local_bus_parents[] = { + TOP_PARENT(CLK_TOP_CLK26M), + TOP_PARENT(CLK_TOP_CLK13M), + TOP_PARENT(CLK_TOP_MAINPLL_D4_D4), + TOP_PARENT(CLK_TOP_MAINPLL_D7_D2), + TOP_PARENT(CLK_TOP_MAINPLL_D5_D2), + TOP_PARENT(CLK_TOP_MAINPLL_D4_D2), + TOP_PARENT(CLK_TOP_MAINPLL_D7), + TOP_PARENT(CLK_TOP_MAINPLL_D4), + TOP_PARENT(CLK_TOP_UNIVPLL_D6), + TOP_PARENT(CLK_TOP_ULPOSC1), + TOP_PARENT(CLK_TOP_ULPOSC1_D4), + TOP_PARENT(CLK_TOP_ULPOSC1_D2), }; -static const int asm_h_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_UNIVPLL_D6_D4, - CLK_TOP_UNIVPLL_D6_D2, - CLK_TOP_MAINPLL_D5_D2 +static const struct mtk_parent asm_h_parents[] = { + TOP_PARENT(CLK_TOP_CLK26M), + TOP_PARENT(CLK_TOP_UNIVPLL_D6_D4), + TOP_PARENT(CLK_TOP_UNIVPLL_D6_D2), + TOP_PARENT(CLK_TOP_MAINPLL_D5_D2), }; -static const int asm_l_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_UNIVPLL_D6_D4, - CLK_TOP_UNIVPLL_D6_D2, - CLK_TOP_MAINPLL_D5_D2 +static const struct mtk_parent asm_l_parents[] = { + TOP_PARENT(CLK_TOP_CLK26M), + TOP_PARENT(CLK_TOP_UNIVPLL_D6_D4), + TOP_PARENT(CLK_TOP_UNIVPLL_D6_D2), + TOP_PARENT(CLK_TOP_MAINPLL_D5_D2), }; -static const int apll1_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_APLL1_D4 +static const struct mtk_parent apll1_parents[] = { + TOP_PARENT(CLK_TOP_CLK26M), + TOP_PARENT(CLK_TOP_APLL1_D4), }; -static const int apll2_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_APLL2_D4 +static const struct mtk_parent apll2_parents[] = { + TOP_PARENT(CLK_TOP_CLK26M), + TOP_PARENT(CLK_TOP_APLL2_D4), }; -static const int apll3_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_APLL3_D4 +static const struct mtk_parent apll3_parents[] = { + TOP_PARENT(CLK_TOP_CLK26M), + TOP_PARENT(CLK_TOP_APLL3_D4), }; -static const int apll4_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_APLL4_D4 +static const struct mtk_parent apll4_parents[] = { + TOP_PARENT(CLK_TOP_CLK26M), + TOP_PARENT(CLK_TOP_APLL4_D4), }; -static const int apll5_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_APLL5_D4 +static const struct mtk_parent apll5_parents[] = { + TOP_PARENT(CLK_TOP_CLK26M), + TOP_PARENT(CLK_TOP_APLL5_D4), }; -static const int i2so1_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_APLL1, - CLK_TOP_APLL2, - CLK_TOP_APLL3, - CLK_TOP_APLL4, - CLK_TOP_APLL5 +static const struct mtk_parent i2so1_parents[] = { + TOP_PARENT(CLK_TOP_CLK26M), + TOP_PARENT(CLK_TOP_APLL1), + TOP_PARENT(CLK_TOP_APLL2), + TOP_PARENT(CLK_TOP_APLL3), + TOP_PARENT(CLK_TOP_APLL4), + TOP_PARENT(CLK_TOP_APLL5), }; -static const int i2so2_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_APLL1, - CLK_TOP_APLL2, - CLK_TOP_APLL3, - CLK_TOP_APLL4, - CLK_TOP_APLL5 +static const struct mtk_parent i2so2_parents[] = { + TOP_PARENT(CLK_TOP_CLK26M), + TOP_PARENT(CLK_TOP_APLL1), + TOP_PARENT(CLK_TOP_APLL2), + TOP_PARENT(CLK_TOP_APLL3), + TOP_PARENT(CLK_TOP_APLL4), + TOP_PARENT(CLK_TOP_APLL5), }; -static const int i2si1_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_APLL1, - CLK_TOP_APLL2, - CLK_TOP_APLL3, - CLK_TOP_APLL4, - CLK_TOP_APLL5 +static const struct mtk_parent i2si1_parents[] = { + TOP_PARENT(CLK_TOP_CLK26M), + TOP_PARENT(CLK_TOP_APLL1), + TOP_PARENT(CLK_TOP_APLL2), + TOP_PARENT(CLK_TOP_APLL3), + TOP_PARENT(CLK_TOP_APLL4), + TOP_PARENT(CLK_TOP_APLL5), }; -static const int i2si2_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_APLL1, - CLK_TOP_APLL2, - CLK_TOP_APLL3, - CLK_TOP_APLL4, - CLK_TOP_APLL5 +static const struct mtk_parent i2si2_parents[] = { + TOP_PARENT(CLK_TOP_CLK26M), + TOP_PARENT(CLK_TOP_APLL1), + TOP_PARENT(CLK_TOP_APLL2), + TOP_PARENT(CLK_TOP_APLL3), + TOP_PARENT(CLK_TOP_APLL4), + TOP_PARENT(CLK_TOP_APLL5), }; -static const int dptx_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_APLL1, - CLK_TOP_APLL2, - CLK_TOP_APLL3, - CLK_TOP_APLL4, - CLK_TOP_APLL5 +static const struct mtk_parent dptx_parents[] = { + TOP_PARENT(CLK_TOP_CLK26M), + TOP_PARENT(CLK_TOP_APLL1), + TOP_PARENT(CLK_TOP_APLL2), + TOP_PARENT(CLK_TOP_APLL3), + TOP_PARENT(CLK_TOP_APLL4), + TOP_PARENT(CLK_TOP_APLL5), }; -static const int aud_iec_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_APLL1, - CLK_TOP_APLL2, - CLK_TOP_APLL3, - CLK_TOP_APLL4, - CLK_TOP_APLL5 +static const struct mtk_parent aud_iec_parents[] = { + TOP_PARENT(CLK_TOP_CLK26M), + TOP_PARENT(CLK_TOP_APLL1), + TOP_PARENT(CLK_TOP_APLL2), + TOP_PARENT(CLK_TOP_APLL3), + TOP_PARENT(CLK_TOP_APLL4), + TOP_PARENT(CLK_TOP_APLL5), }; -static const int a1sys_hp_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_APLL1_D4 +static const struct mtk_parent a1sys_hp_parents[] = { + TOP_PARENT(CLK_TOP_CLK26M), + TOP_PARENT(CLK_TOP_APLL1_D4), }; -static const int a2sys_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_APLL2_D4 +static const struct mtk_parent a2sys_parents[] = { + TOP_PARENT(CLK_TOP_CLK26M), + TOP_PARENT(CLK_TOP_APLL2_D4), }; -static const int a3sys_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_APLL3_D4, - CLK_TOP_APLL4_D4, - CLK_TOP_APLL5_D4 +static const struct mtk_parent a3sys_parents[] = { + TOP_PARENT(CLK_TOP_CLK26M), + TOP_PARENT(CLK_TOP_APLL3_D4), + TOP_PARENT(CLK_TOP_APLL4_D4), + TOP_PARENT(CLK_TOP_APLL5_D4), }; -static const int a4sys_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_APLL3_D4, - CLK_TOP_APLL4_D4, - CLK_TOP_APLL5_D4 +static const struct mtk_parent a4sys_parents[] = { + TOP_PARENT(CLK_TOP_CLK26M), + TOP_PARENT(CLK_TOP_APLL3_D4), + TOP_PARENT(CLK_TOP_APLL4_D4), + TOP_PARENT(CLK_TOP_APLL5_D4), }; -static const int ecc_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_MAINPLL_D4_D4, - CLK_TOP_MAINPLL_D5_D2, - CLK_TOP_MAINPLL_D4_D2, - CLK_TOP_MAINPLL_D6, - CLK_TOP_UNIVPLL_D6 +static const struct mtk_parent ecc_parents[] = { + TOP_PARENT(CLK_TOP_CLK26M), + TOP_PARENT(CLK_TOP_MAINPLL_D4_D4), + TOP_PARENT(CLK_TOP_MAINPLL_D5_D2), + TOP_PARENT(CLK_TOP_MAINPLL_D4_D2), + TOP_PARENT(CLK_TOP_MAINPLL_D6), + TOP_PARENT(CLK_TOP_UNIVPLL_D6), }; -static const int spinor_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_CLK13M, - CLK_TOP_MAINPLL_D7_D8, - CLK_TOP_UNIVPLL_D6_D8 +static const struct mtk_parent spinor_parents[] = { + TOP_PARENT(CLK_TOP_CLK26M), + TOP_PARENT(CLK_TOP_CLK13M), + TOP_PARENT(CLK_TOP_MAINPLL_D7_D8), + TOP_PARENT(CLK_TOP_UNIVPLL_D6_D8), }; -static const int ulposc_parents[] = { - CLK_TOP_ULPOSC1, - CLK_TOP_ETHPLL_D2, - CLK_TOP_MAINPLL_D4_D2, - CLK_TOP_ETHPLL_D10 +static const struct mtk_parent ulposc_parents[] = { + TOP_PARENT(CLK_TOP_ULPOSC1), + TOP_PARENT(CLK_TOP_ETHPLL_D2), + TOP_PARENT(CLK_TOP_MAINPLL_D4_D2), + TOP_PARENT(CLK_TOP_ETHPLL_D10), }; -static const int srck_parents[] = { - CLK_TOP_ULPOSC1_D10, - CLK_TOP_CLK26M +static const struct mtk_parent srck_parents[] = { + TOP_PARENT(CLK_TOP_ULPOSC1_D10), + TOP_PARENT(CLK_TOP_CLK26M), }; static const struct mtk_composite top_muxes[] = { /* CLK_CFG_0 */ - MUX_GATE(CLK_TOP_AXI, axi_parents, 0x020, 0, 4, 7), - MUX_GATE(CLK_TOP_SPM, spm_parents, 0x020, 8, 4, 15), - MUX_GATE(CLK_TOP_SCP, scp_parents, 0x020, 16, 4, 23), - MUX_GATE(CLK_TOP_BUS_AXIMEM, bus_aximem_parents, 0x020, 24, 4, 31), + MUX_GATE_MIXED(CLK_TOP_AXI, axi_parents, 0x020, 0, 4, 7), + MUX_GATE_MIXED(CLK_TOP_SPM, spm_parents, 0x020, 8, 4, 15), + MUX_GATE_MIXED(CLK_TOP_SCP, scp_parents, 0x020, 16, 4, 23), + MUX_GATE_MIXED(CLK_TOP_BUS_AXIMEM, bus_aximem_parents, 0x020, 24, 4, 31), /* CLK_CFG_1 */ - MUX_GATE(CLK_TOP_VPP, vpp_parents, 0x02C, 0, 4, 7), - MUX_GATE(CLK_TOP_ETHDR, ethdr_parents, 0x02C, 8, 4, 15), - MUX_GATE(CLK_TOP_IPE, ipe_parents, 0x02C, 16, 4, 23), - MUX_GATE(CLK_TOP_CAM, cam_parents, 0x02C, 24, 4, 31), + MUX_GATE_MIXED(CLK_TOP_VPP, vpp_parents, 0x02C, 0, 4, 7), + MUX_GATE_MIXED(CLK_TOP_ETHDR, ethdr_parents, 0x02C, 8, 4, 15), + MUX_GATE_MIXED(CLK_TOP_IPE, ipe_parents, 0x02C, 16, 4, 23), + MUX_GATE_MIXED(CLK_TOP_CAM, cam_parents, 0x02C, 24, 4, 31), /* CLK_CFG_2 */ - MUX_GATE(CLK_TOP_CCU, ccu_parents, 0x038, 0, 4, 7), - MUX_GATE(CLK_TOP_CCU_AHB, ccu_ahb_parents, 0x038, 8, 4, 15), - MUX_GATE(CLK_TOP_IMG, img_parents, 0x038, 16, 4, 23), - MUX_GATE(CLK_TOP_CAMTM, camtm_parents, 0x038, 24, 4, 31), + MUX_GATE_MIXED(CLK_TOP_CCU, ccu_parents, 0x038, 0, 4, 7), + MUX_GATE_MIXED(CLK_TOP_CCU_AHB, ccu_ahb_parents, 0x038, 8, 4, 15), + MUX_GATE_MIXED(CLK_TOP_IMG, img_parents, 0x038, 16, 4, 23), + MUX_GATE_MIXED(CLK_TOP_CAMTM, camtm_parents, 0x038, 24, 4, 31), /* CLK_CFG_3 */ - MUX_GATE(CLK_TOP_DSP, dsp_parents, 0x044, 0, 4, 7), - MUX_GATE(CLK_TOP_DSP1, dsp1_parents, 0x044, 8, 4, 15), - MUX_GATE(CLK_TOP_DSP2, dsp2_parents, 0x044, 16, 4, 23), - MUX_GATE(CLK_TOP_DSP3, dsp3_parents, 0x044, 24, 4, 31), + MUX_GATE_MIXED(CLK_TOP_DSP, dsp_parents, 0x044, 0, 4, 7), + MUX_GATE_MIXED(CLK_TOP_DSP1, dsp1_parents, 0x044, 8, 4, 15), + MUX_GATE_MIXED(CLK_TOP_DSP2, dsp2_parents, 0x044, 16, 4, 23), + MUX_GATE_MIXED(CLK_TOP_DSP3, dsp3_parents, 0x044, 24, 4, 31), /* CLK_CFG_4 */ - MUX_GATE(CLK_TOP_DSP4, dsp4_parents, 0x050, 0, 4, 7), - MUX_GATE(CLK_TOP_DSP5, dsp5_parents, 0x050, 8, 4, 15), - MUX_GATE(CLK_TOP_DSP6, dsp6_parents, 0x050, 16, 4, 23), - MUX_GATE(CLK_TOP_DSP7, dsp7_parents, 0x050, 24, 4, 31), + MUX_GATE_MIXED(CLK_TOP_DSP4, dsp4_parents, 0x050, 0, 4, 7), + MUX_GATE_MIXED(CLK_TOP_DSP5, dsp5_parents, 0x050, 8, 4, 15), + MUX_GATE_MIXED(CLK_TOP_DSP6, dsp6_parents, 0x050, 16, 4, 23), + MUX_GATE_MIXED(CLK_TOP_DSP7, dsp7_parents, 0x050, 24, 4, 31), /* CLK_CFG_5 */ - MUX_GATE(CLK_TOP_MFG_CORE_TMP, mfg_core_tmp_parents, 0x05C, 0, 4, 7), - MUX_GATE(CLK_TOP_CAMTG, camtg_parents, 0x05C, 8, 4, 15), - MUX_GATE(CLK_TOP_CAMTG2, camtg2_parents, 0x05C, 16, 4, 23), - MUX_GATE(CLK_TOP_CAMTG3, camtg3_parents, 0x05C, 24, 4, 31), + MUX_GATE_MIXED(CLK_TOP_MFG_CORE_TMP, mfg_core_tmp_parents, 0x05C, 0, 4, 7), + MUX_GATE_MIXED(CLK_TOP_CAMTG, camtg_parents, 0x05C, 8, 4, 15), + MUX_GATE_MIXED(CLK_TOP_CAMTG2, camtg2_parents, 0x05C, 16, 4, 23), + MUX_GATE_MIXED(CLK_TOP_CAMTG3, camtg3_parents, 0x05C, 24, 4, 31), /* CLK_CFG_6 */ - MUX_GATE(CLK_TOP_UART, uart_parents, 0x068, 0, 4, 7), - MUX_GATE(CLK_TOP_SPI, spi_parents, 0x068, 8, 4, 15), - MUX_GATE(CLK_TOP_MSDC50_0_HCLK, msdc5hclk_parents, 0x068, 16, 4, 23), - MUX_GATE(CLK_TOP_MSDC50_0, msdc50_0_parents, 0x068, 24, 4, 31), + MUX_GATE_MIXED(CLK_TOP_UART, uart_parents, 0x068, 0, 4, 7), + MUX_GATE_MIXED(CLK_TOP_SPI, spi_parents, 0x068, 8, 4, 15), + MUX_GATE_MIXED(CLK_TOP_MSDC50_0_HCLK, msdc5hclk_parents, 0x068, 16, 4, 23), + MUX_GATE_MIXED(CLK_TOP_MSDC50_0, msdc50_0_parents, 0x068, 24, 4, 31), /* CLK_CFG_7 */ - MUX_GATE(CLK_TOP_MSDC30_1, msdc30_1_parents, 0x074, 0, 4, 7), - MUX_GATE(CLK_TOP_MSDC30_2, msdc30_2_parents, 0x074, 8, 4, 15), - MUX_GATE(CLK_TOP_INTDIR, intdir_parents, 0x074, 16, 4, 23), - MUX_GATE(CLK_TOP_AUD_INTBUS, aud_intbus_parents, 0x074, 24, 4, 31), + MUX_GATE_MIXED(CLK_TOP_MSDC30_1, msdc30_1_parents, 0x074, 0, 4, 7), + MUX_GATE_MIXED(CLK_TOP_MSDC30_2, msdc30_2_parents, 0x074, 8, 4, 15), + MUX_GATE_MIXED(CLK_TOP_INTDIR, intdir_parents, 0x074, 16, 4, 23), + MUX_GATE_MIXED(CLK_TOP_AUD_INTBUS, aud_intbus_parents, 0x074, 24, 4, 31), /* CLK_CFG_8 */ - MUX_GATE(CLK_TOP_AUDIO_H, audio_h_parents, 0x080, 0, 4, 7), - MUX_GATE(CLK_TOP_PWRAP_ULPOSC, pwrap_ulposc_parents, 0x080, 8, 4, 15), - MUX_GATE(CLK_TOP_ATB, atb_parents, 0x080, 16, 4, 23), - MUX_GATE(CLK_TOP_SSPM, sspm_parents, 0x080, 24, 4, 31), + MUX_GATE_MIXED(CLK_TOP_AUDIO_H, audio_h_parents, 0x080, 0, 4, 7), + MUX_GATE_MIXED(CLK_TOP_PWRAP_ULPOSC, pwrap_ulposc_parents, 0x080, 8, 4, 15), + MUX_GATE_MIXED(CLK_TOP_ATB, atb_parents, 0x080, 16, 4, 23), + MUX_GATE_MIXED(CLK_TOP_SSPM, sspm_parents, 0x080, 24, 4, 31), /* CLK_CFG_9 */ - MUX_GATE(CLK_TOP_DP, dp_parents, 0x08C, 0, 4, 7), - MUX_GATE(CLK_TOP_EDP, edp_parents, 0x08C, 8, 4, 15), - MUX_GATE(CLK_TOP_DPI, dpi_parents, 0x08C, 16, 4, 23), - MUX_GATE(CLK_TOP_DISP_PWM0, disp_pwm0_parents, 0x08C, 24, 4, 31), + MUX_GATE_MIXED(CLK_TOP_DP, dp_parents, 0x08C, 0, 4, 7), + MUX_GATE_MIXED(CLK_TOP_EDP, edp_parents, 0x08C, 8, 4, 15), + MUX_GATE_MIXED(CLK_TOP_DPI, dpi_parents, 0x08C, 16, 4, 23), + MUX_GATE_MIXED(CLK_TOP_DISP_PWM0, disp_pwm0_parents, 0x08C, 24, 4, 31), /* CLK_CFG_10 */ - MUX_GATE(CLK_TOP_DISP_PWM1, disp_pwm1_parents, 0x098, 0, 4, 7), - MUX_GATE(CLK_TOP_USB_TOP, usb_parents, 0x098, 8, 4, 15), - MUX_GATE(CLK_TOP_SSUSB_XHCI, ssusb_xhci_parents, 0x098, 16, 4, 23), - MUX_GATE(CLK_TOP_USB_TOP_2P, usb_2p_parents, 0x098, 24, 4, 31), + MUX_GATE_MIXED(CLK_TOP_DISP_PWM1, disp_pwm1_parents, 0x098, 0, 4, 7), + MUX_GATE_MIXED(CLK_TOP_USB_TOP, usb_parents, 0x098, 8, 4, 15), + MUX_GATE_MIXED(CLK_TOP_SSUSB_XHCI, ssusb_xhci_parents, 0x098, 16, 4, 23), + MUX_GATE_MIXED(CLK_TOP_USB_TOP_2P, usb_2p_parents, 0x098, 24, 4, 31), /* CLK_CFG_11 */ - MUX_GATE(CLK_TOP_SSUSB_XHCI_2P, ssusb_xhci_2p_parents, 0x0A4, 0, 4, 7), - MUX_GATE(CLK_TOP_USB_TOP_3P, usb_3p_parents, 0x0A4, 8, 4, 15), - MUX_GATE(CLK_TOP_SSUSB_XHCI_3P, ssusb_xhci_3p_parents, 0x0A4, 16, 4, 23), - MUX_GATE(CLK_TOP_I2C, i2c_parents, 0x0A4, 24, 4, 31), + MUX_GATE_MIXED(CLK_TOP_SSUSB_XHCI_2P, ssusb_xhci_2p_parents, 0x0A4, 0, 4, 7), + MUX_GATE_MIXED(CLK_TOP_USB_TOP_3P, usb_3p_parents, 0x0A4, 8, 4, 15), + MUX_GATE_MIXED(CLK_TOP_SSUSB_XHCI_3P, ssusb_xhci_3p_parents, 0x0A4, 16, 4, 23), + MUX_GATE_MIXED(CLK_TOP_I2C, i2c_parents, 0x0A4, 24, 4, 31), /* CLK_CFG_12 */ - MUX_GATE(CLK_TOP_SENINF, seninf_parents, 0x0B0, 0, 4, 7), - MUX_GATE(CLK_TOP_SENINF1, seninf1_parents, 0x0B0, 8, 4, 15), - MUX_GATE(CLK_TOP_GCPU, gcpu_parents, 0x0B0, 16, 4, 23), - MUX_GATE(CLK_TOP_VENC, venc_parents, 0x0B0, 24, 4, 31), + MUX_GATE_MIXED(CLK_TOP_SENINF, seninf_parents, 0x0B0, 0, 4, 7), + MUX_GATE_MIXED(CLK_TOP_SENINF1, seninf1_parents, 0x0B0, 8, 4, 15), + MUX_GATE_MIXED(CLK_TOP_GCPU, gcpu_parents, 0x0B0, 16, 4, 23), + MUX_GATE_MIXED(CLK_TOP_VENC, venc_parents, 0x0B0, 24, 4, 31), /* CLK_CFG_13 */ - MUX_GATE(CLK_TOP_VDEC, vdec_parents, 0x0BC, 0, 4, 7), - MUX_GATE(CLK_TOP_PWM, pwm_parents, 0x0BC, 8, 4, 15), - MUX_GATE(CLK_TOP_MCUPM, mcupm_parents, 0x0BC, 16, 4, 23), - MUX_GATE(CLK_TOP_SPMI_P_MST, spmi_p_mst_parents, 0x0BC, 24, 4, 31), + MUX_GATE_MIXED(CLK_TOP_VDEC, vdec_parents, 0x0BC, 0, 4, 7), + MUX_GATE_MIXED(CLK_TOP_PWM, pwm_parents, 0x0BC, 8, 4, 15), + MUX_GATE_MIXED(CLK_TOP_MCUPM, mcupm_parents, 0x0BC, 16, 4, 23), + MUX_GATE_MIXED(CLK_TOP_SPMI_P_MST, spmi_p_mst_parents, 0x0BC, 24, 4, 31), /* CLK_CFG_14 */ - MUX_GATE(CLK_TOP_SPMI_M_MST, spmi_m_mst_parents, 0x0C8, 0, 4, 7), - MUX_GATE(CLK_TOP_DVFSRC, dvfsrc_parents, 0x0C8, 8, 4, 15), - MUX_GATE(CLK_TOP_TL, tl_parents, 0x0C8, 16, 4, 23), - MUX_GATE(CLK_TOP_AES_MSDCFDE, aes_msdcfde_parents, 0x0C8, 24, 4, 31), + MUX_GATE_MIXED(CLK_TOP_SPMI_M_MST, spmi_m_mst_parents, 0x0C8, 0, 4, 7), + MUX_GATE_MIXED(CLK_TOP_DVFSRC, dvfsrc_parents, 0x0C8, 8, 4, 15), + MUX_GATE_MIXED(CLK_TOP_TL, tl_parents, 0x0C8, 16, 4, 23), + MUX_GATE_MIXED(CLK_TOP_AES_MSDCFDE, aes_msdcfde_parents, 0x0C8, 24, 4, 31), /* CLK_CFG_15 */ - MUX_GATE(CLK_TOP_DSI_OCC, dsi_occ_parents, 0x0D4, 0, 4, 7), - MUX_GATE(CLK_TOP_WPE_VPP, wpe_vpp_parents, 0x0D4, 8, 4, 15), - MUX_GATE(CLK_TOP_HDCP, hdcp_parents, 0x0D4, 16, 4, 23), - MUX_GATE(CLK_TOP_HDCP_24M, hdcp_24m_parents, 0x0D4, 24, 4, 31), + MUX_GATE_MIXED(CLK_TOP_DSI_OCC, dsi_occ_parents, 0x0D4, 0, 4, 7), + MUX_GATE_MIXED(CLK_TOP_WPE_VPP, wpe_vpp_parents, 0x0D4, 8, 4, 15), + MUX_GATE_MIXED(CLK_TOP_HDCP, hdcp_parents, 0x0D4, 16, 4, 23), + MUX_GATE_MIXED(CLK_TOP_HDCP_24M, hdcp_24m_parents, 0x0D4, 24, 4, 31), /* CLK_CFG_16 */ - MUX_GATE(CLK_TOP_HDMI_APB, hdmi_apb_parents, 0x0E0, 0, 4, 7), - MUX_GATE(CLK_TOP_SNPS_ETH_250M, snps_eth_250m_parents, 0x0E0, 8, 4, 15), - MUX_GATE(CLK_TOP_SNPS_ETH_62P4M_PTP, snps_eth_62p4m_ptp_parents, 0x0E0, 16, 4, 23), - MUX_GATE(CLK_TOP_SNPS_ETH_50M_RMII, snps_eth_50m_rmii_parents, 0x0E0, 24, 4, 31), + MUX_GATE_MIXED(CLK_TOP_HDMI_APB, hdmi_apb_parents, 0x0E0, 0, 4, 7), + MUX_GATE_MIXED(CLK_TOP_SNPS_ETH_250M, snps_eth_250m_parents, 0x0E0, 8, 4, 15), + MUX_GATE_MIXED(CLK_TOP_SNPS_ETH_62P4M_PTP, snps_eth_62p4m_ptp_parents, 0x0E0, 16, 4, 23), + MUX_GATE_MIXED(CLK_TOP_SNPS_ETH_50M_RMII, snps_eth_50m_rmii_parents, 0x0E0, 24, 4, 31), /* CLK_CFG_17 */ - MUX_GATE(CLK_TOP_ADSP, adsp_parents, 0x0EC, 0, 4, 7), - MUX_GATE(CLK_TOP_AUDIO_LOCAL_BUS, audio_local_bus_parents, 0x0EC, 8, 4, 15), - MUX_GATE(CLK_TOP_ASM_H, asm_h_parents, 0x0EC, 16, 4, 23), - MUX_GATE(CLK_TOP_ASM_L, asm_l_parents, 0x0EC, 24, 4, 31), + MUX_GATE_MIXED(CLK_TOP_ADSP, adsp_parents, 0x0EC, 0, 4, 7), + MUX_GATE_MIXED(CLK_TOP_AUDIO_LOCAL_BUS, audio_local_bus_parents, 0x0EC, 8, 4, 15), + MUX_GATE_MIXED(CLK_TOP_ASM_H, asm_h_parents, 0x0EC, 16, 4, 23), + MUX_GATE_MIXED(CLK_TOP_ASM_L, asm_l_parents, 0x0EC, 24, 4, 31), /* CLK_CFG_18 */ - MUX_GATE(CLK_TOP_APLL1, apll1_parents, 0x0F8, 0, 4, 7), - MUX_GATE(CLK_TOP_APLL2, apll2_parents, 0x0F8, 8, 4, 15), - MUX_GATE(CLK_TOP_APLL3, apll3_parents, 0x0F8, 16, 4, 23), - MUX_GATE(CLK_TOP_APLL4, apll4_parents, 0x0F8, 24, 4, 31), + MUX_GATE_MIXED(CLK_TOP_APLL1, apll1_parents, 0x0F8, 0, 4, 7), + MUX_GATE_MIXED(CLK_TOP_APLL2, apll2_parents, 0x0F8, 8, 4, 15), + MUX_GATE_MIXED(CLK_TOP_APLL3, apll3_parents, 0x0F8, 16, 4, 23), + MUX_GATE_MIXED(CLK_TOP_APLL4, apll4_parents, 0x0F8, 24, 4, 31), /* CLK_CFG_19 */ - MUX_GATE(CLK_TOP_APLL5, apll5_parents, 0x0104, 0, 4, 7), - MUX_GATE(CLK_TOP_I2SO1, i2so1_parents, 0x0104, 8, 4, 15), - MUX_GATE(CLK_TOP_I2SO2, i2so2_parents, 0x0104, 16, 4, 23), - MUX_GATE(CLK_TOP_I2SI1, i2si1_parents, 0x0104, 24, 4, 31), + MUX_GATE_MIXED(CLK_TOP_APLL5, apll5_parents, 0x0104, 0, 4, 7), + MUX_GATE_MIXED(CLK_TOP_I2SO1, i2so1_parents, 0x0104, 8, 4, 15), + MUX_GATE_MIXED(CLK_TOP_I2SO2, i2so2_parents, 0x0104, 16, 4, 23), + MUX_GATE_MIXED(CLK_TOP_I2SI1, i2si1_parents, 0x0104, 24, 4, 31), /* CLK_CFG_20 */ - MUX_GATE(CLK_TOP_I2SI2, i2si2_parents, 0x0110, 0, 4, 7), - MUX_GATE(CLK_TOP_DPTX, dptx_parents, 0x0110, 8, 4, 15), - MUX_GATE(CLK_TOP_AUD_IEC, aud_iec_parents, 0x0110, 16, 4, 23), - MUX_GATE(CLK_TOP_A1SYS_HP, a1sys_hp_parents, 0x0110, 24, 4, 31), + MUX_GATE_MIXED(CLK_TOP_I2SI2, i2si2_parents, 0x0110, 0, 4, 7), + MUX_GATE_MIXED(CLK_TOP_DPTX, dptx_parents, 0x0110, 8, 4, 15), + MUX_GATE_MIXED(CLK_TOP_AUD_IEC, aud_iec_parents, 0x0110, 16, 4, 23), + MUX_GATE_MIXED(CLK_TOP_A1SYS_HP, a1sys_hp_parents, 0x0110, 24, 4, 31), /* CLK_CFG_21 */ - MUX_GATE(CLK_TOP_A2SYS, a2sys_parents, 0x011C, 0, 4, 7), - MUX_GATE(CLK_TOP_A3SYS, a3sys_parents, 0x011C, 8, 4, 15), - MUX_GATE(CLK_TOP_A4SYS, a4sys_parents, 0x011C, 16, 4, 23), - MUX_GATE(CLK_TOP_ECC, ecc_parents, 0x011C, 24, 4, 31), + MUX_GATE_MIXED(CLK_TOP_A2SYS, a2sys_parents, 0x011C, 0, 4, 7), + MUX_GATE_MIXED(CLK_TOP_A3SYS, a3sys_parents, 0x011C, 8, 4, 15), + MUX_GATE_MIXED(CLK_TOP_A4SYS, a4sys_parents, 0x011C, 16, 4, 23), + MUX_GATE_MIXED(CLK_TOP_ECC, ecc_parents, 0x011C, 24, 4, 31), /* CLK_CFG_22 */ - MUX_GATE(CLK_TOP_SPINOR, spinor_parents, 0x0128, 0, 4, 7), - MUX_GATE(CLK_TOP_ULPOSC, ulposc_parents, 0x0128, 8, 4, 15), - MUX_GATE(CLK_TOP_SRCK, srck_parents, 0x0128, 16, 4, 23), + MUX_GATE_MIXED(CLK_TOP_SPINOR, spinor_parents, 0x0128, 0, 4, 7), + MUX_GATE_MIXED(CLK_TOP_ULPOSC, ulposc_parents, 0x0128, 8, 4, 15), + MUX_GATE_MIXED(CLK_TOP_SRCK, srck_parents, 0x0128, 16, 4, 23), }; static const int mt8188_id_top_offs_map[] = { -- cgit v1.3.1 From 3c46c551fa1b6c027fde3dd690b72136e38917d3 Mon Sep 17 00:00:00 2001 From: David Lechner Date: Tue, 17 Mar 2026 18:23:22 -0500 Subject: clk: mediatek: mt8195: convert to struct mtk_parent Convert all parent clock arrays to use struct mtk_parent. This will allow us to simplify core code later by having only one possible data type for mux parent arrays. Reviewed-by: Macpaul Lin Reviewed-by: Julien Stephan Link: https://patch.msgid.link/20260317-clk-mtk-unify-mux-parents-v3-9-a4760f5b0a80@baylibre.com Signed-off-by: David Lechner --- drivers/clk/mediatek/clk-mt8195.c | 1579 ++++++++++++++++++------------------- 1 file changed, 789 insertions(+), 790 deletions(-) diff --git a/drivers/clk/mediatek/clk-mt8195.c b/drivers/clk/mediatek/clk-mt8195.c index d9d63601cc4..c709d61af94 100644 --- a/drivers/clk/mediatek/clk-mt8195.c +++ b/drivers/clk/mediatek/clk-mt8195.c @@ -232,890 +232,889 @@ static const struct mtk_fixed_factor top_fixed_divs[] = { FACTOR0(CLK_TOP_HDMIRX_APLL, CLK_APMIXED_HDMIRX_APLL, 1, 1), }; -static const int axi_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_MAINPLL_D4_D4, - CLK_TOP_MAINPLL_D7_D2, - CLK_TOP_MAINPLL_D4_D2, - CLK_TOP_MAINPLL_D5_D2, - CLK_TOP_MAINPLL_D6_D2, - CLK_TOP_ULPOSC1_D4 -}; - -static const int spm_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_ULPOSC1_D10, - CLK_TOP_MAINPLL_D7_D4, - CLK_TOP_CLK32K -}; - -static const int scp_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_UNIVPLL_D4, - CLK_TOP_MAINPLL_D6, - CLK_TOP_UNIVPLL_D6, - CLK_TOP_UNIVPLL_D4_D2, - CLK_TOP_MAINPLL_D4_D2, - CLK_TOP_MAINPLL_D4, - CLK_TOP_MAINPLL_D6_D2 -}; - -static const int bus_aximem_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_MAINPLL_D7_D2, - CLK_TOP_MAINPLL_D4_D2, - CLK_TOP_MAINPLL_D5_D2, - CLK_TOP_MAINPLL_D6 -}; - -static const int vpp_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_UNIVPLL_D6_D2, - CLK_TOP_MAINPLL_D5_D2, - CLK_TOP_MMPLL_D6_D2, - CLK_TOP_UNIVPLL_D5_D2, - CLK_TOP_UNIVPLL_D4_D2, - CLK_TOP_MMPLL_D4_D2, - CLK_TOP_MMPLL_D7, - CLK_TOP_UNIVPLL_D6, - CLK_TOP_MAINPLL_D4, - CLK_TOP_MMPLL_D5, - CLK_TOP_TVDPLL1, - CLK_TOP_TVDPLL2, - CLK_TOP_UNIVPLL_D4, - CLK_TOP_MMPLL_D4 -}; - -static const int ethdr_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_UNIVPLL_D6_D2, - CLK_TOP_MAINPLL_D5_D2, - CLK_TOP_MMPLL_D6_D2, - CLK_TOP_UNIVPLL_D5_D2, - CLK_TOP_UNIVPLL_D4_D2, - CLK_TOP_MMPLL_D4_D2, - CLK_TOP_MMPLL_D7, - CLK_TOP_UNIVPLL_D6, - CLK_TOP_MAINPLL_D4, - CLK_TOP_MMPLL_D5_D4, - CLK_TOP_TVDPLL1, - CLK_TOP_TVDPLL2, - CLK_TOP_UNIVPLL_D4, - CLK_TOP_MMPLL_D4 -}; - -static const int ipe_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_IMGPLL, - CLK_TOP_MAINPLL_D4, - CLK_TOP_MMPLL_D6, - CLK_TOP_UNIVPLL_D6, - CLK_TOP_MAINPLL_D6, - CLK_TOP_MMPLL_D4_D2, - CLK_TOP_UNIVPLL_D4_D2, - CLK_TOP_MAINPLL_D4_D2, - CLK_TOP_MMPLL_D6_D2, - CLK_TOP_UNIVPLL_D5_D2 -}; - -static const int cam_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_MAINPLL_D4, - CLK_TOP_MMPLL_D4, - CLK_TOP_UNIVPLL_D4, - CLK_TOP_UNIVPLL_D5, - CLK_TOP_UNIVPLL_D6, - CLK_TOP_MMPLL_D7, - CLK_TOP_UNIVPLL_D4_D2, - CLK_TOP_MAINPLL_D4_D2, - CLK_TOP_IMGPLL -}; - -static const int ccu_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_UNIVPLL_D6, - CLK_TOP_MAINPLL_D4_D2, - CLK_TOP_MAINPLL_D4, - CLK_TOP_UNIVPLL_D5, - CLK_TOP_MAINPLL_D6, - CLK_TOP_MMPLL_D6, - CLK_TOP_MMPLL_D7, - CLK_TOP_UNIVPLL_D4_D2, - CLK_TOP_UNIVPLL_D7 -}; - -static const int img_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_IMGPLL, - CLK_TOP_UNIVPLL_D4, - CLK_TOP_MAINPLL_D4, - CLK_TOP_UNIVPLL_D5, - CLK_TOP_MMPLL_D6, - CLK_TOP_UNIVPLL_D6, - CLK_TOP_MAINPLL_D6, - CLK_TOP_MMPLL_D4_D2, - CLK_TOP_UNIVPLL_D4_D2, - CLK_TOP_MAINPLL_D4_D2, - CLK_TOP_UNIVPLL_D5_D2 -}; - -static const int camtm_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_UNIVPLL_D4_D4, - CLK_TOP_UNIVPLL_D6_D2, - CLK_TOP_UNIVPLL_D6_D4 -}; - -static const int dsp_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_UNIVPLL_D6_D2, - CLK_TOP_UNIVPLL_D4_D2, - CLK_TOP_UNIVPLL_D5, - CLK_TOP_UNIVPLL_D4, - CLK_TOP_MMPLL_D4, - CLK_TOP_MAINPLL_D3, - CLK_TOP_UNIVPLL_D3 -}; - -static const int dsp1_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_UNIVPLL_D6_D2, - CLK_TOP_MAINPLL_D4_D2, - CLK_TOP_UNIVPLL_D5, - CLK_TOP_MMPLL_D5, - CLK_TOP_UNIVPLL_D4, - CLK_TOP_MAINPLL_D3, - CLK_TOP_UNIVPLL_D3 -}; - -static const int dsp2_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_UNIVPLL_D6_D2, - CLK_TOP_UNIVPLL_D4_D2, - CLK_TOP_MAINPLL_D4, - CLK_TOP_UNIVPLL_D4, - CLK_TOP_MMPLL_D4, - CLK_TOP_MAINPLL_D3, - CLK_TOP_UNIVPLL_D3 -}; - -static const int ipu_if_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_UNIVPLL_D6_D2, - CLK_TOP_UNIVPLL_D5_D2, - CLK_TOP_MAINPLL_D4_D2, - CLK_TOP_MAINPLL_D6, - CLK_TOP_UNIVPLL_D5, - CLK_TOP_UNIVPLL_D4, - CLK_TOP_MMPLL_D4 -}; - -static const int mfg_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_MAINPLL_D5_D2, - CLK_TOP_UNIVPLL_D6, - CLK_TOP_UNIVPLL_D7 -}; - -static const int camtg_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_UNIVPLL_192M_D8, - CLK_TOP_UNIVPLL_D6_D8, - CLK_TOP_UNIVPLL_192M_D4, - CLK_TOP_UNIVPLL_D6_D16, - CLK_TOP_CLK26M_D2, - CLK_TOP_UNIVPLL_192M_D16, - CLK_TOP_UNIVPLL_192M_D32 -}; - -static const int uart_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_UNIVPLL_D6_D8 -}; - -static const int spi_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_MAINPLL_D5_D4, - CLK_TOP_MAINPLL_D6_D4, - CLK_TOP_MSDCPLL_D4, - CLK_TOP_UNIVPLL_D6_D2, - CLK_TOP_MAINPLL_D6_D2, - CLK_TOP_MAINPLL_D4_D4, - CLK_TOP_UNIVPLL_D5_D4 -}; - -static const int spis_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_UNIVPLL_D6, - CLK_TOP_MAINPLL_D6, - CLK_TOP_UNIVPLL_D4_D2, - CLK_TOP_UNIVPLL_D6_D2, - CLK_TOP_UNIVPLL_D4_D4, - CLK_TOP_UNIVPLL_D6_D4, - CLK_TOP_MAINPLL_D7_D4 -}; - -static const int msdc50_0_h_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_MAINPLL_D4_D2, - CLK_TOP_MAINPLL_D6_D2 -}; - -static const int msdc50_0_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_MSDCPLL, - CLK_TOP_MSDCPLL_D2, - CLK_TOP_UNIVPLL_D4_D4, - CLK_TOP_MAINPLL_D6_D2, - CLK_TOP_UNIVPLL_D4_D2 -}; - -static const int msdc30_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_UNIVPLL_D6_D2, - CLK_TOP_MAINPLL_D6_D2, - CLK_TOP_MAINPLL_D7_D2, - CLK_TOP_MSDCPLL_D2 -}; - -static const int intdir_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_UNIVPLL_D6, - CLK_TOP_MAINPLL_D4, - CLK_TOP_UNIVPLL_D4 -}; - -static const int aud_intbus_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_MAINPLL_D4_D4, - CLK_TOP_MAINPLL_D7_D4 -}; - -static const int audio_h_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_UNIVPLL_D7, - CLK_TOP_APLL1, - CLK_TOP_APLL2 -}; - -static const int pwrap_ulposc_parents[] = { - CLK_TOP_ULPOSC1_D10, - CLK_TOP_CLK26M, - CLK_TOP_ULPOSC1_D4, - CLK_TOP_ULPOSC1_D7, - CLK_TOP_ULPOSC1_D8, - CLK_TOP_ULPOSC1_D16, - CLK_TOP_MAINPLL_D4_D8, - CLK_TOP_UNIVPLL_D5_D8 -}; - -static const int atb_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_MAINPLL_D4_D2, - CLK_TOP_MAINPLL_D5_D2 -}; +static const struct mtk_parent axi_parents[] = { + TOP_PARENT(CLK_TOP_CLK26M), + TOP_PARENT(CLK_TOP_MAINPLL_D4_D4), + TOP_PARENT(CLK_TOP_MAINPLL_D7_D2), + TOP_PARENT(CLK_TOP_MAINPLL_D4_D2), + TOP_PARENT(CLK_TOP_MAINPLL_D5_D2), + TOP_PARENT(CLK_TOP_MAINPLL_D6_D2), + TOP_PARENT(CLK_TOP_ULPOSC1_D4), +}; + +static const struct mtk_parent spm_parents[] = { + TOP_PARENT(CLK_TOP_CLK26M), + TOP_PARENT(CLK_TOP_ULPOSC1_D10), + TOP_PARENT(CLK_TOP_MAINPLL_D7_D4), + TOP_PARENT(CLK_TOP_CLK32K), +}; + +static const struct mtk_parent scp_parents[] = { + TOP_PARENT(CLK_TOP_CLK26M), + TOP_PARENT(CLK_TOP_UNIVPLL_D4), + TOP_PARENT(CLK_TOP_MAINPLL_D6), + TOP_PARENT(CLK_TOP_UNIVPLL_D6), + TOP_PARENT(CLK_TOP_UNIVPLL_D4_D2), + TOP_PARENT(CLK_TOP_MAINPLL_D4_D2), + TOP_PARENT(CLK_TOP_MAINPLL_D4), + TOP_PARENT(CLK_TOP_MAINPLL_D6_D2), +}; + +static const struct mtk_parent bus_aximem_parents[] = { + TOP_PARENT(CLK_TOP_CLK26M), + TOP_PARENT(CLK_TOP_MAINPLL_D7_D2), + TOP_PARENT(CLK_TOP_MAINPLL_D4_D2), + TOP_PARENT(CLK_TOP_MAINPLL_D5_D2), + TOP_PARENT(CLK_TOP_MAINPLL_D6), +}; + +static const struct mtk_parent vpp_parents[] = { + TOP_PARENT(CLK_TOP_CLK26M), + TOP_PARENT(CLK_TOP_UNIVPLL_D6_D2), + TOP_PARENT(CLK_TOP_MAINPLL_D5_D2), + TOP_PARENT(CLK_TOP_MMPLL_D6_D2), + TOP_PARENT(CLK_TOP_UNIVPLL_D5_D2), + TOP_PARENT(CLK_TOP_UNIVPLL_D4_D2), + TOP_PARENT(CLK_TOP_MMPLL_D4_D2), + TOP_PARENT(CLK_TOP_MMPLL_D7), + TOP_PARENT(CLK_TOP_UNIVPLL_D6), + TOP_PARENT(CLK_TOP_MAINPLL_D4), + TOP_PARENT(CLK_TOP_MMPLL_D5), + TOP_PARENT(CLK_TOP_TVDPLL1), + TOP_PARENT(CLK_TOP_TVDPLL2), + TOP_PARENT(CLK_TOP_UNIVPLL_D4), + TOP_PARENT(CLK_TOP_MMPLL_D4), +}; + +static const struct mtk_parent ethdr_parents[] = { + TOP_PARENT(CLK_TOP_CLK26M), + TOP_PARENT(CLK_TOP_UNIVPLL_D6_D2), + TOP_PARENT(CLK_TOP_MAINPLL_D5_D2), + TOP_PARENT(CLK_TOP_MMPLL_D6_D2), + TOP_PARENT(CLK_TOP_UNIVPLL_D5_D2), + TOP_PARENT(CLK_TOP_UNIVPLL_D4_D2), + TOP_PARENT(CLK_TOP_MMPLL_D4_D2), + TOP_PARENT(CLK_TOP_MMPLL_D7), + TOP_PARENT(CLK_TOP_UNIVPLL_D6), + TOP_PARENT(CLK_TOP_MAINPLL_D4), + TOP_PARENT(CLK_TOP_MMPLL_D5_D4), + TOP_PARENT(CLK_TOP_TVDPLL1), + TOP_PARENT(CLK_TOP_TVDPLL2), + TOP_PARENT(CLK_TOP_UNIVPLL_D4), + TOP_PARENT(CLK_TOP_MMPLL_D4), +}; + +static const struct mtk_parent ipe_parents[] = { + TOP_PARENT(CLK_TOP_CLK26M), + TOP_PARENT(CLK_TOP_IMGPLL), + TOP_PARENT(CLK_TOP_MAINPLL_D4), + TOP_PARENT(CLK_TOP_MMPLL_D6), + TOP_PARENT(CLK_TOP_UNIVPLL_D6), + TOP_PARENT(CLK_TOP_MAINPLL_D6), + TOP_PARENT(CLK_TOP_MMPLL_D4_D2), + TOP_PARENT(CLK_TOP_UNIVPLL_D4_D2), + TOP_PARENT(CLK_TOP_MAINPLL_D4_D2), + TOP_PARENT(CLK_TOP_MMPLL_D6_D2), + TOP_PARENT(CLK_TOP_UNIVPLL_D5_D2), +}; + +static const struct mtk_parent cam_parents[] = { + TOP_PARENT(CLK_TOP_CLK26M), + TOP_PARENT(CLK_TOP_MAINPLL_D4), + TOP_PARENT(CLK_TOP_MMPLL_D4), + TOP_PARENT(CLK_TOP_UNIVPLL_D4), + TOP_PARENT(CLK_TOP_UNIVPLL_D5), + TOP_PARENT(CLK_TOP_UNIVPLL_D6), + TOP_PARENT(CLK_TOP_MMPLL_D7), + TOP_PARENT(CLK_TOP_UNIVPLL_D4_D2), + TOP_PARENT(CLK_TOP_MAINPLL_D4_D2), + TOP_PARENT(CLK_TOP_IMGPLL), +}; + +static const struct mtk_parent ccu_parents[] = { + TOP_PARENT(CLK_TOP_CLK26M), + TOP_PARENT(CLK_TOP_UNIVPLL_D6), + TOP_PARENT(CLK_TOP_MAINPLL_D4_D2), + TOP_PARENT(CLK_TOP_MAINPLL_D4), + TOP_PARENT(CLK_TOP_UNIVPLL_D5), + TOP_PARENT(CLK_TOP_MAINPLL_D6), + TOP_PARENT(CLK_TOP_MMPLL_D6), + TOP_PARENT(CLK_TOP_MMPLL_D7), + TOP_PARENT(CLK_TOP_UNIVPLL_D4_D2), + TOP_PARENT(CLK_TOP_UNIVPLL_D7), +}; + +static const struct mtk_parent img_parents[] = { + TOP_PARENT(CLK_TOP_CLK26M), + TOP_PARENT(CLK_TOP_IMGPLL), + TOP_PARENT(CLK_TOP_UNIVPLL_D4), + TOP_PARENT(CLK_TOP_MAINPLL_D4), + TOP_PARENT(CLK_TOP_UNIVPLL_D5), + TOP_PARENT(CLK_TOP_MMPLL_D6), + TOP_PARENT(CLK_TOP_UNIVPLL_D6), + TOP_PARENT(CLK_TOP_MAINPLL_D6), + TOP_PARENT(CLK_TOP_MMPLL_D4_D2), + TOP_PARENT(CLK_TOP_UNIVPLL_D4_D2), + TOP_PARENT(CLK_TOP_MAINPLL_D4_D2), + TOP_PARENT(CLK_TOP_UNIVPLL_D5_D2), +}; + +static const struct mtk_parent camtm_parents[] = { + TOP_PARENT(CLK_TOP_CLK26M), + TOP_PARENT(CLK_TOP_UNIVPLL_D4_D4), + TOP_PARENT(CLK_TOP_UNIVPLL_D6_D2), + TOP_PARENT(CLK_TOP_UNIVPLL_D6_D4), +}; + +static const struct mtk_parent dsp_parents[] = { + TOP_PARENT(CLK_TOP_CLK26M), + TOP_PARENT(CLK_TOP_UNIVPLL_D6_D2), + TOP_PARENT(CLK_TOP_UNIVPLL_D4_D2), + TOP_PARENT(CLK_TOP_UNIVPLL_D5), + TOP_PARENT(CLK_TOP_UNIVPLL_D4), + TOP_PARENT(CLK_TOP_MMPLL_D4), + TOP_PARENT(CLK_TOP_MAINPLL_D3), + TOP_PARENT(CLK_TOP_UNIVPLL_D3), +}; + +static const struct mtk_parent dsp1_parents[] = { + TOP_PARENT(CLK_TOP_CLK26M), + TOP_PARENT(CLK_TOP_UNIVPLL_D6_D2), + TOP_PARENT(CLK_TOP_MAINPLL_D4_D2), + TOP_PARENT(CLK_TOP_UNIVPLL_D5), + TOP_PARENT(CLK_TOP_MMPLL_D5), + TOP_PARENT(CLK_TOP_UNIVPLL_D4), + TOP_PARENT(CLK_TOP_MAINPLL_D3), + TOP_PARENT(CLK_TOP_UNIVPLL_D3), +}; + +static const struct mtk_parent dsp2_parents[] = { + TOP_PARENT(CLK_TOP_CLK26M), + TOP_PARENT(CLK_TOP_UNIVPLL_D6_D2), + TOP_PARENT(CLK_TOP_UNIVPLL_D4_D2), + TOP_PARENT(CLK_TOP_MAINPLL_D4), + TOP_PARENT(CLK_TOP_UNIVPLL_D4), + TOP_PARENT(CLK_TOP_MMPLL_D4), + TOP_PARENT(CLK_TOP_MAINPLL_D3), + TOP_PARENT(CLK_TOP_UNIVPLL_D3), +}; + +static const struct mtk_parent ipu_if_parents[] = { + TOP_PARENT(CLK_TOP_CLK26M), + TOP_PARENT(CLK_TOP_UNIVPLL_D6_D2), + TOP_PARENT(CLK_TOP_UNIVPLL_D5_D2), + TOP_PARENT(CLK_TOP_MAINPLL_D4_D2), + TOP_PARENT(CLK_TOP_MAINPLL_D6), + TOP_PARENT(CLK_TOP_UNIVPLL_D5), + TOP_PARENT(CLK_TOP_UNIVPLL_D4), + TOP_PARENT(CLK_TOP_MMPLL_D4), +}; + +static const struct mtk_parent mfg_parents[] = { + TOP_PARENT(CLK_TOP_CLK26M), + TOP_PARENT(CLK_TOP_MAINPLL_D5_D2), + TOP_PARENT(CLK_TOP_UNIVPLL_D6), + TOP_PARENT(CLK_TOP_UNIVPLL_D7), +}; + +static const struct mtk_parent camtg_parents[] = { + TOP_PARENT(CLK_TOP_CLK26M), + TOP_PARENT(CLK_TOP_UNIVPLL_192M_D8), + TOP_PARENT(CLK_TOP_UNIVPLL_D6_D8), + TOP_PARENT(CLK_TOP_UNIVPLL_192M_D4), + TOP_PARENT(CLK_TOP_UNIVPLL_D6_D16), + TOP_PARENT(CLK_TOP_CLK26M_D2), + TOP_PARENT(CLK_TOP_UNIVPLL_192M_D16), + TOP_PARENT(CLK_TOP_UNIVPLL_192M_D32), +}; + +static const struct mtk_parent uart_parents[] = { + TOP_PARENT(CLK_TOP_CLK26M), + TOP_PARENT(CLK_TOP_UNIVPLL_D6_D8), +}; + +static const struct mtk_parent spi_parents[] = { + TOP_PARENT(CLK_TOP_CLK26M), + TOP_PARENT(CLK_TOP_MAINPLL_D5_D4), + TOP_PARENT(CLK_TOP_MAINPLL_D6_D4), + TOP_PARENT(CLK_TOP_MSDCPLL_D4), + TOP_PARENT(CLK_TOP_UNIVPLL_D6_D2), + TOP_PARENT(CLK_TOP_MAINPLL_D6_D2), + TOP_PARENT(CLK_TOP_MAINPLL_D4_D4), + TOP_PARENT(CLK_TOP_UNIVPLL_D5_D4), +}; + +static const struct mtk_parent spis_parents[] = { + TOP_PARENT(CLK_TOP_CLK26M), + TOP_PARENT(CLK_TOP_UNIVPLL_D6), + TOP_PARENT(CLK_TOP_MAINPLL_D6), + TOP_PARENT(CLK_TOP_UNIVPLL_D4_D2), + TOP_PARENT(CLK_TOP_UNIVPLL_D6_D2), + TOP_PARENT(CLK_TOP_UNIVPLL_D4_D4), + TOP_PARENT(CLK_TOP_UNIVPLL_D6_D4), + TOP_PARENT(CLK_TOP_MAINPLL_D7_D4), +}; + +static const struct mtk_parent msdc50_0_h_parents[] = { + TOP_PARENT(CLK_TOP_CLK26M), + TOP_PARENT(CLK_TOP_MAINPLL_D4_D2), + TOP_PARENT(CLK_TOP_MAINPLL_D6_D2), +}; + +static const struct mtk_parent msdc50_0_parents[] = { + TOP_PARENT(CLK_TOP_CLK26M), + TOP_PARENT(CLK_TOP_MSDCPLL), + TOP_PARENT(CLK_TOP_MSDCPLL_D2), + TOP_PARENT(CLK_TOP_UNIVPLL_D4_D4), + TOP_PARENT(CLK_TOP_MAINPLL_D6_D2), + TOP_PARENT(CLK_TOP_UNIVPLL_D4_D2), +}; + +static const struct mtk_parent msdc30_parents[] = { + TOP_PARENT(CLK_TOP_CLK26M), + TOP_PARENT(CLK_TOP_UNIVPLL_D6_D2), + TOP_PARENT(CLK_TOP_MAINPLL_D6_D2), + TOP_PARENT(CLK_TOP_MAINPLL_D7_D2), + TOP_PARENT(CLK_TOP_MSDCPLL_D2), +}; + +static const struct mtk_parent intdir_parents[] = { + TOP_PARENT(CLK_TOP_CLK26M), + TOP_PARENT(CLK_TOP_UNIVPLL_D6), + TOP_PARENT(CLK_TOP_MAINPLL_D4), + TOP_PARENT(CLK_TOP_UNIVPLL_D4), +}; + +static const struct mtk_parent aud_intbus_parents[] = { + TOP_PARENT(CLK_TOP_CLK26M), + TOP_PARENT(CLK_TOP_MAINPLL_D4_D4), + TOP_PARENT(CLK_TOP_MAINPLL_D7_D4), +}; + +static const struct mtk_parent audio_h_parents[] = { + TOP_PARENT(CLK_TOP_CLK26M), + TOP_PARENT(CLK_TOP_UNIVPLL_D7), + TOP_PARENT(CLK_TOP_APLL1), + TOP_PARENT(CLK_TOP_APLL2), +}; + +static const struct mtk_parent pwrap_ulposc_parents[] = { + TOP_PARENT(CLK_TOP_ULPOSC1_D10), + TOP_PARENT(CLK_TOP_CLK26M), + TOP_PARENT(CLK_TOP_ULPOSC1_D4), + TOP_PARENT(CLK_TOP_ULPOSC1_D7), + TOP_PARENT(CLK_TOP_ULPOSC1_D8), + TOP_PARENT(CLK_TOP_ULPOSC1_D16), + TOP_PARENT(CLK_TOP_MAINPLL_D4_D8), + TOP_PARENT(CLK_TOP_UNIVPLL_D5_D8), +}; + +static const struct mtk_parent atb_parents[] = { + TOP_PARENT(CLK_TOP_CLK26M), + TOP_PARENT(CLK_TOP_MAINPLL_D4_D2), + TOP_PARENT(CLK_TOP_MAINPLL_D5_D2), +}; -static const int pwrmcu_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_MAINPLL_D7_D2, - CLK_TOP_MAINPLL_D6_D2, - CLK_TOP_MAINPLL_D5_D2, - CLK_TOP_MAINPLL_D9, - CLK_TOP_MAINPLL_D4_D2 +static const struct mtk_parent pwrmcu_parents[] = { + TOP_PARENT(CLK_TOP_CLK26M), + TOP_PARENT(CLK_TOP_MAINPLL_D7_D2), + TOP_PARENT(CLK_TOP_MAINPLL_D6_D2), + TOP_PARENT(CLK_TOP_MAINPLL_D5_D2), + TOP_PARENT(CLK_TOP_MAINPLL_D9), + TOP_PARENT(CLK_TOP_MAINPLL_D4_D2), }; -static const int dp_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_TVDPLL1_D2, - CLK_TOP_TVDPLL2_D2, - CLK_TOP_TVDPLL1_D4, - CLK_TOP_TVDPLL2_D4, - CLK_TOP_TVDPLL1_D8, - CLK_TOP_TVDPLL2_D8, - CLK_TOP_TVDPLL1_D16, - CLK_TOP_TVDPLL2_D16 -}; - -static const int disp_pwm_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_UNIVPLL_D6_D4, - CLK_TOP_ULPOSC1_D2, - CLK_TOP_ULPOSC1_D4, - CLK_TOP_ULPOSC1_D16 -}; - -static const int usb_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_UNIVPLL_D5_D4, - CLK_TOP_UNIVPLL_D6_D4, - CLK_TOP_UNIVPLL_D5_D2 -}; - -static const int i2c_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_MAINPLL_D4_D8, - CLK_TOP_UNIVPLL_D5_D4 -}; - -static const int seninf_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_UNIVPLL_D4_D4, - CLK_TOP_UNIVPLL_D6_D2, - CLK_TOP_UNIVPLL_D4_D2, - CLK_TOP_UNIVPLL_D7, - CLK_TOP_UNIVPLL_D6, - CLK_TOP_MMPLL_D6, - CLK_TOP_UNIVPLL_D5 -}; - -static const int gcpu_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_MAINPLL_D6, - CLK_TOP_UNIVPLL_D4_D2, - CLK_TOP_MMPLL_D5_D2, - CLK_TOP_UNIVPLL_D5_D2 -}; - -static const int dxcc_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_MAINPLL_D4_D2, - CLK_TOP_MAINPLL_D4_D4, - CLK_TOP_MAINPLL_D4_D8 -}; - -static const int dpmaif_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_UNIVPLL_D4_D4, - CLK_TOP_MAINPLL_D6, - CLK_TOP_MAINPLL_D4_D2, - CLK_TOP_UNIVPLL_D4_D2 -}; - -static const int aes_fde_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_MAINPLL_D4_D2, - CLK_TOP_MAINPLL_D6, - CLK_TOP_MAINPLL_D4_D4, - CLK_TOP_UNIVPLL_D4_D2, - CLK_TOP_UNIVPLL_D6 -}; - -static const int ufs_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_MAINPLL_D4_D4, - CLK_TOP_MAINPLL_D4_D8, - CLK_TOP_UNIVPLL_D4_D4, - CLK_TOP_MAINPLL_D6_D2, - CLK_TOP_UNIVPLL_D6_D2, - CLK_TOP_MSDCPLL_D2 -}; - -static const int ufs_tick1us_parents[] = { - CLK_TOP_CLK26M_D52, - CLK_TOP_CLK26M -}; - -static const int ufs_mp_sap_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_MSDCPLL_D16 -}; - -static const int venc_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_MMPLL_D4_D2, - CLK_TOP_MAINPLL_D6, - CLK_TOP_UNIVPLL_D4_D2, - CLK_TOP_MAINPLL_D4_D2, - CLK_TOP_UNIVPLL_D6, - CLK_TOP_MMPLL_D6, - CLK_TOP_MAINPLL_D5_D2, - CLK_TOP_MAINPLL_D6_D2, - CLK_TOP_MMPLL_D9, - CLK_TOP_UNIVPLL_D4_D4, - CLK_TOP_MAINPLL_D4, - CLK_TOP_UNIVPLL_D4, - CLK_TOP_UNIVPLL_D5, - CLK_TOP_UNIVPLL_D5_D2, - CLK_TOP_MAINPLL_D5 -}; - -static const int vdec_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_MAINPLL_D5_D2, - CLK_TOP_MMPLL_D6_D2, - CLK_TOP_UNIVPLL_D4_D2, - CLK_TOP_MMPLL_D4_D2, - CLK_TOP_MAINPLL_D5, - CLK_TOP_MMPLL_D6, - CLK_TOP_MMPLL_D5, - CLK_TOP_VDECPLL, - CLK_TOP_UNIVPLL_D4, - CLK_TOP_MMPLL_D4, - CLK_TOP_UNIVPLL_D6_D2, - CLK_TOP_MMPLL_D9, - CLK_TOP_UNIVPLL_D6, - CLK_TOP_UNIVPLL_D5, - CLK_TOP_MAINPLL_D4 -}; - -static const int pwm_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_UNIVPLL_D4_D8 -}; - -static const int mcupm_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_MAINPLL_D6_D2, - CLK_TOP_MAINPLL_D7_D4, -}; - -static const int spmi_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_CLK26M_D2, - CLK_TOP_ULPOSC1_D8, - CLK_TOP_ULPOSC1_D10, - CLK_TOP_ULPOSC1_D16, - CLK_TOP_ULPOSC1_D7, - CLK_TOP_CLK32K, - CLK_TOP_MAINPLL_D7_D8, - CLK_TOP_MAINPLL_D6_D8, - CLK_TOP_MAINPLL_D5_D8 -}; - -static const int dvfsrc_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_ULPOSC1_D10, - CLK_TOP_UNIVPLL_D6_D8, - CLK_TOP_MSDCPLL_D16 -}; - -static const int tl_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_UNIVPLL_D5_D4, - CLK_TOP_MAINPLL_D4_D4 -}; - -static const int dsi_occ_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_MAINPLL_D6_D2, - CLK_TOP_UNIVPLL_D5_D2, - CLK_TOP_UNIVPLL_D4_D2 -}; - -static const int wpe_vpp_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_MAINPLL_D5_D2, - CLK_TOP_MMPLL_D6_D2, - CLK_TOP_UNIVPLL_D5_D2, - CLK_TOP_MAINPLL_D4_D2, - CLK_TOP_UNIVPLL_D4_D2, - CLK_TOP_MMPLL_D4_D2, - CLK_TOP_MAINPLL_D6, - CLK_TOP_MMPLL_D7, - CLK_TOP_UNIVPLL_D6, - CLK_TOP_MAINPLL_D5, - CLK_TOP_UNIVPLL_D5, - CLK_TOP_MAINPLL_D4, - CLK_TOP_TVDPLL1, - CLK_TOP_UNIVPLL_D4 -}; - -static const int hdcp_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_UNIVPLL_D4_D8, - CLK_TOP_MAINPLL_D5_D8, - CLK_TOP_UNIVPLL_D6_D4 -}; - -static const int hdcp_24m_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_UNIVPLL_192M_D4, - CLK_TOP_UNIVPLL_192M_D8, - CLK_TOP_UNIVPLL_D6_D8 -}; - -static const int hd20_dacr_ref_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_UNIVPLL_D4_D2, - CLK_TOP_UNIVPLL_D4_D4, - CLK_TOP_UNIVPLL_D4_D8 -}; - -static const int hd20_hdcp_c_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_MSDCPLL_D4, - CLK_TOP_UNIVPLL_D4_D8, - CLK_TOP_UNIVPLL_D6_D8 +static const struct mtk_parent dp_parents[] = { + TOP_PARENT(CLK_TOP_CLK26M), + TOP_PARENT(CLK_TOP_TVDPLL1_D2), + TOP_PARENT(CLK_TOP_TVDPLL2_D2), + TOP_PARENT(CLK_TOP_TVDPLL1_D4), + TOP_PARENT(CLK_TOP_TVDPLL2_D4), + TOP_PARENT(CLK_TOP_TVDPLL1_D8), + TOP_PARENT(CLK_TOP_TVDPLL2_D8), + TOP_PARENT(CLK_TOP_TVDPLL1_D16), + TOP_PARENT(CLK_TOP_TVDPLL2_D16), +}; + +static const struct mtk_parent disp_pwm_parents[] = { + TOP_PARENT(CLK_TOP_CLK26M), + TOP_PARENT(CLK_TOP_UNIVPLL_D6_D4), + TOP_PARENT(CLK_TOP_ULPOSC1_D2), + TOP_PARENT(CLK_TOP_ULPOSC1_D4), + TOP_PARENT(CLK_TOP_ULPOSC1_D16), +}; + +static const struct mtk_parent usb_parents[] = { + TOP_PARENT(CLK_TOP_CLK26M), + TOP_PARENT(CLK_TOP_UNIVPLL_D5_D4), + TOP_PARENT(CLK_TOP_UNIVPLL_D6_D4), + TOP_PARENT(CLK_TOP_UNIVPLL_D5_D2), +}; + +static const struct mtk_parent i2c_parents[] = { + TOP_PARENT(CLK_TOP_CLK26M), + TOP_PARENT(CLK_TOP_MAINPLL_D4_D8), + TOP_PARENT(CLK_TOP_UNIVPLL_D5_D4), +}; + +static const struct mtk_parent seninf_parents[] = { + TOP_PARENT(CLK_TOP_CLK26M), + TOP_PARENT(CLK_TOP_UNIVPLL_D4_D4), + TOP_PARENT(CLK_TOP_UNIVPLL_D6_D2), + TOP_PARENT(CLK_TOP_UNIVPLL_D4_D2), + TOP_PARENT(CLK_TOP_UNIVPLL_D7), + TOP_PARENT(CLK_TOP_UNIVPLL_D6), + TOP_PARENT(CLK_TOP_MMPLL_D6), + TOP_PARENT(CLK_TOP_UNIVPLL_D5), +}; + +static const struct mtk_parent gcpu_parents[] = { + TOP_PARENT(CLK_TOP_CLK26M), + TOP_PARENT(CLK_TOP_MAINPLL_D6), + TOP_PARENT(CLK_TOP_UNIVPLL_D4_D2), + TOP_PARENT(CLK_TOP_MMPLL_D5_D2), + TOP_PARENT(CLK_TOP_UNIVPLL_D5_D2), +}; + +static const struct mtk_parent dxcc_parents[] = { + TOP_PARENT(CLK_TOP_CLK26M), + TOP_PARENT(CLK_TOP_MAINPLL_D4_D2), + TOP_PARENT(CLK_TOP_MAINPLL_D4_D4), + TOP_PARENT(CLK_TOP_MAINPLL_D4_D8), +}; + +static const struct mtk_parent dpmaif_parents[] = { + TOP_PARENT(CLK_TOP_CLK26M), + TOP_PARENT(CLK_TOP_UNIVPLL_D4_D4), + TOP_PARENT(CLK_TOP_MAINPLL_D6), + TOP_PARENT(CLK_TOP_MAINPLL_D4_D2), + TOP_PARENT(CLK_TOP_UNIVPLL_D4_D2), +}; + +static const struct mtk_parent aes_fde_parents[] = { + TOP_PARENT(CLK_TOP_CLK26M), + TOP_PARENT(CLK_TOP_MAINPLL_D4_D2), + TOP_PARENT(CLK_TOP_MAINPLL_D6), + TOP_PARENT(CLK_TOP_MAINPLL_D4_D4), + TOP_PARENT(CLK_TOP_UNIVPLL_D4_D2), + TOP_PARENT(CLK_TOP_UNIVPLL_D6), +}; + +static const struct mtk_parent ufs_parents[] = { + TOP_PARENT(CLK_TOP_CLK26M), + TOP_PARENT(CLK_TOP_MAINPLL_D4_D4), + TOP_PARENT(CLK_TOP_MAINPLL_D4_D8), + TOP_PARENT(CLK_TOP_UNIVPLL_D4_D4), + TOP_PARENT(CLK_TOP_MAINPLL_D6_D2), + TOP_PARENT(CLK_TOP_UNIVPLL_D6_D2), + TOP_PARENT(CLK_TOP_MSDCPLL_D2), +}; + +static const struct mtk_parent ufs_tick1us_parents[] = { + TOP_PARENT(CLK_TOP_CLK26M_D52), + TOP_PARENT(CLK_TOP_CLK26M), +}; + +static const struct mtk_parent ufs_mp_sap_parents[] = { + TOP_PARENT(CLK_TOP_CLK26M), + TOP_PARENT(CLK_TOP_MSDCPLL_D16), +}; + +static const struct mtk_parent venc_parents[] = { + TOP_PARENT(CLK_TOP_CLK26M), + TOP_PARENT(CLK_TOP_MMPLL_D4_D2), + TOP_PARENT(CLK_TOP_MAINPLL_D6), + TOP_PARENT(CLK_TOP_UNIVPLL_D4_D2), + TOP_PARENT(CLK_TOP_MAINPLL_D4_D2), + TOP_PARENT(CLK_TOP_UNIVPLL_D6), + TOP_PARENT(CLK_TOP_MMPLL_D6), + TOP_PARENT(CLK_TOP_MAINPLL_D5_D2), + TOP_PARENT(CLK_TOP_MAINPLL_D6_D2), + TOP_PARENT(CLK_TOP_MMPLL_D9), + TOP_PARENT(CLK_TOP_UNIVPLL_D4_D4), + TOP_PARENT(CLK_TOP_MAINPLL_D4), + TOP_PARENT(CLK_TOP_UNIVPLL_D4), + TOP_PARENT(CLK_TOP_UNIVPLL_D5), + TOP_PARENT(CLK_TOP_UNIVPLL_D5_D2), + TOP_PARENT(CLK_TOP_MAINPLL_D5), +}; + +static const struct mtk_parent vdec_parents[] = { + TOP_PARENT(CLK_TOP_CLK26M), + TOP_PARENT(CLK_TOP_MAINPLL_D5_D2), + TOP_PARENT(CLK_TOP_MMPLL_D6_D2), + TOP_PARENT(CLK_TOP_UNIVPLL_D4_D2), + TOP_PARENT(CLK_TOP_MMPLL_D4_D2), + TOP_PARENT(CLK_TOP_MAINPLL_D5), + TOP_PARENT(CLK_TOP_MMPLL_D6), + TOP_PARENT(CLK_TOP_MMPLL_D5), + TOP_PARENT(CLK_TOP_VDECPLL), + TOP_PARENT(CLK_TOP_UNIVPLL_D4), + TOP_PARENT(CLK_TOP_MMPLL_D4), + TOP_PARENT(CLK_TOP_UNIVPLL_D6_D2), + TOP_PARENT(CLK_TOP_MMPLL_D9), + TOP_PARENT(CLK_TOP_UNIVPLL_D6), + TOP_PARENT(CLK_TOP_UNIVPLL_D5), + TOP_PARENT(CLK_TOP_MAINPLL_D4), +}; + +static const struct mtk_parent pwm_parents[] = { + TOP_PARENT(CLK_TOP_CLK26M), + TOP_PARENT(CLK_TOP_UNIVPLL_D4_D8), +}; + +static const struct mtk_parent mcupm_parents[] = { + TOP_PARENT(CLK_TOP_CLK26M), + TOP_PARENT(CLK_TOP_MAINPLL_D6_D2), + TOP_PARENT(CLK_TOP_MAINPLL_D7_D4), +}; + +static const struct mtk_parent spmi_parents[] = { + TOP_PARENT(CLK_TOP_CLK26M), + TOP_PARENT(CLK_TOP_CLK26M_D2), + TOP_PARENT(CLK_TOP_ULPOSC1_D8), + TOP_PARENT(CLK_TOP_ULPOSC1_D10), + TOP_PARENT(CLK_TOP_ULPOSC1_D16), + TOP_PARENT(CLK_TOP_ULPOSC1_D7), + TOP_PARENT(CLK_TOP_CLK32K), + TOP_PARENT(CLK_TOP_MAINPLL_D7_D8), + TOP_PARENT(CLK_TOP_MAINPLL_D6_D8), + TOP_PARENT(CLK_TOP_MAINPLL_D5_D8), +}; + +static const struct mtk_parent dvfsrc_parents[] = { + TOP_PARENT(CLK_TOP_CLK26M), + TOP_PARENT(CLK_TOP_ULPOSC1_D10), + TOP_PARENT(CLK_TOP_UNIVPLL_D6_D8), + TOP_PARENT(CLK_TOP_MSDCPLL_D16), +}; + +static const struct mtk_parent tl_parents[] = { + TOP_PARENT(CLK_TOP_CLK26M), + TOP_PARENT(CLK_TOP_UNIVPLL_D5_D4), + TOP_PARENT(CLK_TOP_MAINPLL_D4_D4), +}; + +static const struct mtk_parent dsi_occ_parents[] = { + TOP_PARENT(CLK_TOP_CLK26M), + TOP_PARENT(CLK_TOP_MAINPLL_D6_D2), + TOP_PARENT(CLK_TOP_UNIVPLL_D5_D2), + TOP_PARENT(CLK_TOP_UNIVPLL_D4_D2), +}; + +static const struct mtk_parent wpe_vpp_parents[] = { + TOP_PARENT(CLK_TOP_CLK26M), + TOP_PARENT(CLK_TOP_MAINPLL_D5_D2), + TOP_PARENT(CLK_TOP_MMPLL_D6_D2), + TOP_PARENT(CLK_TOP_UNIVPLL_D5_D2), + TOP_PARENT(CLK_TOP_MAINPLL_D4_D2), + TOP_PARENT(CLK_TOP_UNIVPLL_D4_D2), + TOP_PARENT(CLK_TOP_MMPLL_D4_D2), + TOP_PARENT(CLK_TOP_MAINPLL_D6), + TOP_PARENT(CLK_TOP_MMPLL_D7), + TOP_PARENT(CLK_TOP_UNIVPLL_D6), + TOP_PARENT(CLK_TOP_MAINPLL_D5), + TOP_PARENT(CLK_TOP_UNIVPLL_D5), + TOP_PARENT(CLK_TOP_MAINPLL_D4), + TOP_PARENT(CLK_TOP_TVDPLL1), + TOP_PARENT(CLK_TOP_UNIVPLL_D4), +}; + +static const struct mtk_parent hdcp_parents[] = { + TOP_PARENT(CLK_TOP_CLK26M), + TOP_PARENT(CLK_TOP_UNIVPLL_D4_D8), + TOP_PARENT(CLK_TOP_MAINPLL_D5_D8), + TOP_PARENT(CLK_TOP_UNIVPLL_D6_D4), +}; + +static const struct mtk_parent hdcp_24m_parents[] = { + TOP_PARENT(CLK_TOP_CLK26M), + TOP_PARENT(CLK_TOP_UNIVPLL_192M_D4), + TOP_PARENT(CLK_TOP_UNIVPLL_192M_D8), + TOP_PARENT(CLK_TOP_UNIVPLL_D6_D8), +}; + +static const struct mtk_parent hd20_dacr_ref_parents[] = { + TOP_PARENT(CLK_TOP_CLK26M), + TOP_PARENT(CLK_TOP_UNIVPLL_D4_D2), + TOP_PARENT(CLK_TOP_UNIVPLL_D4_D4), + TOP_PARENT(CLK_TOP_UNIVPLL_D4_D8), +}; + +static const struct mtk_parent hd20_hdcp_c_parents[] = { + TOP_PARENT(CLK_TOP_CLK26M), + TOP_PARENT(CLK_TOP_MSDCPLL_D4), + TOP_PARENT(CLK_TOP_UNIVPLL_D4_D8), + TOP_PARENT(CLK_TOP_UNIVPLL_D6_D8), }; -static const int hdmi_xtal_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_CLK26M_D2 +static const struct mtk_parent hdmi_xtal_parents[] = { + TOP_PARENT(CLK_TOP_CLK26M), + TOP_PARENT(CLK_TOP_CLK26M_D2), }; -static const int hdmi_apb_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_UNIVPLL_D6_D4, - CLK_TOP_MSDCPLL_D2 +static const struct mtk_parent hdmi_apb_parents[] = { + TOP_PARENT(CLK_TOP_CLK26M), + TOP_PARENT(CLK_TOP_UNIVPLL_D6_D4), + TOP_PARENT(CLK_TOP_MSDCPLL_D2), }; -static const int snps_eth_250m_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_ETHPLL_D2 +static const struct mtk_parent snps_eth_250m_parents[] = { + TOP_PARENT(CLK_TOP_CLK26M), + TOP_PARENT(CLK_TOP_ETHPLL_D2), }; -static const int snps_eth_62p4m_ptp_parents[] = { - CLK_TOP_APLL2_D3, - CLK_TOP_APLL1_D3, - CLK_TOP_CLK26M, - CLK_TOP_ETHPLL_D8 +static const struct mtk_parent snps_eth_62p4m_ptp_parents[] = { + TOP_PARENT(CLK_TOP_APLL2_D3), + TOP_PARENT(CLK_TOP_APLL1_D3), + TOP_PARENT(CLK_TOP_CLK26M), + TOP_PARENT(CLK_TOP_ETHPLL_D8), }; -static const int snps_eth_50m_rmii_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_ETHPLL_D10 +static const struct mtk_parent snps_eth_50m_rmii_parents[] = { + TOP_PARENT(CLK_TOP_CLK26M), + TOP_PARENT(CLK_TOP_ETHPLL_D10), }; -static const int dgi_out_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_DGIPLL, - CLK_TOP_DGIPLL_D2, - CLK_TOP_IN_DGI, - CLK_TOP_IN_DGI_D2, - CLK_TOP_MMPLL_D4_D4 +static const struct mtk_parent dgi_out_parents[] = { + TOP_PARENT(CLK_TOP_CLK26M), + TOP_PARENT(CLK_TOP_DGIPLL), + TOP_PARENT(CLK_TOP_DGIPLL_D2), + TOP_PARENT(CLK_TOP_IN_DGI), + TOP_PARENT(CLK_TOP_IN_DGI_D2), + TOP_PARENT(CLK_TOP_MMPLL_D4_D4), }; -static const int nna_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_NNAPLL, - CLK_TOP_UNIVPLL_D4, - CLK_TOP_MAINPLL_D4, - CLK_TOP_UNIVPLL_D5, - CLK_TOP_MMPLL_D6, - CLK_TOP_UNIVPLL_D6, - CLK_TOP_MAINPLL_D6, - CLK_TOP_MMPLL_D4_D2, - CLK_TOP_UNIVPLL_D4_D2, - CLK_TOP_MAINPLL_D4_D2, - CLK_TOP_MMPLL_D6_D2 +static const struct mtk_parent nna_parents[] = { + TOP_PARENT(CLK_TOP_CLK26M), + TOP_PARENT(CLK_TOP_NNAPLL), + TOP_PARENT(CLK_TOP_UNIVPLL_D4), + TOP_PARENT(CLK_TOP_MAINPLL_D4), + TOP_PARENT(CLK_TOP_UNIVPLL_D5), + TOP_PARENT(CLK_TOP_MMPLL_D6), + TOP_PARENT(CLK_TOP_UNIVPLL_D6), + TOP_PARENT(CLK_TOP_MAINPLL_D6), + TOP_PARENT(CLK_TOP_MMPLL_D4_D2), + TOP_PARENT(CLK_TOP_UNIVPLL_D4_D2), + TOP_PARENT(CLK_TOP_MAINPLL_D4_D2), + TOP_PARENT(CLK_TOP_MMPLL_D6_D2), }; -static const int adsp_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_CLK26M_D2, - CLK_TOP_MAINPLL_D6, - CLK_TOP_MAINPLL_D5_D2, - CLK_TOP_UNIVPLL_D4_D4, - CLK_TOP_UNIVPLL_D4, - CLK_TOP_UNIVPLL_D6, - CLK_TOP_ULPOSC1, - CLK_TOP_ADSPPLL, - CLK_TOP_ADSPPLL_D2, - CLK_TOP_ADSPPLL_D4, - CLK_TOP_ADSPPLL_D8 +static const struct mtk_parent adsp_parents[] = { + TOP_PARENT(CLK_TOP_CLK26M), + TOP_PARENT(CLK_TOP_CLK26M_D2), + TOP_PARENT(CLK_TOP_MAINPLL_D6), + TOP_PARENT(CLK_TOP_MAINPLL_D5_D2), + TOP_PARENT(CLK_TOP_UNIVPLL_D4_D4), + TOP_PARENT(CLK_TOP_UNIVPLL_D4), + TOP_PARENT(CLK_TOP_UNIVPLL_D6), + TOP_PARENT(CLK_TOP_ULPOSC1), + TOP_PARENT(CLK_TOP_ADSPPLL), + TOP_PARENT(CLK_TOP_ADSPPLL_D2), + TOP_PARENT(CLK_TOP_ADSPPLL_D4), + TOP_PARENT(CLK_TOP_ADSPPLL_D8), }; -static const int asm_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_UNIVPLL_D6_D4, - CLK_TOP_UNIVPLL_D6_D2, - CLK_TOP_MAINPLL_D5_D2 +static const struct mtk_parent asm_parents[] = { + TOP_PARENT(CLK_TOP_CLK26M), + TOP_PARENT(CLK_TOP_UNIVPLL_D6_D4), + TOP_PARENT(CLK_TOP_UNIVPLL_D6_D2), + TOP_PARENT(CLK_TOP_MAINPLL_D5_D2), }; -static const int apll1_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_APLL1_D4 +static const struct mtk_parent apll1_parents[] = { + TOP_PARENT(CLK_TOP_CLK26M), + TOP_PARENT(CLK_TOP_APLL1_D4), }; -static const int apll2_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_APLL2_D4 +static const struct mtk_parent apll2_parents[] = { + TOP_PARENT(CLK_TOP_CLK26M), + TOP_PARENT(CLK_TOP_APLL2_D4), }; -static const int apll3_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_APLL3_D4 +static const struct mtk_parent apll3_parents[] = { + TOP_PARENT(CLK_TOP_CLK26M), + TOP_PARENT(CLK_TOP_APLL3_D4), }; -static const int apll4_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_APLL4_D4 +static const struct mtk_parent apll4_parents[] = { + TOP_PARENT(CLK_TOP_CLK26M), + TOP_PARENT(CLK_TOP_APLL4_D4), }; -static const int apll5_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_APLL5_D4 +static const struct mtk_parent apll5_parents[] = { + TOP_PARENT(CLK_TOP_CLK26M), + TOP_PARENT(CLK_TOP_APLL5_D4), }; -static const int i2s_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_APLL1, - CLK_TOP_APLL2, - CLK_TOP_APLL3, - CLK_TOP_APLL4, - CLK_TOP_APLL5, - CLK_TOP_HDMIRX_APLL +static const struct mtk_parent i2s_parents[] = { + TOP_PARENT(CLK_TOP_CLK26M), + TOP_PARENT(CLK_TOP_APLL1), + TOP_PARENT(CLK_TOP_APLL2), + TOP_PARENT(CLK_TOP_APLL3), + TOP_PARENT(CLK_TOP_APLL4), + TOP_PARENT(CLK_TOP_APLL5), + TOP_PARENT(CLK_TOP_HDMIRX_APLL), }; -static const int a1sys_hp_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_APLL1_D4 +static const struct mtk_parent a1sys_hp_parents[] = { + TOP_PARENT(CLK_TOP_CLK26M), + TOP_PARENT(CLK_TOP_APLL1_D4), }; -static const int a2sys_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_APLL2_D4 +static const struct mtk_parent a2sys_parents[] = { + TOP_PARENT(CLK_TOP_CLK26M), + TOP_PARENT(CLK_TOP_APLL2_D4), }; -static const int a3sys_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_APLL3_D4, - CLK_TOP_APLL4_D4, - CLK_TOP_APLL5_D4, - CLK_TOP_HDMIRX_APLL_D3, - CLK_TOP_HDMIRX_APLL_D4, - CLK_TOP_HDMIRX_APLL_D6 -}; - -static const int spinfi_b_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_UNIVPLL_D6_D8, - CLK_TOP_UNIVPLL_D5_D8, - CLK_TOP_MAINPLL_D4_D8, - CLK_TOP_MAINPLL_D7_D4, - CLK_TOP_MAINPLL_D6_D4, - CLK_TOP_UNIVPLL_D6_D4, - CLK_TOP_UNIVPLL_D5_D4 -}; - -static const int nfi1x_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_UNIVPLL_D5_D4, - CLK_TOP_MAINPLL_D7_D4, - CLK_TOP_MAINPLL_D6_D4, - CLK_TOP_UNIVPLL_D6_D4, - CLK_TOP_MAINPLL_D4_D4, - CLK_TOP_MAINPLL_D7_D2, - CLK_TOP_MAINPLL_D6_D2 +static const struct mtk_parent a3sys_parents[] = { + TOP_PARENT(CLK_TOP_CLK26M), + TOP_PARENT(CLK_TOP_APLL3_D4), + TOP_PARENT(CLK_TOP_APLL4_D4), + TOP_PARENT(CLK_TOP_APLL5_D4), + TOP_PARENT(CLK_TOP_HDMIRX_APLL_D3), + TOP_PARENT(CLK_TOP_HDMIRX_APLL_D4), + TOP_PARENT(CLK_TOP_HDMIRX_APLL_D6), +}; + +static const struct mtk_parent spinfi_b_parents[] = { + TOP_PARENT(CLK_TOP_CLK26M), + TOP_PARENT(CLK_TOP_UNIVPLL_D6_D8), + TOP_PARENT(CLK_TOP_UNIVPLL_D5_D8), + TOP_PARENT(CLK_TOP_MAINPLL_D4_D8), + TOP_PARENT(CLK_TOP_MAINPLL_D7_D4), + TOP_PARENT(CLK_TOP_MAINPLL_D6_D4), + TOP_PARENT(CLK_TOP_UNIVPLL_D6_D4), + TOP_PARENT(CLK_TOP_UNIVPLL_D5_D4), +}; + +static const struct mtk_parent nfi1x_parents[] = { + TOP_PARENT(CLK_TOP_CLK26M), + TOP_PARENT(CLK_TOP_UNIVPLL_D5_D4), + TOP_PARENT(CLK_TOP_MAINPLL_D7_D4), + TOP_PARENT(CLK_TOP_MAINPLL_D6_D4), + TOP_PARENT(CLK_TOP_UNIVPLL_D6_D4), + TOP_PARENT(CLK_TOP_MAINPLL_D4_D4), + TOP_PARENT(CLK_TOP_MAINPLL_D7_D2), + TOP_PARENT(CLK_TOP_MAINPLL_D6_D2), }; -static const int ecc_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_MAINPLL_D4_D4, - CLK_TOP_MAINPLL_D5_D2, - CLK_TOP_MAINPLL_D4_D2, - CLK_TOP_MAINPLL_D6, - CLK_TOP_UNIVPLL_D6 +static const struct mtk_parent ecc_parents[] = { + TOP_PARENT(CLK_TOP_CLK26M), + TOP_PARENT(CLK_TOP_MAINPLL_D4_D4), + TOP_PARENT(CLK_TOP_MAINPLL_D5_D2), + TOP_PARENT(CLK_TOP_MAINPLL_D4_D2), + TOP_PARENT(CLK_TOP_MAINPLL_D6), + TOP_PARENT(CLK_TOP_UNIVPLL_D6), }; -static const int audio_local_bus_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_CLK26M_D2, - CLK_TOP_MAINPLL_D4_D4, - CLK_TOP_MAINPLL_D7_D2, - CLK_TOP_MAINPLL_D4_D2, - CLK_TOP_MAINPLL_D5_D2, - CLK_TOP_MAINPLL_D6_D2, - CLK_TOP_MAINPLL_D7, - CLK_TOP_UNIVPLL_D6, - CLK_TOP_ULPOSC1, - CLK_TOP_ULPOSC1_D4, - CLK_TOP_ULPOSC1_D2 +static const struct mtk_parent audio_local_bus_parents[] = { + TOP_PARENT(CLK_TOP_CLK26M), + TOP_PARENT(CLK_TOP_CLK26M_D2), + TOP_PARENT(CLK_TOP_MAINPLL_D4_D4), + TOP_PARENT(CLK_TOP_MAINPLL_D7_D2), + TOP_PARENT(CLK_TOP_MAINPLL_D4_D2), + TOP_PARENT(CLK_TOP_MAINPLL_D5_D2), + TOP_PARENT(CLK_TOP_MAINPLL_D6_D2), + TOP_PARENT(CLK_TOP_MAINPLL_D7), + TOP_PARENT(CLK_TOP_UNIVPLL_D6), + TOP_PARENT(CLK_TOP_ULPOSC1), + TOP_PARENT(CLK_TOP_ULPOSC1_D4), + TOP_PARENT(CLK_TOP_ULPOSC1_D2), }; -static const int spinor_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_CLK26M_D2, - CLK_TOP_MAINPLL_D7_D8, - CLK_TOP_UNIVPLL_D6_D8 +static const struct mtk_parent spinor_parents[] = { + TOP_PARENT(CLK_TOP_CLK26M), + TOP_PARENT(CLK_TOP_CLK26M_D2), + TOP_PARENT(CLK_TOP_MAINPLL_D7_D8), + TOP_PARENT(CLK_TOP_UNIVPLL_D6_D8), }; -static const int dvio_dgi_ref_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_IN_DGI, - CLK_TOP_IN_DGI_D2, - CLK_TOP_IN_DGI_D4, - CLK_TOP_IN_DGI_D6, - CLK_TOP_IN_DGI_D8, - CLK_TOP_MMPLL_D4_D4 +static const struct mtk_parent dvio_dgi_ref_parents[] = { + TOP_PARENT(CLK_TOP_CLK26M), + TOP_PARENT(CLK_TOP_IN_DGI), + TOP_PARENT(CLK_TOP_IN_DGI_D2), + TOP_PARENT(CLK_TOP_IN_DGI_D4), + TOP_PARENT(CLK_TOP_IN_DGI_D6), + TOP_PARENT(CLK_TOP_IN_DGI_D8), + TOP_PARENT(CLK_TOP_MMPLL_D4_D4), }; -static const int ulposc_parents[] = { - CLK_TOP_ULPOSC1, - CLK_TOP_ETHPLL_D2, - CLK_TOP_MAINPLL_D4_D2, - CLK_TOP_ETHPLL_D10 +static const struct mtk_parent ulposc_parents[] = { + TOP_PARENT(CLK_TOP_ULPOSC1), + TOP_PARENT(CLK_TOP_ETHPLL_D2), + TOP_PARENT(CLK_TOP_MAINPLL_D4_D2), + TOP_PARENT(CLK_TOP_ETHPLL_D10), }; - -static const int ulposc_core_parents[] = { - CLK_TOP_ULPOSC2, - CLK_TOP_UNIVPLL_D7, - CLK_TOP_MAINPLL_D6, - CLK_TOP_ETHPLL_D10 + +static const struct mtk_parent ulposc_core_parents[] = { + TOP_PARENT(CLK_TOP_ULPOSC2), + TOP_PARENT(CLK_TOP_UNIVPLL_D7), + TOP_PARENT(CLK_TOP_MAINPLL_D6), + TOP_PARENT(CLK_TOP_ETHPLL_D10), }; -static const int srck_parents[] = { - CLK_TOP_ULPOSC1_D10, - CLK_TOP_CLK26M +static const struct mtk_parent srck_parents[] = { + TOP_PARENT(CLK_TOP_ULPOSC1_D10), + TOP_PARENT(CLK_TOP_CLK26M), }; static const struct mtk_composite top_muxes[] = { /* CLK_CFG_0 */ - MUX_GATE(CLK_TOP_AXI, axi_parents, 0x020, 0, 3, 7), - MUX_GATE(CLK_TOP_SPM, spm_parents, 0x020, 8, 2, 15), - MUX_GATE(CLK_TOP_SCP, scp_parents, 0x020, 16, 3, 23), - MUX_GATE(CLK_TOP_BUS_AXIMEM, bus_aximem_parents, 0x020, 24, 3, 31), + MUX_GATE_MIXED(CLK_TOP_AXI, axi_parents, 0x020, 0, 3, 7), + MUX_GATE_MIXED(CLK_TOP_SPM, spm_parents, 0x020, 8, 2, 15), + MUX_GATE_MIXED(CLK_TOP_SCP, scp_parents, 0x020, 16, 3, 23), + MUX_GATE_MIXED(CLK_TOP_BUS_AXIMEM, bus_aximem_parents, 0x020, 24, 3, 31), /* CLK_CFG_1 */ - MUX_GATE(CLK_TOP_VPP, vpp_parents, 0x02C, 0, 4, 7), - MUX_GATE(CLK_TOP_ETHDR, ethdr_parents, 0x02C, 8, 4, 15), - MUX_GATE(CLK_TOP_IPE, ipe_parents, 0x02C, 16, 4, 23), - MUX_GATE(CLK_TOP_CAM, cam_parents, 0x02C, 24, 4, 31), + MUX_GATE_MIXED(CLK_TOP_VPP, vpp_parents, 0x02C, 0, 4, 7), + MUX_GATE_MIXED(CLK_TOP_ETHDR, ethdr_parents, 0x02C, 8, 4, 15), + MUX_GATE_MIXED(CLK_TOP_IPE, ipe_parents, 0x02C, 16, 4, 23), + MUX_GATE_MIXED(CLK_TOP_CAM, cam_parents, 0x02C, 24, 4, 31), /* CLK_CFG_2 */ - MUX_GATE(CLK_TOP_CCU, ccu_parents, 0x038, 0, 4, 7), - MUX_GATE(CLK_TOP_IMG, img_parents, 0x038, 8, 4, 15), - MUX_GATE(CLK_TOP_CAMTM, camtm_parents, 0x038, 16, 2, 23), - MUX_GATE(CLK_TOP_DSP, dsp_parents, 0x038, 24, 3, 31), + MUX_GATE_MIXED(CLK_TOP_CCU, ccu_parents, 0x038, 0, 4, 7), + MUX_GATE_MIXED(CLK_TOP_IMG, img_parents, 0x038, 8, 4, 15), + MUX_GATE_MIXED(CLK_TOP_CAMTM, camtm_parents, 0x038, 16, 2, 23), + MUX_GATE_MIXED(CLK_TOP_DSP, dsp_parents, 0x038, 24, 3, 31), /* CLK_CFG_3 */ - MUX_GATE(CLK_TOP_DSP1, dsp1_parents, 0x044, 0, 3, 7), - MUX_GATE(CLK_TOP_DSP2, dsp1_parents, 0x044, 8, 3, 15), - MUX_GATE(CLK_TOP_DSP3, dsp1_parents, 0x044, 16, 3, 23), - MUX_GATE(CLK_TOP_DSP4, dsp2_parents, 0x044, 24, 3, 31), + MUX_GATE_MIXED(CLK_TOP_DSP1, dsp1_parents, 0x044, 0, 3, 7), + MUX_GATE_MIXED(CLK_TOP_DSP2, dsp1_parents, 0x044, 8, 3, 15), + MUX_GATE_MIXED(CLK_TOP_DSP3, dsp1_parents, 0x044, 16, 3, 23), + MUX_GATE_MIXED(CLK_TOP_DSP4, dsp2_parents, 0x044, 24, 3, 31), /* CLK_CFG_4 */ - MUX_GATE(CLK_TOP_DSP5, dsp2_parents, 0x050, 0, 3, 7), - MUX_GATE(CLK_TOP_DSP6, dsp2_parents, 0x050, 8, 3, 15), - MUX_GATE(CLK_TOP_DSP7, dsp_parents, 0x050, 16, 3, 23), - MUX_GATE(CLK_TOP_IPU_IF, ipu_if_parents, 0x050, 24, 3, 31), + MUX_GATE_MIXED(CLK_TOP_DSP5, dsp2_parents, 0x050, 0, 3, 7), + MUX_GATE_MIXED(CLK_TOP_DSP6, dsp2_parents, 0x050, 8, 3, 15), + MUX_GATE_MIXED(CLK_TOP_DSP7, dsp_parents, 0x050, 16, 3, 23), + MUX_GATE_MIXED(CLK_TOP_IPU_IF, ipu_if_parents, 0x050, 24, 3, 31), /* CLK_CFG_5 */ - MUX_GATE(CLK_TOP_MFG_CORE_TMP, mfg_parents, 0x05C, 0, 2, 7), - MUX_GATE(CLK_TOP_CAMTG, camtg_parents, 0x05C, 8, 3, 15), - MUX_GATE(CLK_TOP_CAMTG2, camtg_parents, 0x05C, 16, 3, 23), - MUX_GATE(CLK_TOP_CAMTG3, camtg_parents, 0x05C, 24, 3, 31), + MUX_GATE_MIXED(CLK_TOP_MFG_CORE_TMP, mfg_parents, 0x05C, 0, 2, 7), + MUX_GATE_MIXED(CLK_TOP_CAMTG, camtg_parents, 0x05C, 8, 3, 15), + MUX_GATE_MIXED(CLK_TOP_CAMTG2, camtg_parents, 0x05C, 16, 3, 23), + MUX_GATE_MIXED(CLK_TOP_CAMTG3, camtg_parents, 0x05C, 24, 3, 31), /* CLK_CFG_6 */ - MUX_GATE(CLK_TOP_CAMTG4, camtg_parents, 0x068, 0, 3, 7), - MUX_GATE(CLK_TOP_CAMTG5, camtg_parents, 0x068, 8, 3, 15), - MUX_GATE(CLK_TOP_UART, uart_parents, 0x068, 16, 1, 23), - MUX_GATE(CLK_TOP_SPI, spi_parents, 0x068, 24, 3, 31), + MUX_GATE_MIXED(CLK_TOP_CAMTG4, camtg_parents, 0x068, 0, 3, 7), + MUX_GATE_MIXED(CLK_TOP_CAMTG5, camtg_parents, 0x068, 8, 3, 15), + MUX_GATE_MIXED(CLK_TOP_UART, uart_parents, 0x068, 16, 1, 23), + MUX_GATE_MIXED(CLK_TOP_SPI, spi_parents, 0x068, 24, 3, 31), /* CLK_CFG_7 */ - MUX_GATE(CLK_TOP_SPIS, spis_parents, 0x074, 0, 3, 7), - MUX_GATE(CLK_TOP_MSDC50_0_HCLK, msdc50_0_h_parents, 0x074, 8, 2, 15), - MUX_GATE(CLK_TOP_MSDC50_0, msdc50_0_parents, 0x074, 16, 3, 23), - MUX_GATE(CLK_TOP_MSDC30_1, msdc30_parents, 0x074, 24, 3, 31), + MUX_GATE_MIXED(CLK_TOP_SPIS, spis_parents, 0x074, 0, 3, 7), + MUX_GATE_MIXED(CLK_TOP_MSDC50_0_HCLK, msdc50_0_h_parents, 0x074, 8, 2, 15), + MUX_GATE_MIXED(CLK_TOP_MSDC50_0, msdc50_0_parents, 0x074, 16, 3, 23), + MUX_GATE_MIXED(CLK_TOP_MSDC30_1, msdc30_parents, 0x074, 24, 3, 31), /* CLK_CFG_8 */ - MUX_GATE(CLK_TOP_MSDC30_2, msdc30_parents, 0x080, 0, 3, 7), - MUX_GATE(CLK_TOP_INTDIR, intdir_parents, 0x080, 8, 2, 15), - MUX_GATE(CLK_TOP_AUD_INTBUS, aud_intbus_parents, 0x080, 16, 2, 23), - MUX_GATE(CLK_TOP_AUDIO_H, audio_h_parents, 0x080, 24, 2, 31), + MUX_GATE_MIXED(CLK_TOP_MSDC30_2, msdc30_parents, 0x080, 0, 3, 7), + MUX_GATE_MIXED(CLK_TOP_INTDIR, intdir_parents, 0x080, 8, 2, 15), + MUX_GATE_MIXED(CLK_TOP_AUD_INTBUS, aud_intbus_parents, 0x080, 16, 2, 23), + MUX_GATE_MIXED(CLK_TOP_AUDIO_H, audio_h_parents, 0x080, 24, 2, 31), /* CLK_CFG_9 */ - MUX_GATE(CLK_TOP_PWRAP_ULPOSC, pwrap_ulposc_parents, 0x08C, 0, 3, 7), - MUX_GATE(CLK_TOP_ATB, atb_parents, 0x08C, 8, 2, 15), - MUX_GATE(CLK_TOP_PWRMCU, pwrmcu_parents, 0x08C, 16, 3, 23), - MUX_GATE(CLK_TOP_DP, dp_parents, 0x08C, 24, 4, 31), + MUX_GATE_MIXED(CLK_TOP_PWRAP_ULPOSC, pwrap_ulposc_parents, 0x08C, 0, 3, 7), + MUX_GATE_MIXED(CLK_TOP_ATB, atb_parents, 0x08C, 8, 2, 15), + MUX_GATE_MIXED(CLK_TOP_PWRMCU, pwrmcu_parents, 0x08C, 16, 3, 23), + MUX_GATE_MIXED(CLK_TOP_DP, dp_parents, 0x08C, 24, 4, 31), /* CLK_CFG_10 */ - MUX_GATE(CLK_TOP_EDP, dp_parents, 0x098, 0, 4, 7), - MUX_GATE(CLK_TOP_DPI, dp_parents, 0x098, 8, 4, 15), - MUX_GATE(CLK_TOP_DISP_PWM0, disp_pwm_parents, 0x098, 16, 3, 23), - MUX_GATE(CLK_TOP_DISP_PWM1, disp_pwm_parents, 0x098, 24, 3, 31), + MUX_GATE_MIXED(CLK_TOP_EDP, dp_parents, 0x098, 0, 4, 7), + MUX_GATE_MIXED(CLK_TOP_DPI, dp_parents, 0x098, 8, 4, 15), + MUX_GATE_MIXED(CLK_TOP_DISP_PWM0, disp_pwm_parents, 0x098, 16, 3, 23), + MUX_GATE_MIXED(CLK_TOP_DISP_PWM1, disp_pwm_parents, 0x098, 24, 3, 31), /* CLK_CFG_11 */ - MUX_GATE(CLK_TOP_USB_TOP, usb_parents, 0x0A4, 0, 2, 7), - MUX_GATE(CLK_TOP_SSUSB_XHCI, usb_parents, 0x0A4, 8, 2, 15), - MUX_GATE(CLK_TOP_USB_TOP_1P, usb_parents, 0x0A4, 16, 2, 23), - MUX_GATE(CLK_TOP_SSUSB_XHCI_1P, usb_parents, 0x0A4, 24, 2, 31), + MUX_GATE_MIXED(CLK_TOP_USB_TOP, usb_parents, 0x0A4, 0, 2, 7), + MUX_GATE_MIXED(CLK_TOP_SSUSB_XHCI, usb_parents, 0x0A4, 8, 2, 15), + MUX_GATE_MIXED(CLK_TOP_USB_TOP_1P, usb_parents, 0x0A4, 16, 2, 23), + MUX_GATE_MIXED(CLK_TOP_SSUSB_XHCI_1P, usb_parents, 0x0A4, 24, 2, 31), /* CLK_CFG_12 */ - MUX_GATE(CLK_TOP_USB_TOP_2P, usb_parents, 0x0B0, 0, 2, 7), - MUX_GATE(CLK_TOP_SSUSB_XHCI_2P, usb_parents, 0x0B0, 8, 2, 15), - MUX_GATE(CLK_TOP_USB_TOP_3P, usb_parents, 0x0B0, 16, 2, 23), - MUX_GATE(CLK_TOP_SSUSB_XHCI_3P, usb_parents, 0x0B0, 24, 2, 31), + MUX_GATE_MIXED(CLK_TOP_USB_TOP_2P, usb_parents, 0x0B0, 0, 2, 7), + MUX_GATE_MIXED(CLK_TOP_SSUSB_XHCI_2P, usb_parents, 0x0B0, 8, 2, 15), + MUX_GATE_MIXED(CLK_TOP_USB_TOP_3P, usb_parents, 0x0B0, 16, 2, 23), + MUX_GATE_MIXED(CLK_TOP_SSUSB_XHCI_3P, usb_parents, 0x0B0, 24, 2, 31), /* CLK_CFG_13 */ - MUX_GATE(CLK_TOP_I2C, i2c_parents, 0x0BC, 0, 2, 7), - MUX_GATE(CLK_TOP_SENINF, seninf_parents, 0x0BC, 8, 3, 15), - MUX_GATE(CLK_TOP_SENINF1, seninf_parents, 0x0BC, 16, 3, 23), - MUX_GATE(CLK_TOP_SENINF2, seninf_parents, 0x0BC, 24, 3, 31), + MUX_GATE_MIXED(CLK_TOP_I2C, i2c_parents, 0x0BC, 0, 2, 7), + MUX_GATE_MIXED(CLK_TOP_SENINF, seninf_parents, 0x0BC, 8, 3, 15), + MUX_GATE_MIXED(CLK_TOP_SENINF1, seninf_parents, 0x0BC, 16, 3, 23), + MUX_GATE_MIXED(CLK_TOP_SENINF2, seninf_parents, 0x0BC, 24, 3, 31), /* CLK_CFG_14 */ - MUX_GATE(CLK_TOP_SENINF3, seninf_parents, 0x0C8, 0, 3, 7), - MUX_GATE(CLK_TOP_GCPU, gcpu_parents, 0x0C8, 8, 3, 15), - MUX_GATE(CLK_TOP_DXCC, dxcc_parents, 0x0C8, 16, 2, 23), - MUX_GATE(CLK_TOP_DPMAIF_MAIN, dpmaif_parents, 0x0C8, 24, 3, 31), + MUX_GATE_MIXED(CLK_TOP_SENINF3, seninf_parents, 0x0C8, 0, 3, 7), + MUX_GATE_MIXED(CLK_TOP_GCPU, gcpu_parents, 0x0C8, 8, 3, 15), + MUX_GATE_MIXED(CLK_TOP_DXCC, dxcc_parents, 0x0C8, 16, 2, 23), + MUX_GATE_MIXED(CLK_TOP_DPMAIF_MAIN, dpmaif_parents, 0x0C8, 24, 3, 31), /* CLK_CFG_15 */ - MUX_GATE(CLK_TOP_AES_UFSFDE, aes_fde_parents, 0x0D4, 0, 3, 7), - MUX_GATE(CLK_TOP_UFS, ufs_parents, 0x0D4, 8, 3, 15), - MUX_GATE(CLK_TOP_UFS_TICK1US, ufs_tick1us_parents, 0x0D4, 16, 1, 23), - MUX_GATE(CLK_TOP_UFS_MP_SAP_CFG, ufs_mp_sap_parents, 0x0D4, 24, 1, 31), + MUX_GATE_MIXED(CLK_TOP_AES_UFSFDE, aes_fde_parents, 0x0D4, 0, 3, 7), + MUX_GATE_MIXED(CLK_TOP_UFS, ufs_parents, 0x0D4, 8, 3, 15), + MUX_GATE_MIXED(CLK_TOP_UFS_TICK1US, ufs_tick1us_parents, 0x0D4, 16, 1, 23), + MUX_GATE_MIXED(CLK_TOP_UFS_MP_SAP_CFG, ufs_mp_sap_parents, 0x0D4, 24, 1, 31), /* CLK_CFG_16 */ - MUX_GATE(CLK_TOP_VENC, venc_parents, 0x0E0, 0, 4, 7), - MUX_GATE(CLK_TOP_VDEC, vdec_parents, 0x0E0, 8, 4, 15), - MUX_GATE(CLK_TOP_PWM, pwm_parents, 0x0E0, 16, 1, 23), - MUX_GATE(CLK_TOP_MCUPM, mcupm_parents, 0x0E0, 24, 2, 31), + MUX_GATE_MIXED(CLK_TOP_VENC, venc_parents, 0x0E0, 0, 4, 7), + MUX_GATE_MIXED(CLK_TOP_VDEC, vdec_parents, 0x0E0, 8, 4, 15), + MUX_GATE_MIXED(CLK_TOP_PWM, pwm_parents, 0x0E0, 16, 1, 23), + MUX_GATE_MIXED(CLK_TOP_MCUPM, mcupm_parents, 0x0E0, 24, 2, 31), /* CLK_CFG_17 */ - MUX_GATE(CLK_TOP_SPMI_P_MST, spmi_parents, 0x0EC, 0, 4, 7), - MUX_GATE(CLK_TOP_SPMI_M_MST, spmi_parents, 0x0EC, 8, 4, 15), - MUX_GATE(CLK_TOP_DVFSRC, dvfsrc_parents, 0x0EC, 16, 2, 23), - MUX_GATE(CLK_TOP_TL, tl_parents, 0x0EC, 24, 2, 31), + MUX_GATE_MIXED(CLK_TOP_SPMI_P_MST, spmi_parents, 0x0EC, 0, 4, 7), + MUX_GATE_MIXED(CLK_TOP_SPMI_M_MST, spmi_parents, 0x0EC, 8, 4, 15), + MUX_GATE_MIXED(CLK_TOP_DVFSRC, dvfsrc_parents, 0x0EC, 16, 2, 23), + MUX_GATE_MIXED(CLK_TOP_TL, tl_parents, 0x0EC, 24, 2, 31), /* CLK_CFG_18 */ - MUX_GATE(CLK_TOP_TL_P1, tl_parents, 0x0F8, 0, 2, 7), - MUX_GATE(CLK_TOP_AES_MSDCFDE, aes_fde_parents, 0x0F8, 8, 3, 15), - MUX_GATE(CLK_TOP_DSI_OCC, dsi_occ_parents, 0x0F8, 16, 2, 23), - MUX_GATE(CLK_TOP_WPE_VPP, wpe_vpp_parents, 0x0F8, 24, 4, 31), + MUX_GATE_MIXED(CLK_TOP_TL_P1, tl_parents, 0x0F8, 0, 2, 7), + MUX_GATE_MIXED(CLK_TOP_AES_MSDCFDE, aes_fde_parents, 0x0F8, 8, 3, 15), + MUX_GATE_MIXED(CLK_TOP_DSI_OCC, dsi_occ_parents, 0x0F8, 16, 2, 23), + MUX_GATE_MIXED(CLK_TOP_WPE_VPP, wpe_vpp_parents, 0x0F8, 24, 4, 31), /* CLK_CFG_19 */ - MUX_GATE(CLK_TOP_HDCP, hdcp_parents, 0x0104, 0, 2, 7), - MUX_GATE(CLK_TOP_HDCP_24M, hdcp_24m_parents, 0x0104, 8, 2, 15), - MUX_GATE(CLK_TOP_HD20_DACR_REF_CLK, hd20_dacr_ref_parents, 0x0104, 16, 2, 23), - MUX_GATE(CLK_TOP_HD20_HDCP_CCLK, hd20_hdcp_c_parents, 0x0104, 24, 2, 31), + MUX_GATE_MIXED(CLK_TOP_HDCP, hdcp_parents, 0x0104, 0, 2, 7), + MUX_GATE_MIXED(CLK_TOP_HDCP_24M, hdcp_24m_parents, 0x0104, 8, 2, 15), + MUX_GATE_MIXED(CLK_TOP_HD20_DACR_REF_CLK, hd20_dacr_ref_parents, 0x0104, 16, 2, 23), + MUX_GATE_MIXED(CLK_TOP_HD20_HDCP_CCLK, hd20_hdcp_c_parents, 0x0104, 24, 2, 31), /* CLK_CFG_20 */ - MUX_GATE(CLK_TOP_HDMI_XTAL, hdmi_xtal_parents, 0x0110, 0, 1, 7), - MUX_GATE(CLK_TOP_HDMI_APB, hdmi_apb_parents, 0x0110, 8, 2, 15), - MUX_GATE(CLK_TOP_SNPS_ETH_250M, snps_eth_250m_parents, 0x0110, 16, 1, - 23), - MUX_GATE(CLK_TOP_SNPS_ETH_62P4M_PTP, snps_eth_62p4m_ptp_parents, 0x0110, 24, 2, 31), + MUX_GATE_MIXED(CLK_TOP_HDMI_XTAL, hdmi_xtal_parents, 0x0110, 0, 1, 7), + MUX_GATE_MIXED(CLK_TOP_HDMI_APB, hdmi_apb_parents, 0x0110, 8, 2, 15), + MUX_GATE_MIXED(CLK_TOP_SNPS_ETH_250M, snps_eth_250m_parents, 0x0110, 16, 1, 23), + MUX_GATE_MIXED(CLK_TOP_SNPS_ETH_62P4M_PTP, snps_eth_62p4m_ptp_parents, 0x0110, 24, 2, 31), /* CLK_CFG_21 */ - MUX_GATE(CLK_TOP_SNPS_ETH_50M_RMII, snps_eth_50m_rmii_parents, 0x011C, 0, 1, 7), - MUX_GATE(CLK_TOP_DGI_OUT, dgi_out_parents, 0x011C, 8, 3, 15), - MUX_GATE(CLK_TOP_NNA0, nna_parents, 0x011C, 16, 4, 23), - MUX_GATE(CLK_TOP_NNA1, nna_parents, 0x011C, 24, 4, 31), + MUX_GATE_MIXED(CLK_TOP_SNPS_ETH_50M_RMII, snps_eth_50m_rmii_parents, 0x011C, 0, 1, 7), + MUX_GATE_MIXED(CLK_TOP_DGI_OUT, dgi_out_parents, 0x011C, 8, 3, 15), + MUX_GATE_MIXED(CLK_TOP_NNA0, nna_parents, 0x011C, 16, 4, 23), + MUX_GATE_MIXED(CLK_TOP_NNA1, nna_parents, 0x011C, 24, 4, 31), /* CLK_CFG_22 */ - MUX_GATE(CLK_TOP_ADSP, adsp_parents, 0x0128, 0, 4, 7), - MUX_GATE(CLK_TOP_ASM_H, asm_parents, 0x0128, 8, 2, 15), - MUX_GATE(CLK_TOP_ASM_M, asm_parents, 0x0128, 16, 2, 23), - MUX_GATE(CLK_TOP_ASM_L, asm_parents, 0x0128, 24, 2, 31), + MUX_GATE_MIXED(CLK_TOP_ADSP, adsp_parents, 0x0128, 0, 4, 7), + MUX_GATE_MIXED(CLK_TOP_ASM_H, asm_parents, 0x0128, 8, 2, 15), + MUX_GATE_MIXED(CLK_TOP_ASM_M, asm_parents, 0x0128, 16, 2, 23), + MUX_GATE_MIXED(CLK_TOP_ASM_L, asm_parents, 0x0128, 24, 2, 31), /* CLK_CFG_23 */ - MUX_GATE(CLK_TOP_APLL1, apll1_parents, 0x0134, 0, 1, 7), - MUX_GATE(CLK_TOP_APLL2, apll2_parents, 0x0134, 8, 1, 15), - MUX_GATE(CLK_TOP_APLL3, apll3_parents, 0x0134, 16, 1, 23), - MUX_GATE(CLK_TOP_APLL4, apll4_parents, 0x0134, 24, 1, 31), + MUX_GATE_MIXED(CLK_TOP_APLL1, apll1_parents, 0x0134, 0, 1, 7), + MUX_GATE_MIXED(CLK_TOP_APLL2, apll2_parents, 0x0134, 8, 1, 15), + MUX_GATE_MIXED(CLK_TOP_APLL3, apll3_parents, 0x0134, 16, 1, 23), + MUX_GATE_MIXED(CLK_TOP_APLL4, apll4_parents, 0x0134, 24, 1, 31), /* * CLK_CFG_24 * i2so4_mck is not used in MT8195. */ - MUX_GATE(CLK_TOP_APLL5, apll5_parents, 0x0140, 0, 1, 7), - MUX_GATE(CLK_TOP_I2SO1_MCK, i2s_parents, 0x0140, 8, 3, 15), - MUX_GATE(CLK_TOP_I2SO2_MCK, i2s_parents, 0x0140, 16, 3, 23), + MUX_GATE_MIXED(CLK_TOP_APLL5, apll5_parents, 0x0140, 0, 1, 7), + MUX_GATE_MIXED(CLK_TOP_I2SO1_MCK, i2s_parents, 0x0140, 8, 3, 15), + MUX_GATE_MIXED(CLK_TOP_I2SO2_MCK, i2s_parents, 0x0140, 16, 3, 23), /* * CLK_CFG_25 * i2so5_mck and i2si4_mck are not used in MT8195. */ - MUX_GATE(CLK_TOP_I2SI1_MCK, i2s_parents, 0x014C, 8, 3, 15), - MUX_GATE(CLK_TOP_I2SI2_MCK, i2s_parents, 0x014C, 16, 3, 23), + MUX_GATE_MIXED(CLK_TOP_I2SI1_MCK, i2s_parents, 0x014C, 8, 3, 15), + MUX_GATE_MIXED(CLK_TOP_I2SI2_MCK, i2s_parents, 0x014C, 16, 3, 23), /* * CLK_CFG_26 * i2si5_mck is not used in MT8195. */ - MUX_GATE(CLK_TOP_DPTX_MCK, i2s_parents, 0x0158, 8, 3, 15), - MUX_GATE(CLK_TOP_AUD_IEC_CLK, i2s_parents, 0x0158, 16, 3, 23), - MUX_GATE(CLK_TOP_A1SYS_HP, a1sys_hp_parents, 0x0158, 24, 1, 31), + MUX_GATE_MIXED(CLK_TOP_DPTX_MCK, i2s_parents, 0x0158, 8, 3, 15), + MUX_GATE_MIXED(CLK_TOP_AUD_IEC_CLK, i2s_parents, 0x0158, 16, 3, 23), + MUX_GATE_MIXED(CLK_TOP_A1SYS_HP, a1sys_hp_parents, 0x0158, 24, 1, 31), /* CLK_CFG_27 */ - MUX_GATE(CLK_TOP_A2SYS_HF, a2sys_parents, 0x0164, 0, 1, 7), - MUX_GATE(CLK_TOP_A3SYS_HF, a3sys_parents, 0x0164, 8, 3, 15), - MUX_GATE(CLK_TOP_A4SYS_HF, a3sys_parents, 0x0164, 16, 3, 23), - MUX_GATE(CLK_TOP_SPINFI_BCLK, spinfi_b_parents, 0x0164, 24, 3, 31), + MUX_GATE_MIXED(CLK_TOP_A2SYS_HF, a2sys_parents, 0x0164, 0, 1, 7), + MUX_GATE_MIXED(CLK_TOP_A3SYS_HF, a3sys_parents, 0x0164, 8, 3, 15), + MUX_GATE_MIXED(CLK_TOP_A4SYS_HF, a3sys_parents, 0x0164, 16, 3, 23), + MUX_GATE_MIXED(CLK_TOP_SPINFI_BCLK, spinfi_b_parents, 0x0164, 24, 3, 31), /* CLK_CFG_28 */ - MUX_GATE(CLK_TOP_NFI1X, nfi1x_parents, 0x0170, 0, 3, 7), - MUX_GATE(CLK_TOP_ECC, ecc_parents, 0x0170, 8, 3, 15), - MUX_GATE(CLK_TOP_AUDIO_LOCAL_BUS, audio_local_bus_parents, 0x0170, 16, 4, 23), - MUX_GATE(CLK_TOP_SPINOR, spinor_parents, 0x0170, 24, 2, 31), + MUX_GATE_MIXED(CLK_TOP_NFI1X, nfi1x_parents, 0x0170, 0, 3, 7), + MUX_GATE_MIXED(CLK_TOP_ECC, ecc_parents, 0x0170, 8, 3, 15), + MUX_GATE_MIXED(CLK_TOP_AUDIO_LOCAL_BUS, audio_local_bus_parents, 0x0170, 16, 4, 23), + MUX_GATE_MIXED(CLK_TOP_SPINOR, spinor_parents, 0x0170, 24, 2, 31), /* CLK_CFG_29 */ - MUX_GATE(CLK_TOP_DVIO_DGI_REF, dvio_dgi_ref_parents, 0x017C, 0, 3, 7), - MUX_GATE(CLK_TOP_ULPOSC, ulposc_parents, 0x017C, 8, 2, 15), - MUX_GATE(CLK_TOP_ULPOSC_CORE, ulposc_core_parents, 0x017C, 16, 2, 23), - MUX_GATE(CLK_TOP_SRCK, srck_parents, 0x017C, 24, 1, 31), + MUX_GATE_MIXED(CLK_TOP_DVIO_DGI_REF, dvio_dgi_ref_parents, 0x017C, 0, 3, 7), + MUX_GATE_MIXED(CLK_TOP_ULPOSC, ulposc_parents, 0x017C, 8, 2, 15), + MUX_GATE_MIXED(CLK_TOP_ULPOSC_CORE, ulposc_core_parents, 0x017C, 16, 2, 23), + MUX_GATE_MIXED(CLK_TOP_SRCK, srck_parents, 0x017C, 24, 1, 31), }; static const struct mtk_gate_regs top0_cg_regs = { -- cgit v1.3.1 From ec7f2425a1960d13863ceea1b1ccf5c86c814fcd Mon Sep 17 00:00:00 2001 From: David Lechner Date: Tue, 17 Mar 2026 18:23:23 -0500 Subject: clk: mediatek: mt8365: convert to struct mtk_parent Convert all parent clock arrays to use struct mtk_parent. This will allow us to simplify core code later by having only one possible data type for mux parent arrays. Reviewed-by: Macpaul Lin Reviewed-by: Julien Stephan Link: https://patch.msgid.link/20260317-clk-mtk-unify-mux-parents-v3-10-a4760f5b0a80@baylibre.com Signed-off-by: David Lechner --- drivers/clk/mediatek/clk-mt8365.c | 522 +++++++++++++++++++------------------- 1 file changed, 261 insertions(+), 261 deletions(-) diff --git a/drivers/clk/mediatek/clk-mt8365.c b/drivers/clk/mediatek/clk-mt8365.c index 2b1703e7203..41dd2479c5a 100644 --- a/drivers/clk/mediatek/clk-mt8365.c +++ b/drivers/clk/mediatek/clk-mt8365.c @@ -298,347 +298,347 @@ static const struct mtk_fixed_factor top_divs[] = { PLL_FACTOR2(CLK_TOP_CLK26M_D52, "clk26m_d52", CLK_XTAL, 1, 52), }; -static const int axi_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_SYSPLL_D7, - CLK_TOP_SYSPLL1_D4, - CLK_TOP_SYSPLL3_D2 -}; - -static const int mem_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_MMPLL, - CLK_TOP_SYSPLL_D3, - CLK_TOP_SYSPLL1_D2 -}; - -static const int mm_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_MMPLL, - CLK_TOP_SYSPLL1_D2, - CLK_TOP_SYSPLL_D5, - CLK_TOP_SYSPLL1_D4, - CLK_TOP_UNIVPLL_D5, - CLK_TOP_UNIVPLL1_D2, - CLK_TOP_MMPLL_D2, -}; - -static const int scp_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_SYSPLL4_D2, - CLK_TOP_UNIVPLL2_D2, - CLK_TOP_SYSPLL1_D2, - CLK_TOP_UNIVPLL1_D2, - CLK_TOP_SYSPLL_D3, - CLK_TOP_UNIVPLL_D3 +static const struct mtk_parent axi_parents[] = { + TOP_PARENT(CLK_TOP_CLK26M), + TOP_PARENT(CLK_TOP_SYSPLL_D7), + TOP_PARENT(CLK_TOP_SYSPLL1_D4), + TOP_PARENT(CLK_TOP_SYSPLL3_D2), +}; + +static const struct mtk_parent mem_parents[] = { + TOP_PARENT(CLK_TOP_CLK26M), + TOP_PARENT(CLK_TOP_MMPLL), + TOP_PARENT(CLK_TOP_SYSPLL_D3), + TOP_PARENT(CLK_TOP_SYSPLL1_D2), +}; + +static const struct mtk_parent mm_parents[] = { + TOP_PARENT(CLK_TOP_CLK26M), + TOP_PARENT(CLK_TOP_MMPLL), + TOP_PARENT(CLK_TOP_SYSPLL1_D2), + TOP_PARENT(CLK_TOP_SYSPLL_D5), + TOP_PARENT(CLK_TOP_SYSPLL1_D4), + TOP_PARENT(CLK_TOP_UNIVPLL_D5), + TOP_PARENT(CLK_TOP_UNIVPLL1_D2), + TOP_PARENT(CLK_TOP_MMPLL_D2), +}; + +static const struct mtk_parent scp_parents[] = { + TOP_PARENT(CLK_TOP_CLK26M), + TOP_PARENT(CLK_TOP_SYSPLL4_D2), + TOP_PARENT(CLK_TOP_UNIVPLL2_D2), + TOP_PARENT(CLK_TOP_SYSPLL1_D2), + TOP_PARENT(CLK_TOP_UNIVPLL1_D2), + TOP_PARENT(CLK_TOP_SYSPLL_D3), + TOP_PARENT(CLK_TOP_UNIVPLL_D3), }; -static const int mfg_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_MFGPLL, - CLK_TOP_SYSPLL_D3, - CLK_TOP_UNIVPLL_D3 +static const struct mtk_parent mfg_parents[] = { + TOP_PARENT(CLK_TOP_CLK26M), + TOP_PARENT(CLK_TOP_MFGPLL), + TOP_PARENT(CLK_TOP_SYSPLL_D3), + TOP_PARENT(CLK_TOP_UNIVPLL_D3), }; -static const int atb_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_SYSPLL1_D4, - CLK_TOP_SYSPLL1_D2 +static const struct mtk_parent atb_parents[] = { + TOP_PARENT(CLK_TOP_CLK26M), + TOP_PARENT(CLK_TOP_SYSPLL1_D4), + TOP_PARENT(CLK_TOP_SYSPLL1_D2), }; -static const int camtg_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_USB20_192M_D8, - CLK_TOP_UNIVPLL2_D8, - CLK_TOP_USB20_192M_D4, - CLK_TOP_UNIVPLL2_D32, - CLK_TOP_USB20_192M_D16, - CLK_TOP_USB20_192M_D32, +static const struct mtk_parent camtg_parents[] = { + TOP_PARENT(CLK_TOP_CLK26M), + TOP_PARENT(CLK_TOP_USB20_192M_D8), + TOP_PARENT(CLK_TOP_UNIVPLL2_D8), + TOP_PARENT(CLK_TOP_USB20_192M_D4), + TOP_PARENT(CLK_TOP_UNIVPLL2_D32), + TOP_PARENT(CLK_TOP_USB20_192M_D16), + TOP_PARENT(CLK_TOP_USB20_192M_D32), }; -static const int uart_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_UNIVPLL2_D8 +static const struct mtk_parent uart_parents[] = { + TOP_PARENT(CLK_TOP_CLK26M), + TOP_PARENT(CLK_TOP_UNIVPLL2_D8), }; -static const int spi_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_UNIVPLL2_D2, - CLK_TOP_UNIVPLL2_D4, - CLK_TOP_UNIVPLL2_D8 +static const struct mtk_parent spi_parents[] = { + TOP_PARENT(CLK_TOP_CLK26M), + TOP_PARENT(CLK_TOP_UNIVPLL2_D2), + TOP_PARENT(CLK_TOP_UNIVPLL2_D4), + TOP_PARENT(CLK_TOP_UNIVPLL2_D8), }; -static const int msdc50_0_hc_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_SYSPLL1_D2, - CLK_TOP_UNIVPLL1_D4, - CLK_TOP_SYSPLL2_D2 +static const struct mtk_parent msdc50_0_hc_parents[] = { + TOP_PARENT(CLK_TOP_CLK26M), + TOP_PARENT(CLK_TOP_SYSPLL1_D2), + TOP_PARENT(CLK_TOP_UNIVPLL1_D4), + TOP_PARENT(CLK_TOP_SYSPLL2_D2), }; -static const int msdc50_0_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_MSDCPLL, - CLK_TOP_UNIVPLL1_D2, - CLK_TOP_SYSPLL1_D2, - CLK_TOP_UNIVPLL_D5, - CLK_TOP_SYSPLL2_D2, - CLK_TOP_UNIVPLL1_D4, - CLK_TOP_SYSPLL4_D2 +static const struct mtk_parent msdc50_0_parents[] = { + TOP_PARENT(CLK_TOP_CLK26M), + TOP_PARENT(CLK_TOP_MSDCPLL), + TOP_PARENT(CLK_TOP_UNIVPLL1_D2), + TOP_PARENT(CLK_TOP_SYSPLL1_D2), + TOP_PARENT(CLK_TOP_UNIVPLL_D5), + TOP_PARENT(CLK_TOP_SYSPLL2_D2), + TOP_PARENT(CLK_TOP_UNIVPLL1_D4), + TOP_PARENT(CLK_TOP_SYSPLL4_D2), }; -static const int msdc50_2_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_MSDCPLL, - CLK_TOP_UNIVPLL_D3, - CLK_TOP_UNIVPLL1_D2, - CLK_TOP_SYSPLL1_D2, - CLK_TOP_UNIVPLL2_D2, - CLK_TOP_SYSPLL2_D2, - CLK_TOP_UNIVPLL1_D4 +static const struct mtk_parent msdc50_2_parents[] = { + TOP_PARENT(CLK_TOP_CLK26M), + TOP_PARENT(CLK_TOP_MSDCPLL), + TOP_PARENT(CLK_TOP_UNIVPLL_D3), + TOP_PARENT(CLK_TOP_UNIVPLL1_D2), + TOP_PARENT(CLK_TOP_SYSPLL1_D2), + TOP_PARENT(CLK_TOP_UNIVPLL2_D2), + TOP_PARENT(CLK_TOP_SYSPLL2_D2), + TOP_PARENT(CLK_TOP_UNIVPLL1_D4), }; -static const int msdc30_1_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_MSDCPLL_D2, - CLK_TOP_UNIVPLL2_D2, - CLK_TOP_SYSPLL2_D2, - CLK_TOP_UNIVPLL1_D4, - CLK_TOP_SYSPLL1_D4, - CLK_TOP_SYSPLL2_D4, - CLK_TOP_UNIVPLL2_D8 +static const struct mtk_parent msdc30_1_parents[] = { + TOP_PARENT(CLK_TOP_CLK26M), + TOP_PARENT(CLK_TOP_MSDCPLL_D2), + TOP_PARENT(CLK_TOP_UNIVPLL2_D2), + TOP_PARENT(CLK_TOP_SYSPLL2_D2), + TOP_PARENT(CLK_TOP_UNIVPLL1_D4), + TOP_PARENT(CLK_TOP_SYSPLL1_D4), + TOP_PARENT(CLK_TOP_SYSPLL2_D4), + TOP_PARENT(CLK_TOP_UNIVPLL2_D8), }; -static const int audio_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_SYSPLL3_D4, - CLK_TOP_SYSPLL4_D4, - CLK_TOP_SYSPLL1_D16 +static const struct mtk_parent audio_parents[] = { + TOP_PARENT(CLK_TOP_CLK26M), + TOP_PARENT(CLK_TOP_SYSPLL3_D4), + TOP_PARENT(CLK_TOP_SYSPLL4_D4), + TOP_PARENT(CLK_TOP_SYSPLL1_D16), }; -static const int aud_intbus_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_SYSPLL1_D4, - CLK_TOP_SYSPLL4_D2 +static const struct mtk_parent aud_intbus_parents[] = { + TOP_PARENT(CLK_TOP_CLK26M), + TOP_PARENT(CLK_TOP_SYSPLL1_D4), + TOP_PARENT(CLK_TOP_SYSPLL4_D2), }; -static const int aud_1_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_APLL1 +static const struct mtk_parent aud_1_parents[] = { + TOP_PARENT(CLK_TOP_CLK26M), + TOP_PARENT(CLK_TOP_APLL1), }; -static const int aud_2_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_APLL2 +static const struct mtk_parent aud_2_parents[] = { + TOP_PARENT(CLK_TOP_CLK26M), + TOP_PARENT(CLK_TOP_APLL2), }; -static const int aud_engen1_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_APLL1_D2, - CLK_TOP_APLL1_D4, - CLK_TOP_APLL1_D8 +static const struct mtk_parent aud_engen1_parents[] = { + TOP_PARENT(CLK_TOP_CLK26M), + TOP_PARENT(CLK_TOP_APLL1_D2), + TOP_PARENT(CLK_TOP_APLL1_D4), + TOP_PARENT(CLK_TOP_APLL1_D8), }; -static const int aud_engen2_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_APLL2_D2, - CLK_TOP_APLL2_D4, - CLK_TOP_APLL2_D8, +static const struct mtk_parent aud_engen2_parents[] = { + TOP_PARENT(CLK_TOP_CLK26M), + TOP_PARENT(CLK_TOP_APLL2_D2), + TOP_PARENT(CLK_TOP_APLL2_D4), + TOP_PARENT(CLK_TOP_APLL2_D8), }; -static const int aud_spdif_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_UNIVPLL_D2 +static const struct mtk_parent aud_spdif_parents[] = { + TOP_PARENT(CLK_TOP_CLK26M), + TOP_PARENT(CLK_TOP_UNIVPLL_D2), }; -static const int disp_pwm_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_UNIVPLL2_D4 +static const struct mtk_parent disp_pwm_parents[] = { + TOP_PARENT(CLK_TOP_CLK26M), + TOP_PARENT(CLK_TOP_UNIVPLL2_D4), }; -static const int dxcc_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_SYSPLL1_D2, - CLK_TOP_SYSPLL1_D4, - CLK_TOP_SYSPLL1_D8 +static const struct mtk_parent dxcc_parents[] = { + TOP_PARENT(CLK_TOP_CLK26M), + TOP_PARENT(CLK_TOP_SYSPLL1_D2), + TOP_PARENT(CLK_TOP_SYSPLL1_D4), + TOP_PARENT(CLK_TOP_SYSPLL1_D8), }; -static const int ssusb_sys_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_UNIVPLL3_D4, - CLK_TOP_UNIVPLL2_D4, - CLK_TOP_UNIVPLL3_D2 +static const struct mtk_parent ssusb_sys_parents[] = { + TOP_PARENT(CLK_TOP_CLK26M), + TOP_PARENT(CLK_TOP_UNIVPLL3_D4), + TOP_PARENT(CLK_TOP_UNIVPLL2_D4), + TOP_PARENT(CLK_TOP_UNIVPLL3_D2), }; -static const int spm_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_SYSPLL1_D8 +static const struct mtk_parent spm_parents[] = { + TOP_PARENT(CLK_TOP_CLK26M), + TOP_PARENT(CLK_TOP_SYSPLL1_D8), }; -static const int i2c_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_UNIVPLL3_D4, - CLK_TOP_UNIVPLL3_D2, - CLK_TOP_SYSPLL1_D8, - CLK_TOP_SYSPLL2_D8 +static const struct mtk_parent i2c_parents[] = { + TOP_PARENT(CLK_TOP_CLK26M), + TOP_PARENT(CLK_TOP_UNIVPLL3_D4), + TOP_PARENT(CLK_TOP_UNIVPLL3_D2), + TOP_PARENT(CLK_TOP_SYSPLL1_D8), + TOP_PARENT(CLK_TOP_SYSPLL2_D8), }; -static const int pwm_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_UNIVPLL3_D4, - CLK_TOP_SYSPLL1_D8 +static const struct mtk_parent pwm_parents[] = { + TOP_PARENT(CLK_TOP_CLK26M), + TOP_PARENT(CLK_TOP_UNIVPLL3_D4), + TOP_PARENT(CLK_TOP_SYSPLL1_D8), }; -static const int senif_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_UNIVPLL1_D4, - CLK_TOP_UNIVPLL1_D2, - CLK_TOP_UNIVPLL2_D2 +static const struct mtk_parent senif_parents[] = { + TOP_PARENT(CLK_TOP_CLK26M), + TOP_PARENT(CLK_TOP_UNIVPLL1_D4), + TOP_PARENT(CLK_TOP_UNIVPLL1_D2), + TOP_PARENT(CLK_TOP_UNIVPLL2_D2), }; -static const int aes_fde_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_MSDCPLL, - CLK_TOP_UNIVPLL_D3, - CLK_TOP_UNIVPLL2_D2, - CLK_TOP_UNIVPLL1_D2, - CLK_TOP_SYSPLL1_D2 +static const struct mtk_parent aes_fde_parents[] = { + TOP_PARENT(CLK_TOP_CLK26M), + TOP_PARENT(CLK_TOP_MSDCPLL), + TOP_PARENT(CLK_TOP_UNIVPLL_D3), + TOP_PARENT(CLK_TOP_UNIVPLL2_D2), + TOP_PARENT(CLK_TOP_UNIVPLL1_D2), + TOP_PARENT(CLK_TOP_SYSPLL1_D2), }; -static const int dpi0_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_LVDSPLL_D2, - CLK_TOP_LVDSPLL_D4, - CLK_TOP_LVDSPLL_D8, - CLK_TOP_LVDSPLL_D16 +static const struct mtk_parent dpi0_parents[] = { + TOP_PARENT(CLK_TOP_CLK26M), + TOP_PARENT(CLK_TOP_LVDSPLL_D2), + TOP_PARENT(CLK_TOP_LVDSPLL_D4), + TOP_PARENT(CLK_TOP_LVDSPLL_D8), + TOP_PARENT(CLK_TOP_LVDSPLL_D16), }; -static const int dsp_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_SYS_26M_D2, - CLK_TOP_DSPPLL, - CLK_TOP_DSPPLL_D2, - CLK_TOP_DSPPLL_D4, - CLK_TOP_DSPPLL_D8 +static const struct mtk_parent dsp_parents[] = { + TOP_PARENT(CLK_TOP_CLK26M), + TOP_PARENT(CLK_TOP_SYS_26M_D2), + TOP_PARENT(CLK_TOP_DSPPLL), + TOP_PARENT(CLK_TOP_DSPPLL_D2), + TOP_PARENT(CLK_TOP_DSPPLL_D4), + TOP_PARENT(CLK_TOP_DSPPLL_D8), }; -static const int nfi2x_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_SYSPLL2_D2, - CLK_TOP_SYSPLL_D7, - CLK_TOP_SYSPLL_D3, - CLK_TOP_SYSPLL2_D4, - CLK_TOP_MSDCPLL_D2, - CLK_TOP_UNIVPLL1_D2, - CLK_TOP_UNIVPLL_D5 +static const struct mtk_parent nfi2x_parents[] = { + TOP_PARENT(CLK_TOP_CLK26M), + TOP_PARENT(CLK_TOP_SYSPLL2_D2), + TOP_PARENT(CLK_TOP_SYSPLL_D7), + TOP_PARENT(CLK_TOP_SYSPLL_D3), + TOP_PARENT(CLK_TOP_SYSPLL2_D4), + TOP_PARENT(CLK_TOP_MSDCPLL_D2), + TOP_PARENT(CLK_TOP_UNIVPLL1_D2), + TOP_PARENT(CLK_TOP_UNIVPLL_D5), }; -static const int nfiecc_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_SYSPLL4_D2, - CLK_TOP_UNIVPLL2_D4, - CLK_TOP_SYSPLL_D7, - CLK_TOP_UNIVPLL1_D2, - CLK_TOP_SYSPLL1_D2, - CLK_TOP_UNIVPLL2_D2, - CLK_TOP_SYSPLL_D5 +static const struct mtk_parent nfiecc_parents[] = { + TOP_PARENT(CLK_TOP_CLK26M), + TOP_PARENT(CLK_TOP_SYSPLL4_D2), + TOP_PARENT(CLK_TOP_UNIVPLL2_D4), + TOP_PARENT(CLK_TOP_SYSPLL_D7), + TOP_PARENT(CLK_TOP_UNIVPLL1_D2), + TOP_PARENT(CLK_TOP_SYSPLL1_D2), + TOP_PARENT(CLK_TOP_UNIVPLL2_D2), + TOP_PARENT(CLK_TOP_SYSPLL_D5), }; -static const int ecc_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_UNIVPLL2_D2, - CLK_TOP_UNIVPLL1_D2, - CLK_TOP_UNIVPLL_D3, - CLK_TOP_SYSPLL_D2 +static const struct mtk_parent ecc_parents[] = { + TOP_PARENT(CLK_TOP_CLK26M), + TOP_PARENT(CLK_TOP_UNIVPLL2_D2), + TOP_PARENT(CLK_TOP_UNIVPLL1_D2), + TOP_PARENT(CLK_TOP_UNIVPLL_D3), + TOP_PARENT(CLK_TOP_SYSPLL_D2), }; -static const int eth_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_UNIVPLL2_D8, - CLK_TOP_SYSPLL4_D4, - CLK_TOP_SYSPLL1_D8, - CLK_TOP_SYSPLL4_D2 +static const struct mtk_parent eth_parents[] = { + TOP_PARENT(CLK_TOP_CLK26M), + TOP_PARENT(CLK_TOP_UNIVPLL2_D8), + TOP_PARENT(CLK_TOP_SYSPLL4_D4), + TOP_PARENT(CLK_TOP_SYSPLL1_D8), + TOP_PARENT(CLK_TOP_SYSPLL4_D2), }; -static const int gcpu_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_UNIVPLL_D3, - CLK_TOP_UNIVPLL2_D2, - CLK_TOP_SYSPLL_D3, - CLK_TOP_SYSPLL2_D2 +static const struct mtk_parent gcpu_parents[] = { + TOP_PARENT(CLK_TOP_CLK26M), + TOP_PARENT(CLK_TOP_UNIVPLL_D3), + TOP_PARENT(CLK_TOP_UNIVPLL2_D2), + TOP_PARENT(CLK_TOP_SYSPLL_D3), + TOP_PARENT(CLK_TOP_SYSPLL2_D2), }; -static const int gcpu_cpm_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_UNIVPLL2_D2, - CLK_TOP_SYSPLL2_D2 +static const struct mtk_parent gcpu_cpm_parents[] = { + TOP_PARENT(CLK_TOP_CLK26M), + TOP_PARENT(CLK_TOP_UNIVPLL2_D2), + TOP_PARENT(CLK_TOP_SYSPLL2_D2), }; -static const int apu_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_UNIVPLL_D2, - CLK_TOP_APUPLL, - CLK_TOP_MMPLL, - CLK_TOP_SYSPLL_D3, - CLK_TOP_UNIVPLL1_D2, - CLK_TOP_SYSPLL1_D2, - CLK_TOP_SYSPLL1_D4 +static const struct mtk_parent apu_parents[] = { + TOP_PARENT(CLK_TOP_CLK26M), + TOP_PARENT(CLK_TOP_UNIVPLL_D2), + TOP_PARENT(CLK_TOP_APUPLL), + TOP_PARENT(CLK_TOP_MMPLL), + TOP_PARENT(CLK_TOP_SYSPLL_D3), + TOP_PARENT(CLK_TOP_UNIVPLL1_D2), + TOP_PARENT(CLK_TOP_SYSPLL1_D2), + TOP_PARENT(CLK_TOP_SYSPLL1_D4), }; static const struct mtk_composite top_muxes[] = { /* CLK_CFG_0 */ - MUX_GATE(CLK_TOP_AXI_SEL, axi_parents, 0x040, 0, 2, 7), - MUX_GATE(CLK_TOP_MEM_SEL, mem_parents, 0x040, 8, 2, 15), - MUX_GATE(CLK_TOP_MM_SEL, mm_parents, 0x040, 16, 3, 23), - MUX_GATE(CLK_TOP_SCP_SEL, scp_parents, 0x040, 24, 3, 31), + MUX_GATE_MIXED(CLK_TOP_AXI_SEL, axi_parents, 0x040, 0, 2, 7), + MUX_GATE_MIXED(CLK_TOP_MEM_SEL, mem_parents, 0x040, 8, 2, 15), + MUX_GATE_MIXED(CLK_TOP_MM_SEL, mm_parents, 0x040, 16, 3, 23), + MUX_GATE_MIXED(CLK_TOP_SCP_SEL, scp_parents, 0x040, 24, 3, 31), /* CLK_CFG_1 */ - MUX_GATE(CLK_TOP_MFG_SEL, mfg_parents, 0x050, 0, 2, 7), - MUX_GATE(CLK_TOP_ATB_SEL, atb_parents, 0x050, 8, 2, 15), - MUX_GATE(CLK_TOP_CAMTG_SEL, camtg_parents, 0x050, 16, 3, 23), - MUX_GATE(CLK_TOP_CAMTG1_SEL, camtg_parents, 0x050, 24, 3, 31), + MUX_GATE_MIXED(CLK_TOP_MFG_SEL, mfg_parents, 0x050, 0, 2, 7), + MUX_GATE_MIXED(CLK_TOP_ATB_SEL, atb_parents, 0x050, 8, 2, 15), + MUX_GATE_MIXED(CLK_TOP_CAMTG_SEL, camtg_parents, 0x050, 16, 3, 23), + MUX_GATE_MIXED(CLK_TOP_CAMTG1_SEL, camtg_parents, 0x050, 24, 3, 31), /* CLK_CFG_2 */ - MUX_GATE(CLK_TOP_UART_SEL, uart_parents, 0x060, 0, 1, 7), - MUX_GATE(CLK_TOP_SPI_SEL, spi_parents, 0x060, 8, 2, 15), - MUX_GATE(CLK_TOP_MSDC50_0_HC_SEL, msdc50_0_hc_parents, 0x060, 16, 2, 23), - MUX_GATE(CLK_TOP_MSDC2_2_HC_SEL, msdc50_0_hc_parents, 0x060, 24, 2, 31), + MUX_GATE_MIXED(CLK_TOP_UART_SEL, uart_parents, 0x060, 0, 1, 7), + MUX_GATE_MIXED(CLK_TOP_SPI_SEL, spi_parents, 0x060, 8, 2, 15), + MUX_GATE_MIXED(CLK_TOP_MSDC50_0_HC_SEL, msdc50_0_hc_parents, 0x060, 16, 2, 23), + MUX_GATE_MIXED(CLK_TOP_MSDC2_2_HC_SEL, msdc50_0_hc_parents, 0x060, 24, 2, 31), /* CLK_CFG_3 */ - MUX_GATE(CLK_TOP_MSDC50_0_SEL, msdc50_0_parents, 0x070, 0, 3, 7), - MUX_GATE(CLK_TOP_MSDC50_2_SEL, msdc50_2_parents, 0x070, 8, 3, 15), - MUX_GATE(CLK_TOP_MSDC30_1_SEL, msdc30_1_parents, 0x070, 16, 3, 23), - MUX_GATE(CLK_TOP_AUDIO_SEL, audio_parents, 0x070, 24, 2, 31), + MUX_GATE_MIXED(CLK_TOP_MSDC50_0_SEL, msdc50_0_parents, 0x070, 0, 3, 7), + MUX_GATE_MIXED(CLK_TOP_MSDC50_2_SEL, msdc50_2_parents, 0x070, 8, 3, 15), + MUX_GATE_MIXED(CLK_TOP_MSDC30_1_SEL, msdc30_1_parents, 0x070, 16, 3, 23), + MUX_GATE_MIXED(CLK_TOP_AUDIO_SEL, audio_parents, 0x070, 24, 2, 31), /* CLK_CFG_4 */ - MUX_GATE(CLK_TOP_AUD_INTBUS_SEL, aud_intbus_parents, 0x080, 0, 2, 7), - MUX_GATE(CLK_TOP_AUD_1_SEL, aud_1_parents, 0x080, 8, 1, 15), - MUX_GATE(CLK_TOP_AUD_2_SEL, aud_2_parents, 0x080, 16, 1, 23), - MUX_GATE(CLK_TOP_AUD_ENGEN1_SEL, aud_engen1_parents, 0x080, 24, 2, 31), + MUX_GATE_MIXED(CLK_TOP_AUD_INTBUS_SEL, aud_intbus_parents, 0x080, 0, 2, 7), + MUX_GATE_MIXED(CLK_TOP_AUD_1_SEL, aud_1_parents, 0x080, 8, 1, 15), + MUX_GATE_MIXED(CLK_TOP_AUD_2_SEL, aud_2_parents, 0x080, 16, 1, 23), + MUX_GATE_MIXED(CLK_TOP_AUD_ENGEN1_SEL, aud_engen1_parents, 0x080, 24, 2, 31), /* CLK_CFG_5 */ - MUX_GATE(CLK_TOP_AUD_ENGEN2_SEL, aud_engen2_parents, 0x090, 0, 2, 7), - MUX_GATE(CLK_TOP_AUD_SPDIF_SEL, aud_spdif_parents, 0x090, 8, 1, 15), - MUX_GATE(CLK_TOP_DISP_PWM_SEL, disp_pwm_parents, 0x090, 16, 2, 23), + MUX_GATE_MIXED(CLK_TOP_AUD_ENGEN2_SEL, aud_engen2_parents, 0x090, 0, 2, 7), + MUX_GATE_MIXED(CLK_TOP_AUD_SPDIF_SEL, aud_spdif_parents, 0x090, 8, 1, 15), + MUX_GATE_MIXED(CLK_TOP_DISP_PWM_SEL, disp_pwm_parents, 0x090, 16, 2, 23), /* CLK_CFG_6 */ - MUX_GATE(CLK_TOP_DXCC_SEL, dxcc_parents, 0x0a0, 0, 2, 7), - MUX_GATE(CLK_TOP_SSUSB_SYS_SEL, ssusb_sys_parents, 0x0a0, 8, 2, 15), - MUX_GATE(CLK_TOP_SSUSB_XHCI_SEL, ssusb_sys_parents, 0x0a0, 16, 2, 23), - MUX_GATE(CLK_TOP_SPM_SEL, spm_parents, 0x0a0, 24, 1, 31), + MUX_GATE_MIXED(CLK_TOP_DXCC_SEL, dxcc_parents, 0x0a0, 0, 2, 7), + MUX_GATE_MIXED(CLK_TOP_SSUSB_SYS_SEL, ssusb_sys_parents, 0x0a0, 8, 2, 15), + MUX_GATE_MIXED(CLK_TOP_SSUSB_XHCI_SEL, ssusb_sys_parents, 0x0a0, 16, 2, 23), + MUX_GATE_MIXED(CLK_TOP_SPM_SEL, spm_parents, 0x0a0, 24, 1, 31), /* CLK_CFG_7 */ - MUX_GATE(CLK_TOP_I2C_SEL, i2c_parents, 0x0b0, 0, 3, 7), - MUX_GATE(CLK_TOP_PWM_SEL, pwm_parents, 0x0b0, 8, 2, 15), - MUX_GATE(CLK_TOP_SENIF_SEL, senif_parents, 0x0b0, 16, 2, 23), - MUX_GATE(CLK_TOP_AES_FDE_SEL, aes_fde_parents, 0x0b0, 24, 3, 31), + MUX_GATE_MIXED(CLK_TOP_I2C_SEL, i2c_parents, 0x0b0, 0, 3, 7), + MUX_GATE_MIXED(CLK_TOP_PWM_SEL, pwm_parents, 0x0b0, 8, 2, 15), + MUX_GATE_MIXED(CLK_TOP_SENIF_SEL, senif_parents, 0x0b0, 16, 2, 23), + MUX_GATE_MIXED(CLK_TOP_AES_FDE_SEL, aes_fde_parents, 0x0b0, 24, 3, 31), /* CLK_CFG_8 */ - MUX_GATE(CLK_TOP_CAMTM_SEL, senif_parents, 0x0c0, 0, 2, 7), - MUX_GATE(CLK_TOP_DPI0_SEL, dpi0_parents, 0x0c0, 8, 3, 15), - MUX_GATE(CLK_TOP_DPI1_SEL, dpi0_parents, 0x0c0, 16, 3, 23), - MUX_GATE(CLK_TOP_DSP_SEL, dsp_parents, 0x0c0, 24, 3, 31), + MUX_GATE_MIXED(CLK_TOP_CAMTM_SEL, senif_parents, 0x0c0, 0, 2, 7), + MUX_GATE_MIXED(CLK_TOP_DPI0_SEL, dpi0_parents, 0x0c0, 8, 3, 15), + MUX_GATE_MIXED(CLK_TOP_DPI1_SEL, dpi0_parents, 0x0c0, 16, 3, 23), + MUX_GATE_MIXED(CLK_TOP_DSP_SEL, dsp_parents, 0x0c0, 24, 3, 31), /* CLK_CFG_9 */ - MUX_GATE(CLK_TOP_NFI2X_SEL, nfi2x_parents, 0x0d0, 0, 3, 7), - MUX_GATE(CLK_TOP_NFIECC_SEL, nfiecc_parents, 0x0d0, 8, 3, 15), - MUX_GATE(CLK_TOP_ECC_SEL, ecc_parents, 0x0d0, 16, 3, 23), - MUX_GATE(CLK_TOP_ETH_SEL, eth_parents, 0x0d0, 24, 3, 31), + MUX_GATE_MIXED(CLK_TOP_NFI2X_SEL, nfi2x_parents, 0x0d0, 0, 3, 7), + MUX_GATE_MIXED(CLK_TOP_NFIECC_SEL, nfiecc_parents, 0x0d0, 8, 3, 15), + MUX_GATE_MIXED(CLK_TOP_ECC_SEL, ecc_parents, 0x0d0, 16, 3, 23), + MUX_GATE_MIXED(CLK_TOP_ETH_SEL, eth_parents, 0x0d0, 24, 3, 31), /* CLK_CFG_10 */ - MUX_GATE(CLK_TOP_GCPU_SEL, gcpu_parents, 0x0e0, 0, 3, 7), - MUX_GATE(CLK_TOP_GCPU_CPM_SEL, gcpu_cpm_parents, 0x0e0, 8, 2, 15), - MUX_GATE(CLK_TOP_APU_SEL, apu_parents, 0x0e0, 16, 3, 23), - MUX_GATE(CLK_TOP_APU_IF_SEL, apu_parents, 0x0e0, 24, 3, 31), + MUX_GATE_MIXED(CLK_TOP_GCPU_SEL, gcpu_parents, 0x0e0, 0, 3, 7), + MUX_GATE_MIXED(CLK_TOP_GCPU_CPM_SEL, gcpu_cpm_parents, 0x0e0, 8, 2, 15), + MUX_GATE_MIXED(CLK_TOP_APU_SEL, apu_parents, 0x0e0, 16, 3, 23), + MUX_GATE_MIXED(CLK_TOP_APU_IF_SEL, apu_parents, 0x0e0, 24, 3, 31), }; /* topckgen cg */ -- cgit v1.3.1 From e4ade301caef438e7a1627f197e087375f2723b5 Mon Sep 17 00:00:00 2001 From: David Lechner Date: Tue, 17 Mar 2026 18:23:24 -0500 Subject: clk: mediatek: mt8512: convert to struct mtk_parent Convert all parent clock arrays to use struct mtk_parent. This will allow us to simplify core code later by having only one possible data type for mux parent arrays. Reviewed-by: Julien Stephan Link: https://patch.msgid.link/20260317-clk-mtk-unify-mux-parents-v3-11-a4760f5b0a80@baylibre.com Signed-off-by: David Lechner --- drivers/clk/mediatek/clk-mt8512.c | 692 +++++++++++++++++++------------------- 1 file changed, 346 insertions(+), 346 deletions(-) diff --git a/drivers/clk/mediatek/clk-mt8512.c b/drivers/clk/mediatek/clk-mt8512.c index 7af5858286c..0ea600b577a 100644 --- a/drivers/clk/mediatek/clk-mt8512.c +++ b/drivers/clk/mediatek/clk-mt8512.c @@ -135,465 +135,465 @@ static const struct mtk_fixed_factor top_fixed_divs[] = { FACTOR1(CLK_TOP_NFI2X_CK_D2, CLK_TOP_NFI2X_SEL, 1, 2), }; -static const int axi_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_SYSPLL1_D4, - CLK_TOP_UNIVPLL3_D2, - CLK_TOP_SYSPLL1_D8, - CLK_TOP_SYS_26M_D2, - CLK_TOP_CLK32K -}; - -static const int mem_parents[] = { - CLK_TOP_DSPPLL, - CLK_TOP_IPPLL, - CLK_TOP_CLK26M, - CLK_TOP_UNIVPLL_D3 -}; - -static const int uart_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_UNIVPLL2_D8 -}; - -static const int spi_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_UNIVPLL2_D2, - CLK_TOP_SYSPLL2_D2, - CLK_TOP_UNIVPLL1_D4, - CLK_TOP_SYSPLL1_D4, - CLK_TOP_UNIVPLL3_D2, - CLK_TOP_UNIVPLL2_D4, - CLK_TOP_SYSPLL4_D2 -}; - -static const int spis_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_UNIVPLL_D3, - CLK_TOP_SYSPLL_D3, - CLK_TOP_UNIVPLL1_D2, - CLK_TOP_UNIVPLL2_D2, - CLK_TOP_UNIVPLL1_D4, - CLK_TOP_UNIVPLL2_D4, - CLK_TOP_SYSPLL4_D2 -}; - -static const int msdc50_0_hc_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_SYSPLL1_D2, - CLK_TOP_UNIVPLL1_D4, - CLK_TOP_SYSPLL2_D2 -}; - -static const int msdc50_0_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_MSDCPLL_D2, - CLK_TOP_UNIVPLL2_D2, - CLK_TOP_SYSPLL2_D2, - CLK_TOP_UNIVPLL1_D4, - CLK_TOP_SYSPLL1_D4, - CLK_TOP_SYSPLL2_D4, - CLK_TOP_UNIVPLL2_D8 -}; - -static const int msdc50_2_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_MSDCPLL, - CLK_TOP_UNIVPLL_D3, - CLK_TOP_UNIVPLL1_D2, - CLK_TOP_SYSPLL1_D2, - CLK_TOP_UNIVPLL2_D2, - CLK_TOP_SYSPLL2_D2, - CLK_TOP_UNIVPLL1_D4 -}; - -static const int audio_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_UNIVPLL2_D8, - CLK_TOP_APLL1_D4, - CLK_TOP_APLL2_D4 -}; - -static const int aud_intbus_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_SYSPLL1_D4, - CLK_TOP_UNIVPLL3_D2, - CLK_TOP_APLL2_D8, - CLK_TOP_SYS_26M_D2, - CLK_TOP_APLL1_D8, - CLK_TOP_UNIVPLL3_D4 -}; - -static const int hapll1_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_APLL1, - CLK_TOP_APLL1_D2, - CLK_TOP_APLL1_D3, - CLK_TOP_APLL1_D4, - CLK_TOP_APLL1_D8, - CLK_TOP_APLL1_D16, - CLK_TOP_SYS_26M_D2 -}; - -static const int hapll2_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_APLL2, - CLK_TOP_APLL2_D2, - CLK_TOP_APLL2_D3, - CLK_TOP_APLL2_D4, - CLK_TOP_APLL2_D8, - CLK_TOP_APLL2_D16, - CLK_TOP_SYS_26M_D2 -}; - -static const int asm_l_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_UNIVPLL2_D4, - CLK_TOP_UNIVPLL2_D2, - CLK_TOP_SYSPLL_D5 -}; - -static const int aud_spdif_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_UNIVPLL_D2, - CLK_TOP_DSPPLL -}; - -static const int aud_1_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_APLL1 -}; - -static const int aud_2_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_APLL2 -}; - -static const int ssusb_sys_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_UNIVPLL3_D4, - CLK_TOP_UNIVPLL2_D4, - CLK_TOP_UNIVPLL3_D2 -}; - -static const int spm_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_SYSPLL1_D8 -}; - -static const int i2c_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_SYS_26M_D2, - CLK_TOP_UNIVPLL3_D4, - CLK_TOP_UNIVPLL3_D2, - CLK_TOP_SYSPLL1_D8, - CLK_TOP_SYSPLL2_D8, - CLK_TOP_CLK32K -}; - -static const int pwm_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_UNIVPLL3_D4, - CLK_TOP_SYSPLL1_D8, - CLK_TOP_UNIVPLL2_D4, - CLK_TOP_SYS_26M_D2, - CLK_TOP_CLK32K -}; - -static const int dsp_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_DSPPLL, - CLK_TOP_DSPPLL_D2, - CLK_TOP_DSPPLL_D4, - CLK_TOP_DSPPLL_D8, - CLK_TOP_APLL2_D4, - CLK_TOP_SYS_26M_D2, - CLK_TOP_CLK32K -}; - -static const int nfi2x_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_SYSPLL2_D2, - CLK_TOP_SYSPLL_D7, - CLK_TOP_SYSPLL_D3, - CLK_TOP_SYSPLL2_D4, - CLK_TOP_MSDCPLL_D2, - CLK_TOP_UNIVPLL1_D2, - CLK_TOP_UNIVPLL_D5 -}; - -static const int spinfi_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_UNIVPLL2_D8, - CLK_TOP_UNIVPLL3_D4, - CLK_TOP_SYSPLL1_D8, - CLK_TOP_SYSPLL4_D2, - CLK_TOP_SYSPLL2_D4, - CLK_TOP_UNIVPLL2_D4, - CLK_TOP_UNIVPLL3_D2 -}; - -static const int ecc_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_SYSPLL_D5, - CLK_TOP_SYSPLL_D3, - CLK_TOP_UNIVPLL_D3 -}; - -static const int gcpu_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_UNIVPLL_D3, - CLK_TOP_SYSPLL_D3, - CLK_TOP_UNIVPLL1_D2, - CLK_TOP_SYSPLL1_D2, - CLK_TOP_UNIVPLL2_D2 +static const struct mtk_parent axi_parents[] = { + TOP_PARENT(CLK_TOP_CLK26M), + TOP_PARENT(CLK_TOP_SYSPLL1_D4), + TOP_PARENT(CLK_TOP_UNIVPLL3_D2), + TOP_PARENT(CLK_TOP_SYSPLL1_D8), + TOP_PARENT(CLK_TOP_SYS_26M_D2), + TOP_PARENT(CLK_TOP_CLK32K), +}; + +static const struct mtk_parent mem_parents[] = { + TOP_PARENT(CLK_TOP_DSPPLL), + TOP_PARENT(CLK_TOP_IPPLL), + TOP_PARENT(CLK_TOP_CLK26M), + TOP_PARENT(CLK_TOP_UNIVPLL_D3), +}; + +static const struct mtk_parent uart_parents[] = { + TOP_PARENT(CLK_TOP_CLK26M), + TOP_PARENT(CLK_TOP_UNIVPLL2_D8), +}; + +static const struct mtk_parent spi_parents[] = { + TOP_PARENT(CLK_TOP_CLK26M), + TOP_PARENT(CLK_TOP_UNIVPLL2_D2), + TOP_PARENT(CLK_TOP_SYSPLL2_D2), + TOP_PARENT(CLK_TOP_UNIVPLL1_D4), + TOP_PARENT(CLK_TOP_SYSPLL1_D4), + TOP_PARENT(CLK_TOP_UNIVPLL3_D2), + TOP_PARENT(CLK_TOP_UNIVPLL2_D4), + TOP_PARENT(CLK_TOP_SYSPLL4_D2), +}; + +static const struct mtk_parent spis_parents[] = { + TOP_PARENT(CLK_TOP_CLK26M), + TOP_PARENT(CLK_TOP_UNIVPLL_D3), + TOP_PARENT(CLK_TOP_SYSPLL_D3), + TOP_PARENT(CLK_TOP_UNIVPLL1_D2), + TOP_PARENT(CLK_TOP_UNIVPLL2_D2), + TOP_PARENT(CLK_TOP_UNIVPLL1_D4), + TOP_PARENT(CLK_TOP_UNIVPLL2_D4), + TOP_PARENT(CLK_TOP_SYSPLL4_D2), +}; + +static const struct mtk_parent msdc50_0_hc_parents[] = { + TOP_PARENT(CLK_TOP_CLK26M), + TOP_PARENT(CLK_TOP_SYSPLL1_D2), + TOP_PARENT(CLK_TOP_UNIVPLL1_D4), + TOP_PARENT(CLK_TOP_SYSPLL2_D2), +}; + +static const struct mtk_parent msdc50_0_parents[] = { + TOP_PARENT(CLK_TOP_CLK26M), + TOP_PARENT(CLK_TOP_MSDCPLL_D2), + TOP_PARENT(CLK_TOP_UNIVPLL2_D2), + TOP_PARENT(CLK_TOP_SYSPLL2_D2), + TOP_PARENT(CLK_TOP_UNIVPLL1_D4), + TOP_PARENT(CLK_TOP_SYSPLL1_D4), + TOP_PARENT(CLK_TOP_SYSPLL2_D4), + TOP_PARENT(CLK_TOP_UNIVPLL2_D8), +}; + +static const struct mtk_parent msdc50_2_parents[] = { + TOP_PARENT(CLK_TOP_CLK26M), + TOP_PARENT(CLK_TOP_MSDCPLL), + TOP_PARENT(CLK_TOP_UNIVPLL_D3), + TOP_PARENT(CLK_TOP_UNIVPLL1_D2), + TOP_PARENT(CLK_TOP_SYSPLL1_D2), + TOP_PARENT(CLK_TOP_UNIVPLL2_D2), + TOP_PARENT(CLK_TOP_SYSPLL2_D2), + TOP_PARENT(CLK_TOP_UNIVPLL1_D4), +}; + +static const struct mtk_parent audio_parents[] = { + TOP_PARENT(CLK_TOP_CLK26M), + TOP_PARENT(CLK_TOP_UNIVPLL2_D8), + TOP_PARENT(CLK_TOP_APLL1_D4), + TOP_PARENT(CLK_TOP_APLL2_D4), +}; + +static const struct mtk_parent aud_intbus_parents[] = { + TOP_PARENT(CLK_TOP_CLK26M), + TOP_PARENT(CLK_TOP_SYSPLL1_D4), + TOP_PARENT(CLK_TOP_UNIVPLL3_D2), + TOP_PARENT(CLK_TOP_APLL2_D8), + TOP_PARENT(CLK_TOP_SYS_26M_D2), + TOP_PARENT(CLK_TOP_APLL1_D8), + TOP_PARENT(CLK_TOP_UNIVPLL3_D4), +}; + +static const struct mtk_parent hapll1_parents[] = { + TOP_PARENT(CLK_TOP_CLK26M), + TOP_PARENT(CLK_TOP_APLL1), + TOP_PARENT(CLK_TOP_APLL1_D2), + TOP_PARENT(CLK_TOP_APLL1_D3), + TOP_PARENT(CLK_TOP_APLL1_D4), + TOP_PARENT(CLK_TOP_APLL1_D8), + TOP_PARENT(CLK_TOP_APLL1_D16), + TOP_PARENT(CLK_TOP_SYS_26M_D2), +}; + +static const struct mtk_parent hapll2_parents[] = { + TOP_PARENT(CLK_TOP_CLK26M), + TOP_PARENT(CLK_TOP_APLL2), + TOP_PARENT(CLK_TOP_APLL2_D2), + TOP_PARENT(CLK_TOP_APLL2_D3), + TOP_PARENT(CLK_TOP_APLL2_D4), + TOP_PARENT(CLK_TOP_APLL2_D8), + TOP_PARENT(CLK_TOP_APLL2_D16), + TOP_PARENT(CLK_TOP_SYS_26M_D2), +}; + +static const struct mtk_parent asm_l_parents[] = { + TOP_PARENT(CLK_TOP_CLK26M), + TOP_PARENT(CLK_TOP_UNIVPLL2_D4), + TOP_PARENT(CLK_TOP_UNIVPLL2_D2), + TOP_PARENT(CLK_TOP_SYSPLL_D5), +}; + +static const struct mtk_parent aud_spdif_parents[] = { + TOP_PARENT(CLK_TOP_CLK26M), + TOP_PARENT(CLK_TOP_UNIVPLL_D2), + TOP_PARENT(CLK_TOP_DSPPLL), +}; + +static const struct mtk_parent aud_1_parents[] = { + TOP_PARENT(CLK_TOP_CLK26M), + TOP_PARENT(CLK_TOP_APLL1), +}; + +static const struct mtk_parent aud_2_parents[] = { + TOP_PARENT(CLK_TOP_CLK26M), + TOP_PARENT(CLK_TOP_APLL2), +}; + +static const struct mtk_parent ssusb_sys_parents[] = { + TOP_PARENT(CLK_TOP_CLK26M), + TOP_PARENT(CLK_TOP_UNIVPLL3_D4), + TOP_PARENT(CLK_TOP_UNIVPLL2_D4), + TOP_PARENT(CLK_TOP_UNIVPLL3_D2), +}; + +static const struct mtk_parent spm_parents[] = { + TOP_PARENT(CLK_TOP_CLK26M), + TOP_PARENT(CLK_TOP_SYSPLL1_D8), +}; + +static const struct mtk_parent i2c_parents[] = { + TOP_PARENT(CLK_TOP_CLK26M), + TOP_PARENT(CLK_TOP_SYS_26M_D2), + TOP_PARENT(CLK_TOP_UNIVPLL3_D4), + TOP_PARENT(CLK_TOP_UNIVPLL3_D2), + TOP_PARENT(CLK_TOP_SYSPLL1_D8), + TOP_PARENT(CLK_TOP_SYSPLL2_D8), + TOP_PARENT(CLK_TOP_CLK32K), +}; + +static const struct mtk_parent pwm_parents[] = { + TOP_PARENT(CLK_TOP_CLK26M), + TOP_PARENT(CLK_TOP_UNIVPLL3_D4), + TOP_PARENT(CLK_TOP_SYSPLL1_D8), + TOP_PARENT(CLK_TOP_UNIVPLL2_D4), + TOP_PARENT(CLK_TOP_SYS_26M_D2), + TOP_PARENT(CLK_TOP_CLK32K), +}; + +static const struct mtk_parent dsp_parents[] = { + TOP_PARENT(CLK_TOP_CLK26M), + TOP_PARENT(CLK_TOP_DSPPLL), + TOP_PARENT(CLK_TOP_DSPPLL_D2), + TOP_PARENT(CLK_TOP_DSPPLL_D4), + TOP_PARENT(CLK_TOP_DSPPLL_D8), + TOP_PARENT(CLK_TOP_APLL2_D4), + TOP_PARENT(CLK_TOP_SYS_26M_D2), + TOP_PARENT(CLK_TOP_CLK32K), +}; + +static const struct mtk_parent nfi2x_parents[] = { + TOP_PARENT(CLK_TOP_CLK26M), + TOP_PARENT(CLK_TOP_SYSPLL2_D2), + TOP_PARENT(CLK_TOP_SYSPLL_D7), + TOP_PARENT(CLK_TOP_SYSPLL_D3), + TOP_PARENT(CLK_TOP_SYSPLL2_D4), + TOP_PARENT(CLK_TOP_MSDCPLL_D2), + TOP_PARENT(CLK_TOP_UNIVPLL1_D2), + TOP_PARENT(CLK_TOP_UNIVPLL_D5), +}; + +static const struct mtk_parent spinfi_parents[] = { + TOP_PARENT(CLK_TOP_CLK26M), + TOP_PARENT(CLK_TOP_UNIVPLL2_D8), + TOP_PARENT(CLK_TOP_UNIVPLL3_D4), + TOP_PARENT(CLK_TOP_SYSPLL1_D8), + TOP_PARENT(CLK_TOP_SYSPLL4_D2), + TOP_PARENT(CLK_TOP_SYSPLL2_D4), + TOP_PARENT(CLK_TOP_UNIVPLL2_D4), + TOP_PARENT(CLK_TOP_UNIVPLL3_D2), +}; + +static const struct mtk_parent ecc_parents[] = { + TOP_PARENT(CLK_TOP_CLK26M), + TOP_PARENT(CLK_TOP_SYSPLL_D5), + TOP_PARENT(CLK_TOP_SYSPLL_D3), + TOP_PARENT(CLK_TOP_UNIVPLL_D3), +}; + +static const struct mtk_parent gcpu_parents[] = { + TOP_PARENT(CLK_TOP_CLK26M), + TOP_PARENT(CLK_TOP_UNIVPLL_D3), + TOP_PARENT(CLK_TOP_SYSPLL_D3), + TOP_PARENT(CLK_TOP_UNIVPLL1_D2), + TOP_PARENT(CLK_TOP_SYSPLL1_D2), + TOP_PARENT(CLK_TOP_UNIVPLL2_D2), }; -static const int gcpu_cpm_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_UNIVPLL2_D2, - CLK_TOP_SYSPLL2_D2, - CLK_TOP_UNIVPLL1_D4 +static const struct mtk_parent gcpu_cpm_parents[] = { + TOP_PARENT(CLK_TOP_CLK26M), + TOP_PARENT(CLK_TOP_UNIVPLL2_D2), + TOP_PARENT(CLK_TOP_SYSPLL2_D2), + TOP_PARENT(CLK_TOP_UNIVPLL1_D4), }; -static const int mbist_diag_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_SYS_26M_D2 -}; - -static const int ip0_nna_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_DSPPLL, - CLK_TOP_DSPPLL_D2, - CLK_TOP_DSPPLL_D4, - CLK_TOP_IPPLL, - CLK_TOP_SYS_26M_D2, - CLK_TOP_IPPLL_D2, - CLK_TOP_MSDCPLL_D2 -}; - -static const int ip2_wfst_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_UNIVPLL_D3, - CLK_TOP_UNIVPLL1_D2, - CLK_TOP_UNIVPLL2_D2, - CLK_TOP_IPPLL, - CLK_TOP_IPPLL_D2, - CLK_TOP_SYS_26M_D2, - CLK_TOP_MSDCPLL -}; - -static const int sflash_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_SYSPLL1_D16, - CLK_TOP_SYSPLL2_D8, - CLK_TOP_SYSPLL3_D4, - CLK_TOP_UNIVPLL3_D4, - CLK_TOP_UNIVPLL1_D8, - CLK_TOP_USB20_192M_D2, - CLK_TOP_UNIVPLL2_D4 -}; - -static const int sram_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_DSPPLL, - CLK_TOP_UNIVPLL_D3, - CLK_TOP_SYSPLL1_D2, - CLK_TOP_APLL1, - CLK_TOP_APLL2, - CLK_TOP_SYSPLL1_D4, - CLK_TOP_SYS_26M_D2 -}; - -static const int mm_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_SYSPLL_D3, - CLK_TOP_SYSPLL1_D2, - CLK_TOP_SYSPLL_D5, - CLK_TOP_SYSPLL1_D4, - CLK_TOP_UNIVPLL_D5, - CLK_TOP_UNIVPLL1_D2, - CLK_TOP_UNIVPLL_D3 -}; - -static const int dpi0_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_TCONPLL_D2, - CLK_TOP_TCONPLL_D4, - CLK_TOP_TCONPLL_D8, - CLK_TOP_TCONPLL_D16, - CLK_TOP_TCONPLL_D32, - CLK_TOP_TCONPLL_D64 -}; +static const struct mtk_parent mbist_diag_parents[] = { + TOP_PARENT(CLK_TOP_CLK26M), + TOP_PARENT(CLK_TOP_SYS_26M_D2), +}; + +static const struct mtk_parent ip0_nna_parents[] = { + TOP_PARENT(CLK_TOP_CLK26M), + TOP_PARENT(CLK_TOP_DSPPLL), + TOP_PARENT(CLK_TOP_DSPPLL_D2), + TOP_PARENT(CLK_TOP_DSPPLL_D4), + TOP_PARENT(CLK_TOP_IPPLL), + TOP_PARENT(CLK_TOP_SYS_26M_D2), + TOP_PARENT(CLK_TOP_IPPLL_D2), + TOP_PARENT(CLK_TOP_MSDCPLL_D2), +}; + +static const struct mtk_parent ip2_wfst_parents[] = { + TOP_PARENT(CLK_TOP_CLK26M), + TOP_PARENT(CLK_TOP_UNIVPLL_D3), + TOP_PARENT(CLK_TOP_UNIVPLL1_D2), + TOP_PARENT(CLK_TOP_UNIVPLL2_D2), + TOP_PARENT(CLK_TOP_IPPLL), + TOP_PARENT(CLK_TOP_IPPLL_D2), + TOP_PARENT(CLK_TOP_SYS_26M_D2), + TOP_PARENT(CLK_TOP_MSDCPLL), +}; + +static const struct mtk_parent sflash_parents[] = { + TOP_PARENT(CLK_TOP_CLK26M), + TOP_PARENT(CLK_TOP_SYSPLL1_D16), + TOP_PARENT(CLK_TOP_SYSPLL2_D8), + TOP_PARENT(CLK_TOP_SYSPLL3_D4), + TOP_PARENT(CLK_TOP_UNIVPLL3_D4), + TOP_PARENT(CLK_TOP_UNIVPLL1_D8), + TOP_PARENT(CLK_TOP_USB20_192M_D2), + TOP_PARENT(CLK_TOP_UNIVPLL2_D4), +}; + +static const struct mtk_parent sram_parents[] = { + TOP_PARENT(CLK_TOP_CLK26M), + TOP_PARENT(CLK_TOP_DSPPLL), + TOP_PARENT(CLK_TOP_UNIVPLL_D3), + TOP_PARENT(CLK_TOP_SYSPLL1_D2), + TOP_PARENT(CLK_TOP_APLL1), + TOP_PARENT(CLK_TOP_APLL2), + TOP_PARENT(CLK_TOP_SYSPLL1_D4), + TOP_PARENT(CLK_TOP_SYS_26M_D2), +}; + +static const struct mtk_parent mm_parents[] = { + TOP_PARENT(CLK_TOP_CLK26M), + TOP_PARENT(CLK_TOP_SYSPLL_D3), + TOP_PARENT(CLK_TOP_SYSPLL1_D2), + TOP_PARENT(CLK_TOP_SYSPLL_D5), + TOP_PARENT(CLK_TOP_SYSPLL1_D4), + TOP_PARENT(CLK_TOP_UNIVPLL_D5), + TOP_PARENT(CLK_TOP_UNIVPLL1_D2), + TOP_PARENT(CLK_TOP_UNIVPLL_D3), +}; + +static const struct mtk_parent dpi0_parents[] = { + TOP_PARENT(CLK_TOP_CLK26M), + TOP_PARENT(CLK_TOP_TCONPLL_D2), + TOP_PARENT(CLK_TOP_TCONPLL_D4), + TOP_PARENT(CLK_TOP_TCONPLL_D8), + TOP_PARENT(CLK_TOP_TCONPLL_D16), + TOP_PARENT(CLK_TOP_TCONPLL_D32), + TOP_PARENT(CLK_TOP_TCONPLL_D64), +}; -static const int dbg_atclk_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_UNIVPLL1_D2, - CLK_TOP_UNIVPLL_D5 +static const struct mtk_parent dbg_atclk_parents[] = { + TOP_PARENT(CLK_TOP_CLK26M), + TOP_PARENT(CLK_TOP_UNIVPLL1_D2), + TOP_PARENT(CLK_TOP_UNIVPLL_D5), }; -static const int occ_104m_parents[] = { - CLK_TOP_UNIVPLL2_D4, - CLK_TOP_UNIVPLL2_D8 +static const struct mtk_parent occ_104m_parents[] = { + TOP_PARENT(CLK_TOP_UNIVPLL2_D4), + TOP_PARENT(CLK_TOP_UNIVPLL2_D8), }; -static const int occ_68m_parents[] = { - CLK_TOP_SYSPLL1_D8, - CLK_TOP_UNIVPLL2_D8 -}; +static const struct mtk_parent occ_68m_parents[] = { + TOP_PARENT(CLK_TOP_SYSPLL1_D8), + TOP_PARENT(CLK_TOP_UNIVPLL2_D8), +}; -static const int occ_182m_parents[] = { - CLK_TOP_SYSPLL2_D2, - CLK_TOP_UNIVPLL1_D4, - CLK_TOP_UNIVPLL2_D8 +static const struct mtk_parent occ_182m_parents[] = { + TOP_PARENT(CLK_TOP_SYSPLL2_D2), + TOP_PARENT(CLK_TOP_UNIVPLL1_D4), + TOP_PARENT(CLK_TOP_UNIVPLL2_D8), }; static const struct mtk_composite top_muxes[] = { /* CLK_CFG_0 */ - MUX_CLR_SET_UPD_FLAGS(CLK_TOP_AXI_SEL, axi_parents, + MUX_MIXED_CLR_SET_UPD_FLAGS(CLK_TOP_AXI_SEL, axi_parents, 0x040, 0x044, 0x048, 0, 3, 7, 0x4, 0, CLK_MUX_SETCLR_UPD), - MUX_CLR_SET_UPD_FLAGS(CLK_TOP_MEM_SEL, mem_parents, + MUX_MIXED_CLR_SET_UPD_FLAGS(CLK_TOP_MEM_SEL, mem_parents, 0x040, 0x044, 0x048, 8, 2, 15, 0x4, 1, CLK_MUX_SETCLR_UPD), - MUX_CLR_SET_UPD_FLAGS(CLK_TOP_UART_SEL, uart_parents, + MUX_MIXED_CLR_SET_UPD_FLAGS(CLK_TOP_UART_SEL, uart_parents, 0x040, 0x044, 0x048, 16, 1, 23, 0x4, 2, CLK_MUX_SETCLR_UPD), - MUX_CLR_SET_UPD_FLAGS(CLK_TOP_SPI_SEL, spi_parents, + MUX_MIXED_CLR_SET_UPD_FLAGS(CLK_TOP_SPI_SEL, spi_parents, 0x040, 0x044, 0x048, 24, 3, 31, 0x4, 3, CLK_MUX_SETCLR_UPD), /* CLK_CFG_1 */ - MUX_CLR_SET_UPD_FLAGS(CLK_TOP_SPIS_SEL, spis_parents, + MUX_MIXED_CLR_SET_UPD_FLAGS(CLK_TOP_SPIS_SEL, spis_parents, 0x050, 0x054, 0x058, 0, 3, 7, 0x4, 4, CLK_MUX_SETCLR_UPD), - MUX_CLR_SET_UPD_FLAGS(CLK_TOP_MSDC50_0_HC_SEL, msdc50_0_hc_parents, + MUX_MIXED_CLR_SET_UPD_FLAGS(CLK_TOP_MSDC50_0_HC_SEL, msdc50_0_hc_parents, 0x050, 0x054, 0x058, 8, 2, 15, 0x4, 5, CLK_MUX_SETCLR_UPD), - MUX_CLR_SET_UPD_FLAGS(CLK_TOP_MSDC2_2_HC_SEL, msdc50_0_hc_parents, + MUX_MIXED_CLR_SET_UPD_FLAGS(CLK_TOP_MSDC2_2_HC_SEL, msdc50_0_hc_parents, 0x050, 0x054, 0x058, 16, 2, 23, 0x4, 6, CLK_MUX_SETCLR_UPD), - MUX_CLR_SET_UPD_FLAGS(CLK_TOP_MSDC50_0_SEL, msdc50_0_parents, + MUX_MIXED_CLR_SET_UPD_FLAGS(CLK_TOP_MSDC50_0_SEL, msdc50_0_parents, 0x050, 0x054, 0x058, 24, 3, 31, 0x4, 7, CLK_MUX_SETCLR_UPD), /* CLK_CFG_2 */ - MUX_CLR_SET_UPD_FLAGS(CLK_TOP_MSDC50_2_SEL, msdc50_2_parents, + MUX_MIXED_CLR_SET_UPD_FLAGS(CLK_TOP_MSDC50_2_SEL, msdc50_2_parents, 0x060, 0x064, 0x068, 0, 3, 7, 0x4, 8, CLK_MUX_SETCLR_UPD), - MUX_CLR_SET_UPD_FLAGS(CLK_TOP_MSDC30_1_SEL, msdc50_0_parents, + MUX_MIXED_CLR_SET_UPD_FLAGS(CLK_TOP_MSDC30_1_SEL, msdc50_0_parents, 0x060, 0x064, 0x068, 8, 3, 15, 0x4, 9, CLK_MUX_SETCLR_UPD), - MUX_CLR_SET_UPD_FLAGS(CLK_TOP_AUDIO_SEL, audio_parents, + MUX_MIXED_CLR_SET_UPD_FLAGS(CLK_TOP_AUDIO_SEL, audio_parents, 0x060, 0x064, 0x068, 16, 2, 23, 0x4, 10, CLK_MUX_SETCLR_UPD), - MUX_CLR_SET_UPD_FLAGS(CLK_TOP_AUD_INTBUS_SEL, aud_intbus_parents, + MUX_MIXED_CLR_SET_UPD_FLAGS(CLK_TOP_AUD_INTBUS_SEL, aud_intbus_parents, 0x060, 0x064, 0x068, 24, 3, 31, 0x4, 11, CLK_MUX_SETCLR_UPD), /* CLK_CFG_3 */ - MUX_CLR_SET_UPD_FLAGS(CLK_TOP_HAPLL1_SEL, hapll1_parents, + MUX_MIXED_CLR_SET_UPD_FLAGS(CLK_TOP_HAPLL1_SEL, hapll1_parents, 0x070, 0x074, 0x078, 0, 3, 7, 0x4, 12, CLK_MUX_SETCLR_UPD), - MUX_CLR_SET_UPD_FLAGS(CLK_TOP_HAPLL2_SEL, hapll2_parents, + MUX_MIXED_CLR_SET_UPD_FLAGS(CLK_TOP_HAPLL2_SEL, hapll2_parents, 0x070, 0x074, 0x078, 8, 3, 15, 0x4, 13, CLK_MUX_SETCLR_UPD), - MUX_CLR_SET_UPD_FLAGS(CLK_TOP_A2SYS_SEL, hapll1_parents, + MUX_MIXED_CLR_SET_UPD_FLAGS(CLK_TOP_A2SYS_SEL, hapll1_parents, 0x070, 0x074, 0x078, 16, 3, 23, 0x4, 14, CLK_MUX_SETCLR_UPD), - MUX_CLR_SET_UPD_FLAGS(CLK_TOP_A1SYS_SEL, hapll2_parents, + MUX_MIXED_CLR_SET_UPD_FLAGS(CLK_TOP_A1SYS_SEL, hapll2_parents, 0x070, 0x074, 0x078, 24, 3, 31, 0x4, 15, CLK_MUX_SETCLR_UPD), /* CLK_CFG_4 */ - MUX_CLR_SET_UPD_FLAGS(CLK_TOP_ASM_L_SEL, asm_l_parents, + MUX_MIXED_CLR_SET_UPD_FLAGS(CLK_TOP_ASM_L_SEL, asm_l_parents, 0x080, 0x084, 0x088, 0, 2, 7, 0x4, 16, CLK_MUX_SETCLR_UPD), - MUX_CLR_SET_UPD_FLAGS(CLK_TOP_ASM_M_SEL, asm_l_parents, + MUX_MIXED_CLR_SET_UPD_FLAGS(CLK_TOP_ASM_M_SEL, asm_l_parents, 0x080, 0x084, 0x088, 8, 2, 15, 0x4, 17, CLK_MUX_SETCLR_UPD), - MUX_CLR_SET_UPD_FLAGS(CLK_TOP_ASM_H_SEL, asm_l_parents, + MUX_MIXED_CLR_SET_UPD_FLAGS(CLK_TOP_ASM_H_SEL, asm_l_parents, 0x080, 0x084, 0x088, 16, 2, 23, 0x4, 18, CLK_MUX_SETCLR_UPD), - MUX_CLR_SET_UPD_FLAGS(CLK_TOP_AUD_SPDIF_SEL, aud_spdif_parents, + MUX_MIXED_CLR_SET_UPD_FLAGS(CLK_TOP_AUD_SPDIF_SEL, aud_spdif_parents, 0x080, 0x084, 0x088, 24, 2, 31, 0x4, 19, CLK_MUX_SETCLR_UPD), /* CLK_CFG_5 */ - MUX_CLR_SET_UPD_FLAGS(CLK_TOP_AUD_1_SEL, aud_1_parents, + MUX_MIXED_CLR_SET_UPD_FLAGS(CLK_TOP_AUD_1_SEL, aud_1_parents, 0x090, 0x094, 0x098, 0, 1, 7, 0x4, 20, CLK_MUX_SETCLR_UPD), - MUX_CLR_SET_UPD_FLAGS(CLK_TOP_AUD_2_SEL, aud_2_parents, + MUX_MIXED_CLR_SET_UPD_FLAGS(CLK_TOP_AUD_2_SEL, aud_2_parents, 0x090, 0x094, 0x098, 8, 1, 15, 0x4, 21, CLK_MUX_SETCLR_UPD), - MUX_CLR_SET_UPD_FLAGS(CLK_TOP_SSUSB_SYS_SEL, ssusb_sys_parents, + MUX_MIXED_CLR_SET_UPD_FLAGS(CLK_TOP_SSUSB_SYS_SEL, ssusb_sys_parents, 0x090, 0x094, 0x098, 16, 2, 23, 0x4, 22, CLK_MUX_SETCLR_UPD), - MUX_CLR_SET_UPD_FLAGS(CLK_TOP_SSUSB_XHCI_SEL, ssusb_sys_parents, + MUX_MIXED_CLR_SET_UPD_FLAGS(CLK_TOP_SSUSB_XHCI_SEL, ssusb_sys_parents, 0x090, 0x094, 0x098, 24, 2, 31, 0x4, 23, CLK_MUX_SETCLR_UPD), /* CLK_CFG_6 */ - MUX_CLR_SET_UPD_FLAGS(CLK_TOP_SPM_SEL, spm_parents, + MUX_MIXED_CLR_SET_UPD_FLAGS(CLK_TOP_SPM_SEL, spm_parents, 0x0a0, 0x0a4, 0x0a8, 0, 1, 7, 0x4, 24, CLK_MUX_SETCLR_UPD), - MUX_CLR_SET_UPD_FLAGS(CLK_TOP_I2C_SEL, i2c_parents, + MUX_MIXED_CLR_SET_UPD_FLAGS(CLK_TOP_I2C_SEL, i2c_parents, 0x0a0, 0x0a4, 0x0a8, 8, 3, 15, 0x4, 25, CLK_MUX_SETCLR_UPD), - MUX_CLR_SET_UPD_FLAGS(CLK_TOP_PWM_SEL, pwm_parents, + MUX_MIXED_CLR_SET_UPD_FLAGS(CLK_TOP_PWM_SEL, pwm_parents, 0x0a0, 0x0a4, 0x0a8, 16, 3, 23, 0x4, 26, CLK_MUX_SETCLR_UPD), - MUX_CLR_SET_UPD_FLAGS(CLK_TOP_DSP_SEL, dsp_parents, + MUX_MIXED_CLR_SET_UPD_FLAGS(CLK_TOP_DSP_SEL, dsp_parents, 0x0a0, 0x0a4, 0x0a8, 24, 3, 31, 0x4, 27, CLK_MUX_SETCLR_UPD), /* CLK_CFG_7 */ - MUX_CLR_SET_UPD_FLAGS(CLK_TOP_NFI2X_SEL, nfi2x_parents, + MUX_MIXED_CLR_SET_UPD_FLAGS(CLK_TOP_NFI2X_SEL, nfi2x_parents, 0x0b0, 0x0b4, 0x0b8, 0, 3, 7, 0x4, 28, CLK_MUX_SETCLR_UPD), - MUX_CLR_SET_UPD_FLAGS(CLK_TOP_SPINFI_SEL, spinfi_parents, + MUX_MIXED_CLR_SET_UPD_FLAGS(CLK_TOP_SPINFI_SEL, spinfi_parents, 0x0b0, 0x0b4, 0x0b8, 8, 3, 15, 0x4, 29, CLK_MUX_SETCLR_UPD), - MUX_CLR_SET_UPD_FLAGS(CLK_TOP_ECC_SEL, ecc_parents, + MUX_MIXED_CLR_SET_UPD_FLAGS(CLK_TOP_ECC_SEL, ecc_parents, 0x0b0, 0x0b4, 0x0b8, 16, 2, 23, 0x4, 30, CLK_MUX_SETCLR_UPD), - MUX_CLR_SET_UPD_FLAGS(CLK_TOP_GCPU_SEL, gcpu_parents, + MUX_MIXED_CLR_SET_UPD_FLAGS(CLK_TOP_GCPU_SEL, gcpu_parents, 0x0b0, 0x0b4, 0x0b8, 24, 3, 31, 0x4, 31, CLK_MUX_SETCLR_UPD), /* CLK_CFG_8 */ - MUX_CLR_SET_UPD_FLAGS(CLK_TOP_GCPU_CPM_SEL, gcpu_cpm_parents, + MUX_MIXED_CLR_SET_UPD_FLAGS(CLK_TOP_GCPU_CPM_SEL, gcpu_cpm_parents, 0x0c0, 0x0c4, 0x0c8, 0, 2, 7, 0x8, 0, CLK_MUX_SETCLR_UPD), - MUX_CLR_SET_UPD_FLAGS(CLK_TOP_MBIST_DIAG_SEL, mbist_diag_parents, + MUX_MIXED_CLR_SET_UPD_FLAGS(CLK_TOP_MBIST_DIAG_SEL, mbist_diag_parents, 0x0c0, 0x0c4, 0x0c8, 8, 1, 15, 0x8, 1, CLK_MUX_SETCLR_UPD), - MUX_CLR_SET_UPD_FLAGS(CLK_TOP_IP0_NNA_SEL, ip0_nna_parents, + MUX_MIXED_CLR_SET_UPD_FLAGS(CLK_TOP_IP0_NNA_SEL, ip0_nna_parents, 0x0c0, 0x0c4, 0x0c8, 16, 3, 23, 0x8, 2, CLK_MUX_SETCLR_UPD), - MUX_CLR_SET_UPD_FLAGS(CLK_TOP_IP1_NNA_SEL, ip0_nna_parents, + MUX_MIXED_CLR_SET_UPD_FLAGS(CLK_TOP_IP1_NNA_SEL, ip0_nna_parents, 0x0c0, 0x0c4, 0x0c8, 24, 3, 31, 0x8, 3, CLK_MUX_SETCLR_UPD), /* CLK_CFG_9 */ - MUX_CLR_SET_UPD_FLAGS(CLK_TOP_IP2_WFST_SEL, ip2_wfst_parents, + MUX_MIXED_CLR_SET_UPD_FLAGS(CLK_TOP_IP2_WFST_SEL, ip2_wfst_parents, 0x0d0, 0x0d4, 0x0d8, 0, 3, 7, 0x8, 4, CLK_MUX_SETCLR_UPD), - MUX_CLR_SET_UPD_FLAGS(CLK_TOP_SFLASH_SEL, sflash_parents, + MUX_MIXED_CLR_SET_UPD_FLAGS(CLK_TOP_SFLASH_SEL, sflash_parents, 0x0d0, 0x0d4, 0x0d8, 8, 3, 15, 0x8, 5, CLK_MUX_SETCLR_UPD), - MUX_CLR_SET_UPD_FLAGS(CLK_TOP_SRAM_SEL, sram_parents, + MUX_MIXED_CLR_SET_UPD_FLAGS(CLK_TOP_SRAM_SEL, sram_parents, 0x0d0, 0x0d4, 0x0d8, 16, 3, 23, 0x8, 6, CLK_MUX_SETCLR_UPD), - MUX_CLR_SET_UPD_FLAGS(CLK_TOP_MM_SEL, mm_parents, + MUX_MIXED_CLR_SET_UPD_FLAGS(CLK_TOP_MM_SEL, mm_parents, 0x0d0, 0x0d4, 0x0d8, 24, 3, 31, 0x8, 7, CLK_MUX_SETCLR_UPD), /* CLK_CFG_10 */ - MUX_CLR_SET_UPD_FLAGS(CLK_TOP_DPI0_SEL, dpi0_parents, + MUX_MIXED_CLR_SET_UPD_FLAGS(CLK_TOP_DPI0_SEL, dpi0_parents, 0x0e0, 0x0e4, 0x0e8, 0, 3, 7, 0x8, 8, CLK_MUX_SETCLR_UPD), - MUX_CLR_SET_UPD_FLAGS(CLK_TOP_DBG_ATCLK_SEL, dbg_atclk_parents, + MUX_MIXED_CLR_SET_UPD_FLAGS(CLK_TOP_DBG_ATCLK_SEL, dbg_atclk_parents, 0x0e0, 0x0e4, 0x0e8, 8, 2, 15, 0x8, 9, CLK_MUX_SETCLR_UPD), - MUX_CLR_SET_UPD_FLAGS(CLK_TOP_OCC_104M_SEL, occ_104m_parents, + MUX_MIXED_CLR_SET_UPD_FLAGS(CLK_TOP_OCC_104M_SEL, occ_104m_parents, 0x0e0, 0x0e4, 0x0e8, 16, 1, 23, 0x8, 10, CLK_MUX_SETCLR_UPD), - MUX_CLR_SET_UPD_FLAGS(CLK_TOP_OCC_68M_SEL, occ_68m_parents, + MUX_MIXED_CLR_SET_UPD_FLAGS(CLK_TOP_OCC_68M_SEL, occ_68m_parents, 0x0e0, 0x0e4, 0x0e8, 24, 1, 31, 0x8, 11, CLK_MUX_SETCLR_UPD), /* CLK_CFG_11 */ - MUX_CLR_SET_UPD_FLAGS(CLK_TOP_OCC_182M_SEL, occ_182m_parents, + MUX_MIXED_CLR_SET_UPD_FLAGS(CLK_TOP_OCC_182M_SEL, occ_182m_parents, 0x0ec, 0x0f0, 0x0f4, 0, 2, 7, 0x8, 12, CLK_MUX_SETCLR_UPD), }; -- cgit v1.3.1 From 585748a7163cdcb195d62c693f1d325b51e9c6a5 Mon Sep 17 00:00:00 2001 From: David Lechner Date: Tue, 17 Mar 2026 18:23:25 -0500 Subject: clk: mediatek: mt8516: convert to struct mtk_parent Convert all parent clock arrays to use struct mtk_parent. This will allow us to simplify core code later by having only one possible data type for mux parent arrays. Reviewed-by: Julien Stephan Link: https://patch.msgid.link/20260317-clk-mtk-unify-mux-parents-v3-12-a4760f5b0a80@baylibre.com Signed-off-by: David Lechner --- drivers/clk/mediatek/clk-mt8516.c | 786 +++++++++++++++++++------------------- 1 file changed, 393 insertions(+), 393 deletions(-) diff --git a/drivers/clk/mediatek/clk-mt8516.c b/drivers/clk/mediatek/clk-mt8516.c index 9d03e245886..bf62a4aa3a4 100644 --- a/drivers/clk/mediatek/clk-mt8516.c +++ b/drivers/clk/mediatek/clk-mt8516.c @@ -116,432 +116,432 @@ static const struct mtk_fixed_factor top_fixed_divs[] = { FACTOR1(CLK_TOP_ETH_D2, CLK_TOP_ETH_SEL, 1, 2), }; -static const int uart0_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_UNIVPLL_D24, +static const struct mtk_parent uart0_parents[] = { + TOP_PARENT(CLK_TOP_CLK26M), + TOP_PARENT(CLK_TOP_UNIVPLL_D24), }; -static const int gfmux_emi1x_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_DMPLL, -}; - -static const int emi_ddrphy_parents[] = { - CLK_TOP_GFMUX_EMI1X_SEL, - CLK_TOP_GFMUX_EMI1X_SEL, -}; - -static const int ahb_infra_parents[] = { - CLK_TOP_CLK_NULL, - CLK_TOP_CLK26M, - CLK_TOP_MAINPLL_D11, - CLK_TOP_CLK_NULL, - CLK_TOP_MAINPLL_D12, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_MAINPLL_D10, -}; - -static const int csw_mux_mfg_parents[] = { - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_UNIVPLL_D3, - CLK_TOP_UNIVPLL_D2, - CLK_TOP_CLK26M, - CLK_TOP_MAINPLL_D4, - CLK_TOP_UNIVPLL_D24, - CLK_TOP_MMPLL380M, -}; - -static const int msdc0_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_UNIVPLL_D6, - CLK_TOP_MAINPLL_D8, - CLK_TOP_UNIVPLL_D8, - CLK_TOP_MAINPLL_D16, - CLK_TOP_MMPLL_200M, - CLK_TOP_MAINPLL_D12, - CLK_TOP_MMPLL_D2, -}; - -static const int pwm_mm_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_UNIVPLL_D12, -}; - -static const int uart1_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_UNIVPLL_D24, -}; - -static const int msdc1_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_UNIVPLL_D6, - CLK_TOP_MAINPLL_D8, - CLK_TOP_UNIVPLL_D8, - CLK_TOP_MAINPLL_D16, - CLK_TOP_MMPLL_200M, - CLK_TOP_MAINPLL_D12, - CLK_TOP_MMPLL_D2, -}; - -static const int spm_52m_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_UNIVPLL_D24, -}; - -static const int pmicspi_parents[] = { - CLK_TOP_UNIVPLL_D20, - CLK_TOP_USB_PHY48M, - CLK_TOP_UNIVPLL_D16, - CLK_TOP_CLK26M, -}; - -static const int qaxi_aud26m_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_AHB_INFRA_SEL, -}; - -static const int aud_intbus_parents[] = { - CLK_TOP_CLK_NULL, - CLK_TOP_CLK26M, - CLK_TOP_MAINPLL_D22, - CLK_TOP_CLK_NULL, - CLK_TOP_MAINPLL_D11, -}; - -static const int nfi2x_pad_parents[] = { - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK26M, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_MAINPLL_D12, - CLK_TOP_MAINPLL_D8, - CLK_TOP_CLK_NULL, - CLK_TOP_MAINPLL_D6, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_MAINPLL_D4, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_MAINPLL_D10, - CLK_TOP_MAINPLL_D7, - CLK_TOP_CLK_NULL, - CLK_TOP_MAINPLL_D5 -}; - -static const int nfi1x_pad_parents[] = { - CLK_TOP_AHB_INFRA_SEL, - CLK_TOP_NFI1X, -}; - -static const int mfg_mm_parents[] = { - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CSW_MUX_MFG_SEL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_MAINPLL_D3, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_MAINPLL_D5, - CLK_TOP_MAINPLL_D7, - CLK_TOP_CLK_NULL, - CLK_TOP_MAINPLL_D14 -}; - -static const int ddrphycfg_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_MAINPLL_D16 -}; - -static const int usb_78m_parents[] = { - CLK_TOP_CLK_NULL, - CLK_TOP_CLK26M, - CLK_TOP_UNIVPLL_D16, - CLK_TOP_CLK_NULL, - CLK_TOP_MAINPLL_D20, -}; - -static const int spinor_parents[] = { - CLK_TOP_CLK26M_D2, - CLK_TOP_CLK26M, - CLK_TOP_MAINPLL_D40, - CLK_TOP_UNIVPLL_D24, - CLK_TOP_UNIVPLL_D20, - CLK_TOP_MAINPLL_D20, - CLK_TOP_MAINPLL_D16, - CLK_TOP_UNIVPLL_D12 -}; - -static const int msdc2_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_UNIVPLL_D6, - CLK_TOP_MAINPLL_D8, - CLK_TOP_UNIVPLL_D8, - CLK_TOP_MAINPLL_D16, - CLK_TOP_MMPLL_200M, - CLK_TOP_MAINPLL_D12, - CLK_TOP_MMPLL_D2 -}; - -static const int eth_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_MAINPLL_D40, - CLK_TOP_UNIVPLL_D24, - CLK_TOP_UNIVPLL_D20, - CLK_TOP_MAINPLL_D20 -}; - -static const int axi_mfg_in_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_MAINPLL_D11, - CLK_TOP_UNIVPLL_D24, - CLK_TOP_MMPLL380M, -}; - -static const int slow_mfg_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_UNIVPLL_D12, - CLK_TOP_UNIVPLL_D24 +static const struct mtk_parent gfmux_emi1x_parents[] = { + TOP_PARENT(CLK_TOP_CLK26M), + TOP_PARENT(CLK_TOP_DMPLL), +}; + +static const struct mtk_parent emi_ddrphy_parents[] = { + TOP_PARENT(CLK_TOP_GFMUX_EMI1X_SEL), + TOP_PARENT(CLK_TOP_GFMUX_EMI1X_SEL), +}; + +static const struct mtk_parent ahb_infra_parents[] = { + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK26M), + TOP_PARENT(CLK_TOP_MAINPLL_D11), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_MAINPLL_D12), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_MAINPLL_D10), +}; + +static const struct mtk_parent csw_mux_mfg_parents[] = { + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_UNIVPLL_D3), + TOP_PARENT(CLK_TOP_UNIVPLL_D2), + TOP_PARENT(CLK_TOP_CLK26M), + TOP_PARENT(CLK_TOP_MAINPLL_D4), + TOP_PARENT(CLK_TOP_UNIVPLL_D24), + TOP_PARENT(CLK_TOP_MMPLL380M), +}; + +static const struct mtk_parent msdc0_parents[] = { + TOP_PARENT(CLK_TOP_CLK26M), + TOP_PARENT(CLK_TOP_UNIVPLL_D6), + TOP_PARENT(CLK_TOP_MAINPLL_D8), + TOP_PARENT(CLK_TOP_UNIVPLL_D8), + TOP_PARENT(CLK_TOP_MAINPLL_D16), + TOP_PARENT(CLK_TOP_MMPLL_200M), + TOP_PARENT(CLK_TOP_MAINPLL_D12), + TOP_PARENT(CLK_TOP_MMPLL_D2), +}; + +static const struct mtk_parent pwm_mm_parents[] = { + TOP_PARENT(CLK_TOP_CLK26M), + TOP_PARENT(CLK_TOP_UNIVPLL_D12), +}; + +static const struct mtk_parent uart1_parents[] = { + TOP_PARENT(CLK_TOP_CLK26M), + TOP_PARENT(CLK_TOP_UNIVPLL_D24), +}; + +static const struct mtk_parent msdc1_parents[] = { + TOP_PARENT(CLK_TOP_CLK26M), + TOP_PARENT(CLK_TOP_UNIVPLL_D6), + TOP_PARENT(CLK_TOP_MAINPLL_D8), + TOP_PARENT(CLK_TOP_UNIVPLL_D8), + TOP_PARENT(CLK_TOP_MAINPLL_D16), + TOP_PARENT(CLK_TOP_MMPLL_200M), + TOP_PARENT(CLK_TOP_MAINPLL_D12), + TOP_PARENT(CLK_TOP_MMPLL_D2), +}; + +static const struct mtk_parent spm_52m_parents[] = { + TOP_PARENT(CLK_TOP_CLK26M), + TOP_PARENT(CLK_TOP_UNIVPLL_D24), +}; + +static const struct mtk_parent pmicspi_parents[] = { + TOP_PARENT(CLK_TOP_UNIVPLL_D20), + TOP_PARENT(CLK_TOP_USB_PHY48M), + TOP_PARENT(CLK_TOP_UNIVPLL_D16), + TOP_PARENT(CLK_TOP_CLK26M), +}; + +static const struct mtk_parent qaxi_aud26m_parents[] = { + TOP_PARENT(CLK_TOP_CLK26M), + TOP_PARENT(CLK_TOP_AHB_INFRA_SEL), +}; + +static const struct mtk_parent aud_intbus_parents[] = { + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK26M), + TOP_PARENT(CLK_TOP_MAINPLL_D22), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_MAINPLL_D11), +}; + +static const struct mtk_parent nfi2x_pad_parents[] = { + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK26M), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_MAINPLL_D12), + TOP_PARENT(CLK_TOP_MAINPLL_D8), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_MAINPLL_D6), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_MAINPLL_D4), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_MAINPLL_D10), + TOP_PARENT(CLK_TOP_MAINPLL_D7), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_MAINPLL_D5), +}; + +static const struct mtk_parent nfi1x_pad_parents[] = { + TOP_PARENT(CLK_TOP_AHB_INFRA_SEL), + TOP_PARENT(CLK_TOP_NFI1X), +}; + +static const struct mtk_parent mfg_mm_parents[] = { + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CSW_MUX_MFG_SEL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_MAINPLL_D3), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_MAINPLL_D5), + TOP_PARENT(CLK_TOP_MAINPLL_D7), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_MAINPLL_D14), +}; + +static const struct mtk_parent ddrphycfg_parents[] = { + TOP_PARENT(CLK_TOP_CLK26M), + TOP_PARENT(CLK_TOP_MAINPLL_D16), +}; + +static const struct mtk_parent usb_78m_parents[] = { + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK26M), + TOP_PARENT(CLK_TOP_UNIVPLL_D16), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_MAINPLL_D20), +}; + +static const struct mtk_parent spinor_parents[] = { + TOP_PARENT(CLK_TOP_CLK26M_D2), + TOP_PARENT(CLK_TOP_CLK26M), + TOP_PARENT(CLK_TOP_MAINPLL_D40), + TOP_PARENT(CLK_TOP_UNIVPLL_D24), + TOP_PARENT(CLK_TOP_UNIVPLL_D20), + TOP_PARENT(CLK_TOP_MAINPLL_D20), + TOP_PARENT(CLK_TOP_MAINPLL_D16), + TOP_PARENT(CLK_TOP_UNIVPLL_D12), +}; + +static const struct mtk_parent msdc2_parents[] = { + TOP_PARENT(CLK_TOP_CLK26M), + TOP_PARENT(CLK_TOP_UNIVPLL_D6), + TOP_PARENT(CLK_TOP_MAINPLL_D8), + TOP_PARENT(CLK_TOP_UNIVPLL_D8), + TOP_PARENT(CLK_TOP_MAINPLL_D16), + TOP_PARENT(CLK_TOP_MMPLL_200M), + TOP_PARENT(CLK_TOP_MAINPLL_D12), + TOP_PARENT(CLK_TOP_MMPLL_D2), +}; + +static const struct mtk_parent eth_parents[] = { + TOP_PARENT(CLK_TOP_CLK26M), + TOP_PARENT(CLK_TOP_MAINPLL_D40), + TOP_PARENT(CLK_TOP_UNIVPLL_D24), + TOP_PARENT(CLK_TOP_UNIVPLL_D20), + TOP_PARENT(CLK_TOP_MAINPLL_D20), +}; + +static const struct mtk_parent axi_mfg_in_parents[] = { + TOP_PARENT(CLK_TOP_CLK26M), + TOP_PARENT(CLK_TOP_MAINPLL_D11), + TOP_PARENT(CLK_TOP_UNIVPLL_D24), + TOP_PARENT(CLK_TOP_MMPLL380M), +}; + +static const struct mtk_parent slow_mfg_parents[] = { + TOP_PARENT(CLK_TOP_CLK26M), + TOP_PARENT(CLK_TOP_UNIVPLL_D12), + TOP_PARENT(CLK_TOP_UNIVPLL_D24), }; - -static const int aud1_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_APLL1 -}; - -static const int aud2_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_APLL2 -}; - -static const int aud_engen1_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_RG_APLL1_D2_EN, - CLK_TOP_RG_APLL1_D4_EN, - CLK_TOP_RG_APLL1_D8_EN + +static const struct mtk_parent aud1_parents[] = { + TOP_PARENT(CLK_TOP_CLK26M), + TOP_PARENT(CLK_TOP_APLL1), +}; + +static const struct mtk_parent aud2_parents[] = { + TOP_PARENT(CLK_TOP_CLK26M), + TOP_PARENT(CLK_TOP_APLL2), +}; + +static const struct mtk_parent aud_engen1_parents[] = { + TOP_PARENT(CLK_TOP_CLK26M), + TOP_PARENT(CLK_TOP_RG_APLL1_D2_EN), + TOP_PARENT(CLK_TOP_RG_APLL1_D4_EN), + TOP_PARENT(CLK_TOP_RG_APLL1_D8_EN), }; -static const int aud_engen2_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_RG_APLL2_D2_EN, - CLK_TOP_RG_APLL2_D4_EN, - CLK_TOP_RG_APLL2_D8_EN +static const struct mtk_parent aud_engen2_parents[] = { + TOP_PARENT(CLK_TOP_CLK26M), + TOP_PARENT(CLK_TOP_RG_APLL2_D2_EN), + TOP_PARENT(CLK_TOP_RG_APLL2_D4_EN), + TOP_PARENT(CLK_TOP_RG_APLL2_D8_EN), }; -static const int i2c_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_UNIVPLL_D20, - CLK_TOP_UNIVPLL_D16, - CLK_TOP_UNIVPLL_D12 +static const struct mtk_parent i2c_parents[] = { + TOP_PARENT(CLK_TOP_CLK26M), + TOP_PARENT(CLK_TOP_UNIVPLL_D20), + TOP_PARENT(CLK_TOP_UNIVPLL_D16), + TOP_PARENT(CLK_TOP_UNIVPLL_D12), }; -static const int aud_i2s0_m_parents[] = { - CLK_TOP_RG_AUD1, - CLK_TOP_RG_AUD2 +static const struct mtk_parent aud_i2s0_m_parents[] = { + TOP_PARENT(CLK_TOP_RG_AUD1), + TOP_PARENT(CLK_TOP_RG_AUD2), }; -static const int pwm_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_UNIVPLL_D12 +static const struct mtk_parent pwm_parents[] = { + TOP_PARENT(CLK_TOP_CLK26M), + TOP_PARENT(CLK_TOP_UNIVPLL_D12), }; -static const int spi_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_UNIVPLL_D12, - CLK_TOP_UNIVPLL_D8, - CLK_TOP_UNIVPLL_D6 +static const struct mtk_parent spi_parents[] = { + TOP_PARENT(CLK_TOP_CLK26M), + TOP_PARENT(CLK_TOP_UNIVPLL_D12), + TOP_PARENT(CLK_TOP_UNIVPLL_D8), + TOP_PARENT(CLK_TOP_UNIVPLL_D6), }; -static const int aud_spdifin_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_UNIVPLL_D2 +static const struct mtk_parent aud_spdifin_parents[] = { + TOP_PARENT(CLK_TOP_CLK26M), + TOP_PARENT(CLK_TOP_UNIVPLL_D2), }; -static const int uart2_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_UNIVPLL_D24 +static const struct mtk_parent uart2_parents[] = { + TOP_PARENT(CLK_TOP_CLK26M), + TOP_PARENT(CLK_TOP_UNIVPLL_D24), }; -static const int bsi_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_MAINPLL_D10, - CLK_TOP_MAINPLL_D12, - CLK_TOP_MAINPLL_D20 +static const struct mtk_parent bsi_parents[] = { + TOP_PARENT(CLK_TOP_CLK26M), + TOP_PARENT(CLK_TOP_MAINPLL_D10), + TOP_PARENT(CLK_TOP_MAINPLL_D12), + TOP_PARENT(CLK_TOP_MAINPLL_D20), }; -static const int dbg_atclk_parents[] = { - CLK_TOP_CLK_NULL, - CLK_TOP_CLK26M, - CLK_TOP_MAINPLL_D5, - CLK_TOP_CLK_NULL, - CLK_TOP_UNIVPLL_D5 +static const struct mtk_parent dbg_atclk_parents[] = { + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK26M), + TOP_PARENT(CLK_TOP_MAINPLL_D5), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_UNIVPLL_D5), }; -static const int csw_nfiecc_parents[] = { - CLK_TOP_CLK_NULL, - CLK_TOP_MAINPLL_D7, - CLK_TOP_MAINPLL_D6, - CLK_TOP_CLK_NULL, - CLK_TOP_MAINPLL_D5 +static const struct mtk_parent csw_nfiecc_parents[] = { + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_MAINPLL_D7), + TOP_PARENT(CLK_TOP_MAINPLL_D6), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_MAINPLL_D5), }; -static const int nfiecc_parents[] = { - CLK_TOP_CLK_NULL, - CLK_TOP_NFI2X_PAD_SEL, - CLK_TOP_MAINPLL_D4, - CLK_TOP_CLK_NULL, - CLK_TOP_CSW_NFIECC_SEL, +static const struct mtk_parent nfiecc_parents[] = { + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_NFI2X_PAD_SEL), + TOP_PARENT(CLK_TOP_MAINPLL_D4), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CSW_NFIECC_SEL), }; static const struct mtk_composite top_muxes[] = { /* CLK_MUX_SEL0 */ - MUX(CLK_TOP_UART0_SEL, uart0_parents, 0x000, 0, 1), - MUX(CLK_TOP_GFMUX_EMI1X_SEL, gfmux_emi1x_parents, 0x000, 1, 1), - MUX(CLK_TOP_EMI_DDRPHY_SEL, emi_ddrphy_parents, 0x000, 2, 1), - MUX(CLK_TOP_AHB_INFRA_SEL, ahb_infra_parents, 0x000, 4, 4), - MUX(CLK_TOP_CSW_MUX_MFG_SEL, csw_mux_mfg_parents, 0x000, 8, 3), - MUX(CLK_TOP_MSDC0_SEL, msdc0_parents, 0x000, 11, 3), - MUX(CLK_TOP_PWM_MM_SEL, pwm_mm_parents, 0x000, 18, 1), - MUX(CLK_TOP_UART1_SEL, uart1_parents, 0x000, 19, 1), - MUX(CLK_TOP_MSDC1_SEL, msdc1_parents, 0x000, 20, 3), - MUX(CLK_TOP_SPM_52M_SEL, spm_52m_parents, 0x000, 23, 1), - MUX(CLK_TOP_PMICSPI_SEL, pmicspi_parents, 0x000, 24, 2), - MUX(CLK_TOP_QAXI_AUD26M_SEL, qaxi_aud26m_parents, 0x000, 26, 1), - MUX(CLK_TOP_AUD_INTBUS_SEL, aud_intbus_parents, 0x000, 27, 3), + MUX_MIXED(CLK_TOP_UART0_SEL, uart0_parents, 0x000, 0, 1), + MUX_MIXED(CLK_TOP_GFMUX_EMI1X_SEL, gfmux_emi1x_parents, 0x000, 1, 1), + MUX_MIXED(CLK_TOP_EMI_DDRPHY_SEL, emi_ddrphy_parents, 0x000, 2, 1), + MUX_MIXED(CLK_TOP_AHB_INFRA_SEL, ahb_infra_parents, 0x000, 4, 4), + MUX_MIXED(CLK_TOP_CSW_MUX_MFG_SEL, csw_mux_mfg_parents, 0x000, 8, 3), + MUX_MIXED(CLK_TOP_MSDC0_SEL, msdc0_parents, 0x000, 11, 3), + MUX_MIXED(CLK_TOP_PWM_MM_SEL, pwm_mm_parents, 0x000, 18, 1), + MUX_MIXED(CLK_TOP_UART1_SEL, uart1_parents, 0x000, 19, 1), + MUX_MIXED(CLK_TOP_MSDC1_SEL, msdc1_parents, 0x000, 20, 3), + MUX_MIXED(CLK_TOP_SPM_52M_SEL, spm_52m_parents, 0x000, 23, 1), + MUX_MIXED(CLK_TOP_PMICSPI_SEL, pmicspi_parents, 0x000, 24, 2), + MUX_MIXED(CLK_TOP_QAXI_AUD26M_SEL, qaxi_aud26m_parents, 0x000, 26, 1), + MUX_MIXED(CLK_TOP_AUD_INTBUS_SEL, aud_intbus_parents, 0x000, 27, 3), /* CLK_MUX_SEL1 */ - MUX(CLK_TOP_NFI2X_PAD_SEL, nfi2x_pad_parents, 0x004, 0, 7), - MUX(CLK_TOP_NFI1X_PAD_SEL, nfi1x_pad_parents, 0x004, 7, 1), - MUX(CLK_TOP_MFG_MM_SEL, mfg_mm_parents, 0x004, 8, 6), - MUX(CLK_TOP_DDRPHYCFG_SEL, ddrphycfg_parents, 0x004, 15, 1), - MUX(CLK_TOP_USB_78M_SEL, usb_78m_parents, 0x004, 20, 3), + MUX_MIXED(CLK_TOP_NFI2X_PAD_SEL, nfi2x_pad_parents, 0x004, 0, 7), + MUX_MIXED(CLK_TOP_NFI1X_PAD_SEL, nfi1x_pad_parents, 0x004, 7, 1), + MUX_MIXED(CLK_TOP_MFG_MM_SEL, mfg_mm_parents, 0x004, 8, 6), + MUX_MIXED(CLK_TOP_DDRPHYCFG_SEL, ddrphycfg_parents, 0x004, 15, 1), + MUX_MIXED(CLK_TOP_USB_78M_SEL, usb_78m_parents, 0x004, 20, 3), /* CLK_MUX_SEL8 */ - MUX(CLK_TOP_SPINOR_SEL, spinor_parents, 0x040, 0, 3), - MUX(CLK_TOP_MSDC2_SEL, msdc2_parents, 0x040, 3, 3), - MUX(CLK_TOP_ETH_SEL, eth_parents, 0x040, 6, 3), - MUX(CLK_TOP_AXI_MFG_IN_SEL, axi_mfg_in_parents, 0x040, 18, 2), - MUX(CLK_TOP_SLOW_MFG_SEL, slow_mfg_parents, 0x040, 20, 2), - MUX(CLK_TOP_AUD1_SEL, aud1_parents, 0x040, 22, 1), - MUX(CLK_TOP_AUD2_SEL, aud2_parents, 0x040, 23, 1), - MUX(CLK_TOP_AUD_ENGEN1_SEL, aud_engen1_parents, 0x040, 24, 2), - MUX(CLK_TOP_AUD_ENGEN2_SEL, aud_engen2_parents, 0x040, 26, 2), - MUX(CLK_TOP_I2C_SEL, i2c_parents, 0x040, 28, 2), + MUX_MIXED(CLK_TOP_SPINOR_SEL, spinor_parents, 0x040, 0, 3), + MUX_MIXED(CLK_TOP_MSDC2_SEL, msdc2_parents, 0x040, 3, 3), + MUX_MIXED(CLK_TOP_ETH_SEL, eth_parents, 0x040, 6, 3), + MUX_MIXED(CLK_TOP_AXI_MFG_IN_SEL, axi_mfg_in_parents, 0x040, 18, 2), + MUX_MIXED(CLK_TOP_SLOW_MFG_SEL, slow_mfg_parents, 0x040, 20, 2), + MUX_MIXED(CLK_TOP_AUD1_SEL, aud1_parents, 0x040, 22, 1), + MUX_MIXED(CLK_TOP_AUD2_SEL, aud2_parents, 0x040, 23, 1), + MUX_MIXED(CLK_TOP_AUD_ENGEN1_SEL, aud_engen1_parents, 0x040, 24, 2), + MUX_MIXED(CLK_TOP_AUD_ENGEN2_SEL, aud_engen2_parents, 0x040, 26, 2), + MUX_MIXED(CLK_TOP_I2C_SEL, i2c_parents, 0x040, 28, 2), /* CLK_MUX_SEL9 */ - MUX(CLK_TOP_AUD_I2S0_M_SEL, aud_i2s0_m_parents, 0x044, 12, 1), - MUX(CLK_TOP_AUD_I2S1_M_SEL, aud_i2s0_m_parents, 0x044, 13, 1), - MUX(CLK_TOP_AUD_I2S2_M_SEL, aud_i2s0_m_parents, 0x044, 14, 1), - MUX(CLK_TOP_AUD_I2S3_M_SEL, aud_i2s0_m_parents, 0x044, 15, 1), - MUX(CLK_TOP_AUD_I2S4_M_SEL, aud_i2s0_m_parents, 0x044, 16, 1), - MUX(CLK_TOP_AUD_I2S5_M_SEL, aud_i2s0_m_parents, 0x044, 17, 1), - MUX(CLK_TOP_AUD_SPDIF_B_SEL, aud_i2s0_m_parents, 0x044, 18, 1), + MUX_MIXED(CLK_TOP_AUD_I2S0_M_SEL, aud_i2s0_m_parents, 0x044, 12, 1), + MUX_MIXED(CLK_TOP_AUD_I2S1_M_SEL, aud_i2s0_m_parents, 0x044, 13, 1), + MUX_MIXED(CLK_TOP_AUD_I2S2_M_SEL, aud_i2s0_m_parents, 0x044, 14, 1), + MUX_MIXED(CLK_TOP_AUD_I2S3_M_SEL, aud_i2s0_m_parents, 0x044, 15, 1), + MUX_MIXED(CLK_TOP_AUD_I2S4_M_SEL, aud_i2s0_m_parents, 0x044, 16, 1), + MUX_MIXED(CLK_TOP_AUD_I2S5_M_SEL, aud_i2s0_m_parents, 0x044, 17, 1), + MUX_MIXED(CLK_TOP_AUD_SPDIF_B_SEL, aud_i2s0_m_parents, 0x044, 18, 1), /* CLK_MUX_SEL13 */ - MUX(CLK_TOP_PWM_SEL, pwm_parents, 0x07c, 0, 1), - MUX(CLK_TOP_SPI_SEL, spi_parents, 0x07c, 1, 2), - MUX(CLK_TOP_AUD_SPDIFIN_SEL, aud_spdifin_parents, 0x07c, 3, 1), - MUX(CLK_TOP_UART2_SEL, uart2_parents, 0x07c, 4, 1), - MUX(CLK_TOP_BSI_SEL, bsi_parents, 0x07c, 5, 2), - MUX(CLK_TOP_DBG_ATCLK_SEL, dbg_atclk_parents, 0x07c, 7, 3), - MUX(CLK_TOP_CSW_NFIECC_SEL, csw_nfiecc_parents, 0x07c, 10, 3), - MUX(CLK_TOP_NFIECC_SEL, nfiecc_parents, 0x07c, 13, 3), + MUX_MIXED(CLK_TOP_PWM_SEL, pwm_parents, 0x07c, 0, 1), + MUX_MIXED(CLK_TOP_SPI_SEL, spi_parents, 0x07c, 1, 2), + MUX_MIXED(CLK_TOP_AUD_SPDIFIN_SEL, aud_spdifin_parents, 0x07c, 3, 1), + MUX_MIXED(CLK_TOP_UART2_SEL, uart2_parents, 0x07c, 4, 1), + MUX_MIXED(CLK_TOP_BSI_SEL, bsi_parents, 0x07c, 5, 2), + MUX_MIXED(CLK_TOP_DBG_ATCLK_SEL, dbg_atclk_parents, 0x07c, 7, 3), + MUX_MIXED(CLK_TOP_CSW_NFIECC_SEL, csw_nfiecc_parents, 0x07c, 10, 3), + MUX_MIXED(CLK_TOP_NFIECC_SEL, nfiecc_parents, 0x07c, 13, 3), }; static const struct mtk_gate_regs top0_cg_regs = { -- cgit v1.3.1 From cc8738cadc5229a3e50f70d8f212817d7b000890 Mon Sep 17 00:00:00 2001 From: David Lechner Date: Tue, 17 Mar 2026 18:23:26 -0500 Subject: clk: mediatek: mt8518: convert to struct mtk_parent Convert all parent clock arrays to use struct mtk_parent. This will allow us to simplify core code later by having only one possible data type for mux parent arrays. Reviewed-by: Julien Stephan Link: https://patch.msgid.link/20260317-clk-mtk-unify-mux-parents-v3-13-a4760f5b0a80@baylibre.com Signed-off-by: David Lechner --- drivers/clk/mediatek/clk-mt8518.c | 2206 ++++++++++++++++++------------------- 1 file changed, 1103 insertions(+), 1103 deletions(-) diff --git a/drivers/clk/mediatek/clk-mt8518.c b/drivers/clk/mediatek/clk-mt8518.c index e7de9d33e00..482d1346da5 100644 --- a/drivers/clk/mediatek/clk-mt8518.c +++ b/drivers/clk/mediatek/clk-mt8518.c @@ -134,1125 +134,1125 @@ static const struct mtk_fixed_factor top_fixed_divs[] = { FACTOR1(CLK_TOP_AHB_INFRA_D2, CLK_TOP_AXIBUS_SEL, 1, 2), }; -static const int uart0_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_UNIVPLL_D24 -}; - -static const int emi1x_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_DMPLL -}; - -static const int emi_ddrphy_parents[] = { - CLK_TOP_EMI1X_SEL, - CLK_TOP_EMI1X_SEL -}; - -static const int msdc1_parents[] = { - CLK_TOP_CLK_NULL, - CLK_TOP_CLK26M, - CLK_TOP_UNIVPLL_D6, - CLK_TOP_CLK_NULL, - CLK_TOP_MAINPLL_D8, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_UNIVPLL_D8, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_MAINPLL_D16, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_MMPLL_D2, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_MAINPLL_D12 -}; - -static const int pwm_mm_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_UNIVPLL_D12 -}; - -static const int pmicspi_parents[] = { - CLK_TOP_UNIVPLL_D20, - CLK_TOP_USB20_48M, - CLK_TOP_UNIVPLL_D16, - CLK_TOP_CLK26M, - CLK_TOP_CLK26M_D2 -}; - -static const int nfi2x_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_MAINPLL_D4, - CLK_TOP_MAINPLL_D5, - CLK_TOP_MAINPLL_D6, - CLK_TOP_MAINPLL_D7, - CLK_TOP_MAINPLL_D8, - CLK_TOP_MAINPLL_D10, - CLK_TOP_MAINPLL_D12 -}; - -static const int ddrphycfg_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_MAINPLL_D16 -}; - -static const int smi_parents[] = { - CLK_TOP_CLK_NULL, - CLK_TOP_CLK26M, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_UNIVPLL_D4, - CLK_TOP_MAINPLL_D7, - CLK_TOP_CLK_NULL, - CLK_TOP_MAINPLL_D14 -}; - -static const int usb_parents[] = { - CLK_TOP_CLK_NULL, - CLK_TOP_CLK26M, - CLK_TOP_UNIVPLL_D16, - CLK_TOP_CLK_NULL, - CLK_TOP_MAINPLL_D20 -}; - -static const int spinor_parents[] = { - CLK_TOP_CLK26M_D2, - CLK_TOP_CLK26M, - CLK_TOP_MAINPLL_D40, - CLK_TOP_UNIVPLL_D24, - CLK_TOP_UNIVPLL_D20, - CLK_TOP_MAINPLL_D20, - CLK_TOP_MAINPLL_D16, - CLK_TOP_UNIVPLL_D12 -}; - -static const int eth_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_MAINPLL_D40, - CLK_TOP_UNIVPLL_D24, - CLK_TOP_UNIVPLL_D20, - CLK_TOP_MAINPLL_D20 -}; - -static const int aud1_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_APLL1_SRC_SEL -}; - -static const int aud2_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_APLL2_SRC_SEL -}; - -static const int i2c_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_USB20_48M, - CLK_TOP_UNIVPLL_D12, - CLK_TOP_UNIVPLL_D10, - CLK_TOP_UNIVPLL_D8 -}; - -static const int aud_i2s0_m_parents[] = { - CLK_TOP_AUD1, - CLK_TOP_AUD2 -}; - -static const int aud_spdifin_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_UNIVPLL_D2, - CLK_TOP_TVDPLL -}; - -static const int dbg_atclk_parents[] = { - CLK_TOP_CLK_NULL, - CLK_TOP_CLK26M, - CLK_TOP_MAINPLL_D5, - CLK_TOP_CLK_NULL, - CLK_TOP_UNIVPLL_D5 -}; - -static const int png_sys_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_UNIVPLL_D8, - CLK_TOP_MAINPLL_D7, - CLK_TOP_MAINPLL_D6, - CLK_TOP_MAINPLL_D5, - CLK_TOP_UNIVPLL_D3 -}; - -static const int sej_13m_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_CLK26M_D2 -}; - -static const int imgrz_sys_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_MAINPLL_D6, - CLK_TOP_MAINPLL_D7, - CLK_TOP_MAINPLL_D5, - CLK_TOP_UNIVPLL_D4, - CLK_TOP_UNIVPLL_D10, - CLK_TOP_UNIVPLL_D5, - CLK_TOP_UNIVPLL_D6 -}; - -static const int graph_eclk_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_MAINPLL_D6, - CLK_TOP_UNIVPLL_D8, - CLK_TOP_UNIVPLL_D16, - CLK_TOP_MAINPLL_D7, - CLK_TOP_UNIVPLL_D4, - CLK_TOP_UNIVPLL_D10, - CLK_TOP_UNIVPLL_D24, - CLK_TOP_MAINPLL_D8 -}; - -static const int fdbi_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_MAINPLL_D12, - CLK_TOP_MAINPLL_D14, - CLK_TOP_MAINPLL_D16, - CLK_TOP_UNIVPLL_D10, - CLK_TOP_UNIVPLL_D12, - CLK_TOP_UNIVPLL_D16, - CLK_TOP_UNIVPLL_D24, - CLK_TOP_TVDPLL_D2, - CLK_TOP_TVDPLL_D4, - CLK_TOP_TVDPLL_D8, - CLK_TOP_TVDPLL_D16 -}; - -static const int faudio_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_UNIVPLL_D24, - CLK_TOP_APLL1_D4, - CLK_TOP_APLL2_D4 -}; - -static const int fa2sys_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_APLL1_SRC_SEL, - CLK_TOP_RG_APLL1_D2, - CLK_TOP_RG_APLL1_D4, - CLK_TOP_RG_APLL1_D8, - CLK_TOP_RG_APLL1_D16, - CLK_TOP_CLK26M_D2, - CLK_TOP_RG_APLL1_D3 -}; - -static const int fa1sys_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_APLL2_SRC_SEL, - CLK_TOP_RG_APLL2_D2, - CLK_TOP_RG_APLL2_D4, - CLK_TOP_RG_APLL2_D8, - CLK_TOP_RG_APLL2_D16, - CLK_TOP_CLK26M_D2, - CLK_TOP_RG_APLL2_D3 -}; - -static const int fasm_m_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_UNIVPLL_D12, - CLK_TOP_UNIVPLL_D6, - CLK_TOP_MAINPLL_D7 -}; - -static const int fecc_ck_parents[] = { - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK26M, - CLK_TOP_UNIVPLL_D6, - CLK_TOP_CLK_NULL, - CLK_TOP_UNIVPLL_D4, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_UNIVPLL_D3, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_MAINPLL_D3 -}; - -static const int pe2_mac_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_MAINPLL_D11, - CLK_TOP_MAINPLL_D16, - CLK_TOP_UNIVPLL_D12, - CLK_TOP_UNIVPLL_D10 -}; - -static const int cmsys_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_UNIVPLL_D5, - CLK_TOP_UNIVPLL_D6, - CLK_TOP_MAINPLL_D5, - CLK_TOP_APLL2, - CLK_TOP_APLL2_D2, - CLK_TOP_APLL2_D4, - CLK_TOP_APLL2_D3 -}; - -static const int gcpu_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_MAINPLL_D4, - CLK_TOP_MAINPLL_D5, - CLK_TOP_MAINPLL_D6, - CLK_TOP_MAINPLL_D7, - CLK_TOP_UNIVPLL_D4, - CLK_TOP_UNIVPLL_D10, - CLK_TOP_UNIVPLL_D3 -}; - -static const int spis_ck_parents[] = { - CLK_TOP_CLK_NULL, - CLK_TOP_CLK26M, - CLK_TOP_UNIVPLL_D12, - CLK_TOP_CLK_NULL, - CLK_TOP_UNIVPLL_D8, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_UNIVPLL_D6, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_UNIVPLL_D5, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_UNIVPLL_D4, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_MAINPLL_D4, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_UNIVPLL_D3 -}; - -static const int apll1_ref_parents[] = { - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL -}; - -static const int int_32k_parents[] = { - CLK_TOP_CLK32K, - CLK_TOP_CLK26M_D793 -}; - -static const int apll1_src_parents[] = { - CLK_TOP_APLL1, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL -}; - -static const int apll2_src_parents[] = { - CLK_TOP_APLL2, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL -}; - -static const int faud_intbus_parents[] = { - CLK_TOP_CLK_NULL, - CLK_TOP_CLK26M, - CLK_TOP_MAINPLL_D11, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK26M, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_UNIVPLL_D10, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_RG_APLL2_D8, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK26M_D2, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_RG_APLL1_D8, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_UNIVPLL_D20 -}; - -static const int axibus_parents[] = { - CLK_TOP_CLK_NULL, - CLK_TOP_CLK26M, - CLK_TOP_MAINPLL_D11, - CLK_TOP_CLK_NULL, - CLK_TOP_MAINPLL_D12, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_UNIVPLL_D10, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK26M_D2, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_APLL2_D8 -}; - -static const int hapll1_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_APLL1_SRC_SEL, - CLK_TOP_RG_APLL1_D2, - CLK_TOP_RG_APLL1_D4, - CLK_TOP_RG_APLL1_D8, - CLK_TOP_RG_APLL1_D16, - CLK_TOP_CLK26M_D2, - CLK_TOP_CLK26M_D8, - CLK_TOP_RG_APLL1_D3 -}; - -static const int hapll2_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_APLL2_SRC_SEL, - CLK_TOP_RG_APLL2_D2, - CLK_TOP_RG_APLL2_D4, - CLK_TOP_RG_APLL2_D8, - CLK_TOP_RG_APLL2_D16, - CLK_TOP_CLK26M_D2, - CLK_TOP_CLK26M_D4, - CLK_TOP_RG_APLL2_D3 -}; - -static const int spinfi_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_UNIVPLL_D24, - CLK_TOP_UNIVPLL_D20, - CLK_TOP_MAINPLL_D22, - CLK_TOP_UNIVPLL_D16, - CLK_TOP_MAINPLL_D16, - CLK_TOP_UNIVPLL_D12, - CLK_TOP_UNIVPLL_D10, - CLK_TOP_MAINPLL_D11 -}; - -static const int msdc0_parents[] = { - CLK_TOP_CLK_NULL, - CLK_TOP_CLK26M, - CLK_TOP_UNIVPLL_D6, - CLK_TOP_CLK_NULL, - CLK_TOP_MAINPLL_D8, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_UNIVPLL_D8, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_MAINPLL_D16, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_MAINPLL_D12, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_APMIXED_MMPLL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_MMPLL_D2 -}; - -static const int msdc0_clk50_parents[] = { - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK26M, - CLK_TOP_UNIVPLL_D6, - CLK_TOP_CLK_NULL, - CLK_TOP_MAINPLL_D8, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_UNIVPLL_D8, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_MAINPLL_D6 -}; - -static const int msdc2_parents[] = { - CLK_TOP_CLK_NULL, - CLK_TOP_CLK26M, - CLK_TOP_UNIVPLL_D6, - CLK_TOP_CLK_NULL, - CLK_TOP_MAINPLL_D8, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_UNIVPLL_D8, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_MAINPLL_D16, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_MMPLL_D2, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_MAINPLL_D12, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_APMIXED_MMPLL -}; - -static const int disp_dpi_ck_parents[] = { - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK26M, - CLK_TOP_TVDPLL_D2, - CLK_TOP_CLK_NULL, - CLK_TOP_TVDPLL_D4, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_TVDPLL_D8, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_TVDPLL_D16 +static const struct mtk_parent uart0_parents[] = { + TOP_PARENT(CLK_TOP_CLK26M), + TOP_PARENT(CLK_TOP_UNIVPLL_D24), +}; + +static const struct mtk_parent emi1x_parents[] = { + TOP_PARENT(CLK_TOP_CLK26M), + TOP_PARENT(CLK_TOP_DMPLL), +}; + +static const struct mtk_parent emi_ddrphy_parents[] = { + TOP_PARENT(CLK_TOP_EMI1X_SEL), + TOP_PARENT(CLK_TOP_EMI1X_SEL), +}; + +static const struct mtk_parent msdc1_parents[] = { + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK26M), + TOP_PARENT(CLK_TOP_UNIVPLL_D6), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_MAINPLL_D8), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_UNIVPLL_D8), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_MAINPLL_D16), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_MMPLL_D2), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_MAINPLL_D12), +}; + +static const struct mtk_parent pwm_mm_parents[] = { + TOP_PARENT(CLK_TOP_CLK26M), + TOP_PARENT(CLK_TOP_UNIVPLL_D12), +}; + +static const struct mtk_parent pmicspi_parents[] = { + TOP_PARENT(CLK_TOP_UNIVPLL_D20), + TOP_PARENT(CLK_TOP_USB20_48M), + TOP_PARENT(CLK_TOP_UNIVPLL_D16), + TOP_PARENT(CLK_TOP_CLK26M), + TOP_PARENT(CLK_TOP_CLK26M_D2), +}; + +static const struct mtk_parent nfi2x_parents[] = { + TOP_PARENT(CLK_TOP_CLK26M), + TOP_PARENT(CLK_TOP_MAINPLL_D4), + TOP_PARENT(CLK_TOP_MAINPLL_D5), + TOP_PARENT(CLK_TOP_MAINPLL_D6), + TOP_PARENT(CLK_TOP_MAINPLL_D7), + TOP_PARENT(CLK_TOP_MAINPLL_D8), + TOP_PARENT(CLK_TOP_MAINPLL_D10), + TOP_PARENT(CLK_TOP_MAINPLL_D12), +}; + +static const struct mtk_parent ddrphycfg_parents[] = { + TOP_PARENT(CLK_TOP_CLK26M), + TOP_PARENT(CLK_TOP_MAINPLL_D16), +}; + +static const struct mtk_parent smi_parents[] = { + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK26M), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_UNIVPLL_D4), + TOP_PARENT(CLK_TOP_MAINPLL_D7), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_MAINPLL_D14), +}; + +static const struct mtk_parent usb_parents[] = { + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK26M), + TOP_PARENT(CLK_TOP_UNIVPLL_D16), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_MAINPLL_D20), +}; + +static const struct mtk_parent spinor_parents[] = { + TOP_PARENT(CLK_TOP_CLK26M_D2), + TOP_PARENT(CLK_TOP_CLK26M), + TOP_PARENT(CLK_TOP_MAINPLL_D40), + TOP_PARENT(CLK_TOP_UNIVPLL_D24), + TOP_PARENT(CLK_TOP_UNIVPLL_D20), + TOP_PARENT(CLK_TOP_MAINPLL_D20), + TOP_PARENT(CLK_TOP_MAINPLL_D16), + TOP_PARENT(CLK_TOP_UNIVPLL_D12), +}; + +static const struct mtk_parent eth_parents[] = { + TOP_PARENT(CLK_TOP_CLK26M), + TOP_PARENT(CLK_TOP_MAINPLL_D40), + TOP_PARENT(CLK_TOP_UNIVPLL_D24), + TOP_PARENT(CLK_TOP_UNIVPLL_D20), + TOP_PARENT(CLK_TOP_MAINPLL_D20), +}; + +static const struct mtk_parent aud1_parents[] = { + TOP_PARENT(CLK_TOP_CLK26M), + TOP_PARENT(CLK_TOP_APLL1_SRC_SEL), +}; + +static const struct mtk_parent aud2_parents[] = { + TOP_PARENT(CLK_TOP_CLK26M), + TOP_PARENT(CLK_TOP_APLL2_SRC_SEL), +}; + +static const struct mtk_parent i2c_parents[] = { + TOP_PARENT(CLK_TOP_CLK26M), + TOP_PARENT(CLK_TOP_USB20_48M), + TOP_PARENT(CLK_TOP_UNIVPLL_D12), + TOP_PARENT(CLK_TOP_UNIVPLL_D10), + TOP_PARENT(CLK_TOP_UNIVPLL_D8), +}; + +static const struct mtk_parent aud_i2s0_m_parents[] = { + TOP_PARENT(CLK_TOP_AUD1), + TOP_PARENT(CLK_TOP_AUD2), +}; + +static const struct mtk_parent aud_spdifin_parents[] = { + TOP_PARENT(CLK_TOP_CLK26M), + TOP_PARENT(CLK_TOP_UNIVPLL_D2), + TOP_PARENT(CLK_TOP_TVDPLL), +}; + +static const struct mtk_parent dbg_atclk_parents[] = { + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK26M), + TOP_PARENT(CLK_TOP_MAINPLL_D5), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_UNIVPLL_D5), +}; + +static const struct mtk_parent png_sys_parents[] = { + TOP_PARENT(CLK_TOP_CLK26M), + TOP_PARENT(CLK_TOP_UNIVPLL_D8), + TOP_PARENT(CLK_TOP_MAINPLL_D7), + TOP_PARENT(CLK_TOP_MAINPLL_D6), + TOP_PARENT(CLK_TOP_MAINPLL_D5), + TOP_PARENT(CLK_TOP_UNIVPLL_D3), +}; + +static const struct mtk_parent sej_13m_parents[] = { + TOP_PARENT(CLK_TOP_CLK26M), + TOP_PARENT(CLK_TOP_CLK26M_D2), +}; + +static const struct mtk_parent imgrz_sys_parents[] = { + TOP_PARENT(CLK_TOP_CLK26M), + TOP_PARENT(CLK_TOP_MAINPLL_D6), + TOP_PARENT(CLK_TOP_MAINPLL_D7), + TOP_PARENT(CLK_TOP_MAINPLL_D5), + TOP_PARENT(CLK_TOP_UNIVPLL_D4), + TOP_PARENT(CLK_TOP_UNIVPLL_D10), + TOP_PARENT(CLK_TOP_UNIVPLL_D5), + TOP_PARENT(CLK_TOP_UNIVPLL_D6), +}; + +static const struct mtk_parent graph_eclk_parents[] = { + TOP_PARENT(CLK_TOP_CLK26M), + TOP_PARENT(CLK_TOP_MAINPLL_D6), + TOP_PARENT(CLK_TOP_UNIVPLL_D8), + TOP_PARENT(CLK_TOP_UNIVPLL_D16), + TOP_PARENT(CLK_TOP_MAINPLL_D7), + TOP_PARENT(CLK_TOP_UNIVPLL_D4), + TOP_PARENT(CLK_TOP_UNIVPLL_D10), + TOP_PARENT(CLK_TOP_UNIVPLL_D24), + TOP_PARENT(CLK_TOP_MAINPLL_D8), +}; + +static const struct mtk_parent fdbi_parents[] = { + TOP_PARENT(CLK_TOP_CLK26M), + TOP_PARENT(CLK_TOP_MAINPLL_D12), + TOP_PARENT(CLK_TOP_MAINPLL_D14), + TOP_PARENT(CLK_TOP_MAINPLL_D16), + TOP_PARENT(CLK_TOP_UNIVPLL_D10), + TOP_PARENT(CLK_TOP_UNIVPLL_D12), + TOP_PARENT(CLK_TOP_UNIVPLL_D16), + TOP_PARENT(CLK_TOP_UNIVPLL_D24), + TOP_PARENT(CLK_TOP_TVDPLL_D2), + TOP_PARENT(CLK_TOP_TVDPLL_D4), + TOP_PARENT(CLK_TOP_TVDPLL_D8), + TOP_PARENT(CLK_TOP_TVDPLL_D16), +}; + +static const struct mtk_parent faudio_parents[] = { + TOP_PARENT(CLK_TOP_CLK26M), + TOP_PARENT(CLK_TOP_UNIVPLL_D24), + TOP_PARENT(CLK_TOP_APLL1_D4), + TOP_PARENT(CLK_TOP_APLL2_D4), +}; + +static const struct mtk_parent fa2sys_parents[] = { + TOP_PARENT(CLK_TOP_CLK26M), + TOP_PARENT(CLK_TOP_APLL1_SRC_SEL), + TOP_PARENT(CLK_TOP_RG_APLL1_D2), + TOP_PARENT(CLK_TOP_RG_APLL1_D4), + TOP_PARENT(CLK_TOP_RG_APLL1_D8), + TOP_PARENT(CLK_TOP_RG_APLL1_D16), + TOP_PARENT(CLK_TOP_CLK26M_D2), + TOP_PARENT(CLK_TOP_RG_APLL1_D3), +}; + +static const struct mtk_parent fa1sys_parents[] = { + TOP_PARENT(CLK_TOP_CLK26M), + TOP_PARENT(CLK_TOP_APLL2_SRC_SEL), + TOP_PARENT(CLK_TOP_RG_APLL2_D2), + TOP_PARENT(CLK_TOP_RG_APLL2_D4), + TOP_PARENT(CLK_TOP_RG_APLL2_D8), + TOP_PARENT(CLK_TOP_RG_APLL2_D16), + TOP_PARENT(CLK_TOP_CLK26M_D2), + TOP_PARENT(CLK_TOP_RG_APLL2_D3), +}; + +static const struct mtk_parent fasm_m_parents[] = { + TOP_PARENT(CLK_TOP_CLK26M), + TOP_PARENT(CLK_TOP_UNIVPLL_D12), + TOP_PARENT(CLK_TOP_UNIVPLL_D6), + TOP_PARENT(CLK_TOP_MAINPLL_D7), +}; + +static const struct mtk_parent fecc_ck_parents[] = { + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK26M), + TOP_PARENT(CLK_TOP_UNIVPLL_D6), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_UNIVPLL_D4), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_UNIVPLL_D3), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_MAINPLL_D3), +}; + +static const struct mtk_parent pe2_mac_parents[] = { + TOP_PARENT(CLK_TOP_CLK26M), + TOP_PARENT(CLK_TOP_MAINPLL_D11), + TOP_PARENT(CLK_TOP_MAINPLL_D16), + TOP_PARENT(CLK_TOP_UNIVPLL_D12), + TOP_PARENT(CLK_TOP_UNIVPLL_D10), +}; + +static const struct mtk_parent cmsys_parents[] = { + TOP_PARENT(CLK_TOP_CLK26M), + TOP_PARENT(CLK_TOP_UNIVPLL_D5), + TOP_PARENT(CLK_TOP_UNIVPLL_D6), + TOP_PARENT(CLK_TOP_MAINPLL_D5), + TOP_PARENT(CLK_TOP_APLL2), + TOP_PARENT(CLK_TOP_APLL2_D2), + TOP_PARENT(CLK_TOP_APLL2_D4), + TOP_PARENT(CLK_TOP_APLL2_D3), +}; + +static const struct mtk_parent gcpu_parents[] = { + TOP_PARENT(CLK_TOP_CLK26M), + TOP_PARENT(CLK_TOP_MAINPLL_D4), + TOP_PARENT(CLK_TOP_MAINPLL_D5), + TOP_PARENT(CLK_TOP_MAINPLL_D6), + TOP_PARENT(CLK_TOP_MAINPLL_D7), + TOP_PARENT(CLK_TOP_UNIVPLL_D4), + TOP_PARENT(CLK_TOP_UNIVPLL_D10), + TOP_PARENT(CLK_TOP_UNIVPLL_D3), +}; + +static const struct mtk_parent spis_ck_parents[] = { + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK26M), + TOP_PARENT(CLK_TOP_UNIVPLL_D12), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_UNIVPLL_D8), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_UNIVPLL_D6), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_UNIVPLL_D5), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_UNIVPLL_D4), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_MAINPLL_D4), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_UNIVPLL_D3), +}; + +static const struct mtk_parent apll1_ref_parents[] = { + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), +}; + +static const struct mtk_parent int_32k_parents[] = { + TOP_PARENT(CLK_TOP_CLK32K), + TOP_PARENT(CLK_TOP_CLK26M_D793), +}; + +static const struct mtk_parent apll1_src_parents[] = { + TOP_PARENT(CLK_TOP_APLL1), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), +}; + +static const struct mtk_parent apll2_src_parents[] = { + TOP_PARENT(CLK_TOP_APLL2), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), +}; + +static const struct mtk_parent faud_intbus_parents[] = { + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK26M), + TOP_PARENT(CLK_TOP_MAINPLL_D11), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK26M), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_UNIVPLL_D10), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_RG_APLL2_D8), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK26M_D2), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_RG_APLL1_D8), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_UNIVPLL_D20), +}; + +static const struct mtk_parent axibus_parents[] = { + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK26M), + TOP_PARENT(CLK_TOP_MAINPLL_D11), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_MAINPLL_D12), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_UNIVPLL_D10), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK26M_D2), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_APLL2_D8), +}; + +static const struct mtk_parent hapll1_parents[] = { + TOP_PARENT(CLK_TOP_CLK26M), + TOP_PARENT(CLK_TOP_APLL1_SRC_SEL), + TOP_PARENT(CLK_TOP_RG_APLL1_D2), + TOP_PARENT(CLK_TOP_RG_APLL1_D4), + TOP_PARENT(CLK_TOP_RG_APLL1_D8), + TOP_PARENT(CLK_TOP_RG_APLL1_D16), + TOP_PARENT(CLK_TOP_CLK26M_D2), + TOP_PARENT(CLK_TOP_CLK26M_D8), + TOP_PARENT(CLK_TOP_RG_APLL1_D3), +}; + +static const struct mtk_parent hapll2_parents[] = { + TOP_PARENT(CLK_TOP_CLK26M), + TOP_PARENT(CLK_TOP_APLL2_SRC_SEL), + TOP_PARENT(CLK_TOP_RG_APLL2_D2), + TOP_PARENT(CLK_TOP_RG_APLL2_D4), + TOP_PARENT(CLK_TOP_RG_APLL2_D8), + TOP_PARENT(CLK_TOP_RG_APLL2_D16), + TOP_PARENT(CLK_TOP_CLK26M_D2), + TOP_PARENT(CLK_TOP_CLK26M_D4), + TOP_PARENT(CLK_TOP_RG_APLL2_D3), +}; + +static const struct mtk_parent spinfi_parents[] = { + TOP_PARENT(CLK_TOP_CLK26M), + TOP_PARENT(CLK_TOP_UNIVPLL_D24), + TOP_PARENT(CLK_TOP_UNIVPLL_D20), + TOP_PARENT(CLK_TOP_MAINPLL_D22), + TOP_PARENT(CLK_TOP_UNIVPLL_D16), + TOP_PARENT(CLK_TOP_MAINPLL_D16), + TOP_PARENT(CLK_TOP_UNIVPLL_D12), + TOP_PARENT(CLK_TOP_UNIVPLL_D10), + TOP_PARENT(CLK_TOP_MAINPLL_D11), +}; + +static const struct mtk_parent msdc0_parents[] = { + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK26M), + TOP_PARENT(CLK_TOP_UNIVPLL_D6), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_MAINPLL_D8), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_UNIVPLL_D8), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_MAINPLL_D16), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_MAINPLL_D12), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_APMIXED_MMPLL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_MMPLL_D2), +}; + +static const struct mtk_parent msdc0_clk50_parents[] = { + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK26M), + TOP_PARENT(CLK_TOP_UNIVPLL_D6), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_MAINPLL_D8), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_UNIVPLL_D8), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_MAINPLL_D6), +}; + +static const struct mtk_parent msdc2_parents[] = { + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK26M), + TOP_PARENT(CLK_TOP_UNIVPLL_D6), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_MAINPLL_D8), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_UNIVPLL_D8), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_MAINPLL_D16), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_MMPLL_D2), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_MAINPLL_D12), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_APMIXED_MMPLL), +}; + +static const struct mtk_parent disp_dpi_ck_parents[] = { + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK26M), + TOP_PARENT(CLK_TOP_TVDPLL_D2), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_TVDPLL_D4), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_TVDPLL_D8), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_TVDPLL_D16), }; static const struct mtk_composite top_muxes[] = { /* CLK_MUX_SEL0 */ - MUX(CLK_TOP_UART0_SEL, uart0_parents, 0x000, 0, 1), - MUX(CLK_TOP_EMI1X_SEL, emi1x_parents, 0x000, 1, 1), - MUX(CLK_TOP_EMI_DDRPHY_SEL, emi_ddrphy_parents, 0x000, 2, 1), - MUX(CLK_TOP_MSDC1_SEL, msdc1_parents, 0x000, 4, 8), - MUX(CLK_TOP_PWM_MM_SEL, pwm_mm_parents, 0x000, 18, 1), - MUX(CLK_TOP_UART1_SEL, uart0_parents, 0x000, 19, 1), - MUX(CLK_TOP_SPM_52M_SEL, uart0_parents, 0x000, 22, 1), - MUX(CLK_TOP_PMICSPI_SEL, pmicspi_parents, 0x000, 23, 3), + MUX_MIXED(CLK_TOP_UART0_SEL, uart0_parents, 0x000, 0, 1), + MUX_MIXED(CLK_TOP_EMI1X_SEL, emi1x_parents, 0x000, 1, 1), + MUX_MIXED(CLK_TOP_EMI_DDRPHY_SEL, emi_ddrphy_parents, 0x000, 2, 1), + MUX_MIXED(CLK_TOP_MSDC1_SEL, msdc1_parents, 0x000, 4, 8), + MUX_MIXED(CLK_TOP_PWM_MM_SEL, pwm_mm_parents, 0x000, 18, 1), + MUX_MIXED(CLK_TOP_UART1_SEL, uart0_parents, 0x000, 19, 1), + MUX_MIXED(CLK_TOP_SPM_52M_SEL, uart0_parents, 0x000, 22, 1), + MUX_MIXED(CLK_TOP_PMICSPI_SEL, pmicspi_parents, 0x000, 23, 3), /* CLK_MUX_SEL1 */ - MUX(CLK_TOP_NFI2X_SEL, nfi2x_parents, 0x004, 0, 3), - MUX(CLK_TOP_DDRPHYCFG_SEL, ddrphycfg_parents, 0x004, 15, 1), - MUX(CLK_TOP_SMI_SEL, smi_parents, 0x004, 16, 4), - MUX(CLK_TOP_USB_SEL, usb_parents, 0x004, 20, 3), + MUX_MIXED(CLK_TOP_NFI2X_SEL, nfi2x_parents, 0x004, 0, 3), + MUX_MIXED(CLK_TOP_DDRPHYCFG_SEL, ddrphycfg_parents, 0x004, 15, 1), + MUX_MIXED(CLK_TOP_SMI_SEL, smi_parents, 0x004, 16, 4), + MUX_MIXED(CLK_TOP_USB_SEL, usb_parents, 0x004, 20, 3), /* CLK_MUX_SEL8 */ - MUX(CLK_TOP_SPINOR_SEL, spinor_parents, 0x040, 0, 3), - MUX(CLK_TOP_ETH_SEL, eth_parents, 0x040, 6, 3), - MUX(CLK_TOP_AUD1_SEL, aud1_parents, 0x040, 22, 1), - MUX(CLK_TOP_AUD2_SEL, aud2_parents, 0x040, 23, 1), - MUX(CLK_TOP_I2C_SEL, i2c_parents, 0x040, 28, 3), + MUX_MIXED(CLK_TOP_SPINOR_SEL, spinor_parents, 0x040, 0, 3), + MUX_MIXED(CLK_TOP_ETH_SEL, eth_parents, 0x040, 6, 3), + MUX_MIXED(CLK_TOP_AUD1_SEL, aud1_parents, 0x040, 22, 1), + MUX_MIXED(CLK_TOP_AUD2_SEL, aud2_parents, 0x040, 23, 1), + MUX_MIXED(CLK_TOP_I2C_SEL, i2c_parents, 0x040, 28, 3), /* CLK_SEL_9 */ - MUX(CLK_TOP_AUD_I2S0_M_SEL, aud_i2s0_m_parents, 0x044, 12, 1), - MUX(CLK_TOP_AUD_I2S3_M_SEL, aud_i2s0_m_parents, 0x044, 15, 1), - MUX(CLK_TOP_AUD_I2S4_M_SEL, aud_i2s0_m_parents, 0x044, 16, 1), - MUX(CLK_TOP_AUD_I2S6_M_SEL, aud_i2s0_m_parents, 0x044, 18, 1), + MUX_MIXED(CLK_TOP_AUD_I2S0_M_SEL, aud_i2s0_m_parents, 0x044, 12, 1), + MUX_MIXED(CLK_TOP_AUD_I2S3_M_SEL, aud_i2s0_m_parents, 0x044, 15, 1), + MUX_MIXED(CLK_TOP_AUD_I2S4_M_SEL, aud_i2s0_m_parents, 0x044, 16, 1), + MUX_MIXED(CLK_TOP_AUD_I2S6_M_SEL, aud_i2s0_m_parents, 0x044, 18, 1), /* CLK_MUX_SEL13 */ - MUX(CLK_TOP_PWM_SEL, pwm_mm_parents, 0x07c, 0, 1), - MUX(CLK_TOP_AUD_SPDIFIN_SEL, aud_spdifin_parents, 0x07c, 2, 2), - MUX(CLK_TOP_UART2_SEL, uart0_parents, 0x07c, 4, 1), - MUX(CLK_TOP_DBG_ATCLK_SEL, dbg_atclk_parents, 0x07c, 7, 3), - MUX(CLK_TOP_PNG_SYS_SEL, png_sys_parents, 0x07c, 16, 3), - MUX(CLK_TOP_SEJ_13M_SEL, sej_13m_parents, 0x07c, 22, 1), + MUX_MIXED(CLK_TOP_PWM_SEL, pwm_mm_parents, 0x07c, 0, 1), + MUX_MIXED(CLK_TOP_AUD_SPDIFIN_SEL, aud_spdifin_parents, 0x07c, 2, 2), + MUX_MIXED(CLK_TOP_UART2_SEL, uart0_parents, 0x07c, 4, 1), + MUX_MIXED(CLK_TOP_DBG_ATCLK_SEL, dbg_atclk_parents, 0x07c, 7, 3), + MUX_MIXED(CLK_TOP_PNG_SYS_SEL, png_sys_parents, 0x07c, 16, 3), + MUX_MIXED(CLK_TOP_SEJ_13M_SEL, sej_13m_parents, 0x07c, 22, 1), /* CLK_MUX_SEL14 */ - MUX(CLK_TOP_IMGRZ_SYS_SEL, imgrz_sys_parents, 0xc0, 0, 3), - MUX(CLK_TOP_GRAPH_ECLK_SEL, graph_eclk_parents, 0xc0, 8, 4), - MUX(CLK_TOP_FDBI_SEL, fdbi_parents, 0xc0, 12, 4), - MUX(CLK_TOP_FAUDIO_SEL, faudio_parents, 0xc0, 16, 2), - MUX(CLK_TOP_FA2SYS_SEL, fa2sys_parents, 0xc0, 24, 3), - MUX(CLK_TOP_FA1SYS_SEL, fa1sys_parents, 0xc0, 27, 3), - MUX(CLK_TOP_FASM_M_SEL, fasm_m_parents, 0xc0, 30, 2), + MUX_MIXED(CLK_TOP_IMGRZ_SYS_SEL, imgrz_sys_parents, 0xc0, 0, 3), + MUX_MIXED(CLK_TOP_GRAPH_ECLK_SEL, graph_eclk_parents, 0xc0, 8, 4), + MUX_MIXED(CLK_TOP_FDBI_SEL, fdbi_parents, 0xc0, 12, 4), + MUX_MIXED(CLK_TOP_FAUDIO_SEL, faudio_parents, 0xc0, 16, 2), + MUX_MIXED(CLK_TOP_FA2SYS_SEL, fa2sys_parents, 0xc0, 24, 3), + MUX_MIXED(CLK_TOP_FA1SYS_SEL, fa1sys_parents, 0xc0, 27, 3), + MUX_MIXED(CLK_TOP_FASM_M_SEL, fasm_m_parents, 0xc0, 30, 2), /* CLK_MUX_SEL15 */ - MUX(CLK_TOP_FASM_H_SEL, fasm_m_parents, 0xC4, 0, 2), - MUX(CLK_TOP_FASM_L_SEL, fasm_m_parents, 0xC4, 2, 2), - MUX(CLK_TOP_FECC_CK_SEL, fecc_ck_parents, 0xC4, 18, 6), - MUX(CLK_TOP_PE2_MAC_SEL, pe2_mac_parents, 0xC4, 24, 3), - MUX(CLK_TOP_CMSYS_SEL, cmsys_parents, 0xC4, 28, 3), + MUX_MIXED(CLK_TOP_FASM_H_SEL, fasm_m_parents, 0xC4, 0, 2), + MUX_MIXED(CLK_TOP_FASM_L_SEL, fasm_m_parents, 0xC4, 2, 2), + MUX_MIXED(CLK_TOP_FECC_CK_SEL, fecc_ck_parents, 0xC4, 18, 6), + MUX_MIXED(CLK_TOP_PE2_MAC_SEL, pe2_mac_parents, 0xC4, 24, 3), + MUX_MIXED(CLK_TOP_CMSYS_SEL, cmsys_parents, 0xC4, 28, 3), /* CLK_MUX_SEL16 */ - MUX(CLK_TOP_GCPU_SEL, gcpu_parents, 0xC8, 0, 3), - MUX(CLK_TOP_SPIS_CK_SEL, spis_ck_parents, 0xC8, 4, 8), + MUX_MIXED(CLK_TOP_GCPU_SEL, gcpu_parents, 0xC8, 0, 3), + MUX_MIXED(CLK_TOP_SPIS_CK_SEL, spis_ck_parents, 0xC8, 4, 8), /* CLK_MUX_SEL17 */ - MUX(CLK_TOP_APLL1_REF_SEL, apll1_ref_parents, 0xCC, 6, 3), - MUX(CLK_TOP_APLL2_REF_SEL, apll1_ref_parents, 0xCC, 9, 3), - MUX(CLK_TOP_INT_32K_SEL, int_32k_parents, 0xCC, 12, 1), - MUX(CLK_TOP_APLL1_SRC_SEL, apll1_src_parents, 0xCC, 13, 2), - MUX(CLK_TOP_APLL2_SRC_SEL, apll2_src_parents, 0xCC, 15, 2), + MUX_MIXED(CLK_TOP_APLL1_REF_SEL, apll1_ref_parents, 0xCC, 6, 3), + MUX_MIXED(CLK_TOP_APLL2_REF_SEL, apll1_ref_parents, 0xCC, 9, 3), + MUX_MIXED(CLK_TOP_INT_32K_SEL, int_32k_parents, 0xCC, 12, 1), + MUX_MIXED(CLK_TOP_APLL1_SRC_SEL, apll1_src_parents, 0xCC, 13, 2), + MUX_MIXED(CLK_TOP_APLL2_SRC_SEL, apll2_src_parents, 0xCC, 15, 2), /* CLK_MUX_SEL19 */ - MUX(CLK_TOP_FAUD_INTBUS_SEL, faud_intbus_parents, 0xD4, 8, 8), - MUX(CLK_TOP_AXIBUS_SEL, axibus_parents, 0xD4, 24, 8), + MUX_MIXED(CLK_TOP_FAUD_INTBUS_SEL, faud_intbus_parents, 0xD4, 8, 8), + MUX_MIXED(CLK_TOP_AXIBUS_SEL, axibus_parents, 0xD4, 24, 8), /* CLK_MUX_SEL21 */ - MUX(CLK_TOP_HAPLL1_SEL, hapll1_parents, 0xDC, 0, 4), - MUX(CLK_TOP_HAPLL2_SEL, hapll2_parents, 0xDC, 4, 4), - MUX(CLK_TOP_SPINFI_SEL, spinfi_parents, 0xDC, 8, 4), + MUX_MIXED(CLK_TOP_HAPLL1_SEL, hapll1_parents, 0xDC, 0, 4), + MUX_MIXED(CLK_TOP_HAPLL2_SEL, hapll2_parents, 0xDC, 4, 4), + MUX_MIXED(CLK_TOP_SPINFI_SEL, spinfi_parents, 0xDC, 8, 4), /* CLK_MUX_SEL22 */ - MUX(CLK_TOP_MSDC0_SEL, msdc0_parents, 0xF4, 0, 8), - MUX(CLK_TOP_MSDC0_CLK50_SEL, msdc0_clk50_parents, 0xF4, 8, 6), - MUX(CLK_TOP_MSDC2_SEL, msdc2_parents, 0xF4, 15, 8), - MUX(CLK_TOP_MSDC2_CLK50_SEL, msdc0_clk50_parents, 0xF4, 23, 6), + MUX_MIXED(CLK_TOP_MSDC0_SEL, msdc0_parents, 0xF4, 0, 8), + MUX_MIXED(CLK_TOP_MSDC0_CLK50_SEL, msdc0_clk50_parents, 0xF4, 8, 6), + MUX_MIXED(CLK_TOP_MSDC2_SEL, msdc2_parents, 0xF4, 15, 8), + MUX_MIXED(CLK_TOP_MSDC2_CLK50_SEL, msdc0_clk50_parents, 0xF4, 23, 6), /* CLK_MUX_SEL23 */ - MUX(CLK_TOP_DISP_DPI_CK_SEL, disp_dpi_ck_parents, 0xF8, 0, 6), - MUX(CLK_TOP_SPI1_SEL, spis_ck_parents, 0xF8, 6, 8), - MUX(CLK_TOP_SPI2_SEL, spis_ck_parents, 0xF8, 14, 8), - MUX(CLK_TOP_SPI3_SEL, spis_ck_parents, 0xF8, 22, 8), + MUX_MIXED(CLK_TOP_DISP_DPI_CK_SEL, disp_dpi_ck_parents, 0xF8, 0, 6), + MUX_MIXED(CLK_TOP_SPI1_SEL, spis_ck_parents, 0xF8, 6, 8), + MUX_MIXED(CLK_TOP_SPI2_SEL, spis_ck_parents, 0xF8, 14, 8), + MUX_MIXED(CLK_TOP_SPI3_SEL, spis_ck_parents, 0xF8, 22, 8), }; static const struct mtk_gate_regs top0_cg_regs = { -- cgit v1.3.1 From a56b24bf58dd8f5d5bcdf210933d7775b83adec3 Mon Sep 17 00:00:00 2001 From: David Lechner Date: Tue, 17 Mar 2026 18:23:27 -0500 Subject: clk: mediatek: remove use of CLK_BYPASS_XTAL flag Remove the CLK_BYPASS_XTAL flag completely. It was a bit of a hack that was meant to handle mux clocks that had mixed parents (e.g. XTAL and TOPCKGEN). The idea was that if you didn't have CLK_XTAL as a parent, then you were supposed to add the CLK_BYPASS_XTAL flag to the clock tree. There are likely a number of drivers missing this since it is not intuitive. In the meantime, we have introduced the CLK_PARENT_MIXED flag which handles this more robustly. All of the affected drivers (the ones without CLK_BYPASS_XTAL) have been updated to use CLK_PARENT_MIXED, so the CLK_BYPASS_XTAL flag is no longer needed on other drivers. Reviewed-by: Julien Stephan Link: https://patch.msgid.link/20260317-clk-mtk-unify-mux-parents-v3-14-a4760f5b0a80@baylibre.com Signed-off-by: David Lechner --- drivers/clk/mediatek/clk-mt7981.c | 2 +- drivers/clk/mediatek/clk-mt7986.c | 2 +- drivers/clk/mediatek/clk-mt7987.c | 3 +-- drivers/clk/mediatek/clk-mt7988.c | 3 +-- drivers/clk/mediatek/clk-mtk.c | 8 -------- drivers/clk/mediatek/clk-mtk.h | 7 ------- 6 files changed, 4 insertions(+), 21 deletions(-) diff --git a/drivers/clk/mediatek/clk-mt7981.c b/drivers/clk/mediatek/clk-mt7981.c index 0c770a0bd93..cdd9b9e4092 100644 --- a/drivers/clk/mediatek/clk-mt7981.c +++ b/drivers/clk/mediatek/clk-mt7981.c @@ -623,7 +623,7 @@ static const struct mtk_clk_tree mt7981_topckgen_clk_tree = { .num_fclks = ARRAY_SIZE(top_fixed_clks), .num_fdivs = ARRAY_SIZE(top_fixed_divs), .num_muxes = ARRAY_SIZE(top_muxes), - .flags = CLK_BYPASS_XTAL | CLK_PARENT_TOPCKGEN, + .flags = CLK_PARENT_TOPCKGEN, }; static const struct mtk_clk_tree mt7981_infracfg_clk_tree = { diff --git a/drivers/clk/mediatek/clk-mt7986.c b/drivers/clk/mediatek/clk-mt7986.c index c2c216fcdf4..65d4142fa63 100644 --- a/drivers/clk/mediatek/clk-mt7986.c +++ b/drivers/clk/mediatek/clk-mt7986.c @@ -530,7 +530,7 @@ static const struct mtk_clk_tree mt7986_topckgen_clk_tree = { .num_fclks = ARRAY_SIZE(top_fixed_clks), .num_fdivs = ARRAY_SIZE(top_fixed_divs), .num_muxes = ARRAY_SIZE(top_muxes), - .flags = CLK_BYPASS_XTAL | CLK_PARENT_TOPCKGEN, + .flags = CLK_PARENT_TOPCKGEN, }; static const struct mtk_clk_tree mt7986_infracfg_clk_tree = { diff --git a/drivers/clk/mediatek/clk-mt7987.c b/drivers/clk/mediatek/clk-mt7987.c index 2f3e314b648..5ae76a2c47a 100644 --- a/drivers/clk/mediatek/clk-mt7987.c +++ b/drivers/clk/mediatek/clk-mt7987.c @@ -446,7 +446,7 @@ static const struct mtk_clk_tree mt7987_topckgen_clk_tree = { .muxes = topckgen_mtk_muxes, .num_fdivs = ARRAY_SIZE(topckgen_mtk_fixed_factors), .num_muxes = ARRAY_SIZE(topckgen_mtk_muxes), - .flags = CLK_BYPASS_XTAL | CLK_PARENT_TOPCKGEN, + .flags = CLK_PARENT_TOPCKGEN, .xtal_rate = MT7987_XTAL_RATE, }; @@ -772,7 +772,6 @@ static const struct mtk_clk_tree mt7987_infracfg_clk_tree = { .gates = infracfg_mtk_gates, .num_muxes = ARRAY_SIZE(infracfg_mtk_mux), .num_gates = ARRAY_SIZE(infracfg_mtk_gates), - .flags = CLK_BYPASS_XTAL, .xtal_rate = MT7987_XTAL_RATE, }; diff --git a/drivers/clk/mediatek/clk-mt7988.c b/drivers/clk/mediatek/clk-mt7988.c index 21d194ed807..38a5c20035d 100644 --- a/drivers/clk/mediatek/clk-mt7988.c +++ b/drivers/clk/mediatek/clk-mt7988.c @@ -812,7 +812,7 @@ static const struct mtk_clk_tree mt7988_topckgen_clk_tree = { .num_fclks = ARRAY_SIZE(topckgen_mtk_fixed_clks), .num_fdivs = ARRAY_SIZE(topckgen_mtk_fixed_factors), .num_muxes = ARRAY_SIZE(topckgen_mtk_muxes), - .flags = CLK_BYPASS_XTAL | CLK_PARENT_TOPCKGEN, + .flags = CLK_PARENT_TOPCKGEN, .xtal_rate = 40 * MHZ, }; @@ -823,7 +823,6 @@ static const struct mtk_clk_tree mt7988_infracfg_clk_tree = { .gates = infracfg_mtk_gates, .num_muxes = ARRAY_SIZE(infracfg_mtk_mux), .num_gates = ARRAY_SIZE(infracfg_mtk_gates), - .flags = CLK_BYPASS_XTAL, .xtal_rate = 40 * MHZ, }; diff --git a/drivers/clk/mediatek/clk-mtk.c b/drivers/clk/mediatek/clk-mtk.c index e86e677d8ac..30439ae7d93 100644 --- a/drivers/clk/mediatek/clk-mtk.c +++ b/drivers/clk/mediatek/clk-mtk.c @@ -735,10 +735,6 @@ static ulong mtk_topckgen_get_mux_rate(struct clk *clk, u32 off) return mtk_find_parent_rate(priv, clk, parent->id, parent->flags); } - if (mux->parent[index] == CLK_XTAL && - !(priv->tree->flags & CLK_BYPASS_XTAL)) - return priv->tree->xtal_rate; - return mtk_find_parent_rate(priv, clk, mux->parent[index], mux->flags); } @@ -1005,10 +1001,6 @@ static ulong mtk_infrasys_get_mux_rate(struct clk *clk, u32 off) return mtk_find_parent_rate(priv, clk, parent->id, parent->flags); } - if (mux->parent[index] == CLK_XTAL && - !(priv->tree->flags & CLK_BYPASS_XTAL)) - return priv->tree->xtal_rate; - return mtk_find_parent_rate(priv, clk, mux->parent[index], mux->flags); } diff --git a/drivers/clk/mediatek/clk-mtk.h b/drivers/clk/mediatek/clk-mtk.h index f81e214bf00..2d67cf15f47 100644 --- a/drivers/clk/mediatek/clk-mtk.h +++ b/drivers/clk/mediatek/clk-mtk.h @@ -13,13 +13,6 @@ /* flags in struct mtk_clk_tree */ -/* clk id == 0 doesn't mean it's xtal clk - * This doesn't apply when CLK_PARENT_MIXED is defined. - * With CLK_PARENT_MIXED declare CLK_PARENT_XTAL for the - * relevant parent. - */ -#define CLK_BYPASS_XTAL BIT(0) - #define CLK_PLL_HAVE_RST_BAR BIT(0) #define CLK_MUX_DOMAIN_SCPSYS BIT(0) -- cgit v1.3.1 From 84c89c25291eb6a6afa131c27a324fc456861e59 Mon Sep 17 00:00:00 2001 From: David Lechner Date: Tue, 17 Mar 2026 18:23:28 -0500 Subject: clk: mediatek: remove CLK_PARENT_MIXED flag Remove CLK_PARENT_MIXED and all dead code paths related to it. All mux clocks have been converted to use struct mtk_parent (the parent_flags field of the parent/parent_flags union). Use of this struct was indicated by CLK_PARENT_MIXED. Now, this is always the case and we can drop the flag and the union. All MUX_MIXED* macros are change to use the equivalent MUX* macros since we no longer need to set the flag. Reviewed-by: Julien Stephan Link: https://patch.msgid.link/20260317-clk-mtk-unify-mux-parents-v3-15-a4760f5b0a80@baylibre.com Signed-off-by: David Lechner --- drivers/clk/mediatek/clk-mt7622.c | 79 +++++++------ drivers/clk/mediatek/clk-mt7623.c | 147 ++++++++++++------------ drivers/clk/mediatek/clk-mt7629.c | 71 ++++++------ drivers/clk/mediatek/clk-mt7981.c | 9 +- drivers/clk/mediatek/clk-mt7986.c | 10 +- drivers/clk/mediatek/clk-mt7987.c | 8 +- drivers/clk/mediatek/clk-mt7988.c | 9 +- drivers/clk/mediatek/clk-mt8183.c | 84 +++++++------- drivers/clk/mediatek/clk-mt8188.c | 182 +++++++++++++++--------------- drivers/clk/mediatek/clk-mt8189.c | 12 +- drivers/clk/mediatek/clk-mt8195.c | 232 +++++++++++++++++++------------------- drivers/clk/mediatek/clk-mt8365.c | 86 +++++++------- drivers/clk/mediatek/clk-mt8512.c | 90 +++++++-------- drivers/clk/mediatek/clk-mt8516.c | 86 +++++++------- drivers/clk/mediatek/clk-mt8518.c | 118 +++++++++---------- drivers/clk/mediatek/clk-mtk.c | 66 +++-------- drivers/clk/mediatek/clk-mtk.h | 62 +--------- 17 files changed, 632 insertions(+), 719 deletions(-) diff --git a/drivers/clk/mediatek/clk-mt7622.c b/drivers/clk/mediatek/clk-mt7622.c index 8a7d446ad79..9e6fd12a6a5 100644 --- a/drivers/clk/mediatek/clk-mt7622.c +++ b/drivers/clk/mediatek/clk-mt7622.c @@ -330,60 +330,59 @@ static const struct mtk_parent apll1_ck_parents[] = { static const struct mtk_composite top_muxes[] = { /* CLK_CFG_0 */ - MUX_GATE_MIXED(CLK_TOP_AXI_SEL, axi_parents, 0x40, 0, 3, 7), - MUX_GATE_MIXED(CLK_TOP_MEM_SEL, mem_parents, 0x40, 8, 1, 15), - MUX_GATE_MIXED(CLK_TOP_DDRPHYCFG_SEL, ddrphycfg_parents, 0x40, 16, 1, 23), - MUX_GATE_MIXED(CLK_TOP_ETH_SEL, eth_parents, 0x40, 24, 3, 31), + MUX_GATE(CLK_TOP_AXI_SEL, axi_parents, 0x40, 0, 3, 7), + MUX_GATE(CLK_TOP_MEM_SEL, mem_parents, 0x40, 8, 1, 15), + MUX_GATE(CLK_TOP_DDRPHYCFG_SEL, ddrphycfg_parents, 0x40, 16, 1, 23), + MUX_GATE(CLK_TOP_ETH_SEL, eth_parents, 0x40, 24, 3, 31), /* CLK_CFG_1 */ - MUX_GATE_MIXED(CLK_TOP_PWM_SEL, pwm_parents, 0x50, 0, 2, 7), - MUX_GATE_MIXED(CLK_TOP_F10M_REF_SEL, f10m_ref_parents, 0x50, 8, 1, 15), - MUX_GATE_MIXED(CLK_TOP_NFI_INFRA_SEL, nfi_infra_parents, 0x50, 16, 4, 23), - MUX_GATE_MIXED(CLK_TOP_FLASH_SEL, flash_parents, 0x50, 24, 3, 31), + MUX_GATE(CLK_TOP_PWM_SEL, pwm_parents, 0x50, 0, 2, 7), + MUX_GATE(CLK_TOP_F10M_REF_SEL, f10m_ref_parents, 0x50, 8, 1, 15), + MUX_GATE(CLK_TOP_NFI_INFRA_SEL, nfi_infra_parents, 0x50, 16, 4, 23), + MUX_GATE(CLK_TOP_FLASH_SEL, flash_parents, 0x50, 24, 3, 31), /* CLK_CFG_2 */ - MUX_GATE_MIXED(CLK_TOP_UART_SEL, uart_parents, 0x60, 0, 1, 7), - MUX_GATE_MIXED(CLK_TOP_SPI0_SEL, spi0_parents, 0x60, 8, 3, 15), - MUX_GATE_MIXED(CLK_TOP_SPI1_SEL, spi1_parents, 0x60, 16, 3, 23), - MUX_GATE_MIXED(CLK_TOP_MSDC50_0_SEL, uart_parents, 0x60, 24, 3, 31), + MUX_GATE(CLK_TOP_UART_SEL, uart_parents, 0x60, 0, 1, 7), + MUX_GATE(CLK_TOP_SPI0_SEL, spi0_parents, 0x60, 8, 3, 15), + MUX_GATE(CLK_TOP_SPI1_SEL, spi1_parents, 0x60, 16, 3, 23), + MUX_GATE(CLK_TOP_MSDC50_0_SEL, uart_parents, 0x60, 24, 3, 31), /* CLK_CFG_3 */ - MUX_GATE_MIXED(CLK_TOP_MSDC30_0_SEL, msdc30_0_parents, 0x70, 0, 3, 7), - MUX_GATE_MIXED(CLK_TOP_MSDC30_1_SEL, msdc30_0_parents, 0x70, 8, 3, 15), - MUX_GATE_MIXED(CLK_TOP_A1SYS_HP_SEL, a1sys_hp_parents, 0x70, 16, 3, 23), - MUX_GATE_MIXED(CLK_TOP_A2SYS_HP_SEL, a1sys_hp_parents, 0x70, 24, 3, 31), + MUX_GATE(CLK_TOP_MSDC30_0_SEL, msdc30_0_parents, 0x70, 0, 3, 7), + MUX_GATE(CLK_TOP_MSDC30_1_SEL, msdc30_0_parents, 0x70, 8, 3, 15), + MUX_GATE(CLK_TOP_A1SYS_HP_SEL, a1sys_hp_parents, 0x70, 16, 3, 23), + MUX_GATE(CLK_TOP_A2SYS_HP_SEL, a1sys_hp_parents, 0x70, 24, 3, 31), /* CLK_CFG_4 */ - MUX_GATE_MIXED(CLK_TOP_INTDIR_SEL, intdir_parents, 0x80, 0, 2, 7), - MUX_GATE_MIXED(CLK_TOP_AUD_INTBUS_SEL, aud_intbus_parents, 0x80, 8, 2, 15), - MUX_GATE_MIXED(CLK_TOP_PMICSPI_SEL, pmicspi_parents, 0x80, 16, 3, 23), - MUX_GATE_MIXED(CLK_TOP_SCP_SEL, ddrphycfg_parents, 0x80, 24, 2, 31), + MUX_GATE(CLK_TOP_INTDIR_SEL, intdir_parents, 0x80, 0, 2, 7), + MUX_GATE(CLK_TOP_AUD_INTBUS_SEL, aud_intbus_parents, 0x80, 8, 2, 15), + MUX_GATE(CLK_TOP_PMICSPI_SEL, pmicspi_parents, 0x80, 16, 3, 23), + MUX_GATE(CLK_TOP_SCP_SEL, ddrphycfg_parents, 0x80, 24, 2, 31), /* CLK_CFG_5 */ - MUX_GATE_MIXED(CLK_TOP_ATB_SEL, atb_parents, 0x90, 0, 2, 7), - MUX_GATE_MIXED_FLAGS(CLK_TOP_HIF_SEL, eth_parents, 0x90, 8, 3, 15, - CLK_MUX_DOMAIN_SCPSYS), - MUX_GATE_MIXED(CLK_TOP_AUDIO_SEL, audio_parents, 0x90, 16, 2, 23), - MUX_GATE_MIXED(CLK_TOP_U2_SEL, usb20_parents, 0x90, 24, 2, 31), + MUX_GATE(CLK_TOP_ATB_SEL, atb_parents, 0x90, 0, 2, 7), + MUX_GATE_FLAGS(CLK_TOP_HIF_SEL, eth_parents, 0x90, 8, 3, 15, CLK_MUX_DOMAIN_SCPSYS), + MUX_GATE(CLK_TOP_AUDIO_SEL, audio_parents, 0x90, 16, 2, 23), + MUX_GATE(CLK_TOP_U2_SEL, usb20_parents, 0x90, 24, 2, 31), /* CLK_CFG_6 */ - MUX_GATE_MIXED(CLK_TOP_AUD1_SEL, aud1_parents, 0xA0, 0, 1, 7), - MUX_GATE_MIXED(CLK_TOP_AUD2_SEL, aud1_parents, 0xA0, 8, 1, 15), - MUX_GATE_MIXED(CLK_TOP_IRRX_SEL, f10m_ref_parents, 0xA0, 16, 1, 23), - MUX_GATE_MIXED(CLK_TOP_IRTX_SEL, f10m_ref_parents, 0xA0, 24, 1, 31), + MUX_GATE(CLK_TOP_AUD1_SEL, aud1_parents, 0xA0, 0, 1, 7), + MUX_GATE(CLK_TOP_AUD2_SEL, aud1_parents, 0xA0, 8, 1, 15), + MUX_GATE(CLK_TOP_IRRX_SEL, f10m_ref_parents, 0xA0, 16, 1, 23), + MUX_GATE(CLK_TOP_IRTX_SEL, f10m_ref_parents, 0xA0, 24, 1, 31), /* CLK_CFG_7 */ - MUX_GATE_MIXED(CLK_TOP_ASM_L_SEL, asm_l_parents, 0xB0, 0, 2, 7), - MUX_GATE_MIXED(CLK_TOP_ASM_M_SEL, asm_l_parents, 0xB0, 8, 2, 15), - MUX_GATE_MIXED(CLK_TOP_ASM_H_SEL, asm_l_parents, 0xB0, 16, 2, 23), + MUX_GATE(CLK_TOP_ASM_L_SEL, asm_l_parents, 0xB0, 0, 2, 7), + MUX_GATE(CLK_TOP_ASM_M_SEL, asm_l_parents, 0xB0, 8, 2, 15), + MUX_GATE(CLK_TOP_ASM_H_SEL, asm_l_parents, 0xB0, 16, 2, 23), /* CLK_AUDDIV_0 */ - MUX_MIXED(CLK_TOP_APLL1_SEL, apll1_ck_parents, 0x120, 6, 1), - MUX_MIXED(CLK_TOP_APLL2_SEL, apll1_ck_parents, 0x120, 7, 1), - MUX_MIXED(CLK_TOP_I2S0_MCK_SEL, apll1_ck_parents, 0x120, 8, 1), - MUX_MIXED(CLK_TOP_I2S1_MCK_SEL, apll1_ck_parents, 0x120, 9, 1), - MUX_MIXED(CLK_TOP_I2S2_MCK_SEL, apll1_ck_parents, 0x120, 10, 1), - MUX_MIXED(CLK_TOP_I2S3_MCK_SEL, apll1_ck_parents, 0x120, 161, 1), + MUX(CLK_TOP_APLL1_SEL, apll1_ck_parents, 0x120, 6, 1), + MUX(CLK_TOP_APLL2_SEL, apll1_ck_parents, 0x120, 7, 1), + MUX(CLK_TOP_I2S0_MCK_SEL, apll1_ck_parents, 0x120, 8, 1), + MUX(CLK_TOP_I2S1_MCK_SEL, apll1_ck_parents, 0x120, 9, 1), + MUX(CLK_TOP_I2S2_MCK_SEL, apll1_ck_parents, 0x120, 10, 1), + MUX(CLK_TOP_I2S3_MCK_SEL, apll1_ck_parents, 0x120, 161, 1), }; /* infracfg */ @@ -396,7 +395,7 @@ static const struct mtk_parent infra_mux1_parents[] = { }; static const struct mtk_composite infra_muxes[] = { - MUX_MIXED(CLK_INFRA_MUX1_SEL, infra_mux1_parents, 0x000, 2, 2), + MUX(CLK_INFRA_MUX1_SEL, infra_mux1_parents, 0x000, 2, 2), }; static const struct mtk_gate_regs infra_cg_regs = { @@ -429,7 +428,7 @@ static const struct mtk_parent peribus_ck_parents[] = { }; static const struct mtk_composite peri_muxes[] = { - MUX_MIXED(CLK_PERIBUS_SEL, peribus_ck_parents, 0x05c, 0, 1), + MUX(CLK_PERIBUS_SEL, peribus_ck_parents, 0x05c, 0, 1), }; static const struct mtk_gate_regs peri0_cg_regs = { diff --git a/drivers/clk/mediatek/clk-mt7623.c b/drivers/clk/mediatek/clk-mt7623.c index 9bb2a1af734..9e1522d4615 100644 --- a/drivers/clk/mediatek/clk-mt7623.c +++ b/drivers/clk/mediatek/clk-mt7623.c @@ -697,77 +697,74 @@ static const struct mtk_parent aud_src_parents[] = { }; static const struct mtk_composite top_muxes[] = { - MUX_GATE_MIXED(CLK_TOP_AXI_SEL, axi_parents, 0x40, 0, 3, 7), - MUX_GATE_MIXED(CLK_TOP_MEM_SEL, mem_parents, 0x40, 8, 1, 15), - MUX_GATE_MIXED(CLK_TOP_DDRPHYCFG_SEL, ddrphycfg_parents, 0x40, 16, 1, 23), - MUX_GATE_MIXED_FLAGS(CLK_TOP_MM_SEL, mm_parents, 0x40, 24, 3, 31, - CLK_MUX_DOMAIN_SCPSYS), - - MUX_GATE_MIXED(CLK_TOP_PWM_SEL, pwm_parents, 0x50, 0, 2, 7), - MUX_GATE_MIXED(CLK_TOP_VDEC_SEL, vdec_parents, 0x50, 8, 4, 15), - MUX_GATE_MIXED_FLAGS(CLK_TOP_MFG_SEL, mfg_parents, 0x50, 16, 3, 23, - CLK_MUX_DOMAIN_SCPSYS), - MUX_GATE_MIXED(CLK_TOP_CAMTG_SEL, camtg_parents, 0x50, 24, 3, 31), - - MUX_GATE_MIXED(CLK_TOP_UART_SEL, uart_parents, 0x60, 0, 1, 7), - MUX_GATE_MIXED(CLK_TOP_SPI0_SEL, spi_parents, 0x60, 8, 3, 15), - MUX_GATE_MIXED(CLK_TOP_USB20_SEL, usb20_parents, 0x60, 16, 2, 23), - MUX_GATE_MIXED(CLK_TOP_MSDC30_0_SEL, msdc30_parents, 0x60, 24, 3, 31), - - MUX_GATE_MIXED(CLK_TOP_MSDC30_1_SEL, msdc30_parents, 0x70, 0, 3, 7), - MUX_GATE_MIXED(CLK_TOP_MSDC30_2_SEL, msdc30_parents, 0x70, 8, 3, 15), - MUX_GATE_MIXED(CLK_TOP_AUDIO_SEL, msdc30_parents, 0x70, 16, 1, 23), - MUX_GATE_MIXED(CLK_TOP_AUDINTBUS_SEL, aud_intbus_parents, 0x70, 24, 3, 31), - - MUX_GATE_MIXED(CLK_TOP_PMICSPI_SEL, pmicspi_parents, 0x80, 0, 4, 7), - MUX_GATE_MIXED(CLK_TOP_SCP_SEL, scp_parents, 0x80, 8, 2, 15), - MUX_GATE_MIXED(CLK_TOP_DPI0_SEL, dpi0_tve_parents, 0x80, 16, 3, 23), - MUX_GATE_MIXED(CLK_TOP_DPI1_SEL, dpi1_parents, 0x80, 24, 2, 31), - - MUX_GATE_MIXED(CLK_TOP_TVE_SEL, dpi0_tve_parents, 0x90, 0, 3, 7), - MUX_GATE_MIXED(CLK_TOP_HDMI_SEL, hdmi_parents, 0x90, 8, 2, 15), - MUX_GATE_MIXED(CLK_TOP_APLL_SEL, apll_parents, 0x90, 16, 3, 23), - - MUX_GATE_MIXED(CLK_TOP_RTC_SEL, rtc_parents, 0xA0, 0, 2, 7), - MUX_GATE_MIXED(CLK_TOP_NFI2X_SEL, nfi2x_parents, 0xA0, 8, 3, 15), - MUX_GATE_MIXED(CLK_TOP_EMMC_HCLK_SEL, emmc_hclk_parents, 0xA0, 24, 2, 31), - - MUX_GATE_MIXED(CLK_TOP_FLASH_SEL, flash_parents, 0xB0, 0, 3, 7), - MUX_GATE_MIXED(CLK_TOP_DI_SEL, di_parents, 0xB0, 8, 2, 15), - MUX_GATE_MIXED(CLK_TOP_NR_SEL, nr_osd_parents, 0xB0, 16, 3, 23), - MUX_GATE_MIXED(CLK_TOP_OSD_SEL, nr_osd_parents, 0xB0, 24, 3, 31), - - MUX_GATE_MIXED(CLK_TOP_HDMIRX_BIST_SEL, hdmirx_bist_parents, 0xC0, 0, 3, 7), - MUX_GATE_MIXED(CLK_TOP_INTDIR_SEL, intdir_parents, 0xC0, 8, 2, 15), - MUX_GATE_MIXED(CLK_TOP_ASM_I_SEL, asm_parents, 0xC0, 16, 2, 23), - MUX_GATE_MIXED(CLK_TOP_ASM_M_SEL, asm_parents, 0xC0, 24, 3, 31), - - MUX_GATE_MIXED(CLK_TOP_ASM_H_SEL, asm_parents, 0xD0, 0, 2, 7), - MUX_GATE_MIXED(CLK_TOP_MS_CARD_SEL, ms_card_parents, 0xD0, 16, 2, 23), - MUX_GATE_MIXED_FLAGS(CLK_TOP_ETHIF_SEL, ethif_parents, 0xD0, 24, 3, 31, - CLK_MUX_DOMAIN_SCPSYS), - - MUX_GATE_MIXED(CLK_TOP_HDMIRX26_24_SEL, hdmirx_parents, 0xE0, 0, 1, 7), - MUX_GATE_MIXED(CLK_TOP_MSDC30_3_SEL, msdc30_parents, 0xE0, 8, 3, 15), - MUX_GATE_MIXED(CLK_TOP_CMSYS_SEL, cmsys_parents, 0xE0, 16, 4, 23), - - MUX_GATE_MIXED(CLK_TOP_SPI1_SEL, spi_parents, 0xE0, 24, 3, 31), - MUX_GATE_MIXED(CLK_TOP_SPI2_SEL, spi_parents, 0xF0, 0, 3, 7), - MUX_GATE_MIXED(CLK_TOP_8BDAC_SEL, clk_8bdac_parents, 0xF0, 8, 2, 15), - MUX_GATE_MIXED(CLK_TOP_AUD2DVD_SEL, aud2dvd_parents, 0xF0, 16, 1, 23), - - MUX_MIXED(CLK_TOP_PADMCLK_SEL, padmclk_parents, 0x100, 0, 3), - - MUX_MIXED(CLK_TOP_AUD_MUX1_SEL, aud_mux_parents, 0x12c, 0, 3), - MUX_MIXED(CLK_TOP_AUD_MUX2_SEL, aud_mux_parents, 0x12c, 3, 3), - MUX_MIXED(CLK_TOP_AUDPLL_MUX_SEL, aud_mux_parents, 0x12c, 6, 3), - - MUX_GATE_MIXED(CLK_TOP_AUD_K1_SRC_SEL, aud_src_parents, 0x12c, 15, 1, 23), - MUX_GATE_MIXED(CLK_TOP_AUD_K2_SRC_SEL, aud_src_parents, 0x12c, 16, 1, 24), - MUX_GATE_MIXED(CLK_TOP_AUD_K3_SRC_SEL, aud_src_parents, 0x12c, 17, 1, 25), - MUX_GATE_MIXED(CLK_TOP_AUD_K4_SRC_SEL, aud_src_parents, 0x12c, 18, 1, 26), - MUX_GATE_MIXED(CLK_TOP_AUD_K5_SRC_SEL, aud_src_parents, 0x12c, 19, 1, 27), - MUX_GATE_MIXED(CLK_TOP_AUD_K6_SRC_SEL, aud_src_parents, 0x12c, 20, 1, 28), + MUX_GATE(CLK_TOP_AXI_SEL, axi_parents, 0x40, 0, 3, 7), + MUX_GATE(CLK_TOP_MEM_SEL, mem_parents, 0x40, 8, 1, 15), + MUX_GATE(CLK_TOP_DDRPHYCFG_SEL, ddrphycfg_parents, 0x40, 16, 1, 23), + MUX_GATE_FLAGS(CLK_TOP_MM_SEL, mm_parents, 0x40, 24, 3, 31, CLK_MUX_DOMAIN_SCPSYS), + + MUX_GATE(CLK_TOP_PWM_SEL, pwm_parents, 0x50, 0, 2, 7), + MUX_GATE(CLK_TOP_VDEC_SEL, vdec_parents, 0x50, 8, 4, 15), + MUX_GATE_FLAGS(CLK_TOP_MFG_SEL, mfg_parents, 0x50, 16, 3, 23, CLK_MUX_DOMAIN_SCPSYS), + MUX_GATE(CLK_TOP_CAMTG_SEL, camtg_parents, 0x50, 24, 3, 31), + + MUX_GATE(CLK_TOP_UART_SEL, uart_parents, 0x60, 0, 1, 7), + MUX_GATE(CLK_TOP_SPI0_SEL, spi_parents, 0x60, 8, 3, 15), + MUX_GATE(CLK_TOP_USB20_SEL, usb20_parents, 0x60, 16, 2, 23), + MUX_GATE(CLK_TOP_MSDC30_0_SEL, msdc30_parents, 0x60, 24, 3, 31), + + MUX_GATE(CLK_TOP_MSDC30_1_SEL, msdc30_parents, 0x70, 0, 3, 7), + MUX_GATE(CLK_TOP_MSDC30_2_SEL, msdc30_parents, 0x70, 8, 3, 15), + MUX_GATE(CLK_TOP_AUDIO_SEL, msdc30_parents, 0x70, 16, 1, 23), + MUX_GATE(CLK_TOP_AUDINTBUS_SEL, aud_intbus_parents, 0x70, 24, 3, 31), + + MUX_GATE(CLK_TOP_PMICSPI_SEL, pmicspi_parents, 0x80, 0, 4, 7), + MUX_GATE(CLK_TOP_SCP_SEL, scp_parents, 0x80, 8, 2, 15), + MUX_GATE(CLK_TOP_DPI0_SEL, dpi0_tve_parents, 0x80, 16, 3, 23), + MUX_GATE(CLK_TOP_DPI1_SEL, dpi1_parents, 0x80, 24, 2, 31), + + MUX_GATE(CLK_TOP_TVE_SEL, dpi0_tve_parents, 0x90, 0, 3, 7), + MUX_GATE(CLK_TOP_HDMI_SEL, hdmi_parents, 0x90, 8, 2, 15), + MUX_GATE(CLK_TOP_APLL_SEL, apll_parents, 0x90, 16, 3, 23), + + MUX_GATE(CLK_TOP_RTC_SEL, rtc_parents, 0xA0, 0, 2, 7), + MUX_GATE(CLK_TOP_NFI2X_SEL, nfi2x_parents, 0xA0, 8, 3, 15), + MUX_GATE(CLK_TOP_EMMC_HCLK_SEL, emmc_hclk_parents, 0xA0, 24, 2, 31), + + MUX_GATE(CLK_TOP_FLASH_SEL, flash_parents, 0xB0, 0, 3, 7), + MUX_GATE(CLK_TOP_DI_SEL, di_parents, 0xB0, 8, 2, 15), + MUX_GATE(CLK_TOP_NR_SEL, nr_osd_parents, 0xB0, 16, 3, 23), + MUX_GATE(CLK_TOP_OSD_SEL, nr_osd_parents, 0xB0, 24, 3, 31), + + MUX_GATE(CLK_TOP_HDMIRX_BIST_SEL, hdmirx_bist_parents, 0xC0, 0, 3, 7), + MUX_GATE(CLK_TOP_INTDIR_SEL, intdir_parents, 0xC0, 8, 2, 15), + MUX_GATE(CLK_TOP_ASM_I_SEL, asm_parents, 0xC0, 16, 2, 23), + MUX_GATE(CLK_TOP_ASM_M_SEL, asm_parents, 0xC0, 24, 3, 31), + + MUX_GATE(CLK_TOP_ASM_H_SEL, asm_parents, 0xD0, 0, 2, 7), + MUX_GATE(CLK_TOP_MS_CARD_SEL, ms_card_parents, 0xD0, 16, 2, 23), + MUX_GATE_FLAGS(CLK_TOP_ETHIF_SEL, ethif_parents, 0xD0, 24, 3, 31, CLK_MUX_DOMAIN_SCPSYS), + + MUX_GATE(CLK_TOP_HDMIRX26_24_SEL, hdmirx_parents, 0xE0, 0, 1, 7), + MUX_GATE(CLK_TOP_MSDC30_3_SEL, msdc30_parents, 0xE0, 8, 3, 15), + MUX_GATE(CLK_TOP_CMSYS_SEL, cmsys_parents, 0xE0, 16, 4, 23), + + MUX_GATE(CLK_TOP_SPI1_SEL, spi_parents, 0xE0, 24, 3, 31), + MUX_GATE(CLK_TOP_SPI2_SEL, spi_parents, 0xF0, 0, 3, 7), + MUX_GATE(CLK_TOP_8BDAC_SEL, clk_8bdac_parents, 0xF0, 8, 2, 15), + MUX_GATE(CLK_TOP_AUD2DVD_SEL, aud2dvd_parents, 0xF0, 16, 1, 23), + + MUX(CLK_TOP_PADMCLK_SEL, padmclk_parents, 0x100, 0, 3), + + MUX(CLK_TOP_AUD_MUX1_SEL, aud_mux_parents, 0x12c, 0, 3), + MUX(CLK_TOP_AUD_MUX2_SEL, aud_mux_parents, 0x12c, 3, 3), + MUX(CLK_TOP_AUDPLL_MUX_SEL, aud_mux_parents, 0x12c, 6, 3), + + MUX_GATE(CLK_TOP_AUD_K1_SRC_SEL, aud_src_parents, 0x12c, 15, 1, 23), + MUX_GATE(CLK_TOP_AUD_K2_SRC_SEL, aud_src_parents, 0x12c, 16, 1, 24), + MUX_GATE(CLK_TOP_AUD_K3_SRC_SEL, aud_src_parents, 0x12c, 17, 1, 25), + MUX_GATE(CLK_TOP_AUD_K4_SRC_SEL, aud_src_parents, 0x12c, 18, 1, 26), + MUX_GATE(CLK_TOP_AUD_K5_SRC_SEL, aud_src_parents, 0x12c, 19, 1, 27), + MUX_GATE(CLK_TOP_AUD_K6_SRC_SEL, aud_src_parents, 0x12c, 20, 1, 28), }; /* infracfg */ @@ -872,10 +869,10 @@ static const struct mtk_parent uart_ck_sel_parents[] = { }; static const struct mtk_composite peri_muxes[] = { - MUX_MIXED(CLK_PERI_UART0_SEL, uart_ck_sel_parents, 0x40C, 0, 1), - MUX_MIXED(CLK_PERI_UART1_SEL, uart_ck_sel_parents, 0x40C, 1, 1), - MUX_MIXED(CLK_PERI_UART2_SEL, uart_ck_sel_parents, 0x40C, 2, 1), - MUX_MIXED(CLK_PERI_UART3_SEL, uart_ck_sel_parents, 0x40C, 3, 1), + MUX(CLK_PERI_UART0_SEL, uart_ck_sel_parents, 0x40C, 0, 1), + MUX(CLK_PERI_UART1_SEL, uart_ck_sel_parents, 0x40C, 1, 1), + MUX(CLK_PERI_UART2_SEL, uart_ck_sel_parents, 0x40C, 2, 1), + MUX(CLK_PERI_UART3_SEL, uart_ck_sel_parents, 0x40C, 3, 1), }; static const struct mtk_gate_regs peri0_cg_regs = { diff --git a/drivers/clk/mediatek/clk-mt7629.c b/drivers/clk/mediatek/clk-mt7629.c index c675104d573..42670269d3e 100644 --- a/drivers/clk/mediatek/clk-mt7629.c +++ b/drivers/clk/mediatek/clk-mt7629.c @@ -365,58 +365,57 @@ static const struct mtk_parent gpt10m_parents[] = { static const struct mtk_composite top_muxes[] = { /* CLK_CFG_0 */ - MUX_GATE_MIXED(CLK_TOP_AXI_SEL, axi_parents, 0x40, 0, 3, 7), - MUX_GATE_MIXED(CLK_TOP_MEM_SEL, mem_parents, 0x40, 8, 1, 15), - MUX_GATE_MIXED(CLK_TOP_DDRPHYCFG_SEL, ddrphycfg_parents, 0x40, 16, 1, 23), - MUX_GATE_MIXED(CLK_TOP_ETH_SEL, eth_parents, 0x40, 24, 3, 31), + MUX_GATE(CLK_TOP_AXI_SEL, axi_parents, 0x40, 0, 3, 7), + MUX_GATE(CLK_TOP_MEM_SEL, mem_parents, 0x40, 8, 1, 15), + MUX_GATE(CLK_TOP_DDRPHYCFG_SEL, ddrphycfg_parents, 0x40, 16, 1, 23), + MUX_GATE(CLK_TOP_ETH_SEL, eth_parents, 0x40, 24, 3, 31), /* CLK_CFG_1 */ - MUX_GATE_MIXED(CLK_TOP_PWM_SEL, pwm_parents, 0x50, 0, 2, 7), - MUX_GATE_MIXED(CLK_TOP_F10M_REF_SEL, irrx_parents, 0x50, 8, 1, 15), - MUX_GATE_MIXED(CLK_TOP_NFI_INFRA_SEL, nfi_infra_parents, 0x50, 16, 4, 23), - MUX_GATE_MIXED(CLK_TOP_FLASH_SEL, flash_parents, 0x50, 24, 3, 31), + MUX_GATE(CLK_TOP_PWM_SEL, pwm_parents, 0x50, 0, 2, 7), + MUX_GATE(CLK_TOP_F10M_REF_SEL, irrx_parents, 0x50, 8, 1, 15), + MUX_GATE(CLK_TOP_NFI_INFRA_SEL, nfi_infra_parents, 0x50, 16, 4, 23), + MUX_GATE(CLK_TOP_FLASH_SEL, flash_parents, 0x50, 24, 3, 31), /* CLK_CFG_2 */ - MUX_GATE_MIXED(CLK_TOP_UART_SEL, uart_parents, 0x60, 0, 1, 7), - MUX_GATE_MIXED(CLK_TOP_SPI0_SEL, spi0_parents, 0x60, 8, 3, 15), - MUX_GATE_MIXED(CLK_TOP_SPI1_SEL, spi1_parents, 0x60, 16, 3, 23), - MUX_GATE_MIXED(CLK_TOP_MSDC50_0_SEL, uart_parents, 0x60, 24, 3, 31), + MUX_GATE(CLK_TOP_UART_SEL, uart_parents, 0x60, 0, 1, 7), + MUX_GATE(CLK_TOP_SPI0_SEL, spi0_parents, 0x60, 8, 3, 15), + MUX_GATE(CLK_TOP_SPI1_SEL, spi1_parents, 0x60, 16, 3, 23), + MUX_GATE(CLK_TOP_MSDC50_0_SEL, uart_parents, 0x60, 24, 3, 31), /* CLK_CFG_3 */ - MUX_GATE_MIXED(CLK_TOP_MSDC30_0_SEL, msdc30_0_parents, 0x70, 0, 3, 7), - MUX_GATE_MIXED(CLK_TOP_MSDC30_1_SEL, msdc30_1_parents, 0x70, 8, 3, 15), - MUX_GATE_MIXED(CLK_TOP_AP2WBMCU_SEL, ap2wbmcu_parents, 0x70, 16, 3, 23), - MUX_GATE_MIXED(CLK_TOP_AP2WBHIF_SEL, ap2wbmcu_parents, 0x70, 24, 3, 31), + MUX_GATE(CLK_TOP_MSDC30_0_SEL, msdc30_0_parents, 0x70, 0, 3, 7), + MUX_GATE(CLK_TOP_MSDC30_1_SEL, msdc30_1_parents, 0x70, 8, 3, 15), + MUX_GATE(CLK_TOP_AP2WBMCU_SEL, ap2wbmcu_parents, 0x70, 16, 3, 23), + MUX_GATE(CLK_TOP_AP2WBHIF_SEL, ap2wbmcu_parents, 0x70, 24, 3, 31), /* CLK_CFG_4 */ - MUX_GATE_MIXED(CLK_TOP_AUDIO_SEL, audio_parents, 0x80, 0, 2, 7), - MUX_GATE_MIXED(CLK_TOP_AUD_INTBUS_SEL, aud_intbus_parents, 0x80, 8, 2, 15), - MUX_GATE_MIXED(CLK_TOP_PMICSPI_SEL, pmicspi_parents, 0x80, 16, 3, 23), - MUX_GATE_MIXED(CLK_TOP_SCP_SEL, scp_parents, 0x80, 24, 2, 31), + MUX_GATE(CLK_TOP_AUDIO_SEL, audio_parents, 0x80, 0, 2, 7), + MUX_GATE(CLK_TOP_AUD_INTBUS_SEL, aud_intbus_parents, 0x80, 8, 2, 15), + MUX_GATE(CLK_TOP_PMICSPI_SEL, pmicspi_parents, 0x80, 16, 3, 23), + MUX_GATE(CLK_TOP_SCP_SEL, scp_parents, 0x80, 24, 2, 31), /* CLK_CFG_5 */ - MUX_GATE_MIXED(CLK_TOP_ATB_SEL, atb_parents, 0x90, 0, 2, 7), - MUX_GATE_MIXED_FLAGS(CLK_TOP_HIF_SEL, hif_parents, 0x90, 8, 3, 15, - CLK_MUX_DOMAIN_SCPSYS), - MUX_GATE_MIXED(CLK_TOP_SATA_SEL, sata_parents, 0x90, 16, 1, 23), - MUX_GATE_MIXED(CLK_TOP_U2_SEL, usb20_parents, 0x90, 24, 2, 31), + MUX_GATE(CLK_TOP_ATB_SEL, atb_parents, 0x90, 0, 2, 7), + MUX_GATE_FLAGS(CLK_TOP_HIF_SEL, hif_parents, 0x90, 8, 3, 15, CLK_MUX_DOMAIN_SCPSYS), + MUX_GATE(CLK_TOP_SATA_SEL, sata_parents, 0x90, 16, 1, 23), + MUX_GATE(CLK_TOP_U2_SEL, usb20_parents, 0x90, 24, 2, 31), /* CLK_CFG_6 */ - MUX_GATE_MIXED(CLK_TOP_AUD1_SEL, aud1_parents, 0xA0, 0, 1, 7), - MUX_GATE_MIXED(CLK_TOP_AUD2_SEL, aud1_parents, 0xA0, 8, 1, 15), - MUX_GATE_MIXED(CLK_TOP_IRRX_SEL, irrx_parents, 0xA0, 16, 1, 23), - MUX_GATE_MIXED(CLK_TOP_IRTX_SEL, irrx_parents, 0xA0, 24, 1, 31), + MUX_GATE(CLK_TOP_AUD1_SEL, aud1_parents, 0xA0, 0, 1, 7), + MUX_GATE(CLK_TOP_AUD2_SEL, aud1_parents, 0xA0, 8, 1, 15), + MUX_GATE(CLK_TOP_IRRX_SEL, irrx_parents, 0xA0, 16, 1, 23), + MUX_GATE(CLK_TOP_IRTX_SEL, irrx_parents, 0xA0, 24, 1, 31), /* CLK_CFG_7 */ - MUX_GATE_MIXED(CLK_TOP_SATA_MCU_SEL, scp_parents, 0xB0, 0, 2, 7), - MUX_GATE_MIXED(CLK_TOP_PCIE0_MCU_SEL, scp_parents, 0xB0, 8, 2, 15), - MUX_GATE_MIXED(CLK_TOP_PCIE1_MCU_SEL, scp_parents, 0xB0, 16, 2, 23), - MUX_GATE_MIXED(CLK_TOP_SSUSB_MCU_SEL, scp_parents, 0xB0, 24, 2, 31), + MUX_GATE(CLK_TOP_SATA_MCU_SEL, scp_parents, 0xB0, 0, 2, 7), + MUX_GATE(CLK_TOP_PCIE0_MCU_SEL, scp_parents, 0xB0, 8, 2, 15), + MUX_GATE(CLK_TOP_PCIE1_MCU_SEL, scp_parents, 0xB0, 16, 2, 23), + MUX_GATE(CLK_TOP_SSUSB_MCU_SEL, scp_parents, 0xB0, 24, 2, 31), /* CLK_CFG_8 */ - MUX_GATE_MIXED(CLK_TOP_CRYPTO_SEL, crypto_parents, 0xC0, 0, 3, 7), - MUX_GATE_MIXED(CLK_TOP_SGMII_REF_1_SEL, sgmii_ref_1_parents, 0xC0, 8, 1, 15), - MUX_GATE_MIXED(CLK_TOP_10M_SEL, gpt10m_parents, 0xC0, 16, 1, 23), + MUX_GATE(CLK_TOP_CRYPTO_SEL, crypto_parents, 0xC0, 0, 3, 7), + MUX_GATE(CLK_TOP_SGMII_REF_1_SEL, sgmii_ref_1_parents, 0xC0, 8, 1, 15), + MUX_GATE(CLK_TOP_10M_SEL, gpt10m_parents, 0xC0, 16, 1, 23), }; /* infracfg */ diff --git a/drivers/clk/mediatek/clk-mt7981.c b/drivers/clk/mediatek/clk-mt7981.c index cdd9b9e4092..685abd844f2 100644 --- a/drivers/clk/mediatek/clk-mt7981.c +++ b/drivers/clk/mediatek/clk-mt7981.c @@ -336,9 +336,9 @@ static const struct mtk_parent usb_frmcnt_parents[] = { .upd_shift = _upd, .mux_shift = _shift, \ .mux_mask = BIT(_width) - 1, .gate_reg = _mux_ofs, \ .gate_shift = _gate, \ - .parent_flags = _parents, \ + .parent = _parents, \ .num_parents = ARRAY_SIZE(_parents), \ - .flags = CLK_MUX_SETCLR_UPD | CLK_PARENT_MIXED, \ + .flags = CLK_MUX_SETCLR_UPD, \ } /* TOPCKGEN MUX_GATE */ @@ -458,8 +458,9 @@ static const struct mtk_parent infra_pcie_parents[] = { .mux_set_reg = (_reg) + 0x0, .mux_clr_reg = (_reg) + 0x4, \ .mux_shift = _shift, .mux_mask = BIT(_width) - 1, \ .gate_shift = -1, .upd_shift = -1, \ - .parent_flags = _parents, .num_parents = ARRAY_SIZE(_parents), \ - .flags = CLK_MUX_SETCLR_UPD | CLK_PARENT_MIXED, \ + .parent = _parents, \ + .num_parents = ARRAY_SIZE(_parents), \ + .flags = CLK_MUX_SETCLR_UPD, \ } /* INFRA MUX */ diff --git a/drivers/clk/mediatek/clk-mt7986.c b/drivers/clk/mediatek/clk-mt7986.c index 65d4142fa63..ed65aa81a21 100644 --- a/drivers/clk/mediatek/clk-mt7986.c +++ b/drivers/clk/mediatek/clk-mt7986.c @@ -229,9 +229,10 @@ static const struct mtk_parent da_u2_refsel_parents[] = { .mux_clr_reg = _mux_clr_ofs, .upd_reg = _upd_ofs, \ .upd_shift = _upd, .mux_shift = _shift, \ .mux_mask = BIT(_width) - 1, .gate_reg = _mux_ofs, \ - .gate_shift = _gate, .parent_flags = _parents, \ + .gate_shift = _gate, \ + .parent = _parents, \ .num_parents = ARRAY_SIZE(_parents), \ - .flags = CLK_MUX_SETCLR_UPD | CLK_PARENT_MIXED, \ + .flags = CLK_MUX_SETCLR_UPD, \ } /* TOPCKGEN MUX_GATE */ @@ -365,8 +366,9 @@ static const struct mtk_parent infra_pcie_parents[] = { .mux_set_reg = (_reg) + 0x0, .mux_clr_reg = (_reg) + 0x4, \ .mux_shift = _shift, .mux_mask = BIT(_width) - 1, \ .gate_shift = -1, .upd_shift = -1, \ - .parent_flags = _parents, .num_parents = ARRAY_SIZE(_parents), \ - .flags = CLK_MUX_SETCLR_UPD | CLK_PARENT_MIXED, \ + .parent = _parents, \ + .num_parents = ARRAY_SIZE(_parents), \ + .flags = CLK_MUX_SETCLR_UPD, \ } /* INFRA MUX */ diff --git a/drivers/clk/mediatek/clk-mt7987.c b/drivers/clk/mediatek/clk-mt7987.c index 5ae76a2c47a..2fdd0fd20c9 100644 --- a/drivers/clk/mediatek/clk-mt7987.c +++ b/drivers/clk/mediatek/clk-mt7987.c @@ -339,9 +339,9 @@ static const struct mtk_parent emmc_200m_parents[] = { .upd_reg = (_upd_ofs), .upd_shift = (_upd), \ .mux_shift = (_shift), .mux_mask = BIT(_width) - 1, \ .gate_reg = (_mux_ofs), .gate_shift = (_gate), \ - .parent_flags = (_parents), \ + .parent = (_parents), \ .num_parents = ARRAY_SIZE(_parents), \ - .flags = CLK_MUX_SETCLR_UPD | CLK_PARENT_MIXED, \ + .flags = CLK_MUX_SETCLR_UPD, \ } /* TOPCKGEN MUX_GATE */ @@ -545,9 +545,9 @@ static const struct mtk_parent infra_pcie_gfmux_tl_ck_o_p1_parents[] = { .mux_clr_reg = (_reg) + 0x4, .mux_set_reg = (_reg) + 0x0, \ .mux_shift = (_shift), .mux_mask = BIT(_width) - 1, \ .gate_shift = -1, .upd_shift = -1, \ - .parent_flags = (_parents), \ + .parent = (_parents), \ .num_parents = ARRAY_SIZE(_parents), \ - .flags = CLK_MUX_SETCLR_UPD | CLK_PARENT_MIXED, \ + .flags = CLK_MUX_SETCLR_UPD, \ } /* INFRA MUX */ diff --git a/drivers/clk/mediatek/clk-mt7988.c b/drivers/clk/mediatek/clk-mt7988.c index 38a5c20035d..f951a6fc58d 100644 --- a/drivers/clk/mediatek/clk-mt7988.c +++ b/drivers/clk/mediatek/clk-mt7988.c @@ -281,9 +281,10 @@ static const struct mtk_parent eth_mii_parents[] = { .mux_clr_reg = _mux_clr_ofs, .upd_reg = _upd_ofs, \ .upd_shift = _upd, .mux_shift = _shift, \ .mux_mask = BIT(_width) - 1, .gate_reg = _mux_ofs, \ - .gate_shift = _gate, .parent_flags = _parents, \ + .gate_shift = _gate, \ + .parent = _parents, \ .num_parents = ARRAY_SIZE(_parents), \ - .flags = CLK_MUX_SETCLR_UPD | CLK_PARENT_MIXED, \ + .flags = CLK_MUX_SETCLR_UPD, \ } /* TOPCKGEN MUX_GATE */ @@ -509,10 +510,10 @@ static const struct mtk_parent infra_pcie_gfmux_tl_ck_o_p3_parents[] = { .id = _id, .mux_reg = _reg + 0x8, .mux_set_reg = _reg + 0x0, \ .mux_clr_reg = _reg + 0x4, .mux_shift = _shift, \ .mux_mask = BIT(_width) - 1, \ - .parent_flags = _parents, \ + .parent = _parents, \ .gate_shift = -1, .upd_shift = -1, \ .num_parents = ARRAY_SIZE(_parents), \ - .flags = CLK_MUX_SETCLR_UPD | CLK_PARENT_MIXED, \ + .flags = CLK_MUX_SETCLR_UPD, \ } /* INFRA MUX */ diff --git a/drivers/clk/mediatek/clk-mt8183.c b/drivers/clk/mediatek/clk-mt8183.c index d98614d8da6..54e31efd2ea 100644 --- a/drivers/clk/mediatek/clk-mt8183.c +++ b/drivers/clk/mediatek/clk-mt8183.c @@ -542,58 +542,58 @@ static const struct mtk_parent aud_2_parents[] = { static const struct mtk_composite top_muxes[] = { /* CLK_CFG_0 */ - MUX_MIXED(CLK_TOP_MUX_AXI, axi_parents, 0x40, 0, 2), - MUX_MIXED(CLK_TOP_MUX_MM, mm_parents, 0x40, 8, 3), - MUX_MIXED(CLK_TOP_MUX_IMG, img_parents, 0x40, 16, 3), - MUX_MIXED(CLK_TOP_MUX_CAM, cam_parents, 0x40, 24, 4), + MUX(CLK_TOP_MUX_AXI, axi_parents, 0x40, 0, 2), + MUX(CLK_TOP_MUX_MM, mm_parents, 0x40, 8, 3), + MUX(CLK_TOP_MUX_IMG, img_parents, 0x40, 16, 3), + MUX(CLK_TOP_MUX_CAM, cam_parents, 0x40, 24, 4), /* CLK_CFG_1 */ - MUX_MIXED(CLK_TOP_MUX_DSP, dsp_parents, 0x50, 0, 4), - MUX_MIXED(CLK_TOP_MUX_DSP1, dsp1_parents, 0x50, 8, 4), - MUX_MIXED(CLK_TOP_MUX_DSP2, dsp2_parents, 0x50, 16, 4), - MUX_MIXED(CLK_TOP_MUX_IPU_IF, ipu_if_parents, 0x50, 24, 4), + MUX(CLK_TOP_MUX_DSP, dsp_parents, 0x50, 0, 4), + MUX(CLK_TOP_MUX_DSP1, dsp1_parents, 0x50, 8, 4), + MUX(CLK_TOP_MUX_DSP2, dsp2_parents, 0x50, 16, 4), + MUX(CLK_TOP_MUX_IPU_IF, ipu_if_parents, 0x50, 24, 4), /* CLK_CFG_2 */ - MUX_MIXED(CLK_TOP_MUX_MFG, mfg_parents, 0x60, 0, 2), - MUX_MIXED(CLK_TOP_MUX_F52M_MFG, f52m_mfg_parents, 0x60, 8, 2), - MUX_MIXED(CLK_TOP_MUX_CAMTG, camtg_parents, 0x60, 16, 3), - MUX_MIXED(CLK_TOP_MUX_CAMTG2, camtg2_parents, 0x60, 24, 3), + MUX(CLK_TOP_MUX_MFG, mfg_parents, 0x60, 0, 2), + MUX(CLK_TOP_MUX_F52M_MFG, f52m_mfg_parents, 0x60, 8, 2), + MUX(CLK_TOP_MUX_CAMTG, camtg_parents, 0x60, 16, 3), + MUX(CLK_TOP_MUX_CAMTG2, camtg2_parents, 0x60, 24, 3), /* CLK_CFG_3 */ - MUX_MIXED(CLK_TOP_MUX_CAMTG3, camtg3_parents, 0x70, 0, 3), - MUX_MIXED(CLK_TOP_MUX_CAMTG4, camtg4_parents, 0x70, 8, 3), - MUX_MIXED(CLK_TOP_MUX_UART, uart_parents, 0x70, 16, 1), - MUX_MIXED(CLK_TOP_MUX_SPI, spi_parents, 0x70, 24, 2), + MUX(CLK_TOP_MUX_CAMTG3, camtg3_parents, 0x70, 0, 3), + MUX(CLK_TOP_MUX_CAMTG4, camtg4_parents, 0x70, 8, 3), + MUX(CLK_TOP_MUX_UART, uart_parents, 0x70, 16, 1), + MUX(CLK_TOP_MUX_SPI, spi_parents, 0x70, 24, 2), /* CLK_CFG_4 */ - MUX_MIXED(CLK_TOP_MUX_MSDC50_0_HCLK, msdc50_hclk_parents, 0x80, 0, 2), - MUX_MIXED(CLK_TOP_MUX_MSDC50_0, msdc50_0_parents, 0x80, 8, 3), - MUX_MIXED(CLK_TOP_MUX_MSDC30_1, msdc30_1_parents, 0x80, 16, 3), - MUX_MIXED(CLK_TOP_MUX_MSDC30_2, msdc30_2_parents, 0x80, 24, 3), + MUX(CLK_TOP_MUX_MSDC50_0_HCLK, msdc50_hclk_parents, 0x80, 0, 2), + MUX(CLK_TOP_MUX_MSDC50_0, msdc50_0_parents, 0x80, 8, 3), + MUX(CLK_TOP_MUX_MSDC30_1, msdc30_1_parents, 0x80, 16, 3), + MUX(CLK_TOP_MUX_MSDC30_2, msdc30_2_parents, 0x80, 24, 3), /* CLK_CFG_5 */ - MUX_MIXED(CLK_TOP_MUX_AUDIO, audio_parents, 0x90, 0, 2), - MUX_MIXED(CLK_TOP_MUX_AUD_INTBUS, aud_intbus_parents, 0x90, 8, 2), - MUX_MIXED(CLK_TOP_MUX_PMICSPI, pmicspi_parents, 0x90, 16, 2), - MUX_MIXED(CLK_TOP_MUX_FPWRAP_ULPOSC, fpwrap_ulposc_parents, 0x90, 24, 2), + MUX(CLK_TOP_MUX_AUDIO, audio_parents, 0x90, 0, 2), + MUX(CLK_TOP_MUX_AUD_INTBUS, aud_intbus_parents, 0x90, 8, 2), + MUX(CLK_TOP_MUX_PMICSPI, pmicspi_parents, 0x90, 16, 2), + MUX(CLK_TOP_MUX_FPWRAP_ULPOSC, fpwrap_ulposc_parents, 0x90, 24, 2), /* CLK_CFG_6 */ - MUX_MIXED(CLK_TOP_MUX_ATB, atb_parents, 0xa0, 0, 2), - MUX_MIXED(CLK_TOP_MUX_SSPM, sspm_parents, 0xa0, 8, 3), - MUX_MIXED(CLK_TOP_MUX_DPI0, dpi0_parents, 0xa0, 16, 4), - MUX_MIXED(CLK_TOP_MUX_SCAM, scam_parents, 0xa0, 24, 1), + MUX(CLK_TOP_MUX_ATB, atb_parents, 0xa0, 0, 2), + MUX(CLK_TOP_MUX_SSPM, sspm_parents, 0xa0, 8, 3), + MUX(CLK_TOP_MUX_DPI0, dpi0_parents, 0xa0, 16, 4), + MUX(CLK_TOP_MUX_SCAM, scam_parents, 0xa0, 24, 1), /* CLK_CFG_7 */ - MUX_MIXED(CLK_TOP_MUX_DISP_PWM, disppwm_parents, 0xb0, 0, 3), - MUX_MIXED(CLK_TOP_MUX_USB_TOP, usb_top_parents, 0xb0, 8, 2), - MUX_MIXED(CLK_TOP_MUX_SSUSB_TOP_XHCI, ssusb_top_xhci_parents, 0xb0, 16, 2), - MUX_MIXED(CLK_TOP_MUX_SPM, spm_parents, 0xb0, 24, 1), + MUX(CLK_TOP_MUX_DISP_PWM, disppwm_parents, 0xb0, 0, 3), + MUX(CLK_TOP_MUX_USB_TOP, usb_top_parents, 0xb0, 8, 2), + MUX(CLK_TOP_MUX_SSUSB_TOP_XHCI, ssusb_top_xhci_parents, 0xb0, 16, 2), + MUX(CLK_TOP_MUX_SPM, spm_parents, 0xb0, 24, 1), /* CLK_CFG_8 */ - MUX_MIXED(CLK_TOP_MUX_I2C, i2c_parents, 0xc0, 0, 2), - MUX_MIXED(CLK_TOP_MUX_SCP, scp_parents, 0xc0, 8, 3), - MUX_MIXED(CLK_TOP_MUX_SENINF, seninf_parents, 0xc0, 16, 2), - MUX_MIXED(CLK_TOP_MUX_DXCC, dxcc_parents, 0xc0, 24, 2), + MUX(CLK_TOP_MUX_I2C, i2c_parents, 0xc0, 0, 2), + MUX(CLK_TOP_MUX_SCP, scp_parents, 0xc0, 8, 3), + MUX(CLK_TOP_MUX_SENINF, seninf_parents, 0xc0, 16, 2), + MUX(CLK_TOP_MUX_DXCC, dxcc_parents, 0xc0, 24, 2), /* CLK_CFG_9 */ - MUX_MIXED(CLK_TOP_MUX_AUD_ENG1, aud_engen1_parents, 0xd0, 0, 2), - MUX_MIXED(CLK_TOP_MUX_AUD_ENG2, aud_engen2_parents, 0xd0, 8, 2), - MUX_MIXED(CLK_TOP_MUX_FAES_UFSFDE, faes_ufsfde_parents, 0xd0, 16, 3), - MUX_MIXED(CLK_TOP_MUX_FUFS, fufs_parents, 0xd0, 24, 2), + MUX(CLK_TOP_MUX_AUD_ENG1, aud_engen1_parents, 0xd0, 0, 2), + MUX(CLK_TOP_MUX_AUD_ENG2, aud_engen2_parents, 0xd0, 8, 2), + MUX(CLK_TOP_MUX_FAES_UFSFDE, faes_ufsfde_parents, 0xd0, 16, 3), + MUX(CLK_TOP_MUX_FUFS, fufs_parents, 0xd0, 24, 2), /* CLK_CFG_10 */ - MUX_MIXED(CLK_TOP_MUX_AUD_1, aud_1_parents, 0xe0, 0, 1), - MUX_MIXED(CLK_TOP_MUX_AUD_2, aud_2_parents, 0xe0, 8, 1), + MUX(CLK_TOP_MUX_AUD_1, aud_1_parents, 0xe0, 0, 1), + MUX(CLK_TOP_MUX_AUD_2, aud_2_parents, 0xe0, 8, 1), }; static const struct mtk_clk_tree mt8183_clk_tree = { diff --git a/drivers/clk/mediatek/clk-mt8188.c b/drivers/clk/mediatek/clk-mt8188.c index 1db5350763e..706390b6c6c 100644 --- a/drivers/clk/mediatek/clk-mt8188.c +++ b/drivers/clk/mediatek/clk-mt8188.c @@ -1027,119 +1027,119 @@ static const struct mtk_parent srck_parents[] = { static const struct mtk_composite top_muxes[] = { /* CLK_CFG_0 */ - MUX_GATE_MIXED(CLK_TOP_AXI, axi_parents, 0x020, 0, 4, 7), - MUX_GATE_MIXED(CLK_TOP_SPM, spm_parents, 0x020, 8, 4, 15), - MUX_GATE_MIXED(CLK_TOP_SCP, scp_parents, 0x020, 16, 4, 23), - MUX_GATE_MIXED(CLK_TOP_BUS_AXIMEM, bus_aximem_parents, 0x020, 24, 4, 31), + MUX_GATE(CLK_TOP_AXI, axi_parents, 0x020, 0, 4, 7), + MUX_GATE(CLK_TOP_SPM, spm_parents, 0x020, 8, 4, 15), + MUX_GATE(CLK_TOP_SCP, scp_parents, 0x020, 16, 4, 23), + MUX_GATE(CLK_TOP_BUS_AXIMEM, bus_aximem_parents, 0x020, 24, 4, 31), /* CLK_CFG_1 */ - MUX_GATE_MIXED(CLK_TOP_VPP, vpp_parents, 0x02C, 0, 4, 7), - MUX_GATE_MIXED(CLK_TOP_ETHDR, ethdr_parents, 0x02C, 8, 4, 15), - MUX_GATE_MIXED(CLK_TOP_IPE, ipe_parents, 0x02C, 16, 4, 23), - MUX_GATE_MIXED(CLK_TOP_CAM, cam_parents, 0x02C, 24, 4, 31), + MUX_GATE(CLK_TOP_VPP, vpp_parents, 0x02C, 0, 4, 7), + MUX_GATE(CLK_TOP_ETHDR, ethdr_parents, 0x02C, 8, 4, 15), + MUX_GATE(CLK_TOP_IPE, ipe_parents, 0x02C, 16, 4, 23), + MUX_GATE(CLK_TOP_CAM, cam_parents, 0x02C, 24, 4, 31), /* CLK_CFG_2 */ - MUX_GATE_MIXED(CLK_TOP_CCU, ccu_parents, 0x038, 0, 4, 7), - MUX_GATE_MIXED(CLK_TOP_CCU_AHB, ccu_ahb_parents, 0x038, 8, 4, 15), - MUX_GATE_MIXED(CLK_TOP_IMG, img_parents, 0x038, 16, 4, 23), - MUX_GATE_MIXED(CLK_TOP_CAMTM, camtm_parents, 0x038, 24, 4, 31), + MUX_GATE(CLK_TOP_CCU, ccu_parents, 0x038, 0, 4, 7), + MUX_GATE(CLK_TOP_CCU_AHB, ccu_ahb_parents, 0x038, 8, 4, 15), + MUX_GATE(CLK_TOP_IMG, img_parents, 0x038, 16, 4, 23), + MUX_GATE(CLK_TOP_CAMTM, camtm_parents, 0x038, 24, 4, 31), /* CLK_CFG_3 */ - MUX_GATE_MIXED(CLK_TOP_DSP, dsp_parents, 0x044, 0, 4, 7), - MUX_GATE_MIXED(CLK_TOP_DSP1, dsp1_parents, 0x044, 8, 4, 15), - MUX_GATE_MIXED(CLK_TOP_DSP2, dsp2_parents, 0x044, 16, 4, 23), - MUX_GATE_MIXED(CLK_TOP_DSP3, dsp3_parents, 0x044, 24, 4, 31), + MUX_GATE(CLK_TOP_DSP, dsp_parents, 0x044, 0, 4, 7), + MUX_GATE(CLK_TOP_DSP1, dsp1_parents, 0x044, 8, 4, 15), + MUX_GATE(CLK_TOP_DSP2, dsp2_parents, 0x044, 16, 4, 23), + MUX_GATE(CLK_TOP_DSP3, dsp3_parents, 0x044, 24, 4, 31), /* CLK_CFG_4 */ - MUX_GATE_MIXED(CLK_TOP_DSP4, dsp4_parents, 0x050, 0, 4, 7), - MUX_GATE_MIXED(CLK_TOP_DSP5, dsp5_parents, 0x050, 8, 4, 15), - MUX_GATE_MIXED(CLK_TOP_DSP6, dsp6_parents, 0x050, 16, 4, 23), - MUX_GATE_MIXED(CLK_TOP_DSP7, dsp7_parents, 0x050, 24, 4, 31), + MUX_GATE(CLK_TOP_DSP4, dsp4_parents, 0x050, 0, 4, 7), + MUX_GATE(CLK_TOP_DSP5, dsp5_parents, 0x050, 8, 4, 15), + MUX_GATE(CLK_TOP_DSP6, dsp6_parents, 0x050, 16, 4, 23), + MUX_GATE(CLK_TOP_DSP7, dsp7_parents, 0x050, 24, 4, 31), /* CLK_CFG_5 */ - MUX_GATE_MIXED(CLK_TOP_MFG_CORE_TMP, mfg_core_tmp_parents, 0x05C, 0, 4, 7), - MUX_GATE_MIXED(CLK_TOP_CAMTG, camtg_parents, 0x05C, 8, 4, 15), - MUX_GATE_MIXED(CLK_TOP_CAMTG2, camtg2_parents, 0x05C, 16, 4, 23), - MUX_GATE_MIXED(CLK_TOP_CAMTG3, camtg3_parents, 0x05C, 24, 4, 31), + MUX_GATE(CLK_TOP_MFG_CORE_TMP, mfg_core_tmp_parents, 0x05C, 0, 4, 7), + MUX_GATE(CLK_TOP_CAMTG, camtg_parents, 0x05C, 8, 4, 15), + MUX_GATE(CLK_TOP_CAMTG2, camtg2_parents, 0x05C, 16, 4, 23), + MUX_GATE(CLK_TOP_CAMTG3, camtg3_parents, 0x05C, 24, 4, 31), /* CLK_CFG_6 */ - MUX_GATE_MIXED(CLK_TOP_UART, uart_parents, 0x068, 0, 4, 7), - MUX_GATE_MIXED(CLK_TOP_SPI, spi_parents, 0x068, 8, 4, 15), - MUX_GATE_MIXED(CLK_TOP_MSDC50_0_HCLK, msdc5hclk_parents, 0x068, 16, 4, 23), - MUX_GATE_MIXED(CLK_TOP_MSDC50_0, msdc50_0_parents, 0x068, 24, 4, 31), + MUX_GATE(CLK_TOP_UART, uart_parents, 0x068, 0, 4, 7), + MUX_GATE(CLK_TOP_SPI, spi_parents, 0x068, 8, 4, 15), + MUX_GATE(CLK_TOP_MSDC50_0_HCLK, msdc5hclk_parents, 0x068, 16, 4, 23), + MUX_GATE(CLK_TOP_MSDC50_0, msdc50_0_parents, 0x068, 24, 4, 31), /* CLK_CFG_7 */ - MUX_GATE_MIXED(CLK_TOP_MSDC30_1, msdc30_1_parents, 0x074, 0, 4, 7), - MUX_GATE_MIXED(CLK_TOP_MSDC30_2, msdc30_2_parents, 0x074, 8, 4, 15), - MUX_GATE_MIXED(CLK_TOP_INTDIR, intdir_parents, 0x074, 16, 4, 23), - MUX_GATE_MIXED(CLK_TOP_AUD_INTBUS, aud_intbus_parents, 0x074, 24, 4, 31), + MUX_GATE(CLK_TOP_MSDC30_1, msdc30_1_parents, 0x074, 0, 4, 7), + MUX_GATE(CLK_TOP_MSDC30_2, msdc30_2_parents, 0x074, 8, 4, 15), + MUX_GATE(CLK_TOP_INTDIR, intdir_parents, 0x074, 16, 4, 23), + MUX_GATE(CLK_TOP_AUD_INTBUS, aud_intbus_parents, 0x074, 24, 4, 31), /* CLK_CFG_8 */ - MUX_GATE_MIXED(CLK_TOP_AUDIO_H, audio_h_parents, 0x080, 0, 4, 7), - MUX_GATE_MIXED(CLK_TOP_PWRAP_ULPOSC, pwrap_ulposc_parents, 0x080, 8, 4, 15), - MUX_GATE_MIXED(CLK_TOP_ATB, atb_parents, 0x080, 16, 4, 23), - MUX_GATE_MIXED(CLK_TOP_SSPM, sspm_parents, 0x080, 24, 4, 31), + MUX_GATE(CLK_TOP_AUDIO_H, audio_h_parents, 0x080, 0, 4, 7), + MUX_GATE(CLK_TOP_PWRAP_ULPOSC, pwrap_ulposc_parents, 0x080, 8, 4, 15), + MUX_GATE(CLK_TOP_ATB, atb_parents, 0x080, 16, 4, 23), + MUX_GATE(CLK_TOP_SSPM, sspm_parents, 0x080, 24, 4, 31), /* CLK_CFG_9 */ - MUX_GATE_MIXED(CLK_TOP_DP, dp_parents, 0x08C, 0, 4, 7), - MUX_GATE_MIXED(CLK_TOP_EDP, edp_parents, 0x08C, 8, 4, 15), - MUX_GATE_MIXED(CLK_TOP_DPI, dpi_parents, 0x08C, 16, 4, 23), - MUX_GATE_MIXED(CLK_TOP_DISP_PWM0, disp_pwm0_parents, 0x08C, 24, 4, 31), + MUX_GATE(CLK_TOP_DP, dp_parents, 0x08C, 0, 4, 7), + MUX_GATE(CLK_TOP_EDP, edp_parents, 0x08C, 8, 4, 15), + MUX_GATE(CLK_TOP_DPI, dpi_parents, 0x08C, 16, 4, 23), + MUX_GATE(CLK_TOP_DISP_PWM0, disp_pwm0_parents, 0x08C, 24, 4, 31), /* CLK_CFG_10 */ - MUX_GATE_MIXED(CLK_TOP_DISP_PWM1, disp_pwm1_parents, 0x098, 0, 4, 7), - MUX_GATE_MIXED(CLK_TOP_USB_TOP, usb_parents, 0x098, 8, 4, 15), - MUX_GATE_MIXED(CLK_TOP_SSUSB_XHCI, ssusb_xhci_parents, 0x098, 16, 4, 23), - MUX_GATE_MIXED(CLK_TOP_USB_TOP_2P, usb_2p_parents, 0x098, 24, 4, 31), + MUX_GATE(CLK_TOP_DISP_PWM1, disp_pwm1_parents, 0x098, 0, 4, 7), + MUX_GATE(CLK_TOP_USB_TOP, usb_parents, 0x098, 8, 4, 15), + MUX_GATE(CLK_TOP_SSUSB_XHCI, ssusb_xhci_parents, 0x098, 16, 4, 23), + MUX_GATE(CLK_TOP_USB_TOP_2P, usb_2p_parents, 0x098, 24, 4, 31), /* CLK_CFG_11 */ - MUX_GATE_MIXED(CLK_TOP_SSUSB_XHCI_2P, ssusb_xhci_2p_parents, 0x0A4, 0, 4, 7), - MUX_GATE_MIXED(CLK_TOP_USB_TOP_3P, usb_3p_parents, 0x0A4, 8, 4, 15), - MUX_GATE_MIXED(CLK_TOP_SSUSB_XHCI_3P, ssusb_xhci_3p_parents, 0x0A4, 16, 4, 23), - MUX_GATE_MIXED(CLK_TOP_I2C, i2c_parents, 0x0A4, 24, 4, 31), + MUX_GATE(CLK_TOP_SSUSB_XHCI_2P, ssusb_xhci_2p_parents, 0x0A4, 0, 4, 7), + MUX_GATE(CLK_TOP_USB_TOP_3P, usb_3p_parents, 0x0A4, 8, 4, 15), + MUX_GATE(CLK_TOP_SSUSB_XHCI_3P, ssusb_xhci_3p_parents, 0x0A4, 16, 4, 23), + MUX_GATE(CLK_TOP_I2C, i2c_parents, 0x0A4, 24, 4, 31), /* CLK_CFG_12 */ - MUX_GATE_MIXED(CLK_TOP_SENINF, seninf_parents, 0x0B0, 0, 4, 7), - MUX_GATE_MIXED(CLK_TOP_SENINF1, seninf1_parents, 0x0B0, 8, 4, 15), - MUX_GATE_MIXED(CLK_TOP_GCPU, gcpu_parents, 0x0B0, 16, 4, 23), - MUX_GATE_MIXED(CLK_TOP_VENC, venc_parents, 0x0B0, 24, 4, 31), + MUX_GATE(CLK_TOP_SENINF, seninf_parents, 0x0B0, 0, 4, 7), + MUX_GATE(CLK_TOP_SENINF1, seninf1_parents, 0x0B0, 8, 4, 15), + MUX_GATE(CLK_TOP_GCPU, gcpu_parents, 0x0B0, 16, 4, 23), + MUX_GATE(CLK_TOP_VENC, venc_parents, 0x0B0, 24, 4, 31), /* CLK_CFG_13 */ - MUX_GATE_MIXED(CLK_TOP_VDEC, vdec_parents, 0x0BC, 0, 4, 7), - MUX_GATE_MIXED(CLK_TOP_PWM, pwm_parents, 0x0BC, 8, 4, 15), - MUX_GATE_MIXED(CLK_TOP_MCUPM, mcupm_parents, 0x0BC, 16, 4, 23), - MUX_GATE_MIXED(CLK_TOP_SPMI_P_MST, spmi_p_mst_parents, 0x0BC, 24, 4, 31), + MUX_GATE(CLK_TOP_VDEC, vdec_parents, 0x0BC, 0, 4, 7), + MUX_GATE(CLK_TOP_PWM, pwm_parents, 0x0BC, 8, 4, 15), + MUX_GATE(CLK_TOP_MCUPM, mcupm_parents, 0x0BC, 16, 4, 23), + MUX_GATE(CLK_TOP_SPMI_P_MST, spmi_p_mst_parents, 0x0BC, 24, 4, 31), /* CLK_CFG_14 */ - MUX_GATE_MIXED(CLK_TOP_SPMI_M_MST, spmi_m_mst_parents, 0x0C8, 0, 4, 7), - MUX_GATE_MIXED(CLK_TOP_DVFSRC, dvfsrc_parents, 0x0C8, 8, 4, 15), - MUX_GATE_MIXED(CLK_TOP_TL, tl_parents, 0x0C8, 16, 4, 23), - MUX_GATE_MIXED(CLK_TOP_AES_MSDCFDE, aes_msdcfde_parents, 0x0C8, 24, 4, 31), + MUX_GATE(CLK_TOP_SPMI_M_MST, spmi_m_mst_parents, 0x0C8, 0, 4, 7), + MUX_GATE(CLK_TOP_DVFSRC, dvfsrc_parents, 0x0C8, 8, 4, 15), + MUX_GATE(CLK_TOP_TL, tl_parents, 0x0C8, 16, 4, 23), + MUX_GATE(CLK_TOP_AES_MSDCFDE, aes_msdcfde_parents, 0x0C8, 24, 4, 31), /* CLK_CFG_15 */ - MUX_GATE_MIXED(CLK_TOP_DSI_OCC, dsi_occ_parents, 0x0D4, 0, 4, 7), - MUX_GATE_MIXED(CLK_TOP_WPE_VPP, wpe_vpp_parents, 0x0D4, 8, 4, 15), - MUX_GATE_MIXED(CLK_TOP_HDCP, hdcp_parents, 0x0D4, 16, 4, 23), - MUX_GATE_MIXED(CLK_TOP_HDCP_24M, hdcp_24m_parents, 0x0D4, 24, 4, 31), + MUX_GATE(CLK_TOP_DSI_OCC, dsi_occ_parents, 0x0D4, 0, 4, 7), + MUX_GATE(CLK_TOP_WPE_VPP, wpe_vpp_parents, 0x0D4, 8, 4, 15), + MUX_GATE(CLK_TOP_HDCP, hdcp_parents, 0x0D4, 16, 4, 23), + MUX_GATE(CLK_TOP_HDCP_24M, hdcp_24m_parents, 0x0D4, 24, 4, 31), /* CLK_CFG_16 */ - MUX_GATE_MIXED(CLK_TOP_HDMI_APB, hdmi_apb_parents, 0x0E0, 0, 4, 7), - MUX_GATE_MIXED(CLK_TOP_SNPS_ETH_250M, snps_eth_250m_parents, 0x0E0, 8, 4, 15), - MUX_GATE_MIXED(CLK_TOP_SNPS_ETH_62P4M_PTP, snps_eth_62p4m_ptp_parents, 0x0E0, 16, 4, 23), - MUX_GATE_MIXED(CLK_TOP_SNPS_ETH_50M_RMII, snps_eth_50m_rmii_parents, 0x0E0, 24, 4, 31), + MUX_GATE(CLK_TOP_HDMI_APB, hdmi_apb_parents, 0x0E0, 0, 4, 7), + MUX_GATE(CLK_TOP_SNPS_ETH_250M, snps_eth_250m_parents, 0x0E0, 8, 4, 15), + MUX_GATE(CLK_TOP_SNPS_ETH_62P4M_PTP, snps_eth_62p4m_ptp_parents, 0x0E0, 16, 4, 23), + MUX_GATE(CLK_TOP_SNPS_ETH_50M_RMII, snps_eth_50m_rmii_parents, 0x0E0, 24, 4, 31), /* CLK_CFG_17 */ - MUX_GATE_MIXED(CLK_TOP_ADSP, adsp_parents, 0x0EC, 0, 4, 7), - MUX_GATE_MIXED(CLK_TOP_AUDIO_LOCAL_BUS, audio_local_bus_parents, 0x0EC, 8, 4, 15), - MUX_GATE_MIXED(CLK_TOP_ASM_H, asm_h_parents, 0x0EC, 16, 4, 23), - MUX_GATE_MIXED(CLK_TOP_ASM_L, asm_l_parents, 0x0EC, 24, 4, 31), + MUX_GATE(CLK_TOP_ADSP, adsp_parents, 0x0EC, 0, 4, 7), + MUX_GATE(CLK_TOP_AUDIO_LOCAL_BUS, audio_local_bus_parents, 0x0EC, 8, 4, 15), + MUX_GATE(CLK_TOP_ASM_H, asm_h_parents, 0x0EC, 16, 4, 23), + MUX_GATE(CLK_TOP_ASM_L, asm_l_parents, 0x0EC, 24, 4, 31), /* CLK_CFG_18 */ - MUX_GATE_MIXED(CLK_TOP_APLL1, apll1_parents, 0x0F8, 0, 4, 7), - MUX_GATE_MIXED(CLK_TOP_APLL2, apll2_parents, 0x0F8, 8, 4, 15), - MUX_GATE_MIXED(CLK_TOP_APLL3, apll3_parents, 0x0F8, 16, 4, 23), - MUX_GATE_MIXED(CLK_TOP_APLL4, apll4_parents, 0x0F8, 24, 4, 31), + MUX_GATE(CLK_TOP_APLL1, apll1_parents, 0x0F8, 0, 4, 7), + MUX_GATE(CLK_TOP_APLL2, apll2_parents, 0x0F8, 8, 4, 15), + MUX_GATE(CLK_TOP_APLL3, apll3_parents, 0x0F8, 16, 4, 23), + MUX_GATE(CLK_TOP_APLL4, apll4_parents, 0x0F8, 24, 4, 31), /* CLK_CFG_19 */ - MUX_GATE_MIXED(CLK_TOP_APLL5, apll5_parents, 0x0104, 0, 4, 7), - MUX_GATE_MIXED(CLK_TOP_I2SO1, i2so1_parents, 0x0104, 8, 4, 15), - MUX_GATE_MIXED(CLK_TOP_I2SO2, i2so2_parents, 0x0104, 16, 4, 23), - MUX_GATE_MIXED(CLK_TOP_I2SI1, i2si1_parents, 0x0104, 24, 4, 31), + MUX_GATE(CLK_TOP_APLL5, apll5_parents, 0x0104, 0, 4, 7), + MUX_GATE(CLK_TOP_I2SO1, i2so1_parents, 0x0104, 8, 4, 15), + MUX_GATE(CLK_TOP_I2SO2, i2so2_parents, 0x0104, 16, 4, 23), + MUX_GATE(CLK_TOP_I2SI1, i2si1_parents, 0x0104, 24, 4, 31), /* CLK_CFG_20 */ - MUX_GATE_MIXED(CLK_TOP_I2SI2, i2si2_parents, 0x0110, 0, 4, 7), - MUX_GATE_MIXED(CLK_TOP_DPTX, dptx_parents, 0x0110, 8, 4, 15), - MUX_GATE_MIXED(CLK_TOP_AUD_IEC, aud_iec_parents, 0x0110, 16, 4, 23), - MUX_GATE_MIXED(CLK_TOP_A1SYS_HP, a1sys_hp_parents, 0x0110, 24, 4, 31), + MUX_GATE(CLK_TOP_I2SI2, i2si2_parents, 0x0110, 0, 4, 7), + MUX_GATE(CLK_TOP_DPTX, dptx_parents, 0x0110, 8, 4, 15), + MUX_GATE(CLK_TOP_AUD_IEC, aud_iec_parents, 0x0110, 16, 4, 23), + MUX_GATE(CLK_TOP_A1SYS_HP, a1sys_hp_parents, 0x0110, 24, 4, 31), /* CLK_CFG_21 */ - MUX_GATE_MIXED(CLK_TOP_A2SYS, a2sys_parents, 0x011C, 0, 4, 7), - MUX_GATE_MIXED(CLK_TOP_A3SYS, a3sys_parents, 0x011C, 8, 4, 15), - MUX_GATE_MIXED(CLK_TOP_A4SYS, a4sys_parents, 0x011C, 16, 4, 23), - MUX_GATE_MIXED(CLK_TOP_ECC, ecc_parents, 0x011C, 24, 4, 31), + MUX_GATE(CLK_TOP_A2SYS, a2sys_parents, 0x011C, 0, 4, 7), + MUX_GATE(CLK_TOP_A3SYS, a3sys_parents, 0x011C, 8, 4, 15), + MUX_GATE(CLK_TOP_A4SYS, a4sys_parents, 0x011C, 16, 4, 23), + MUX_GATE(CLK_TOP_ECC, ecc_parents, 0x011C, 24, 4, 31), /* CLK_CFG_22 */ - MUX_GATE_MIXED(CLK_TOP_SPINOR, spinor_parents, 0x0128, 0, 4, 7), - MUX_GATE_MIXED(CLK_TOP_ULPOSC, ulposc_parents, 0x0128, 8, 4, 15), - MUX_GATE_MIXED(CLK_TOP_SRCK, srck_parents, 0x0128, 16, 4, 23), + MUX_GATE(CLK_TOP_SPINOR, spinor_parents, 0x0128, 0, 4, 7), + MUX_GATE(CLK_TOP_ULPOSC, ulposc_parents, 0x0128, 8, 4, 15), + MUX_GATE(CLK_TOP_SRCK, srck_parents, 0x0128, 16, 4, 23), }; static const int mt8188_id_top_offs_map[] = { diff --git a/drivers/clk/mediatek/clk-mt8189.c b/drivers/clk/mediatek/clk-mt8189.c index 60e6f53013a..6c917735914 100644 --- a/drivers/clk/mediatek/clk-mt8189.c +++ b/drivers/clk/mediatek/clk-mt8189.c @@ -1109,16 +1109,16 @@ static const struct mtk_parent ecc_parents[] = { #define MUX_CLR_SET_UPD(_id, _parents, _mux_ofs, _mux_set_ofs, _mux_clr_ofs, \ _shift, _width, _upd_ofs, _upd) \ - MUX_MIXED_CLR_SET_UPD_FLAGS(_id, _parents, _mux_ofs, _mux_set_ofs, \ - _mux_clr_ofs, _shift, _width, -1, _upd_ofs, \ - _upd, CLK_MUX_SETCLR_UPD) + MUX_CLR_SET_UPD_FLAGS(_id, _parents, _mux_ofs, _mux_set_ofs, \ + _mux_clr_ofs, _shift, _width, -1, _upd_ofs, \ + _upd, CLK_MUX_SETCLR_UPD) #define MUX_GATE_CLR_SET_UPD(_id, _parents, _mux_ofs, _mux_set_ofs, \ _mux_clr_ofs, _shift, _width, _gate, _upd_ofs, \ _upd) \ - MUX_MIXED_CLR_SET_UPD_FLAGS(_id, _parents, _mux_ofs, _mux_set_ofs, \ - _mux_clr_ofs, _shift, _width, _gate, \ - _upd_ofs, _upd, CLK_MUX_SETCLR_UPD) + MUX_CLR_SET_UPD_FLAGS(_id, _parents, _mux_ofs, _mux_set_ofs, \ + _mux_clr_ofs, _shift, _width, _gate, \ + _upd_ofs, _upd, CLK_MUX_SETCLR_UPD) const struct mtk_composite top_muxes[] = { /* CLK_CFG_0 */ diff --git a/drivers/clk/mediatek/clk-mt8195.c b/drivers/clk/mediatek/clk-mt8195.c index c709d61af94..fc7b9ff1d8d 100644 --- a/drivers/clk/mediatek/clk-mt8195.c +++ b/drivers/clk/mediatek/clk-mt8195.c @@ -961,160 +961,160 @@ static const struct mtk_parent srck_parents[] = { static const struct mtk_composite top_muxes[] = { /* CLK_CFG_0 */ - MUX_GATE_MIXED(CLK_TOP_AXI, axi_parents, 0x020, 0, 3, 7), - MUX_GATE_MIXED(CLK_TOP_SPM, spm_parents, 0x020, 8, 2, 15), - MUX_GATE_MIXED(CLK_TOP_SCP, scp_parents, 0x020, 16, 3, 23), - MUX_GATE_MIXED(CLK_TOP_BUS_AXIMEM, bus_aximem_parents, 0x020, 24, 3, 31), + MUX_GATE(CLK_TOP_AXI, axi_parents, 0x020, 0, 3, 7), + MUX_GATE(CLK_TOP_SPM, spm_parents, 0x020, 8, 2, 15), + MUX_GATE(CLK_TOP_SCP, scp_parents, 0x020, 16, 3, 23), + MUX_GATE(CLK_TOP_BUS_AXIMEM, bus_aximem_parents, 0x020, 24, 3, 31), /* CLK_CFG_1 */ - MUX_GATE_MIXED(CLK_TOP_VPP, vpp_parents, 0x02C, 0, 4, 7), - MUX_GATE_MIXED(CLK_TOP_ETHDR, ethdr_parents, 0x02C, 8, 4, 15), - MUX_GATE_MIXED(CLK_TOP_IPE, ipe_parents, 0x02C, 16, 4, 23), - MUX_GATE_MIXED(CLK_TOP_CAM, cam_parents, 0x02C, 24, 4, 31), + MUX_GATE(CLK_TOP_VPP, vpp_parents, 0x02C, 0, 4, 7), + MUX_GATE(CLK_TOP_ETHDR, ethdr_parents, 0x02C, 8, 4, 15), + MUX_GATE(CLK_TOP_IPE, ipe_parents, 0x02C, 16, 4, 23), + MUX_GATE(CLK_TOP_CAM, cam_parents, 0x02C, 24, 4, 31), /* CLK_CFG_2 */ - MUX_GATE_MIXED(CLK_TOP_CCU, ccu_parents, 0x038, 0, 4, 7), - MUX_GATE_MIXED(CLK_TOP_IMG, img_parents, 0x038, 8, 4, 15), - MUX_GATE_MIXED(CLK_TOP_CAMTM, camtm_parents, 0x038, 16, 2, 23), - MUX_GATE_MIXED(CLK_TOP_DSP, dsp_parents, 0x038, 24, 3, 31), + MUX_GATE(CLK_TOP_CCU, ccu_parents, 0x038, 0, 4, 7), + MUX_GATE(CLK_TOP_IMG, img_parents, 0x038, 8, 4, 15), + MUX_GATE(CLK_TOP_CAMTM, camtm_parents, 0x038, 16, 2, 23), + MUX_GATE(CLK_TOP_DSP, dsp_parents, 0x038, 24, 3, 31), /* CLK_CFG_3 */ - MUX_GATE_MIXED(CLK_TOP_DSP1, dsp1_parents, 0x044, 0, 3, 7), - MUX_GATE_MIXED(CLK_TOP_DSP2, dsp1_parents, 0x044, 8, 3, 15), - MUX_GATE_MIXED(CLK_TOP_DSP3, dsp1_parents, 0x044, 16, 3, 23), - MUX_GATE_MIXED(CLK_TOP_DSP4, dsp2_parents, 0x044, 24, 3, 31), + MUX_GATE(CLK_TOP_DSP1, dsp1_parents, 0x044, 0, 3, 7), + MUX_GATE(CLK_TOP_DSP2, dsp1_parents, 0x044, 8, 3, 15), + MUX_GATE(CLK_TOP_DSP3, dsp1_parents, 0x044, 16, 3, 23), + MUX_GATE(CLK_TOP_DSP4, dsp2_parents, 0x044, 24, 3, 31), /* CLK_CFG_4 */ - MUX_GATE_MIXED(CLK_TOP_DSP5, dsp2_parents, 0x050, 0, 3, 7), - MUX_GATE_MIXED(CLK_TOP_DSP6, dsp2_parents, 0x050, 8, 3, 15), - MUX_GATE_MIXED(CLK_TOP_DSP7, dsp_parents, 0x050, 16, 3, 23), - MUX_GATE_MIXED(CLK_TOP_IPU_IF, ipu_if_parents, 0x050, 24, 3, 31), + MUX_GATE(CLK_TOP_DSP5, dsp2_parents, 0x050, 0, 3, 7), + MUX_GATE(CLK_TOP_DSP6, dsp2_parents, 0x050, 8, 3, 15), + MUX_GATE(CLK_TOP_DSP7, dsp_parents, 0x050, 16, 3, 23), + MUX_GATE(CLK_TOP_IPU_IF, ipu_if_parents, 0x050, 24, 3, 31), /* CLK_CFG_5 */ - MUX_GATE_MIXED(CLK_TOP_MFG_CORE_TMP, mfg_parents, 0x05C, 0, 2, 7), - MUX_GATE_MIXED(CLK_TOP_CAMTG, camtg_parents, 0x05C, 8, 3, 15), - MUX_GATE_MIXED(CLK_TOP_CAMTG2, camtg_parents, 0x05C, 16, 3, 23), - MUX_GATE_MIXED(CLK_TOP_CAMTG3, camtg_parents, 0x05C, 24, 3, 31), + MUX_GATE(CLK_TOP_MFG_CORE_TMP, mfg_parents, 0x05C, 0, 2, 7), + MUX_GATE(CLK_TOP_CAMTG, camtg_parents, 0x05C, 8, 3, 15), + MUX_GATE(CLK_TOP_CAMTG2, camtg_parents, 0x05C, 16, 3, 23), + MUX_GATE(CLK_TOP_CAMTG3, camtg_parents, 0x05C, 24, 3, 31), /* CLK_CFG_6 */ - MUX_GATE_MIXED(CLK_TOP_CAMTG4, camtg_parents, 0x068, 0, 3, 7), - MUX_GATE_MIXED(CLK_TOP_CAMTG5, camtg_parents, 0x068, 8, 3, 15), - MUX_GATE_MIXED(CLK_TOP_UART, uart_parents, 0x068, 16, 1, 23), - MUX_GATE_MIXED(CLK_TOP_SPI, spi_parents, 0x068, 24, 3, 31), + MUX_GATE(CLK_TOP_CAMTG4, camtg_parents, 0x068, 0, 3, 7), + MUX_GATE(CLK_TOP_CAMTG5, camtg_parents, 0x068, 8, 3, 15), + MUX_GATE(CLK_TOP_UART, uart_parents, 0x068, 16, 1, 23), + MUX_GATE(CLK_TOP_SPI, spi_parents, 0x068, 24, 3, 31), /* CLK_CFG_7 */ - MUX_GATE_MIXED(CLK_TOP_SPIS, spis_parents, 0x074, 0, 3, 7), - MUX_GATE_MIXED(CLK_TOP_MSDC50_0_HCLK, msdc50_0_h_parents, 0x074, 8, 2, 15), - MUX_GATE_MIXED(CLK_TOP_MSDC50_0, msdc50_0_parents, 0x074, 16, 3, 23), - MUX_GATE_MIXED(CLK_TOP_MSDC30_1, msdc30_parents, 0x074, 24, 3, 31), + MUX_GATE(CLK_TOP_SPIS, spis_parents, 0x074, 0, 3, 7), + MUX_GATE(CLK_TOP_MSDC50_0_HCLK, msdc50_0_h_parents, 0x074, 8, 2, 15), + MUX_GATE(CLK_TOP_MSDC50_0, msdc50_0_parents, 0x074, 16, 3, 23), + MUX_GATE(CLK_TOP_MSDC30_1, msdc30_parents, 0x074, 24, 3, 31), /* CLK_CFG_8 */ - MUX_GATE_MIXED(CLK_TOP_MSDC30_2, msdc30_parents, 0x080, 0, 3, 7), - MUX_GATE_MIXED(CLK_TOP_INTDIR, intdir_parents, 0x080, 8, 2, 15), - MUX_GATE_MIXED(CLK_TOP_AUD_INTBUS, aud_intbus_parents, 0x080, 16, 2, 23), - MUX_GATE_MIXED(CLK_TOP_AUDIO_H, audio_h_parents, 0x080, 24, 2, 31), + MUX_GATE(CLK_TOP_MSDC30_2, msdc30_parents, 0x080, 0, 3, 7), + MUX_GATE(CLK_TOP_INTDIR, intdir_parents, 0x080, 8, 2, 15), + MUX_GATE(CLK_TOP_AUD_INTBUS, aud_intbus_parents, 0x080, 16, 2, 23), + MUX_GATE(CLK_TOP_AUDIO_H, audio_h_parents, 0x080, 24, 2, 31), /* CLK_CFG_9 */ - MUX_GATE_MIXED(CLK_TOP_PWRAP_ULPOSC, pwrap_ulposc_parents, 0x08C, 0, 3, 7), - MUX_GATE_MIXED(CLK_TOP_ATB, atb_parents, 0x08C, 8, 2, 15), - MUX_GATE_MIXED(CLK_TOP_PWRMCU, pwrmcu_parents, 0x08C, 16, 3, 23), - MUX_GATE_MIXED(CLK_TOP_DP, dp_parents, 0x08C, 24, 4, 31), + MUX_GATE(CLK_TOP_PWRAP_ULPOSC, pwrap_ulposc_parents, 0x08C, 0, 3, 7), + MUX_GATE(CLK_TOP_ATB, atb_parents, 0x08C, 8, 2, 15), + MUX_GATE(CLK_TOP_PWRMCU, pwrmcu_parents, 0x08C, 16, 3, 23), + MUX_GATE(CLK_TOP_DP, dp_parents, 0x08C, 24, 4, 31), /* CLK_CFG_10 */ - MUX_GATE_MIXED(CLK_TOP_EDP, dp_parents, 0x098, 0, 4, 7), - MUX_GATE_MIXED(CLK_TOP_DPI, dp_parents, 0x098, 8, 4, 15), - MUX_GATE_MIXED(CLK_TOP_DISP_PWM0, disp_pwm_parents, 0x098, 16, 3, 23), - MUX_GATE_MIXED(CLK_TOP_DISP_PWM1, disp_pwm_parents, 0x098, 24, 3, 31), + MUX_GATE(CLK_TOP_EDP, dp_parents, 0x098, 0, 4, 7), + MUX_GATE(CLK_TOP_DPI, dp_parents, 0x098, 8, 4, 15), + MUX_GATE(CLK_TOP_DISP_PWM0, disp_pwm_parents, 0x098, 16, 3, 23), + MUX_GATE(CLK_TOP_DISP_PWM1, disp_pwm_parents, 0x098, 24, 3, 31), /* CLK_CFG_11 */ - MUX_GATE_MIXED(CLK_TOP_USB_TOP, usb_parents, 0x0A4, 0, 2, 7), - MUX_GATE_MIXED(CLK_TOP_SSUSB_XHCI, usb_parents, 0x0A4, 8, 2, 15), - MUX_GATE_MIXED(CLK_TOP_USB_TOP_1P, usb_parents, 0x0A4, 16, 2, 23), - MUX_GATE_MIXED(CLK_TOP_SSUSB_XHCI_1P, usb_parents, 0x0A4, 24, 2, 31), + MUX_GATE(CLK_TOP_USB_TOP, usb_parents, 0x0A4, 0, 2, 7), + MUX_GATE(CLK_TOP_SSUSB_XHCI, usb_parents, 0x0A4, 8, 2, 15), + MUX_GATE(CLK_TOP_USB_TOP_1P, usb_parents, 0x0A4, 16, 2, 23), + MUX_GATE(CLK_TOP_SSUSB_XHCI_1P, usb_parents, 0x0A4, 24, 2, 31), /* CLK_CFG_12 */ - MUX_GATE_MIXED(CLK_TOP_USB_TOP_2P, usb_parents, 0x0B0, 0, 2, 7), - MUX_GATE_MIXED(CLK_TOP_SSUSB_XHCI_2P, usb_parents, 0x0B0, 8, 2, 15), - MUX_GATE_MIXED(CLK_TOP_USB_TOP_3P, usb_parents, 0x0B0, 16, 2, 23), - MUX_GATE_MIXED(CLK_TOP_SSUSB_XHCI_3P, usb_parents, 0x0B0, 24, 2, 31), + MUX_GATE(CLK_TOP_USB_TOP_2P, usb_parents, 0x0B0, 0, 2, 7), + MUX_GATE(CLK_TOP_SSUSB_XHCI_2P, usb_parents, 0x0B0, 8, 2, 15), + MUX_GATE(CLK_TOP_USB_TOP_3P, usb_parents, 0x0B0, 16, 2, 23), + MUX_GATE(CLK_TOP_SSUSB_XHCI_3P, usb_parents, 0x0B0, 24, 2, 31), /* CLK_CFG_13 */ - MUX_GATE_MIXED(CLK_TOP_I2C, i2c_parents, 0x0BC, 0, 2, 7), - MUX_GATE_MIXED(CLK_TOP_SENINF, seninf_parents, 0x0BC, 8, 3, 15), - MUX_GATE_MIXED(CLK_TOP_SENINF1, seninf_parents, 0x0BC, 16, 3, 23), - MUX_GATE_MIXED(CLK_TOP_SENINF2, seninf_parents, 0x0BC, 24, 3, 31), + MUX_GATE(CLK_TOP_I2C, i2c_parents, 0x0BC, 0, 2, 7), + MUX_GATE(CLK_TOP_SENINF, seninf_parents, 0x0BC, 8, 3, 15), + MUX_GATE(CLK_TOP_SENINF1, seninf_parents, 0x0BC, 16, 3, 23), + MUX_GATE(CLK_TOP_SENINF2, seninf_parents, 0x0BC, 24, 3, 31), /* CLK_CFG_14 */ - MUX_GATE_MIXED(CLK_TOP_SENINF3, seninf_parents, 0x0C8, 0, 3, 7), - MUX_GATE_MIXED(CLK_TOP_GCPU, gcpu_parents, 0x0C8, 8, 3, 15), - MUX_GATE_MIXED(CLK_TOP_DXCC, dxcc_parents, 0x0C8, 16, 2, 23), - MUX_GATE_MIXED(CLK_TOP_DPMAIF_MAIN, dpmaif_parents, 0x0C8, 24, 3, 31), + MUX_GATE(CLK_TOP_SENINF3, seninf_parents, 0x0C8, 0, 3, 7), + MUX_GATE(CLK_TOP_GCPU, gcpu_parents, 0x0C8, 8, 3, 15), + MUX_GATE(CLK_TOP_DXCC, dxcc_parents, 0x0C8, 16, 2, 23), + MUX_GATE(CLK_TOP_DPMAIF_MAIN, dpmaif_parents, 0x0C8, 24, 3, 31), /* CLK_CFG_15 */ - MUX_GATE_MIXED(CLK_TOP_AES_UFSFDE, aes_fde_parents, 0x0D4, 0, 3, 7), - MUX_GATE_MIXED(CLK_TOP_UFS, ufs_parents, 0x0D4, 8, 3, 15), - MUX_GATE_MIXED(CLK_TOP_UFS_TICK1US, ufs_tick1us_parents, 0x0D4, 16, 1, 23), - MUX_GATE_MIXED(CLK_TOP_UFS_MP_SAP_CFG, ufs_mp_sap_parents, 0x0D4, 24, 1, 31), + MUX_GATE(CLK_TOP_AES_UFSFDE, aes_fde_parents, 0x0D4, 0, 3, 7), + MUX_GATE(CLK_TOP_UFS, ufs_parents, 0x0D4, 8, 3, 15), + MUX_GATE(CLK_TOP_UFS_TICK1US, ufs_tick1us_parents, 0x0D4, 16, 1, 23), + MUX_GATE(CLK_TOP_UFS_MP_SAP_CFG, ufs_mp_sap_parents, 0x0D4, 24, 1, 31), /* CLK_CFG_16 */ - MUX_GATE_MIXED(CLK_TOP_VENC, venc_parents, 0x0E0, 0, 4, 7), - MUX_GATE_MIXED(CLK_TOP_VDEC, vdec_parents, 0x0E0, 8, 4, 15), - MUX_GATE_MIXED(CLK_TOP_PWM, pwm_parents, 0x0E0, 16, 1, 23), - MUX_GATE_MIXED(CLK_TOP_MCUPM, mcupm_parents, 0x0E0, 24, 2, 31), + MUX_GATE(CLK_TOP_VENC, venc_parents, 0x0E0, 0, 4, 7), + MUX_GATE(CLK_TOP_VDEC, vdec_parents, 0x0E0, 8, 4, 15), + MUX_GATE(CLK_TOP_PWM, pwm_parents, 0x0E0, 16, 1, 23), + MUX_GATE(CLK_TOP_MCUPM, mcupm_parents, 0x0E0, 24, 2, 31), /* CLK_CFG_17 */ - MUX_GATE_MIXED(CLK_TOP_SPMI_P_MST, spmi_parents, 0x0EC, 0, 4, 7), - MUX_GATE_MIXED(CLK_TOP_SPMI_M_MST, spmi_parents, 0x0EC, 8, 4, 15), - MUX_GATE_MIXED(CLK_TOP_DVFSRC, dvfsrc_parents, 0x0EC, 16, 2, 23), - MUX_GATE_MIXED(CLK_TOP_TL, tl_parents, 0x0EC, 24, 2, 31), + MUX_GATE(CLK_TOP_SPMI_P_MST, spmi_parents, 0x0EC, 0, 4, 7), + MUX_GATE(CLK_TOP_SPMI_M_MST, spmi_parents, 0x0EC, 8, 4, 15), + MUX_GATE(CLK_TOP_DVFSRC, dvfsrc_parents, 0x0EC, 16, 2, 23), + MUX_GATE(CLK_TOP_TL, tl_parents, 0x0EC, 24, 2, 31), /* CLK_CFG_18 */ - MUX_GATE_MIXED(CLK_TOP_TL_P1, tl_parents, 0x0F8, 0, 2, 7), - MUX_GATE_MIXED(CLK_TOP_AES_MSDCFDE, aes_fde_parents, 0x0F8, 8, 3, 15), - MUX_GATE_MIXED(CLK_TOP_DSI_OCC, dsi_occ_parents, 0x0F8, 16, 2, 23), - MUX_GATE_MIXED(CLK_TOP_WPE_VPP, wpe_vpp_parents, 0x0F8, 24, 4, 31), + MUX_GATE(CLK_TOP_TL_P1, tl_parents, 0x0F8, 0, 2, 7), + MUX_GATE(CLK_TOP_AES_MSDCFDE, aes_fde_parents, 0x0F8, 8, 3, 15), + MUX_GATE(CLK_TOP_DSI_OCC, dsi_occ_parents, 0x0F8, 16, 2, 23), + MUX_GATE(CLK_TOP_WPE_VPP, wpe_vpp_parents, 0x0F8, 24, 4, 31), /* CLK_CFG_19 */ - MUX_GATE_MIXED(CLK_TOP_HDCP, hdcp_parents, 0x0104, 0, 2, 7), - MUX_GATE_MIXED(CLK_TOP_HDCP_24M, hdcp_24m_parents, 0x0104, 8, 2, 15), - MUX_GATE_MIXED(CLK_TOP_HD20_DACR_REF_CLK, hd20_dacr_ref_parents, 0x0104, 16, 2, 23), - MUX_GATE_MIXED(CLK_TOP_HD20_HDCP_CCLK, hd20_hdcp_c_parents, 0x0104, 24, 2, 31), + MUX_GATE(CLK_TOP_HDCP, hdcp_parents, 0x0104, 0, 2, 7), + MUX_GATE(CLK_TOP_HDCP_24M, hdcp_24m_parents, 0x0104, 8, 2, 15), + MUX_GATE(CLK_TOP_HD20_DACR_REF_CLK, hd20_dacr_ref_parents, 0x0104, 16, 2, 23), + MUX_GATE(CLK_TOP_HD20_HDCP_CCLK, hd20_hdcp_c_parents, 0x0104, 24, 2, 31), /* CLK_CFG_20 */ - MUX_GATE_MIXED(CLK_TOP_HDMI_XTAL, hdmi_xtal_parents, 0x0110, 0, 1, 7), - MUX_GATE_MIXED(CLK_TOP_HDMI_APB, hdmi_apb_parents, 0x0110, 8, 2, 15), - MUX_GATE_MIXED(CLK_TOP_SNPS_ETH_250M, snps_eth_250m_parents, 0x0110, 16, 1, 23), - MUX_GATE_MIXED(CLK_TOP_SNPS_ETH_62P4M_PTP, snps_eth_62p4m_ptp_parents, 0x0110, 24, 2, 31), + MUX_GATE(CLK_TOP_HDMI_XTAL, hdmi_xtal_parents, 0x0110, 0, 1, 7), + MUX_GATE(CLK_TOP_HDMI_APB, hdmi_apb_parents, 0x0110, 8, 2, 15), + MUX_GATE(CLK_TOP_SNPS_ETH_250M, snps_eth_250m_parents, 0x0110, 16, 1, 23), + MUX_GATE(CLK_TOP_SNPS_ETH_62P4M_PTP, snps_eth_62p4m_ptp_parents, 0x0110, 24, 2, 31), /* CLK_CFG_21 */ - MUX_GATE_MIXED(CLK_TOP_SNPS_ETH_50M_RMII, snps_eth_50m_rmii_parents, 0x011C, 0, 1, 7), - MUX_GATE_MIXED(CLK_TOP_DGI_OUT, dgi_out_parents, 0x011C, 8, 3, 15), - MUX_GATE_MIXED(CLK_TOP_NNA0, nna_parents, 0x011C, 16, 4, 23), - MUX_GATE_MIXED(CLK_TOP_NNA1, nna_parents, 0x011C, 24, 4, 31), + MUX_GATE(CLK_TOP_SNPS_ETH_50M_RMII, snps_eth_50m_rmii_parents, 0x011C, 0, 1, 7), + MUX_GATE(CLK_TOP_DGI_OUT, dgi_out_parents, 0x011C, 8, 3, 15), + MUX_GATE(CLK_TOP_NNA0, nna_parents, 0x011C, 16, 4, 23), + MUX_GATE(CLK_TOP_NNA1, nna_parents, 0x011C, 24, 4, 31), /* CLK_CFG_22 */ - MUX_GATE_MIXED(CLK_TOP_ADSP, adsp_parents, 0x0128, 0, 4, 7), - MUX_GATE_MIXED(CLK_TOP_ASM_H, asm_parents, 0x0128, 8, 2, 15), - MUX_GATE_MIXED(CLK_TOP_ASM_M, asm_parents, 0x0128, 16, 2, 23), - MUX_GATE_MIXED(CLK_TOP_ASM_L, asm_parents, 0x0128, 24, 2, 31), + MUX_GATE(CLK_TOP_ADSP, adsp_parents, 0x0128, 0, 4, 7), + MUX_GATE(CLK_TOP_ASM_H, asm_parents, 0x0128, 8, 2, 15), + MUX_GATE(CLK_TOP_ASM_M, asm_parents, 0x0128, 16, 2, 23), + MUX_GATE(CLK_TOP_ASM_L, asm_parents, 0x0128, 24, 2, 31), /* CLK_CFG_23 */ - MUX_GATE_MIXED(CLK_TOP_APLL1, apll1_parents, 0x0134, 0, 1, 7), - MUX_GATE_MIXED(CLK_TOP_APLL2, apll2_parents, 0x0134, 8, 1, 15), - MUX_GATE_MIXED(CLK_TOP_APLL3, apll3_parents, 0x0134, 16, 1, 23), - MUX_GATE_MIXED(CLK_TOP_APLL4, apll4_parents, 0x0134, 24, 1, 31), + MUX_GATE(CLK_TOP_APLL1, apll1_parents, 0x0134, 0, 1, 7), + MUX_GATE(CLK_TOP_APLL2, apll2_parents, 0x0134, 8, 1, 15), + MUX_GATE(CLK_TOP_APLL3, apll3_parents, 0x0134, 16, 1, 23), + MUX_GATE(CLK_TOP_APLL4, apll4_parents, 0x0134, 24, 1, 31), /* * CLK_CFG_24 * i2so4_mck is not used in MT8195. */ - MUX_GATE_MIXED(CLK_TOP_APLL5, apll5_parents, 0x0140, 0, 1, 7), - MUX_GATE_MIXED(CLK_TOP_I2SO1_MCK, i2s_parents, 0x0140, 8, 3, 15), - MUX_GATE_MIXED(CLK_TOP_I2SO2_MCK, i2s_parents, 0x0140, 16, 3, 23), + MUX_GATE(CLK_TOP_APLL5, apll5_parents, 0x0140, 0, 1, 7), + MUX_GATE(CLK_TOP_I2SO1_MCK, i2s_parents, 0x0140, 8, 3, 15), + MUX_GATE(CLK_TOP_I2SO2_MCK, i2s_parents, 0x0140, 16, 3, 23), /* * CLK_CFG_25 * i2so5_mck and i2si4_mck are not used in MT8195. */ - MUX_GATE_MIXED(CLK_TOP_I2SI1_MCK, i2s_parents, 0x014C, 8, 3, 15), - MUX_GATE_MIXED(CLK_TOP_I2SI2_MCK, i2s_parents, 0x014C, 16, 3, 23), + MUX_GATE(CLK_TOP_I2SI1_MCK, i2s_parents, 0x014C, 8, 3, 15), + MUX_GATE(CLK_TOP_I2SI2_MCK, i2s_parents, 0x014C, 16, 3, 23), /* * CLK_CFG_26 * i2si5_mck is not used in MT8195. */ - MUX_GATE_MIXED(CLK_TOP_DPTX_MCK, i2s_parents, 0x0158, 8, 3, 15), - MUX_GATE_MIXED(CLK_TOP_AUD_IEC_CLK, i2s_parents, 0x0158, 16, 3, 23), - MUX_GATE_MIXED(CLK_TOP_A1SYS_HP, a1sys_hp_parents, 0x0158, 24, 1, 31), + MUX_GATE(CLK_TOP_DPTX_MCK, i2s_parents, 0x0158, 8, 3, 15), + MUX_GATE(CLK_TOP_AUD_IEC_CLK, i2s_parents, 0x0158, 16, 3, 23), + MUX_GATE(CLK_TOP_A1SYS_HP, a1sys_hp_parents, 0x0158, 24, 1, 31), /* CLK_CFG_27 */ - MUX_GATE_MIXED(CLK_TOP_A2SYS_HF, a2sys_parents, 0x0164, 0, 1, 7), - MUX_GATE_MIXED(CLK_TOP_A3SYS_HF, a3sys_parents, 0x0164, 8, 3, 15), - MUX_GATE_MIXED(CLK_TOP_A4SYS_HF, a3sys_parents, 0x0164, 16, 3, 23), - MUX_GATE_MIXED(CLK_TOP_SPINFI_BCLK, spinfi_b_parents, 0x0164, 24, 3, 31), + MUX_GATE(CLK_TOP_A2SYS_HF, a2sys_parents, 0x0164, 0, 1, 7), + MUX_GATE(CLK_TOP_A3SYS_HF, a3sys_parents, 0x0164, 8, 3, 15), + MUX_GATE(CLK_TOP_A4SYS_HF, a3sys_parents, 0x0164, 16, 3, 23), + MUX_GATE(CLK_TOP_SPINFI_BCLK, spinfi_b_parents, 0x0164, 24, 3, 31), /* CLK_CFG_28 */ - MUX_GATE_MIXED(CLK_TOP_NFI1X, nfi1x_parents, 0x0170, 0, 3, 7), - MUX_GATE_MIXED(CLK_TOP_ECC, ecc_parents, 0x0170, 8, 3, 15), - MUX_GATE_MIXED(CLK_TOP_AUDIO_LOCAL_BUS, audio_local_bus_parents, 0x0170, 16, 4, 23), - MUX_GATE_MIXED(CLK_TOP_SPINOR, spinor_parents, 0x0170, 24, 2, 31), + MUX_GATE(CLK_TOP_NFI1X, nfi1x_parents, 0x0170, 0, 3, 7), + MUX_GATE(CLK_TOP_ECC, ecc_parents, 0x0170, 8, 3, 15), + MUX_GATE(CLK_TOP_AUDIO_LOCAL_BUS, audio_local_bus_parents, 0x0170, 16, 4, 23), + MUX_GATE(CLK_TOP_SPINOR, spinor_parents, 0x0170, 24, 2, 31), /* CLK_CFG_29 */ - MUX_GATE_MIXED(CLK_TOP_DVIO_DGI_REF, dvio_dgi_ref_parents, 0x017C, 0, 3, 7), - MUX_GATE_MIXED(CLK_TOP_ULPOSC, ulposc_parents, 0x017C, 8, 2, 15), - MUX_GATE_MIXED(CLK_TOP_ULPOSC_CORE, ulposc_core_parents, 0x017C, 16, 2, 23), - MUX_GATE_MIXED(CLK_TOP_SRCK, srck_parents, 0x017C, 24, 1, 31), + MUX_GATE(CLK_TOP_DVIO_DGI_REF, dvio_dgi_ref_parents, 0x017C, 0, 3, 7), + MUX_GATE(CLK_TOP_ULPOSC, ulposc_parents, 0x017C, 8, 2, 15), + MUX_GATE(CLK_TOP_ULPOSC_CORE, ulposc_core_parents, 0x017C, 16, 2, 23), + MUX_GATE(CLK_TOP_SRCK, srck_parents, 0x017C, 24, 1, 31), }; static const struct mtk_gate_regs top0_cg_regs = { diff --git a/drivers/clk/mediatek/clk-mt8365.c b/drivers/clk/mediatek/clk-mt8365.c index 41dd2479c5a..c6803090f35 100644 --- a/drivers/clk/mediatek/clk-mt8365.c +++ b/drivers/clk/mediatek/clk-mt8365.c @@ -586,59 +586,59 @@ static const struct mtk_parent apu_parents[] = { static const struct mtk_composite top_muxes[] = { /* CLK_CFG_0 */ - MUX_GATE_MIXED(CLK_TOP_AXI_SEL, axi_parents, 0x040, 0, 2, 7), - MUX_GATE_MIXED(CLK_TOP_MEM_SEL, mem_parents, 0x040, 8, 2, 15), - MUX_GATE_MIXED(CLK_TOP_MM_SEL, mm_parents, 0x040, 16, 3, 23), - MUX_GATE_MIXED(CLK_TOP_SCP_SEL, scp_parents, 0x040, 24, 3, 31), + MUX_GATE(CLK_TOP_AXI_SEL, axi_parents, 0x040, 0, 2, 7), + MUX_GATE(CLK_TOP_MEM_SEL, mem_parents, 0x040, 8, 2, 15), + MUX_GATE(CLK_TOP_MM_SEL, mm_parents, 0x040, 16, 3, 23), + MUX_GATE(CLK_TOP_SCP_SEL, scp_parents, 0x040, 24, 3, 31), /* CLK_CFG_1 */ - MUX_GATE_MIXED(CLK_TOP_MFG_SEL, mfg_parents, 0x050, 0, 2, 7), - MUX_GATE_MIXED(CLK_TOP_ATB_SEL, atb_parents, 0x050, 8, 2, 15), - MUX_GATE_MIXED(CLK_TOP_CAMTG_SEL, camtg_parents, 0x050, 16, 3, 23), - MUX_GATE_MIXED(CLK_TOP_CAMTG1_SEL, camtg_parents, 0x050, 24, 3, 31), + MUX_GATE(CLK_TOP_MFG_SEL, mfg_parents, 0x050, 0, 2, 7), + MUX_GATE(CLK_TOP_ATB_SEL, atb_parents, 0x050, 8, 2, 15), + MUX_GATE(CLK_TOP_CAMTG_SEL, camtg_parents, 0x050, 16, 3, 23), + MUX_GATE(CLK_TOP_CAMTG1_SEL, camtg_parents, 0x050, 24, 3, 31), /* CLK_CFG_2 */ - MUX_GATE_MIXED(CLK_TOP_UART_SEL, uart_parents, 0x060, 0, 1, 7), - MUX_GATE_MIXED(CLK_TOP_SPI_SEL, spi_parents, 0x060, 8, 2, 15), - MUX_GATE_MIXED(CLK_TOP_MSDC50_0_HC_SEL, msdc50_0_hc_parents, 0x060, 16, 2, 23), - MUX_GATE_MIXED(CLK_TOP_MSDC2_2_HC_SEL, msdc50_0_hc_parents, 0x060, 24, 2, 31), + MUX_GATE(CLK_TOP_UART_SEL, uart_parents, 0x060, 0, 1, 7), + MUX_GATE(CLK_TOP_SPI_SEL, spi_parents, 0x060, 8, 2, 15), + MUX_GATE(CLK_TOP_MSDC50_0_HC_SEL, msdc50_0_hc_parents, 0x060, 16, 2, 23), + MUX_GATE(CLK_TOP_MSDC2_2_HC_SEL, msdc50_0_hc_parents, 0x060, 24, 2, 31), /* CLK_CFG_3 */ - MUX_GATE_MIXED(CLK_TOP_MSDC50_0_SEL, msdc50_0_parents, 0x070, 0, 3, 7), - MUX_GATE_MIXED(CLK_TOP_MSDC50_2_SEL, msdc50_2_parents, 0x070, 8, 3, 15), - MUX_GATE_MIXED(CLK_TOP_MSDC30_1_SEL, msdc30_1_parents, 0x070, 16, 3, 23), - MUX_GATE_MIXED(CLK_TOP_AUDIO_SEL, audio_parents, 0x070, 24, 2, 31), + MUX_GATE(CLK_TOP_MSDC50_0_SEL, msdc50_0_parents, 0x070, 0, 3, 7), + MUX_GATE(CLK_TOP_MSDC50_2_SEL, msdc50_2_parents, 0x070, 8, 3, 15), + MUX_GATE(CLK_TOP_MSDC30_1_SEL, msdc30_1_parents, 0x070, 16, 3, 23), + MUX_GATE(CLK_TOP_AUDIO_SEL, audio_parents, 0x070, 24, 2, 31), /* CLK_CFG_4 */ - MUX_GATE_MIXED(CLK_TOP_AUD_INTBUS_SEL, aud_intbus_parents, 0x080, 0, 2, 7), - MUX_GATE_MIXED(CLK_TOP_AUD_1_SEL, aud_1_parents, 0x080, 8, 1, 15), - MUX_GATE_MIXED(CLK_TOP_AUD_2_SEL, aud_2_parents, 0x080, 16, 1, 23), - MUX_GATE_MIXED(CLK_TOP_AUD_ENGEN1_SEL, aud_engen1_parents, 0x080, 24, 2, 31), + MUX_GATE(CLK_TOP_AUD_INTBUS_SEL, aud_intbus_parents, 0x080, 0, 2, 7), + MUX_GATE(CLK_TOP_AUD_1_SEL, aud_1_parents, 0x080, 8, 1, 15), + MUX_GATE(CLK_TOP_AUD_2_SEL, aud_2_parents, 0x080, 16, 1, 23), + MUX_GATE(CLK_TOP_AUD_ENGEN1_SEL, aud_engen1_parents, 0x080, 24, 2, 31), /* CLK_CFG_5 */ - MUX_GATE_MIXED(CLK_TOP_AUD_ENGEN2_SEL, aud_engen2_parents, 0x090, 0, 2, 7), - MUX_GATE_MIXED(CLK_TOP_AUD_SPDIF_SEL, aud_spdif_parents, 0x090, 8, 1, 15), - MUX_GATE_MIXED(CLK_TOP_DISP_PWM_SEL, disp_pwm_parents, 0x090, 16, 2, 23), + MUX_GATE(CLK_TOP_AUD_ENGEN2_SEL, aud_engen2_parents, 0x090, 0, 2, 7), + MUX_GATE(CLK_TOP_AUD_SPDIF_SEL, aud_spdif_parents, 0x090, 8, 1, 15), + MUX_GATE(CLK_TOP_DISP_PWM_SEL, disp_pwm_parents, 0x090, 16, 2, 23), /* CLK_CFG_6 */ - MUX_GATE_MIXED(CLK_TOP_DXCC_SEL, dxcc_parents, 0x0a0, 0, 2, 7), - MUX_GATE_MIXED(CLK_TOP_SSUSB_SYS_SEL, ssusb_sys_parents, 0x0a0, 8, 2, 15), - MUX_GATE_MIXED(CLK_TOP_SSUSB_XHCI_SEL, ssusb_sys_parents, 0x0a0, 16, 2, 23), - MUX_GATE_MIXED(CLK_TOP_SPM_SEL, spm_parents, 0x0a0, 24, 1, 31), + MUX_GATE(CLK_TOP_DXCC_SEL, dxcc_parents, 0x0a0, 0, 2, 7), + MUX_GATE(CLK_TOP_SSUSB_SYS_SEL, ssusb_sys_parents, 0x0a0, 8, 2, 15), + MUX_GATE(CLK_TOP_SSUSB_XHCI_SEL, ssusb_sys_parents, 0x0a0, 16, 2, 23), + MUX_GATE(CLK_TOP_SPM_SEL, spm_parents, 0x0a0, 24, 1, 31), /* CLK_CFG_7 */ - MUX_GATE_MIXED(CLK_TOP_I2C_SEL, i2c_parents, 0x0b0, 0, 3, 7), - MUX_GATE_MIXED(CLK_TOP_PWM_SEL, pwm_parents, 0x0b0, 8, 2, 15), - MUX_GATE_MIXED(CLK_TOP_SENIF_SEL, senif_parents, 0x0b0, 16, 2, 23), - MUX_GATE_MIXED(CLK_TOP_AES_FDE_SEL, aes_fde_parents, 0x0b0, 24, 3, 31), + MUX_GATE(CLK_TOP_I2C_SEL, i2c_parents, 0x0b0, 0, 3, 7), + MUX_GATE(CLK_TOP_PWM_SEL, pwm_parents, 0x0b0, 8, 2, 15), + MUX_GATE(CLK_TOP_SENIF_SEL, senif_parents, 0x0b0, 16, 2, 23), + MUX_GATE(CLK_TOP_AES_FDE_SEL, aes_fde_parents, 0x0b0, 24, 3, 31), /* CLK_CFG_8 */ - MUX_GATE_MIXED(CLK_TOP_CAMTM_SEL, senif_parents, 0x0c0, 0, 2, 7), - MUX_GATE_MIXED(CLK_TOP_DPI0_SEL, dpi0_parents, 0x0c0, 8, 3, 15), - MUX_GATE_MIXED(CLK_TOP_DPI1_SEL, dpi0_parents, 0x0c0, 16, 3, 23), - MUX_GATE_MIXED(CLK_TOP_DSP_SEL, dsp_parents, 0x0c0, 24, 3, 31), + MUX_GATE(CLK_TOP_CAMTM_SEL, senif_parents, 0x0c0, 0, 2, 7), + MUX_GATE(CLK_TOP_DPI0_SEL, dpi0_parents, 0x0c0, 8, 3, 15), + MUX_GATE(CLK_TOP_DPI1_SEL, dpi0_parents, 0x0c0, 16, 3, 23), + MUX_GATE(CLK_TOP_DSP_SEL, dsp_parents, 0x0c0, 24, 3, 31), /* CLK_CFG_9 */ - MUX_GATE_MIXED(CLK_TOP_NFI2X_SEL, nfi2x_parents, 0x0d0, 0, 3, 7), - MUX_GATE_MIXED(CLK_TOP_NFIECC_SEL, nfiecc_parents, 0x0d0, 8, 3, 15), - MUX_GATE_MIXED(CLK_TOP_ECC_SEL, ecc_parents, 0x0d0, 16, 3, 23), - MUX_GATE_MIXED(CLK_TOP_ETH_SEL, eth_parents, 0x0d0, 24, 3, 31), + MUX_GATE(CLK_TOP_NFI2X_SEL, nfi2x_parents, 0x0d0, 0, 3, 7), + MUX_GATE(CLK_TOP_NFIECC_SEL, nfiecc_parents, 0x0d0, 8, 3, 15), + MUX_GATE(CLK_TOP_ECC_SEL, ecc_parents, 0x0d0, 16, 3, 23), + MUX_GATE(CLK_TOP_ETH_SEL, eth_parents, 0x0d0, 24, 3, 31), /* CLK_CFG_10 */ - MUX_GATE_MIXED(CLK_TOP_GCPU_SEL, gcpu_parents, 0x0e0, 0, 3, 7), - MUX_GATE_MIXED(CLK_TOP_GCPU_CPM_SEL, gcpu_cpm_parents, 0x0e0, 8, 2, 15), - MUX_GATE_MIXED(CLK_TOP_APU_SEL, apu_parents, 0x0e0, 16, 3, 23), - MUX_GATE_MIXED(CLK_TOP_APU_IF_SEL, apu_parents, 0x0e0, 24, 3, 31), + MUX_GATE(CLK_TOP_GCPU_SEL, gcpu_parents, 0x0e0, 0, 3, 7), + MUX_GATE(CLK_TOP_GCPU_CPM_SEL, gcpu_cpm_parents, 0x0e0, 8, 2, 15), + MUX_GATE(CLK_TOP_APU_SEL, apu_parents, 0x0e0, 16, 3, 23), + MUX_GATE(CLK_TOP_APU_IF_SEL, apu_parents, 0x0e0, 24, 3, 31), }; /* topckgen cg */ diff --git a/drivers/clk/mediatek/clk-mt8512.c b/drivers/clk/mediatek/clk-mt8512.c index 0ea600b577a..de0d3eae7ee 100644 --- a/drivers/clk/mediatek/clk-mt8512.c +++ b/drivers/clk/mediatek/clk-mt8512.c @@ -450,150 +450,150 @@ static const struct mtk_parent occ_182m_parents[] = { static const struct mtk_composite top_muxes[] = { /* CLK_CFG_0 */ - MUX_MIXED_CLR_SET_UPD_FLAGS(CLK_TOP_AXI_SEL, axi_parents, + MUX_CLR_SET_UPD_FLAGS(CLK_TOP_AXI_SEL, axi_parents, 0x040, 0x044, 0x048, 0, 3, 7, 0x4, 0, CLK_MUX_SETCLR_UPD), - MUX_MIXED_CLR_SET_UPD_FLAGS(CLK_TOP_MEM_SEL, mem_parents, + MUX_CLR_SET_UPD_FLAGS(CLK_TOP_MEM_SEL, mem_parents, 0x040, 0x044, 0x048, 8, 2, 15, 0x4, 1, CLK_MUX_SETCLR_UPD), - MUX_MIXED_CLR_SET_UPD_FLAGS(CLK_TOP_UART_SEL, uart_parents, + MUX_CLR_SET_UPD_FLAGS(CLK_TOP_UART_SEL, uart_parents, 0x040, 0x044, 0x048, 16, 1, 23, 0x4, 2, CLK_MUX_SETCLR_UPD), - MUX_MIXED_CLR_SET_UPD_FLAGS(CLK_TOP_SPI_SEL, spi_parents, + MUX_CLR_SET_UPD_FLAGS(CLK_TOP_SPI_SEL, spi_parents, 0x040, 0x044, 0x048, 24, 3, 31, 0x4, 3, CLK_MUX_SETCLR_UPD), /* CLK_CFG_1 */ - MUX_MIXED_CLR_SET_UPD_FLAGS(CLK_TOP_SPIS_SEL, spis_parents, + MUX_CLR_SET_UPD_FLAGS(CLK_TOP_SPIS_SEL, spis_parents, 0x050, 0x054, 0x058, 0, 3, 7, 0x4, 4, CLK_MUX_SETCLR_UPD), - MUX_MIXED_CLR_SET_UPD_FLAGS(CLK_TOP_MSDC50_0_HC_SEL, msdc50_0_hc_parents, + MUX_CLR_SET_UPD_FLAGS(CLK_TOP_MSDC50_0_HC_SEL, msdc50_0_hc_parents, 0x050, 0x054, 0x058, 8, 2, 15, 0x4, 5, CLK_MUX_SETCLR_UPD), - MUX_MIXED_CLR_SET_UPD_FLAGS(CLK_TOP_MSDC2_2_HC_SEL, msdc50_0_hc_parents, + MUX_CLR_SET_UPD_FLAGS(CLK_TOP_MSDC2_2_HC_SEL, msdc50_0_hc_parents, 0x050, 0x054, 0x058, 16, 2, 23, 0x4, 6, CLK_MUX_SETCLR_UPD), - MUX_MIXED_CLR_SET_UPD_FLAGS(CLK_TOP_MSDC50_0_SEL, msdc50_0_parents, + MUX_CLR_SET_UPD_FLAGS(CLK_TOP_MSDC50_0_SEL, msdc50_0_parents, 0x050, 0x054, 0x058, 24, 3, 31, 0x4, 7, CLK_MUX_SETCLR_UPD), /* CLK_CFG_2 */ - MUX_MIXED_CLR_SET_UPD_FLAGS(CLK_TOP_MSDC50_2_SEL, msdc50_2_parents, + MUX_CLR_SET_UPD_FLAGS(CLK_TOP_MSDC50_2_SEL, msdc50_2_parents, 0x060, 0x064, 0x068, 0, 3, 7, 0x4, 8, CLK_MUX_SETCLR_UPD), - MUX_MIXED_CLR_SET_UPD_FLAGS(CLK_TOP_MSDC30_1_SEL, msdc50_0_parents, + MUX_CLR_SET_UPD_FLAGS(CLK_TOP_MSDC30_1_SEL, msdc50_0_parents, 0x060, 0x064, 0x068, 8, 3, 15, 0x4, 9, CLK_MUX_SETCLR_UPD), - MUX_MIXED_CLR_SET_UPD_FLAGS(CLK_TOP_AUDIO_SEL, audio_parents, + MUX_CLR_SET_UPD_FLAGS(CLK_TOP_AUDIO_SEL, audio_parents, 0x060, 0x064, 0x068, 16, 2, 23, 0x4, 10, CLK_MUX_SETCLR_UPD), - MUX_MIXED_CLR_SET_UPD_FLAGS(CLK_TOP_AUD_INTBUS_SEL, aud_intbus_parents, + MUX_CLR_SET_UPD_FLAGS(CLK_TOP_AUD_INTBUS_SEL, aud_intbus_parents, 0x060, 0x064, 0x068, 24, 3, 31, 0x4, 11, CLK_MUX_SETCLR_UPD), /* CLK_CFG_3 */ - MUX_MIXED_CLR_SET_UPD_FLAGS(CLK_TOP_HAPLL1_SEL, hapll1_parents, + MUX_CLR_SET_UPD_FLAGS(CLK_TOP_HAPLL1_SEL, hapll1_parents, 0x070, 0x074, 0x078, 0, 3, 7, 0x4, 12, CLK_MUX_SETCLR_UPD), - MUX_MIXED_CLR_SET_UPD_FLAGS(CLK_TOP_HAPLL2_SEL, hapll2_parents, + MUX_CLR_SET_UPD_FLAGS(CLK_TOP_HAPLL2_SEL, hapll2_parents, 0x070, 0x074, 0x078, 8, 3, 15, 0x4, 13, CLK_MUX_SETCLR_UPD), - MUX_MIXED_CLR_SET_UPD_FLAGS(CLK_TOP_A2SYS_SEL, hapll1_parents, + MUX_CLR_SET_UPD_FLAGS(CLK_TOP_A2SYS_SEL, hapll1_parents, 0x070, 0x074, 0x078, 16, 3, 23, 0x4, 14, CLK_MUX_SETCLR_UPD), - MUX_MIXED_CLR_SET_UPD_FLAGS(CLK_TOP_A1SYS_SEL, hapll2_parents, + MUX_CLR_SET_UPD_FLAGS(CLK_TOP_A1SYS_SEL, hapll2_parents, 0x070, 0x074, 0x078, 24, 3, 31, 0x4, 15, CLK_MUX_SETCLR_UPD), /* CLK_CFG_4 */ - MUX_MIXED_CLR_SET_UPD_FLAGS(CLK_TOP_ASM_L_SEL, asm_l_parents, + MUX_CLR_SET_UPD_FLAGS(CLK_TOP_ASM_L_SEL, asm_l_parents, 0x080, 0x084, 0x088, 0, 2, 7, 0x4, 16, CLK_MUX_SETCLR_UPD), - MUX_MIXED_CLR_SET_UPD_FLAGS(CLK_TOP_ASM_M_SEL, asm_l_parents, + MUX_CLR_SET_UPD_FLAGS(CLK_TOP_ASM_M_SEL, asm_l_parents, 0x080, 0x084, 0x088, 8, 2, 15, 0x4, 17, CLK_MUX_SETCLR_UPD), - MUX_MIXED_CLR_SET_UPD_FLAGS(CLK_TOP_ASM_H_SEL, asm_l_parents, + MUX_CLR_SET_UPD_FLAGS(CLK_TOP_ASM_H_SEL, asm_l_parents, 0x080, 0x084, 0x088, 16, 2, 23, 0x4, 18, CLK_MUX_SETCLR_UPD), - MUX_MIXED_CLR_SET_UPD_FLAGS(CLK_TOP_AUD_SPDIF_SEL, aud_spdif_parents, + MUX_CLR_SET_UPD_FLAGS(CLK_TOP_AUD_SPDIF_SEL, aud_spdif_parents, 0x080, 0x084, 0x088, 24, 2, 31, 0x4, 19, CLK_MUX_SETCLR_UPD), /* CLK_CFG_5 */ - MUX_MIXED_CLR_SET_UPD_FLAGS(CLK_TOP_AUD_1_SEL, aud_1_parents, + MUX_CLR_SET_UPD_FLAGS(CLK_TOP_AUD_1_SEL, aud_1_parents, 0x090, 0x094, 0x098, 0, 1, 7, 0x4, 20, CLK_MUX_SETCLR_UPD), - MUX_MIXED_CLR_SET_UPD_FLAGS(CLK_TOP_AUD_2_SEL, aud_2_parents, + MUX_CLR_SET_UPD_FLAGS(CLK_TOP_AUD_2_SEL, aud_2_parents, 0x090, 0x094, 0x098, 8, 1, 15, 0x4, 21, CLK_MUX_SETCLR_UPD), - MUX_MIXED_CLR_SET_UPD_FLAGS(CLK_TOP_SSUSB_SYS_SEL, ssusb_sys_parents, + MUX_CLR_SET_UPD_FLAGS(CLK_TOP_SSUSB_SYS_SEL, ssusb_sys_parents, 0x090, 0x094, 0x098, 16, 2, 23, 0x4, 22, CLK_MUX_SETCLR_UPD), - MUX_MIXED_CLR_SET_UPD_FLAGS(CLK_TOP_SSUSB_XHCI_SEL, ssusb_sys_parents, + MUX_CLR_SET_UPD_FLAGS(CLK_TOP_SSUSB_XHCI_SEL, ssusb_sys_parents, 0x090, 0x094, 0x098, 24, 2, 31, 0x4, 23, CLK_MUX_SETCLR_UPD), /* CLK_CFG_6 */ - MUX_MIXED_CLR_SET_UPD_FLAGS(CLK_TOP_SPM_SEL, spm_parents, + MUX_CLR_SET_UPD_FLAGS(CLK_TOP_SPM_SEL, spm_parents, 0x0a0, 0x0a4, 0x0a8, 0, 1, 7, 0x4, 24, CLK_MUX_SETCLR_UPD), - MUX_MIXED_CLR_SET_UPD_FLAGS(CLK_TOP_I2C_SEL, i2c_parents, + MUX_CLR_SET_UPD_FLAGS(CLK_TOP_I2C_SEL, i2c_parents, 0x0a0, 0x0a4, 0x0a8, 8, 3, 15, 0x4, 25, CLK_MUX_SETCLR_UPD), - MUX_MIXED_CLR_SET_UPD_FLAGS(CLK_TOP_PWM_SEL, pwm_parents, + MUX_CLR_SET_UPD_FLAGS(CLK_TOP_PWM_SEL, pwm_parents, 0x0a0, 0x0a4, 0x0a8, 16, 3, 23, 0x4, 26, CLK_MUX_SETCLR_UPD), - MUX_MIXED_CLR_SET_UPD_FLAGS(CLK_TOP_DSP_SEL, dsp_parents, + MUX_CLR_SET_UPD_FLAGS(CLK_TOP_DSP_SEL, dsp_parents, 0x0a0, 0x0a4, 0x0a8, 24, 3, 31, 0x4, 27, CLK_MUX_SETCLR_UPD), /* CLK_CFG_7 */ - MUX_MIXED_CLR_SET_UPD_FLAGS(CLK_TOP_NFI2X_SEL, nfi2x_parents, + MUX_CLR_SET_UPD_FLAGS(CLK_TOP_NFI2X_SEL, nfi2x_parents, 0x0b0, 0x0b4, 0x0b8, 0, 3, 7, 0x4, 28, CLK_MUX_SETCLR_UPD), - MUX_MIXED_CLR_SET_UPD_FLAGS(CLK_TOP_SPINFI_SEL, spinfi_parents, + MUX_CLR_SET_UPD_FLAGS(CLK_TOP_SPINFI_SEL, spinfi_parents, 0x0b0, 0x0b4, 0x0b8, 8, 3, 15, 0x4, 29, CLK_MUX_SETCLR_UPD), - MUX_MIXED_CLR_SET_UPD_FLAGS(CLK_TOP_ECC_SEL, ecc_parents, + MUX_CLR_SET_UPD_FLAGS(CLK_TOP_ECC_SEL, ecc_parents, 0x0b0, 0x0b4, 0x0b8, 16, 2, 23, 0x4, 30, CLK_MUX_SETCLR_UPD), - MUX_MIXED_CLR_SET_UPD_FLAGS(CLK_TOP_GCPU_SEL, gcpu_parents, + MUX_CLR_SET_UPD_FLAGS(CLK_TOP_GCPU_SEL, gcpu_parents, 0x0b0, 0x0b4, 0x0b8, 24, 3, 31, 0x4, 31, CLK_MUX_SETCLR_UPD), /* CLK_CFG_8 */ - MUX_MIXED_CLR_SET_UPD_FLAGS(CLK_TOP_GCPU_CPM_SEL, gcpu_cpm_parents, + MUX_CLR_SET_UPD_FLAGS(CLK_TOP_GCPU_CPM_SEL, gcpu_cpm_parents, 0x0c0, 0x0c4, 0x0c8, 0, 2, 7, 0x8, 0, CLK_MUX_SETCLR_UPD), - MUX_MIXED_CLR_SET_UPD_FLAGS(CLK_TOP_MBIST_DIAG_SEL, mbist_diag_parents, + MUX_CLR_SET_UPD_FLAGS(CLK_TOP_MBIST_DIAG_SEL, mbist_diag_parents, 0x0c0, 0x0c4, 0x0c8, 8, 1, 15, 0x8, 1, CLK_MUX_SETCLR_UPD), - MUX_MIXED_CLR_SET_UPD_FLAGS(CLK_TOP_IP0_NNA_SEL, ip0_nna_parents, + MUX_CLR_SET_UPD_FLAGS(CLK_TOP_IP0_NNA_SEL, ip0_nna_parents, 0x0c0, 0x0c4, 0x0c8, 16, 3, 23, 0x8, 2, CLK_MUX_SETCLR_UPD), - MUX_MIXED_CLR_SET_UPD_FLAGS(CLK_TOP_IP1_NNA_SEL, ip0_nna_parents, + MUX_CLR_SET_UPD_FLAGS(CLK_TOP_IP1_NNA_SEL, ip0_nna_parents, 0x0c0, 0x0c4, 0x0c8, 24, 3, 31, 0x8, 3, CLK_MUX_SETCLR_UPD), /* CLK_CFG_9 */ - MUX_MIXED_CLR_SET_UPD_FLAGS(CLK_TOP_IP2_WFST_SEL, ip2_wfst_parents, + MUX_CLR_SET_UPD_FLAGS(CLK_TOP_IP2_WFST_SEL, ip2_wfst_parents, 0x0d0, 0x0d4, 0x0d8, 0, 3, 7, 0x8, 4, CLK_MUX_SETCLR_UPD), - MUX_MIXED_CLR_SET_UPD_FLAGS(CLK_TOP_SFLASH_SEL, sflash_parents, + MUX_CLR_SET_UPD_FLAGS(CLK_TOP_SFLASH_SEL, sflash_parents, 0x0d0, 0x0d4, 0x0d8, 8, 3, 15, 0x8, 5, CLK_MUX_SETCLR_UPD), - MUX_MIXED_CLR_SET_UPD_FLAGS(CLK_TOP_SRAM_SEL, sram_parents, + MUX_CLR_SET_UPD_FLAGS(CLK_TOP_SRAM_SEL, sram_parents, 0x0d0, 0x0d4, 0x0d8, 16, 3, 23, 0x8, 6, CLK_MUX_SETCLR_UPD), - MUX_MIXED_CLR_SET_UPD_FLAGS(CLK_TOP_MM_SEL, mm_parents, + MUX_CLR_SET_UPD_FLAGS(CLK_TOP_MM_SEL, mm_parents, 0x0d0, 0x0d4, 0x0d8, 24, 3, 31, 0x8, 7, CLK_MUX_SETCLR_UPD), /* CLK_CFG_10 */ - MUX_MIXED_CLR_SET_UPD_FLAGS(CLK_TOP_DPI0_SEL, dpi0_parents, + MUX_CLR_SET_UPD_FLAGS(CLK_TOP_DPI0_SEL, dpi0_parents, 0x0e0, 0x0e4, 0x0e8, 0, 3, 7, 0x8, 8, CLK_MUX_SETCLR_UPD), - MUX_MIXED_CLR_SET_UPD_FLAGS(CLK_TOP_DBG_ATCLK_SEL, dbg_atclk_parents, + MUX_CLR_SET_UPD_FLAGS(CLK_TOP_DBG_ATCLK_SEL, dbg_atclk_parents, 0x0e0, 0x0e4, 0x0e8, 8, 2, 15, 0x8, 9, CLK_MUX_SETCLR_UPD), - MUX_MIXED_CLR_SET_UPD_FLAGS(CLK_TOP_OCC_104M_SEL, occ_104m_parents, + MUX_CLR_SET_UPD_FLAGS(CLK_TOP_OCC_104M_SEL, occ_104m_parents, 0x0e0, 0x0e4, 0x0e8, 16, 1, 23, 0x8, 10, CLK_MUX_SETCLR_UPD), - MUX_MIXED_CLR_SET_UPD_FLAGS(CLK_TOP_OCC_68M_SEL, occ_68m_parents, + MUX_CLR_SET_UPD_FLAGS(CLK_TOP_OCC_68M_SEL, occ_68m_parents, 0x0e0, 0x0e4, 0x0e8, 24, 1, 31, 0x8, 11, CLK_MUX_SETCLR_UPD), /* CLK_CFG_11 */ - MUX_MIXED_CLR_SET_UPD_FLAGS(CLK_TOP_OCC_182M_SEL, occ_182m_parents, + MUX_CLR_SET_UPD_FLAGS(CLK_TOP_OCC_182M_SEL, occ_182m_parents, 0x0ec, 0x0f0, 0x0f4, 0, 2, 7, 0x8, 12, CLK_MUX_SETCLR_UPD), }; diff --git a/drivers/clk/mediatek/clk-mt8516.c b/drivers/clk/mediatek/clk-mt8516.c index bf62a4aa3a4..6b30ea9ce4a 100644 --- a/drivers/clk/mediatek/clk-mt8516.c +++ b/drivers/clk/mediatek/clk-mt8516.c @@ -495,53 +495,53 @@ static const struct mtk_parent nfiecc_parents[] = { static const struct mtk_composite top_muxes[] = { /* CLK_MUX_SEL0 */ - MUX_MIXED(CLK_TOP_UART0_SEL, uart0_parents, 0x000, 0, 1), - MUX_MIXED(CLK_TOP_GFMUX_EMI1X_SEL, gfmux_emi1x_parents, 0x000, 1, 1), - MUX_MIXED(CLK_TOP_EMI_DDRPHY_SEL, emi_ddrphy_parents, 0x000, 2, 1), - MUX_MIXED(CLK_TOP_AHB_INFRA_SEL, ahb_infra_parents, 0x000, 4, 4), - MUX_MIXED(CLK_TOP_CSW_MUX_MFG_SEL, csw_mux_mfg_parents, 0x000, 8, 3), - MUX_MIXED(CLK_TOP_MSDC0_SEL, msdc0_parents, 0x000, 11, 3), - MUX_MIXED(CLK_TOP_PWM_MM_SEL, pwm_mm_parents, 0x000, 18, 1), - MUX_MIXED(CLK_TOP_UART1_SEL, uart1_parents, 0x000, 19, 1), - MUX_MIXED(CLK_TOP_MSDC1_SEL, msdc1_parents, 0x000, 20, 3), - MUX_MIXED(CLK_TOP_SPM_52M_SEL, spm_52m_parents, 0x000, 23, 1), - MUX_MIXED(CLK_TOP_PMICSPI_SEL, pmicspi_parents, 0x000, 24, 2), - MUX_MIXED(CLK_TOP_QAXI_AUD26M_SEL, qaxi_aud26m_parents, 0x000, 26, 1), - MUX_MIXED(CLK_TOP_AUD_INTBUS_SEL, aud_intbus_parents, 0x000, 27, 3), + MUX(CLK_TOP_UART0_SEL, uart0_parents, 0x000, 0, 1), + MUX(CLK_TOP_GFMUX_EMI1X_SEL, gfmux_emi1x_parents, 0x000, 1, 1), + MUX(CLK_TOP_EMI_DDRPHY_SEL, emi_ddrphy_parents, 0x000, 2, 1), + MUX(CLK_TOP_AHB_INFRA_SEL, ahb_infra_parents, 0x000, 4, 4), + MUX(CLK_TOP_CSW_MUX_MFG_SEL, csw_mux_mfg_parents, 0x000, 8, 3), + MUX(CLK_TOP_MSDC0_SEL, msdc0_parents, 0x000, 11, 3), + MUX(CLK_TOP_PWM_MM_SEL, pwm_mm_parents, 0x000, 18, 1), + MUX(CLK_TOP_UART1_SEL, uart1_parents, 0x000, 19, 1), + MUX(CLK_TOP_MSDC1_SEL, msdc1_parents, 0x000, 20, 3), + MUX(CLK_TOP_SPM_52M_SEL, spm_52m_parents, 0x000, 23, 1), + MUX(CLK_TOP_PMICSPI_SEL, pmicspi_parents, 0x000, 24, 2), + MUX(CLK_TOP_QAXI_AUD26M_SEL, qaxi_aud26m_parents, 0x000, 26, 1), + MUX(CLK_TOP_AUD_INTBUS_SEL, aud_intbus_parents, 0x000, 27, 3), /* CLK_MUX_SEL1 */ - MUX_MIXED(CLK_TOP_NFI2X_PAD_SEL, nfi2x_pad_parents, 0x004, 0, 7), - MUX_MIXED(CLK_TOP_NFI1X_PAD_SEL, nfi1x_pad_parents, 0x004, 7, 1), - MUX_MIXED(CLK_TOP_MFG_MM_SEL, mfg_mm_parents, 0x004, 8, 6), - MUX_MIXED(CLK_TOP_DDRPHYCFG_SEL, ddrphycfg_parents, 0x004, 15, 1), - MUX_MIXED(CLK_TOP_USB_78M_SEL, usb_78m_parents, 0x004, 20, 3), + MUX(CLK_TOP_NFI2X_PAD_SEL, nfi2x_pad_parents, 0x004, 0, 7), + MUX(CLK_TOP_NFI1X_PAD_SEL, nfi1x_pad_parents, 0x004, 7, 1), + MUX(CLK_TOP_MFG_MM_SEL, mfg_mm_parents, 0x004, 8, 6), + MUX(CLK_TOP_DDRPHYCFG_SEL, ddrphycfg_parents, 0x004, 15, 1), + MUX(CLK_TOP_USB_78M_SEL, usb_78m_parents, 0x004, 20, 3), /* CLK_MUX_SEL8 */ - MUX_MIXED(CLK_TOP_SPINOR_SEL, spinor_parents, 0x040, 0, 3), - MUX_MIXED(CLK_TOP_MSDC2_SEL, msdc2_parents, 0x040, 3, 3), - MUX_MIXED(CLK_TOP_ETH_SEL, eth_parents, 0x040, 6, 3), - MUX_MIXED(CLK_TOP_AXI_MFG_IN_SEL, axi_mfg_in_parents, 0x040, 18, 2), - MUX_MIXED(CLK_TOP_SLOW_MFG_SEL, slow_mfg_parents, 0x040, 20, 2), - MUX_MIXED(CLK_TOP_AUD1_SEL, aud1_parents, 0x040, 22, 1), - MUX_MIXED(CLK_TOP_AUD2_SEL, aud2_parents, 0x040, 23, 1), - MUX_MIXED(CLK_TOP_AUD_ENGEN1_SEL, aud_engen1_parents, 0x040, 24, 2), - MUX_MIXED(CLK_TOP_AUD_ENGEN2_SEL, aud_engen2_parents, 0x040, 26, 2), - MUX_MIXED(CLK_TOP_I2C_SEL, i2c_parents, 0x040, 28, 2), + MUX(CLK_TOP_SPINOR_SEL, spinor_parents, 0x040, 0, 3), + MUX(CLK_TOP_MSDC2_SEL, msdc2_parents, 0x040, 3, 3), + MUX(CLK_TOP_ETH_SEL, eth_parents, 0x040, 6, 3), + MUX(CLK_TOP_AXI_MFG_IN_SEL, axi_mfg_in_parents, 0x040, 18, 2), + MUX(CLK_TOP_SLOW_MFG_SEL, slow_mfg_parents, 0x040, 20, 2), + MUX(CLK_TOP_AUD1_SEL, aud1_parents, 0x040, 22, 1), + MUX(CLK_TOP_AUD2_SEL, aud2_parents, 0x040, 23, 1), + MUX(CLK_TOP_AUD_ENGEN1_SEL, aud_engen1_parents, 0x040, 24, 2), + MUX(CLK_TOP_AUD_ENGEN2_SEL, aud_engen2_parents, 0x040, 26, 2), + MUX(CLK_TOP_I2C_SEL, i2c_parents, 0x040, 28, 2), /* CLK_MUX_SEL9 */ - MUX_MIXED(CLK_TOP_AUD_I2S0_M_SEL, aud_i2s0_m_parents, 0x044, 12, 1), - MUX_MIXED(CLK_TOP_AUD_I2S1_M_SEL, aud_i2s0_m_parents, 0x044, 13, 1), - MUX_MIXED(CLK_TOP_AUD_I2S2_M_SEL, aud_i2s0_m_parents, 0x044, 14, 1), - MUX_MIXED(CLK_TOP_AUD_I2S3_M_SEL, aud_i2s0_m_parents, 0x044, 15, 1), - MUX_MIXED(CLK_TOP_AUD_I2S4_M_SEL, aud_i2s0_m_parents, 0x044, 16, 1), - MUX_MIXED(CLK_TOP_AUD_I2S5_M_SEL, aud_i2s0_m_parents, 0x044, 17, 1), - MUX_MIXED(CLK_TOP_AUD_SPDIF_B_SEL, aud_i2s0_m_parents, 0x044, 18, 1), + MUX(CLK_TOP_AUD_I2S0_M_SEL, aud_i2s0_m_parents, 0x044, 12, 1), + MUX(CLK_TOP_AUD_I2S1_M_SEL, aud_i2s0_m_parents, 0x044, 13, 1), + MUX(CLK_TOP_AUD_I2S2_M_SEL, aud_i2s0_m_parents, 0x044, 14, 1), + MUX(CLK_TOP_AUD_I2S3_M_SEL, aud_i2s0_m_parents, 0x044, 15, 1), + MUX(CLK_TOP_AUD_I2S4_M_SEL, aud_i2s0_m_parents, 0x044, 16, 1), + MUX(CLK_TOP_AUD_I2S5_M_SEL, aud_i2s0_m_parents, 0x044, 17, 1), + MUX(CLK_TOP_AUD_SPDIF_B_SEL, aud_i2s0_m_parents, 0x044, 18, 1), /* CLK_MUX_SEL13 */ - MUX_MIXED(CLK_TOP_PWM_SEL, pwm_parents, 0x07c, 0, 1), - MUX_MIXED(CLK_TOP_SPI_SEL, spi_parents, 0x07c, 1, 2), - MUX_MIXED(CLK_TOP_AUD_SPDIFIN_SEL, aud_spdifin_parents, 0x07c, 3, 1), - MUX_MIXED(CLK_TOP_UART2_SEL, uart2_parents, 0x07c, 4, 1), - MUX_MIXED(CLK_TOP_BSI_SEL, bsi_parents, 0x07c, 5, 2), - MUX_MIXED(CLK_TOP_DBG_ATCLK_SEL, dbg_atclk_parents, 0x07c, 7, 3), - MUX_MIXED(CLK_TOP_CSW_NFIECC_SEL, csw_nfiecc_parents, 0x07c, 10, 3), - MUX_MIXED(CLK_TOP_NFIECC_SEL, nfiecc_parents, 0x07c, 13, 3), + MUX(CLK_TOP_PWM_SEL, pwm_parents, 0x07c, 0, 1), + MUX(CLK_TOP_SPI_SEL, spi_parents, 0x07c, 1, 2), + MUX(CLK_TOP_AUD_SPDIFIN_SEL, aud_spdifin_parents, 0x07c, 3, 1), + MUX(CLK_TOP_UART2_SEL, uart2_parents, 0x07c, 4, 1), + MUX(CLK_TOP_BSI_SEL, bsi_parents, 0x07c, 5, 2), + MUX(CLK_TOP_DBG_ATCLK_SEL, dbg_atclk_parents, 0x07c, 7, 3), + MUX(CLK_TOP_CSW_NFIECC_SEL, csw_nfiecc_parents, 0x07c, 10, 3), + MUX(CLK_TOP_NFIECC_SEL, nfiecc_parents, 0x07c, 13, 3), }; static const struct mtk_gate_regs top0_cg_regs = { diff --git a/drivers/clk/mediatek/clk-mt8518.c b/drivers/clk/mediatek/clk-mt8518.c index 482d1346da5..34fa5a127d5 100644 --- a/drivers/clk/mediatek/clk-mt8518.c +++ b/drivers/clk/mediatek/clk-mt8518.c @@ -1182,77 +1182,77 @@ static const struct mtk_parent disp_dpi_ck_parents[] = { static const struct mtk_composite top_muxes[] = { /* CLK_MUX_SEL0 */ - MUX_MIXED(CLK_TOP_UART0_SEL, uart0_parents, 0x000, 0, 1), - MUX_MIXED(CLK_TOP_EMI1X_SEL, emi1x_parents, 0x000, 1, 1), - MUX_MIXED(CLK_TOP_EMI_DDRPHY_SEL, emi_ddrphy_parents, 0x000, 2, 1), - MUX_MIXED(CLK_TOP_MSDC1_SEL, msdc1_parents, 0x000, 4, 8), - MUX_MIXED(CLK_TOP_PWM_MM_SEL, pwm_mm_parents, 0x000, 18, 1), - MUX_MIXED(CLK_TOP_UART1_SEL, uart0_parents, 0x000, 19, 1), - MUX_MIXED(CLK_TOP_SPM_52M_SEL, uart0_parents, 0x000, 22, 1), - MUX_MIXED(CLK_TOP_PMICSPI_SEL, pmicspi_parents, 0x000, 23, 3), + MUX(CLK_TOP_UART0_SEL, uart0_parents, 0x000, 0, 1), + MUX(CLK_TOP_EMI1X_SEL, emi1x_parents, 0x000, 1, 1), + MUX(CLK_TOP_EMI_DDRPHY_SEL, emi_ddrphy_parents, 0x000, 2, 1), + MUX(CLK_TOP_MSDC1_SEL, msdc1_parents, 0x000, 4, 8), + MUX(CLK_TOP_PWM_MM_SEL, pwm_mm_parents, 0x000, 18, 1), + MUX(CLK_TOP_UART1_SEL, uart0_parents, 0x000, 19, 1), + MUX(CLK_TOP_SPM_52M_SEL, uart0_parents, 0x000, 22, 1), + MUX(CLK_TOP_PMICSPI_SEL, pmicspi_parents, 0x000, 23, 3), /* CLK_MUX_SEL1 */ - MUX_MIXED(CLK_TOP_NFI2X_SEL, nfi2x_parents, 0x004, 0, 3), - MUX_MIXED(CLK_TOP_DDRPHYCFG_SEL, ddrphycfg_parents, 0x004, 15, 1), - MUX_MIXED(CLK_TOP_SMI_SEL, smi_parents, 0x004, 16, 4), - MUX_MIXED(CLK_TOP_USB_SEL, usb_parents, 0x004, 20, 3), + MUX(CLK_TOP_NFI2X_SEL, nfi2x_parents, 0x004, 0, 3), + MUX(CLK_TOP_DDRPHYCFG_SEL, ddrphycfg_parents, 0x004, 15, 1), + MUX(CLK_TOP_SMI_SEL, smi_parents, 0x004, 16, 4), + MUX(CLK_TOP_USB_SEL, usb_parents, 0x004, 20, 3), /* CLK_MUX_SEL8 */ - MUX_MIXED(CLK_TOP_SPINOR_SEL, spinor_parents, 0x040, 0, 3), - MUX_MIXED(CLK_TOP_ETH_SEL, eth_parents, 0x040, 6, 3), - MUX_MIXED(CLK_TOP_AUD1_SEL, aud1_parents, 0x040, 22, 1), - MUX_MIXED(CLK_TOP_AUD2_SEL, aud2_parents, 0x040, 23, 1), - MUX_MIXED(CLK_TOP_I2C_SEL, i2c_parents, 0x040, 28, 3), + MUX(CLK_TOP_SPINOR_SEL, spinor_parents, 0x040, 0, 3), + MUX(CLK_TOP_ETH_SEL, eth_parents, 0x040, 6, 3), + MUX(CLK_TOP_AUD1_SEL, aud1_parents, 0x040, 22, 1), + MUX(CLK_TOP_AUD2_SEL, aud2_parents, 0x040, 23, 1), + MUX(CLK_TOP_I2C_SEL, i2c_parents, 0x040, 28, 3), /* CLK_SEL_9 */ - MUX_MIXED(CLK_TOP_AUD_I2S0_M_SEL, aud_i2s0_m_parents, 0x044, 12, 1), - MUX_MIXED(CLK_TOP_AUD_I2S3_M_SEL, aud_i2s0_m_parents, 0x044, 15, 1), - MUX_MIXED(CLK_TOP_AUD_I2S4_M_SEL, aud_i2s0_m_parents, 0x044, 16, 1), - MUX_MIXED(CLK_TOP_AUD_I2S6_M_SEL, aud_i2s0_m_parents, 0x044, 18, 1), + MUX(CLK_TOP_AUD_I2S0_M_SEL, aud_i2s0_m_parents, 0x044, 12, 1), + MUX(CLK_TOP_AUD_I2S3_M_SEL, aud_i2s0_m_parents, 0x044, 15, 1), + MUX(CLK_TOP_AUD_I2S4_M_SEL, aud_i2s0_m_parents, 0x044, 16, 1), + MUX(CLK_TOP_AUD_I2S6_M_SEL, aud_i2s0_m_parents, 0x044, 18, 1), /* CLK_MUX_SEL13 */ - MUX_MIXED(CLK_TOP_PWM_SEL, pwm_mm_parents, 0x07c, 0, 1), - MUX_MIXED(CLK_TOP_AUD_SPDIFIN_SEL, aud_spdifin_parents, 0x07c, 2, 2), - MUX_MIXED(CLK_TOP_UART2_SEL, uart0_parents, 0x07c, 4, 1), - MUX_MIXED(CLK_TOP_DBG_ATCLK_SEL, dbg_atclk_parents, 0x07c, 7, 3), - MUX_MIXED(CLK_TOP_PNG_SYS_SEL, png_sys_parents, 0x07c, 16, 3), - MUX_MIXED(CLK_TOP_SEJ_13M_SEL, sej_13m_parents, 0x07c, 22, 1), + MUX(CLK_TOP_PWM_SEL, pwm_mm_parents, 0x07c, 0, 1), + MUX(CLK_TOP_AUD_SPDIFIN_SEL, aud_spdifin_parents, 0x07c, 2, 2), + MUX(CLK_TOP_UART2_SEL, uart0_parents, 0x07c, 4, 1), + MUX(CLK_TOP_DBG_ATCLK_SEL, dbg_atclk_parents, 0x07c, 7, 3), + MUX(CLK_TOP_PNG_SYS_SEL, png_sys_parents, 0x07c, 16, 3), + MUX(CLK_TOP_SEJ_13M_SEL, sej_13m_parents, 0x07c, 22, 1), /* CLK_MUX_SEL14 */ - MUX_MIXED(CLK_TOP_IMGRZ_SYS_SEL, imgrz_sys_parents, 0xc0, 0, 3), - MUX_MIXED(CLK_TOP_GRAPH_ECLK_SEL, graph_eclk_parents, 0xc0, 8, 4), - MUX_MIXED(CLK_TOP_FDBI_SEL, fdbi_parents, 0xc0, 12, 4), - MUX_MIXED(CLK_TOP_FAUDIO_SEL, faudio_parents, 0xc0, 16, 2), - MUX_MIXED(CLK_TOP_FA2SYS_SEL, fa2sys_parents, 0xc0, 24, 3), - MUX_MIXED(CLK_TOP_FA1SYS_SEL, fa1sys_parents, 0xc0, 27, 3), - MUX_MIXED(CLK_TOP_FASM_M_SEL, fasm_m_parents, 0xc0, 30, 2), + MUX(CLK_TOP_IMGRZ_SYS_SEL, imgrz_sys_parents, 0xc0, 0, 3), + MUX(CLK_TOP_GRAPH_ECLK_SEL, graph_eclk_parents, 0xc0, 8, 4), + MUX(CLK_TOP_FDBI_SEL, fdbi_parents, 0xc0, 12, 4), + MUX(CLK_TOP_FAUDIO_SEL, faudio_parents, 0xc0, 16, 2), + MUX(CLK_TOP_FA2SYS_SEL, fa2sys_parents, 0xc0, 24, 3), + MUX(CLK_TOP_FA1SYS_SEL, fa1sys_parents, 0xc0, 27, 3), + MUX(CLK_TOP_FASM_M_SEL, fasm_m_parents, 0xc0, 30, 2), /* CLK_MUX_SEL15 */ - MUX_MIXED(CLK_TOP_FASM_H_SEL, fasm_m_parents, 0xC4, 0, 2), - MUX_MIXED(CLK_TOP_FASM_L_SEL, fasm_m_parents, 0xC4, 2, 2), - MUX_MIXED(CLK_TOP_FECC_CK_SEL, fecc_ck_parents, 0xC4, 18, 6), - MUX_MIXED(CLK_TOP_PE2_MAC_SEL, pe2_mac_parents, 0xC4, 24, 3), - MUX_MIXED(CLK_TOP_CMSYS_SEL, cmsys_parents, 0xC4, 28, 3), + MUX(CLK_TOP_FASM_H_SEL, fasm_m_parents, 0xC4, 0, 2), + MUX(CLK_TOP_FASM_L_SEL, fasm_m_parents, 0xC4, 2, 2), + MUX(CLK_TOP_FECC_CK_SEL, fecc_ck_parents, 0xC4, 18, 6), + MUX(CLK_TOP_PE2_MAC_SEL, pe2_mac_parents, 0xC4, 24, 3), + MUX(CLK_TOP_CMSYS_SEL, cmsys_parents, 0xC4, 28, 3), /* CLK_MUX_SEL16 */ - MUX_MIXED(CLK_TOP_GCPU_SEL, gcpu_parents, 0xC8, 0, 3), - MUX_MIXED(CLK_TOP_SPIS_CK_SEL, spis_ck_parents, 0xC8, 4, 8), + MUX(CLK_TOP_GCPU_SEL, gcpu_parents, 0xC8, 0, 3), + MUX(CLK_TOP_SPIS_CK_SEL, spis_ck_parents, 0xC8, 4, 8), /* CLK_MUX_SEL17 */ - MUX_MIXED(CLK_TOP_APLL1_REF_SEL, apll1_ref_parents, 0xCC, 6, 3), - MUX_MIXED(CLK_TOP_APLL2_REF_SEL, apll1_ref_parents, 0xCC, 9, 3), - MUX_MIXED(CLK_TOP_INT_32K_SEL, int_32k_parents, 0xCC, 12, 1), - MUX_MIXED(CLK_TOP_APLL1_SRC_SEL, apll1_src_parents, 0xCC, 13, 2), - MUX_MIXED(CLK_TOP_APLL2_SRC_SEL, apll2_src_parents, 0xCC, 15, 2), + MUX(CLK_TOP_APLL1_REF_SEL, apll1_ref_parents, 0xCC, 6, 3), + MUX(CLK_TOP_APLL2_REF_SEL, apll1_ref_parents, 0xCC, 9, 3), + MUX(CLK_TOP_INT_32K_SEL, int_32k_parents, 0xCC, 12, 1), + MUX(CLK_TOP_APLL1_SRC_SEL, apll1_src_parents, 0xCC, 13, 2), + MUX(CLK_TOP_APLL2_SRC_SEL, apll2_src_parents, 0xCC, 15, 2), /* CLK_MUX_SEL19 */ - MUX_MIXED(CLK_TOP_FAUD_INTBUS_SEL, faud_intbus_parents, 0xD4, 8, 8), - MUX_MIXED(CLK_TOP_AXIBUS_SEL, axibus_parents, 0xD4, 24, 8), + MUX(CLK_TOP_FAUD_INTBUS_SEL, faud_intbus_parents, 0xD4, 8, 8), + MUX(CLK_TOP_AXIBUS_SEL, axibus_parents, 0xD4, 24, 8), /* CLK_MUX_SEL21 */ - MUX_MIXED(CLK_TOP_HAPLL1_SEL, hapll1_parents, 0xDC, 0, 4), - MUX_MIXED(CLK_TOP_HAPLL2_SEL, hapll2_parents, 0xDC, 4, 4), - MUX_MIXED(CLK_TOP_SPINFI_SEL, spinfi_parents, 0xDC, 8, 4), + MUX(CLK_TOP_HAPLL1_SEL, hapll1_parents, 0xDC, 0, 4), + MUX(CLK_TOP_HAPLL2_SEL, hapll2_parents, 0xDC, 4, 4), + MUX(CLK_TOP_SPINFI_SEL, spinfi_parents, 0xDC, 8, 4), /* CLK_MUX_SEL22 */ - MUX_MIXED(CLK_TOP_MSDC0_SEL, msdc0_parents, 0xF4, 0, 8), - MUX_MIXED(CLK_TOP_MSDC0_CLK50_SEL, msdc0_clk50_parents, 0xF4, 8, 6), - MUX_MIXED(CLK_TOP_MSDC2_SEL, msdc2_parents, 0xF4, 15, 8), - MUX_MIXED(CLK_TOP_MSDC2_CLK50_SEL, msdc0_clk50_parents, 0xF4, 23, 6), + MUX(CLK_TOP_MSDC0_SEL, msdc0_parents, 0xF4, 0, 8), + MUX(CLK_TOP_MSDC0_CLK50_SEL, msdc0_clk50_parents, 0xF4, 8, 6), + MUX(CLK_TOP_MSDC2_SEL, msdc2_parents, 0xF4, 15, 8), + MUX(CLK_TOP_MSDC2_CLK50_SEL, msdc0_clk50_parents, 0xF4, 23, 6), /* CLK_MUX_SEL23 */ - MUX_MIXED(CLK_TOP_DISP_DPI_CK_SEL, disp_dpi_ck_parents, 0xF8, 0, 6), - MUX_MIXED(CLK_TOP_SPI1_SEL, spis_ck_parents, 0xF8, 6, 8), - MUX_MIXED(CLK_TOP_SPI2_SEL, spis_ck_parents, 0xF8, 14, 8), - MUX_MIXED(CLK_TOP_SPI3_SEL, spis_ck_parents, 0xF8, 22, 8), + MUX(CLK_TOP_DISP_DPI_CK_SEL, disp_dpi_ck_parents, 0xF8, 0, 6), + MUX(CLK_TOP_SPI1_SEL, spis_ck_parents, 0xF8, 6, 8), + MUX(CLK_TOP_SPI2_SEL, spis_ck_parents, 0xF8, 14, 8), + MUX(CLK_TOP_SPI3_SEL, spis_ck_parents, 0xF8, 22, 8), }; static const struct mtk_gate_regs top0_cg_regs = { diff --git a/drivers/clk/mediatek/clk-mtk.c b/drivers/clk/mediatek/clk-mtk.c index 30439ae7d93..ddf4ac755bb 100644 --- a/drivers/clk/mediatek/clk-mtk.c +++ b/drivers/clk/mediatek/clk-mtk.c @@ -259,22 +259,15 @@ static int mtk_clk_mux_set_parent(void __iomem *base, u32 parent, { u32 val, index = 0; - if (mux->flags & CLK_PARENT_MIXED) { - /* - * Assume parent_type in clk_tree to be always set with - * CLK_PARENT_MIXED implementation. If it's not, assume - * not parent clk ID clash is possible. - */ - while (mux->parent_flags[index].id != parent || - (parent_type && (mux->parent_flags[index].flags & CLK_PARENT_MASK) != - parent_type)) - if (++index == mux->num_parents) - return -EINVAL; - } else { - while (mux->parent[index] != parent) - if (++index == mux->num_parents) - return -EINVAL; - } + /* + * Assume parent_type in clk_tree to be always set. If it's not, assume + * parent clk ID clash is not possible. + */ + while (mux->parent[index].id != parent || + (parent_type && (mux->parent[index].flags & CLK_PARENT_MASK) != + parent_type)) + if (++index == mux->num_parents) + return -EINVAL; if (mux->flags & CLK_MUX_SETCLR_UPD) { val = (mux->mux_mask << mux->mux_shift); @@ -350,9 +343,6 @@ static void mtk_clk_print_parent(const char *prefix, int parent, u32 flags) case CLK_PARENT_EXT: parent_type_str = "ext"; break; - case CLK_PARENT_MIXED: - parent_type_str = "mixed"; - break; default: parent_type_str = "default"; break; @@ -381,18 +371,14 @@ static void mtk_clk_print_mux_parents(struct mtk_clk_priv *priv, /* Print parents separated by "/" and selected parent enclosed in "*"s */ for (i = 0; i < mux->num_parents; i++) { + const struct mtk_parent *parent = &mux->parent[i]; + if (i == selected) { printf("%s", prefix); prefix = "*"; } - if (mux->flags & CLK_PARENT_MIXED) { - const struct mtk_parent *parent = &mux->parent_flags[i]; - - mtk_clk_print_parent(prefix, parent->id, parent->flags); - } else { - mtk_clk_print_parent(prefix, mux->parent[i], mux->flags); - } + mtk_clk_print_parent(prefix, parent->id, parent->flags); prefix = "/"; @@ -719,23 +705,15 @@ static ulong mtk_topckgen_get_mux_rate(struct clk *clk, u32 off) { struct mtk_clk_priv *priv = dev_get_priv(clk->dev); const struct mtk_composite *mux = &priv->tree->muxes[off]; + const struct mtk_parent *parent; u32 index; index = readl(priv->base + mux->mux_reg); index &= mux->mux_mask << mux->mux_shift; index = index >> mux->mux_shift; + parent = &mux->parent[index]; - /* - * Parents can be either from APMIXED or TOPCKGEN, - * inspect the mtk_parent struct to check the source - */ - if (mux->flags & CLK_PARENT_MIXED) { - const struct mtk_parent *parent = &mux->parent_flags[index]; - - return mtk_find_parent_rate(priv, clk, parent->id, parent->flags); - } - - return mtk_find_parent_rate(priv, clk, mux->parent[index], mux->flags); + return mtk_find_parent_rate(priv, clk, parent->id, parent->flags); } static ulong mtk_topckgen_get_rate(struct clk *clk) @@ -985,23 +963,15 @@ static ulong mtk_infrasys_get_mux_rate(struct clk *clk, u32 off) { struct mtk_clk_priv *priv = dev_get_priv(clk->dev); const struct mtk_composite *mux = &priv->tree->muxes[off]; + const struct mtk_parent *parent; u32 index; index = readl(priv->base + mux->mux_reg); index &= mux->mux_mask << mux->mux_shift; index = index >> mux->mux_shift; + parent = &mux->parent[index]; - /* - * Parents can be either from TOPCKGEN or INFRACFG, - * inspect the mtk_parent struct to check the source - */ - if (mux->flags & CLK_PARENT_MIXED) { - const struct mtk_parent *parent = &mux->parent_flags[index]; - - return mtk_find_parent_rate(priv, clk, parent->id, parent->flags); - } - - return mtk_find_parent_rate(priv, clk, mux->parent[index], mux->flags); + return mtk_find_parent_rate(priv, clk, parent->id, parent->flags); } static ulong mtk_infrasys_get_rate(struct clk *clk) diff --git a/drivers/clk/mediatek/clk-mtk.h b/drivers/clk/mediatek/clk-mtk.h index 2d67cf15f47..10a0723de47 100644 --- a/drivers/clk/mediatek/clk-mtk.h +++ b/drivers/clk/mediatek/clk-mtk.h @@ -29,12 +29,7 @@ #define CLK_PARENT_INFRASYS BIT(6) #define CLK_PARENT_XTAL BIT(7) #define CLK_PARENT_EXT BIT(8) -/* - * For CLK_PARENT_MIXED to correctly work, is required to - * define in clk_tree flags the clk type using the alias. - */ -#define CLK_PARENT_MIXED BIT(9) -#define CLK_PARENT_MASK GENMASK(9, 4) +#define CLK_PARENT_MASK GENMASK(8, 4) #define ETHSYS_HIFSYS_RST_CTRL_OFS 0x34 @@ -133,8 +128,7 @@ struct mtk_parent { * struct mtk_composite - aggregate clock of mux, divider and gate clocks * * @id: unmapped ID of clocks - * @parent: unmapped ID of parent clocks - * @parent_flags: table of parent clocks with flags + * @parent: array of parent clocks * @mux_reg: hardware-specific mux register * @gate_reg: hardware-specific gate register * @mux_mask: mask to the mux bit field @@ -145,10 +139,7 @@ struct mtk_parent { */ struct mtk_composite { const int id; - union { - const int *parent; - const struct mtk_parent *parent_flags; - }; + const struct mtk_parent *parent; u32 mux_reg; u32 mux_set_reg; u32 mux_clr_reg; @@ -178,35 +169,6 @@ struct mtk_composite { #define MUX_GATE(_id, _parents, _reg, _shift, _width, _gate) \ MUX_GATE_FLAGS(_id, _parents, _reg, _shift, _width, _gate, 0) -#define MUX_GATE_MIXED_FLAGS(_id, _parents, _reg, _shift, _width, _gate,\ - _flags) { \ - .id = _id, \ - .mux_reg = _reg, \ - .mux_shift = _shift, \ - .mux_mask = BIT(_width) - 1, \ - .gate_reg = _reg, \ - .gate_shift = _gate, \ - .parent_flags = _parents, \ - .num_parents = ARRAY_SIZE(_parents), \ - .flags = (_flags) | CLK_PARENT_MIXED, \ - } - -#define MUX_GATE_MIXED(_id, _parents, _reg, _shift, _width, _gate) \ - MUX_GATE_MIXED_FLAGS(_id, _parents, _reg, _shift, _width, _gate, 0) - -#define MUX_MIXED_FLAGS(_id, _parents, _reg, _shift, _width, _flags) { \ - .id = _id, \ - .mux_reg = _reg, \ - .mux_shift = _shift, \ - .mux_mask = BIT(_width) - 1, \ - .gate_shift = -1, \ - .parent_flags = _parents, \ - .num_parents = ARRAY_SIZE(_parents), \ - .flags = CLK_PARENT_MIXED | (_flags), \ - } -#define MUX_MIXED(_id, _parents, _reg, _shift, _width) \ - MUX_MIXED_FLAGS(_id, _parents, _reg, _shift, _width, 0) - #define MUX_FLAGS(_id, _parents, _reg, _shift, _width, _flags) { \ .id = _id, \ .mux_reg = _reg, \ @@ -238,24 +200,6 @@ struct mtk_composite { .flags = _flags, \ } -#define MUX_MIXED_CLR_SET_UPD_FLAGS(_id, _parents, _mux_ofs, _mux_set_ofs,\ - _mux_clr_ofs, _shift, _width, _gate,\ - _upd_ofs, _upd, _flags) { \ - .id = _id, \ - .mux_reg = _mux_ofs, \ - .mux_set_reg = _mux_set_ofs, \ - .mux_clr_reg = _mux_clr_ofs, \ - .upd_reg = _upd_ofs, \ - .upd_shift = _upd, \ - .mux_shift = _shift, \ - .mux_mask = BIT(_width) - 1, \ - .gate_reg = _mux_ofs, \ - .gate_shift = _gate, \ - .parent_flags = _parents, \ - .num_parents = ARRAY_SIZE(_parents), \ - .flags = CLK_PARENT_MIXED | (_flags), \ - } - struct mtk_gate_regs { u32 sta_ofs; u32 clr_ofs; -- cgit v1.3.1 From 256499eebf4fe81d1d7ea5b5899ff201d38296fd Mon Sep 17 00:00:00 2001 From: David Lechner Date: Tue, 17 Mar 2026 18:23:29 -0500 Subject: clk: mediatek: refactor duplicate *_mux_get_rate() Refactor two identical functions for getting mux clock rates. The functions are renamed and moved to the section of the code that contains other common functions. Reviewed-by: Julien Stephan Link: https://patch.msgid.link/20260317-clk-mtk-unify-mux-parents-v3-16-a4760f5b0a80@baylibre.com Signed-off-by: David Lechner --- drivers/clk/mediatek/clk-mtk.c | 50 ++++++++++++++---------------------------- 1 file changed, 17 insertions(+), 33 deletions(-) diff --git a/drivers/clk/mediatek/clk-mtk.c b/drivers/clk/mediatek/clk-mtk.c index ddf4ac755bb..fa4a84bfceb 100644 --- a/drivers/clk/mediatek/clk-mtk.c +++ b/drivers/clk/mediatek/clk-mtk.c @@ -253,6 +253,21 @@ static ulong mtk_find_parent_rate(struct mtk_clk_priv *priv, struct clk *clk, return mtk_clk_find_parent_rate(clk, parent, parent_dev); } +static ulong mtk_clk_mux_get_rate(struct clk *clk, u32 off) +{ + struct mtk_clk_priv *priv = dev_get_priv(clk->dev); + const struct mtk_composite *mux = &priv->tree->muxes[off]; + const struct mtk_parent *parent; + u32 index; + + index = readl(priv->base + mux->mux_reg); + index &= mux->mux_mask << mux->mux_shift; + index = index >> mux->mux_shift; + parent = &mux->parent[index]; + + return mtk_find_parent_rate(priv, clk, parent->id, parent->flags); +} + static int mtk_clk_mux_set_parent(void __iomem *base, u32 parent, u32 parent_type, const struct mtk_composite *mux) @@ -701,21 +716,6 @@ static ulong mtk_topckgen_get_factor_rate(struct clk *clk, u32 off) return mtk_factor_recalc_rate(fdiv, rate); } -static ulong mtk_topckgen_get_mux_rate(struct clk *clk, u32 off) -{ - struct mtk_clk_priv *priv = dev_get_priv(clk->dev); - const struct mtk_composite *mux = &priv->tree->muxes[off]; - const struct mtk_parent *parent; - u32 index; - - index = readl(priv->base + mux->mux_reg); - index &= mux->mux_mask << mux->mux_shift; - index = index >> mux->mux_shift; - parent = &mux->parent[index]; - - return mtk_find_parent_rate(priv, clk, parent->id, parent->flags); -} - static ulong mtk_topckgen_get_rate(struct clk *clk) { struct mtk_clk_priv *priv = dev_get_priv(clk->dev); @@ -728,7 +728,7 @@ static ulong mtk_topckgen_get_rate(struct clk *clk) return mtk_topckgen_get_factor_rate(clk, clk->id - tree->fdivs_offs); if (mtk_clk_id_is_mux(tree, clk->id)) - return mtk_topckgen_get_mux_rate(clk, clk->id - tree->muxes_offs); + return mtk_clk_mux_get_rate(clk, clk->id - tree->muxes_offs); if (mtk_clk_id_is_gate(tree, clk->id)) { const struct mtk_gate *gate = &tree->gates[clk->id - tree->gates_offs]; @@ -959,21 +959,6 @@ static ulong mtk_infrasys_get_factor_rate(struct clk *clk, u32 off) return mtk_factor_recalc_rate(fdiv, rate); } -static ulong mtk_infrasys_get_mux_rate(struct clk *clk, u32 off) -{ - struct mtk_clk_priv *priv = dev_get_priv(clk->dev); - const struct mtk_composite *mux = &priv->tree->muxes[off]; - const struct mtk_parent *parent; - u32 index; - - index = readl(priv->base + mux->mux_reg); - index &= mux->mux_mask << mux->mux_shift; - index = index >> mux->mux_shift; - parent = &mux->parent[index]; - - return mtk_find_parent_rate(priv, clk, parent->id, parent->flags); -} - static ulong mtk_infrasys_get_rate(struct clk *clk) { struct mtk_clk_priv *priv = dev_get_priv(clk->dev); @@ -986,8 +971,7 @@ static ulong mtk_infrasys_get_rate(struct clk *clk) priv->tree->fdivs_offs); /* No gates defined or ID is a MUX */ } else if (!mtk_clk_id_is_gate(priv->tree, clk->id)) { - rate = mtk_infrasys_get_mux_rate(clk, clk->id - - priv->tree->muxes_offs); + rate = mtk_clk_mux_get_rate(clk, clk->id - priv->tree->muxes_offs); /* Only valid with muxes + gates implementation */ } else { const struct mtk_gate *gate; -- cgit v1.3.1 From de935cb5191c21fc57dfd1f1235023bd8d0a8513 Mon Sep 17 00:00:00 2001 From: David Lechner Date: Tue, 3 Mar 2026 16:17:47 -0600 Subject: clk: mediatek: mt8365: drop topckgen map Drop the clock ID map for MT8365 TOPCKGEN clocks. Previously, we didn't have the EXT clock feature, so we needed the map. Now we can replace it with the new feature to avoid the map. Reviewed-by: Julien Stephan Link: https://patch.msgid.link/20260303-mtk-clk-8365-drop-map-v1-1-17f81c375290@baylibre.com Signed-off-by: David Lechner --- drivers/clk/mediatek/clk-mt8365.c | 307 +++++++++++++------------------------- 1 file changed, 103 insertions(+), 204 deletions(-) diff --git a/drivers/clk/mediatek/clk-mt8365.c b/drivers/clk/mediatek/clk-mt8365.c index c6803090f35..a69799b8496 100644 --- a/drivers/clk/mediatek/clk-mt8365.c +++ b/drivers/clk/mediatek/clk-mt8365.c @@ -13,9 +13,15 @@ #include #include "clk-mtk.h" -/* Missing topckgen clocks definition in dt-bindings */ -#define CLK_TOP_CLK26M 141 -#define CLK_TOP_CLK32K 142 +enum { + CLK_PAD_CLK32K, + CLK_PAD_CLK26M, +}; + +static const ulong ext_clock_rates[] = { + [CLK_PAD_CLK32K] = 32000, + [CLK_PAD_CLK26M] = 26000000, +}; /* apmixedsys */ #define MT8365_PLL_FMAX (3800UL * MHZ) @@ -70,151 +76,14 @@ static const struct mtk_pll_data apmixed_plls[] = { static const struct mtk_clk_tree mt8365_apmixed_tree = { .xtal_rate = 26 * MHZ, .xtal2_rate = 26 * MHZ, + .ext_clk_rates = ext_clock_rates, + .num_ext_clks = ARRAY_SIZE(ext_clock_rates), .plls = apmixed_plls, .num_plls = ARRAY_SIZE(apmixed_plls), }; /* topckgen */ -/* - * The devicetree bindings missed a few clocks and can't be changed, so we need - * to provide a mapping to fix the omissions. - */ -static const int mt8365_topckgen_id_map[] = { - [0 ... CLK_TOP_NR_CLK - 1] = -1, - /* FIXED */ - /* Fixed 32K oscillator is not available in devicetree definitions */ - [CLK_TOP_CLK32K] = 0, - [CLK_TOP_CLK_NULL] = 1, - [CLK_TOP_I2S0_BCK] = 2, - [CLK_TOP_DSI0_LNTC_DSICK] = 3, - [CLK_TOP_VPLL_DPIX] = 4, - [CLK_TOP_LVDSTX_CLKDIG_CTS] = 5, - /* FACTOR */ - [CLK_TOP_MFGPLL] = 6, - [CLK_TOP_SYSPLL_D2] = 7, - [CLK_TOP_SYSPLL1_D2] = 8, - [CLK_TOP_SYSPLL1_D4] = 9, - [CLK_TOP_SYSPLL1_D8] = 10, - [CLK_TOP_SYSPLL1_D16] = 11, - [CLK_TOP_SYSPLL_D3] = 12, - [CLK_TOP_SYSPLL2_D2] = 13, - [CLK_TOP_SYSPLL2_D4] = 14, - [CLK_TOP_SYSPLL2_D8] = 15, - [CLK_TOP_SYSPLL_D5] = 16, - [CLK_TOP_SYSPLL3_D2] = 17, - [CLK_TOP_SYSPLL3_D4] = 18, - [CLK_TOP_SYSPLL_D7] = 19, - [CLK_TOP_SYSPLL4_D2] = 20, - [CLK_TOP_SYSPLL4_D4] = 21, - /* Skipping CLK_TOP_UNIVPLL since isn't a real clock. */ - [CLK_TOP_UNIVPLL_D2] = 22, - [CLK_TOP_UNIVPLL1_D2] = 23, - [CLK_TOP_UNIVPLL1_D4] = 24, - [CLK_TOP_UNIVPLL_D3] = 25, - [CLK_TOP_UNIVPLL2_D2] = 26, - [CLK_TOP_UNIVPLL2_D4] = 27, - [CLK_TOP_UNIVPLL2_D8] = 28, - [CLK_TOP_UNIVPLL2_D32] = 29, - [CLK_TOP_UNIVPLL_D5] = 30, - [CLK_TOP_UNIVPLL3_D2] = 31, - [CLK_TOP_UNIVPLL3_D4] = 32, - [CLK_TOP_MMPLL] = 33, - [CLK_TOP_MMPLL_D2] = 34, - [CLK_TOP_LVDSPLL_D2] = 35, - [CLK_TOP_LVDSPLL_D4] = 36, - [CLK_TOP_LVDSPLL_D8] = 37, - [CLK_TOP_LVDSPLL_D16] = 38, - [CLK_TOP_USB20_192M] = 39, - [CLK_TOP_USB20_192M_D4] = 40, - [CLK_TOP_USB20_192M_D8] = 41, - [CLK_TOP_USB20_192M_D16] = 42, - [CLK_TOP_USB20_192M_D32] = 43, - [CLK_TOP_APLL1] = 44, - [CLK_TOP_APLL1_D2] = 45, - [CLK_TOP_APLL1_D4] = 46, - [CLK_TOP_APLL1_D8] = 47, - [CLK_TOP_APLL2] = 48, - [CLK_TOP_APLL2_D2] = 49, - [CLK_TOP_APLL2_D4] = 50, - [CLK_TOP_APLL2_D8] = 51, - /* Fixed 26M oscillator is not available in devicetree definitions */ - [CLK_TOP_CLK26M] = 52, - [CLK_TOP_SYS_26M_D2] = 53, - [CLK_TOP_MSDCPLL] = 54, - [CLK_TOP_MSDCPLL_D2] = 55, - [CLK_TOP_DSPPLL] = 56, - [CLK_TOP_DSPPLL_D2] = 57, - [CLK_TOP_DSPPLL_D4] = 58, - [CLK_TOP_DSPPLL_D8] = 59, - [CLK_TOP_APUPLL] = 60, - [CLK_TOP_CLK26M_D52] = 61, - /* MUX */ - [CLK_TOP_AXI_SEL] = 62, - [CLK_TOP_MEM_SEL] = 63, - [CLK_TOP_MM_SEL] = 64, - [CLK_TOP_SCP_SEL] = 65, - [CLK_TOP_MFG_SEL] = 66, - [CLK_TOP_ATB_SEL] = 67, - [CLK_TOP_CAMTG_SEL] = 68, - [CLK_TOP_CAMTG1_SEL] = 69, - [CLK_TOP_UART_SEL] = 70, - [CLK_TOP_SPI_SEL] = 71, - [CLK_TOP_MSDC50_0_HC_SEL] = 72, - [CLK_TOP_MSDC2_2_HC_SEL] = 73, - [CLK_TOP_MSDC50_0_SEL] = 74, - [CLK_TOP_MSDC50_2_SEL] = 75, - [CLK_TOP_MSDC30_1_SEL] = 76, - [CLK_TOP_AUDIO_SEL] = 77, - [CLK_TOP_AUD_INTBUS_SEL] = 78, - [CLK_TOP_AUD_1_SEL] = 79, - [CLK_TOP_AUD_2_SEL] = 80, - [CLK_TOP_AUD_ENGEN1_SEL] = 81, - [CLK_TOP_AUD_ENGEN2_SEL] = 82, - [CLK_TOP_AUD_SPDIF_SEL] = 83, - [CLK_TOP_DISP_PWM_SEL] = 84, - [CLK_TOP_DXCC_SEL] = 85, - [CLK_TOP_SSUSB_SYS_SEL] = 86, - [CLK_TOP_SSUSB_XHCI_SEL] = 87, - [CLK_TOP_SPM_SEL] = 88, - [CLK_TOP_I2C_SEL] = 89, - [CLK_TOP_PWM_SEL] = 90, - [CLK_TOP_SENIF_SEL] = 91, - [CLK_TOP_AES_FDE_SEL] = 92, - [CLK_TOP_CAMTM_SEL] = 93, - [CLK_TOP_DPI0_SEL] = 94, - [CLK_TOP_DPI1_SEL] = 95, - [CLK_TOP_DSP_SEL] = 96, - [CLK_TOP_NFI2X_SEL] = 97, - [CLK_TOP_NFIECC_SEL] = 98, - [CLK_TOP_ECC_SEL] = 99, - [CLK_TOP_ETH_SEL] = 100, - [CLK_TOP_GCPU_SEL] = 101, - [CLK_TOP_GCPU_CPM_SEL] = 102, - [CLK_TOP_APU_SEL] = 103, - [CLK_TOP_APU_IF_SEL] = 104, - /* GATE */ - [CLK_TOP_AUD_I2S0_M] = 105, - [CLK_TOP_AUD_I2S1_M] = 106, - [CLK_TOP_AUD_I2S2_M] = 107, - [CLK_TOP_AUD_I2S3_M] = 108, - [CLK_TOP_AUD_TDMOUT_M] = 109, - [CLK_TOP_AUD_TDMOUT_B] = 110, - [CLK_TOP_AUD_TDMIN_M] = 111, - [CLK_TOP_AUD_TDMIN_B] = 112, - [CLK_TOP_AUD_SPDIF_M] = 113, - [CLK_TOP_USB20_48M_EN] = 114, - [CLK_TOP_UNIVPLL_48M_EN] = 115, - [CLK_TOP_LVDSTX_CLKDIG_EN] = 116, - [CLK_TOP_VPLL_DPIX_EN] = 117, - [CLK_TOP_SSUSB_TOP_CK_EN] = 118, - [CLK_TOP_SSUSB_PHY_CK_EN] = 119, - [CLK_TOP_CONN_32K] = 120, - [CLK_TOP_CONN_26M] = 121, - [CLK_TOP_DSP_32K] = 122, - [CLK_TOP_DSP_26M] = 123, -}; - #define FIXED_CLK0(_id, _rate) \ FIXED_CLK(_id, CLK_XTAL, CLK_PARENT_XTAL, _rate) @@ -222,7 +91,6 @@ static const int mt8365_topckgen_id_map[] = { FIXED_CLK(_id, CLK_TOP_CLK_NULL, CLK_PARENT_TOPCKGEN, _rate) static const struct mtk_fixed_clk top_fixed_clks[] = { - FIXED_CLK0(CLK_TOP_CLK32K, 32000), FIXED_CLK0(CLK_TOP_CLK_NULL, 0), FIXED_CLK1(CLK_TOP_I2S0_BCK, 26000000), FIXED_CLK0(CLK_TOP_DSI0_LNTC_DSICK, 75000000), @@ -256,6 +124,7 @@ static const struct mtk_fixed_factor top_divs[] = { PLL_FACTOR(CLK_TOP_SYSPLL_D7, "syspll_d7", CLK_APMIXED_MAINPLL, 1, 7), PLL_FACTOR(CLK_TOP_SYSPLL4_D2, "syspll4_d2", CLK_APMIXED_MAINPLL, 1, 14), PLL_FACTOR(CLK_TOP_SYSPLL4_D4, "syspll4_d4", CLK_APMIXED_MAINPLL, 1, 28), + PLL_FACTOR(CLK_TOP_UNIVPLL, "univpll", CLK_APMIXED_UNIVPLL, 1, 1), PLL_FACTOR(CLK_TOP_UNIVPLL_D2, "univpll_d2", CLK_APMIXED_UNIVPLL, 1, 2), PLL_FACTOR(CLK_TOP_UNIVPLL1_D2, "univpll1_d2", CLK_APMIXED_UNIVPLL, 1, 4), PLL_FACTOR(CLK_TOP_UNIVPLL1_D4, "univpll1_d4", CLK_APMIXED_UNIVPLL, 1, 8), @@ -286,7 +155,6 @@ static const struct mtk_fixed_factor top_divs[] = { PLL_FACTOR1(CLK_TOP_APLL2_D2, "apll2_d2", CLK_TOP_APLL2, 1, 2), PLL_FACTOR1(CLK_TOP_APLL2_D4, "apll2_d4", CLK_TOP_APLL2, 1, 4), PLL_FACTOR1(CLK_TOP_APLL2_D8, "apll2_d8", CLK_TOP_APLL2, 1, 8), - PLL_FACTOR2(CLK_TOP_CLK26M, "clk26m_ck", CLK_XTAL, 1, 1), PLL_FACTOR2(CLK_TOP_SYS_26M_D2, "sys_26m_d2", CLK_XTAL, 1, 2), PLL_FACTOR(CLK_TOP_MSDCPLL, "msdcpll_ck", CLK_APMIXED_MSDCPLL, 1, 1), PLL_FACTOR(CLK_TOP_MSDCPLL_D2, "msdcpll_d2", CLK_APMIXED_MSDCPLL, 1, 2), @@ -299,21 +167,21 @@ static const struct mtk_fixed_factor top_divs[] = { }; static const struct mtk_parent axi_parents[] = { - TOP_PARENT(CLK_TOP_CLK26M), + EXT_PARENT(CLK_PAD_CLK26M), TOP_PARENT(CLK_TOP_SYSPLL_D7), TOP_PARENT(CLK_TOP_SYSPLL1_D4), TOP_PARENT(CLK_TOP_SYSPLL3_D2), }; static const struct mtk_parent mem_parents[] = { - TOP_PARENT(CLK_TOP_CLK26M), + EXT_PARENT(CLK_PAD_CLK26M), TOP_PARENT(CLK_TOP_MMPLL), TOP_PARENT(CLK_TOP_SYSPLL_D3), TOP_PARENT(CLK_TOP_SYSPLL1_D2), }; static const struct mtk_parent mm_parents[] = { - TOP_PARENT(CLK_TOP_CLK26M), + EXT_PARENT(CLK_PAD_CLK26M), TOP_PARENT(CLK_TOP_MMPLL), TOP_PARENT(CLK_TOP_SYSPLL1_D2), TOP_PARENT(CLK_TOP_SYSPLL_D5), @@ -324,7 +192,7 @@ static const struct mtk_parent mm_parents[] = { }; static const struct mtk_parent scp_parents[] = { - TOP_PARENT(CLK_TOP_CLK26M), + EXT_PARENT(CLK_PAD_CLK26M), TOP_PARENT(CLK_TOP_SYSPLL4_D2), TOP_PARENT(CLK_TOP_UNIVPLL2_D2), TOP_PARENT(CLK_TOP_SYSPLL1_D2), @@ -334,20 +202,20 @@ static const struct mtk_parent scp_parents[] = { }; static const struct mtk_parent mfg_parents[] = { - TOP_PARENT(CLK_TOP_CLK26M), + EXT_PARENT(CLK_PAD_CLK26M), TOP_PARENT(CLK_TOP_MFGPLL), TOP_PARENT(CLK_TOP_SYSPLL_D3), TOP_PARENT(CLK_TOP_UNIVPLL_D3), }; static const struct mtk_parent atb_parents[] = { - TOP_PARENT(CLK_TOP_CLK26M), + EXT_PARENT(CLK_PAD_CLK26M), TOP_PARENT(CLK_TOP_SYSPLL1_D4), TOP_PARENT(CLK_TOP_SYSPLL1_D2), }; static const struct mtk_parent camtg_parents[] = { - TOP_PARENT(CLK_TOP_CLK26M), + EXT_PARENT(CLK_PAD_CLK26M), TOP_PARENT(CLK_TOP_USB20_192M_D8), TOP_PARENT(CLK_TOP_UNIVPLL2_D8), TOP_PARENT(CLK_TOP_USB20_192M_D4), @@ -357,26 +225,26 @@ static const struct mtk_parent camtg_parents[] = { }; static const struct mtk_parent uart_parents[] = { - TOP_PARENT(CLK_TOP_CLK26M), + EXT_PARENT(CLK_PAD_CLK26M), TOP_PARENT(CLK_TOP_UNIVPLL2_D8), }; static const struct mtk_parent spi_parents[] = { - TOP_PARENT(CLK_TOP_CLK26M), + EXT_PARENT(CLK_PAD_CLK26M), TOP_PARENT(CLK_TOP_UNIVPLL2_D2), TOP_PARENT(CLK_TOP_UNIVPLL2_D4), TOP_PARENT(CLK_TOP_UNIVPLL2_D8), }; static const struct mtk_parent msdc50_0_hc_parents[] = { - TOP_PARENT(CLK_TOP_CLK26M), + EXT_PARENT(CLK_PAD_CLK26M), TOP_PARENT(CLK_TOP_SYSPLL1_D2), TOP_PARENT(CLK_TOP_UNIVPLL1_D4), TOP_PARENT(CLK_TOP_SYSPLL2_D2), }; static const struct mtk_parent msdc50_0_parents[] = { - TOP_PARENT(CLK_TOP_CLK26M), + EXT_PARENT(CLK_PAD_CLK26M), TOP_PARENT(CLK_TOP_MSDCPLL), TOP_PARENT(CLK_TOP_UNIVPLL1_D2), TOP_PARENT(CLK_TOP_SYSPLL1_D2), @@ -387,7 +255,7 @@ static const struct mtk_parent msdc50_0_parents[] = { }; static const struct mtk_parent msdc50_2_parents[] = { - TOP_PARENT(CLK_TOP_CLK26M), + EXT_PARENT(CLK_PAD_CLK26M), TOP_PARENT(CLK_TOP_MSDCPLL), TOP_PARENT(CLK_TOP_UNIVPLL_D3), TOP_PARENT(CLK_TOP_UNIVPLL1_D2), @@ -398,7 +266,7 @@ static const struct mtk_parent msdc50_2_parents[] = { }; static const struct mtk_parent msdc30_1_parents[] = { - TOP_PARENT(CLK_TOP_CLK26M), + EXT_PARENT(CLK_PAD_CLK26M), TOP_PARENT(CLK_TOP_MSDCPLL_D2), TOP_PARENT(CLK_TOP_UNIVPLL2_D2), TOP_PARENT(CLK_TOP_SYSPLL2_D2), @@ -409,73 +277,73 @@ static const struct mtk_parent msdc30_1_parents[] = { }; static const struct mtk_parent audio_parents[] = { - TOP_PARENT(CLK_TOP_CLK26M), + EXT_PARENT(CLK_PAD_CLK26M), TOP_PARENT(CLK_TOP_SYSPLL3_D4), TOP_PARENT(CLK_TOP_SYSPLL4_D4), TOP_PARENT(CLK_TOP_SYSPLL1_D16), }; static const struct mtk_parent aud_intbus_parents[] = { - TOP_PARENT(CLK_TOP_CLK26M), + EXT_PARENT(CLK_PAD_CLK26M), TOP_PARENT(CLK_TOP_SYSPLL1_D4), TOP_PARENT(CLK_TOP_SYSPLL4_D2), }; static const struct mtk_parent aud_1_parents[] = { - TOP_PARENT(CLK_TOP_CLK26M), + EXT_PARENT(CLK_PAD_CLK26M), TOP_PARENT(CLK_TOP_APLL1), }; static const struct mtk_parent aud_2_parents[] = { - TOP_PARENT(CLK_TOP_CLK26M), + EXT_PARENT(CLK_PAD_CLK26M), TOP_PARENT(CLK_TOP_APLL2), }; static const struct mtk_parent aud_engen1_parents[] = { - TOP_PARENT(CLK_TOP_CLK26M), + EXT_PARENT(CLK_PAD_CLK26M), TOP_PARENT(CLK_TOP_APLL1_D2), TOP_PARENT(CLK_TOP_APLL1_D4), TOP_PARENT(CLK_TOP_APLL1_D8), }; static const struct mtk_parent aud_engen2_parents[] = { - TOP_PARENT(CLK_TOP_CLK26M), + EXT_PARENT(CLK_PAD_CLK26M), TOP_PARENT(CLK_TOP_APLL2_D2), TOP_PARENT(CLK_TOP_APLL2_D4), TOP_PARENT(CLK_TOP_APLL2_D8), }; static const struct mtk_parent aud_spdif_parents[] = { - TOP_PARENT(CLK_TOP_CLK26M), + EXT_PARENT(CLK_PAD_CLK26M), TOP_PARENT(CLK_TOP_UNIVPLL_D2), }; static const struct mtk_parent disp_pwm_parents[] = { - TOP_PARENT(CLK_TOP_CLK26M), + EXT_PARENT(CLK_PAD_CLK26M), TOP_PARENT(CLK_TOP_UNIVPLL2_D4), }; static const struct mtk_parent dxcc_parents[] = { - TOP_PARENT(CLK_TOP_CLK26M), + EXT_PARENT(CLK_PAD_CLK26M), TOP_PARENT(CLK_TOP_SYSPLL1_D2), TOP_PARENT(CLK_TOP_SYSPLL1_D4), TOP_PARENT(CLK_TOP_SYSPLL1_D8), }; static const struct mtk_parent ssusb_sys_parents[] = { - TOP_PARENT(CLK_TOP_CLK26M), + EXT_PARENT(CLK_PAD_CLK26M), TOP_PARENT(CLK_TOP_UNIVPLL3_D4), TOP_PARENT(CLK_TOP_UNIVPLL2_D4), TOP_PARENT(CLK_TOP_UNIVPLL3_D2), }; static const struct mtk_parent spm_parents[] = { - TOP_PARENT(CLK_TOP_CLK26M), + EXT_PARENT(CLK_PAD_CLK26M), TOP_PARENT(CLK_TOP_SYSPLL1_D8), }; static const struct mtk_parent i2c_parents[] = { - TOP_PARENT(CLK_TOP_CLK26M), + EXT_PARENT(CLK_PAD_CLK26M), TOP_PARENT(CLK_TOP_UNIVPLL3_D4), TOP_PARENT(CLK_TOP_UNIVPLL3_D2), TOP_PARENT(CLK_TOP_SYSPLL1_D8), @@ -483,20 +351,20 @@ static const struct mtk_parent i2c_parents[] = { }; static const struct mtk_parent pwm_parents[] = { - TOP_PARENT(CLK_TOP_CLK26M), + EXT_PARENT(CLK_PAD_CLK26M), TOP_PARENT(CLK_TOP_UNIVPLL3_D4), TOP_PARENT(CLK_TOP_SYSPLL1_D8), }; static const struct mtk_parent senif_parents[] = { - TOP_PARENT(CLK_TOP_CLK26M), + EXT_PARENT(CLK_PAD_CLK26M), TOP_PARENT(CLK_TOP_UNIVPLL1_D4), TOP_PARENT(CLK_TOP_UNIVPLL1_D2), TOP_PARENT(CLK_TOP_UNIVPLL2_D2), }; static const struct mtk_parent aes_fde_parents[] = { - TOP_PARENT(CLK_TOP_CLK26M), + EXT_PARENT(CLK_PAD_CLK26M), TOP_PARENT(CLK_TOP_MSDCPLL), TOP_PARENT(CLK_TOP_UNIVPLL_D3), TOP_PARENT(CLK_TOP_UNIVPLL2_D2), @@ -505,7 +373,7 @@ static const struct mtk_parent aes_fde_parents[] = { }; static const struct mtk_parent dpi0_parents[] = { - TOP_PARENT(CLK_TOP_CLK26M), + EXT_PARENT(CLK_PAD_CLK26M), TOP_PARENT(CLK_TOP_LVDSPLL_D2), TOP_PARENT(CLK_TOP_LVDSPLL_D4), TOP_PARENT(CLK_TOP_LVDSPLL_D8), @@ -513,7 +381,7 @@ static const struct mtk_parent dpi0_parents[] = { }; static const struct mtk_parent dsp_parents[] = { - TOP_PARENT(CLK_TOP_CLK26M), + EXT_PARENT(CLK_PAD_CLK26M), TOP_PARENT(CLK_TOP_SYS_26M_D2), TOP_PARENT(CLK_TOP_DSPPLL), TOP_PARENT(CLK_TOP_DSPPLL_D2), @@ -522,7 +390,7 @@ static const struct mtk_parent dsp_parents[] = { }; static const struct mtk_parent nfi2x_parents[] = { - TOP_PARENT(CLK_TOP_CLK26M), + EXT_PARENT(CLK_PAD_CLK26M), TOP_PARENT(CLK_TOP_SYSPLL2_D2), TOP_PARENT(CLK_TOP_SYSPLL_D7), TOP_PARENT(CLK_TOP_SYSPLL_D3), @@ -533,7 +401,7 @@ static const struct mtk_parent nfi2x_parents[] = { }; static const struct mtk_parent nfiecc_parents[] = { - TOP_PARENT(CLK_TOP_CLK26M), + EXT_PARENT(CLK_PAD_CLK26M), TOP_PARENT(CLK_TOP_SYSPLL4_D2), TOP_PARENT(CLK_TOP_UNIVPLL2_D4), TOP_PARENT(CLK_TOP_SYSPLL_D7), @@ -544,7 +412,7 @@ static const struct mtk_parent nfiecc_parents[] = { }; static const struct mtk_parent ecc_parents[] = { - TOP_PARENT(CLK_TOP_CLK26M), + EXT_PARENT(CLK_PAD_CLK26M), TOP_PARENT(CLK_TOP_UNIVPLL2_D2), TOP_PARENT(CLK_TOP_UNIVPLL1_D2), TOP_PARENT(CLK_TOP_UNIVPLL_D3), @@ -552,7 +420,7 @@ static const struct mtk_parent ecc_parents[] = { }; static const struct mtk_parent eth_parents[] = { - TOP_PARENT(CLK_TOP_CLK26M), + EXT_PARENT(CLK_PAD_CLK26M), TOP_PARENT(CLK_TOP_UNIVPLL2_D8), TOP_PARENT(CLK_TOP_SYSPLL4_D4), TOP_PARENT(CLK_TOP_SYSPLL1_D8), @@ -560,7 +428,7 @@ static const struct mtk_parent eth_parents[] = { }; static const struct mtk_parent gcpu_parents[] = { - TOP_PARENT(CLK_TOP_CLK26M), + EXT_PARENT(CLK_PAD_CLK26M), TOP_PARENT(CLK_TOP_UNIVPLL_D3), TOP_PARENT(CLK_TOP_UNIVPLL2_D2), TOP_PARENT(CLK_TOP_SYSPLL_D3), @@ -568,13 +436,13 @@ static const struct mtk_parent gcpu_parents[] = { }; static const struct mtk_parent gcpu_cpm_parents[] = { - TOP_PARENT(CLK_TOP_CLK26M), + EXT_PARENT(CLK_PAD_CLK26M), TOP_PARENT(CLK_TOP_UNIVPLL2_D2), TOP_PARENT(CLK_TOP_SYSPLL2_D2), }; static const struct mtk_parent apu_parents[] = { - TOP_PARENT(CLK_TOP_CLK26M), + EXT_PARENT(CLK_PAD_CLK26M), TOP_PARENT(CLK_TOP_UNIVPLL_D2), TOP_PARENT(CLK_TOP_APUPLL), TOP_PARENT(CLK_TOP_MMPLL), @@ -684,6 +552,14 @@ static const struct mtk_gate_regs top2_cg_regs = { .flags = CLK_GATE_NO_SETCLR_INV | CLK_PARENT_TOPCKGEN, \ } +#define GATE_EXT(_id, _parent, _shift) { \ + .id = _id, \ + .parent = _parent, \ + .regs = &top0_cg_regs, \ + .shift = _shift, \ + .flags = CLK_GATE_NO_SETCLR | CLK_PARENT_EXT, \ + } + static const struct mtk_gate top_clk_gates[] = { GATE_TOP2(CLK_TOP_AUD_I2S0_M, CLK_TOP_APLL12_CK_DIV0, 0), GATE_TOP2(CLK_TOP_AUD_I2S1_M, CLK_TOP_APLL12_CK_DIV1, 1), @@ -700,19 +576,19 @@ static const struct mtk_gate top_clk_gates[] = { GATE_TOP1(CLK_TOP_VPLL_DPIX_EN, CLK_TOP_VPLL_DPIX, 21), GATE_TOP1(CLK_TOP_SSUSB_TOP_CK_EN, CLK_TOP_CLK_NULL, 22), GATE_TOP1(CLK_TOP_SSUSB_PHY_CK_EN, CLK_TOP_CLK_NULL, 23), - GATE_TOP0(CLK_TOP_CONN_32K, CLK_TOP_CLK32K, 10), - GATE_TOP0(CLK_TOP_CONN_26M, CLK_TOP_CLK26M, 11), - GATE_TOP0(CLK_TOP_DSP_32K, CLK_TOP_CLK32K, 16), - GATE_TOP0(CLK_TOP_DSP_26M, CLK_TOP_CLK26M, 17), + GATE_EXT(CLK_TOP_CONN_32K, CLK_PAD_CLK32K, 10), + GATE_EXT(CLK_TOP_CONN_26M, CLK_PAD_CLK26M, 11), + GATE_EXT(CLK_TOP_DSP_32K, CLK_PAD_CLK32K, 16), + GATE_EXT(CLK_TOP_DSP_26M, CLK_PAD_CLK26M, 17), }; static const struct mtk_clk_tree mt8365_topckgen_tree = { .xtal_rate = 26 * MHZ, - .id_offs_map = mt8365_topckgen_id_map, - .id_offs_map_size = ARRAY_SIZE(mt8365_topckgen_id_map), - .fdivs_offs = mt8365_topckgen_id_map[CLK_TOP_MFGPLL], - .muxes_offs = mt8365_topckgen_id_map[CLK_TOP_AXI_SEL], - .gates_offs = mt8365_topckgen_id_map[CLK_TOP_AUD_I2S0_M], + .ext_clk_rates = ext_clock_rates, + .num_ext_clks = ARRAY_SIZE(ext_clock_rates), + .fdivs_offs = CLK_TOP_MFGPLL, + .muxes_offs = CLK_TOP_AXI_SEL, + .gates_offs = CLK_TOP_AUD_I2S0_M, .fclks = top_fixed_clks, .fdivs = top_divs, .muxes = top_muxes, @@ -778,12 +654,33 @@ static const struct mtk_gate_regs ifr6_cg_regs = { #define GATE_IFR6(_id, _parent, _shift) \ GATE_IFRX(_id, _parent, _shift, &ifr6_cg_regs) +#define GATE_IFRX_EXT(_id, _parent, _shift, _regs) \ + { \ + .id = _id, \ + .parent = _parent, \ + .regs = _regs, \ + .shift = _shift, \ + .flags = CLK_GATE_SETCLR | CLK_PARENT_EXT, \ + } + +#define GATE_IFR2_EXT(_id, _parent, _shift) \ + GATE_IFRX_EXT(_id, _parent, _shift, &ifr2_cg_regs) + +#define GATE_IFR3_EXT(_id, _parent, _shift) \ + GATE_IFRX_EXT(_id, _parent, _shift, &ifr3_cg_regs) + +#define GATE_IFR4_EXT(_id, _parent, _shift) \ + GATE_IFRX_EXT(_id, _parent, _shift, &ifr4_cg_regs) + +#define GATE_IFR5_EXT(_id, _parent, _shift) \ + GATE_IFRX_EXT(_id, _parent, _shift, &ifr5_cg_regs) + static const struct mtk_gate ifr_clks[] = { /* IFR2 */ - GATE_IFR2(CLK_IFR_PMIC_TMR, CLK_TOP_CLK26M, 0), - GATE_IFR2(CLK_IFR_PMIC_AP, CLK_TOP_CLK26M, 1), - GATE_IFR2(CLK_IFR_PMIC_MD, CLK_TOP_CLK26M, 2), - GATE_IFR2(CLK_IFR_PMIC_CONN, CLK_TOP_CLK26M, 3), + GATE_IFR2_EXT(CLK_IFR_PMIC_TMR, CLK_PAD_CLK26M, 0), + GATE_IFR2_EXT(CLK_IFR_PMIC_AP, CLK_PAD_CLK26M, 1), + GATE_IFR2_EXT(CLK_IFR_PMIC_MD, CLK_PAD_CLK26M, 2), + GATE_IFR2_EXT(CLK_IFR_PMIC_CONN, CLK_PAD_CLK26M, 3), GATE_IFR2(CLK_IFR_ICUSB, CLK_TOP_AXI_SEL, 8), GATE_IFR2(CLK_IFR_GCE, CLK_TOP_AXI_SEL, 9), GATE_IFR2(CLK_IFR_THERM, CLK_TOP_AXI_SEL, 10), @@ -798,7 +695,7 @@ static const struct mtk_gate ifr_clks[] = { GATE_IFR2(CLK_IFR_UART1, CLK_TOP_UART_SEL, 23), GATE_IFR2(CLK_IFR_UART2, CLK_TOP_UART_SEL, 24), GATE_IFR2(CLK_IFR_DSP_UART, CLK_TOP_UART_SEL, 26), - GATE_IFR2(CLK_IFR_GCE_26M, CLK_TOP_CLK26M, 27), + GATE_IFR2_EXT(CLK_IFR_GCE_26M, CLK_PAD_CLK26M, 27), GATE_IFR2(CLK_IFR_CQ_DMA_FPC, CLK_TOP_AXI_SEL, 28), GATE_IFR2(CLK_IFR_BTIF, CLK_TOP_AXI_SEL, 31), /* IFR3 */ @@ -806,19 +703,19 @@ static const struct mtk_gate ifr_clks[] = { GATE_IFR3(CLK_IFR_MSDC0_HCLK, CLK_TOP_AXI_SEL, 2), GATE_IFR3(CLK_IFR_MSDC2_HCLK, CLK_TOP_AXI_SEL, 3), GATE_IFR3(CLK_IFR_MSDC1_HCLK, CLK_TOP_AXI_SEL, 4), - GATE_IFR3(CLK_IFR_DVFSRC, CLK_TOP_CLK26M, 7), + GATE_IFR3_EXT(CLK_IFR_DVFSRC, CLK_PAD_CLK26M, 7), GATE_IFR3(CLK_IFR_GCPU, CLK_TOP_AXI_SEL, 8), GATE_IFR3(CLK_IFR_TRNG, CLK_TOP_AXI_SEL, 9), - GATE_IFR3(CLK_IFR_AUXADC, CLK_TOP_CLK26M, 10), + GATE_IFR3_EXT(CLK_IFR_AUXADC, CLK_PAD_CLK26M, 10), GATE_IFR3(CLK_IFR_CPUM, CLK_TOP_AXI_SEL, 11), - GATE_IFR3(CLK_IFR_AUXADC_MD, CLK_TOP_CLK26M, 14), + GATE_IFR3_EXT(CLK_IFR_AUXADC_MD, CLK_PAD_CLK26M, 14), GATE_IFR3(CLK_IFR_AP_DMA, CLK_TOP_AXI_SEL, 18), GATE_IFR3(CLK_IFR_DEBUGSYS, CLK_TOP_AXI_SEL, 24), GATE_IFR3(CLK_IFR_AUDIO, CLK_TOP_AXI_SEL, 25), /* IFR4 */ GATE_IFR4(CLK_IFR_PWM_FBCLK6, CLK_TOP_PWM_SEL, 0), GATE_IFR4(CLK_IFR_DISP_PWM, CLK_TOP_DISP_PWM_SEL, 2), - GATE_IFR4(CLK_IFR_AUD_26M_BK, CLK_TOP_CLK26M, 4), + GATE_IFR4_EXT(CLK_IFR_AUD_26M_BK, CLK_PAD_CLK26M, 4), GATE_IFR4(CLK_IFR_CQ_DMA, CLK_TOP_AXI_SEL, 27), /* IFR5 */ GATE_IFR5(CLK_IFR_MSDC0_SF, CLK_TOP_MSDC50_0_SEL, 0), @@ -829,12 +726,12 @@ static const struct mtk_gate ifr_clks[] = { GATE_IFR5(CLK_IFR_MSDC0_SRC, CLK_TOP_MSDC50_0_SEL, 9), GATE_IFR5(CLK_IFR_MSDC1_SRC, CLK_TOP_MSDC30_1_SEL, 10), GATE_IFR5(CLK_IFR_MSDC2_SRC, CLK_TOP_MSDC50_2_SEL, 11), - GATE_IFR5(CLK_IFR_PWRAP_TMR, CLK_TOP_CLK26M, 12), - GATE_IFR5(CLK_IFR_PWRAP_SPI, CLK_TOP_CLK26M, 13), - GATE_IFR5(CLK_IFR_PWRAP_SYS, CLK_TOP_CLK26M, 14), + GATE_IFR5_EXT(CLK_IFR_PWRAP_TMR, CLK_PAD_CLK26M, 12), + GATE_IFR5_EXT(CLK_IFR_PWRAP_SPI, CLK_PAD_CLK26M, 13), + GATE_IFR5_EXT(CLK_IFR_PWRAP_SYS, CLK_PAD_CLK26M, 14), GATE_IFR5(CLK_IFR_MCU_PM_BK, CLK_TOP_AXI_SEL, 16), - GATE_IFR5(CLK_IFR_IRRX_26M, CLK_TOP_CLK26M, 22), - GATE_IFR5(CLK_IFR_IRRX_32K, CLK_TOP_CLK32K, 23), + GATE_IFR5_EXT(CLK_IFR_IRRX_26M, CLK_PAD_CLK26M, 22), + GATE_IFR5_EXT(CLK_IFR_IRRX_32K, CLK_PAD_CLK32K, 23), GATE_IFR5(CLK_IFR_I2C0_AXI, CLK_TOP_I2C_SEL, 24), GATE_IFR5(CLK_IFR_I2C1_AXI, CLK_TOP_I2C_SEL, 25), GATE_IFR5(CLK_IFR_I2C2_AXI, CLK_TOP_I2C_SEL, 26), @@ -859,6 +756,8 @@ static const struct mtk_gate ifr_clks[] = { static const struct mtk_clk_tree mt8365_infracfg_tree = { .xtal_rate = 26 * MHZ, + .ext_clk_rates = ext_clock_rates, + .num_ext_clks = ARRAY_SIZE(ext_clock_rates), }; static int mt8365_apmixedsys_probe(struct udevice *dev) -- cgit v1.3.1 From f7d48558cf1b952236ed3e423d8cc25e498a40f2 Mon Sep 17 00:00:00 2001 From: David Lechner Date: Mon, 9 Mar 2026 17:51:10 -0500 Subject: clk: mediatek: mt8188: use ext_clock_rates Convert the mt8188 clock driver to use ext_clock_rates. Now that we have the ext_clock_rates feature and also mux clock parents have been converted to struct mtk_parent, we can remove the hack of adding "missing" topckgen clocks. Instead we can use the proper parents. The topckgen ID map is still needed though because the upstream dt-bindings didn't use the conventional number ordering by clock type for these. Reviewed-by: Julien Stephan Link: https://patch.msgid.link/20260309-clk-mtk-mt8188-drop-extra-top-clocks-v1-1-6ee4743a8465@baylibre.com Signed-off-by: David Lechner --- drivers/clk/mediatek/clk-mt8188.c | 741 ++++++++++++++++++++------------------ 1 file changed, 399 insertions(+), 342 deletions(-) diff --git a/drivers/clk/mediatek/clk-mt8188.c b/drivers/clk/mediatek/clk-mt8188.c index 706390b6c6c..e4297c92bd9 100644 --- a/drivers/clk/mediatek/clk-mt8188.c +++ b/drivers/clk/mediatek/clk-mt8188.c @@ -19,14 +19,17 @@ #define MT8188_PLL_FMAX (3800UL * MHZ) #define MT8188_PLL_FMIN (1500UL * MHZ) -/* Missing topckgen clocks definition in dt-bindings */ -#define CLK_TOP_ADSPPLL CLK_TOP_NR_CLK -#define CLK_TOP_CLK13M CLK_TOP_NR_CLK + 1 -#define CLK_TOP_CLK26M CLK_TOP_NR_CLK + 2 -#define CLK_TOP_CLK32K CLK_TOP_NR_CLK + 3 -#define CLK_TOP_IMGPLL CLK_TOP_NR_CLK + 4 -#define CLK_TOP_MSDCPLL CLK_TOP_NR_CLK + 5 -#define CLK_TOP_FULL_NR_CLK CLK_TOP_NR_CLK + 6 +enum { + CLK_PAD_CLK32K, + CLK_PAD_CLK26M, + CLK_PAD_CLK13M, +}; + +static const ulong ext_clock_rates[] = { + [CLK_PAD_CLK32K] = 32000, + [CLK_PAD_CLK26M] = 26 * MHZ, + [CLK_PAD_CLK13M] = 13 * MHZ, +}; /* apmixedsys */ #define PLL(_id, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, _pd_reg, \ @@ -83,6 +86,8 @@ static const struct mtk_pll_data apmixed_plls[] = { static const struct mtk_clk_tree mt8188_apmixedsys_clk_tree = { .xtal_rate = 26 * MHZ, .xtal2_rate = 26 * MHZ, + .ext_clk_rates = ext_clock_rates, + .num_ext_clks = ARRAY_SIZE(ext_clock_rates), .plls = apmixed_plls, .num_plls = ARRAY_SIZE(apmixed_plls), }; @@ -97,9 +102,6 @@ static const struct mtk_fixed_clk top_fixed_clks[] = { FIXED_CLK0(CLK_TOP_466M_FMEM, 533000000), FIXED_CLK0(CLK_TOP_PEXTP_PIPE, 250000000), FIXED_CLK0(CLK_TOP_DSI_PHY, 500000000), - FIXED_CLK0(CLK_TOP_CLK13M, 13000000), - FIXED_CLK0(CLK_TOP_CLK26M, 26000000), - FIXED_CLK0(CLK_TOP_CLK32K, 32000), }; #define FACTOR0(_id, _parent, _mult, _div) \ @@ -172,7 +174,6 @@ static const struct mtk_fixed_factor top_fixed_divs[] = { FACTOR0(CLK_TOP_TVDPLL2_D4, CLK_APMIXED_TVDPLL2, 1, 4), FACTOR0(CLK_TOP_TVDPLL2_D8, CLK_APMIXED_TVDPLL2, 1, 8), FACTOR0(CLK_TOP_TVDPLL2_D16, CLK_APMIXED_TVDPLL2, 1, 16), - FACTOR0(CLK_TOP_MSDCPLL, CLK_APMIXED_MSDCPLL, 1, 1), FACTOR0(CLK_TOP_MSDCPLL_D2, CLK_APMIXED_MSDCPLL, 1, 2), FACTOR0(CLK_TOP_MSDCPLL_D16, CLK_APMIXED_MSDCPLL, 1, 16), FACTOR0(CLK_TOP_ETHPLL_D2, CLK_APMIXED_ETHPLL, 1, 2), @@ -191,7 +192,7 @@ static const struct mtk_fixed_factor top_fixed_divs[] = { }; static const struct mtk_parent axi_parents[] = { - TOP_PARENT(CLK_TOP_CLK26M), + EXT_PARENT(CLK_PAD_CLK26M), TOP_PARENT(CLK_TOP_MAINPLL_D4_D4), TOP_PARENT(CLK_TOP_MAINPLL_D7_D2), TOP_PARENT(CLK_TOP_MAINPLL_D4_D2), @@ -201,14 +202,14 @@ static const struct mtk_parent axi_parents[] = { }; static const struct mtk_parent spm_parents[] = { - TOP_PARENT(CLK_TOP_CLK26M), + EXT_PARENT(CLK_PAD_CLK26M), TOP_PARENT(CLK_TOP_ULPOSC1_D10), TOP_PARENT(CLK_TOP_MAINPLL_D7_D4), - TOP_PARENT(CLK_TOP_CLK32K), + EXT_PARENT(CLK_PAD_CLK32K), }; static const struct mtk_parent scp_parents[] = { - TOP_PARENT(CLK_TOP_CLK26M), + EXT_PARENT(CLK_PAD_CLK26M), TOP_PARENT(CLK_TOP_UNIVPLL_D4), TOP_PARENT(CLK_TOP_MAINPLL_D6), TOP_PARENT(CLK_TOP_UNIVPLL_D6), @@ -219,7 +220,7 @@ static const struct mtk_parent scp_parents[] = { }; static const struct mtk_parent bus_aximem_parents[] = { - TOP_PARENT(CLK_TOP_CLK26M), + EXT_PARENT(CLK_PAD_CLK26M), TOP_PARENT(CLK_TOP_MAINPLL_D7_D2), TOP_PARENT(CLK_TOP_MAINPLL_D4_D2), TOP_PARENT(CLK_TOP_MAINPLL_D5_D2), @@ -227,7 +228,7 @@ static const struct mtk_parent bus_aximem_parents[] = { }; static const struct mtk_parent vpp_parents[] = { - TOP_PARENT(CLK_TOP_CLK26M), + EXT_PARENT(CLK_PAD_CLK26M), TOP_PARENT(CLK_TOP_UNIVPLL_D6_D2), TOP_PARENT(CLK_TOP_MAINPLL_D5_D2), TOP_PARENT(CLK_TOP_MMPLL_D6_D2), @@ -245,7 +246,7 @@ static const struct mtk_parent vpp_parents[] = { }; static const struct mtk_parent ethdr_parents[] = { - TOP_PARENT(CLK_TOP_CLK26M), + EXT_PARENT(CLK_PAD_CLK26M), TOP_PARENT(CLK_TOP_UNIVPLL_D6_D2), TOP_PARENT(CLK_TOP_MAINPLL_D5_D2), TOP_PARENT(CLK_TOP_MMPLL_D6_D2), @@ -263,8 +264,8 @@ static const struct mtk_parent ethdr_parents[] = { }; static const struct mtk_parent ipe_parents[] = { - TOP_PARENT(CLK_TOP_CLK26M), - TOP_PARENT(CLK_TOP_IMGPLL), + EXT_PARENT(CLK_PAD_CLK26M), + APMIXED_PARENT(CLK_APMIXED_IMGPLL), TOP_PARENT(CLK_TOP_MAINPLL_D4), TOP_PARENT(CLK_TOP_MMPLL_D6), TOP_PARENT(CLK_TOP_UNIVPLL_D6), @@ -278,7 +279,7 @@ static const struct mtk_parent ipe_parents[] = { }; static const struct mtk_parent cam_parents[] = { - TOP_PARENT(CLK_TOP_CLK26M), + EXT_PARENT(CLK_PAD_CLK26M), TOP_PARENT(CLK_TOP_TVDPLL1), TOP_PARENT(CLK_TOP_MAINPLL_D4), TOP_PARENT(CLK_TOP_MMPLL_D4), @@ -288,11 +289,11 @@ static const struct mtk_parent cam_parents[] = { TOP_PARENT(CLK_TOP_MMPLL_D7), TOP_PARENT(CLK_TOP_UNIVPLL_D4_D2), TOP_PARENT(CLK_TOP_MAINPLL_D4_D2), - TOP_PARENT(CLK_TOP_IMGPLL), + APMIXED_PARENT(CLK_APMIXED_IMGPLL), }; static const struct mtk_parent ccu_parents[] = { - TOP_PARENT(CLK_TOP_CLK26M), + EXT_PARENT(CLK_PAD_CLK26M), TOP_PARENT(CLK_TOP_UNIVPLL_D6), TOP_PARENT(CLK_TOP_MAINPLL_D4_D2), TOP_PARENT(CLK_TOP_MAINPLL_D4), @@ -305,7 +306,7 @@ static const struct mtk_parent ccu_parents[] = { }; static const struct mtk_parent ccu_ahb_parents[] = { - TOP_PARENT(CLK_TOP_CLK26M), + EXT_PARENT(CLK_PAD_CLK26M), TOP_PARENT(CLK_TOP_UNIVPLL_D6), TOP_PARENT(CLK_TOP_MAINPLL_D4_D2), TOP_PARENT(CLK_TOP_MAINPLL_D4), @@ -318,8 +319,8 @@ static const struct mtk_parent ccu_ahb_parents[] = { }; static const struct mtk_parent img_parents[] = { - TOP_PARENT(CLK_TOP_CLK26M), - TOP_PARENT(CLK_TOP_IMGPLL), + EXT_PARENT(CLK_PAD_CLK26M), + APMIXED_PARENT(CLK_APMIXED_IMGPLL), TOP_PARENT(CLK_TOP_UNIVPLL_D4), TOP_PARENT(CLK_TOP_MAINPLL_D4), TOP_PARENT(CLK_TOP_UNIVPLL_D5), @@ -334,14 +335,14 @@ static const struct mtk_parent img_parents[] = { }; static const struct mtk_parent camtm_parents[] = { - TOP_PARENT(CLK_TOP_CLK26M), + EXT_PARENT(CLK_PAD_CLK26M), TOP_PARENT(CLK_TOP_UNIVPLL_D4_D4), TOP_PARENT(CLK_TOP_UNIVPLL_D6_D2), TOP_PARENT(CLK_TOP_UNIVPLL_D6_D4), }; static const struct mtk_parent dsp_parents[] = { - TOP_PARENT(CLK_TOP_CLK26M), + EXT_PARENT(CLK_PAD_CLK26M), TOP_PARENT(CLK_TOP_UNIVPLL_D6_D2), TOP_PARENT(CLK_TOP_UNIVPLL_D4_D2), TOP_PARENT(CLK_TOP_UNIVPLL_D5), @@ -352,7 +353,7 @@ static const struct mtk_parent dsp_parents[] = { }; static const struct mtk_parent dsp1_parents[] = { - TOP_PARENT(CLK_TOP_CLK26M), + EXT_PARENT(CLK_PAD_CLK26M), TOP_PARENT(CLK_TOP_UNIVPLL_D6_D2), TOP_PARENT(CLK_TOP_MAINPLL_D4_D2), TOP_PARENT(CLK_TOP_UNIVPLL_D5), @@ -363,7 +364,7 @@ static const struct mtk_parent dsp1_parents[] = { }; static const struct mtk_parent dsp2_parents[] = { - TOP_PARENT(CLK_TOP_CLK26M), + EXT_PARENT(CLK_PAD_CLK26M), TOP_PARENT(CLK_TOP_UNIVPLL_D6_D2), TOP_PARENT(CLK_TOP_MAINPLL_D4_D2), TOP_PARENT(CLK_TOP_UNIVPLL_D5), @@ -374,7 +375,7 @@ static const struct mtk_parent dsp2_parents[] = { }; static const struct mtk_parent dsp3_parents[] = { - TOP_PARENT(CLK_TOP_CLK26M), + EXT_PARENT(CLK_PAD_CLK26M), TOP_PARENT(CLK_TOP_UNIVPLL_D6_D2), TOP_PARENT(CLK_TOP_MAINPLL_D4_D2), TOP_PARENT(CLK_TOP_UNIVPLL_D5), @@ -385,7 +386,7 @@ static const struct mtk_parent dsp3_parents[] = { }; static const struct mtk_parent dsp4_parents[] = { - TOP_PARENT(CLK_TOP_CLK26M), + EXT_PARENT(CLK_PAD_CLK26M), TOP_PARENT(CLK_TOP_UNIVPLL_D6_D2), TOP_PARENT(CLK_TOP_UNIVPLL_D4_D2), TOP_PARENT(CLK_TOP_MAINPLL_D4), @@ -396,7 +397,7 @@ static const struct mtk_parent dsp4_parents[] = { }; static const struct mtk_parent dsp5_parents[] = { - TOP_PARENT(CLK_TOP_CLK26M), + EXT_PARENT(CLK_PAD_CLK26M), TOP_PARENT(CLK_TOP_UNIVPLL_D6_D2), TOP_PARENT(CLK_TOP_UNIVPLL_D4_D2), TOP_PARENT(CLK_TOP_MAINPLL_D4), @@ -407,7 +408,7 @@ static const struct mtk_parent dsp5_parents[] = { }; static const struct mtk_parent dsp6_parents[] = { - TOP_PARENT(CLK_TOP_CLK26M), + EXT_PARENT(CLK_PAD_CLK26M), TOP_PARENT(CLK_TOP_UNIVPLL_D6_D2), TOP_PARENT(CLK_TOP_UNIVPLL_D4_D2), TOP_PARENT(CLK_TOP_MAINPLL_D4), @@ -418,7 +419,7 @@ static const struct mtk_parent dsp6_parents[] = { }; static const struct mtk_parent dsp7_parents[] = { - TOP_PARENT(CLK_TOP_CLK26M), + EXT_PARENT(CLK_PAD_CLK26M), TOP_PARENT(CLK_TOP_UNIVPLL_D6_D2), TOP_PARENT(CLK_TOP_UNIVPLL_D4_D2), TOP_PARENT(CLK_TOP_UNIVPLL_D5), @@ -429,52 +430,52 @@ static const struct mtk_parent dsp7_parents[] = { }; static const struct mtk_parent mfg_core_tmp_parents[] = { - TOP_PARENT(CLK_TOP_CLK26M), + EXT_PARENT(CLK_PAD_CLK26M), TOP_PARENT(CLK_TOP_MAINPLL_D5_D2), TOP_PARENT(CLK_TOP_UNIVPLL_D6), TOP_PARENT(CLK_TOP_UNIVPLL_D7), }; static const struct mtk_parent camtg_parents[] = { - TOP_PARENT(CLK_TOP_CLK26M), + EXT_PARENT(CLK_PAD_CLK26M), TOP_PARENT(CLK_TOP_UNIVPLL_192M_D8), TOP_PARENT(CLK_TOP_UNIVPLL_D6_D8), TOP_PARENT(CLK_TOP_UNIVPLL_192M_D4), TOP_PARENT(CLK_TOP_UNIVPLL_192M_D10), - TOP_PARENT(CLK_TOP_CLK13M), + EXT_PARENT(CLK_PAD_CLK13M), TOP_PARENT(CLK_TOP_UNIVPLL_192M_D16), TOP_PARENT(CLK_TOP_UNIVPLL_192M_D32), }; static const struct mtk_parent camtg2_parents[] = { - TOP_PARENT(CLK_TOP_CLK26M), + EXT_PARENT(CLK_PAD_CLK26M), TOP_PARENT(CLK_TOP_UNIVPLL_192M_D8), TOP_PARENT(CLK_TOP_UNIVPLL_D6_D8), TOP_PARENT(CLK_TOP_UNIVPLL_192M_D4), TOP_PARENT(CLK_TOP_UNIVPLL_192M_D10), - TOP_PARENT(CLK_TOP_CLK13M), + EXT_PARENT(CLK_PAD_CLK13M), TOP_PARENT(CLK_TOP_UNIVPLL_192M_D16), TOP_PARENT(CLK_TOP_UNIVPLL_192M_D32), }; static const struct mtk_parent camtg3_parents[] = { - TOP_PARENT(CLK_TOP_CLK26M), + EXT_PARENT(CLK_PAD_CLK26M), TOP_PARENT(CLK_TOP_UNIVPLL_192M_D8), TOP_PARENT(CLK_TOP_UNIVPLL_D6_D8), TOP_PARENT(CLK_TOP_UNIVPLL_192M_D4), TOP_PARENT(CLK_TOP_UNIVPLL_192M_D10), - TOP_PARENT(CLK_TOP_CLK13M), + EXT_PARENT(CLK_PAD_CLK13M), TOP_PARENT(CLK_TOP_UNIVPLL_192M_D16), TOP_PARENT(CLK_TOP_UNIVPLL_192M_D32), }; static const struct mtk_parent uart_parents[] = { - TOP_PARENT(CLK_TOP_CLK26M), + EXT_PARENT(CLK_PAD_CLK26M), TOP_PARENT(CLK_TOP_UNIVPLL_D6_D8), }; static const struct mtk_parent spi_parents[] = { - TOP_PARENT(CLK_TOP_CLK26M), + EXT_PARENT(CLK_PAD_CLK26M), TOP_PARENT(CLK_TOP_MAINPLL_D5_D4), TOP_PARENT(CLK_TOP_MAINPLL_D6_D4), TOP_PARENT(CLK_TOP_UNIVPLL_D6_D4), @@ -485,14 +486,14 @@ static const struct mtk_parent spi_parents[] = { }; static const struct mtk_parent msdc5hclk_parents[] = { - TOP_PARENT(CLK_TOP_CLK26M), + EXT_PARENT(CLK_PAD_CLK26M), TOP_PARENT(CLK_TOP_MAINPLL_D4_D2), TOP_PARENT(CLK_TOP_MAINPLL_D6_D2), }; static const struct mtk_parent msdc50_0_parents[] = { - TOP_PARENT(CLK_TOP_CLK26M), - TOP_PARENT(CLK_TOP_MSDCPLL), + EXT_PARENT(CLK_PAD_CLK26M), + APMIXED_PARENT(CLK_APMIXED_MSDCPLL), TOP_PARENT(CLK_TOP_MSDCPLL_D2), TOP_PARENT(CLK_TOP_UNIVPLL_D4_D4), TOP_PARENT(CLK_TOP_MAINPLL_D6_D2), @@ -500,7 +501,7 @@ static const struct mtk_parent msdc50_0_parents[] = { }; static const struct mtk_parent msdc30_1_parents[] = { - TOP_PARENT(CLK_TOP_CLK26M), + EXT_PARENT(CLK_PAD_CLK26M), TOP_PARENT(CLK_TOP_UNIVPLL_D6_D2), TOP_PARENT(CLK_TOP_MAINPLL_D6_D2), TOP_PARENT(CLK_TOP_MAINPLL_D7_D2), @@ -508,7 +509,7 @@ static const struct mtk_parent msdc30_1_parents[] = { }; static const struct mtk_parent msdc30_2_parents[] = { - TOP_PARENT(CLK_TOP_CLK26M), + EXT_PARENT(CLK_PAD_CLK26M), TOP_PARENT(CLK_TOP_UNIVPLL_D6_D2), TOP_PARENT(CLK_TOP_MAINPLL_D6_D2), TOP_PARENT(CLK_TOP_MAINPLL_D7_D2), @@ -516,27 +517,27 @@ static const struct mtk_parent msdc30_2_parents[] = { }; static const struct mtk_parent intdir_parents[] = { - TOP_PARENT(CLK_TOP_CLK26M), + EXT_PARENT(CLK_PAD_CLK26M), TOP_PARENT(CLK_TOP_UNIVPLL_D6), TOP_PARENT(CLK_TOP_MAINPLL_D4), TOP_PARENT(CLK_TOP_UNIVPLL_D4), }; static const struct mtk_parent aud_intbus_parents[] = { - TOP_PARENT(CLK_TOP_CLK26M), + EXT_PARENT(CLK_PAD_CLK26M), TOP_PARENT(CLK_TOP_MAINPLL_D4_D4), TOP_PARENT(CLK_TOP_MAINPLL_D7_D4), }; static const struct mtk_parent audio_h_parents[] = { - TOP_PARENT(CLK_TOP_CLK26M), + EXT_PARENT(CLK_PAD_CLK26M), TOP_PARENT(CLK_TOP_UNIVPLL_D7), TOP_PARENT(CLK_TOP_APLL1), TOP_PARENT(CLK_TOP_APLL2), }; static const struct mtk_parent pwrap_ulposc_parents[] = { - TOP_PARENT(CLK_TOP_CLK26M), + EXT_PARENT(CLK_PAD_CLK26M), TOP_PARENT(CLK_TOP_ULPOSC1_D10), TOP_PARENT(CLK_TOP_ULPOSC1_D7), TOP_PARENT(CLK_TOP_ULPOSC1_D8), @@ -547,13 +548,13 @@ static const struct mtk_parent pwrap_ulposc_parents[] = { }; static const struct mtk_parent atb_parents[] = { - TOP_PARENT(CLK_TOP_CLK26M), + EXT_PARENT(CLK_PAD_CLK26M), TOP_PARENT(CLK_TOP_MAINPLL_D4_D2), TOP_PARENT(CLK_TOP_MAINPLL_D5_D2), }; static const struct mtk_parent sspm_parents[] = { - TOP_PARENT(CLK_TOP_CLK26M), + EXT_PARENT(CLK_PAD_CLK26M), TOP_PARENT(CLK_TOP_MAINPLL_D7_D2), TOP_PARENT(CLK_TOP_MAINPLL_D6_D2), TOP_PARENT(CLK_TOP_MAINPLL_D5_D2), @@ -567,7 +568,7 @@ static const struct mtk_parent sspm_parents[] = { * in dual output case, which would lead to corruption of functionality loss. */ static const struct mtk_parent dp_parents[] = { - TOP_PARENT(CLK_TOP_CLK26M), + EXT_PARENT(CLK_PAD_CLK26M), TOP_PARENT(CLK_TOP_TVDPLL2_D2), TOP_PARENT(CLK_TOP_TVDPLL2_D4), TOP_PARENT(CLK_TOP_TVDPLL2_D8), @@ -575,7 +576,7 @@ static const struct mtk_parent dp_parents[] = { }; static const struct mtk_parent edp_parents[] = { - TOP_PARENT(CLK_TOP_CLK26M), + EXT_PARENT(CLK_PAD_CLK26M), TOP_PARENT(CLK_TOP_TVDPLL1_D2), TOP_PARENT(CLK_TOP_TVDPLL1_D4), TOP_PARENT(CLK_TOP_TVDPLL1_D8), @@ -583,7 +584,7 @@ static const struct mtk_parent edp_parents[] = { }; static const struct mtk_parent dpi_parents[] = { - TOP_PARENT(CLK_TOP_CLK26M), + EXT_PARENT(CLK_PAD_CLK26M), TOP_PARENT(CLK_TOP_TVDPLL1_D2), TOP_PARENT(CLK_TOP_TVDPLL2_D2), TOP_PARENT(CLK_TOP_TVDPLL1_D4), @@ -595,7 +596,7 @@ static const struct mtk_parent dpi_parents[] = { }; static const struct mtk_parent disp_pwm0_parents[] = { - TOP_PARENT(CLK_TOP_CLK26M), + EXT_PARENT(CLK_PAD_CLK26M), TOP_PARENT(CLK_TOP_UNIVPLL_D6_D4), TOP_PARENT(CLK_TOP_ULPOSC1_D2), TOP_PARENT(CLK_TOP_ULPOSC1_D4), @@ -604,7 +605,7 @@ static const struct mtk_parent disp_pwm0_parents[] = { }; static const struct mtk_parent disp_pwm1_parents[] = { - TOP_PARENT(CLK_TOP_CLK26M), + EXT_PARENT(CLK_PAD_CLK26M), TOP_PARENT(CLK_TOP_UNIVPLL_D6_D4), TOP_PARENT(CLK_TOP_ULPOSC1_D2), TOP_PARENT(CLK_TOP_ULPOSC1_D4), @@ -612,55 +613,55 @@ static const struct mtk_parent disp_pwm1_parents[] = { }; static const struct mtk_parent usb_parents[] = { - TOP_PARENT(CLK_TOP_CLK26M), + EXT_PARENT(CLK_PAD_CLK26M), TOP_PARENT(CLK_TOP_UNIVPLL_D5_D4), TOP_PARENT(CLK_TOP_UNIVPLL_D6_D4), TOP_PARENT(CLK_TOP_UNIVPLL_D5_D2), }; static const struct mtk_parent ssusb_xhci_parents[] = { - TOP_PARENT(CLK_TOP_CLK26M), + EXT_PARENT(CLK_PAD_CLK26M), TOP_PARENT(CLK_TOP_UNIVPLL_D5_D4), TOP_PARENT(CLK_TOP_UNIVPLL_D6_D4), TOP_PARENT(CLK_TOP_UNIVPLL_D5_D2), }; static const struct mtk_parent usb_2p_parents[] = { - TOP_PARENT(CLK_TOP_CLK26M), + EXT_PARENT(CLK_PAD_CLK26M), TOP_PARENT(CLK_TOP_UNIVPLL_D5_D4), TOP_PARENT(CLK_TOP_UNIVPLL_D6_D4), TOP_PARENT(CLK_TOP_UNIVPLL_D5_D2), }; static const struct mtk_parent ssusb_xhci_2p_parents[] = { - TOP_PARENT(CLK_TOP_CLK26M), + EXT_PARENT(CLK_PAD_CLK26M), TOP_PARENT(CLK_TOP_UNIVPLL_D5_D4), TOP_PARENT(CLK_TOP_UNIVPLL_D6_D4), TOP_PARENT(CLK_TOP_UNIVPLL_D5_D2), }; static const struct mtk_parent usb_3p_parents[] = { - TOP_PARENT(CLK_TOP_CLK26M), + EXT_PARENT(CLK_PAD_CLK26M), TOP_PARENT(CLK_TOP_UNIVPLL_D5_D4), TOP_PARENT(CLK_TOP_UNIVPLL_D6_D4), TOP_PARENT(CLK_TOP_UNIVPLL_D5_D2), }; static const struct mtk_parent ssusb_xhci_3p_parents[] = { - TOP_PARENT(CLK_TOP_CLK26M), + EXT_PARENT(CLK_PAD_CLK26M), TOP_PARENT(CLK_TOP_UNIVPLL_D5_D4), TOP_PARENT(CLK_TOP_UNIVPLL_D6_D4), TOP_PARENT(CLK_TOP_UNIVPLL_D5_D2), }; static const struct mtk_parent i2c_parents[] = { - TOP_PARENT(CLK_TOP_CLK26M), + EXT_PARENT(CLK_PAD_CLK26M), TOP_PARENT(CLK_TOP_MAINPLL_D4_D8), TOP_PARENT(CLK_TOP_UNIVPLL_D5_D4), }; static const struct mtk_parent seninf_parents[] = { - TOP_PARENT(CLK_TOP_CLK26M), + EXT_PARENT(CLK_PAD_CLK26M), TOP_PARENT(CLK_TOP_UNIVPLL_D4_D4), TOP_PARENT(CLK_TOP_UNIVPLL_D6_D2), TOP_PARENT(CLK_TOP_MAINPLL_D4_D2), @@ -671,7 +672,7 @@ static const struct mtk_parent seninf_parents[] = { }; static const struct mtk_parent seninf1_parents[] = { - TOP_PARENT(CLK_TOP_CLK26M), + EXT_PARENT(CLK_PAD_CLK26M), TOP_PARENT(CLK_TOP_UNIVPLL_D4_D4), TOP_PARENT(CLK_TOP_UNIVPLL_D6_D2), TOP_PARENT(CLK_TOP_MAINPLL_D4_D2), @@ -682,7 +683,7 @@ static const struct mtk_parent seninf1_parents[] = { }; static const struct mtk_parent gcpu_parents[] = { - TOP_PARENT(CLK_TOP_CLK26M), + EXT_PARENT(CLK_PAD_CLK26M), TOP_PARENT(CLK_TOP_MAINPLL_D6), TOP_PARENT(CLK_TOP_UNIVPLL_D4_D2), TOP_PARENT(CLK_TOP_MMPLL_D5_D2), @@ -690,7 +691,7 @@ static const struct mtk_parent gcpu_parents[] = { }; static const struct mtk_parent venc_parents[] = { - TOP_PARENT(CLK_TOP_CLK26M), + EXT_PARENT(CLK_PAD_CLK26M), TOP_PARENT(CLK_TOP_MMPLL_D4_D2), TOP_PARENT(CLK_TOP_MAINPLL_D6), TOP_PARENT(CLK_TOP_UNIVPLL_D4_D2), @@ -709,7 +710,7 @@ static const struct mtk_parent venc_parents[] = { }; static const struct mtk_parent vdec_parents[] = { - TOP_PARENT(CLK_TOP_CLK26M), + EXT_PARENT(CLK_PAD_CLK26M), TOP_PARENT(CLK_TOP_MAINPLL_D5_D2), TOP_PARENT(CLK_TOP_MMPLL_D6_D2), TOP_PARENT(CLK_TOP_UNIVPLL_D5_D2), @@ -722,65 +723,65 @@ static const struct mtk_parent vdec_parents[] = { TOP_PARENT(CLK_TOP_MAINPLL_D4), TOP_PARENT(CLK_TOP_TVDPLL2), TOP_PARENT(CLK_TOP_UNIVPLL_D4), - TOP_PARENT(CLK_TOP_IMGPLL), + APMIXED_PARENT(CLK_APMIXED_IMGPLL), TOP_PARENT(CLK_TOP_UNIVPLL_D6_D2), TOP_PARENT(CLK_TOP_MMPLL_D9), }; static const struct mtk_parent pwm_parents[] = { - TOP_PARENT(CLK_TOP_CLK32K), - TOP_PARENT(CLK_TOP_CLK26M), + EXT_PARENT(CLK_PAD_CLK32K), + EXT_PARENT(CLK_PAD_CLK26M), TOP_PARENT(CLK_TOP_UNIVPLL_D4_D8), TOP_PARENT(CLK_TOP_UNIVPLL_D6_D4), }; static const struct mtk_parent mcupm_parents[] = { - TOP_PARENT(CLK_TOP_CLK26M), + EXT_PARENT(CLK_PAD_CLK26M), TOP_PARENT(CLK_TOP_MAINPLL_D6_D2), TOP_PARENT(CLK_TOP_MAINPLL_D7_D4), }; static const struct mtk_parent spmi_p_mst_parents[] = { - TOP_PARENT(CLK_TOP_CLK26M), - TOP_PARENT(CLK_TOP_CLK13M), + EXT_PARENT(CLK_PAD_CLK26M), + EXT_PARENT(CLK_PAD_CLK13M), TOP_PARENT(CLK_TOP_ULPOSC1_D8), TOP_PARENT(CLK_TOP_ULPOSC1_D10), TOP_PARENT(CLK_TOP_ULPOSC1_D16), TOP_PARENT(CLK_TOP_ULPOSC1_D7), - TOP_PARENT(CLK_TOP_CLK32K), + EXT_PARENT(CLK_PAD_CLK32K), TOP_PARENT(CLK_TOP_MAINPLL_D7_D8), TOP_PARENT(CLK_TOP_MAINPLL_D6_D8), TOP_PARENT(CLK_TOP_MAINPLL_D5_D8), }; static const struct mtk_parent spmi_m_mst_parents[] = { - TOP_PARENT(CLK_TOP_CLK26M), - TOP_PARENT(CLK_TOP_CLK13M), + EXT_PARENT(CLK_PAD_CLK26M), + EXT_PARENT(CLK_PAD_CLK13M), TOP_PARENT(CLK_TOP_ULPOSC1_D8), TOP_PARENT(CLK_TOP_ULPOSC1_D10), TOP_PARENT(CLK_TOP_ULPOSC1_D16), TOP_PARENT(CLK_TOP_ULPOSC1_D7), - TOP_PARENT(CLK_TOP_CLK32K), + EXT_PARENT(CLK_PAD_CLK32K), TOP_PARENT(CLK_TOP_MAINPLL_D7_D8), TOP_PARENT(CLK_TOP_MAINPLL_D6_D8), TOP_PARENT(CLK_TOP_MAINPLL_D5_D8), }; static const struct mtk_parent dvfsrc_parents[] = { - TOP_PARENT(CLK_TOP_CLK26M), + EXT_PARENT(CLK_PAD_CLK26M), TOP_PARENT(CLK_TOP_ULPOSC1_D10), TOP_PARENT(CLK_TOP_UNIVPLL_D6_D8), TOP_PARENT(CLK_TOP_MSDCPLL_D16), }; static const struct mtk_parent tl_parents[] = { - TOP_PARENT(CLK_TOP_CLK26M), + EXT_PARENT(CLK_PAD_CLK26M), TOP_PARENT(CLK_TOP_UNIVPLL_D5_D4), TOP_PARENT(CLK_TOP_MAINPLL_D4_D4), }; static const struct mtk_parent aes_msdcfde_parents[] = { - TOP_PARENT(CLK_TOP_CLK26M), + EXT_PARENT(CLK_PAD_CLK26M), TOP_PARENT(CLK_TOP_MAINPLL_D4_D2), TOP_PARENT(CLK_TOP_MAINPLL_D6), TOP_PARENT(CLK_TOP_MAINPLL_D4_D4), @@ -789,14 +790,14 @@ static const struct mtk_parent aes_msdcfde_parents[] = { }; static const struct mtk_parent dsi_occ_parents[] = { - TOP_PARENT(CLK_TOP_CLK26M), + EXT_PARENT(CLK_PAD_CLK26M), TOP_PARENT(CLK_TOP_UNIVPLL_D6_D2), TOP_PARENT(CLK_TOP_UNIVPLL_D5_D2), TOP_PARENT(CLK_TOP_UNIVPLL_D4_D2), }; static const struct mtk_parent wpe_vpp_parents[] = { - TOP_PARENT(CLK_TOP_CLK26M), + EXT_PARENT(CLK_PAD_CLK26M), TOP_PARENT(CLK_TOP_MAINPLL_D5_D2), TOP_PARENT(CLK_TOP_MMPLL_D6_D2), TOP_PARENT(CLK_TOP_UNIVPLL_D5_D2), @@ -814,60 +815,60 @@ static const struct mtk_parent wpe_vpp_parents[] = { }; static const struct mtk_parent hdcp_parents[] = { - TOP_PARENT(CLK_TOP_CLK26M), + EXT_PARENT(CLK_PAD_CLK26M), TOP_PARENT(CLK_TOP_UNIVPLL_D4_D8), TOP_PARENT(CLK_TOP_MAINPLL_D5_D8), TOP_PARENT(CLK_TOP_UNIVPLL_D6_D4), }; static const struct mtk_parent hdcp_24m_parents[] = { - TOP_PARENT(CLK_TOP_CLK26M), + EXT_PARENT(CLK_PAD_CLK26M), TOP_PARENT(CLK_TOP_UNIVPLL_192M_D4), TOP_PARENT(CLK_TOP_UNIVPLL_192M_D8), TOP_PARENT(CLK_TOP_UNIVPLL_D6_D8), }; static const struct mtk_parent hdmi_apb_parents[] = { - TOP_PARENT(CLK_TOP_CLK26M), + EXT_PARENT(CLK_PAD_CLK26M), TOP_PARENT(CLK_TOP_UNIVPLL_D6_D4), TOP_PARENT(CLK_TOP_MSDCPLL_D2), }; static const struct mtk_parent snps_eth_250m_parents[] = { - TOP_PARENT(CLK_TOP_CLK26M), + EXT_PARENT(CLK_PAD_CLK26M), TOP_PARENT(CLK_TOP_ETHPLL_D2), }; static const struct mtk_parent snps_eth_62p4m_ptp_parents[] = { TOP_PARENT(CLK_TOP_APLL2_D3), TOP_PARENT(CLK_TOP_APLL1_D3), - TOP_PARENT(CLK_TOP_CLK26M), + EXT_PARENT(CLK_PAD_CLK26M), TOP_PARENT(CLK_TOP_ETHPLL_D8), }; static const struct mtk_parent snps_eth_50m_rmii_parents[] = { - TOP_PARENT(CLK_TOP_CLK26M), + EXT_PARENT(CLK_PAD_CLK26M), TOP_PARENT(CLK_TOP_ETHPLL_D10), }; static const struct mtk_parent adsp_parents[] = { - TOP_PARENT(CLK_TOP_CLK26M), - TOP_PARENT(CLK_TOP_CLK13M), + EXT_PARENT(CLK_PAD_CLK26M), + EXT_PARENT(CLK_PAD_CLK13M), TOP_PARENT(CLK_TOP_MAINPLL_D6), TOP_PARENT(CLK_TOP_MAINPLL_D5_D2), TOP_PARENT(CLK_TOP_UNIVPLL_D4_D4), TOP_PARENT(CLK_TOP_UNIVPLL_D4), TOP_PARENT(CLK_TOP_ULPOSC1_D2), TOP_PARENT(CLK_TOP_ULPOSC1), - TOP_PARENT(CLK_TOP_ADSPPLL), + APMIXED_PARENT(CLK_APMIXED_ADSPPLL), TOP_PARENT(CLK_TOP_ADSPPLL_D2), TOP_PARENT(CLK_TOP_ADSPPLL_D4), TOP_PARENT(CLK_TOP_ADSPPLL_D8), }; static const struct mtk_parent audio_local_bus_parents[] = { - TOP_PARENT(CLK_TOP_CLK26M), - TOP_PARENT(CLK_TOP_CLK13M), + EXT_PARENT(CLK_PAD_CLK26M), + EXT_PARENT(CLK_PAD_CLK13M), TOP_PARENT(CLK_TOP_MAINPLL_D4_D4), TOP_PARENT(CLK_TOP_MAINPLL_D7_D2), TOP_PARENT(CLK_TOP_MAINPLL_D5_D2), @@ -881,46 +882,46 @@ static const struct mtk_parent audio_local_bus_parents[] = { }; static const struct mtk_parent asm_h_parents[] = { - TOP_PARENT(CLK_TOP_CLK26M), + EXT_PARENT(CLK_PAD_CLK26M), TOP_PARENT(CLK_TOP_UNIVPLL_D6_D4), TOP_PARENT(CLK_TOP_UNIVPLL_D6_D2), TOP_PARENT(CLK_TOP_MAINPLL_D5_D2), }; static const struct mtk_parent asm_l_parents[] = { - TOP_PARENT(CLK_TOP_CLK26M), + EXT_PARENT(CLK_PAD_CLK26M), TOP_PARENT(CLK_TOP_UNIVPLL_D6_D4), TOP_PARENT(CLK_TOP_UNIVPLL_D6_D2), TOP_PARENT(CLK_TOP_MAINPLL_D5_D2), }; static const struct mtk_parent apll1_parents[] = { - TOP_PARENT(CLK_TOP_CLK26M), + EXT_PARENT(CLK_PAD_CLK26M), TOP_PARENT(CLK_TOP_APLL1_D4), }; static const struct mtk_parent apll2_parents[] = { - TOP_PARENT(CLK_TOP_CLK26M), + EXT_PARENT(CLK_PAD_CLK26M), TOP_PARENT(CLK_TOP_APLL2_D4), }; static const struct mtk_parent apll3_parents[] = { - TOP_PARENT(CLK_TOP_CLK26M), + EXT_PARENT(CLK_PAD_CLK26M), TOP_PARENT(CLK_TOP_APLL3_D4), }; static const struct mtk_parent apll4_parents[] = { - TOP_PARENT(CLK_TOP_CLK26M), + EXT_PARENT(CLK_PAD_CLK26M), TOP_PARENT(CLK_TOP_APLL4_D4), }; static const struct mtk_parent apll5_parents[] = { - TOP_PARENT(CLK_TOP_CLK26M), + EXT_PARENT(CLK_PAD_CLK26M), TOP_PARENT(CLK_TOP_APLL5_D4), }; static const struct mtk_parent i2so1_parents[] = { - TOP_PARENT(CLK_TOP_CLK26M), + EXT_PARENT(CLK_PAD_CLK26M), TOP_PARENT(CLK_TOP_APLL1), TOP_PARENT(CLK_TOP_APLL2), TOP_PARENT(CLK_TOP_APLL3), @@ -929,7 +930,7 @@ static const struct mtk_parent i2so1_parents[] = { }; static const struct mtk_parent i2so2_parents[] = { - TOP_PARENT(CLK_TOP_CLK26M), + EXT_PARENT(CLK_PAD_CLK26M), TOP_PARENT(CLK_TOP_APLL1), TOP_PARENT(CLK_TOP_APLL2), TOP_PARENT(CLK_TOP_APLL3), @@ -938,7 +939,7 @@ static const struct mtk_parent i2so2_parents[] = { }; static const struct mtk_parent i2si1_parents[] = { - TOP_PARENT(CLK_TOP_CLK26M), + EXT_PARENT(CLK_PAD_CLK26M), TOP_PARENT(CLK_TOP_APLL1), TOP_PARENT(CLK_TOP_APLL2), TOP_PARENT(CLK_TOP_APLL3), @@ -947,7 +948,7 @@ static const struct mtk_parent i2si1_parents[] = { }; static const struct mtk_parent i2si2_parents[] = { - TOP_PARENT(CLK_TOP_CLK26M), + EXT_PARENT(CLK_PAD_CLK26M), TOP_PARENT(CLK_TOP_APLL1), TOP_PARENT(CLK_TOP_APLL2), TOP_PARENT(CLK_TOP_APLL3), @@ -956,7 +957,7 @@ static const struct mtk_parent i2si2_parents[] = { }; static const struct mtk_parent dptx_parents[] = { - TOP_PARENT(CLK_TOP_CLK26M), + EXT_PARENT(CLK_PAD_CLK26M), TOP_PARENT(CLK_TOP_APLL1), TOP_PARENT(CLK_TOP_APLL2), TOP_PARENT(CLK_TOP_APLL3), @@ -965,7 +966,7 @@ static const struct mtk_parent dptx_parents[] = { }; static const struct mtk_parent aud_iec_parents[] = { - TOP_PARENT(CLK_TOP_CLK26M), + EXT_PARENT(CLK_PAD_CLK26M), TOP_PARENT(CLK_TOP_APLL1), TOP_PARENT(CLK_TOP_APLL2), TOP_PARENT(CLK_TOP_APLL3), @@ -974,31 +975,31 @@ static const struct mtk_parent aud_iec_parents[] = { }; static const struct mtk_parent a1sys_hp_parents[] = { - TOP_PARENT(CLK_TOP_CLK26M), + EXT_PARENT(CLK_PAD_CLK26M), TOP_PARENT(CLK_TOP_APLL1_D4), }; static const struct mtk_parent a2sys_parents[] = { - TOP_PARENT(CLK_TOP_CLK26M), + EXT_PARENT(CLK_PAD_CLK26M), TOP_PARENT(CLK_TOP_APLL2_D4), }; static const struct mtk_parent a3sys_parents[] = { - TOP_PARENT(CLK_TOP_CLK26M), + EXT_PARENT(CLK_PAD_CLK26M), TOP_PARENT(CLK_TOP_APLL3_D4), TOP_PARENT(CLK_TOP_APLL4_D4), TOP_PARENT(CLK_TOP_APLL5_D4), }; static const struct mtk_parent a4sys_parents[] = { - TOP_PARENT(CLK_TOP_CLK26M), + EXT_PARENT(CLK_PAD_CLK26M), TOP_PARENT(CLK_TOP_APLL3_D4), TOP_PARENT(CLK_TOP_APLL4_D4), TOP_PARENT(CLK_TOP_APLL5_D4), }; static const struct mtk_parent ecc_parents[] = { - TOP_PARENT(CLK_TOP_CLK26M), + EXT_PARENT(CLK_PAD_CLK26M), TOP_PARENT(CLK_TOP_MAINPLL_D4_D4), TOP_PARENT(CLK_TOP_MAINPLL_D5_D2), TOP_PARENT(CLK_TOP_MAINPLL_D4_D2), @@ -1007,8 +1008,8 @@ static const struct mtk_parent ecc_parents[] = { }; static const struct mtk_parent spinor_parents[] = { - TOP_PARENT(CLK_TOP_CLK26M), - TOP_PARENT(CLK_TOP_CLK13M), + EXT_PARENT(CLK_PAD_CLK26M), + EXT_PARENT(CLK_PAD_CLK13M), TOP_PARENT(CLK_TOP_MAINPLL_D7_D8), TOP_PARENT(CLK_TOP_UNIVPLL_D6_D8), }; @@ -1022,7 +1023,7 @@ static const struct mtk_parent ulposc_parents[] = { static const struct mtk_parent srck_parents[] = { TOP_PARENT(CLK_TOP_ULPOSC1_D10), - TOP_PARENT(CLK_TOP_CLK26M), + EXT_PARENT(CLK_PAD_CLK26M), }; static const struct mtk_composite top_muxes[] = { @@ -1143,7 +1144,7 @@ static const struct mtk_composite top_muxes[] = { }; static const int mt8188_id_top_offs_map[] = { - [0 ... CLK_TOP_FULL_NR_CLK - 1] = -1, + [0 ... CLK_TOP_NR_CLK - 1] = -1, /* FIXED */ [CLK_TOP_ULPOSC1] = 0, [CLK_TOP_MPHONE_SLAVE_BCK] = 1, @@ -1151,202 +1152,198 @@ static const int mt8188_id_top_offs_map[] = { [CLK_TOP_466M_FMEM] = 3, [CLK_TOP_PEXTP_PIPE] = 4, [CLK_TOP_DSI_PHY] = 5, - [CLK_TOP_CLK13M] = 6, - [CLK_TOP_CLK26M] = 7, - [CLK_TOP_CLK32K] = 8, /* FACTOR */ - [CLK_TOP_MAINPLL_D3] = 9, - [CLK_TOP_MAINPLL_D4] = 10, - [CLK_TOP_MAINPLL_D4_D2] = 11, - [CLK_TOP_MAINPLL_D4_D4] = 12, - [CLK_TOP_MAINPLL_D4_D8] = 13, - [CLK_TOP_MAINPLL_D5] = 14, - [CLK_TOP_MAINPLL_D5_D2] = 15, - [CLK_TOP_MAINPLL_D5_D4] = 16, - [CLK_TOP_MAINPLL_D5_D8] = 17, - [CLK_TOP_MAINPLL_D6] = 18, - [CLK_TOP_MAINPLL_D6_D2] = 19, - [CLK_TOP_MAINPLL_D6_D4] = 20, - [CLK_TOP_MAINPLL_D6_D8] = 21, - [CLK_TOP_MAINPLL_D7] = 22, - [CLK_TOP_MAINPLL_D7_D2] = 23, - [CLK_TOP_MAINPLL_D7_D4] = 24, - [CLK_TOP_MAINPLL_D7_D8] = 25, - [CLK_TOP_MAINPLL_D9] = 26, - [CLK_TOP_UNIVPLL_D2] = 27, - [CLK_TOP_UNIVPLL_D3] = 28, - [CLK_TOP_UNIVPLL_D4] = 29, - [CLK_TOP_UNIVPLL_D4_D2] = 30, - [CLK_TOP_UNIVPLL_D4_D4] = 31, - [CLK_TOP_UNIVPLL_D4_D8] = 32, - [CLK_TOP_UNIVPLL_D5] = 33, - [CLK_TOP_UNIVPLL_D5_D2] = 34, - [CLK_TOP_UNIVPLL_D5_D4] = 35, - [CLK_TOP_UNIVPLL_D5_D8] = 36, - [CLK_TOP_UNIVPLL_D6] = 37, - [CLK_TOP_UNIVPLL_D6_D2] = 38, - [CLK_TOP_UNIVPLL_D6_D4] = 39, - [CLK_TOP_UNIVPLL_D6_D8] = 40, - [CLK_TOP_UNIVPLL_D7] = 41, - [CLK_TOP_UNIVPLL_192M] = 42, - [CLK_TOP_UNIVPLL_192M_D4] = 43, - [CLK_TOP_UNIVPLL_192M_D8] = 44, - [CLK_TOP_UNIVPLL_192M_D10] = 45, - [CLK_TOP_UNIVPLL_192M_D16] = 46, - [CLK_TOP_UNIVPLL_192M_D32] = 47, - [CLK_TOP_APLL1_D3] = 48, - [CLK_TOP_APLL1_D4] = 49, - [CLK_TOP_APLL2_D3] = 50, - [CLK_TOP_APLL2_D4] = 51, - [CLK_TOP_APLL3_D4] = 52, - [CLK_TOP_APLL4_D4] = 53, - [CLK_TOP_APLL5_D4] = 54, - [CLK_TOP_MMPLL_D4] = 55, - [CLK_TOP_MMPLL_D4_D2] = 56, - [CLK_TOP_MMPLL_D5] = 57, - [CLK_TOP_MMPLL_D5_D2] = 58, - [CLK_TOP_MMPLL_D5_D4] = 59, - [CLK_TOP_MMPLL_D6] = 60, - [CLK_TOP_MMPLL_D6_D2] = 61, - [CLK_TOP_MMPLL_D7] = 62, - [CLK_TOP_MMPLL_D9] = 62, - [CLK_TOP_TVDPLL1_D2] = 64, - [CLK_TOP_TVDPLL1_D4] = 65, - [CLK_TOP_TVDPLL1_D8] = 66, - [CLK_TOP_TVDPLL1_D16] = 67, - [CLK_TOP_TVDPLL2_D2] = 68, - [CLK_TOP_TVDPLL2_D4] = 69, - [CLK_TOP_TVDPLL2_D8] = 70, - [CLK_TOP_TVDPLL2_D16] = 71, - [CLK_TOP_MSDCPLL] = 72, - [CLK_TOP_MSDCPLL_D2] = 73, - [CLK_TOP_MSDCPLL_D16] = 74, - [CLK_TOP_ETHPLL_D2] = 75, - [CLK_TOP_ETHPLL_D4] = 76, - [CLK_TOP_ETHPLL_D8] = 77, - [CLK_TOP_ETHPLL_D10] = 78, - [CLK_TOP_ADSPPLL_D2] = 79, - [CLK_TOP_ADSPPLL_D4] = 80, - [CLK_TOP_ADSPPLL_D8] = 81, - [CLK_TOP_ULPOSC1_D2] = 82, - [CLK_TOP_ULPOSC1_D4] = 83, - [CLK_TOP_ULPOSC1_D8] = 84, - [CLK_TOP_ULPOSC1_D7] = 85, - [CLK_TOP_ULPOSC1_D10] = 86, - [CLK_TOP_ULPOSC1_D16] = 87, + [CLK_TOP_MAINPLL_D3] = 6, + [CLK_TOP_MAINPLL_D4] = 7, + [CLK_TOP_MAINPLL_D4_D2] = 8, + [CLK_TOP_MAINPLL_D4_D4] = 9, + [CLK_TOP_MAINPLL_D4_D8] = 10, + [CLK_TOP_MAINPLL_D5] = 11, + [CLK_TOP_MAINPLL_D5_D2] = 12, + [CLK_TOP_MAINPLL_D5_D4] = 13, + [CLK_TOP_MAINPLL_D5_D8] = 14, + [CLK_TOP_MAINPLL_D6] = 15, + [CLK_TOP_MAINPLL_D6_D2] = 16, + [CLK_TOP_MAINPLL_D6_D4] = 17, + [CLK_TOP_MAINPLL_D6_D8] = 18, + [CLK_TOP_MAINPLL_D7] = 19, + [CLK_TOP_MAINPLL_D7_D2] = 20, + [CLK_TOP_MAINPLL_D7_D4] = 21, + [CLK_TOP_MAINPLL_D7_D8] = 22, + [CLK_TOP_MAINPLL_D9] = 23, + [CLK_TOP_UNIVPLL_D2] = 24, + [CLK_TOP_UNIVPLL_D3] = 25, + [CLK_TOP_UNIVPLL_D4] = 26, + [CLK_TOP_UNIVPLL_D4_D2] = 27, + [CLK_TOP_UNIVPLL_D4_D4] = 28, + [CLK_TOP_UNIVPLL_D4_D8] = 29, + [CLK_TOP_UNIVPLL_D5] = 30, + [CLK_TOP_UNIVPLL_D5_D2] = 31, + [CLK_TOP_UNIVPLL_D5_D4] = 32, + [CLK_TOP_UNIVPLL_D5_D8] = 33, + [CLK_TOP_UNIVPLL_D6] = 34, + [CLK_TOP_UNIVPLL_D6_D2] = 35, + [CLK_TOP_UNIVPLL_D6_D4] = 36, + [CLK_TOP_UNIVPLL_D6_D8] = 37, + [CLK_TOP_UNIVPLL_D7] = 38, + [CLK_TOP_UNIVPLL_192M] = 39, + [CLK_TOP_UNIVPLL_192M_D4] = 40, + [CLK_TOP_UNIVPLL_192M_D8] = 41, + [CLK_TOP_UNIVPLL_192M_D10] = 42, + [CLK_TOP_UNIVPLL_192M_D16] = 43, + [CLK_TOP_UNIVPLL_192M_D32] = 44, + [CLK_TOP_APLL1_D3] = 45, + [CLK_TOP_APLL1_D4] = 46, + [CLK_TOP_APLL2_D3] = 47, + [CLK_TOP_APLL2_D4] = 48, + [CLK_TOP_APLL3_D4] = 49, + [CLK_TOP_APLL4_D4] = 50, + [CLK_TOP_APLL5_D4] = 51, + [CLK_TOP_MMPLL_D4] = 52, + [CLK_TOP_MMPLL_D4_D2] = 53, + [CLK_TOP_MMPLL_D5] = 54, + [CLK_TOP_MMPLL_D5_D2] = 55, + [CLK_TOP_MMPLL_D5_D4] = 56, + [CLK_TOP_MMPLL_D6] = 57, + [CLK_TOP_MMPLL_D6_D2] = 58, + [CLK_TOP_MMPLL_D7] = 59, + [CLK_TOP_MMPLL_D9] = 60, + [CLK_TOP_TVDPLL1_D2] = 61, + [CLK_TOP_TVDPLL1_D4] = 62, + [CLK_TOP_TVDPLL1_D8] = 63, + [CLK_TOP_TVDPLL1_D16] = 64, + [CLK_TOP_TVDPLL2_D2] = 65, + [CLK_TOP_TVDPLL2_D4] = 66, + [CLK_TOP_TVDPLL2_D8] = 67, + [CLK_TOP_TVDPLL2_D16] = 68, + [CLK_TOP_MSDCPLL_D2] = 69, + [CLK_TOP_MSDCPLL_D16] = 70, + [CLK_TOP_ETHPLL_D2] = 71, + [CLK_TOP_ETHPLL_D4] = 72, + [CLK_TOP_ETHPLL_D8] = 73, + [CLK_TOP_ETHPLL_D10] = 74, + [CLK_TOP_ADSPPLL_D2] = 75, + [CLK_TOP_ADSPPLL_D4] = 76, + [CLK_TOP_ADSPPLL_D8] = 77, + [CLK_TOP_ULPOSC1_D2] = 78, + [CLK_TOP_ULPOSC1_D4] = 79, + [CLK_TOP_ULPOSC1_D8] = 80, + [CLK_TOP_ULPOSC1_D7] = 81, + [CLK_TOP_ULPOSC1_D10] = 82, + [CLK_TOP_ULPOSC1_D16] = 83, /* MUX */ - [CLK_TOP_AXI] = 88, - [CLK_TOP_SPM] = 89, - [CLK_TOP_SCP] = 90, - [CLK_TOP_BUS_AXIMEM] = 91, - [CLK_TOP_VPP] = 92, - [CLK_TOP_ETHDR] = 93, - [CLK_TOP_IPE] = 94, - [CLK_TOP_CAM] = 95, - [CLK_TOP_CCU] = 96, - [CLK_TOP_CCU_AHB] = 97, - [CLK_TOP_IMG] = 98, - [CLK_TOP_CAMTM] = 99, - [CLK_TOP_DSP] = 100, - [CLK_TOP_DSP1] = 101, - [CLK_TOP_DSP2] = 102, - [CLK_TOP_DSP3] = 103, - [CLK_TOP_DSP4] = 104, - [CLK_TOP_DSP5] = 105, - [CLK_TOP_DSP6] = 106, - [CLK_TOP_DSP7] = 107, - [CLK_TOP_MFG_CORE_TMP] = 108, - [CLK_TOP_CAMTG] = 109, - [CLK_TOP_CAMTG2] = 110, - [CLK_TOP_CAMTG3] = 111, - [CLK_TOP_UART] = 112, - [CLK_TOP_SPI] = 113, - [CLK_TOP_MSDC50_0_HCLK] = 114, - [CLK_TOP_MSDC50_0] = 115, - [CLK_TOP_MSDC30_1] = 116, - [CLK_TOP_MSDC30_2] = 117, - [CLK_TOP_INTDIR] = 118, - [CLK_TOP_AUD_INTBUS] = 119, - [CLK_TOP_AUDIO_H] = 120, - [CLK_TOP_PWRAP_ULPOSC] = 121, - [CLK_TOP_ATB] = 122, - [CLK_TOP_SSPM] = 123, - [CLK_TOP_DP] = 124, - [CLK_TOP_EDP] = 125, - [CLK_TOP_DPI] = 126, - [CLK_TOP_DISP_PWM0] = 127, - [CLK_TOP_DISP_PWM1] = 128, - [CLK_TOP_USB_TOP] = 129, - [CLK_TOP_SSUSB_XHCI] = 130, - [CLK_TOP_USB_TOP_2P] = 131, - [CLK_TOP_SSUSB_XHCI_2P] = 132, - [CLK_TOP_USB_TOP_3P] = 133, - [CLK_TOP_SSUSB_XHCI_3P] = 134, - [CLK_TOP_I2C] = 135, - [CLK_TOP_SENINF] = 136, - [CLK_TOP_SENINF1] = 137, - [CLK_TOP_GCPU] = 138, - [CLK_TOP_VENC] = 139, - [CLK_TOP_VDEC] = 140, - [CLK_TOP_PWM] = 141, - [CLK_TOP_MCUPM] = 142, - [CLK_TOP_SPMI_P_MST] = 143, - [CLK_TOP_SPMI_M_MST] = 144, - [CLK_TOP_DVFSRC] = 145, - [CLK_TOP_TL] = 146, - [CLK_TOP_AES_MSDCFDE] = 147, - [CLK_TOP_DSI_OCC] = 148, - [CLK_TOP_WPE_VPP] = 149, - [CLK_TOP_HDCP] = 150, - [CLK_TOP_HDCP_24M] = 151, - [CLK_TOP_HDMI_APB] = 152, - [CLK_TOP_SNPS_ETH_250M] = 153, - [CLK_TOP_SNPS_ETH_62P4M_PTP] = 154, - [CLK_TOP_SNPS_ETH_50M_RMII] = 155, - [CLK_TOP_ADSP] = 156, - [CLK_TOP_AUDIO_LOCAL_BUS] = 157, - [CLK_TOP_ASM_H] = 158, - [CLK_TOP_ASM_L] = 159, - [CLK_TOP_APLL1] = 160, - [CLK_TOP_APLL2] = 161, - [CLK_TOP_APLL3] = 162, - [CLK_TOP_APLL4] = 163, - [CLK_TOP_APLL5] = 164, - [CLK_TOP_I2SO1] = 165, - [CLK_TOP_I2SO2] = 166, - [CLK_TOP_I2SI1] = 167, - [CLK_TOP_I2SI2] = 168, - [CLK_TOP_DPTX] = 169, - [CLK_TOP_AUD_IEC] = 170, - [CLK_TOP_A1SYS_HP] = 171, - [CLK_TOP_A2SYS] = 172, - [CLK_TOP_A3SYS] = 173, - [CLK_TOP_A4SYS] = 174, - [CLK_TOP_ECC] = 175, - [CLK_TOP_SPINOR] = 176, - [CLK_TOP_ULPOSC] = 177, - [CLK_TOP_SRCK] = 178, + [CLK_TOP_AXI] = 84, + [CLK_TOP_SPM] = 85, + [CLK_TOP_SCP] = 86, + [CLK_TOP_BUS_AXIMEM] = 87, + [CLK_TOP_VPP] = 88, + [CLK_TOP_ETHDR] = 89, + [CLK_TOP_IPE] = 90, + [CLK_TOP_CAM] = 91, + [CLK_TOP_CCU] = 92, + [CLK_TOP_CCU_AHB] = 93, + [CLK_TOP_IMG] = 94, + [CLK_TOP_CAMTM] = 95, + [CLK_TOP_DSP] = 96, + [CLK_TOP_DSP1] = 97, + [CLK_TOP_DSP2] = 98, + [CLK_TOP_DSP3] = 99, + [CLK_TOP_DSP4] = 100, + [CLK_TOP_DSP5] = 101, + [CLK_TOP_DSP6] = 102, + [CLK_TOP_DSP7] = 103, + [CLK_TOP_MFG_CORE_TMP] = 104, + [CLK_TOP_CAMTG] = 105, + [CLK_TOP_CAMTG2] = 106, + [CLK_TOP_CAMTG3] = 107, + [CLK_TOP_UART] = 108, + [CLK_TOP_SPI] = 109, + [CLK_TOP_MSDC50_0_HCLK] = 110, + [CLK_TOP_MSDC50_0] = 111, + [CLK_TOP_MSDC30_1] = 112, + [CLK_TOP_MSDC30_2] = 113, + [CLK_TOP_INTDIR] = 114, + [CLK_TOP_AUD_INTBUS] = 115, + [CLK_TOP_AUDIO_H] = 116, + [CLK_TOP_PWRAP_ULPOSC] = 117, + [CLK_TOP_ATB] = 118, + [CLK_TOP_SSPM] = 119, + [CLK_TOP_DP] = 120, + [CLK_TOP_EDP] = 121, + [CLK_TOP_DPI] = 122, + [CLK_TOP_DISP_PWM0] = 123, + [CLK_TOP_DISP_PWM1] = 124, + [CLK_TOP_USB_TOP] = 125, + [CLK_TOP_SSUSB_XHCI] = 126, + [CLK_TOP_USB_TOP_2P] = 127, + [CLK_TOP_SSUSB_XHCI_2P] = 128, + [CLK_TOP_USB_TOP_3P] = 129, + [CLK_TOP_SSUSB_XHCI_3P] = 130, + [CLK_TOP_I2C] = 131, + [CLK_TOP_SENINF] = 132, + [CLK_TOP_SENINF1] = 133, + [CLK_TOP_GCPU] = 134, + [CLK_TOP_VENC] = 135, + [CLK_TOP_VDEC] = 136, + [CLK_TOP_PWM] = 137, + [CLK_TOP_MCUPM] = 138, + [CLK_TOP_SPMI_P_MST] = 139, + [CLK_TOP_SPMI_M_MST] = 140, + [CLK_TOP_DVFSRC] = 141, + [CLK_TOP_TL] = 142, + [CLK_TOP_AES_MSDCFDE] = 143, + [CLK_TOP_DSI_OCC] = 144, + [CLK_TOP_WPE_VPP] = 145, + [CLK_TOP_HDCP] = 146, + [CLK_TOP_HDCP_24M] = 147, + [CLK_TOP_HDMI_APB] = 148, + [CLK_TOP_SNPS_ETH_250M] = 149, + [CLK_TOP_SNPS_ETH_62P4M_PTP] = 150, + [CLK_TOP_SNPS_ETH_50M_RMII] = 151, + [CLK_TOP_ADSP] = 152, + [CLK_TOP_AUDIO_LOCAL_BUS] = 153, + [CLK_TOP_ASM_H] = 154, + [CLK_TOP_ASM_L] = 155, + [CLK_TOP_APLL1] = 156, + [CLK_TOP_APLL2] = 157, + [CLK_TOP_APLL3] = 158, + [CLK_TOP_APLL4] = 159, + [CLK_TOP_APLL5] = 160, + [CLK_TOP_I2SO1] = 161, + [CLK_TOP_I2SO2] = 162, + [CLK_TOP_I2SI1] = 163, + [CLK_TOP_I2SI2] = 164, + [CLK_TOP_DPTX] = 165, + [CLK_TOP_AUD_IEC] = 166, + [CLK_TOP_A1SYS_HP] = 167, + [CLK_TOP_A2SYS] = 168, + [CLK_TOP_A3SYS] = 169, + [CLK_TOP_A4SYS] = 170, + [CLK_TOP_ECC] = 171, + [CLK_TOP_SPINOR] = 172, + [CLK_TOP_ULPOSC] = 173, + [CLK_TOP_SRCK] = 174, /* GATE */ - [CLK_TOP_CFGREG_CLOCK_EN_VPP0] = 179, - [CLK_TOP_CFGREG_CLOCK_EN_VPP1] = 180, - [CLK_TOP_CFGREG_CLOCK_EN_VDO0] = 181, - [CLK_TOP_CFGREG_CLOCK_EN_VDO1] = 182, - [CLK_TOP_CFGREG_CLOCK_ISP_AXI_GALS] = 183, - [CLK_TOP_CFGREG_F26M_VPP0] = 184, - [CLK_TOP_CFGREG_F26M_VPP1] = 185, - [CLK_TOP_CFGREG_F26M_VDO0] = 186, - [CLK_TOP_CFGREG_F26M_VDO1] = 187, - [CLK_TOP_CFGREG_AUD_F26M_AUD] = 188, - [CLK_TOP_CFGREG_UNIPLL_SES] = 189, - [CLK_TOP_CFGREG_F_PCIE_PHY_REF] = 190, - [CLK_TOP_SSUSB_TOP_REF] = 191, - [CLK_TOP_SSUSB_PHY_REF] = 192, - [CLK_TOP_SSUSB_TOP_P1_REF] = 193, - [CLK_TOP_SSUSB_PHY_P1_REF] = 194, - [CLK_TOP_SSUSB_TOP_P2_REF] = 195, - [CLK_TOP_SSUSB_PHY_P2_REF] = 196, - [CLK_TOP_SSUSB_TOP_P3_REF] = 197, - [CLK_TOP_SSUSB_PHY_P3_REF] = 198, + [CLK_TOP_CFGREG_CLOCK_EN_VPP0] = 175, + [CLK_TOP_CFGREG_CLOCK_EN_VPP1] = 176, + [CLK_TOP_CFGREG_CLOCK_EN_VDO0] = 177, + [CLK_TOP_CFGREG_CLOCK_EN_VDO1] = 178, + [CLK_TOP_CFGREG_CLOCK_ISP_AXI_GALS] = 179, + [CLK_TOP_CFGREG_F26M_VPP0] = 180, + [CLK_TOP_CFGREG_F26M_VPP1] = 181, + [CLK_TOP_CFGREG_F26M_VDO0] = 182, + [CLK_TOP_CFGREG_F26M_VDO1] = 183, + [CLK_TOP_CFGREG_AUD_F26M_AUD] = 184, + [CLK_TOP_CFGREG_UNIPLL_SES] = 185, + [CLK_TOP_CFGREG_F_PCIE_PHY_REF] = 186, + [CLK_TOP_SSUSB_TOP_REF] = 187, + [CLK_TOP_SSUSB_PHY_REF] = 188, + [CLK_TOP_SSUSB_TOP_P1_REF] = 189, + [CLK_TOP_SSUSB_PHY_P1_REF] = 190, + [CLK_TOP_SSUSB_TOP_P2_REF] = 191, + [CLK_TOP_SSUSB_PHY_P2_REF] = 192, + [CLK_TOP_SSUSB_TOP_P3_REF] = 193, + [CLK_TOP_SSUSB_PHY_P3_REF] = 194, }; static const struct mtk_gate_regs top0_cg_regs = { @@ -1369,12 +1366,20 @@ static const struct mtk_gate_regs top1_cg_regs = { .flags = CLK_GATE_NO_SETCLR | CLK_PARENT_TOPCKGEN, \ } +#define GATE_TOP0E(_id, _parent, _shift) { \ + .id = _id, \ + .parent = _parent, \ + .regs = &top0_cg_regs, \ + .shift = _shift, \ + .flags = CLK_GATE_NO_SETCLR | CLK_PARENT_EXT, \ + } + #define GATE_TOP1(_id, _parent, _shift) { \ .id = _id, \ .parent = _parent, \ .regs = &top1_cg_regs, \ .shift = _shift, \ - .flags = CLK_GATE_NO_SETCLR_INV | CLK_PARENT_TOPCKGEN, \ + .flags = CLK_GATE_NO_SETCLR_INV | CLK_PARENT_EXT, \ } static const struct mtk_gate topckgen_cg_clks[] = { @@ -1384,26 +1389,28 @@ static const struct mtk_gate topckgen_cg_clks[] = { GATE_TOP0(CLK_TOP_CFGREG_CLOCK_EN_VDO0, CLK_TOP_VPP, 2), GATE_TOP0(CLK_TOP_CFGREG_CLOCK_EN_VDO1, CLK_TOP_VPP, 3), GATE_TOP0(CLK_TOP_CFGREG_CLOCK_ISP_AXI_GALS, CLK_TOP_VPP, 4), - GATE_TOP0(CLK_TOP_CFGREG_F26M_VPP0, CLK_TOP_CLK26M, 5), - GATE_TOP0(CLK_TOP_CFGREG_F26M_VPP1, CLK_TOP_CLK26M, 6), - GATE_TOP0(CLK_TOP_CFGREG_F26M_VDO0, CLK_TOP_CLK26M, 7), - GATE_TOP0(CLK_TOP_CFGREG_F26M_VDO1, CLK_TOP_CLK26M, 8), - GATE_TOP0(CLK_TOP_CFGREG_AUD_F26M_AUD, CLK_TOP_CLK26M, 9), + GATE_TOP0E(CLK_TOP_CFGREG_F26M_VPP0, CLK_PAD_CLK26M, 5), + GATE_TOP0E(CLK_TOP_CFGREG_F26M_VPP1, CLK_PAD_CLK26M, 6), + GATE_TOP0E(CLK_TOP_CFGREG_F26M_VDO0, CLK_PAD_CLK26M, 7), + GATE_TOP0E(CLK_TOP_CFGREG_F26M_VDO1, CLK_PAD_CLK26M, 8), + GATE_TOP0E(CLK_TOP_CFGREG_AUD_F26M_AUD, CLK_PAD_CLK26M, 9), GATE_TOP0(CLK_TOP_CFGREG_UNIPLL_SES, CLK_TOP_UNIVPLL_D2, 15), - GATE_TOP0(CLK_TOP_CFGREG_F_PCIE_PHY_REF, CLK_TOP_CLK26M, 18), + GATE_TOP0E(CLK_TOP_CFGREG_F_PCIE_PHY_REF, CLK_PAD_CLK26M, 18), /* TOP1 */ - GATE_TOP1(CLK_TOP_SSUSB_TOP_REF, CLK_TOP_CLK26M, 0), - GATE_TOP1(CLK_TOP_SSUSB_PHY_REF, CLK_TOP_CLK26M, 1), - GATE_TOP1(CLK_TOP_SSUSB_TOP_P1_REF, CLK_TOP_CLK26M, 2), - GATE_TOP1(CLK_TOP_SSUSB_PHY_P1_REF, CLK_TOP_CLK26M, 3), - GATE_TOP1(CLK_TOP_SSUSB_TOP_P2_REF, CLK_TOP_CLK26M, 4), - GATE_TOP1(CLK_TOP_SSUSB_PHY_P2_REF, CLK_TOP_CLK26M, 5), - GATE_TOP1(CLK_TOP_SSUSB_TOP_P3_REF, CLK_TOP_CLK26M, 6), - GATE_TOP1(CLK_TOP_SSUSB_PHY_P3_REF, CLK_TOP_CLK26M, 7), + GATE_TOP1(CLK_TOP_SSUSB_TOP_REF, CLK_PAD_CLK26M, 0), + GATE_TOP1(CLK_TOP_SSUSB_PHY_REF, CLK_PAD_CLK26M, 1), + GATE_TOP1(CLK_TOP_SSUSB_TOP_P1_REF, CLK_PAD_CLK26M, 2), + GATE_TOP1(CLK_TOP_SSUSB_PHY_P1_REF, CLK_PAD_CLK26M, 3), + GATE_TOP1(CLK_TOP_SSUSB_TOP_P2_REF, CLK_PAD_CLK26M, 4), + GATE_TOP1(CLK_TOP_SSUSB_PHY_P2_REF, CLK_PAD_CLK26M, 5), + GATE_TOP1(CLK_TOP_SSUSB_TOP_P3_REF, CLK_PAD_CLK26M, 6), + GATE_TOP1(CLK_TOP_SSUSB_PHY_P3_REF, CLK_PAD_CLK26M, 7), }; static const struct mtk_clk_tree mt8188_topckgen_clk_tree = { .xtal_rate = 26 * MHZ, + .ext_clk_rates = ext_clock_rates, + .num_ext_clks = ARRAY_SIZE(ext_clock_rates), .id_offs_map = mt8188_id_top_offs_map, .id_offs_map_size = ARRAY_SIZE(mt8188_id_top_offs_map), .fdivs_offs = mt8188_id_top_offs_map[CLK_TOP_MAINPLL_D3], @@ -1457,6 +1464,14 @@ static const struct mtk_gate_regs infra_ao4_cg_regs = { .flags = CLK_GATE_SETCLR | CLK_PARENT_TOPCKGEN, \ } +#define GATE_INFRA_AO0E(_id, _parent, _shift) { \ + .id = _id, \ + .parent = _parent, \ + .regs = &infra_ao0_cg_regs, \ + .shift = _shift, \ + .flags = CLK_GATE_SETCLR | CLK_PARENT_EXT, \ + } + #define GATE_INFRA_AO1(_id, _parent, _shift) { \ .id = _id, \ .parent = _parent, \ @@ -1465,6 +1480,14 @@ static const struct mtk_gate_regs infra_ao4_cg_regs = { .flags = CLK_GATE_SETCLR | CLK_PARENT_TOPCKGEN, \ } +#define GATE_INFRA_AO1E(_id, _parent, _shift) { \ + .id = _id, \ + .parent = _parent, \ + .regs = &infra_ao1_cg_regs, \ + .shift = _shift, \ + .flags = CLK_GATE_SETCLR | CLK_PARENT_EXT, \ + } + #define GATE_INFRA_AO2(_id, _parent, _shift) { \ .id = _id, \ .parent = _parent, \ @@ -1473,6 +1496,14 @@ static const struct mtk_gate_regs infra_ao4_cg_regs = { .flags = CLK_GATE_SETCLR | CLK_PARENT_TOPCKGEN, \ } +#define GATE_INFRA_AO2E(_id, _parent, _shift) { \ + .id = _id, \ + .parent = _parent, \ + .regs = &infra_ao2_cg_regs, \ + .shift = _shift, \ + .flags = CLK_GATE_SETCLR | CLK_PARENT_EXT, \ + } + #define GATE_INFRA_AO3(_id, _parent, _shift) { \ .id = _id, \ .parent = _parent, \ @@ -1481,6 +1512,14 @@ static const struct mtk_gate_regs infra_ao4_cg_regs = { .flags = CLK_GATE_SETCLR | CLK_PARENT_TOPCKGEN, \ } +#define GATE_INFRA_AO3E(_id, _parent, _shift) { \ + .id = _id, \ + .parent = _parent, \ + .regs = &infra_ao3_cg_regs, \ + .shift = _shift, \ + .flags = CLK_GATE_SETCLR | CLK_PARENT_EXT, \ + } + #define GATE_INFRA_AO4(_id, _parent, _shift) { \ .id = _id, \ .parent = _parent, \ @@ -1512,24 +1551,24 @@ static const struct mtk_gate infracfg_ao_clks[] = { GATE_INFRA_AO0(CLK_INFRA_AO_UART2, CLK_TOP_UART, 24), GATE_INFRA_AO0(CLK_INFRA_AO_UART3, CLK_TOP_UART, 25), GATE_INFRA_AO0(CLK_INFRA_AO_UART4, CLK_TOP_UART, 26), - GATE_INFRA_AO0(CLK_INFRA_AO_GCE_26M, CLK_TOP_CLK26M, 27), + GATE_INFRA_AO0E(CLK_INFRA_AO_GCE_26M, CLK_PAD_CLK26M, 27), GATE_INFRA_AO0(CLK_INFRA_AO_CQ_DMA_FPC, CLK_TOP_PAD_FPC, 28), GATE_INFRA_AO0(CLK_INFRA_AO_UART5, CLK_TOP_UART, 29), /* INFRA_AO1 */ - GATE_INFRA_AO1(CLK_INFRA_AO_HDMI_26M, CLK_TOP_CLK26M, 0), + GATE_INFRA_AO1E(CLK_INFRA_AO_HDMI_26M, CLK_PAD_CLK26M, 0), GATE_INFRA_AO1(CLK_INFRA_AO_SPI0, CLK_TOP_SPI, 1), - GATE_INFRA_AO1(CLK_INFRA_AO_MSDC0, CLK_TOP_CLK26M, 2), + GATE_INFRA_AO1E(CLK_INFRA_AO_MSDC0, CLK_PAD_CLK26M, 2), GATE_INFRA_AO1(CLK_INFRA_AO_MSDC1, CLK_TOP_AXI, 4), GATE_INFRA_AO1(CLK_INFRA_AO_MSDC2, CLK_TOP_AXI, 5), GATE_INFRA_AO1(CLK_INFRA_AO_MSDC0_SRC, CLK_TOP_MSDC50_0, 6), /* infra_ao_dvfsrc is for internal DVFS usage, should not be handled by Linux. */ - GATE_INFRA_AO1(CLK_INFRA_AO_DVFSRC, CLK_TOP_CLK26M, 7), + GATE_INFRA_AO1E(CLK_INFRA_AO_DVFSRC, CLK_PAD_CLK26M, 7), GATE_INFRA_AO1(CLK_INFRA_AO_TRNG, CLK_TOP_AXI, 9), - GATE_INFRA_AO1(CLK_INFRA_AO_AUXADC, CLK_TOP_CLK26M, 10), + GATE_INFRA_AO1E(CLK_INFRA_AO_AUXADC, CLK_PAD_CLK26M, 10), GATE_INFRA_AO1(CLK_INFRA_AO_CPUM, CLK_TOP_AXI, 11), - GATE_INFRA_AO1(CLK_INFRA_AO_HDMI_32K, CLK_TOP_CLK32K, 12), + GATE_INFRA_AO1E(CLK_INFRA_AO_HDMI_32K, CLK_PAD_CLK32K, 12), GATE_INFRA_AO1(CLK_INFRA_AO_CEC_66M_HCLK, CLK_TOP_AXI, 13), - GATE_INFRA_AO1(CLK_INFRA_AO_PCIE_TL_26M, CLK_TOP_CLK26M, 15), + GATE_INFRA_AO1E(CLK_INFRA_AO_PCIE_TL_26M, CLK_PAD_CLK26M, 15), GATE_INFRA_AO1(CLK_INFRA_AO_MSDC1_SRC, CLK_TOP_MSDC30_1, 16), GATE_INFRA_AO1(CLK_INFRA_AO_CEC_66M_BCLK, CLK_TOP_AXI, 17), GATE_INFRA_AO1(CLK_INFRA_AO_PCIE_TL_96M, CLK_TOP_TL, 18), @@ -1538,14 +1577,14 @@ static const struct mtk_gate infracfg_ao_clks[] = { GATE_INFRA_AO1(CLK_INFRA_AO_ECC_66M_HCLK, CLK_TOP_AXI, 23), GATE_INFRA_AO1(CLK_INFRA_AO_DEBUGSYS, CLK_TOP_AXI, 24), GATE_INFRA_AO1(CLK_INFRA_AO_AUDIO, CLK_TOP_AXI, 25), - GATE_INFRA_AO1(CLK_INFRA_AO_PCIE_TL_32K, CLK_TOP_CLK32K, 26), + GATE_INFRA_AO1E(CLK_INFRA_AO_PCIE_TL_32K, CLK_PAD_CLK32K, 26), GATE_INFRA_AO1(CLK_INFRA_AO_DBG_TRACE, CLK_TOP_AXI, 29), - GATE_INFRA_AO1(CLK_INFRA_AO_DRAMC_F26M, CLK_TOP_CLK26M, 31), + GATE_INFRA_AO1E(CLK_INFRA_AO_DRAMC_F26M, CLK_PAD_CLK26M, 31), /* INFRA_AO2 */ GATE_INFRA_AO2(CLK_INFRA_AO_IRTX, CLK_TOP_AXI, 0), GATE_INFRA_AO2(CLK_INFRA_AO_DISP_PWM, CLK_TOP_DISP_PWM0, 2), GATE_INFRA_AO2(CLK_INFRA_AO_CLDMA_BCLK, CLK_TOP_AXI, 3), - GATE_INFRA_AO2(CLK_INFRA_AO_AUDIO_26M_BCLK, CLK_TOP_CLK26M, 4), + GATE_INFRA_AO2E(CLK_INFRA_AO_AUDIO_26M_BCLK, CLK_PAD_CLK26M, 4), GATE_INFRA_AO2(CLK_INFRA_AO_SPI1, CLK_TOP_SPI, 6), GATE_INFRA_AO2(CLK_INFRA_AO_SPI2, CLK_TOP_SPI, 9), GATE_INFRA_AO2(CLK_INFRA_AO_SPI3, CLK_TOP_SPI, 10), @@ -1564,14 +1603,14 @@ static const struct mtk_gate infracfg_ao_clks[] = { GATE_INFRA_AO3(CLK_INFRA_AO_MD_MSDC0, CLK_TOP_MSDC50_0, 8), GATE_INFRA_AO3(CLK_INFRA_AO_MSDC30_2, CLK_TOP_MSDC30_2, 9), GATE_INFRA_AO3(CLK_INFRA_AO_GCPU, CLK_TOP_GCPU, 10), - GATE_INFRA_AO3(CLK_INFRA_AO_PCIE_PERI_26M, CLK_TOP_CLK26M, 15), + GATE_INFRA_AO3E(CLK_INFRA_AO_PCIE_PERI_26M, CLK_PAD_CLK26M, 15), GATE_INFRA_AO3(CLK_INFRA_AO_GCPU_66M_BCLK, CLK_TOP_AXI, 16), GATE_INFRA_AO3(CLK_INFRA_AO_GCPU_133M_BCLK, CLK_TOP_AXI, 17), GATE_INFRA_AO3(CLK_INFRA_AO_DISP_PWM1, CLK_TOP_DISP_PWM1, 20), GATE_INFRA_AO3(CLK_INFRA_AO_FBIST2FPC, CLK_TOP_MSDC50_0, 24), /* infra_ao_dapc_sync is for device access permission control module */ GATE_INFRA_AO3(CLK_INFRA_AO_DEVICE_APC_SYNC, CLK_TOP_AXI, 25), - GATE_INFRA_AO3(CLK_INFRA_AO_PCIE_P1_PERI_26M, CLK_TOP_CLK26M, 26), + GATE_INFRA_AO3E(CLK_INFRA_AO_PCIE_P1_PERI_26M, CLK_PAD_CLK26M, 26), /* INFRA_AO4 */ /* infra_ao_133m_mclk_set/infra_ao_66m_mclk_set are main clocks of peripheral */ GATE_INFRA_AO4(CLK_INFRA_AO_133M_MCLK_CK, CLK_TOP_AXI, 0), @@ -1582,6 +1621,8 @@ static const struct mtk_gate infracfg_ao_clks[] = { static const struct mtk_clk_tree mt8188_infracfg_ao_clk_tree = { .xtal_rate = 26 * MHZ, + .ext_clk_rates = ext_clock_rates, + .num_ext_clks = ARRAY_SIZE(ext_clock_rates), }; static const struct mtk_gate_regs peri_ao_cg_regs = { @@ -1598,11 +1639,19 @@ static const struct mtk_gate_regs peri_ao_cg_regs = { .flags = CLK_GATE_SETCLR | CLK_PARENT_TOPCKGEN, \ } +#define GATE_PERI_AOE(_id, _parent, _shift) { \ + .id = _id, \ + .parent = _parent, \ + .regs = &peri_ao_cg_regs, \ + .shift = _shift, \ + .flags = CLK_GATE_SETCLR | CLK_PARENT_EXT, \ + } + static const struct mtk_gate pericfg_ao_clks[] = { GATE_PERI_AO(CLK_PERI_AO_ETHERNET, CLK_TOP_AXI, 0), GATE_PERI_AO(CLK_PERI_AO_ETHERNET_BUS, CLK_TOP_AXI, 1), GATE_PERI_AO(CLK_PERI_AO_FLASHIF_BUS, CLK_TOP_AXI, 3), - GATE_PERI_AO(CLK_PERI_AO_FLASHIF_26M, CLK_TOP_CLK26M, 4), + GATE_PERI_AOE(CLK_PERI_AO_FLASHIF_26M, CLK_PAD_CLK26M, 4), GATE_PERI_AO(CLK_PERI_AO_FLASHIFLASHCK, CLK_TOP_SPINOR, 5), GATE_PERI_AO(CLK_PERI_AO_SSUSB_2P_BUS, CLK_TOP_USB_TOP_2P, 9), GATE_PERI_AO(CLK_PERI_AO_SSUSB_2P_XHCI, CLK_TOP_SSUSB_XHCI_2P, 10), @@ -1615,6 +1664,8 @@ static const struct mtk_gate pericfg_ao_clks[] = { static const struct mtk_clk_tree mt8188_pericfg_ao_clk_tree = { .xtal_rate = 26 * MHZ, + .ext_clk_rates = ext_clock_rates, + .num_ext_clks = ARRAY_SIZE(ext_clock_rates), }; static const struct mtk_gate_regs imp_iic_wrap_cg_regs = { @@ -1649,14 +1700,20 @@ static const struct mtk_gate imp_iic_wrap_en_clks[] = { const struct mtk_clk_tree mt8188_imp_iic_wrap_c_clk_tree = { .xtal_rate = 26 * MHZ, + .ext_clk_rates = ext_clock_rates, + .num_ext_clks = ARRAY_SIZE(ext_clock_rates), }; const struct mtk_clk_tree mt8188_imp_iic_wrap_w_clk_tree = { .xtal_rate = 26 * MHZ, + .ext_clk_rates = ext_clock_rates, + .num_ext_clks = ARRAY_SIZE(ext_clock_rates), }; const struct mtk_clk_tree mt8188_imp_iic_wrap_en_clk_tree = { .xtal_rate = 26 * MHZ, + .ext_clk_rates = ext_clock_rates, + .num_ext_clks = ARRAY_SIZE(ext_clock_rates), }; static int mt8188_apmixedsys_probe(struct udevice *dev) -- cgit v1.3.1 From 6bbfa8fba553df9bccb526ee47ccb8ad010bbbcf Mon Sep 17 00:00:00 2001 From: David Lechner Date: Mon, 9 Mar 2026 17:51:11 -0500 Subject: clk: mediatek: mt8195: use ext_clock_rates Convert the mt8195 clock driver to use ext_clock_rates. Now that we have the ext_clock_rates feature and also mux clock parents have been converted to struct mtk_parent, we can remove the hack of adding "missing" topckgen clocks. Instead we can use the proper parents. The topckgen ID map is still needed though because the upstream dt-bindings didn't use the conventional number ordering by clock type for these. Reviewed-by: Julien Stephan Link: https://patch.msgid.link/20260309-clk-mtk-mt8188-drop-extra-top-clocks-v1-2-6ee4743a8465@baylibre.com Signed-off-by: David Lechner --- drivers/clk/mediatek/clk-mt8195.c | 820 +++++++++++++++++++------------------- 1 file changed, 412 insertions(+), 408 deletions(-) diff --git a/drivers/clk/mediatek/clk-mt8195.c b/drivers/clk/mediatek/clk-mt8195.c index fc7b9ff1d8d..76ece913187 100644 --- a/drivers/clk/mediatek/clk-mt8195.c +++ b/drivers/clk/mediatek/clk-mt8195.c @@ -12,23 +12,20 @@ #include "clk-mtk.h" -#define CLK_TOP_CLK26M CLK_TOP_NR_CLK -#define CLK_TOP_CLK32K CLK_TOP_NR_CLK + 1 -#define CLK_TOP_TVDPLL1 CLK_TOP_NR_CLK + 2 -#define CLK_TOP_TVDPLL2 CLK_TOP_NR_CLK + 3 -#define CLK_TOP_MSDCPLL CLK_TOP_NR_CLK + 4 -#define CLK_TOP_DGIPLL CLK_TOP_NR_CLK + 5 -#define CLK_TOP_ADSPPLL CLK_TOP_NR_CLK + 6 -#define CLK_TOP_IMGPLL CLK_TOP_NR_CLK + 7 -#define CLK_TOP_VDECPLL CLK_TOP_NR_CLK + 8 -#define CLK_TOP_NNAPLL CLK_TOP_NR_CLK + 9 -#define CLK_TOP_HDMIRX_APLL CLK_TOP_NR_CLK + 10 -#define CLK_TOP_FULL_NR_CLK CLK_TOP_NR_CLK + 11 - #define MT8195_PLL_FMAX (3800UL * MHZ) #define MT8195_PLL_FMIN (1500UL * MHZ) #define MT8195_INTEGER_BITS 8 +enum { + CLK_PAD_CLK26M, + CLK_PAD_CLK32K, +}; + +static const ulong ext_clock_rates[] = { + [CLK_PAD_CLK26M] = 26 * MHZ, + [CLK_PAD_CLK32K] = 32000, +}; + #define PLL(_id, _reg, _pwr_reg, _en_mask, _flags, \ _rst_bar_mask, _pcwbits, _pd_reg, _pd_shift,\ _pcw_reg, _pcw_shift, _pcw_chg_reg) { \ @@ -101,6 +98,8 @@ static const struct mtk_pll_data apmixed_plls[] = { static const struct mtk_clk_tree mt8195_apmixedsys_clk_tree = { .xtal_rate = 26 * MHZ, .xtal2_rate = 26 * MHZ, + .ext_clk_rates = ext_clock_rates, + .num_ext_clks = ARRAY_SIZE(ext_clock_rates), .plls = apmixed_plls, .num_plls = ARRAY_SIZE(apmixed_plls), }; @@ -121,8 +120,6 @@ static const struct mtk_fixed_clk top_fixed_clks[] = { FIXED_CLK0(CLK_TOP_UFS_RX_SYMBOL1, 166000000), FIXED_CLK0(CLK_TOP_FPC, 50000000), FIXED_CLK0(CLK_TOP_HDMIRX_P, 594000000), - FIXED_CLK0(CLK_TOP_CLK26M, 26000000), - FIXED_CLK0(CLK_TOP_CLK32K, 32000), }; #define FACTOR0(_id, _parent, _mult, _div) \ @@ -131,9 +128,12 @@ static const struct mtk_fixed_clk top_fixed_clks[] = { #define FACTOR1(_id, _parent, _mult, _div) \ FACTOR(_id, _parent, _mult, _div, CLK_PARENT_TOPCKGEN) +#define FACTOR2(_id, _parent, _mult, _div) \ + FACTOR(_id, _parent, _mult, _div, CLK_PARENT_EXT) + static const struct mtk_fixed_factor top_fixed_divs[] = { - FACTOR1(CLK_TOP_CLK26M_D2, CLK_TOP_CLK26M, 1, 2), - FACTOR1(CLK_TOP_CLK26M_D52, CLK_TOP_CLK26M, 1, 52), + FACTOR2(CLK_TOP_CLK26M_D2, CLK_PAD_CLK26M, 1, 2), + FACTOR2(CLK_TOP_CLK26M_D52, CLK_PAD_CLK26M, 1, 52), FACTOR1(CLK_TOP_IN_DGI_D2, CLK_TOP_IN_DGI, 1, 2), FACTOR1(CLK_TOP_IN_DGI_D4, CLK_TOP_IN_DGI, 1, 4), FACTOR1(CLK_TOP_IN_DGI_D6, CLK_TOP_IN_DGI, 1, 6), @@ -197,43 +197,34 @@ static const struct mtk_fixed_factor top_fixed_divs[] = { FACTOR1(CLK_TOP_MMPLL_D6_D2, CLK_TOP_MMPLL_D6, 1, 2), FACTOR0(CLK_TOP_MMPLL_D7, CLK_APMIXED_MMPLL, 1, 7), FACTOR0(CLK_TOP_MMPLL_D9, CLK_APMIXED_MMPLL, 1, 9), - FACTOR0(CLK_TOP_TVDPLL1, CLK_APMIXED_TVDPLL1, 1, 1), - FACTOR1(CLK_TOP_TVDPLL1_D2, CLK_TOP_TVDPLL1, 1, 2), - FACTOR1(CLK_TOP_TVDPLL1_D4, CLK_TOP_TVDPLL1, 1, 4), - FACTOR1(CLK_TOP_TVDPLL1_D8, CLK_TOP_TVDPLL1, 1, 8), - FACTOR1(CLK_TOP_TVDPLL1_D16, CLK_TOP_TVDPLL1, 1, 16), - FACTOR0(CLK_TOP_TVDPLL2, CLK_APMIXED_TVDPLL2, 1, 1), - FACTOR1(CLK_TOP_TVDPLL2_D2, CLK_TOP_TVDPLL2, 1, 2), - FACTOR1(CLK_TOP_TVDPLL2_D4, CLK_TOP_TVDPLL2, 1, 4), - FACTOR1(CLK_TOP_TVDPLL2_D8, CLK_TOP_TVDPLL2, 1, 8), - FACTOR1(CLK_TOP_TVDPLL2_D16, CLK_TOP_TVDPLL2, 1, 16), - FACTOR0(CLK_TOP_MSDCPLL, CLK_APMIXED_MSDCPLL, 1, 1), - FACTOR1(CLK_TOP_MSDCPLL_D2, CLK_TOP_MSDCPLL, 1, 2), - FACTOR1(CLK_TOP_MSDCPLL_D4, CLK_TOP_MSDCPLL, 1, 4), - FACTOR1(CLK_TOP_MSDCPLL_D16, CLK_TOP_MSDCPLL, 1, 16), + FACTOR0(CLK_TOP_TVDPLL1_D2, CLK_APMIXED_TVDPLL1, 1, 2), + FACTOR0(CLK_TOP_TVDPLL1_D4, CLK_APMIXED_TVDPLL1, 1, 4), + FACTOR0(CLK_TOP_TVDPLL1_D8, CLK_APMIXED_TVDPLL1, 1, 8), + FACTOR0(CLK_TOP_TVDPLL1_D16, CLK_APMIXED_TVDPLL1, 1, 16), + FACTOR0(CLK_TOP_TVDPLL2_D2, CLK_APMIXED_TVDPLL2, 1, 2), + FACTOR0(CLK_TOP_TVDPLL2_D4, CLK_APMIXED_TVDPLL2, 1, 4), + FACTOR0(CLK_TOP_TVDPLL2_D8, CLK_APMIXED_TVDPLL2, 1, 8), + FACTOR0(CLK_TOP_TVDPLL2_D16, CLK_APMIXED_TVDPLL2, 1, 16), + FACTOR0(CLK_TOP_MSDCPLL_D2, CLK_APMIXED_MSDCPLL, 1, 2), + FACTOR0(CLK_TOP_MSDCPLL_D4, CLK_APMIXED_MSDCPLL, 1, 4), + FACTOR0(CLK_TOP_MSDCPLL_D16, CLK_APMIXED_MSDCPLL, 1, 16), FACTOR0(CLK_TOP_ETHPLL_D2, CLK_APMIXED_ETHPLL, 1, 2), FACTOR0(CLK_TOP_ETHPLL_D8, CLK_APMIXED_ETHPLL, 1, 8), FACTOR0(CLK_TOP_ETHPLL_D10, CLK_APMIXED_ETHPLL, 1, 10), - FACTOR0(CLK_TOP_DGIPLL, CLK_APMIXED_DGIPLL, 1, 1), - FACTOR1(CLK_TOP_DGIPLL_D2, CLK_TOP_DGIPLL, 1, 2), + FACTOR0(CLK_TOP_DGIPLL_D2, CLK_APMIXED_DGIPLL, 1, 2), FACTOR1(CLK_TOP_ULPOSC1_D2, CLK_TOP_ULPOSC1, 1, 2), FACTOR1(CLK_TOP_ULPOSC1_D4, CLK_TOP_ULPOSC1, 1, 4), FACTOR1(CLK_TOP_ULPOSC1_D7, CLK_TOP_ULPOSC1, 1, 7), FACTOR1(CLK_TOP_ULPOSC1_D8, CLK_TOP_ULPOSC1, 1, 8), FACTOR1(CLK_TOP_ULPOSC1_D10, CLK_TOP_ULPOSC1, 1, 10), FACTOR1(CLK_TOP_ULPOSC1_D16, CLK_TOP_ULPOSC1, 1, 16), - FACTOR0(CLK_TOP_ADSPPLL, CLK_APMIXED_ADSPPLL, 1, 1), - FACTOR1(CLK_TOP_ADSPPLL_D2, CLK_TOP_ADSPPLL, 1, 2), - FACTOR1(CLK_TOP_ADSPPLL_D4, CLK_TOP_ADSPPLL, 1, 4), - FACTOR1(CLK_TOP_ADSPPLL_D8, CLK_TOP_ADSPPLL, 1, 8), - FACTOR0(CLK_TOP_IMGPLL, CLK_APMIXED_IMGPLL, 1, 1), - FACTOR0(CLK_TOP_VDECPLL, CLK_APMIXED_VDECPLL, 1, 1), - FACTOR0(CLK_TOP_NNAPLL, CLK_APMIXED_NNAPLL, 1, 1), - FACTOR0(CLK_TOP_HDMIRX_APLL, CLK_APMIXED_HDMIRX_APLL, 1, 1), + FACTOR0(CLK_TOP_ADSPPLL_D2, CLK_APMIXED_ADSPPLL, 1, 2), + FACTOR0(CLK_TOP_ADSPPLL_D4, CLK_APMIXED_ADSPPLL, 1, 4), + FACTOR0(CLK_TOP_ADSPPLL_D8, CLK_APMIXED_ADSPPLL, 1, 8), }; static const struct mtk_parent axi_parents[] = { - TOP_PARENT(CLK_TOP_CLK26M), + EXT_PARENT(CLK_PAD_CLK26M), TOP_PARENT(CLK_TOP_MAINPLL_D4_D4), TOP_PARENT(CLK_TOP_MAINPLL_D7_D2), TOP_PARENT(CLK_TOP_MAINPLL_D4_D2), @@ -243,14 +234,14 @@ static const struct mtk_parent axi_parents[] = { }; static const struct mtk_parent spm_parents[] = { - TOP_PARENT(CLK_TOP_CLK26M), + EXT_PARENT(CLK_PAD_CLK26M), TOP_PARENT(CLK_TOP_ULPOSC1_D10), TOP_PARENT(CLK_TOP_MAINPLL_D7_D4), - TOP_PARENT(CLK_TOP_CLK32K), + EXT_PARENT(CLK_PAD_CLK32K), }; static const struct mtk_parent scp_parents[] = { - TOP_PARENT(CLK_TOP_CLK26M), + EXT_PARENT(CLK_PAD_CLK26M), TOP_PARENT(CLK_TOP_UNIVPLL_D4), TOP_PARENT(CLK_TOP_MAINPLL_D6), TOP_PARENT(CLK_TOP_UNIVPLL_D6), @@ -261,7 +252,7 @@ static const struct mtk_parent scp_parents[] = { }; static const struct mtk_parent bus_aximem_parents[] = { - TOP_PARENT(CLK_TOP_CLK26M), + EXT_PARENT(CLK_PAD_CLK26M), TOP_PARENT(CLK_TOP_MAINPLL_D7_D2), TOP_PARENT(CLK_TOP_MAINPLL_D4_D2), TOP_PARENT(CLK_TOP_MAINPLL_D5_D2), @@ -269,7 +260,7 @@ static const struct mtk_parent bus_aximem_parents[] = { }; static const struct mtk_parent vpp_parents[] = { - TOP_PARENT(CLK_TOP_CLK26M), + EXT_PARENT(CLK_PAD_CLK26M), TOP_PARENT(CLK_TOP_UNIVPLL_D6_D2), TOP_PARENT(CLK_TOP_MAINPLL_D5_D2), TOP_PARENT(CLK_TOP_MMPLL_D6_D2), @@ -280,14 +271,14 @@ static const struct mtk_parent vpp_parents[] = { TOP_PARENT(CLK_TOP_UNIVPLL_D6), TOP_PARENT(CLK_TOP_MAINPLL_D4), TOP_PARENT(CLK_TOP_MMPLL_D5), - TOP_PARENT(CLK_TOP_TVDPLL1), - TOP_PARENT(CLK_TOP_TVDPLL2), + APMIXED_PARENT(CLK_APMIXED_TVDPLL1), + APMIXED_PARENT(CLK_APMIXED_TVDPLL2), TOP_PARENT(CLK_TOP_UNIVPLL_D4), TOP_PARENT(CLK_TOP_MMPLL_D4), }; static const struct mtk_parent ethdr_parents[] = { - TOP_PARENT(CLK_TOP_CLK26M), + EXT_PARENT(CLK_PAD_CLK26M), TOP_PARENT(CLK_TOP_UNIVPLL_D6_D2), TOP_PARENT(CLK_TOP_MAINPLL_D5_D2), TOP_PARENT(CLK_TOP_MMPLL_D6_D2), @@ -298,15 +289,15 @@ static const struct mtk_parent ethdr_parents[] = { TOP_PARENT(CLK_TOP_UNIVPLL_D6), TOP_PARENT(CLK_TOP_MAINPLL_D4), TOP_PARENT(CLK_TOP_MMPLL_D5_D4), - TOP_PARENT(CLK_TOP_TVDPLL1), - TOP_PARENT(CLK_TOP_TVDPLL2), + APMIXED_PARENT(CLK_APMIXED_TVDPLL1), + APMIXED_PARENT(CLK_APMIXED_TVDPLL2), TOP_PARENT(CLK_TOP_UNIVPLL_D4), TOP_PARENT(CLK_TOP_MMPLL_D4), }; static const struct mtk_parent ipe_parents[] = { - TOP_PARENT(CLK_TOP_CLK26M), - TOP_PARENT(CLK_TOP_IMGPLL), + EXT_PARENT(CLK_PAD_CLK26M), + APMIXED_PARENT(CLK_APMIXED_IMGPLL), TOP_PARENT(CLK_TOP_MAINPLL_D4), TOP_PARENT(CLK_TOP_MMPLL_D6), TOP_PARENT(CLK_TOP_UNIVPLL_D6), @@ -319,7 +310,7 @@ static const struct mtk_parent ipe_parents[] = { }; static const struct mtk_parent cam_parents[] = { - TOP_PARENT(CLK_TOP_CLK26M), + EXT_PARENT(CLK_PAD_CLK26M), TOP_PARENT(CLK_TOP_MAINPLL_D4), TOP_PARENT(CLK_TOP_MMPLL_D4), TOP_PARENT(CLK_TOP_UNIVPLL_D4), @@ -328,11 +319,11 @@ static const struct mtk_parent cam_parents[] = { TOP_PARENT(CLK_TOP_MMPLL_D7), TOP_PARENT(CLK_TOP_UNIVPLL_D4_D2), TOP_PARENT(CLK_TOP_MAINPLL_D4_D2), - TOP_PARENT(CLK_TOP_IMGPLL), + APMIXED_PARENT(CLK_APMIXED_IMGPLL), }; static const struct mtk_parent ccu_parents[] = { - TOP_PARENT(CLK_TOP_CLK26M), + EXT_PARENT(CLK_PAD_CLK26M), TOP_PARENT(CLK_TOP_UNIVPLL_D6), TOP_PARENT(CLK_TOP_MAINPLL_D4_D2), TOP_PARENT(CLK_TOP_MAINPLL_D4), @@ -345,8 +336,8 @@ static const struct mtk_parent ccu_parents[] = { }; static const struct mtk_parent img_parents[] = { - TOP_PARENT(CLK_TOP_CLK26M), - TOP_PARENT(CLK_TOP_IMGPLL), + EXT_PARENT(CLK_PAD_CLK26M), + APMIXED_PARENT(CLK_APMIXED_IMGPLL), TOP_PARENT(CLK_TOP_UNIVPLL_D4), TOP_PARENT(CLK_TOP_MAINPLL_D4), TOP_PARENT(CLK_TOP_UNIVPLL_D5), @@ -360,14 +351,14 @@ static const struct mtk_parent img_parents[] = { }; static const struct mtk_parent camtm_parents[] = { - TOP_PARENT(CLK_TOP_CLK26M), + EXT_PARENT(CLK_PAD_CLK26M), TOP_PARENT(CLK_TOP_UNIVPLL_D4_D4), TOP_PARENT(CLK_TOP_UNIVPLL_D6_D2), TOP_PARENT(CLK_TOP_UNIVPLL_D6_D4), }; static const struct mtk_parent dsp_parents[] = { - TOP_PARENT(CLK_TOP_CLK26M), + EXT_PARENT(CLK_PAD_CLK26M), TOP_PARENT(CLK_TOP_UNIVPLL_D6_D2), TOP_PARENT(CLK_TOP_UNIVPLL_D4_D2), TOP_PARENT(CLK_TOP_UNIVPLL_D5), @@ -378,7 +369,7 @@ static const struct mtk_parent dsp_parents[] = { }; static const struct mtk_parent dsp1_parents[] = { - TOP_PARENT(CLK_TOP_CLK26M), + EXT_PARENT(CLK_PAD_CLK26M), TOP_PARENT(CLK_TOP_UNIVPLL_D6_D2), TOP_PARENT(CLK_TOP_MAINPLL_D4_D2), TOP_PARENT(CLK_TOP_UNIVPLL_D5), @@ -389,7 +380,7 @@ static const struct mtk_parent dsp1_parents[] = { }; static const struct mtk_parent dsp2_parents[] = { - TOP_PARENT(CLK_TOP_CLK26M), + EXT_PARENT(CLK_PAD_CLK26M), TOP_PARENT(CLK_TOP_UNIVPLL_D6_D2), TOP_PARENT(CLK_TOP_UNIVPLL_D4_D2), TOP_PARENT(CLK_TOP_MAINPLL_D4), @@ -400,7 +391,7 @@ static const struct mtk_parent dsp2_parents[] = { }; static const struct mtk_parent ipu_if_parents[] = { - TOP_PARENT(CLK_TOP_CLK26M), + EXT_PARENT(CLK_PAD_CLK26M), TOP_PARENT(CLK_TOP_UNIVPLL_D6_D2), TOP_PARENT(CLK_TOP_UNIVPLL_D5_D2), TOP_PARENT(CLK_TOP_MAINPLL_D4_D2), @@ -411,14 +402,14 @@ static const struct mtk_parent ipu_if_parents[] = { }; static const struct mtk_parent mfg_parents[] = { - TOP_PARENT(CLK_TOP_CLK26M), + EXT_PARENT(CLK_PAD_CLK26M), TOP_PARENT(CLK_TOP_MAINPLL_D5_D2), TOP_PARENT(CLK_TOP_UNIVPLL_D6), TOP_PARENT(CLK_TOP_UNIVPLL_D7), }; static const struct mtk_parent camtg_parents[] = { - TOP_PARENT(CLK_TOP_CLK26M), + EXT_PARENT(CLK_PAD_CLK26M), TOP_PARENT(CLK_TOP_UNIVPLL_192M_D8), TOP_PARENT(CLK_TOP_UNIVPLL_D6_D8), TOP_PARENT(CLK_TOP_UNIVPLL_192M_D4), @@ -429,12 +420,12 @@ static const struct mtk_parent camtg_parents[] = { }; static const struct mtk_parent uart_parents[] = { - TOP_PARENT(CLK_TOP_CLK26M), + EXT_PARENT(CLK_PAD_CLK26M), TOP_PARENT(CLK_TOP_UNIVPLL_D6_D8), }; static const struct mtk_parent spi_parents[] = { - TOP_PARENT(CLK_TOP_CLK26M), + EXT_PARENT(CLK_PAD_CLK26M), TOP_PARENT(CLK_TOP_MAINPLL_D5_D4), TOP_PARENT(CLK_TOP_MAINPLL_D6_D4), TOP_PARENT(CLK_TOP_MSDCPLL_D4), @@ -445,7 +436,7 @@ static const struct mtk_parent spi_parents[] = { }; static const struct mtk_parent spis_parents[] = { - TOP_PARENT(CLK_TOP_CLK26M), + EXT_PARENT(CLK_PAD_CLK26M), TOP_PARENT(CLK_TOP_UNIVPLL_D6), TOP_PARENT(CLK_TOP_MAINPLL_D6), TOP_PARENT(CLK_TOP_UNIVPLL_D4_D2), @@ -456,14 +447,14 @@ static const struct mtk_parent spis_parents[] = { }; static const struct mtk_parent msdc50_0_h_parents[] = { - TOP_PARENT(CLK_TOP_CLK26M), + EXT_PARENT(CLK_PAD_CLK26M), TOP_PARENT(CLK_TOP_MAINPLL_D4_D2), TOP_PARENT(CLK_TOP_MAINPLL_D6_D2), }; static const struct mtk_parent msdc50_0_parents[] = { - TOP_PARENT(CLK_TOP_CLK26M), - TOP_PARENT(CLK_TOP_MSDCPLL), + EXT_PARENT(CLK_PAD_CLK26M), + APMIXED_PARENT(CLK_APMIXED_MSDCPLL), TOP_PARENT(CLK_TOP_MSDCPLL_D2), TOP_PARENT(CLK_TOP_UNIVPLL_D4_D4), TOP_PARENT(CLK_TOP_MAINPLL_D6_D2), @@ -471,7 +462,7 @@ static const struct mtk_parent msdc50_0_parents[] = { }; static const struct mtk_parent msdc30_parents[] = { - TOP_PARENT(CLK_TOP_CLK26M), + EXT_PARENT(CLK_PAD_CLK26M), TOP_PARENT(CLK_TOP_UNIVPLL_D6_D2), TOP_PARENT(CLK_TOP_MAINPLL_D6_D2), TOP_PARENT(CLK_TOP_MAINPLL_D7_D2), @@ -479,20 +470,20 @@ static const struct mtk_parent msdc30_parents[] = { }; static const struct mtk_parent intdir_parents[] = { - TOP_PARENT(CLK_TOP_CLK26M), + EXT_PARENT(CLK_PAD_CLK26M), TOP_PARENT(CLK_TOP_UNIVPLL_D6), TOP_PARENT(CLK_TOP_MAINPLL_D4), TOP_PARENT(CLK_TOP_UNIVPLL_D4), }; static const struct mtk_parent aud_intbus_parents[] = { - TOP_PARENT(CLK_TOP_CLK26M), + EXT_PARENT(CLK_PAD_CLK26M), TOP_PARENT(CLK_TOP_MAINPLL_D4_D4), TOP_PARENT(CLK_TOP_MAINPLL_D7_D4), }; static const struct mtk_parent audio_h_parents[] = { - TOP_PARENT(CLK_TOP_CLK26M), + EXT_PARENT(CLK_PAD_CLK26M), TOP_PARENT(CLK_TOP_UNIVPLL_D7), TOP_PARENT(CLK_TOP_APLL1), TOP_PARENT(CLK_TOP_APLL2), @@ -500,7 +491,7 @@ static const struct mtk_parent audio_h_parents[] = { static const struct mtk_parent pwrap_ulposc_parents[] = { TOP_PARENT(CLK_TOP_ULPOSC1_D10), - TOP_PARENT(CLK_TOP_CLK26M), + EXT_PARENT(CLK_PAD_CLK26M), TOP_PARENT(CLK_TOP_ULPOSC1_D4), TOP_PARENT(CLK_TOP_ULPOSC1_D7), TOP_PARENT(CLK_TOP_ULPOSC1_D8), @@ -510,13 +501,13 @@ static const struct mtk_parent pwrap_ulposc_parents[] = { }; static const struct mtk_parent atb_parents[] = { - TOP_PARENT(CLK_TOP_CLK26M), + EXT_PARENT(CLK_PAD_CLK26M), TOP_PARENT(CLK_TOP_MAINPLL_D4_D2), TOP_PARENT(CLK_TOP_MAINPLL_D5_D2), }; static const struct mtk_parent pwrmcu_parents[] = { - TOP_PARENT(CLK_TOP_CLK26M), + EXT_PARENT(CLK_PAD_CLK26M), TOP_PARENT(CLK_TOP_MAINPLL_D7_D2), TOP_PARENT(CLK_TOP_MAINPLL_D6_D2), TOP_PARENT(CLK_TOP_MAINPLL_D5_D2), @@ -525,7 +516,7 @@ static const struct mtk_parent pwrmcu_parents[] = { }; static const struct mtk_parent dp_parents[] = { - TOP_PARENT(CLK_TOP_CLK26M), + EXT_PARENT(CLK_PAD_CLK26M), TOP_PARENT(CLK_TOP_TVDPLL1_D2), TOP_PARENT(CLK_TOP_TVDPLL2_D2), TOP_PARENT(CLK_TOP_TVDPLL1_D4), @@ -537,7 +528,7 @@ static const struct mtk_parent dp_parents[] = { }; static const struct mtk_parent disp_pwm_parents[] = { - TOP_PARENT(CLK_TOP_CLK26M), + EXT_PARENT(CLK_PAD_CLK26M), TOP_PARENT(CLK_TOP_UNIVPLL_D6_D4), TOP_PARENT(CLK_TOP_ULPOSC1_D2), TOP_PARENT(CLK_TOP_ULPOSC1_D4), @@ -545,20 +536,20 @@ static const struct mtk_parent disp_pwm_parents[] = { }; static const struct mtk_parent usb_parents[] = { - TOP_PARENT(CLK_TOP_CLK26M), + EXT_PARENT(CLK_PAD_CLK26M), TOP_PARENT(CLK_TOP_UNIVPLL_D5_D4), TOP_PARENT(CLK_TOP_UNIVPLL_D6_D4), TOP_PARENT(CLK_TOP_UNIVPLL_D5_D2), }; static const struct mtk_parent i2c_parents[] = { - TOP_PARENT(CLK_TOP_CLK26M), + EXT_PARENT(CLK_PAD_CLK26M), TOP_PARENT(CLK_TOP_MAINPLL_D4_D8), TOP_PARENT(CLK_TOP_UNIVPLL_D5_D4), }; static const struct mtk_parent seninf_parents[] = { - TOP_PARENT(CLK_TOP_CLK26M), + EXT_PARENT(CLK_PAD_CLK26M), TOP_PARENT(CLK_TOP_UNIVPLL_D4_D4), TOP_PARENT(CLK_TOP_UNIVPLL_D6_D2), TOP_PARENT(CLK_TOP_UNIVPLL_D4_D2), @@ -569,7 +560,7 @@ static const struct mtk_parent seninf_parents[] = { }; static const struct mtk_parent gcpu_parents[] = { - TOP_PARENT(CLK_TOP_CLK26M), + EXT_PARENT(CLK_PAD_CLK26M), TOP_PARENT(CLK_TOP_MAINPLL_D6), TOP_PARENT(CLK_TOP_UNIVPLL_D4_D2), TOP_PARENT(CLK_TOP_MMPLL_D5_D2), @@ -577,14 +568,14 @@ static const struct mtk_parent gcpu_parents[] = { }; static const struct mtk_parent dxcc_parents[] = { - TOP_PARENT(CLK_TOP_CLK26M), + EXT_PARENT(CLK_PAD_CLK26M), TOP_PARENT(CLK_TOP_MAINPLL_D4_D2), TOP_PARENT(CLK_TOP_MAINPLL_D4_D4), TOP_PARENT(CLK_TOP_MAINPLL_D4_D8), }; static const struct mtk_parent dpmaif_parents[] = { - TOP_PARENT(CLK_TOP_CLK26M), + EXT_PARENT(CLK_PAD_CLK26M), TOP_PARENT(CLK_TOP_UNIVPLL_D4_D4), TOP_PARENT(CLK_TOP_MAINPLL_D6), TOP_PARENT(CLK_TOP_MAINPLL_D4_D2), @@ -592,7 +583,7 @@ static const struct mtk_parent dpmaif_parents[] = { }; static const struct mtk_parent aes_fde_parents[] = { - TOP_PARENT(CLK_TOP_CLK26M), + EXT_PARENT(CLK_PAD_CLK26M), TOP_PARENT(CLK_TOP_MAINPLL_D4_D2), TOP_PARENT(CLK_TOP_MAINPLL_D6), TOP_PARENT(CLK_TOP_MAINPLL_D4_D4), @@ -601,7 +592,7 @@ static const struct mtk_parent aes_fde_parents[] = { }; static const struct mtk_parent ufs_parents[] = { - TOP_PARENT(CLK_TOP_CLK26M), + EXT_PARENT(CLK_PAD_CLK26M), TOP_PARENT(CLK_TOP_MAINPLL_D4_D4), TOP_PARENT(CLK_TOP_MAINPLL_D4_D8), TOP_PARENT(CLK_TOP_UNIVPLL_D4_D4), @@ -612,16 +603,16 @@ static const struct mtk_parent ufs_parents[] = { static const struct mtk_parent ufs_tick1us_parents[] = { TOP_PARENT(CLK_TOP_CLK26M_D52), - TOP_PARENT(CLK_TOP_CLK26M), + EXT_PARENT(CLK_PAD_CLK26M), }; static const struct mtk_parent ufs_mp_sap_parents[] = { - TOP_PARENT(CLK_TOP_CLK26M), + EXT_PARENT(CLK_PAD_CLK26M), TOP_PARENT(CLK_TOP_MSDCPLL_D16), }; static const struct mtk_parent venc_parents[] = { - TOP_PARENT(CLK_TOP_CLK26M), + EXT_PARENT(CLK_PAD_CLK26M), TOP_PARENT(CLK_TOP_MMPLL_D4_D2), TOP_PARENT(CLK_TOP_MAINPLL_D6), TOP_PARENT(CLK_TOP_UNIVPLL_D4_D2), @@ -640,7 +631,7 @@ static const struct mtk_parent venc_parents[] = { }; static const struct mtk_parent vdec_parents[] = { - TOP_PARENT(CLK_TOP_CLK26M), + EXT_PARENT(CLK_PAD_CLK26M), TOP_PARENT(CLK_TOP_MAINPLL_D5_D2), TOP_PARENT(CLK_TOP_MMPLL_D6_D2), TOP_PARENT(CLK_TOP_UNIVPLL_D4_D2), @@ -648,7 +639,7 @@ static const struct mtk_parent vdec_parents[] = { TOP_PARENT(CLK_TOP_MAINPLL_D5), TOP_PARENT(CLK_TOP_MMPLL_D6), TOP_PARENT(CLK_TOP_MMPLL_D5), - TOP_PARENT(CLK_TOP_VDECPLL), + APMIXED_PARENT(CLK_APMIXED_VDECPLL), TOP_PARENT(CLK_TOP_UNIVPLL_D4), TOP_PARENT(CLK_TOP_MMPLL_D4), TOP_PARENT(CLK_TOP_UNIVPLL_D6_D2), @@ -659,51 +650,51 @@ static const struct mtk_parent vdec_parents[] = { }; static const struct mtk_parent pwm_parents[] = { - TOP_PARENT(CLK_TOP_CLK26M), + EXT_PARENT(CLK_PAD_CLK26M), TOP_PARENT(CLK_TOP_UNIVPLL_D4_D8), }; static const struct mtk_parent mcupm_parents[] = { - TOP_PARENT(CLK_TOP_CLK26M), + EXT_PARENT(CLK_PAD_CLK26M), TOP_PARENT(CLK_TOP_MAINPLL_D6_D2), TOP_PARENT(CLK_TOP_MAINPLL_D7_D4), }; static const struct mtk_parent spmi_parents[] = { - TOP_PARENT(CLK_TOP_CLK26M), + EXT_PARENT(CLK_PAD_CLK26M), TOP_PARENT(CLK_TOP_CLK26M_D2), TOP_PARENT(CLK_TOP_ULPOSC1_D8), TOP_PARENT(CLK_TOP_ULPOSC1_D10), TOP_PARENT(CLK_TOP_ULPOSC1_D16), TOP_PARENT(CLK_TOP_ULPOSC1_D7), - TOP_PARENT(CLK_TOP_CLK32K), + EXT_PARENT(CLK_PAD_CLK32K), TOP_PARENT(CLK_TOP_MAINPLL_D7_D8), TOP_PARENT(CLK_TOP_MAINPLL_D6_D8), TOP_PARENT(CLK_TOP_MAINPLL_D5_D8), }; static const struct mtk_parent dvfsrc_parents[] = { - TOP_PARENT(CLK_TOP_CLK26M), + EXT_PARENT(CLK_PAD_CLK26M), TOP_PARENT(CLK_TOP_ULPOSC1_D10), TOP_PARENT(CLK_TOP_UNIVPLL_D6_D8), TOP_PARENT(CLK_TOP_MSDCPLL_D16), }; static const struct mtk_parent tl_parents[] = { - TOP_PARENT(CLK_TOP_CLK26M), + EXT_PARENT(CLK_PAD_CLK26M), TOP_PARENT(CLK_TOP_UNIVPLL_D5_D4), TOP_PARENT(CLK_TOP_MAINPLL_D4_D4), }; static const struct mtk_parent dsi_occ_parents[] = { - TOP_PARENT(CLK_TOP_CLK26M), + EXT_PARENT(CLK_PAD_CLK26M), TOP_PARENT(CLK_TOP_MAINPLL_D6_D2), TOP_PARENT(CLK_TOP_UNIVPLL_D5_D2), TOP_PARENT(CLK_TOP_UNIVPLL_D4_D2), }; static const struct mtk_parent wpe_vpp_parents[] = { - TOP_PARENT(CLK_TOP_CLK26M), + EXT_PARENT(CLK_PAD_CLK26M), TOP_PARENT(CLK_TOP_MAINPLL_D5_D2), TOP_PARENT(CLK_TOP_MMPLL_D6_D2), TOP_PARENT(CLK_TOP_UNIVPLL_D5_D2), @@ -716,69 +707,69 @@ static const struct mtk_parent wpe_vpp_parents[] = { TOP_PARENT(CLK_TOP_MAINPLL_D5), TOP_PARENT(CLK_TOP_UNIVPLL_D5), TOP_PARENT(CLK_TOP_MAINPLL_D4), - TOP_PARENT(CLK_TOP_TVDPLL1), + APMIXED_PARENT(CLK_APMIXED_TVDPLL1), TOP_PARENT(CLK_TOP_UNIVPLL_D4), }; static const struct mtk_parent hdcp_parents[] = { - TOP_PARENT(CLK_TOP_CLK26M), + EXT_PARENT(CLK_PAD_CLK26M), TOP_PARENT(CLK_TOP_UNIVPLL_D4_D8), TOP_PARENT(CLK_TOP_MAINPLL_D5_D8), TOP_PARENT(CLK_TOP_UNIVPLL_D6_D4), }; static const struct mtk_parent hdcp_24m_parents[] = { - TOP_PARENT(CLK_TOP_CLK26M), + EXT_PARENT(CLK_PAD_CLK26M), TOP_PARENT(CLK_TOP_UNIVPLL_192M_D4), TOP_PARENT(CLK_TOP_UNIVPLL_192M_D8), TOP_PARENT(CLK_TOP_UNIVPLL_D6_D8), }; static const struct mtk_parent hd20_dacr_ref_parents[] = { - TOP_PARENT(CLK_TOP_CLK26M), + EXT_PARENT(CLK_PAD_CLK26M), TOP_PARENT(CLK_TOP_UNIVPLL_D4_D2), TOP_PARENT(CLK_TOP_UNIVPLL_D4_D4), TOP_PARENT(CLK_TOP_UNIVPLL_D4_D8), }; static const struct mtk_parent hd20_hdcp_c_parents[] = { - TOP_PARENT(CLK_TOP_CLK26M), + EXT_PARENT(CLK_PAD_CLK26M), TOP_PARENT(CLK_TOP_MSDCPLL_D4), TOP_PARENT(CLK_TOP_UNIVPLL_D4_D8), TOP_PARENT(CLK_TOP_UNIVPLL_D6_D8), }; static const struct mtk_parent hdmi_xtal_parents[] = { - TOP_PARENT(CLK_TOP_CLK26M), + EXT_PARENT(CLK_PAD_CLK26M), TOP_PARENT(CLK_TOP_CLK26M_D2), }; static const struct mtk_parent hdmi_apb_parents[] = { - TOP_PARENT(CLK_TOP_CLK26M), + EXT_PARENT(CLK_PAD_CLK26M), TOP_PARENT(CLK_TOP_UNIVPLL_D6_D4), TOP_PARENT(CLK_TOP_MSDCPLL_D2), }; static const struct mtk_parent snps_eth_250m_parents[] = { - TOP_PARENT(CLK_TOP_CLK26M), + EXT_PARENT(CLK_PAD_CLK26M), TOP_PARENT(CLK_TOP_ETHPLL_D2), }; static const struct mtk_parent snps_eth_62p4m_ptp_parents[] = { TOP_PARENT(CLK_TOP_APLL2_D3), TOP_PARENT(CLK_TOP_APLL1_D3), - TOP_PARENT(CLK_TOP_CLK26M), + EXT_PARENT(CLK_PAD_CLK26M), TOP_PARENT(CLK_TOP_ETHPLL_D8), }; static const struct mtk_parent snps_eth_50m_rmii_parents[] = { - TOP_PARENT(CLK_TOP_CLK26M), + EXT_PARENT(CLK_PAD_CLK26M), TOP_PARENT(CLK_TOP_ETHPLL_D10), }; static const struct mtk_parent dgi_out_parents[] = { - TOP_PARENT(CLK_TOP_CLK26M), - TOP_PARENT(CLK_TOP_DGIPLL), + EXT_PARENT(CLK_PAD_CLK26M), + APMIXED_PARENT(CLK_APMIXED_DGIPLL), TOP_PARENT(CLK_TOP_DGIPLL_D2), TOP_PARENT(CLK_TOP_IN_DGI), TOP_PARENT(CLK_TOP_IN_DGI_D2), @@ -786,8 +777,8 @@ static const struct mtk_parent dgi_out_parents[] = { }; static const struct mtk_parent nna_parents[] = { - TOP_PARENT(CLK_TOP_CLK26M), - TOP_PARENT(CLK_TOP_NNAPLL), + EXT_PARENT(CLK_PAD_CLK26M), + APMIXED_PARENT(CLK_APMIXED_NNAPLL), TOP_PARENT(CLK_TOP_UNIVPLL_D4), TOP_PARENT(CLK_TOP_MAINPLL_D4), TOP_PARENT(CLK_TOP_UNIVPLL_D5), @@ -801,7 +792,7 @@ static const struct mtk_parent nna_parents[] = { }; static const struct mtk_parent adsp_parents[] = { - TOP_PARENT(CLK_TOP_CLK26M), + EXT_PARENT(CLK_PAD_CLK26M), TOP_PARENT(CLK_TOP_CLK26M_D2), TOP_PARENT(CLK_TOP_MAINPLL_D6), TOP_PARENT(CLK_TOP_MAINPLL_D5_D2), @@ -809,66 +800,66 @@ static const struct mtk_parent adsp_parents[] = { TOP_PARENT(CLK_TOP_UNIVPLL_D4), TOP_PARENT(CLK_TOP_UNIVPLL_D6), TOP_PARENT(CLK_TOP_ULPOSC1), - TOP_PARENT(CLK_TOP_ADSPPLL), + APMIXED_PARENT(CLK_APMIXED_ADSPPLL), TOP_PARENT(CLK_TOP_ADSPPLL_D2), TOP_PARENT(CLK_TOP_ADSPPLL_D4), TOP_PARENT(CLK_TOP_ADSPPLL_D8), }; static const struct mtk_parent asm_parents[] = { - TOP_PARENT(CLK_TOP_CLK26M), + EXT_PARENT(CLK_PAD_CLK26M), TOP_PARENT(CLK_TOP_UNIVPLL_D6_D4), TOP_PARENT(CLK_TOP_UNIVPLL_D6_D2), TOP_PARENT(CLK_TOP_MAINPLL_D5_D2), }; static const struct mtk_parent apll1_parents[] = { - TOP_PARENT(CLK_TOP_CLK26M), + EXT_PARENT(CLK_PAD_CLK26M), TOP_PARENT(CLK_TOP_APLL1_D4), }; static const struct mtk_parent apll2_parents[] = { - TOP_PARENT(CLK_TOP_CLK26M), + EXT_PARENT(CLK_PAD_CLK26M), TOP_PARENT(CLK_TOP_APLL2_D4), }; static const struct mtk_parent apll3_parents[] = { - TOP_PARENT(CLK_TOP_CLK26M), + EXT_PARENT(CLK_PAD_CLK26M), TOP_PARENT(CLK_TOP_APLL3_D4), }; static const struct mtk_parent apll4_parents[] = { - TOP_PARENT(CLK_TOP_CLK26M), + EXT_PARENT(CLK_PAD_CLK26M), TOP_PARENT(CLK_TOP_APLL4_D4), }; static const struct mtk_parent apll5_parents[] = { - TOP_PARENT(CLK_TOP_CLK26M), + EXT_PARENT(CLK_PAD_CLK26M), TOP_PARENT(CLK_TOP_APLL5_D4), }; static const struct mtk_parent i2s_parents[] = { - TOP_PARENT(CLK_TOP_CLK26M), + EXT_PARENT(CLK_PAD_CLK26M), TOP_PARENT(CLK_TOP_APLL1), TOP_PARENT(CLK_TOP_APLL2), TOP_PARENT(CLK_TOP_APLL3), TOP_PARENT(CLK_TOP_APLL4), TOP_PARENT(CLK_TOP_APLL5), - TOP_PARENT(CLK_TOP_HDMIRX_APLL), + APMIXED_PARENT(CLK_APMIXED_HDMIRX_APLL), }; static const struct mtk_parent a1sys_hp_parents[] = { - TOP_PARENT(CLK_TOP_CLK26M), + EXT_PARENT(CLK_PAD_CLK26M), TOP_PARENT(CLK_TOP_APLL1_D4), }; static const struct mtk_parent a2sys_parents[] = { - TOP_PARENT(CLK_TOP_CLK26M), + EXT_PARENT(CLK_PAD_CLK26M), TOP_PARENT(CLK_TOP_APLL2_D4), }; static const struct mtk_parent a3sys_parents[] = { - TOP_PARENT(CLK_TOP_CLK26M), + EXT_PARENT(CLK_PAD_CLK26M), TOP_PARENT(CLK_TOP_APLL3_D4), TOP_PARENT(CLK_TOP_APLL4_D4), TOP_PARENT(CLK_TOP_APLL5_D4), @@ -878,7 +869,7 @@ static const struct mtk_parent a3sys_parents[] = { }; static const struct mtk_parent spinfi_b_parents[] = { - TOP_PARENT(CLK_TOP_CLK26M), + EXT_PARENT(CLK_PAD_CLK26M), TOP_PARENT(CLK_TOP_UNIVPLL_D6_D8), TOP_PARENT(CLK_TOP_UNIVPLL_D5_D8), TOP_PARENT(CLK_TOP_MAINPLL_D4_D8), @@ -889,7 +880,7 @@ static const struct mtk_parent spinfi_b_parents[] = { }; static const struct mtk_parent nfi1x_parents[] = { - TOP_PARENT(CLK_TOP_CLK26M), + EXT_PARENT(CLK_PAD_CLK26M), TOP_PARENT(CLK_TOP_UNIVPLL_D5_D4), TOP_PARENT(CLK_TOP_MAINPLL_D7_D4), TOP_PARENT(CLK_TOP_MAINPLL_D6_D4), @@ -900,7 +891,7 @@ static const struct mtk_parent nfi1x_parents[] = { }; static const struct mtk_parent ecc_parents[] = { - TOP_PARENT(CLK_TOP_CLK26M), + EXT_PARENT(CLK_PAD_CLK26M), TOP_PARENT(CLK_TOP_MAINPLL_D4_D4), TOP_PARENT(CLK_TOP_MAINPLL_D5_D2), TOP_PARENT(CLK_TOP_MAINPLL_D4_D2), @@ -909,7 +900,7 @@ static const struct mtk_parent ecc_parents[] = { }; static const struct mtk_parent audio_local_bus_parents[] = { - TOP_PARENT(CLK_TOP_CLK26M), + EXT_PARENT(CLK_PAD_CLK26M), TOP_PARENT(CLK_TOP_CLK26M_D2), TOP_PARENT(CLK_TOP_MAINPLL_D4_D4), TOP_PARENT(CLK_TOP_MAINPLL_D7_D2), @@ -924,14 +915,14 @@ static const struct mtk_parent audio_local_bus_parents[] = { }; static const struct mtk_parent spinor_parents[] = { - TOP_PARENT(CLK_TOP_CLK26M), + EXT_PARENT(CLK_PAD_CLK26M), TOP_PARENT(CLK_TOP_CLK26M_D2), TOP_PARENT(CLK_TOP_MAINPLL_D7_D8), TOP_PARENT(CLK_TOP_UNIVPLL_D6_D8), }; static const struct mtk_parent dvio_dgi_ref_parents[] = { - TOP_PARENT(CLK_TOP_CLK26M), + EXT_PARENT(CLK_PAD_CLK26M), TOP_PARENT(CLK_TOP_IN_DGI), TOP_PARENT(CLK_TOP_IN_DGI_D2), TOP_PARENT(CLK_TOP_IN_DGI_D4), @@ -956,7 +947,7 @@ static const struct mtk_parent ulposc_core_parents[] = { static const struct mtk_parent srck_parents[] = { TOP_PARENT(CLK_TOP_ULPOSC1_D10), - TOP_PARENT(CLK_TOP_CLK26M), + EXT_PARENT(CLK_PAD_CLK26M), }; static const struct mtk_composite top_muxes[] = { @@ -1133,9 +1124,13 @@ static const struct mtk_gate_regs top1_cg_regs = { GATE_FLAGS(_id, _parent, &top0_cg_regs, _shift, \ CLK_GATE_NO_SETCLR_INV | CLK_PARENT_TOPCKGEN) +#define GATE_TOP0E(_id, _parent, _shift) \ + GATE_FLAGS(_id, _parent, &top0_cg_regs, _shift, \ + CLK_GATE_NO_SETCLR_INV | CLK_PARENT_EXT) + #define GATE_TOP1(_id, _parent, _shift) \ GATE_FLAGS(_id, _parent, &top1_cg_regs, _shift, \ - CLK_GATE_NO_SETCLR_INV | CLK_PARENT_TOPCKGEN) + CLK_GATE_NO_SETCLR_INV | CLK_PARENT_EXT) static const struct mtk_gate top_cg_clks[] = { /* TOP0 */ @@ -1144,9 +1139,9 @@ static const struct mtk_gate top_cg_clks[] = { GATE_TOP0(CLK_TOP_CFG_VDO0, CLK_TOP_VPP, 2), GATE_TOP0(CLK_TOP_CFG_VDO1, CLK_TOP_VPP, 3), GATE_TOP0(CLK_TOP_CFG_UNIPLL_SES, CLK_TOP_UNIVPLL_D2, 4), - GATE_TOP0(CLK_TOP_CFG_26M_VPP0, CLK_TOP_CLK26M, 5), - GATE_TOP0(CLK_TOP_CFG_26M_VPP1, CLK_TOP_CLK26M, 6), - GATE_TOP0(CLK_TOP_CFG_26M_AUD, CLK_TOP_CLK26M, 9), + GATE_TOP0E(CLK_TOP_CFG_26M_VPP0, CLK_PAD_CLK26M, 5), + GATE_TOP0E(CLK_TOP_CFG_26M_VPP1, CLK_PAD_CLK26M, 6), + GATE_TOP0E(CLK_TOP_CFG_26M_AUD, CLK_PAD_CLK26M, 9), /* * cfg_axi_east, cfg_axi_east_north, cfg_axi_north and cfg_axi_south * are peripheral bus clock branches. @@ -1157,275 +1152,266 @@ static const struct mtk_gate top_cg_clks[] = { GATE_TOP0(CLK_TOP_CFG_AXI_SOUTH, CLK_TOP_AXI, 13), GATE_TOP0(CLK_TOP_CFG_EXT_TEST, CLK_TOP_MSDCPLL_D2, 15), /* TOP1 */ - GATE_TOP1(CLK_TOP_SSUSB_REF, CLK_TOP_CLK26M, 0), - GATE_TOP1(CLK_TOP_SSUSB_PHY_REF, CLK_TOP_CLK26M, 1), - GATE_TOP1(CLK_TOP_SSUSB_P1_REF, CLK_TOP_CLK26M, 2), - GATE_TOP1(CLK_TOP_SSUSB_PHY_P1_REF, CLK_TOP_CLK26M, 3), - GATE_TOP1(CLK_TOP_SSUSB_P2_REF, CLK_TOP_CLK26M, 4), - GATE_TOP1(CLK_TOP_SSUSB_PHY_P2_REF, CLK_TOP_CLK26M, 5), - GATE_TOP1(CLK_TOP_SSUSB_P3_REF, CLK_TOP_CLK26M, 6), - GATE_TOP1(CLK_TOP_SSUSB_PHY_P3_REF, CLK_TOP_CLK26M, 7), + GATE_TOP1(CLK_TOP_SSUSB_REF, CLK_PAD_CLK26M, 0), + GATE_TOP1(CLK_TOP_SSUSB_PHY_REF, CLK_PAD_CLK26M, 1), + GATE_TOP1(CLK_TOP_SSUSB_P1_REF, CLK_PAD_CLK26M, 2), + GATE_TOP1(CLK_TOP_SSUSB_PHY_P1_REF, CLK_PAD_CLK26M, 3), + GATE_TOP1(CLK_TOP_SSUSB_P2_REF, CLK_PAD_CLK26M, 4), + GATE_TOP1(CLK_TOP_SSUSB_PHY_P2_REF, CLK_PAD_CLK26M, 5), + GATE_TOP1(CLK_TOP_SSUSB_P3_REF, CLK_PAD_CLK26M, 6), + GATE_TOP1(CLK_TOP_SSUSB_PHY_P3_REF, CLK_PAD_CLK26M, 7), }; static const int mt8195_id_top_offs_map[] = { - [0 ... CLK_TOP_FULL_NR_CLK] = -1, + [0 ... CLK_TOP_NR_CLK - 1] = -1, /* FIXED */ - [CLK_TOP_IN_DGI] = 0, - [CLK_TOP_ULPOSC1] = 1, - [CLK_TOP_ULPOSC2] = 2, - [CLK_TOP_MEM_466M] = 3, - [CLK_TOP_MPHONE_SLAVE_B] = 4, - [CLK_TOP_PEXTP_PIPE] = 5, - [CLK_TOP_UFS_RX_SYMBOL] = 6, - [CLK_TOP_UFS_TX_SYMBOL] = 7, - [CLK_TOP_SSUSB_U3PHY_P1_P_P0] = 8, - [CLK_TOP_UFS_RX_SYMBOL1] = 9, - [CLK_TOP_FPC] = 10, - [CLK_TOP_HDMIRX_P] = 11, - [CLK_TOP_CLK26M] = 12, - [CLK_TOP_CLK32K] = 13, + [CLK_TOP_IN_DGI] = 0, + [CLK_TOP_ULPOSC1] = 1, + [CLK_TOP_ULPOSC2] = 2, + [CLK_TOP_MEM_466M] = 3, + [CLK_TOP_MPHONE_SLAVE_B] = 4, + [CLK_TOP_PEXTP_PIPE] = 5, + [CLK_TOP_UFS_RX_SYMBOL] = 6, + [CLK_TOP_UFS_TX_SYMBOL] = 7, + [CLK_TOP_SSUSB_U3PHY_P1_P_P0] = 8, + [CLK_TOP_UFS_RX_SYMBOL1] = 9, + [CLK_TOP_FPC] = 10, + [CLK_TOP_HDMIRX_P] = 11, /* FACTOR */ - [CLK_TOP_CLK26M_D2] = 14, - [CLK_TOP_CLK26M_D52] = 15, - [CLK_TOP_IN_DGI_D2] = 16, - [CLK_TOP_IN_DGI_D4] = 17, - [CLK_TOP_IN_DGI_D6] = 18, - [CLK_TOP_IN_DGI_D8] = 19, - [CLK_TOP_MAINPLL_D3] = 20, - [CLK_TOP_MAINPLL_D4] = 21, - [CLK_TOP_MAINPLL_D4_D2] = 22, - [CLK_TOP_MAINPLL_D4_D4] = 23, - [CLK_TOP_MAINPLL_D4_D8] = 24, - [CLK_TOP_MAINPLL_D5] = 25, - [CLK_TOP_MAINPLL_D5_D2] = 26, - [CLK_TOP_MAINPLL_D5_D4] = 27, - [CLK_TOP_MAINPLL_D5_D8] = 28, - [CLK_TOP_MAINPLL_D6] = 29, - [CLK_TOP_MAINPLL_D6_D2] = 30, - [CLK_TOP_MAINPLL_D6_D4] = 31, - [CLK_TOP_MAINPLL_D6_D8] = 32, - [CLK_TOP_MAINPLL_D7] = 33, - [CLK_TOP_MAINPLL_D7_D2] = 34, - [CLK_TOP_MAINPLL_D7_D4] = 35, - [CLK_TOP_MAINPLL_D7_D8] = 36, - [CLK_TOP_MAINPLL_D9] = 37, - [CLK_TOP_UNIVPLL_D2] = 38, - [CLK_TOP_UNIVPLL_D3] = 39, - [CLK_TOP_UNIVPLL_D4] = 40, - [CLK_TOP_UNIVPLL_D4_D2] = 41, - [CLK_TOP_UNIVPLL_D4_D4] = 42, - [CLK_TOP_UNIVPLL_D4_D8] = 43, - [CLK_TOP_UNIVPLL_D5] = 44, - [CLK_TOP_UNIVPLL_D5_D2] = 45, - [CLK_TOP_UNIVPLL_D5_D4] = 46, - [CLK_TOP_UNIVPLL_D5_D8] = 47, - [CLK_TOP_UNIVPLL_D6] = 48, - [CLK_TOP_UNIVPLL_D6_D2] = 49, - [CLK_TOP_UNIVPLL_D6_D4] = 50, - [CLK_TOP_UNIVPLL_D6_D8] = 51, - [CLK_TOP_UNIVPLL_D6_D16] = 52, - [CLK_TOP_UNIVPLL_D7] = 53, - [CLK_TOP_UNIVPLL_192M] = 54, - [CLK_TOP_UNIVPLL_192M_D4] = 55, - [CLK_TOP_UNIVPLL_192M_D8] = 56, - [CLK_TOP_UNIVPLL_192M_D16] = 57, - [CLK_TOP_UNIVPLL_192M_D32] = 58, - [CLK_TOP_APLL1_D3] = 59, - [CLK_TOP_APLL1_D4] = 60, - [CLK_TOP_APLL2_D3] = 61, - [CLK_TOP_APLL2_D4] = 62, - [CLK_TOP_APLL3_D4] = 63, - [CLK_TOP_APLL4_D4] = 64, - [CLK_TOP_APLL5_D4] = 65, - [CLK_TOP_HDMIRX_APLL_D3] = 66, - [CLK_TOP_HDMIRX_APLL_D4] = 67, - [CLK_TOP_HDMIRX_APLL_D6] = 68, - [CLK_TOP_MMPLL_D4] = 69, - [CLK_TOP_MMPLL_D4_D2] = 70, - [CLK_TOP_MMPLL_D4_D4] = 71, - [CLK_TOP_MMPLL_D5] = 72, - [CLK_TOP_MMPLL_D5_D2] = 73, - [CLK_TOP_MMPLL_D5_D4] = 74, - [CLK_TOP_MMPLL_D6] = 75, - [CLK_TOP_MMPLL_D6_D2] = 76, - [CLK_TOP_MMPLL_D7] = 77, - [CLK_TOP_MMPLL_D9] = 78, - [CLK_TOP_TVDPLL1] = 79, - [CLK_TOP_TVDPLL1_D2] = 80, - [CLK_TOP_TVDPLL1_D4] = 81, - [CLK_TOP_TVDPLL1_D8] = 82, - [CLK_TOP_TVDPLL1_D16] = 83, - [CLK_TOP_TVDPLL2] = 84, - [CLK_TOP_TVDPLL2_D2] = 85, - [CLK_TOP_TVDPLL2_D4] = 86, - [CLK_TOP_TVDPLL2_D8] = 87, - [CLK_TOP_TVDPLL2_D16] = 88, - [CLK_TOP_MSDCPLL] = 89, - [CLK_TOP_MSDCPLL_D2] = 90, - [CLK_TOP_MSDCPLL_D4] = 91, - [CLK_TOP_MSDCPLL_D16] = 92, - [CLK_TOP_ETHPLL_D2] = 93, - [CLK_TOP_ETHPLL_D8] = 94, - [CLK_TOP_ETHPLL_D10] = 95, - [CLK_TOP_DGIPLL] = 96, - [CLK_TOP_DGIPLL_D2] = 97, - [CLK_TOP_ULPOSC1_D2] = 98, - [CLK_TOP_ULPOSC1_D4] = 99, - [CLK_TOP_ULPOSC1_D7] = 100, - [CLK_TOP_ULPOSC1_D8] = 101, - [CLK_TOP_ULPOSC1_D10] = 102, - [CLK_TOP_ULPOSC1_D16] = 103, - [CLK_TOP_ADSPPLL] = 104, - [CLK_TOP_ADSPPLL_D2] = 105, - [CLK_TOP_ADSPPLL_D4] = 106, - [CLK_TOP_ADSPPLL_D8] = 107, - [CLK_TOP_IMGPLL] = 108, - [CLK_TOP_VDECPLL] = 109, - [CLK_TOP_NNAPLL] = 110, - [CLK_TOP_HDMIRX_APLL] = 111, + [CLK_TOP_CLK26M_D2] = 12, + [CLK_TOP_CLK26M_D52] = 13, + [CLK_TOP_IN_DGI_D2] = 14, + [CLK_TOP_IN_DGI_D4] = 15, + [CLK_TOP_IN_DGI_D6] = 16, + [CLK_TOP_IN_DGI_D8] = 17, + [CLK_TOP_MAINPLL_D3] = 18, + [CLK_TOP_MAINPLL_D4] = 19, + [CLK_TOP_MAINPLL_D4_D2] = 20, + [CLK_TOP_MAINPLL_D4_D4] = 21, + [CLK_TOP_MAINPLL_D4_D8] = 22, + [CLK_TOP_MAINPLL_D5] = 23, + [CLK_TOP_MAINPLL_D5_D2] = 24, + [CLK_TOP_MAINPLL_D5_D4] = 25, + [CLK_TOP_MAINPLL_D5_D8] = 26, + [CLK_TOP_MAINPLL_D6] = 27, + [CLK_TOP_MAINPLL_D6_D2] = 28, + [CLK_TOP_MAINPLL_D6_D4] = 29, + [CLK_TOP_MAINPLL_D6_D8] = 30, + [CLK_TOP_MAINPLL_D7] = 31, + [CLK_TOP_MAINPLL_D7_D2] = 32, + [CLK_TOP_MAINPLL_D7_D4] = 33, + [CLK_TOP_MAINPLL_D7_D8] = 34, + [CLK_TOP_MAINPLL_D9] = 35, + [CLK_TOP_UNIVPLL_D2] = 36, + [CLK_TOP_UNIVPLL_D3] = 37, + [CLK_TOP_UNIVPLL_D4] = 38, + [CLK_TOP_UNIVPLL_D4_D2] = 39, + [CLK_TOP_UNIVPLL_D4_D4] = 40, + [CLK_TOP_UNIVPLL_D4_D8] = 41, + [CLK_TOP_UNIVPLL_D5] = 42, + [CLK_TOP_UNIVPLL_D5_D2] = 43, + [CLK_TOP_UNIVPLL_D5_D4] = 44, + [CLK_TOP_UNIVPLL_D5_D8] = 45, + [CLK_TOP_UNIVPLL_D6] = 46, + [CLK_TOP_UNIVPLL_D6_D2] = 47, + [CLK_TOP_UNIVPLL_D6_D4] = 48, + [CLK_TOP_UNIVPLL_D6_D8] = 49, + [CLK_TOP_UNIVPLL_D6_D16] = 50, + [CLK_TOP_UNIVPLL_D7] = 51, + [CLK_TOP_UNIVPLL_192M] = 52, + [CLK_TOP_UNIVPLL_192M_D4] = 53, + [CLK_TOP_UNIVPLL_192M_D8] = 54, + [CLK_TOP_UNIVPLL_192M_D16] = 55, + [CLK_TOP_UNIVPLL_192M_D32] = 56, + [CLK_TOP_APLL1_D3] = 57, + [CLK_TOP_APLL1_D4] = 58, + [CLK_TOP_APLL2_D3] = 59, + [CLK_TOP_APLL2_D4] = 60, + [CLK_TOP_APLL3_D4] = 61, + [CLK_TOP_APLL4_D4] = 62, + [CLK_TOP_APLL5_D4] = 63, + [CLK_TOP_HDMIRX_APLL_D3] = 64, + [CLK_TOP_HDMIRX_APLL_D4] = 65, + [CLK_TOP_HDMIRX_APLL_D6] = 66, + [CLK_TOP_MMPLL_D4] = 67, + [CLK_TOP_MMPLL_D4_D2] = 68, + [CLK_TOP_MMPLL_D4_D4] = 69, + [CLK_TOP_MMPLL_D5] = 70, + [CLK_TOP_MMPLL_D5_D2] = 71, + [CLK_TOP_MMPLL_D5_D4] = 72, + [CLK_TOP_MMPLL_D6] = 73, + [CLK_TOP_MMPLL_D6_D2] = 74, + [CLK_TOP_MMPLL_D7] = 75, + [CLK_TOP_MMPLL_D9] = 76, + [CLK_TOP_TVDPLL1_D2] = 77, + [CLK_TOP_TVDPLL1_D4] = 78, + [CLK_TOP_TVDPLL1_D8] = 79, + [CLK_TOP_TVDPLL1_D16] = 80, + [CLK_TOP_TVDPLL2_D2] = 81, + [CLK_TOP_TVDPLL2_D4] = 82, + [CLK_TOP_TVDPLL2_D8] = 83, + [CLK_TOP_TVDPLL2_D16] = 84, + [CLK_TOP_MSDCPLL_D2] = 85, + [CLK_TOP_MSDCPLL_D4] = 86, + [CLK_TOP_MSDCPLL_D16] = 87, + [CLK_TOP_ETHPLL_D2] = 88, + [CLK_TOP_ETHPLL_D8] = 89, + [CLK_TOP_ETHPLL_D10] = 90, + [CLK_TOP_DGIPLL_D2] = 91, + [CLK_TOP_ULPOSC1_D2] = 92, + [CLK_TOP_ULPOSC1_D4] = 93, + [CLK_TOP_ULPOSC1_D7] = 94, + [CLK_TOP_ULPOSC1_D8] = 95, + [CLK_TOP_ULPOSC1_D10] = 96, + [CLK_TOP_ULPOSC1_D16] = 97, + [CLK_TOP_ADSPPLL_D2] = 98, + [CLK_TOP_ADSPPLL_D4] = 99, + [CLK_TOP_ADSPPLL_D8] = 100, /* MUX */ - [CLK_TOP_AXI] = 112, - [CLK_TOP_SPM] = 113, - [CLK_TOP_SCP] = 114, - [CLK_TOP_BUS_AXIMEM] = 115, - [CLK_TOP_VPP] = 116, - [CLK_TOP_ETHDR] = 117, - [CLK_TOP_IPE] = 118, - [CLK_TOP_CAM] = 119, - [CLK_TOP_CCU] = 120, - [CLK_TOP_IMG] = 121, - [CLK_TOP_CAMTM] = 122, - [CLK_TOP_DSP] = 123, - [CLK_TOP_DSP1] = 124, - [CLK_TOP_DSP2] = 125, - [CLK_TOP_DSP3] = 126, - [CLK_TOP_DSP4] = 127, - [CLK_TOP_DSP5] = 128, - [CLK_TOP_DSP6] = 129, - [CLK_TOP_DSP7] = 130, - [CLK_TOP_IPU_IF] = 131, - [CLK_TOP_MFG_CORE_TMP] = 132, - [CLK_TOP_CAMTG] = 133, - [CLK_TOP_CAMTG2] = 134, - [CLK_TOP_CAMTG3] = 135, - [CLK_TOP_CAMTG4] = 136, - [CLK_TOP_CAMTG5] = 137, - [CLK_TOP_UART] = 138, - [CLK_TOP_SPI] = 139, - [CLK_TOP_SPIS] = 140, - [CLK_TOP_MSDC50_0_HCLK] = 141, - [CLK_TOP_MSDC50_0] = 142, - [CLK_TOP_MSDC30_1] = 143, - [CLK_TOP_MSDC30_2] = 144, - [CLK_TOP_INTDIR] = 145, - [CLK_TOP_AUD_INTBUS] = 146, - [CLK_TOP_AUDIO_H] = 147, - [CLK_TOP_PWRAP_ULPOSC] = 148, - [CLK_TOP_ATB] = 149, - [CLK_TOP_PWRMCU] = 150, - [CLK_TOP_DP] = 151, - [CLK_TOP_EDP] = 152, - [CLK_TOP_DPI] = 153, - [CLK_TOP_DISP_PWM0] = 154, - [CLK_TOP_DISP_PWM1] = 155, - [CLK_TOP_USB_TOP] = 156, - [CLK_TOP_SSUSB_XHCI] = 157, - [CLK_TOP_USB_TOP_1P] = 158, - [CLK_TOP_SSUSB_XHCI_1P] = 159, - [CLK_TOP_USB_TOP_2P] = 160, - [CLK_TOP_SSUSB_XHCI_2P] = 161, - [CLK_TOP_USB_TOP_3P] = 162, - [CLK_TOP_SSUSB_XHCI_3P] = 163, - [CLK_TOP_I2C] = 164, - [CLK_TOP_SENINF] = 165, - [CLK_TOP_SENINF1] = 166, - [CLK_TOP_SENINF2] = 167, - [CLK_TOP_SENINF3] = 168, - [CLK_TOP_GCPU] = 169, - [CLK_TOP_DXCC] = 170, - [CLK_TOP_DPMAIF_MAIN] = 171, - [CLK_TOP_AES_UFSFDE] = 172, - [CLK_TOP_UFS] = 173, - [CLK_TOP_UFS_TICK1US] = 174, - [CLK_TOP_UFS_MP_SAP_CFG] = 175, - [CLK_TOP_VENC] = 176, - [CLK_TOP_VDEC] = 177, - [CLK_TOP_PWM] = 178, - [CLK_TOP_MCUPM] = 179, - [CLK_TOP_SPMI_P_MST] = 180, - [CLK_TOP_SPMI_M_MST] = 181, - [CLK_TOP_DVFSRC] = 182, - [CLK_TOP_TL] = 183, - [CLK_TOP_TL_P1] = 184, - [CLK_TOP_AES_MSDCFDE] = 185, - [CLK_TOP_DSI_OCC] = 186, - [CLK_TOP_WPE_VPP] = 187, - [CLK_TOP_HDCP] = 188, - [CLK_TOP_HDCP_24M] = 189, - [CLK_TOP_HD20_DACR_REF_CLK] = 190, - [CLK_TOP_HD20_HDCP_CCLK] = 191, - [CLK_TOP_HDMI_XTAL] = 192, - [CLK_TOP_HDMI_APB] = 193, - [CLK_TOP_SNPS_ETH_250M] = 194, - [CLK_TOP_SNPS_ETH_62P4M_PTP] = 195, - [CLK_TOP_SNPS_ETH_50M_RMII] = 196, - [CLK_TOP_DGI_OUT] = 197, - [CLK_TOP_NNA0] = 198, - [CLK_TOP_NNA1] = 199, - [CLK_TOP_ADSP] = 200, - [CLK_TOP_ASM_H] = 201, - [CLK_TOP_ASM_M] = 202, - [CLK_TOP_ASM_L] = 203, - [CLK_TOP_APLL1] = 204, - [CLK_TOP_APLL2] = 205, - [CLK_TOP_APLL3] = 206, - [CLK_TOP_APLL4] = 207, - [CLK_TOP_APLL5] = 208, - [CLK_TOP_I2SO1_MCK] = 209, - [CLK_TOP_I2SO2_MCK] = 210, - [CLK_TOP_I2SI1_MCK] = 211, - [CLK_TOP_I2SI2_MCK] = 212, - [CLK_TOP_DPTX_MCK] = 213, - [CLK_TOP_AUD_IEC_CLK] = 214, - [CLK_TOP_A1SYS_HP] = 215, - [CLK_TOP_A2SYS_HF] = 216, - [CLK_TOP_A3SYS_HF] = 217, - [CLK_TOP_A4SYS_HF] = 218, - [CLK_TOP_SPINFI_BCLK] = 219, - [CLK_TOP_NFI1X] = 220, - [CLK_TOP_ECC] = 221, - [CLK_TOP_AUDIO_LOCAL_BUS] = 222, - [CLK_TOP_SPINOR] = 223, - [CLK_TOP_DVIO_DGI_REF] = 224, - [CLK_TOP_ULPOSC] = 225, - [CLK_TOP_ULPOSC_CORE] = 226, - [CLK_TOP_SRCK] = 227, + [CLK_TOP_AXI] = 101, + [CLK_TOP_SPM] = 102, + [CLK_TOP_SCP] = 103, + [CLK_TOP_BUS_AXIMEM] = 104, + [CLK_TOP_VPP] = 105, + [CLK_TOP_ETHDR] = 106, + [CLK_TOP_IPE] = 107, + [CLK_TOP_CAM] = 108, + [CLK_TOP_CCU] = 109, + [CLK_TOP_IMG] = 110, + [CLK_TOP_CAMTM] = 111, + [CLK_TOP_DSP] = 112, + [CLK_TOP_DSP1] = 113, + [CLK_TOP_DSP2] = 114, + [CLK_TOP_DSP3] = 115, + [CLK_TOP_DSP4] = 116, + [CLK_TOP_DSP5] = 117, + [CLK_TOP_DSP6] = 118, + [CLK_TOP_DSP7] = 119, + [CLK_TOP_IPU_IF] = 120, + [CLK_TOP_MFG_CORE_TMP] = 121, + [CLK_TOP_CAMTG] = 122, + [CLK_TOP_CAMTG2] = 123, + [CLK_TOP_CAMTG3] = 124, + [CLK_TOP_CAMTG4] = 125, + [CLK_TOP_CAMTG5] = 126, + [CLK_TOP_UART] = 127, + [CLK_TOP_SPI] = 128, + [CLK_TOP_SPIS] = 129, + [CLK_TOP_MSDC50_0_HCLK] = 130, + [CLK_TOP_MSDC50_0] = 131, + [CLK_TOP_MSDC30_1] = 132, + [CLK_TOP_MSDC30_2] = 133, + [CLK_TOP_INTDIR] = 134, + [CLK_TOP_AUD_INTBUS] = 135, + [CLK_TOP_AUDIO_H] = 136, + [CLK_TOP_PWRAP_ULPOSC] = 137, + [CLK_TOP_ATB] = 138, + [CLK_TOP_PWRMCU] = 139, + [CLK_TOP_DP] = 140, + [CLK_TOP_EDP] = 141, + [CLK_TOP_DPI] = 142, + [CLK_TOP_DISP_PWM0] = 143, + [CLK_TOP_DISP_PWM1] = 144, + [CLK_TOP_USB_TOP] = 145, + [CLK_TOP_SSUSB_XHCI] = 146, + [CLK_TOP_USB_TOP_1P] = 147, + [CLK_TOP_SSUSB_XHCI_1P] = 148, + [CLK_TOP_USB_TOP_2P] = 149, + [CLK_TOP_SSUSB_XHCI_2P] = 150, + [CLK_TOP_USB_TOP_3P] = 151, + [CLK_TOP_SSUSB_XHCI_3P] = 152, + [CLK_TOP_I2C] = 153, + [CLK_TOP_SENINF] = 154, + [CLK_TOP_SENINF1] = 155, + [CLK_TOP_SENINF2] = 156, + [CLK_TOP_SENINF3] = 157, + [CLK_TOP_GCPU] = 158, + [CLK_TOP_DXCC] = 159, + [CLK_TOP_DPMAIF_MAIN] = 160, + [CLK_TOP_AES_UFSFDE] = 161, + [CLK_TOP_UFS] = 162, + [CLK_TOP_UFS_TICK1US] = 163, + [CLK_TOP_UFS_MP_SAP_CFG] = 164, + [CLK_TOP_VENC] = 165, + [CLK_TOP_VDEC] = 166, + [CLK_TOP_PWM] = 167, + [CLK_TOP_MCUPM] = 168, + [CLK_TOP_SPMI_P_MST] = 169, + [CLK_TOP_SPMI_M_MST] = 170, + [CLK_TOP_DVFSRC] = 171, + [CLK_TOP_TL] = 172, + [CLK_TOP_TL_P1] = 173, + [CLK_TOP_AES_MSDCFDE] = 174, + [CLK_TOP_DSI_OCC] = 175, + [CLK_TOP_WPE_VPP] = 176, + [CLK_TOP_HDCP] = 177, + [CLK_TOP_HDCP_24M] = 178, + [CLK_TOP_HD20_DACR_REF_CLK] = 179, + [CLK_TOP_HD20_HDCP_CCLK] = 180, + [CLK_TOP_HDMI_XTAL] = 181, + [CLK_TOP_HDMI_APB] = 182, + [CLK_TOP_SNPS_ETH_250M] = 183, + [CLK_TOP_SNPS_ETH_62P4M_PTP] = 184, + [CLK_TOP_SNPS_ETH_50M_RMII] = 185, + [CLK_TOP_DGI_OUT] = 186, + [CLK_TOP_NNA0] = 187, + [CLK_TOP_NNA1] = 188, + [CLK_TOP_ADSP] = 189, + [CLK_TOP_ASM_H] = 190, + [CLK_TOP_ASM_M] = 191, + [CLK_TOP_ASM_L] = 192, + [CLK_TOP_APLL1] = 193, + [CLK_TOP_APLL2] = 194, + [CLK_TOP_APLL3] = 195, + [CLK_TOP_APLL4] = 196, + [CLK_TOP_APLL5] = 197, + [CLK_TOP_I2SO1_MCK] = 198, + [CLK_TOP_I2SO2_MCK] = 199, + [CLK_TOP_I2SI1_MCK] = 200, + [CLK_TOP_I2SI2_MCK] = 201, + [CLK_TOP_DPTX_MCK] = 202, + [CLK_TOP_AUD_IEC_CLK] = 203, + [CLK_TOP_A1SYS_HP] = 204, + [CLK_TOP_A2SYS_HF] = 205, + [CLK_TOP_A3SYS_HF] = 206, + [CLK_TOP_A4SYS_HF] = 207, + [CLK_TOP_SPINFI_BCLK] = 208, + [CLK_TOP_NFI1X] = 209, + [CLK_TOP_ECC] = 210, + [CLK_TOP_AUDIO_LOCAL_BUS] = 211, + [CLK_TOP_SPINOR] = 212, + [CLK_TOP_DVIO_DGI_REF] = 213, + [CLK_TOP_ULPOSC] = 214, + [CLK_TOP_ULPOSC_CORE] = 215, + [CLK_TOP_SRCK] = 216, /* GATE */ - [CLK_TOP_CFG_VPP0] = 228, - [CLK_TOP_CFG_VPP1] = 229, - [CLK_TOP_CFG_VDO0] = 230, - [CLK_TOP_CFG_VDO1] = 231, - [CLK_TOP_CFG_UNIPLL_SES] = 232, - [CLK_TOP_CFG_26M_VPP0] = 233, - [CLK_TOP_CFG_26M_VPP1] = 234, - [CLK_TOP_CFG_26M_AUD] = 235, - [CLK_TOP_CFG_AXI_EAST] = 236, - [CLK_TOP_CFG_AXI_EAST_NORTH] = 237, - [CLK_TOP_CFG_AXI_NORTH] = 238, - [CLK_TOP_CFG_AXI_SOUTH] = 239, - [CLK_TOP_CFG_EXT_TEST] = 240, - [CLK_TOP_SSUSB_REF] = 241, - [CLK_TOP_SSUSB_PHY_REF] = 242, - [CLK_TOP_SSUSB_P1_REF] = 243, - [CLK_TOP_SSUSB_PHY_P1_REF] = 244, - [CLK_TOP_SSUSB_P2_REF] = 245, - [CLK_TOP_SSUSB_PHY_P2_REF] = 246, - [CLK_TOP_SSUSB_P3_REF] = 247, - [CLK_TOP_SSUSB_PHY_P3_REF] = 248, + [CLK_TOP_CFG_VPP0] = 217, + [CLK_TOP_CFG_VPP1] = 218, + [CLK_TOP_CFG_VDO0] = 219, + [CLK_TOP_CFG_VDO1] = 220, + [CLK_TOP_CFG_UNIPLL_SES] = 221, + [CLK_TOP_CFG_26M_VPP0] = 222, + [CLK_TOP_CFG_26M_VPP1] = 223, + [CLK_TOP_CFG_26M_AUD] = 224, + [CLK_TOP_CFG_AXI_EAST] = 225, + [CLK_TOP_CFG_AXI_EAST_NORTH] = 226, + [CLK_TOP_CFG_AXI_NORTH] = 227, + [CLK_TOP_CFG_AXI_SOUTH] = 228, + [CLK_TOP_CFG_EXT_TEST] = 229, + [CLK_TOP_SSUSB_REF] = 230, + [CLK_TOP_SSUSB_PHY_REF] = 231, + [CLK_TOP_SSUSB_P1_REF] = 232, + [CLK_TOP_SSUSB_PHY_P1_REF] = 233, + [CLK_TOP_SSUSB_P2_REF] = 234, + [CLK_TOP_SSUSB_PHY_P2_REF] = 235, + [CLK_TOP_SSUSB_P3_REF] = 236, + [CLK_TOP_SSUSB_PHY_P3_REF] = 237, }; static const struct mtk_clk_tree mt8195_topckgen_clk_tree = { .xtal_rate = 26 * MHZ, + .ext_clk_rates = ext_clock_rates, + .num_ext_clks = ARRAY_SIZE(ext_clock_rates), .id_offs_map = mt8195_id_top_offs_map, .id_offs_map_size = ARRAY_SIZE(mt8195_id_top_offs_map), .fdivs_offs = mt8195_id_top_offs_map[CLK_TOP_CLK26M_D2], @@ -1475,18 +1461,34 @@ static const struct mtk_gate_regs infra_ao4_cg_regs = { GATE_FLAGS(_id, _parent, &infra_ao0_cg_regs, _shift,\ CLK_PARENT_TOPCKGEN | CLK_GATE_SETCLR) +#define GATE_INFRA_AO0E(_id, _parent, _shift) \ + GATE_FLAGS(_id, _parent, &infra_ao0_cg_regs, _shift,\ + CLK_PARENT_EXT | CLK_GATE_SETCLR) + #define GATE_INFRA_AO1(_id, _parent, _shift) \ GATE_FLAGS(_id, _parent, &infra_ao1_cg_regs, _shift,\ CLK_PARENT_TOPCKGEN | CLK_GATE_SETCLR) +#define GATE_INFRA_AO1E(_id, _parent, _shift) \ + GATE_FLAGS(_id, _parent, &infra_ao1_cg_regs, _shift,\ + CLK_PARENT_EXT | CLK_GATE_SETCLR) + #define GATE_INFRA_AO2(_id, _parent, _shift) \ GATE_FLAGS(_id, _parent, &infra_ao2_cg_regs, _shift,\ CLK_PARENT_TOPCKGEN | CLK_GATE_SETCLR) +#define GATE_INFRA_AO2E(_id, _parent, _shift) \ + GATE_FLAGS(_id, _parent, &infra_ao2_cg_regs, _shift,\ + CLK_PARENT_EXT | CLK_GATE_SETCLR) + #define GATE_INFRA_AO3(_id, _parent, _shift) \ GATE_FLAGS(_id, _parent, &infra_ao3_cg_regs, _shift,\ CLK_PARENT_TOPCKGEN | CLK_GATE_SETCLR) +#define GATE_INFRA_AO3E(_id, _parent, _shift) \ + GATE_FLAGS(_id, _parent, &infra_ao3_cg_regs, _shift,\ + CLK_PARENT_EXT | CLK_GATE_SETCLR) + #define GATE_INFRA_AO4(_id, _parent, _shift) \ GATE_FLAGS(_id, _parent, &infra_ao4_cg_regs, _shift,\ CLK_PARENT_TOPCKGEN | CLK_GATE_SETCLR) @@ -1513,23 +1515,23 @@ static const struct mtk_gate infra_ao_clks[] = { GATE_INFRA_AO0(CLK_INFRA_AO_UART2, CLK_TOP_UART, 24), GATE_INFRA_AO0(CLK_INFRA_AO_UART3, CLK_TOP_UART, 25), GATE_INFRA_AO0(CLK_INFRA_AO_UART4, CLK_TOP_UART, 26), - GATE_INFRA_AO0(CLK_INFRA_AO_GCE_26M, CLK_TOP_CLK26M, 27), + GATE_INFRA_AO0E(CLK_INFRA_AO_GCE_26M, CLK_PAD_CLK26M, 27), GATE_INFRA_AO0(CLK_INFRA_AO_CQ_DMA_FPC, CLK_TOP_FPC, 28), GATE_INFRA_AO0(CLK_INFRA_AO_UART5, CLK_TOP_UART, 29), /* INFRA_AO1 */ - GATE_INFRA_AO1(CLK_INFRA_AO_HDMI_26M, CLK_TOP_CLK26M, 0), + GATE_INFRA_AO1E(CLK_INFRA_AO_HDMI_26M, CLK_PAD_CLK26M, 0), GATE_INFRA_AO1(CLK_INFRA_AO_SPI0, CLK_TOP_SPI, 1), GATE_INFRA_AO1(CLK_INFRA_AO_MSDC0, CLK_TOP_MSDC50_0_HCLK, 2), GATE_INFRA_AO1(CLK_INFRA_AO_MSDC1, CLK_TOP_AXI, 4), GATE_INFRA_AO1(CLK_INFRA_AO_CG1_MSDC2, CLK_TOP_AXI, 5), GATE_INFRA_AO1(CLK_INFRA_AO_MSDC0_SRC, CLK_TOP_MSDC50_0, 6), GATE_INFRA_AO1(CLK_INFRA_AO_TRNG, CLK_TOP_AXI, 9), - GATE_INFRA_AO1(CLK_INFRA_AO_AUXADC, CLK_TOP_CLK26M, 10), + GATE_INFRA_AO1E(CLK_INFRA_AO_AUXADC, CLK_PAD_CLK26M, 10), GATE_INFRA_AO1(CLK_INFRA_AO_CPUM, CLK_TOP_AXI, 11), - GATE_INFRA_AO1(CLK_INFRA_AO_HDMI_32K, CLK_TOP_CLK32K, 12), + GATE_INFRA_AO1E(CLK_INFRA_AO_HDMI_32K, CLK_PAD_CLK32K, 12), GATE_INFRA_AO1(CLK_INFRA_AO_CEC_66M_H, CLK_TOP_AXI, 13), GATE_INFRA_AO1(CLK_INFRA_AO_IRRX, CLK_TOP_AXI, 14), - GATE_INFRA_AO1(CLK_INFRA_AO_PCIE_TL_26M, CLK_TOP_CLK26M, 15), + GATE_INFRA_AO1E(CLK_INFRA_AO_PCIE_TL_26M, CLK_PAD_CLK26M, 15), GATE_INFRA_AO1(CLK_INFRA_AO_MSDC1_SRC, CLK_TOP_MSDC30_1, 16), GATE_INFRA_AO1(CLK_INFRA_AO_CEC_66M_B, CLK_TOP_AXI, 17), GATE_INFRA_AO1(CLK_INFRA_AO_PCIE_TL_96M, CLK_TOP_TL, 18), @@ -1537,15 +1539,15 @@ static const struct mtk_gate infra_ao_clks[] = { GATE_INFRA_AO1(CLK_INFRA_AO_ECC_66M_H, CLK_TOP_AXI, 23), GATE_INFRA_AO1(CLK_INFRA_AO_DEBUGSYS, CLK_TOP_AXI, 24), GATE_INFRA_AO1(CLK_INFRA_AO_AUDIO, CLK_TOP_AXI, 25), - GATE_INFRA_AO1(CLK_INFRA_AO_PCIE_TL_32K, CLK_TOP_CLK32K, 26), + GATE_INFRA_AO1E(CLK_INFRA_AO_PCIE_TL_32K, CLK_PAD_CLK32K, 26), GATE_INFRA_AO1(CLK_INFRA_AO_DBG_TRACE, CLK_TOP_AXI, 29), - GATE_INFRA_AO1(CLK_INFRA_AO_DRAMC_F26M, CLK_TOP_CLK26M, 31), + GATE_INFRA_AO1E(CLK_INFRA_AO_DRAMC_F26M, CLK_PAD_CLK26M, 31), /* INFRA_AO2 */ GATE_INFRA_AO2(CLK_INFRA_AO_IRTX, CLK_TOP_AXI, 0), GATE_INFRA_AO2(CLK_INFRA_AO_SSUSB, CLK_TOP_USB_TOP, 1), GATE_INFRA_AO2(CLK_INFRA_AO_DISP_PWM, CLK_TOP_DISP_PWM0, 2), GATE_INFRA_AO2(CLK_INFRA_AO_CLDMA_B, CLK_TOP_AXI, 3), - GATE_INFRA_AO2(CLK_INFRA_AO_AUDIO_26M_B, CLK_TOP_CLK26M, 4), + GATE_INFRA_AO2E(CLK_INFRA_AO_AUDIO_26M_B, CLK_PAD_CLK26M, 4), GATE_INFRA_AO2(CLK_INFRA_AO_SPI1, CLK_TOP_SPI, 6), GATE_INFRA_AO2(CLK_INFRA_AO_SPI2, CLK_TOP_SPI, 9), GATE_INFRA_AO2(CLK_INFRA_AO_SPI3, CLK_TOP_SPI, 10), @@ -1571,13 +1573,13 @@ static const struct mtk_gate infra_ao_clks[] = { GATE_INFRA_AO3(CLK_INFRA_AO_MD_MSDC0, CLK_TOP_MSDC50_0, 8), GATE_INFRA_AO3(CLK_INFRA_AO_CG3_MSDC2, CLK_TOP_MSDC30_2, 9), GATE_INFRA_AO3(CLK_INFRA_AO_GCPU, CLK_TOP_GCPU, 10), - GATE_INFRA_AO3(CLK_INFRA_AO_PCIE_PERI_26M, CLK_TOP_CLK26M, 15), + GATE_INFRA_AO3E(CLK_INFRA_AO_PCIE_PERI_26M, CLK_PAD_CLK26M, 15), GATE_INFRA_AO3(CLK_INFRA_AO_GCPU_66M_B, CLK_TOP_AXI, 16), GATE_INFRA_AO3(CLK_INFRA_AO_GCPU_133M_B, CLK_TOP_AXI, 17), GATE_INFRA_AO3(CLK_INFRA_AO_DISP_PWM1, CLK_TOP_DISP_PWM1, 20), GATE_INFRA_AO3(CLK_INFRA_AO_FBIST2FPC, CLK_TOP_MSDC50_0, 24), GATE_INFRA_AO3(CLK_INFRA_AO_DEVICE_APC_SYNC, CLK_TOP_AXI, 25), - GATE_INFRA_AO3(CLK_INFRA_AO_PCIE_P1_PERI_26M, CLK_TOP_CLK26M, 26), + GATE_INFRA_AO3E(CLK_INFRA_AO_PCIE_P1_PERI_26M, CLK_PAD_CLK26M, 26), GATE_INFRA_AO3(CLK_INFRA_AO_SPIS0, CLK_TOP_SPIS, 28), GATE_INFRA_AO3(CLK_INFRA_AO_SPIS1, CLK_TOP_SPIS, 29), /* INFRA_AO4 */ @@ -1596,6 +1598,8 @@ static const struct mtk_gate infra_ao_clks[] = { static const struct mtk_clk_tree mt8195_infracfg_ao_clk_tree = { .xtal_rate = 26 * MHZ, + .ext_clk_rates = ext_clock_rates, + .num_ext_clks = ARRAY_SIZE(ext_clock_rates), }; static int mt8195_apmixedsys_probe(struct udevice *dev) -- cgit v1.3.1 From 39b6394831d35af0809456fa158fb6cb3b9c3626 Mon Sep 17 00:00:00 2001 From: David Lechner Date: Tue, 10 Mar 2026 10:32:14 -0500 Subject: clk: mediatek: replace xtal2_rate with struct mtk_parent Replace the hard-coded xtal rate for PLL parents with struct mtk_parent. This avoids declaring the same clock rate in multiple places and will allow future drivers to use an arbitrary clock. The variable is renamed to something that better indicate what the field is actually used for. Reviewed-by: Julien Stephan Link: https://patch.msgid.link/20260310-clk-mtk-parent-cleanup-v1-1-66175ca8f637@baylibre.com Signed-off-by: David Lechner --- drivers/clk/mediatek/clk-mt7622.c | 12 +++++++++++- drivers/clk/mediatek/clk-mt7623.c | 12 +++++++++++- drivers/clk/mediatek/clk-mt7629.c | 16 ++++++++++++++-- drivers/clk/mediatek/clk-mt8183.c | 12 +++++++++++- drivers/clk/mediatek/clk-mt8188.c | 2 +- drivers/clk/mediatek/clk-mt8189.c | 4 +--- drivers/clk/mediatek/clk-mt8195.c | 2 +- drivers/clk/mediatek/clk-mt8365.c | 2 +- drivers/clk/mediatek/clk-mt8512.c | 12 +++++++++++- drivers/clk/mediatek/clk-mt8516.c | 12 +++++++++++- drivers/clk/mediatek/clk-mt8518.c | 12 +++++++++++- drivers/clk/mediatek/clk-mtk.c | 33 +++++++++++++++++++++++++-------- drivers/clk/mediatek/clk-mtk.h | 2 +- 13 files changed, 110 insertions(+), 23 deletions(-) diff --git a/drivers/clk/mediatek/clk-mt7622.c b/drivers/clk/mediatek/clk-mt7622.c index 9e6fd12a6a5..c94b4b0e0ed 100644 --- a/drivers/clk/mediatek/clk-mt7622.c +++ b/drivers/clk/mediatek/clk-mt7622.c @@ -28,6 +28,14 @@ #define MCU_BUS_MSK GENMASK(10, 9) #define MCU_BUS_SEL(x) ((x) << 9) +enum { + CLK_PAD_CLK25M, +}; + +static const ulong ext_clock_rates[] = { + [CLK_PAD_CLK25M] = 25 * MHZ, +}; + /* apmixedsys */ #define PLL(_id, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, _pd_reg, \ _pd_shift, _pcw_reg, _pcw_shift) { \ @@ -597,7 +605,9 @@ static const struct mtk_gate ssusb_cgs[] = { }; static const struct mtk_clk_tree mt7622_apmixed_clk_tree = { - .xtal2_rate = 25 * MHZ, + .pll_parent = EXT_PARENT(CLK_PAD_CLK25M), + .ext_clk_rates = ext_clock_rates, + .num_ext_clks = ARRAY_SIZE(ext_clock_rates), .plls = apmixed_plls, .gates_offs = CLK_APMIXED_MAIN_CORE_EN, .gates = apmixed_cgs, diff --git a/drivers/clk/mediatek/clk-mt7623.c b/drivers/clk/mediatek/clk-mt7623.c index 9e1522d4615..1c34bfbf596 100644 --- a/drivers/clk/mediatek/clk-mt7623.c +++ b/drivers/clk/mediatek/clk-mt7623.c @@ -24,6 +24,14 @@ #define AXI_DIV_MSK GENMASK(4, 0) #define AXI_DIV_SEL(x) (x) +enum { + CLK_PAD_CLK26M, +}; + +static const ulong ext_clock_rates[] = { + [CLK_PAD_CLK26M] = 26 * MHZ, +}; + /* apmixedsys */ static const int pll_id_offs_map[] = { [0 ... CLK_APMIXED_NR - 1] = -1, @@ -994,7 +1002,9 @@ static const struct mtk_gate hif_cgs[] = { }; static const struct mtk_clk_tree mt7623_apmixedsys_clk_tree = { - .xtal2_rate = 26 * MHZ, + .pll_parent = EXT_PARENT(CLK_PAD_CLK26M), + .ext_clk_rates = ext_clock_rates, + .num_ext_clks = ARRAY_SIZE(ext_clock_rates), .id_offs_map = pll_id_offs_map, .id_offs_map_size = ARRAY_SIZE(pll_id_offs_map), .plls = apmixed_plls, diff --git a/drivers/clk/mediatek/clk-mt7629.c b/drivers/clk/mediatek/clk-mt7629.c index 42670269d3e..beba7fc4abc 100644 --- a/drivers/clk/mediatek/clk-mt7629.c +++ b/drivers/clk/mediatek/clk-mt7629.c @@ -28,6 +28,14 @@ #define MCU_BUS_MSK GENMASK(10, 9) #define MCU_BUS_SEL(x) ((x) << 9) +enum { + CLK_PAD_CLK20M, +}; + +static const ulong ext_clock_rates[] = { + [CLK_PAD_CLK20M] = 20 * MHZ, +}; + /* apmixedsys */ #define PLL(_id, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, _pd_reg, \ _pd_shift, _pcw_reg, _pcw_shift) { \ @@ -567,7 +575,9 @@ static const struct mtk_gate ssusb_cgs[] = { static const struct mtk_clk_tree mt7629_clk_tree = { .xtal_rate = 40 * MHZ, - .xtal2_rate = 20 * MHZ, + .pll_parent = EXT_PARENT(CLK_PAD_CLK20M), + .ext_clk_rates = ext_clock_rates, + .num_ext_clks = ARRAY_SIZE(ext_clock_rates), .fdivs_offs = CLK_TOP_TO_USB3_SYS, .muxes_offs = CLK_TOP_AXI_SEL, .plls = apmixed_plls, @@ -582,7 +592,9 @@ static const struct mtk_clk_tree mt7629_clk_tree = { static const struct mtk_clk_tree mt7629_peri_clk_tree = { .xtal_rate = 40 * MHZ, - .xtal2_rate = 20 * MHZ, + .pll_parent = EXT_PARENT(CLK_PAD_CLK20M), + .ext_clk_rates = ext_clock_rates, + .num_ext_clks = ARRAY_SIZE(ext_clock_rates), .fdivs_offs = CLK_TOP_TO_USB3_SYS, .muxes_offs = CLK_TOP_AXI_SEL, .plls = apmixed_plls, diff --git a/drivers/clk/mediatek/clk-mt8183.c b/drivers/clk/mediatek/clk-mt8183.c index 54e31efd2ea..6158441fb95 100644 --- a/drivers/clk/mediatek/clk-mt8183.c +++ b/drivers/clk/mediatek/clk-mt8183.c @@ -17,6 +17,14 @@ #define MT8183_PLL_FMAX (3800UL * MHZ) #define MT8183_PLL_FMIN (1500UL * MHZ) +enum { + CLK_PAD_CLK26M, +}; + +static const ulong ext_clock_rates[] = { + [CLK_PAD_CLK26M] = 26 * MHZ, +}; + /* apmixedsys */ #define PLL(_id, _reg, _pwr_reg, _en_mask, _flags, _rst_bar_mask, _pcwbits, \ _pcwibits, _pd_reg, _pd_shift, _pcw_reg, _pcw_shift) { \ @@ -598,7 +606,9 @@ static const struct mtk_composite top_muxes[] = { static const struct mtk_clk_tree mt8183_clk_tree = { .xtal_rate = 26 * MHZ, - .xtal2_rate = 26 * MHZ, + .pll_parent = EXT_PARENT(CLK_PAD_CLK26M), + .ext_clk_rates = ext_clock_rates, + .num_ext_clks = ARRAY_SIZE(ext_clock_rates), .fdivs_offs = CLK_TOP_CLK13M, .muxes_offs = CLK_TOP_MUX_AXI, .plls = apmixed_plls, diff --git a/drivers/clk/mediatek/clk-mt8188.c b/drivers/clk/mediatek/clk-mt8188.c index e4297c92bd9..ca5fa8af86e 100644 --- a/drivers/clk/mediatek/clk-mt8188.c +++ b/drivers/clk/mediatek/clk-mt8188.c @@ -85,7 +85,7 @@ static const struct mtk_pll_data apmixed_plls[] = { static const struct mtk_clk_tree mt8188_apmixedsys_clk_tree = { .xtal_rate = 26 * MHZ, - .xtal2_rate = 26 * MHZ, + .pll_parent = EXT_PARENT(CLK_PAD_CLK26M), .ext_clk_rates = ext_clock_rates, .num_ext_clks = ARRAY_SIZE(ext_clock_rates), .plls = apmixed_plls, diff --git a/drivers/clk/mediatek/clk-mt8189.c b/drivers/clk/mediatek/clk-mt8189.c index 6c917735914..fec908728c0 100644 --- a/drivers/clk/mediatek/clk-mt8189.c +++ b/drivers/clk/mediatek/clk-mt8189.c @@ -1638,8 +1638,7 @@ static const struct mtk_gate mminfra_config_clks[] = { }; static const struct mtk_clk_tree mt8189_apmixedsys_clk_tree = { - .xtal_rate = 26 * MHZ, - .xtal2_rate = 26 * MHZ, + .pll_parent = EXT_PARENT(CLK_PAD_CLK26M), .ext_clk_rates = ext_clock_rates, .num_ext_clks = ARRAY_SIZE(ext_clock_rates), .plls = apmixed_plls, @@ -1647,7 +1646,6 @@ static const struct mtk_clk_tree mt8189_apmixedsys_clk_tree = { }; static const struct mtk_clk_tree mt8189_topckgen_clk_tree = { - .xtal_rate = 26 * MHZ, .ext_clk_rates = ext_clock_rates, .num_ext_clks = ARRAY_SIZE(ext_clock_rates), .fdivs_offs = CLK_TOP_MAINPLL_D3, diff --git a/drivers/clk/mediatek/clk-mt8195.c b/drivers/clk/mediatek/clk-mt8195.c index 76ece913187..28b2e2f12ac 100644 --- a/drivers/clk/mediatek/clk-mt8195.c +++ b/drivers/clk/mediatek/clk-mt8195.c @@ -97,7 +97,7 @@ static const struct mtk_pll_data apmixed_plls[] = { static const struct mtk_clk_tree mt8195_apmixedsys_clk_tree = { .xtal_rate = 26 * MHZ, - .xtal2_rate = 26 * MHZ, + .pll_parent = EXT_PARENT(CLK_PAD_CLK26M), .ext_clk_rates = ext_clock_rates, .num_ext_clks = ARRAY_SIZE(ext_clock_rates), .plls = apmixed_plls, diff --git a/drivers/clk/mediatek/clk-mt8365.c b/drivers/clk/mediatek/clk-mt8365.c index a69799b8496..a87ac2ad922 100644 --- a/drivers/clk/mediatek/clk-mt8365.c +++ b/drivers/clk/mediatek/clk-mt8365.c @@ -75,7 +75,7 @@ static const struct mtk_pll_data apmixed_plls[] = { static const struct mtk_clk_tree mt8365_apmixed_tree = { .xtal_rate = 26 * MHZ, - .xtal2_rate = 26 * MHZ, + .pll_parent = EXT_PARENT(CLK_PAD_CLK26M), .ext_clk_rates = ext_clock_rates, .num_ext_clks = ARRAY_SIZE(ext_clock_rates), .plls = apmixed_plls, diff --git a/drivers/clk/mediatek/clk-mt8512.c b/drivers/clk/mediatek/clk-mt8512.c index de0d3eae7ee..f7d41f4cfdb 100644 --- a/drivers/clk/mediatek/clk-mt8512.c +++ b/drivers/clk/mediatek/clk-mt8512.c @@ -17,6 +17,14 @@ #define MT8512_PLL_FMIN (1500UL * MHZ) #define MT8512_CON0_RST_BAR BIT(23) +enum { + CLK_PAD_CLK26M, +}; + +static const ulong ext_clock_rates[] = { + [CLK_PAD_CLK26M] = 26 * MHZ, +}; + /* apmixedsys */ #define PLL(_id, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, _pd_reg, \ _pd_shift, _pcw_reg, _pcw_shift, _pcw_chg_reg) { \ @@ -786,7 +794,9 @@ static const struct mtk_gate infra_clks[] = { static const struct mtk_clk_tree mt8512_clk_tree = { .xtal_rate = 26 * MHZ, - .xtal2_rate = 26 * MHZ, + .pll_parent = EXT_PARENT(CLK_PAD_CLK26M), + .ext_clk_rates = ext_clock_rates, + .num_ext_clks = ARRAY_SIZE(ext_clock_rates), .fdivs_offs = CLK_TOP_SYSPLL1_D2, .muxes_offs = CLK_TOP_AXI_SEL, .plls = apmixed_plls, diff --git a/drivers/clk/mediatek/clk-mt8516.c b/drivers/clk/mediatek/clk-mt8516.c index 6b30ea9ce4a..74966051b1c 100644 --- a/drivers/clk/mediatek/clk-mt8516.c +++ b/drivers/clk/mediatek/clk-mt8516.c @@ -16,6 +16,14 @@ #define MT8516_PLL_FMAX (1502UL * MHZ) #define MT8516_CON0_RST_BAR BIT(27) +enum { + CLK_PAD_CLK26M, +}; + +static const ulong ext_clock_rates[] = { + [CLK_PAD_CLK26M] = 26 * MHZ, +}; + /* apmixedsys */ #define PLL(_id, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, _pd_reg, \ _pd_shift, _pcw_reg, _pcw_shift) { \ @@ -738,7 +746,9 @@ static const struct mtk_gate top_clks[] = { static const struct mtk_clk_tree mt8516_clk_tree = { .xtal_rate = 26 * MHZ, - .xtal2_rate = 26 * MHZ, + .pll_parent = EXT_PARENT(CLK_PAD_CLK26M), + .ext_clk_rates = ext_clock_rates, + .num_ext_clks = ARRAY_SIZE(ext_clock_rates), .fdivs_offs = CLK_TOP_DMPLL, .muxes_offs = CLK_TOP_UART0_SEL, .plls = apmixed_plls, diff --git a/drivers/clk/mediatek/clk-mt8518.c b/drivers/clk/mediatek/clk-mt8518.c index 34fa5a127d5..85cbb35446b 100644 --- a/drivers/clk/mediatek/clk-mt8518.c +++ b/drivers/clk/mediatek/clk-mt8518.c @@ -16,6 +16,14 @@ #define MT8518_PLL_FMAX (3000UL * MHZ) #define MT8518_CON0_RST_BAR BIT(27) +enum { + CLK_PAD_CLK26M, +}; + +static const ulong ext_clock_rates[] = { + [CLK_PAD_CLK26M] = 26 * MHZ, +}; + /* apmixedsys */ #define PLL(_id, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, _pd_reg, \ _pd_shift, _pcw_reg, _pcw_shift) { \ @@ -1494,7 +1502,9 @@ static const struct mtk_gate top_clks[] = { static const struct mtk_clk_tree mt8518_clk_tree = { .xtal_rate = 26 * MHZ, - .xtal2_rate = 26 * MHZ, + .pll_parent = EXT_PARENT(CLK_PAD_CLK26M), + .ext_clk_rates = ext_clock_rates, + .num_ext_clks = ARRAY_SIZE(ext_clock_rates), .fdivs_offs = CLK_TOP_DMPLL, .muxes_offs = CLK_TOP_UART0_SEL, .plls = apmixed_plls, diff --git a/drivers/clk/mediatek/clk-mtk.c b/drivers/clk/mediatek/clk-mtk.c index fa4a84bfceb..0b6eb0dbc04 100644 --- a/drivers/clk/mediatek/clk-mtk.c +++ b/drivers/clk/mediatek/clk-mtk.c @@ -499,16 +499,21 @@ static void mtk_pll_set_rate_regs(struct mtk_clk_priv *priv, u32 id, * @postdiv: The post divider (output) * @freq: The desired target frequency */ -static void mtk_pll_calc_values(struct mtk_clk_priv *priv, u32 id, - u32 *pcw, u32 *postdiv, u32 freq) +static int mtk_pll_calc_values(struct mtk_clk_priv *priv, struct clk *clk, + u32 *pcw, u32 *postdiv, u32 freq) { const struct mtk_pll_data *pll; - unsigned long fmin; + const struct mtk_parent *parent = &priv->tree->pll_parent; + unsigned long xtal_rate, fmin; u64 _pcw; int ibits; u32 val; - pll = &priv->tree->plls[id]; + xtal_rate = mtk_find_parent_rate(priv, clk, parent->id, parent->flags); + if (IS_ERR_VALUE(xtal_rate)) + return xtal_rate; + + pll = &priv->tree->plls[clk->id]; fmin = pll->fmin ? pll->fmin : 1000 * MHZ; if (freq > pll->fmax) @@ -523,9 +528,11 @@ static void mtk_pll_calc_values(struct mtk_clk_priv *priv, u32 id, /* _pcw = freq * postdiv / xtal_rate * 2^pcwfbits */ ibits = pll->pcwibits ? pll->pcwibits : INTEGER_BITS; _pcw = ((u64)freq << val) << (pll->pcwbits - ibits); - do_div(_pcw, priv->tree->xtal2_rate); + do_div(_pcw, xtal_rate); *pcw = (u32)_pcw; + + return 0; } static ulong mtk_apmixedsys_set_rate(struct clk *clk, ulong rate) @@ -533,11 +540,15 @@ static ulong mtk_apmixedsys_set_rate(struct clk *clk, ulong rate) struct mtk_clk_priv *priv = dev_get_priv(clk->dev); u32 pcw = 0; u32 postdiv; + int ret; if (!mtk_clk_id_is_pll(priv->tree, clk->id)) return -EINVAL; - mtk_pll_calc_values(priv, clk->id, &pcw, &postdiv, rate); + ret = mtk_pll_calc_values(priv, clk, &pcw, &postdiv, rate); + if (ret) + return ret; + mtk_pll_set_rate_regs(priv, clk->id, pcw, postdiv); return 0; @@ -546,8 +557,10 @@ static ulong mtk_apmixedsys_set_rate(struct clk *clk, ulong rate) static ulong mtk_apmixedsys_get_rate(struct clk *clk) { struct mtk_clk_priv *priv = dev_get_priv(clk->dev); + const struct mtk_parent *parent; const struct mtk_pll_data *pll; const struct mtk_gate *gate; + unsigned long xtal_rate; u32 postdiv; u32 pcw; @@ -557,6 +570,11 @@ static ulong mtk_apmixedsys_get_rate(struct clk *clk) return mtk_find_parent_rate(priv, clk, gate->parent, gate->flags); } + parent = &priv->tree->pll_parent; + xtal_rate = mtk_find_parent_rate(priv, clk, parent->id, parent->flags); + if (IS_ERR_VALUE(xtal_rate)) + return xtal_rate; + pll = &priv->tree->plls[clk->id]; postdiv = (readl(priv->base + pll->pd_reg) >> pll->pd_shift) & @@ -566,8 +584,7 @@ static ulong mtk_apmixedsys_get_rate(struct clk *clk) pcw = readl(priv->base + pll->pcw_reg) >> pll->pcw_shift; pcw &= GENMASK(pll->pcwbits - 1, 0); - return __mtk_pll_recalc_rate(pll, priv->tree->xtal2_rate, - pcw, postdiv); + return __mtk_pll_recalc_rate(pll, xtal_rate, pcw, postdiv); } static int mtk_apmixedsys_enable(struct clk *clk) diff --git a/drivers/clk/mediatek/clk-mtk.h b/drivers/clk/mediatek/clk-mtk.h index 10a0723de47..682b4303585 100644 --- a/drivers/clk/mediatek/clk-mtk.h +++ b/drivers/clk/mediatek/clk-mtk.h @@ -234,7 +234,7 @@ struct mtk_gate { /* struct mtk_clk_tree - clock tree */ struct mtk_clk_tree { unsigned long xtal_rate; - unsigned long xtal2_rate; + const struct mtk_parent pll_parent; /* External fixed clocks - excluded from mapping. */ const ulong *ext_clk_rates; const int num_ext_clks; -- cgit v1.3.1 From bd07ed20643ad0bd721a66701b1229e54343d382 Mon Sep 17 00:00:00 2001 From: David Lechner Date: Tue, 10 Mar 2026 10:32:15 -0500 Subject: clk: mediatek: mt7622: convert CLK_XTAL to CLK_PAD_CLK25M Replace all uses of CLK_XTAL with CLK_PAD_CLK25M. This avoids declaring the same parent clock two different ways and will eventually let us remove CLK_PARENT_XTAL completely. Reviewed-by: Julien Stephan Link: https://patch.msgid.link/20260310-clk-mtk-parent-cleanup-v1-2-66175ca8f637@baylibre.com Signed-off-by: David Lechner --- drivers/clk/mediatek/clk-mt7622.c | 109 ++++++++++++++++++++------------------ 1 file changed, 56 insertions(+), 53 deletions(-) diff --git a/drivers/clk/mediatek/clk-mt7622.c b/drivers/clk/mediatek/clk-mt7622.c index c94b4b0e0ed..5c38df70474 100644 --- a/drivers/clk/mediatek/clk-mt7622.c +++ b/drivers/clk/mediatek/clk-mt7622.c @@ -94,7 +94,7 @@ static const struct mtk_gate apmixed_cgs[] = { /* topckgen */ #define FIXED_CLK0(_id, _rate) \ - FIXED_CLK(_id, CLK_XTAL, CLK_PARENT_XTAL, _rate) + FIXED_CLK(_id, CLK_PAD_CLK25M, CLK_PARENT_EXT, _rate) #define FACTOR0(_id, _parent, _mult, _div) \ FACTOR(_id, _parent, _mult, _div, CLK_PARENT_APMIXED) @@ -103,7 +103,7 @@ static const struct mtk_gate apmixed_cgs[] = { FACTOR(_id, _parent, _mult, _div, CLK_PARENT_TOPCKGEN) #define FACTOR2(_id, _parent, _mult, _div) \ - FACTOR(_id, _parent, _mult, _div, CLK_PARENT_XTAL) + FACTOR(_id, _parent, _mult, _div, CLK_PARENT_EXT) static const struct mtk_fixed_clk top_fixed_clks[] = { FIXED_CLK0(CLK_TOP_TO_U2_PHY, 31250000), @@ -124,8 +124,8 @@ static const struct mtk_fixed_factor top_fixed_divs[] = { FACTOR0(CLK_TOP_4MHZ, CLK_APMIXED_ETH1PLL, 1, 125), FACTOR0(CLK_TOP_P0_1MHZ, CLK_APMIXED_ETH1PLL, 1, 500), FACTOR1(CLK_TOP_TXCLK_SRC_PRE, CLK_TOP_SGMIIPLL_D2, 1, 1), - FACTOR2(CLK_TOP_RTC, CLK_XTAL, 1, 1024), - FACTOR2(CLK_TOP_MEMPLL, CLK_XTAL, 32, 1), + FACTOR2(CLK_TOP_RTC, CLK_PAD_CLK25M, 1, 1024), + FACTOR2(CLK_TOP_MEMPLL, CLK_PAD_CLK25M, 32, 1), FACTOR1(CLK_TOP_DMPLL, CLK_TOP_MEMPLL, 1, 1), FACTOR0(CLK_TOP_SYSPLL_D2, CLK_APMIXED_MAINPLL, 1, 2), FACTOR0(CLK_TOP_SYSPLL1_D2, CLK_APMIXED_MAINPLL, 1, 4), @@ -168,7 +168,7 @@ static const struct mtk_fixed_factor top_fixed_divs[] = { }; static const struct mtk_parent axi_parents[] = { - XTAL_PARENT(CLK_XTAL), + EXT_PARENT(CLK_PAD_CLK25M), TOP_PARENT(CLK_TOP_SYSPLL1_D2), TOP_PARENT(CLK_TOP_SYSPLL_D5), TOP_PARENT(CLK_TOP_SYSPLL1_D4), @@ -178,17 +178,17 @@ static const struct mtk_parent axi_parents[] = { }; static const struct mtk_parent mem_parents[] = { - XTAL_PARENT(CLK_XTAL), + EXT_PARENT(CLK_PAD_CLK25M), TOP_PARENT(CLK_TOP_DMPLL), }; static const struct mtk_parent ddrphycfg_parents[] = { - XTAL_PARENT(CLK_XTAL), + EXT_PARENT(CLK_PAD_CLK25M), TOP_PARENT(CLK_TOP_SYSPLL1_D8), }; static const struct mtk_parent eth_parents[] = { - XTAL_PARENT(CLK_XTAL), + EXT_PARENT(CLK_PAD_CLK25M), TOP_PARENT(CLK_TOP_SYSPLL1_D2), TOP_PARENT(CLK_TOP_UNIVPLL1_D2), TOP_PARENT(CLK_TOP_SYSPLL1_D4), @@ -198,24 +198,24 @@ static const struct mtk_parent eth_parents[] = { }; static const struct mtk_parent pwm_parents[] = { - XTAL_PARENT(CLK_XTAL), + EXT_PARENT(CLK_PAD_CLK25M), TOP_PARENT(CLK_TOP_UNIVPLL2_D4), }; static const struct mtk_parent f10m_ref_parents[] = { - XTAL_PARENT(CLK_XTAL), + EXT_PARENT(CLK_PAD_CLK25M), TOP_PARENT(CLK_TOP_SYSPLL4_D16), }; static const struct mtk_parent nfi_infra_parents[] = { - XTAL_PARENT(CLK_XTAL), - XTAL_PARENT(CLK_XTAL), - XTAL_PARENT(CLK_XTAL), - XTAL_PARENT(CLK_XTAL), - XTAL_PARENT(CLK_XTAL), - XTAL_PARENT(CLK_XTAL), - XTAL_PARENT(CLK_XTAL), - XTAL_PARENT(CLK_XTAL), + EXT_PARENT(CLK_PAD_CLK25M), + EXT_PARENT(CLK_PAD_CLK25M), + EXT_PARENT(CLK_PAD_CLK25M), + EXT_PARENT(CLK_PAD_CLK25M), + EXT_PARENT(CLK_PAD_CLK25M), + EXT_PARENT(CLK_PAD_CLK25M), + EXT_PARENT(CLK_PAD_CLK25M), + EXT_PARENT(CLK_PAD_CLK25M), TOP_PARENT(CLK_TOP_UNIVPLL2_D8), TOP_PARENT(CLK_TOP_SYSPLL1_D8), TOP_PARENT(CLK_TOP_UNIVPLL1_D8), @@ -226,7 +226,7 @@ static const struct mtk_parent nfi_infra_parents[] = { }; static const struct mtk_parent flash_parents[] = { - XTAL_PARENT(CLK_XTAL), + EXT_PARENT(CLK_PAD_CLK25M), TOP_PARENT(CLK_TOP_UNIVPLL_D80_D4), TOP_PARENT(CLK_TOP_SYSPLL2_D8), TOP_PARENT(CLK_TOP_SYSPLL3_D4), @@ -237,61 +237,61 @@ static const struct mtk_parent flash_parents[] = { }; static const struct mtk_parent uart_parents[] = { - XTAL_PARENT(CLK_XTAL), + EXT_PARENT(CLK_PAD_CLK25M), TOP_PARENT(CLK_TOP_UNIVPLL2_D8), }; static const struct mtk_parent spi0_parents[] = { - XTAL_PARENT(CLK_XTAL), + EXT_PARENT(CLK_PAD_CLK25M), TOP_PARENT(CLK_TOP_SYSPLL3_D2), - XTAL_PARENT(CLK_XTAL), + EXT_PARENT(CLK_PAD_CLK25M), TOP_PARENT(CLK_TOP_SYSPLL2_D4), TOP_PARENT(CLK_TOP_SYSPLL4_D2), TOP_PARENT(CLK_TOP_UNIVPLL2_D4), TOP_PARENT(CLK_TOP_UNIVPLL1_D8), - XTAL_PARENT(CLK_XTAL), + EXT_PARENT(CLK_PAD_CLK25M), }; static const struct mtk_parent spi1_parents[] = { - XTAL_PARENT(CLK_XTAL), + EXT_PARENT(CLK_PAD_CLK25M), TOP_PARENT(CLK_TOP_SYSPLL3_D2), - XTAL_PARENT(CLK_XTAL), + EXT_PARENT(CLK_PAD_CLK25M), TOP_PARENT(CLK_TOP_SYSPLL4_D4), TOP_PARENT(CLK_TOP_SYSPLL4_D2), TOP_PARENT(CLK_TOP_UNIVPLL2_D4), TOP_PARENT(CLK_TOP_UNIVPLL1_D8), - XTAL_PARENT(CLK_XTAL), + EXT_PARENT(CLK_PAD_CLK25M), }; static const struct mtk_parent msdc30_0_parents[] = { - XTAL_PARENT(CLK_XTAL), + EXT_PARENT(CLK_PAD_CLK25M), TOP_PARENT(CLK_TOP_UNIVPLL2_D16), TOP_PARENT(CLK_TOP_UNIV48M), }; static const struct mtk_parent a1sys_hp_parents[] = { - XTAL_PARENT(CLK_XTAL), + EXT_PARENT(CLK_PAD_CLK25M), TOP_PARENT(CLK_TOP_AUD1PLL), TOP_PARENT(CLK_TOP_AUD2PLL), - XTAL_PARENT(CLK_XTAL), + EXT_PARENT(CLK_PAD_CLK25M), }; static const struct mtk_parent intdir_parents[] = { - XTAL_PARENT(CLK_XTAL), + EXT_PARENT(CLK_PAD_CLK25M), TOP_PARENT(CLK_TOP_SYSPLL1_D2), TOP_PARENT(CLK_TOP_UNIVPLL_D2), TOP_PARENT(CLK_TOP_SGMIIPLL), }; static const struct mtk_parent aud_intbus_parents[] = { - XTAL_PARENT(CLK_XTAL), + EXT_PARENT(CLK_PAD_CLK25M), TOP_PARENT(CLK_TOP_SYSPLL1_D4), TOP_PARENT(CLK_TOP_SYSPLL4_D2), TOP_PARENT(CLK_TOP_SYSPLL3_D2), }; static const struct mtk_parent pmicspi_parents[] = { - XTAL_PARENT(CLK_XTAL), + EXT_PARENT(CLK_PAD_CLK25M), VOID_PARENT, VOID_PARENT, VOID_PARENT, @@ -300,32 +300,32 @@ static const struct mtk_parent pmicspi_parents[] = { }; static const struct mtk_parent atb_parents[] = { - XTAL_PARENT(CLK_XTAL), + EXT_PARENT(CLK_PAD_CLK25M), TOP_PARENT(CLK_TOP_SYSPLL1_D2), TOP_PARENT(CLK_TOP_SYSPLL_D5), }; static const struct mtk_parent audio_parents[] = { - XTAL_PARENT(CLK_XTAL), + EXT_PARENT(CLK_PAD_CLK25M), TOP_PARENT(CLK_TOP_SYSPLL3_D4), TOP_PARENT(CLK_TOP_SYSPLL4_D4), TOP_PARENT(CLK_TOP_UNIVPLL1_D16), }; static const struct mtk_parent usb20_parents[] = { - XTAL_PARENT(CLK_XTAL), + EXT_PARENT(CLK_PAD_CLK25M), TOP_PARENT(CLK_TOP_UNIVPLL3_D4), TOP_PARENT(CLK_TOP_SYSPLL1_D8), - XTAL_PARENT(CLK_XTAL), + EXT_PARENT(CLK_PAD_CLK25M), }; static const struct mtk_parent aud1_parents[] = { - XTAL_PARENT(CLK_XTAL), + EXT_PARENT(CLK_PAD_CLK25M), TOP_PARENT(CLK_TOP_AUD1PLL), }; static const struct mtk_parent asm_l_parents[] = { - XTAL_PARENT(CLK_XTAL), + EXT_PARENT(CLK_PAD_CLK25M), TOP_PARENT(CLK_TOP_SYSPLL_D5), TOP_PARENT(CLK_TOP_UNIVPLL2_D2), TOP_PARENT(CLK_TOP_UNIVPLL2_D4), @@ -396,7 +396,7 @@ static const struct mtk_composite top_muxes[] = { /* infracfg */ static const struct mtk_parent infra_mux1_parents[] = { - XTAL_PARENT(CLK_XTAL), + EXT_PARENT(CLK_PAD_CLK25M), APMIXED_PARENT(CLK_APMIXED_MAINPLL), APMIXED_PARENT(CLK_APMIXED_MAIN_CORE_EN), APMIXED_PARENT(CLK_APMIXED_MAINPLL), @@ -460,8 +460,8 @@ static const struct mtk_gate_regs peri1_cg_regs = { } #define GATE_PERI0(_id, _parent, _shift) \ GATE_PERI0_FLAGS(_id, _parent, _shift, CLK_GATE_SETCLR | CLK_PARENT_TOPCKGEN) -#define GATE_PERI0_XTAL(_id, _parent, _shift) \ - GATE_PERI0_FLAGS(_id, _parent, _shift, CLK_GATE_SETCLR | CLK_PARENT_XTAL) +#define GATE_PERI0_EXT(_id, _parent, _shift) \ + GATE_PERI0_FLAGS(_id, _parent, _shift, CLK_GATE_SETCLR | CLK_PARENT_EXT) #define GATE_PERI1(_id, _parent, _shift) { \ .id = _id, \ @@ -474,14 +474,14 @@ static const struct mtk_gate_regs peri1_cg_regs = { static const struct mtk_gate peri_cgs[] = { /* PERI0 */ GATE_PERI0(CLK_PERI_THERM_PD, CLK_TOP_AXI_SEL, 1), - GATE_PERI0_XTAL(CLK_PERI_PWM1_PD, CLK_XTAL, 2), - GATE_PERI0_XTAL(CLK_PERI_PWM2_PD, CLK_XTAL, 3), - GATE_PERI0_XTAL(CLK_PERI_PWM3_PD, CLK_XTAL, 4), - GATE_PERI0_XTAL(CLK_PERI_PWM4_PD, CLK_XTAL, 5), - GATE_PERI0_XTAL(CLK_PERI_PWM5_PD, CLK_XTAL, 6), - GATE_PERI0_XTAL(CLK_PERI_PWM6_PD, CLK_XTAL, 7), - GATE_PERI0_XTAL(CLK_PERI_PWM7_PD, CLK_XTAL, 8), - GATE_PERI0_XTAL(CLK_PERI_PWM_PD, CLK_XTAL, 9), + GATE_PERI0_EXT(CLK_PERI_PWM1_PD, CLK_PAD_CLK25M, 2), + GATE_PERI0_EXT(CLK_PERI_PWM2_PD, CLK_PAD_CLK25M, 3), + GATE_PERI0_EXT(CLK_PERI_PWM3_PD, CLK_PAD_CLK25M, 4), + GATE_PERI0_EXT(CLK_PERI_PWM4_PD, CLK_PAD_CLK25M, 5), + GATE_PERI0_EXT(CLK_PERI_PWM5_PD, CLK_PAD_CLK25M, 6), + GATE_PERI0_EXT(CLK_PERI_PWM6_PD, CLK_PAD_CLK25M, 7), + GATE_PERI0_EXT(CLK_PERI_PWM7_PD, CLK_PAD_CLK25M, 8), + GATE_PERI0_EXT(CLK_PERI_PWM_PD, CLK_PAD_CLK25M, 9), GATE_PERI0(CLK_PERI_AP_DMA_PD, CLK_TOP_AXI_SEL, 12), GATE_PERI0(CLK_PERI_MSDC30_0_PD, CLK_TOP_MSDC30_0_SEL, 13), GATE_PERI0(CLK_PERI_MSDC30_1_PD, CLK_TOP_MSDC30_1_SEL, 14), @@ -495,7 +495,7 @@ static const struct mtk_gate peri_cgs[] = { GATE_PERI0(CLK_PERI_I2C1_PD, CLK_TOP_AXI_SEL, 24), GATE_PERI0(CLK_PERI_I2C2_PD, CLK_TOP_AXI_SEL, 25), GATE_PERI0(CLK_PERI_SPI1_PD, CLK_TOP_SPI1_SEL, 26), - GATE_PERI0_XTAL(CLK_PERI_AUXADC_PD, CLK_XTAL, 27), + GATE_PERI0_EXT(CLK_PERI_AUXADC_PD, CLK_PAD_CLK25M, 27), GATE_PERI0(CLK_PERI_SPI0_PD, CLK_TOP_SPI0_SEL, 28), GATE_PERI0(CLK_PERI_SNFI_PD, CLK_TOP_NFI_INFRA_SEL, 29), GATE_PERI0(CLK_PERI_NFI_PD, CLK_TOP_AXI_SEL, 30), @@ -616,7 +616,8 @@ static const struct mtk_clk_tree mt7622_apmixed_clk_tree = { }; static const struct mtk_clk_tree mt7622_infra_clk_tree = { - .xtal_rate = 25 * MHZ, + .ext_clk_rates = ext_clock_rates, + .num_ext_clks = ARRAY_SIZE(ext_clock_rates), .muxes_offs = CLK_INFRA_MUX1_SEL, .gates_offs = CLK_INFRA_DBGCLK_PD, .muxes = infra_muxes, @@ -626,7 +627,8 @@ static const struct mtk_clk_tree mt7622_infra_clk_tree = { }; static const struct mtk_clk_tree mt7622_peri_clk_tree = { - .xtal_rate = 25 * MHZ, + .ext_clk_rates = ext_clock_rates, + .num_ext_clks = ARRAY_SIZE(ext_clock_rates), .muxes_offs = CLK_PERIBUS_SEL, .gates_offs = CLK_PERI_THERM_PD, .muxes = peri_muxes, @@ -636,7 +638,8 @@ static const struct mtk_clk_tree mt7622_peri_clk_tree = { }; static const struct mtk_clk_tree mt7622_clk_tree = { - .xtal_rate = 25 * MHZ, + .ext_clk_rates = ext_clock_rates, + .num_ext_clks = ARRAY_SIZE(ext_clock_rates), .fdivs_offs = CLK_TOP_TO_USB3_SYS, .muxes_offs = CLK_TOP_AXI_SEL, .fclks = top_fixed_clks, -- cgit v1.3.1 From 284025cc6e3bf66587d37ae97f88ffed9797dcb8 Mon Sep 17 00:00:00 2001 From: David Lechner Date: Tue, 10 Mar 2026 10:32:16 -0500 Subject: clk: mediatek: mt7623: convert CLK_XTAL to CLK_PAD_CLK26M Replace all uses of CLK_XTAL with CLK_PAD_CLK26M. This avoids declaring the same parent clock two different ways and will eventually let us remove CLK_PARENT_XTAL completely. Reviewed-by: Julien Stephan Link: https://patch.msgid.link/20260310-clk-mtk-parent-cleanup-v1-3-66175ca8f637@baylibre.com Signed-off-by: David Lechner --- drivers/clk/mediatek/clk-mt7623.c | 135 +++++++++++++++++++------------------- 1 file changed, 69 insertions(+), 66 deletions(-) diff --git a/drivers/clk/mediatek/clk-mt7623.c b/drivers/clk/mediatek/clk-mt7623.c index 1c34bfbf596..41bd91a8e05 100644 --- a/drivers/clk/mediatek/clk-mt7623.c +++ b/drivers/clk/mediatek/clk-mt7623.c @@ -268,7 +268,7 @@ static const int top_id_offs_map[CLK_TOP_NR + 1] = { }; #define FIXED_CLK0(_id, _rate) \ - FIXED_CLK(_id, CLK_XTAL, CLK_PARENT_XTAL, _rate) + FIXED_CLK(_id, CLK_PAD_CLK26M, CLK_PARENT_EXT, _rate) #define FACTOR0(_id, _parent, _mult, _div) \ FACTOR(_id, _parent, _mult, _div, CLK_PARENT_APMIXED) @@ -277,7 +277,7 @@ static const int top_id_offs_map[CLK_TOP_NR + 1] = { FACTOR(_id, _parent, _mult, _div, CLK_PARENT_TOPCKGEN) #define FACTOR2(_id, _parent, _mult, _div) \ - FACTOR(_id, _parent, _mult, _div, CLK_PARENT_XTAL) + FACTOR(_id, _parent, _mult, _div, CLK_PARENT_EXT) static const struct mtk_fixed_clk top_fixed_clks[] = { FIXED_CLK0(CLK_TOP_DPI, 108 * MHZ), @@ -377,14 +377,14 @@ static const struct mtk_fixed_factor top_fixed_divs[] = { FACTOR0(CLK_TOP_HADDS2PLL_98M, CLK_APMIXED_HADDS2PLL, 1, 3), FACTOR0(CLK_TOP_HADDS2PLL_294M, CLK_APMIXED_HADDS2PLL, 1, 1), FACTOR0(CLK_TOP_ETHPLL_500M, CLK_APMIXED_ETHPLL, 1, 1), - FACTOR2(CLK_TOP_CLK26M_D8, CLK_XTAL, 1, 8), - FACTOR2(CLK_TOP_32K_INTERNAL, CLK_XTAL, 1, 793), + FACTOR2(CLK_TOP_CLK26M_D8, CLK_PAD_CLK26M, 1, 8), + FACTOR2(CLK_TOP_32K_INTERNAL, CLK_PAD_CLK26M, 1, 793), FACTOR1(CLK_TOP_AXISEL_D4, CLK_TOP_AXI_SEL, 1, 4), FACTOR1(CLK_TOP_8BDAC, CLK_TOP_UNIVPLL_D2, 1, 1), }; static const struct mtk_parent axi_parents[] = { - XTAL_PARENT(CLK_XTAL), + EXT_PARENT(CLK_PAD_CLK26M), TOP_PARENT(CLK_TOP_SYSPLL1_D2), TOP_PARENT(CLK_TOP_SYSPLL_D5), TOP_PARENT(CLK_TOP_SYSPLL1_D4), @@ -395,17 +395,17 @@ static const struct mtk_parent axi_parents[] = { }; static const struct mtk_parent mem_parents[] = { - XTAL_PARENT(CLK_XTAL), + EXT_PARENT(CLK_PAD_CLK26M), TOP_PARENT(CLK_TOP_DMPLL), }; static const struct mtk_parent ddrphycfg_parents[] = { - XTAL_PARENT(CLK_XTAL), + EXT_PARENT(CLK_PAD_CLK26M), TOP_PARENT(CLK_TOP_SYSPLL1_D8), }; static const struct mtk_parent mm_parents[] = { - XTAL_PARENT(CLK_XTAL), + EXT_PARENT(CLK_PAD_CLK26M), TOP_PARENT(CLK_TOP_VENCPLL), TOP_PARENT(CLK_TOP_SYSPLL1_D2), TOP_PARENT(CLK_TOP_SYSPLL1_D4), @@ -416,14 +416,14 @@ static const struct mtk_parent mm_parents[] = { }; static const struct mtk_parent pwm_parents[] = { - XTAL_PARENT(CLK_XTAL), + EXT_PARENT(CLK_PAD_CLK26M), TOP_PARENT(CLK_TOP_UNIVPLL2_D4), TOP_PARENT(CLK_TOP_UNIVPLL3_D2), TOP_PARENT(CLK_TOP_UNIVPLL1_D4), }; static const struct mtk_parent vdec_parents[] = { - XTAL_PARENT(CLK_XTAL), + EXT_PARENT(CLK_PAD_CLK26M), TOP_PARENT(CLK_TOP_VDECPLL), TOP_PARENT(CLK_TOP_SYSPLL_D5), TOP_PARENT(CLK_TOP_SYSPLL1_D4), @@ -435,18 +435,18 @@ static const struct mtk_parent vdec_parents[] = { }; static const struct mtk_parent mfg_parents[] = { - XTAL_PARENT(CLK_XTAL), + EXT_PARENT(CLK_PAD_CLK26M), TOP_PARENT(CLK_TOP_MMPLL), TOP_PARENT(CLK_TOP_DMPLL_X2), TOP_PARENT(CLK_TOP_MSDCPLL), - XTAL_PARENT(CLK_XTAL), + EXT_PARENT(CLK_PAD_CLK26M), TOP_PARENT(CLK_TOP_SYSPLL_D3), TOP_PARENT(CLK_TOP_UNIVPLL_D3), TOP_PARENT(CLK_TOP_UNIVPLL1_D2), }; static const struct mtk_parent camtg_parents[] = { - XTAL_PARENT(CLK_XTAL), + EXT_PARENT(CLK_PAD_CLK26M), TOP_PARENT(CLK_TOP_UNIVPLL_D26), TOP_PARENT(CLK_TOP_UNIVPLL2_D2), TOP_PARENT(CLK_TOP_SYSPLL3_D2), @@ -456,12 +456,12 @@ static const struct mtk_parent camtg_parents[] = { }; static const struct mtk_parent uart_parents[] = { - XTAL_PARENT(CLK_XTAL), + EXT_PARENT(CLK_PAD_CLK26M), TOP_PARENT(CLK_TOP_UNIVPLL2_D8), }; static const struct mtk_parent spi_parents[] = { - XTAL_PARENT(CLK_XTAL), + EXT_PARENT(CLK_PAD_CLK26M), TOP_PARENT(CLK_TOP_SYSPLL3_D2), TOP_PARENT(CLK_TOP_SYSPLL4_D2), TOP_PARENT(CLK_TOP_UNIVPLL2_D4), @@ -469,13 +469,13 @@ static const struct mtk_parent spi_parents[] = { }; static const struct mtk_parent usb20_parents[] = { - XTAL_PARENT(CLK_XTAL), + EXT_PARENT(CLK_PAD_CLK26M), TOP_PARENT(CLK_TOP_UNIVPLL1_D8), TOP_PARENT(CLK_TOP_UNIVPLL3_D4), }; static const struct mtk_parent msdc30_parents[] = { - XTAL_PARENT(CLK_XTAL), + EXT_PARENT(CLK_PAD_CLK26M), TOP_PARENT(CLK_TOP_MSDCPLL_D2), TOP_PARENT(CLK_TOP_SYSPLL2_D2), TOP_PARENT(CLK_TOP_SYSPLL1_D4), @@ -484,7 +484,7 @@ static const struct mtk_parent msdc30_parents[] = { }; static const struct mtk_parent aud_intbus_parents[] = { - XTAL_PARENT(CLK_XTAL), + EXT_PARENT(CLK_PAD_CLK26M), TOP_PARENT(CLK_TOP_SYSPLL1_D4), TOP_PARENT(CLK_TOP_SYSPLL3_D2), TOP_PARENT(CLK_TOP_SYSPLL4_D2), @@ -493,7 +493,7 @@ static const struct mtk_parent aud_intbus_parents[] = { }; static const struct mtk_parent pmicspi_parents[] = { - XTAL_PARENT(CLK_XTAL), + EXT_PARENT(CLK_PAD_CLK26M), TOP_PARENT(CLK_TOP_SYSPLL1_D8), TOP_PARENT(CLK_TOP_SYSPLL2_D4), TOP_PARENT(CLK_TOP_SYSPLL4_D2), @@ -507,68 +507,68 @@ static const struct mtk_parent pmicspi_parents[] = { }; static const struct mtk_parent scp_parents[] = { - XTAL_PARENT(CLK_XTAL), + EXT_PARENT(CLK_PAD_CLK26M), TOP_PARENT(CLK_TOP_SYSPLL1_D8), TOP_PARENT(CLK_TOP_DMPLL_D2), TOP_PARENT(CLK_TOP_DMPLL_D4), }; static const struct mtk_parent dpi0_tve_parents[] = { - XTAL_PARENT(CLK_XTAL), + EXT_PARENT(CLK_PAD_CLK26M), TOP_PARENT(CLK_TOP_MIPIPLL), TOP_PARENT(CLK_TOP_MIPIPLL_D2), TOP_PARENT(CLK_TOP_MIPIPLL_D4), - XTAL_PARENT(CLK_XTAL), + EXT_PARENT(CLK_PAD_CLK26M), TOP_PARENT(CLK_TOP_TVDPLL), TOP_PARENT(CLK_TOP_TVDPLL_D2), TOP_PARENT(CLK_TOP_TVDPLL_D4), }; static const struct mtk_parent dpi1_parents[] = { - XTAL_PARENT(CLK_XTAL), + EXT_PARENT(CLK_PAD_CLK26M), TOP_PARENT(CLK_TOP_TVDPLL), TOP_PARENT(CLK_TOP_TVDPLL_D2), TOP_PARENT(CLK_TOP_TVDPLL_D4), }; static const struct mtk_parent hdmi_parents[] = { - XTAL_PARENT(CLK_XTAL), + EXT_PARENT(CLK_PAD_CLK26M), TOP_PARENT(CLK_TOP_HDMIPLL), TOP_PARENT(CLK_TOP_HDMIPLL_D2), TOP_PARENT(CLK_TOP_HDMIPLL_D3), }; static const struct mtk_parent apll_parents[] = { - XTAL_PARENT(CLK_XTAL), + EXT_PARENT(CLK_PAD_CLK26M), TOP_PARENT(CLK_TOP_AUDPLL), TOP_PARENT(CLK_TOP_AUDPLL_D4), TOP_PARENT(CLK_TOP_AUDPLL_D8), TOP_PARENT(CLK_TOP_AUDPLL_D16), TOP_PARENT(CLK_TOP_AUDPLL_D24), - XTAL_PARENT(CLK_XTAL), - XTAL_PARENT(CLK_XTAL), + EXT_PARENT(CLK_PAD_CLK26M), + EXT_PARENT(CLK_PAD_CLK26M), }; static const struct mtk_parent rtc_parents[] = { TOP_PARENT(CLK_TOP_32K_INTERNAL), TOP_PARENT(CLK_TOP_32K_EXTERNAL), - XTAL_PARENT(CLK_XTAL), + EXT_PARENT(CLK_PAD_CLK26M), TOP_PARENT(CLK_TOP_UNIVPLL3_D8), }; static const struct mtk_parent nfi2x_parents[] = { - XTAL_PARENT(CLK_XTAL), + EXT_PARENT(CLK_PAD_CLK26M), TOP_PARENT(CLK_TOP_SYSPLL2_D2), TOP_PARENT(CLK_TOP_SYSPLL_D7), TOP_PARENT(CLK_TOP_UNIVPLL3_D2), TOP_PARENT(CLK_TOP_SYSPLL2_D4), TOP_PARENT(CLK_TOP_UNIVPLL3_D4), TOP_PARENT(CLK_TOP_SYSPLL4_D4), - XTAL_PARENT(CLK_XTAL), + EXT_PARENT(CLK_PAD_CLK26M), }; static const struct mtk_parent emmc_hclk_parents[] = { - XTAL_PARENT(CLK_XTAL), + EXT_PARENT(CLK_PAD_CLK26M), TOP_PARENT(CLK_TOP_SYSPLL1_D2), TOP_PARENT(CLK_TOP_SYSPLL1_D4), TOP_PARENT(CLK_TOP_SYSPLL2_D2), @@ -576,7 +576,7 @@ static const struct mtk_parent emmc_hclk_parents[] = { static const struct mtk_parent flash_parents[] = { TOP_PARENT(CLK_TOP_CLK26M_D8), - XTAL_PARENT(CLK_XTAL), + EXT_PARENT(CLK_PAD_CLK26M), TOP_PARENT(CLK_TOP_SYSPLL2_D8), TOP_PARENT(CLK_TOP_SYSPLL3_D4), TOP_PARENT(CLK_TOP_UNIVPLL3_D4), @@ -586,14 +586,14 @@ static const struct mtk_parent flash_parents[] = { }; static const struct mtk_parent di_parents[] = { - XTAL_PARENT(CLK_XTAL), + EXT_PARENT(CLK_PAD_CLK26M), TOP_PARENT(CLK_TOP_TVD2PLL), TOP_PARENT(CLK_TOP_TVD2PLL_D2), - XTAL_PARENT(CLK_XTAL), + EXT_PARENT(CLK_PAD_CLK26M), }; static const struct mtk_parent nr_osd_parents[] = { - XTAL_PARENT(CLK_XTAL), + EXT_PARENT(CLK_PAD_CLK26M), TOP_PARENT(CLK_TOP_VENCPLL), TOP_PARENT(CLK_TOP_SYSPLL1_D2), TOP_PARENT(CLK_TOP_SYSPLL1_D4), @@ -604,38 +604,38 @@ static const struct mtk_parent nr_osd_parents[] = { }; static const struct mtk_parent hdmirx_bist_parents[] = { - XTAL_PARENT(CLK_XTAL), + EXT_PARENT(CLK_PAD_CLK26M), TOP_PARENT(CLK_TOP_SYSPLL_D3), - XTAL_PARENT(CLK_XTAL), + EXT_PARENT(CLK_PAD_CLK26M), TOP_PARENT(CLK_TOP_SYSPLL1_D16), TOP_PARENT(CLK_TOP_SYSPLL4_D2), TOP_PARENT(CLK_TOP_SYSPLL1_D4), TOP_PARENT(CLK_TOP_VENCPLL), - XTAL_PARENT(CLK_XTAL), + EXT_PARENT(CLK_PAD_CLK26M), }; static const struct mtk_parent intdir_parents[] = { - XTAL_PARENT(CLK_XTAL), + EXT_PARENT(CLK_PAD_CLK26M), TOP_PARENT(CLK_TOP_MMPLL), TOP_PARENT(CLK_TOP_SYSPLL_D2), TOP_PARENT(CLK_TOP_UNIVPLL_D2), }; static const struct mtk_parent asm_parents[] = { - XTAL_PARENT(CLK_XTAL), + EXT_PARENT(CLK_PAD_CLK26M), TOP_PARENT(CLK_TOP_UNIVPLL2_D4), TOP_PARENT(CLK_TOP_UNIVPLL2_D2), TOP_PARENT(CLK_TOP_SYSPLL_D5), }; static const struct mtk_parent ms_card_parents[] = { - XTAL_PARENT(CLK_XTAL), + EXT_PARENT(CLK_PAD_CLK26M), TOP_PARENT(CLK_TOP_UNIVPLL3_D8), TOP_PARENT(CLK_TOP_SYSPLL4_D4), }; static const struct mtk_parent ethif_parents[] = { - XTAL_PARENT(CLK_XTAL), + EXT_PARENT(CLK_PAD_CLK26M), TOP_PARENT(CLK_TOP_SYSPLL1_D2), TOP_PARENT(CLK_TOP_SYSPLL_D5), TOP_PARENT(CLK_TOP_SYSPLL1_D4), @@ -646,12 +646,12 @@ static const struct mtk_parent ethif_parents[] = { }; static const struct mtk_parent hdmirx_parents[] = { - XTAL_PARENT(CLK_XTAL), + EXT_PARENT(CLK_PAD_CLK26M), TOP_PARENT(CLK_TOP_UNIVPLL_D52), }; static const struct mtk_parent cmsys_parents[] = { - XTAL_PARENT(CLK_XTAL), + EXT_PARENT(CLK_PAD_CLK26M), TOP_PARENT(CLK_TOP_SYSPLL1_D2), TOP_PARENT(CLK_TOP_UNIVPLL1_D2), TOP_PARENT(CLK_TOP_UNIVPLL_D5), @@ -661,18 +661,18 @@ static const struct mtk_parent cmsys_parents[] = { TOP_PARENT(CLK_TOP_SYSPLL3_D2), TOP_PARENT(CLK_TOP_SYSPLL2_D4), TOP_PARENT(CLK_TOP_SYSPLL1_D8), - XTAL_PARENT(CLK_XTAL), - XTAL_PARENT(CLK_XTAL), - XTAL_PARENT(CLK_XTAL), - XTAL_PARENT(CLK_XTAL), - XTAL_PARENT(CLK_XTAL), + EXT_PARENT(CLK_PAD_CLK26M), + EXT_PARENT(CLK_PAD_CLK26M), + EXT_PARENT(CLK_PAD_CLK26M), + EXT_PARENT(CLK_PAD_CLK26M), + EXT_PARENT(CLK_PAD_CLK26M), }; static const struct mtk_parent clk_8bdac_parents[] = { TOP_PARENT(CLK_TOP_32K_INTERNAL), TOP_PARENT(CLK_TOP_8BDAC), - XTAL_PARENT(CLK_XTAL), - XTAL_PARENT(CLK_XTAL), + EXT_PARENT(CLK_PAD_CLK26M), + EXT_PARENT(CLK_PAD_CLK26M), }; static const struct mtk_parent aud2dvd_parents[] = { @@ -681,7 +681,7 @@ static const struct mtk_parent aud2dvd_parents[] = { }; static const struct mtk_parent padmclk_parents[] = { - XTAL_PARENT(CLK_XTAL), + EXT_PARENT(CLK_PAD_CLK26M), TOP_PARENT(CLK_TOP_UNIVPLL_D26), TOP_PARENT(CLK_TOP_UNIVPLL_D52), TOP_PARENT(CLK_TOP_UNIVPLL_D108), @@ -691,7 +691,7 @@ static const struct mtk_parent padmclk_parents[] = { }; static const struct mtk_parent aud_mux_parents[] = { - XTAL_PARENT(CLK_XTAL), + EXT_PARENT(CLK_PAD_CLK26M), TOP_PARENT(CLK_TOP_AUD1PLL_98M), TOP_PARENT(CLK_TOP_AUD2PLL_90M), TOP_PARENT(CLK_TOP_HADDS2PLL_98M), @@ -791,8 +791,8 @@ static const struct mtk_gate_regs infra_cg_regs = { } #define GATE_INFRA(_id, _parent, _shift) \ GATE_INFRA_FLAGS(_id, _parent, _shift, CLK_GATE_SETCLR | CLK_PARENT_TOPCKGEN) -#define GATE_INFRA_XTAL(_id, _parent, _shift) \ - GATE_INFRA_FLAGS(_id, _parent, _shift, CLK_GATE_SETCLR | CLK_PARENT_XTAL) +#define GATE_INFRA_EXT(_id, _parent, _shift) \ + GATE_INFRA_FLAGS(_id, _parent, _shift, CLK_GATE_SETCLR | CLK_PARENT_EXT) static const struct mtk_gate infra_cgs[] = { @@ -800,8 +800,8 @@ static const struct mtk_gate infra_cgs[] = { GATE_INFRA(CLK_INFRA_SMI, CLK_TOP_MM_SEL, 1), GATE_INFRA(CLK_INFRA_QAXI_CM4, CLK_TOP_AXI_SEL, 2), GATE_INFRA(CLK_INFRA_AUD_SPLIN_B, CLK_TOP_HADDS2PLL_294M, 4), - GATE_INFRA_XTAL(CLK_INFRA_AUDIO, CLK_XTAL, 5), - GATE_INFRA_XTAL(CLK_INFRA_EFUSE, CLK_XTAL, 6), + GATE_INFRA_EXT(CLK_INFRA_AUDIO, CLK_PAD_CLK26M, 5), + GATE_INFRA_EXT(CLK_INFRA_EFUSE, CLK_PAD_CLK26M, 6), GATE_INFRA(CLK_INFRA_L2C_SRAM, CLK_TOP_MM_SEL, 7), GATE_INFRA(CLK_INFRA_M4U, CLK_TOP_MEM_SEL, 8), GATE_INFRA(CLK_INFRA_CONNMCU, CLK_TOP_WBG_DIG_416M, 12), @@ -872,7 +872,7 @@ static const int peri_id_offs_map[] = { }; static const struct mtk_parent uart_ck_sel_parents[] = { - XTAL_PARENT(CLK_XTAL), + EXT_PARENT(CLK_PAD_CLK26M), TOP_PARENT(CLK_TOP_UART_SEL), }; @@ -904,8 +904,8 @@ static const struct mtk_gate_regs peri1_cg_regs = { } #define GATE_PERI0(_id, _parent, _shift) \ GATE_PERI0_FLAGS(_id, _parent, _shift, CLK_GATE_SETCLR | CLK_PARENT_TOPCKGEN) -#define GATE_PERI0_XTAL(_id, _parent, _shift) \ - GATE_PERI0_FLAGS(_id, _parent, _shift, CLK_GATE_SETCLR | CLK_PARENT_XTAL) +#define GATE_PERI0_EXT(_id, _parent, _shift) \ + GATE_PERI0_FLAGS(_id, _parent, _shift, CLK_GATE_SETCLR | CLK_PARENT_EXT) #define GATE_PERI1(_id, _parent, _shift) { \ .id = _id, \ @@ -943,10 +943,10 @@ static const struct mtk_gate peri_cgs[] = { GATE_PERI0(CLK_PERI_I2C0, CLK_TOP_AXI_SEL, 24), GATE_PERI0(CLK_PERI_I2C1, CLK_TOP_AXI_SEL, 25), GATE_PERI0(CLK_PERI_I2C2, CLK_TOP_AXI_SEL, 26), - GATE_PERI0_XTAL(CLK_PERI_I2C3, CLK_XTAL, 27), - GATE_PERI0_XTAL(CLK_PERI_AUXADC, CLK_XTAL, 28), + GATE_PERI0_EXT(CLK_PERI_I2C3, CLK_PAD_CLK26M, 27), + GATE_PERI0_EXT(CLK_PERI_AUXADC, CLK_PAD_CLK26M, 28), GATE_PERI0(CLK_PERI_SPI0, CLK_TOP_SPI0_SEL, 29), - GATE_PERI0_XTAL(CLK_PERI_ETH, CLK_XTAL, 30), + GATE_PERI0_EXT(CLK_PERI_ETH, CLK_PAD_CLK26M, 30), GATE_PERI0(CLK_PERI_USB0_MCU, CLK_TOP_AXI_SEL, 31), GATE_PERI1(CLK_PERI_USB1_MCU, CLK_TOP_AXI_SEL, 0), @@ -1012,7 +1012,8 @@ static const struct mtk_clk_tree mt7623_apmixedsys_clk_tree = { }; static const struct mtk_clk_tree mt7623_topckgen_clk_tree = { - .xtal_rate = 26 * MHZ, + .ext_clk_rates = ext_clock_rates, + .num_ext_clks = ARRAY_SIZE(ext_clock_rates), .id_offs_map = top_id_offs_map, .id_offs_map_size = ARRAY_SIZE(top_id_offs_map), .fdivs_offs = top_id_offs_map[CLK_TOP_SYSPLL], @@ -1062,7 +1063,8 @@ static int mt7623_topckgen_probe(struct udevice *dev) } static const struct mtk_clk_tree mt7623_clk_gate_tree = { - .xtal_rate = 26 * MHZ, + .ext_clk_rates = ext_clock_rates, + .num_ext_clks = ARRAY_SIZE(ext_clock_rates), }; static int mt7623_infracfg_probe(struct udevice *dev) @@ -1072,6 +1074,8 @@ static int mt7623_infracfg_probe(struct udevice *dev) } static const struct mtk_clk_tree mt7623_clk_peri_tree = { + .ext_clk_rates = ext_clock_rates, + .num_ext_clks = ARRAY_SIZE(ext_clock_rates), .id_offs_map = peri_id_offs_map, .id_offs_map_size = ARRAY_SIZE(peri_id_offs_map), .muxes_offs = peri_id_offs_map[CLK_PERI_UART0_SEL], @@ -1080,7 +1084,6 @@ static const struct mtk_clk_tree mt7623_clk_peri_tree = { .gates = peri_cgs, .num_muxes = ARRAY_SIZE(peri_muxes), .num_gates = ARRAY_SIZE(peri_cgs), - .xtal_rate = 26 * MHZ, }; static int mt7623_pericfg_probe(struct udevice *dev) -- cgit v1.3.1 From 57a3c93336f21e46074a954576b81508ac61dec0 Mon Sep 17 00:00:00 2001 From: David Lechner Date: Tue, 10 Mar 2026 10:32:17 -0500 Subject: clk: mediatek: mt7629: convert CLK_XTAL to CLK_PAD_CLK40M Replace all uses of CLK_XTAL with CLK_PAD_CLK40M. This will eventually let us remove CLK_PARENT_XTAL completely. Reviewed-by: Julien Stephan Link: https://patch.msgid.link/20260310-clk-mtk-parent-cleanup-v1-4-66175ca8f637@baylibre.com Signed-off-by: David Lechner --- drivers/clk/mediatek/clk-mt7629.c | 92 +++++++++++++++++++-------------------- 1 file changed, 46 insertions(+), 46 deletions(-) diff --git a/drivers/clk/mediatek/clk-mt7629.c b/drivers/clk/mediatek/clk-mt7629.c index beba7fc4abc..74510ee36a9 100644 --- a/drivers/clk/mediatek/clk-mt7629.c +++ b/drivers/clk/mediatek/clk-mt7629.c @@ -29,10 +29,12 @@ #define MCU_BUS_SEL(x) ((x) << 9) enum { + CLK_PAD_CLK40M, CLK_PAD_CLK20M, }; static const ulong ext_clock_rates[] = { + [CLK_PAD_CLK40M] = 40 * MHZ, [CLK_PAD_CLK20M] = 20 * MHZ, }; @@ -70,7 +72,7 @@ static const struct mtk_pll_data apmixed_plls[] = { /* topckgen */ #define FIXED_CLK0(_id, _rate) \ - FIXED_CLK(_id, CLK_XTAL, CLK_PARENT_XTAL, _rate) + FIXED_CLK(_id, CLK_PAD_CLK40M, CLK_PARENT_EXT, _rate) #define FACTOR0(_id, _parent, _mult, _div) \ FACTOR(_id, _parent, _mult, _div, CLK_PARENT_APMIXED) @@ -79,7 +81,7 @@ static const struct mtk_pll_data apmixed_plls[] = { FACTOR(_id, _parent, _mult, _div, CLK_PARENT_TOPCKGEN) #define FACTOR2(_id, _parent, _mult, _div) \ - FACTOR(_id, _parent, _mult, _div, CLK_PARENT_XTAL) + FACTOR(_id, _parent, _mult, _div, CLK_PARENT_EXT) static const struct mtk_fixed_clk top_fixed_clks[] = { FIXED_CLK0(CLK_TOP_TO_U2_PHY, 31250000), @@ -101,11 +103,11 @@ static const struct mtk_fixed_factor top_fixed_divs[] = { FACTOR0(CLK_TOP_P0_1MHZ, CLK_APMIXED_ETH1PLL, 1, 500), FACTOR0(CLK_TOP_ETH_500M, CLK_APMIXED_ETH1PLL, 1, 1), FACTOR1(CLK_TOP_TXCLK_SRC_PRE, CLK_TOP_SGMIIPLL_D2, 1, 1), - FACTOR2(CLK_TOP_RTC, CLK_XTAL, 1, 1024), - FACTOR2(CLK_TOP_PWM_QTR_26M, CLK_XTAL, 1, 1), - FACTOR2(CLK_TOP_CPUM_TCK_IN, CLK_XTAL, 1, 1), - FACTOR2(CLK_TOP_TO_USB3_DA_TOP, CLK_XTAL, 1, 1), - FACTOR2(CLK_TOP_MEMPLL, CLK_XTAL, 32, 1), + FACTOR2(CLK_TOP_RTC, CLK_PAD_CLK40M, 1, 1024), + FACTOR2(CLK_TOP_PWM_QTR_26M, CLK_PAD_CLK40M, 1, 1), + FACTOR2(CLK_TOP_CPUM_TCK_IN, CLK_PAD_CLK40M, 1, 1), + FACTOR2(CLK_TOP_TO_USB3_DA_TOP, CLK_PAD_CLK40M, 1, 1), + FACTOR2(CLK_TOP_MEMPLL, CLK_PAD_CLK40M, 32, 1), FACTOR1(CLK_TOP_DMPLL, CLK_TOP_MEMPLL, 1, 1), FACTOR1(CLK_TOP_DMPLL_D4, CLK_TOP_MEMPLL, 1, 4), FACTOR1(CLK_TOP_DMPLL_D8, CLK_TOP_MEMPLL, 1, 8), @@ -141,7 +143,7 @@ static const struct mtk_fixed_factor top_fixed_divs[] = { FACTOR1(CLK_TOP_UNIVPLL_D80_D4, CLK_TOP_UNIVPLL, 1, 320), FACTOR1(CLK_TOP_UNIV48M, CLK_TOP_UNIVPLL, 1, 25), FACTOR0(CLK_TOP_SGMIIPLL_D2, CLK_APMIXED_SGMIPLL, 1, 2), - FACTOR2(CLK_TOP_CLKXTAL_D4, CLK_XTAL, 1, 4), + FACTOR2(CLK_TOP_CLKXTAL_D4, CLK_PAD_CLK40M, 1, 4), FACTOR1(CLK_TOP_HD_FAXI, CLK_TOP_AXI_SEL, 1, 1), FACTOR1(CLK_TOP_FAXI, CLK_TOP_AXI_SEL, 1, 1), FACTOR1(CLK_TOP_F_FAUD_INTBUS, CLK_TOP_AUD_INTBUS_SEL, 1, 1), @@ -161,7 +163,7 @@ static const struct mtk_fixed_factor top_fixed_divs[] = { }; static const struct mtk_parent axi_parents[] = { - XTAL_PARENT(CLK_XTAL), + EXT_PARENT(CLK_PAD_CLK40M), TOP_PARENT(CLK_TOP_SYSPLL1_D2), TOP_PARENT(CLK_TOP_SYSPLL_D5), TOP_PARENT(CLK_TOP_SYSPLL1_D4), @@ -172,17 +174,17 @@ static const struct mtk_parent axi_parents[] = { }; static const struct mtk_parent mem_parents[] = { - XTAL_PARENT(CLK_XTAL), + EXT_PARENT(CLK_PAD_CLK40M), TOP_PARENT(CLK_TOP_DMPLL), }; static const struct mtk_parent ddrphycfg_parents[] = { - XTAL_PARENT(CLK_XTAL), + EXT_PARENT(CLK_PAD_CLK40M), TOP_PARENT(CLK_TOP_SYSPLL1_D8), }; static const struct mtk_parent eth_parents[] = { - XTAL_PARENT(CLK_XTAL), + EXT_PARENT(CLK_PAD_CLK40M), TOP_PARENT(CLK_TOP_SYSPLL1_D2), TOP_PARENT(CLK_TOP_UNIVPLL1_D2), TOP_PARENT(CLK_TOP_SYSPLL1_D4), @@ -193,22 +195,22 @@ static const struct mtk_parent eth_parents[] = { }; static const struct mtk_parent pwm_parents[] = { - XTAL_PARENT(CLK_XTAL), + EXT_PARENT(CLK_PAD_CLK40M), TOP_PARENT(CLK_TOP_UNIVPLL2_D4), }; static const struct mtk_parent sgmii_ref_1_parents[] = { - XTAL_PARENT(CLK_XTAL), + EXT_PARENT(CLK_PAD_CLK40M), TOP_PARENT(CLK_TOP_SGMIIPLL_D2), }; static const struct mtk_parent nfi_infra_parents[] = { - XTAL_PARENT(CLK_XTAL), - XTAL_PARENT(CLK_XTAL), - XTAL_PARENT(CLK_XTAL), - XTAL_PARENT(CLK_XTAL), - XTAL_PARENT(CLK_XTAL), - XTAL_PARENT(CLK_XTAL), + EXT_PARENT(CLK_PAD_CLK40M), + EXT_PARENT(CLK_PAD_CLK40M), + EXT_PARENT(CLK_PAD_CLK40M), + EXT_PARENT(CLK_PAD_CLK40M), + EXT_PARENT(CLK_PAD_CLK40M), + EXT_PARENT(CLK_PAD_CLK40M), TOP_PARENT(CLK_TOP_UNIVPLL2_D8), TOP_PARENT(CLK_TOP_UNIVPLL3_D4), TOP_PARENT(CLK_TOP_SYSPLL1_D8), @@ -222,7 +224,7 @@ static const struct mtk_parent nfi_infra_parents[] = { }; static const struct mtk_parent flash_parents[] = { - XTAL_PARENT(CLK_XTAL), + EXT_PARENT(CLK_PAD_CLK40M), TOP_PARENT(CLK_TOP_UNIVPLL_D80_D4), TOP_PARENT(CLK_TOP_SYSPLL2_D8), TOP_PARENT(CLK_TOP_SYSPLL3_D4), @@ -233,40 +235,40 @@ static const struct mtk_parent flash_parents[] = { }; static const struct mtk_parent uart_parents[] = { - XTAL_PARENT(CLK_XTAL), + EXT_PARENT(CLK_PAD_CLK40M), TOP_PARENT(CLK_TOP_UNIVPLL2_D8), }; static const struct mtk_parent spi0_parents[] = { - XTAL_PARENT(CLK_XTAL), + EXT_PARENT(CLK_PAD_CLK40M), TOP_PARENT(CLK_TOP_SYSPLL3_D2), - XTAL_PARENT(CLK_XTAL), + EXT_PARENT(CLK_PAD_CLK40M), TOP_PARENT(CLK_TOP_SYSPLL2_D4), TOP_PARENT(CLK_TOP_SYSPLL4_D2), TOP_PARENT(CLK_TOP_UNIVPLL2_D4), TOP_PARENT(CLK_TOP_UNIVPLL1_D8), - XTAL_PARENT(CLK_XTAL), + EXT_PARENT(CLK_PAD_CLK40M), }; static const struct mtk_parent spi1_parents[] = { - XTAL_PARENT(CLK_XTAL), + EXT_PARENT(CLK_PAD_CLK40M), TOP_PARENT(CLK_TOP_SYSPLL3_D2), - XTAL_PARENT(CLK_XTAL), + EXT_PARENT(CLK_PAD_CLK40M), TOP_PARENT(CLK_TOP_SYSPLL4_D4), TOP_PARENT(CLK_TOP_SYSPLL4_D2), TOP_PARENT(CLK_TOP_UNIVPLL2_D4), TOP_PARENT(CLK_TOP_UNIVPLL1_D8), - XTAL_PARENT(CLK_XTAL), + EXT_PARENT(CLK_PAD_CLK40M), }; static const struct mtk_parent msdc30_0_parents[] = { - XTAL_PARENT(CLK_XTAL), + EXT_PARENT(CLK_PAD_CLK40M), TOP_PARENT(CLK_TOP_UNIVPLL2_D16), TOP_PARENT(CLK_TOP_UNIV48M), }; static const struct mtk_parent msdc30_1_parents[] = { - XTAL_PARENT(CLK_XTAL), + EXT_PARENT(CLK_PAD_CLK40M), TOP_PARENT(CLK_TOP_UNIVPLL2_D16), TOP_PARENT(CLK_TOP_UNIV48M), TOP_PARENT(CLK_TOP_SYSPLL2_D4), @@ -277,7 +279,7 @@ static const struct mtk_parent msdc30_1_parents[] = { }; static const struct mtk_parent ap2wbmcu_parents[] = { - XTAL_PARENT(CLK_XTAL), + EXT_PARENT(CLK_PAD_CLK40M), TOP_PARENT(CLK_TOP_SYSPLL1_D2), TOP_PARENT(CLK_TOP_UNIV48M), TOP_PARENT(CLK_TOP_SYSPLL1_D8), @@ -288,45 +290,45 @@ static const struct mtk_parent ap2wbmcu_parents[] = { }; static const struct mtk_parent audio_parents[] = { - XTAL_PARENT(CLK_XTAL), + EXT_PARENT(CLK_PAD_CLK40M), TOP_PARENT(CLK_TOP_SYSPLL3_D4), TOP_PARENT(CLK_TOP_SYSPLL4_D4), TOP_PARENT(CLK_TOP_SYSPLL1_D16), }; static const struct mtk_parent aud_intbus_parents[] = { - XTAL_PARENT(CLK_XTAL), + EXT_PARENT(CLK_PAD_CLK40M), TOP_PARENT(CLK_TOP_SYSPLL1_D4), TOP_PARENT(CLK_TOP_SYSPLL4_D2), TOP_PARENT(CLK_TOP_DMPLL_D4), }; static const struct mtk_parent pmicspi_parents[] = { - XTAL_PARENT(CLK_XTAL), + EXT_PARENT(CLK_PAD_CLK40M), TOP_PARENT(CLK_TOP_SYSPLL1_D8), TOP_PARENT(CLK_TOP_SYSPLL3_D4), TOP_PARENT(CLK_TOP_SYSPLL1_D16), TOP_PARENT(CLK_TOP_UNIVPLL3_D4), - XTAL_PARENT(CLK_XTAL), + EXT_PARENT(CLK_PAD_CLK40M), TOP_PARENT(CLK_TOP_UNIVPLL2_D4), TOP_PARENT(CLK_TOP_DMPLL_D8), }; static const struct mtk_parent scp_parents[] = { - XTAL_PARENT(CLK_XTAL), + EXT_PARENT(CLK_PAD_CLK40M), TOP_PARENT(CLK_TOP_SYSPLL1_D8), TOP_PARENT(CLK_TOP_UNIVPLL2_D2), TOP_PARENT(CLK_TOP_UNIVPLL2_D4), }; static const struct mtk_parent atb_parents[] = { - XTAL_PARENT(CLK_XTAL), + EXT_PARENT(CLK_PAD_CLK40M), TOP_PARENT(CLK_TOP_SYSPLL1_D2), TOP_PARENT(CLK_TOP_SYSPLL_D5), }; static const struct mtk_parent hif_parents[] = { - XTAL_PARENT(CLK_XTAL), + EXT_PARENT(CLK_PAD_CLK40M), TOP_PARENT(CLK_TOP_SYSPLL1_D2), TOP_PARENT(CLK_TOP_UNIVPLL1_D2), TOP_PARENT(CLK_TOP_SYSPLL1_D4), @@ -336,27 +338,27 @@ static const struct mtk_parent hif_parents[] = { }; static const struct mtk_parent sata_parents[] = { - XTAL_PARENT(CLK_XTAL), + EXT_PARENT(CLK_PAD_CLK40M), TOP_PARENT(CLK_TOP_UNIVPLL2_D4), }; static const struct mtk_parent usb20_parents[] = { - XTAL_PARENT(CLK_XTAL), + EXT_PARENT(CLK_PAD_CLK40M), TOP_PARENT(CLK_TOP_UNIVPLL3_D4), TOP_PARENT(CLK_TOP_SYSPLL1_D8), }; static const struct mtk_parent aud1_parents[] = { - XTAL_PARENT(CLK_XTAL), + EXT_PARENT(CLK_PAD_CLK40M), }; static const struct mtk_parent irrx_parents[] = { - XTAL_PARENT(CLK_XTAL), + EXT_PARENT(CLK_PAD_CLK40M), TOP_PARENT(CLK_TOP_SYSPLL4_D16), }; static const struct mtk_parent crypto_parents[] = { - XTAL_PARENT(CLK_XTAL), + EXT_PARENT(CLK_PAD_CLK40M), TOP_PARENT(CLK_TOP_UNIVPLL_D3), TOP_PARENT(CLK_TOP_UNIVPLL1_D2), TOP_PARENT(CLK_TOP_SYSPLL1_D2), @@ -367,7 +369,7 @@ static const struct mtk_parent crypto_parents[] = { }; static const struct mtk_parent gpt10m_parents[] = { - XTAL_PARENT(CLK_XTAL), + EXT_PARENT(CLK_PAD_CLK40M), TOP_PARENT(CLK_TOP_CLKXTAL_D4), }; @@ -574,7 +576,6 @@ static const struct mtk_gate ssusb_cgs[] = { }; static const struct mtk_clk_tree mt7629_clk_tree = { - .xtal_rate = 40 * MHZ, .pll_parent = EXT_PARENT(CLK_PAD_CLK20M), .ext_clk_rates = ext_clock_rates, .num_ext_clks = ARRAY_SIZE(ext_clock_rates), @@ -591,7 +592,6 @@ static const struct mtk_clk_tree mt7629_clk_tree = { }; static const struct mtk_clk_tree mt7629_peri_clk_tree = { - .xtal_rate = 40 * MHZ, .pll_parent = EXT_PARENT(CLK_PAD_CLK20M), .ext_clk_rates = ext_clock_rates, .num_ext_clks = ARRAY_SIZE(ext_clock_rates), -- cgit v1.3.1 From ca0d2abc27ddcc62bdc74df4560f59af5845fde8 Mon Sep 17 00:00:00 2001 From: David Lechner Date: Tue, 10 Mar 2026 10:32:18 -0500 Subject: clk: mediatek: mt7981: convert CLK_XTAL to CLK_PAD_CLK40M Replace all uses of CLK_XTAL with CLK_PAD_CLK40M. This will eventually let us remove CLK_PARENT_XTAL completely. Reviewed-by: Julien Stephan Link: https://patch.msgid.link/20260310-clk-mtk-parent-cleanup-v1-5-66175ca8f637@baylibre.com Signed-off-by: David Lechner --- drivers/clk/mediatek/clk-mt7981.c | 17 +++++++++++++++-- 1 file changed, 15 insertions(+), 2 deletions(-) diff --git a/drivers/clk/mediatek/clk-mt7981.c b/drivers/clk/mediatek/clk-mt7981.c index 685abd844f2..8c2944b7fb3 100644 --- a/drivers/clk/mediatek/clk-mt7981.c +++ b/drivers/clk/mediatek/clk-mt7981.c @@ -18,8 +18,16 @@ #define MT7981_CLK_PDN 0x250 #define MT7981_CLK_PDN_EN_WRITE BIT(31) +enum { + CLK_PAD_CLK40M, +}; + +static const ulong ext_clock_rates[] = { + [CLK_PAD_CLK40M] = 40 * MHZ, +}; + #define FIXED_CLK0(_id, _rate) \ - FIXED_CLK(_id, CLK_XTAL, CLK_PARENT_XTAL, _rate) + FIXED_CLK(_id, CLK_PAD_CLK40M, CLK_PARENT_EXT, _rate) #define PLL_FACTOR(_id, _name, _parent, _mult, _div) \ FACTOR(_id, _parent, _mult, _div, CLK_PARENT_APMIXED) @@ -609,13 +617,16 @@ static const struct mtk_gate infracfg_gates[] = { }; static const struct mtk_clk_tree mt7981_fixed_pll_clk_tree = { + .ext_clk_rates = ext_clock_rates, + .num_ext_clks = ARRAY_SIZE(ext_clock_rates), .fdivs_offs = CLK_APMIXED_NR_CLK, - .xtal_rate = 40 * MHZ, .fclks = fixed_pll_clks, .num_fclks = ARRAY_SIZE(fixed_pll_clks), }; static const struct mtk_clk_tree mt7981_topckgen_clk_tree = { + .ext_clk_rates = ext_clock_rates, + .num_ext_clks = ARRAY_SIZE(ext_clock_rates), .fdivs_offs = CLK_TOP_CB_M_416M, .muxes_offs = CLK_TOP_NFI1X_SEL, .fclks = top_fixed_clks, @@ -628,6 +639,8 @@ static const struct mtk_clk_tree mt7981_topckgen_clk_tree = { }; static const struct mtk_clk_tree mt7981_infracfg_clk_tree = { + .ext_clk_rates = ext_clock_rates, + .num_ext_clks = ARRAY_SIZE(ext_clock_rates), .fdivs_offs = CLK_INFRA_66M_MCK, .muxes_offs = CLK_INFRA_UART0_SEL, .gates_offs = CLK_INFRA_GPT_STA, -- cgit v1.3.1 From 7ad6dab0dc0a041a51ccc50b72eb3027fa44d509 Mon Sep 17 00:00:00 2001 From: David Lechner Date: Tue, 10 Mar 2026 10:32:19 -0500 Subject: clk: mediatek: mt7986: convert CLK_XTAL to CLK_PAD_CLK40M Replace all uses of CLK_XTAL with CLK_PAD_CLK40M. This will eventually let us remove CLK_PARENT_XTAL completely. Reviewed-by: Julien Stephan Link: https://patch.msgid.link/20260310-clk-mtk-parent-cleanup-v1-6-66175ca8f637@baylibre.com Signed-off-by: David Lechner --- drivers/clk/mediatek/clk-mt7986.c | 17 +++++++++++++++-- 1 file changed, 15 insertions(+), 2 deletions(-) diff --git a/drivers/clk/mediatek/clk-mt7986.c b/drivers/clk/mediatek/clk-mt7986.c index ed65aa81a21..9c6514120a6 100644 --- a/drivers/clk/mediatek/clk-mt7986.c +++ b/drivers/clk/mediatek/clk-mt7986.c @@ -18,8 +18,16 @@ #define MT7986_CLK_PDN 0x250 #define MT7986_CLK_PDN_EN_WRITE BIT(31) +enum { + CLK_PAD_CLK40M, +}; + +static const ulong ext_clock_rates[] = { + [CLK_PAD_CLK40M] = 40 * MHZ, +}; + #define FIXED_CLK0(_id, _rate) \ - FIXED_CLK(_id, CLK_XTAL, CLK_PARENT_XTAL, _rate) + FIXED_CLK(_id, CLK_PAD_CLK40M, CLK_PARENT_EXT, _rate) #define PLL_FACTOR(_id, _name, _parent, _mult, _div) \ FACTOR(_id, _parent, _mult, _div, CLK_PARENT_APMIXED) @@ -516,14 +524,17 @@ static const struct mtk_gate infracfg_gates[] = { }; static const struct mtk_clk_tree mt7986_fixed_pll_clk_tree = { + .ext_clk_rates = ext_clock_rates, + .num_ext_clks = ARRAY_SIZE(ext_clock_rates), .fdivs_offs = CLK_APMIXED_NR_CLK, - .xtal_rate = 40 * MHZ, .fclks = fixed_pll_clks, .num_fclks = ARRAY_SIZE(fixed_pll_clks), .flags = CLK_PARENT_APMIXED, }; static const struct mtk_clk_tree mt7986_topckgen_clk_tree = { + .ext_clk_rates = ext_clock_rates, + .num_ext_clks = ARRAY_SIZE(ext_clock_rates), .fdivs_offs = CLK_TOP_XTAL_D2, .muxes_offs = CLK_TOP_NFI1X_SEL, .fclks = top_fixed_clks, @@ -536,6 +547,8 @@ static const struct mtk_clk_tree mt7986_topckgen_clk_tree = { }; static const struct mtk_clk_tree mt7986_infracfg_clk_tree = { + .ext_clk_rates = ext_clock_rates, + .num_ext_clks = ARRAY_SIZE(ext_clock_rates), .fdivs_offs = CLK_INFRA_SYSAXI_D2, .muxes_offs = CLK_INFRA_UART0_SEL, .gates_offs = CLK_INFRA_GPT_STA, -- cgit v1.3.1 From b8189e6e148e049ef751dc9c6484efe794729a4e Mon Sep 17 00:00:00 2001 From: David Lechner Date: Tue, 10 Mar 2026 10:32:20 -0500 Subject: clk: mediatek: mt7987: convert CLK_XTAL to CLK_PAD_CLK40M Replace all uses of CLK_XTAL with CLK_PAD_CLK40M. This will eventually let us remove CLK_PARENT_XTAL completely. Reviewed-by: Julien Stephan Link: https://patch.msgid.link/20260310-clk-mtk-parent-cleanup-v1-7-66175ca8f637@baylibre.com Signed-off-by: David Lechner --- drivers/clk/mediatek/clk-mt7987.c | 46 ++++++++++++++++++++++++--------------- 1 file changed, 28 insertions(+), 18 deletions(-) diff --git a/drivers/clk/mediatek/clk-mt7987.c b/drivers/clk/mediatek/clk-mt7987.c index 2fdd0fd20c9..5f102636079 100644 --- a/drivers/clk/mediatek/clk-mt7987.c +++ b/drivers/clk/mediatek/clk-mt7987.c @@ -15,15 +15,22 @@ #include "clk-mtk.h" -#define MT7987_XTAL_RATE (40 * MHZ) #define MT7987_CLK_PDN 0x250 #define MT7987_CLK_PDN_EN_WRITE BIT(31) +enum { + CLK_PAD_CLK40M, +}; + +static const ulong ext_clock_rates[] = { + [CLK_PAD_CLK40M] = 40 * MHZ, +}; + #define FIXED_CLK0(_id, _rate) \ - FIXED_CLK(_id, CLK_XTAL, CLK_PARENT_XTAL, _rate) + FIXED_CLK(_id, CLK_PAD_CLK40M, CLK_PARENT_EXT, _rate) -#define XTAL_FACTOR(_id, _name, _parent, _mult, _div) \ - FACTOR(_id, _parent, _mult, _div, CLK_PARENT_XTAL) +#define EXT_FACTOR(_id, _name, _parent, _mult, _div) \ + FACTOR(_id, _parent, _mult, _div, CLK_PARENT_EXT) #define PLL_FACTOR(_id, _name, _parent, _mult, _div) \ FACTOR(_id, _parent, _mult, _div, CLK_PARENT_APMIXED) @@ -47,11 +54,12 @@ static const struct mtk_fixed_clk apmixedsys_mtk_plls[] = { }; static const struct mtk_clk_tree mt7987_fixed_pll_clk_tree = { + .ext_clk_rates = ext_clock_rates, + .num_ext_clks = ARRAY_SIZE(ext_clock_rates), .fdivs_offs = ARRAY_SIZE(apmixedsys_mtk_plls), .fclks = apmixedsys_mtk_plls, .num_fclks = ARRAY_SIZE(apmixedsys_mtk_plls), .flags = CLK_PARENT_APMIXED, - .xtal_rate = 40 * MHZ, }; static const struct udevice_id mt7987_fixed_pll_compat[] = { @@ -104,7 +112,7 @@ static const struct mtk_fixed_factor topckgen_mtk_fixed_factors[] = { PLL_FACTOR(CLK_TOP_NET2_D7_D2, "net2_d7_d2", CLK_APMIXED_NET2PLL, 1, 14), PLL_FACTOR(CLK_TOP_CB_NET2_D8, "cb_net2_d8", CLK_APMIXED_NET2PLL, 1, 8), PLL_FACTOR(CLK_TOP_MSDC_D2, "msdc_d2", CLK_APMIXED_MSDCPLL, 1, 2), - XTAL_FACTOR(CLK_TOP_CB_CKSQ_40M, "cb_cksq_40m", CLK_XTAL, 1, 1), + EXT_FACTOR(CLK_TOP_CB_CKSQ_40M, "cb_cksq_40m", CLK_PAD_CLK40M, 1, 1), TOP_FACTOR(CLK_TOP_CKSQ_40M_D2, "cksq_40m_d2", CLK_TOP_CB_CKSQ_40M, 1, 2), TOP_FACTOR(CLK_TOP_CB_RTC_32K, "cb_rtc_32k", CLK_TOP_CB_CKSQ_40M, 1, 1250), TOP_FACTOR(CLK_TOP_CB_RTC_32P7K, "cb_rtc_32p7k", CLK_TOP_CB_CKSQ_40M, 1, 1221), @@ -441,13 +449,14 @@ static const struct mtk_composite topckgen_mtk_muxes[] = { }; static const struct mtk_clk_tree mt7987_topckgen_clk_tree = { + .ext_clk_rates = ext_clock_rates, + .num_ext_clks = ARRAY_SIZE(ext_clock_rates), .muxes_offs = CLK_TOP_NETSYS_SEL, .fdivs = topckgen_mtk_fixed_factors, .muxes = topckgen_mtk_muxes, .num_fdivs = ARRAY_SIZE(topckgen_mtk_fixed_factors), .num_muxes = ARRAY_SIZE(topckgen_mtk_muxes), .flags = CLK_PARENT_TOPCKGEN, - .xtal_rate = MT7987_XTAL_RATE, }; static const struct udevice_id mt7987_topckgen_compat[] = { @@ -639,8 +648,8 @@ static const struct mtk_gate_regs infra_3_cg_regs = { GATE_INFRA3(_id, _name, _parent, _shift, CLK_GATE_SETCLR | CLK_PARENT_INFRASYS) #define GATE_INFRA3_TOP(_id, _name, _parent, _shift) \ GATE_INFRA3(_id, _name, _parent, _shift, CLK_GATE_SETCLR | CLK_PARENT_TOPCKGEN) -#define GATE_INFRA3_XTAL(_id, _name, _parent, _shift) \ - GATE_INFRA3(_id, _name, _parent, _shift, CLK_GATE_SETCLR | CLK_PARENT_XTAL) +#define GATE_INFRA3_EXT(_id, _name, _parent, _shift) \ + GATE_INFRA3(_id, _name, _parent, _shift, CLK_GATE_SETCLR | CLK_PARENT_EXT) /* INFRA GATE */ static const struct mtk_gate infracfg_mtk_gates[] = { @@ -741,20 +750,20 @@ static const struct mtk_gate infracfg_mtk_gates[] = { CLK_TOP_CB_CKSQ_40M, 7), GATE_INFRA3_TOP(CLK_INFRA_USB_FRMCNT_CK_P1, "infra_usb_frmcnt_ck_p1", CLK_TOP_CKSQ_40M_D2, 9), - GATE_INFRA3_XTAL(CLK_INFRA_USB_PIPE_CK_P1, - "infra_usb_pipe_ck_p1", CLK_XTAL, 11), - GATE_INFRA3_XTAL(CLK_INFRA_USB_UTMI_CK_P1, - "infra_usb_utmi_ck_p1", CLK_XTAL, 13), + GATE_INFRA3_EXT(CLK_INFRA_USB_PIPE_CK_P1, + "infra_usb_pipe_ck_p1", CLK_PAD_CLK40M, 11), + GATE_INFRA3_EXT(CLK_INFRA_USB_UTMI_CK_P1, + "infra_usb_utmi_ck_p1", CLK_PAD_CLK40M, 13), GATE_INFRA3_TOP(CLK_INFRA_USB_XHCI_CK_P1, "infra_usb_xhci_ck_p1", CLK_TOP_USB_XHCI_P1_SEL, 15), GATE_INFRA3_INFRA(CLK_INFRA_PCIE_GFMUX_TL_P0, "infra_pcie_gfmux_tl_ck_p0", CLK_INFRA_PCIE_GFMUX_TL_O_P0_SEL, 20), GATE_INFRA3_INFRA(CLK_INFRA_PCIE_GFMUX_TL_P1, "infra_pcie_gfmux_tl_ck_p1", CLK_INFRA_PCIE_GFMUX_TL_O_P1_SEL, 21), - GATE_INFRA3_XTAL(CLK_INFRA_PCIE_PIPE_P0, - "infra_pcie_pipe_ck_p0", CLK_XTAL, 24), - GATE_INFRA3_XTAL(CLK_INFRA_PCIE_PIPE_P1, - "infra_pcie_pipe_ck_p1", CLK_XTAL, 25), + GATE_INFRA3_EXT(CLK_INFRA_PCIE_PIPE_P0, + "infra_pcie_pipe_ck_p0", CLK_PAD_CLK40M, 24), + GATE_INFRA3_EXT(CLK_INFRA_PCIE_PIPE_P1, + "infra_pcie_pipe_ck_p1", CLK_PAD_CLK40M, 25), GATE_INFRA3_TOP(CLK_INFRA_133M_PCIE_CK_P0, "infra_133m_pcie_ck_p0", CLK_TOP_SYSAXI_SEL, 28), GATE_INFRA3_TOP(CLK_INFRA_133M_PCIE_CK_P1, @@ -766,13 +775,14 @@ static const struct mtk_gate infracfg_mtk_gates[] = { }; static const struct mtk_clk_tree mt7987_infracfg_clk_tree = { + .ext_clk_rates = ext_clock_rates, + .num_ext_clks = ARRAY_SIZE(ext_clock_rates), .muxes_offs = CLK_INFRA_MUX_UART0_SEL, .gates_offs = CLK_INFRA_66M_GPT_BCK, .muxes = infracfg_mtk_mux, .gates = infracfg_mtk_gates, .num_muxes = ARRAY_SIZE(infracfg_mtk_mux), .num_gates = ARRAY_SIZE(infracfg_mtk_gates), - .xtal_rate = MT7987_XTAL_RATE, }; static const struct udevice_id mt7987_infracfg_compat[] = { -- cgit v1.3.1 From e60c459757aad646bcf2f0a9c208dff222ab24f5 Mon Sep 17 00:00:00 2001 From: David Lechner Date: Tue, 10 Mar 2026 10:32:21 -0500 Subject: clk: mediatek: mt7988: convert CLK_XTAL to CLK_PAD_CLK40M Replace all uses of CLK_XTAL with CLK_PAD_CLK40M. This will eventually let us remove CLK_PARENT_XTAL completely. Reviewed-by: Julien Stephan Link: https://patch.msgid.link/20260310-clk-mtk-parent-cleanup-v1-8-66175ca8f637@baylibre.com Signed-off-by: David Lechner --- drivers/clk/mediatek/clk-mt7988.c | 62 ++++++++++++++++++++++----------------- 1 file changed, 35 insertions(+), 27 deletions(-) diff --git a/drivers/clk/mediatek/clk-mt7988.c b/drivers/clk/mediatek/clk-mt7988.c index f951a6fc58d..4e19f285da0 100644 --- a/drivers/clk/mediatek/clk-mt7988.c +++ b/drivers/clk/mediatek/clk-mt7988.c @@ -21,11 +21,19 @@ #define MT7988_ETHDMA_RST_CTRL_OFS 0x34 #define MT7988_ETHWARP_RST_CTRL_OFS 0x8 +enum { + CLK_PAD_CLK40M, +}; + +static const ulong ext_clock_rates[] = { + [CLK_PAD_CLK40M] = 40 * MHZ, +}; + #define FIXED_CLK0(_id, _rate) \ - FIXED_CLK(_id, CLK_XTAL, CLK_PARENT_XTAL, _rate) + FIXED_CLK(_id, CLK_PAD_CLK40M, CLK_PARENT_EXT, _rate) -#define XTAL_FACTOR(_id, _name, _parent, _mult, _div) \ - FACTOR(_id, _parent, _mult, _div, CLK_PARENT_XTAL) +#define EXT_FACTOR(_id, _name, _parent, _mult, _div) \ + FACTOR(_id, _parent, _mult, _div, CLK_PARENT_EXT) #define PLL_FACTOR(_id, _name, _parent, _mult, _div) \ FACTOR(_id, _parent, _mult, _div, CLK_PARENT_APMIXED) @@ -629,8 +637,8 @@ static const struct mtk_gate_regs infra_3_cg_regs = { GATE_INFRA3(_id, _name, _parent, _shift, CLK_GATE_SETCLR | CLK_PARENT_INFRASYS) #define GATE_INFRA3_TOP(_id, _name, _parent, _shift) \ GATE_INFRA3(_id, _name, _parent, _shift, CLK_GATE_SETCLR | CLK_PARENT_TOPCKGEN) -#define GATE_INFRA3_XTAL(_id, _name, _parent, _shift) \ - GATE_INFRA3(_id, _name, _parent, _shift, CLK_GATE_SETCLR | CLK_PARENT_XTAL) +#define GATE_INFRA3_EXT(_id, _name, _parent, _shift) \ + GATE_INFRA3(_id, _name, _parent, _shift, CLK_GATE_SETCLR | CLK_PARENT_EXT) /* INFRA GATE */ static const struct mtk_gate infracfg_mtk_gates[] = { @@ -751,21 +759,18 @@ static const struct mtk_gate infracfg_mtk_gates[] = { GATE_INFRA3_TOP(CLK_INFRA_USB_SYS, "infra_usb_sys", CLK_TOP_USB_SYS_SEL, 4), GATE_INFRA3_TOP(CLK_INFRA_USB_SYS_CK_P1, "infra_usb_sys_ck_p1", CLK_TOP_USB_SYS_P1_SEL, 5), - GATE_INFRA3_XTAL(CLK_INFRA_USB_REF, "infra_usb_ref", CLK_XTAL, 6), - GATE_INFRA3_XTAL(CLK_INFRA_USB_CK_P1, "infra_usb_ck_p1", CLK_XTAL, - 7), + GATE_INFRA3_EXT(CLK_INFRA_USB_REF, "infra_usb_ref", CLK_PAD_CLK40M, 6), + GATE_INFRA3_EXT(CLK_INFRA_USB_CK_P1, "infra_usb_ck_p1", CLK_PAD_CLK40M, 7), GATE_INFRA3_TOP(CLK_INFRA_USB_FRMCNT, "infra_usb_frmcnt", CLK_TOP_USB_FRMCNT_SEL, 8), GATE_INFRA3_TOP(CLK_INFRA_USB_FRMCNT_CK_P1, "infra_usb_frmcnt_ck_p1", CLK_TOP_USB_FRMCNT_P1_SEL, 9), - GATE_INFRA3_XTAL(CLK_INFRA_USB_PIPE, "infra_usb_pipe", CLK_XTAL, - 10), - GATE_INFRA3_XTAL(CLK_INFRA_USB_PIPE_CK_P1, "infra_usb_pipe_ck_p1", - CLK_XTAL, 11), - GATE_INFRA3_XTAL(CLK_INFRA_USB_UTMI, "infra_usb_utmi", CLK_XTAL, - 12), - GATE_INFRA3_XTAL(CLK_INFRA_USB_UTMI_CK_P1, "infra_usb_utmi_ck_p1", - CLK_XTAL, 13), + GATE_INFRA3_EXT(CLK_INFRA_USB_PIPE, "infra_usb_pipe", CLK_PAD_CLK40M, 10), + GATE_INFRA3_EXT(CLK_INFRA_USB_PIPE_CK_P1, "infra_usb_pipe_ck_p1", + CLK_PAD_CLK40M, 11), + GATE_INFRA3_EXT(CLK_INFRA_USB_UTMI, "infra_usb_utmi", CLK_PAD_CLK40M, 12), + GATE_INFRA3_EXT(CLK_INFRA_USB_UTMI_CK_P1, "infra_usb_utmi_ck_p1", + CLK_PAD_CLK40M, 13), GATE_INFRA3_TOP(CLK_INFRA_USB_XHCI, "infra_usb_xhci", CLK_TOP_USB_XHCI_SEL, 14), GATE_INFRA3_TOP(CLK_INFRA_USB_XHCI_CK_P1, "infra_usb_xhci_ck_p1", @@ -778,14 +783,14 @@ static const struct mtk_gate infracfg_mtk_gates[] = { CLK_INFRA_PCIE_GFMUX_TL_O_P2_SEL, 22), GATE_INFRA3_INFRA(CLK_INFRA_PCIE_GFMUX_TL_P3, "infra_pcie_gfmux_tl_ck_p3", CLK_INFRA_PCIE_GFMUX_TL_O_P3_SEL, 23), - GATE_INFRA3_XTAL(CLK_INFRA_PCIE_PIPE_P0, "infra_pcie_pipe_ck_p0", - CLK_XTAL, 24), - GATE_INFRA3_XTAL(CLK_INFRA_PCIE_PIPE_P1, "infra_pcie_pipe_ck_p1", - CLK_XTAL, 25), - GATE_INFRA3_XTAL(CLK_INFRA_PCIE_PIPE_P2, "infra_pcie_pipe_ck_p2", - CLK_XTAL, 26), - GATE_INFRA3_XTAL(CLK_INFRA_PCIE_PIPE_P3, "infra_pcie_pipe_ck_p3", - CLK_XTAL, 27), + GATE_INFRA3_EXT(CLK_INFRA_PCIE_PIPE_P0, "infra_pcie_pipe_ck_p0", + CLK_PAD_CLK40M, 24), + GATE_INFRA3_EXT(CLK_INFRA_PCIE_PIPE_P1, "infra_pcie_pipe_ck_p1", + CLK_PAD_CLK40M, 25), + GATE_INFRA3_EXT(CLK_INFRA_PCIE_PIPE_P2, "infra_pcie_pipe_ck_p2", + CLK_PAD_CLK40M, 26), + GATE_INFRA3_EXT(CLK_INFRA_PCIE_PIPE_P3, "infra_pcie_pipe_ck_p3", + CLK_PAD_CLK40M, 27), GATE_INFRA3_TOP(CLK_INFRA_133M_PCIE_CK_P0, "infra_133m_pcie_ck_p0", CLK_TOP_SYSAXI_SEL, 28), GATE_INFRA3_TOP(CLK_INFRA_133M_PCIE_CK_P1, "infra_133m_pcie_ck_p1", @@ -797,14 +802,17 @@ static const struct mtk_gate infracfg_mtk_gates[] = { }; static const struct mtk_clk_tree mt7988_fixed_pll_clk_tree = { + .ext_clk_rates = ext_clock_rates, + .num_ext_clks = ARRAY_SIZE(ext_clock_rates), .fdivs_offs = ARRAY_SIZE(apmixedsys_mtk_plls), .fclks = apmixedsys_mtk_plls, .num_fclks = ARRAY_SIZE(apmixedsys_mtk_plls), .flags = CLK_PARENT_APMIXED, - .xtal_rate = 40 * MHZ, }; static const struct mtk_clk_tree mt7988_topckgen_clk_tree = { + .ext_clk_rates = ext_clock_rates, + .num_ext_clks = ARRAY_SIZE(ext_clock_rates), .fdivs_offs = CLK_TOP_XTAL_D2, .muxes_offs = CLK_TOP_NETSYS_SEL, .fclks = topckgen_mtk_fixed_clks, @@ -814,17 +822,17 @@ static const struct mtk_clk_tree mt7988_topckgen_clk_tree = { .num_fdivs = ARRAY_SIZE(topckgen_mtk_fixed_factors), .num_muxes = ARRAY_SIZE(topckgen_mtk_muxes), .flags = CLK_PARENT_TOPCKGEN, - .xtal_rate = 40 * MHZ, }; static const struct mtk_clk_tree mt7988_infracfg_clk_tree = { + .ext_clk_rates = ext_clock_rates, + .num_ext_clks = ARRAY_SIZE(ext_clock_rates), .muxes_offs = CLK_INFRA_MUX_UART0_SEL, .gates_offs = CLK_INFRA_PCIE_PERI_26M_CK_P0, .muxes = infracfg_mtk_mux, .gates = infracfg_mtk_gates, .num_muxes = ARRAY_SIZE(infracfg_mtk_mux), .num_gates = ARRAY_SIZE(infracfg_mtk_gates), - .xtal_rate = 40 * MHZ, }; static const struct udevice_id mt7988_fixed_pll_compat[] = { -- cgit v1.3.1 From 999c169c354399639d4e10d36c0ab464beeaced5 Mon Sep 17 00:00:00 2001 From: David Lechner Date: Tue, 10 Mar 2026 10:32:22 -0500 Subject: clk: mediatek: mt8183: convert CLK_XTAL to CLK_PAD_CLK26M Replace all uses of CLK_XTAL with CLK_PAD_CLK26M. This avoids declaring the same parent clock two different ways and will eventually let us remove CLK_PARENT_XTAL completely. Reviewed-by: Julien Stephan Link: https://patch.msgid.link/20260310-clk-mtk-parent-cleanup-v1-9-66175ca8f637@baylibre.com Signed-off-by: David Lechner --- drivers/clk/mediatek/clk-mt8183.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/drivers/clk/mediatek/clk-mt8183.c b/drivers/clk/mediatek/clk-mt8183.c index 6158441fb95..7b2d796bc6c 100644 --- a/drivers/clk/mediatek/clk-mt8183.c +++ b/drivers/clk/mediatek/clk-mt8183.c @@ -76,7 +76,7 @@ static const struct mtk_pll_data apmixed_plls[] = { }; #define FIXED_CLK0(_id, _rate) \ - FIXED_CLK(_id, CLK_XTAL, CLK_PARENT_XTAL, _rate) + FIXED_CLK(_id, CLK_PAD_CLK26M, CLK_PARENT_EXT, _rate) #define FIXED_CLK1(_id, _rate) \ FIXED_CLK(_id, CLK_TOP_UNIVPLL, CLK_PARENT_TOPCKGEN, _rate) @@ -605,7 +605,6 @@ static const struct mtk_composite top_muxes[] = { }; static const struct mtk_clk_tree mt8183_clk_tree = { - .xtal_rate = 26 * MHZ, .pll_parent = EXT_PARENT(CLK_PAD_CLK26M), .ext_clk_rates = ext_clock_rates, .num_ext_clks = ARRAY_SIZE(ext_clock_rates), -- cgit v1.3.1 From bd547724395cdb17b16ca96b2d9b260a9ac533f3 Mon Sep 17 00:00:00 2001 From: David Lechner Date: Tue, 10 Mar 2026 10:32:23 -0500 Subject: clk: mediatek: mt8188: convert CLK_XTAL to CLK_PAD_CLK26M Replace all uses of CLK_XTAL with CLK_PAD_CLK26M. This avoids declaring the same parent clock two different ways and will eventually let us remove CLK_PARENT_XTAL completely. Reviewed-by: Julien Stephan Link: https://patch.msgid.link/20260310-clk-mtk-parent-cleanup-v1-10-66175ca8f637@baylibre.com Signed-off-by: David Lechner --- drivers/clk/mediatek/clk-mt8188.c | 9 +-------- 1 file changed, 1 insertion(+), 8 deletions(-) diff --git a/drivers/clk/mediatek/clk-mt8188.c b/drivers/clk/mediatek/clk-mt8188.c index ca5fa8af86e..3e413e111f1 100644 --- a/drivers/clk/mediatek/clk-mt8188.c +++ b/drivers/clk/mediatek/clk-mt8188.c @@ -84,7 +84,6 @@ static const struct mtk_pll_data apmixed_plls[] = { }; static const struct mtk_clk_tree mt8188_apmixedsys_clk_tree = { - .xtal_rate = 26 * MHZ, .pll_parent = EXT_PARENT(CLK_PAD_CLK26M), .ext_clk_rates = ext_clock_rates, .num_ext_clks = ARRAY_SIZE(ext_clock_rates), @@ -93,7 +92,7 @@ static const struct mtk_clk_tree mt8188_apmixedsys_clk_tree = { }; #define FIXED_CLK0(_id, _rate) \ - FIXED_CLK(_id, CLK_XTAL, CLK_PARENT_XTAL, _rate) + FIXED_CLK(_id, CLK_PAD_CLK26M, CLK_PARENT_EXT, _rate) static const struct mtk_fixed_clk top_fixed_clks[] = { FIXED_CLK0(CLK_TOP_ULPOSC1, 260000000), @@ -1408,7 +1407,6 @@ static const struct mtk_gate topckgen_cg_clks[] = { }; static const struct mtk_clk_tree mt8188_topckgen_clk_tree = { - .xtal_rate = 26 * MHZ, .ext_clk_rates = ext_clock_rates, .num_ext_clks = ARRAY_SIZE(ext_clock_rates), .id_offs_map = mt8188_id_top_offs_map, @@ -1620,7 +1618,6 @@ static const struct mtk_gate infracfg_ao_clks[] = { }; static const struct mtk_clk_tree mt8188_infracfg_ao_clk_tree = { - .xtal_rate = 26 * MHZ, .ext_clk_rates = ext_clock_rates, .num_ext_clks = ARRAY_SIZE(ext_clock_rates), }; @@ -1663,7 +1660,6 @@ static const struct mtk_gate pericfg_ao_clks[] = { }; static const struct mtk_clk_tree mt8188_pericfg_ao_clk_tree = { - .xtal_rate = 26 * MHZ, .ext_clk_rates = ext_clock_rates, .num_ext_clks = ARRAY_SIZE(ext_clock_rates), }; @@ -1699,19 +1695,16 @@ static const struct mtk_gate imp_iic_wrap_en_clks[] = { }; const struct mtk_clk_tree mt8188_imp_iic_wrap_c_clk_tree = { - .xtal_rate = 26 * MHZ, .ext_clk_rates = ext_clock_rates, .num_ext_clks = ARRAY_SIZE(ext_clock_rates), }; const struct mtk_clk_tree mt8188_imp_iic_wrap_w_clk_tree = { - .xtal_rate = 26 * MHZ, .ext_clk_rates = ext_clock_rates, .num_ext_clks = ARRAY_SIZE(ext_clock_rates), }; const struct mtk_clk_tree mt8188_imp_iic_wrap_en_clk_tree = { - .xtal_rate = 26 * MHZ, .ext_clk_rates = ext_clock_rates, .num_ext_clks = ARRAY_SIZE(ext_clock_rates), }; -- cgit v1.3.1 From 7c95a2a95c7e9671fe059dc92012177b16e4d199 Mon Sep 17 00:00:00 2001 From: David Lechner Date: Tue, 10 Mar 2026 10:32:24 -0500 Subject: clk: mediatek: mt8195: convert CLK_XTAL to CLK_PAD_CLK26M Replace all uses of CLK_XTAL with CLK_PAD_CLK26M. This avoids declaring the same parent clock two different ways and will eventually let us remove CLK_PARENT_XTAL completely. Reviewed-by: Julien Stephan Link: https://patch.msgid.link/20260310-clk-mtk-parent-cleanup-v1-11-66175ca8f637@baylibre.com Signed-off-by: David Lechner --- drivers/clk/mediatek/clk-mt8195.c | 5 +---- 1 file changed, 1 insertion(+), 4 deletions(-) diff --git a/drivers/clk/mediatek/clk-mt8195.c b/drivers/clk/mediatek/clk-mt8195.c index 28b2e2f12ac..37cceb5f32b 100644 --- a/drivers/clk/mediatek/clk-mt8195.c +++ b/drivers/clk/mediatek/clk-mt8195.c @@ -96,7 +96,6 @@ static const struct mtk_pll_data apmixed_plls[] = { }; static const struct mtk_clk_tree mt8195_apmixedsys_clk_tree = { - .xtal_rate = 26 * MHZ, .pll_parent = EXT_PARENT(CLK_PAD_CLK26M), .ext_clk_rates = ext_clock_rates, .num_ext_clks = ARRAY_SIZE(ext_clock_rates), @@ -105,7 +104,7 @@ static const struct mtk_clk_tree mt8195_apmixedsys_clk_tree = { }; #define FIXED_CLK0(_id, _rate) \ - FIXED_CLK(_id, CLK_XTAL, CLK_PARENT_XTAL, _rate) + FIXED_CLK(_id, CLK_PAD_CLK26M, CLK_PARENT_EXT, _rate) static const struct mtk_fixed_clk top_fixed_clks[] = { FIXED_CLK0(CLK_TOP_IN_DGI, 165000000), @@ -1409,7 +1408,6 @@ static const int mt8195_id_top_offs_map[] = { }; static const struct mtk_clk_tree mt8195_topckgen_clk_tree = { - .xtal_rate = 26 * MHZ, .ext_clk_rates = ext_clock_rates, .num_ext_clks = ARRAY_SIZE(ext_clock_rates), .id_offs_map = mt8195_id_top_offs_map, @@ -1597,7 +1595,6 @@ static const struct mtk_gate infra_ao_clks[] = { }; static const struct mtk_clk_tree mt8195_infracfg_ao_clk_tree = { - .xtal_rate = 26 * MHZ, .ext_clk_rates = ext_clock_rates, .num_ext_clks = ARRAY_SIZE(ext_clock_rates), }; -- cgit v1.3.1 From c15c522fa3c8c4472b9524749a999584435eb99e Mon Sep 17 00:00:00 2001 From: David Lechner Date: Tue, 10 Mar 2026 10:32:25 -0500 Subject: clk: mediatek: mt8365: convert CLK_XTAL to CLK_PAD_CLK26M Replace all uses of CLK_XTAL with CLK_PAD_CLK26M. This avoids declaring the same parent clock two different ways and will eventually let us remove CLK_PARENT_XTAL completely. Reviewed-by: Julien Stephan Link: https://patch.msgid.link/20260310-clk-mtk-parent-cleanup-v1-12-66175ca8f637@baylibre.com Signed-off-by: David Lechner --- drivers/clk/mediatek/clk-mt8365.c | 11 ++++------- 1 file changed, 4 insertions(+), 7 deletions(-) diff --git a/drivers/clk/mediatek/clk-mt8365.c b/drivers/clk/mediatek/clk-mt8365.c index a87ac2ad922..eb94b86622c 100644 --- a/drivers/clk/mediatek/clk-mt8365.c +++ b/drivers/clk/mediatek/clk-mt8365.c @@ -74,7 +74,6 @@ static const struct mtk_pll_data apmixed_plls[] = { }; static const struct mtk_clk_tree mt8365_apmixed_tree = { - .xtal_rate = 26 * MHZ, .pll_parent = EXT_PARENT(CLK_PAD_CLK26M), .ext_clk_rates = ext_clock_rates, .num_ext_clks = ARRAY_SIZE(ext_clock_rates), @@ -85,7 +84,7 @@ static const struct mtk_clk_tree mt8365_apmixed_tree = { /* topckgen */ #define FIXED_CLK0(_id, _rate) \ - FIXED_CLK(_id, CLK_XTAL, CLK_PARENT_XTAL, _rate) + FIXED_CLK(_id, CLK_PAD_CLK26M, CLK_PARENT_EXT, _rate) #define FIXED_CLK1(_id, _rate) \ FIXED_CLK(_id, CLK_TOP_CLK_NULL, CLK_PARENT_TOPCKGEN, _rate) @@ -105,7 +104,7 @@ static const struct mtk_fixed_clk top_fixed_clks[] = { FACTOR(_id, _parent, _mult, _div, CLK_PARENT_TOPCKGEN) #define PLL_FACTOR2(_id, _name, _parent, _mult, _div) \ - FACTOR(_id, _parent, _mult, _div, CLK_PARENT_XTAL) + FACTOR(_id, _parent, _mult, _div, CLK_PARENT_EXT) static const struct mtk_fixed_factor top_divs[] = { PLL_FACTOR(CLK_TOP_MFGPLL, "mfgpll_ck", CLK_APMIXED_MFGPLL, 1, 1), @@ -155,7 +154,7 @@ static const struct mtk_fixed_factor top_divs[] = { PLL_FACTOR1(CLK_TOP_APLL2_D2, "apll2_d2", CLK_TOP_APLL2, 1, 2), PLL_FACTOR1(CLK_TOP_APLL2_D4, "apll2_d4", CLK_TOP_APLL2, 1, 4), PLL_FACTOR1(CLK_TOP_APLL2_D8, "apll2_d8", CLK_TOP_APLL2, 1, 8), - PLL_FACTOR2(CLK_TOP_SYS_26M_D2, "sys_26m_d2", CLK_XTAL, 1, 2), + PLL_FACTOR2(CLK_TOP_SYS_26M_D2, "sys_26m_d2", CLK_PAD_CLK26M, 1, 2), PLL_FACTOR(CLK_TOP_MSDCPLL, "msdcpll_ck", CLK_APMIXED_MSDCPLL, 1, 1), PLL_FACTOR(CLK_TOP_MSDCPLL_D2, "msdcpll_d2", CLK_APMIXED_MSDCPLL, 1, 2), PLL_FACTOR(CLK_TOP_DSPPLL, "dsppll_ck", CLK_APMIXED_DSPPLL, 1, 1), @@ -163,7 +162,7 @@ static const struct mtk_fixed_factor top_divs[] = { PLL_FACTOR(CLK_TOP_DSPPLL_D4, "dsppll_d4", CLK_APMIXED_DSPPLL, 1, 4), PLL_FACTOR(CLK_TOP_DSPPLL_D8, "dsppll_d8", CLK_APMIXED_DSPPLL, 1, 8), PLL_FACTOR(CLK_TOP_APUPLL, "apupll_ck", CLK_APMIXED_APUPLL, 1, 1), - PLL_FACTOR2(CLK_TOP_CLK26M_D52, "clk26m_d52", CLK_XTAL, 1, 52), + PLL_FACTOR2(CLK_TOP_CLK26M_D52, "clk26m_d52", CLK_PAD_CLK26M, 1, 52), }; static const struct mtk_parent axi_parents[] = { @@ -583,7 +582,6 @@ static const struct mtk_gate top_clk_gates[] = { }; static const struct mtk_clk_tree mt8365_topckgen_tree = { - .xtal_rate = 26 * MHZ, .ext_clk_rates = ext_clock_rates, .num_ext_clks = ARRAY_SIZE(ext_clock_rates), .fdivs_offs = CLK_TOP_MFGPLL, @@ -755,7 +753,6 @@ static const struct mtk_gate ifr_clks[] = { }; static const struct mtk_clk_tree mt8365_infracfg_tree = { - .xtal_rate = 26 * MHZ, .ext_clk_rates = ext_clock_rates, .num_ext_clks = ARRAY_SIZE(ext_clock_rates), }; -- cgit v1.3.1 From 93a3f1677b63843a5e9a7b131cb5bda6979779f3 Mon Sep 17 00:00:00 2001 From: David Lechner Date: Tue, 10 Mar 2026 10:32:26 -0500 Subject: clk: mediatek: mt8512: convert CLK_XTAL to CLK_PAD_CLK26M Replace all uses of CLK_XTAL with CLK_PAD_CLK26M. This avoids declaring the same parent clock two different ways and will eventually let us remove CLK_PARENT_XTAL completely. Reviewed-by: Julien Stephan Link: https://patch.msgid.link/20260310-clk-mtk-parent-cleanup-v1-13-66175ca8f637@baylibre.com Signed-off-by: David Lechner --- drivers/clk/mediatek/clk-mt8512.c | 9 ++++----- 1 file changed, 4 insertions(+), 5 deletions(-) diff --git a/drivers/clk/mediatek/clk-mt8512.c b/drivers/clk/mediatek/clk-mt8512.c index f7d41f4cfdb..d6e58be8e22 100644 --- a/drivers/clk/mediatek/clk-mt8512.c +++ b/drivers/clk/mediatek/clk-mt8512.c @@ -68,7 +68,7 @@ static const struct mtk_pll_data apmixed_plls[] = { /* topckgen */ #define FIXED_CLK0(_id, _rate) \ - FIXED_CLK(_id, CLK_XTAL, CLK_PARENT_XTAL, _rate) + FIXED_CLK(_id, CLK_PAD_CLK26M, CLK_PARENT_EXT, _rate) #define FACTOR0(_id, _parent, _mult, _div) \ FACTOR(_id, _parent, _mult, _div, CLK_PARENT_APMIXED) @@ -77,7 +77,7 @@ static const struct mtk_pll_data apmixed_plls[] = { FACTOR(_id, _parent, _mult, _div, CLK_PARENT_TOPCKGEN) #define FACTOR2(_id, _parent, _mult, _div) \ - FACTOR(_id, _parent, _mult, _div, CLK_PARENT_XTAL) + FACTOR(_id, _parent, _mult, _div, CLK_PARENT_EXT) static const struct mtk_fixed_clk top_fixed_clks[] = { FIXED_CLK0(CLK_TOP_CLK_NULL, 26000000), @@ -130,8 +130,8 @@ static const struct mtk_fixed_factor top_fixed_divs[] = { FACTOR0(CLK_TOP_APLL2_D4, CLK_APMIXED_APLL2, 1, 4), FACTOR0(CLK_TOP_APLL2_D8, CLK_APMIXED_APLL2, 1, 8), FACTOR0(CLK_TOP_APLL2_D16, CLK_APMIXED_APLL2, 1, 16), - FACTOR2(CLK_TOP_CLK26M, CLK_XTAL, 1, 1), - FACTOR2(CLK_TOP_SYS_26M_D2, CLK_XTAL, 1, 2), + FACTOR2(CLK_TOP_CLK26M, CLK_PAD_CLK26M, 1, 1), + FACTOR2(CLK_TOP_SYS_26M_D2, CLK_PAD_CLK26M, 1, 2), FACTOR0(CLK_TOP_MSDCPLL, CLK_APMIXED_MSDCPLL, 1, 1), FACTOR0(CLK_TOP_MSDCPLL_D2, CLK_APMIXED_MSDCPLL, 1, 2), FACTOR0(CLK_TOP_DSPPLL, CLK_APMIXED_DSPPLL, 1, 1), @@ -793,7 +793,6 @@ static const struct mtk_gate infra_clks[] = { }; static const struct mtk_clk_tree mt8512_clk_tree = { - .xtal_rate = 26 * MHZ, .pll_parent = EXT_PARENT(CLK_PAD_CLK26M), .ext_clk_rates = ext_clock_rates, .num_ext_clks = ARRAY_SIZE(ext_clock_rates), -- cgit v1.3.1 From ecea053c46db32a385daa0ecb2794b1fe1edaab8 Mon Sep 17 00:00:00 2001 From: David Lechner Date: Tue, 10 Mar 2026 10:32:27 -0500 Subject: clk: mediatek: mt8516: convert CLK_XTAL to CLK_PAD_CLK26M Replace all uses of CLK_XTAL with CLK_PAD_CLK26M. This avoids declaring the same parent clock two different ways and will eventually let us remove CLK_PARENT_XTAL completely. Reviewed-by: Julien Stephan Link: https://patch.msgid.link/20260310-clk-mtk-parent-cleanup-v1-14-66175ca8f637@baylibre.com Signed-off-by: David Lechner --- drivers/clk/mediatek/clk-mt8516.c | 9 ++++----- 1 file changed, 4 insertions(+), 5 deletions(-) diff --git a/drivers/clk/mediatek/clk-mt8516.c b/drivers/clk/mediatek/clk-mt8516.c index 74966051b1c..1070dd1551b 100644 --- a/drivers/clk/mediatek/clk-mt8516.c +++ b/drivers/clk/mediatek/clk-mt8516.c @@ -58,7 +58,7 @@ static const struct mtk_pll_data apmixed_plls[] = { /* topckgen */ #define FIXED_CLK0(_id, _rate) \ - FIXED_CLK(_id, CLK_XTAL, CLK_PARENT_XTAL, _rate) + FIXED_CLK(_id, CLK_PAD_CLK26M, CLK_PARENT_EXT, _rate) #define FIXED_CLK1(_id, _parent, _rate) \ FIXED_CLK(_id, _parent, CLK_PARENT_TOPCKGEN, _rate) @@ -70,7 +70,7 @@ static const struct mtk_pll_data apmixed_plls[] = { FACTOR(_id, _parent, _mult, _div, CLK_PARENT_TOPCKGEN) #define FACTOR2(_id, _parent, _mult, _div) \ - FACTOR(_id, _parent, _mult, _div, CLK_PARENT_XTAL) + FACTOR(_id, _parent, _mult, _div, CLK_PARENT_EXT) static const struct mtk_fixed_clk top_fixed_clks[] = { FIXED_CLK0(CLK_TOP_CLK_NULL, 26000000), @@ -117,8 +117,8 @@ static const struct mtk_fixed_factor top_fixed_divs[] = { FACTOR1(CLK_TOP_APLL2_D2, CLK_TOP_APLL2, 1, 2), FACTOR1(CLK_TOP_APLL2_D4, CLK_TOP_RG_APLL2_D2_EN, 1, 2), FACTOR1(CLK_TOP_APLL2_D8, CLK_TOP_RG_APLL2_D4_EN, 1, 2), - FACTOR2(CLK_TOP_CLK26M, CLK_XTAL, 1, 1), - FACTOR2(CLK_TOP_CLK26M_D2, CLK_XTAL, 1, 2), + FACTOR2(CLK_TOP_CLK26M, CLK_PAD_CLK26M, 1, 1), + FACTOR2(CLK_TOP_CLK26M_D2, CLK_PAD_CLK26M, 1, 2), FACTOR1(CLK_TOP_AHB_INFRA_D2, CLK_TOP_AHB_INFRA_SEL, 1, 2), FACTOR1(CLK_TOP_NFI1X, CLK_TOP_NFI2X_PAD_SEL, 1, 2), FACTOR1(CLK_TOP_ETH_D2, CLK_TOP_ETH_SEL, 1, 2), @@ -745,7 +745,6 @@ static const struct mtk_gate top_clks[] = { }; static const struct mtk_clk_tree mt8516_clk_tree = { - .xtal_rate = 26 * MHZ, .pll_parent = EXT_PARENT(CLK_PAD_CLK26M), .ext_clk_rates = ext_clock_rates, .num_ext_clks = ARRAY_SIZE(ext_clock_rates), -- cgit v1.3.1 From a3ff5a9586096de88eb4bd7caf259ac4c183f4c7 Mon Sep 17 00:00:00 2001 From: David Lechner Date: Tue, 10 Mar 2026 10:32:28 -0500 Subject: clk: mediatek: mt8518: convert CLK_XTAL to CLK_PAD_CLK26M Replace all uses of CLK_XTAL with CLK_PAD_CLK26M. This avoids declaring the same parent clock two different ways and will eventually let us remove CLK_PARENT_XTAL completely. Reviewed-by: Julien Stephan Link: https://patch.msgid.link/20260310-clk-mtk-parent-cleanup-v1-15-66175ca8f637@baylibre.com Signed-off-by: David Lechner --- drivers/clk/mediatek/clk-mt8518.c | 17 ++++++++--------- 1 file changed, 8 insertions(+), 9 deletions(-) diff --git a/drivers/clk/mediatek/clk-mt8518.c b/drivers/clk/mediatek/clk-mt8518.c index 85cbb35446b..2b213e720a0 100644 --- a/drivers/clk/mediatek/clk-mt8518.c +++ b/drivers/clk/mediatek/clk-mt8518.c @@ -60,7 +60,7 @@ static const struct mtk_pll_data apmixed_plls[] = { /* topckgen */ #define FIXED_CLK0(_id, _rate) \ - FIXED_CLK(_id, CLK_XTAL, CLK_PARENT_XTAL, _rate) + FIXED_CLK(_id, CLK_PAD_CLK26M, CLK_PARENT_EXT, _rate) #define FIXED_CLK1(_id, _rate) \ FIXED_CLK(_id, CLK_TOP_CLK_NULL, CLK_PARENT_TOPCKGEN, _rate) @@ -72,7 +72,7 @@ static const struct mtk_pll_data apmixed_plls[] = { FACTOR(_id, _parent, _mult, _div, CLK_PARENT_TOPCKGEN) #define FACTOR2(_id, _parent, _mult, _div) \ - FACTOR(_id, _parent, _mult, _div, CLK_PARENT_XTAL) + FACTOR(_id, _parent, _mult, _div, CLK_PARENT_EXT) static const struct mtk_fixed_clk top_fixed_clks[] = { FIXED_CLK0(CLK_TOP_CLK_NULL, 26000000), @@ -82,7 +82,7 @@ static const struct mtk_fixed_clk top_fixed_clks[] = { }; static const struct mtk_fixed_factor top_fixed_divs[] = { - FACTOR2(CLK_TOP_DMPLL, CLK_XTAL, 1, 1), + FACTOR2(CLK_TOP_DMPLL, CLK_PAD_CLK26M, 1, 1), FACTOR0(CLK_TOP_MAINPLL_D4, CLK_APMIXED_MAINPLL, 1, 4), FACTOR0(CLK_TOP_MAINPLL_D8, CLK_APMIXED_MAINPLL, 1, 8), FACTOR0(CLK_TOP_MAINPLL_D16, CLK_APMIXED_MAINPLL, 1, 16), @@ -117,11 +117,11 @@ static const struct mtk_fixed_factor top_fixed_divs[] = { FACTOR1(CLK_TOP_APLL2_D3, CLK_TOP_APLL2, 1, 3), FACTOR1(CLK_TOP_APLL2_D4, CLK_TOP_APLL2, 1, 4), FACTOR1(CLK_TOP_APLL2_D8, CLK_TOP_APLL2, 1, 8), - FACTOR2(CLK_TOP_CLK26M, CLK_XTAL, 1, 1), - FACTOR2(CLK_TOP_CLK26M_D2, CLK_XTAL, 1, 2), - FACTOR2(CLK_TOP_CLK26M_D4, CLK_XTAL, 1, 4), - FACTOR2(CLK_TOP_CLK26M_D8, CLK_XTAL, 1, 8), - FACTOR2(CLK_TOP_CLK26M_D793, CLK_XTAL, 1, 793), + FACTOR2(CLK_TOP_CLK26M, CLK_PAD_CLK26M, 1, 1), + FACTOR2(CLK_TOP_CLK26M_D2, CLK_PAD_CLK26M, 1, 2), + FACTOR2(CLK_TOP_CLK26M_D4, CLK_PAD_CLK26M, 1, 4), + FACTOR2(CLK_TOP_CLK26M_D8, CLK_PAD_CLK26M, 1, 8), + FACTOR2(CLK_TOP_CLK26M_D793, CLK_PAD_CLK26M, 1, 793), FACTOR0(CLK_TOP_TVDPLL, CLK_APMIXED_TVDPLL, 1, 1), FACTOR1(CLK_TOP_TVDPLL_D2, CLK_TOP_TVDPLL, 1, 2), FACTOR1(CLK_TOP_TVDPLL_D4, CLK_TOP_TVDPLL, 1, 4), @@ -1501,7 +1501,6 @@ static const struct mtk_gate top_clks[] = { }; static const struct mtk_clk_tree mt8518_clk_tree = { - .xtal_rate = 26 * MHZ, .pll_parent = EXT_PARENT(CLK_PAD_CLK26M), .ext_clk_rates = ext_clock_rates, .num_ext_clks = ARRAY_SIZE(ext_clock_rates), -- cgit v1.3.1 From f2ee4a493475da2e0015b2f200ed9640d71e04be Mon Sep 17 00:00:00 2001 From: David Lechner Date: Tue, 10 Mar 2026 10:32:29 -0500 Subject: clk: mediatek: remove CLK_PARENT_XTAL Remove the CLK_PARENT_XTAL flag and related code. These have no more users. Reviewed-by: Julien Stephan Link: https://patch.msgid.link/20260310-clk-mtk-parent-cleanup-v1-16-66175ca8f637@baylibre.com Signed-off-by: David Lechner --- drivers/clk/mediatek/clk-mtk.c | 11 ----------- drivers/clk/mediatek/clk-mtk.h | 9 +++------ 2 files changed, 3 insertions(+), 17 deletions(-) diff --git a/drivers/clk/mediatek/clk-mtk.c b/drivers/clk/mediatek/clk-mtk.c index 0b6eb0dbc04..3557aeac3d5 100644 --- a/drivers/clk/mediatek/clk-mtk.c +++ b/drivers/clk/mediatek/clk-mtk.c @@ -241,8 +241,6 @@ static ulong mtk_find_parent_rate(struct mtk_clk_priv *priv, struct clk *clk, parent_dev = clk->dev; break; - case CLK_PARENT_XTAL: - return priv->tree->xtal_rate; case CLK_PARENT_EXT: return mtk_ext_clock_get_rate(priv->tree, parent); default: @@ -352,9 +350,6 @@ static void mtk_clk_print_parent(const char *prefix, int parent, u32 flags) case CLK_PARENT_INFRASYS: parent_type_str = "infrasys"; break; - case CLK_PARENT_XTAL: - parent_type_str = "xtal"; - break; case CLK_PARENT_EXT: parent_type_str = "ext"; break; @@ -1104,12 +1099,6 @@ static ulong mtk_clk_gate_get_rate(struct clk *clk) parent->driver != DM_DRIVER_GET(mtk_clk_topckgen)) { priv = dev_get_priv(parent); parent = priv->parent; - /* - * Assume xtal_rate to be declared if some gates have - * XTAL as parent - */ - } else if (gate->flags & CLK_PARENT_XTAL) { - return priv->tree->xtal_rate; } else if (gate->flags & CLK_PARENT_EXT) { return mtk_ext_clock_get_rate(priv->tree, gate->parent); } diff --git a/drivers/clk/mediatek/clk-mtk.h b/drivers/clk/mediatek/clk-mtk.h index 682b4303585..b39a62edc43 100644 --- a/drivers/clk/mediatek/clk-mtk.h +++ b/drivers/clk/mediatek/clk-mtk.h @@ -8,7 +8,7 @@ #define __DRV_CLK_MTK_H #include -#define CLK_XTAL 0 + #define MHZ (1000 * 1000) /* flags in struct mtk_clk_tree */ @@ -27,9 +27,8 @@ #define CLK_PARENT_APMIXED BIT(4) #define CLK_PARENT_TOPCKGEN BIT(5) #define CLK_PARENT_INFRASYS BIT(6) -#define CLK_PARENT_XTAL BIT(7) -#define CLK_PARENT_EXT BIT(8) -#define CLK_PARENT_MASK GENMASK(8, 4) +#define CLK_PARENT_EXT BIT(7) +#define CLK_PARENT_MASK GENMASK(7, 4) #define ETHSYS_HIFSYS_RST_CTRL_OFS 0x34 @@ -120,7 +119,6 @@ struct mtk_parent { #define APMIXED_PARENT(id) PARENT(id, CLK_PARENT_APMIXED) #define TOP_PARENT(id) PARENT(id, CLK_PARENT_TOPCKGEN) #define INFRA_PARENT(id) PARENT(id, CLK_PARENT_INFRASYS) -#define XTAL_PARENT(id) PARENT(id, CLK_PARENT_XTAL) #define EXT_PARENT(id) PARENT(id, CLK_PARENT_EXT) #define VOID_PARENT PARENT(-1, 0) @@ -233,7 +231,6 @@ struct mtk_gate { /* struct mtk_clk_tree - clock tree */ struct mtk_clk_tree { - unsigned long xtal_rate; const struct mtk_parent pll_parent; /* External fixed clocks - excluded from mapping. */ const ulong *ext_clk_rates; -- cgit v1.3.1 From f82f50caa1d5c1a9e4e2982a05da58416da356d6 Mon Sep 17 00:00:00 2001 From: David Lechner Date: Wed, 11 Mar 2026 09:52:49 -0500 Subject: MAINTAINERS: add new MediaTek custodians Add new MediaTek custodians and the new MediaTek custodian's git repository to the MAINTAINERS file. Julien and I have volunteered to act as custodians for MediaTek since we have been actively working on upstreaming MediaTek support for some some time now. Reviewed-by: Tom Rini Reviewed-by: Julien Stephan Link: https://patch.msgid.link/20260311-mtk-custodians-v1-1-000f9025b54c@baylibre.com Signed-off-by: David Lechner --- MAINTAINERS | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index f924565d1bf..061717c8fe5 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -415,7 +415,10 @@ M: Ryder Lee M: Weijie Gao M: Chunfeng Yun M: Igor Belwon +M: David Lechner +M: Julien Stephan R: GSS_MTK_Uboot_upstream +T: git https://source.denx.de/u-boot/custodians/u-boot-mediatek.git S: Maintained F: arch/arm/dts/mt* F: arch/arm/mach-mediatek/ @@ -1391,7 +1394,10 @@ F: drivers/net/phy/ca_phy.c MIPS MEDIATEK M: Weijie Gao +M: David Lechner +M: Julien Stephan R: GSS_MTK_Uboot_upstream +T: git https://source.denx.de/u-boot/custodians/u-boot-mediatek.git S: Maintained F: arch/mips/mach-mtmips/ F: arch/mips/dts/mt7620.dtsi -- cgit v1.3.1 From 71e736ed6d4ff22130aff7b12b0150e042f64cf8 Mon Sep 17 00:00:00 2001 From: Julien Stephan Date: Thu, 12 Mar 2026 17:19:26 +0100 Subject: pinctrl: mediatek: Add missing bind callback for several SoCs Commit f4df9f53b7a9 ("pinctrl: mediatek: Bind gpio while binding pinctrl") refactored pinctrl-mtk-common.c and the SoC-specific drivers to register the gpiochip during the bind phase instead of probe. As part of this change, each SoC driver must implement a bind callback. The drivers recently added for mt8188, mt8189, mt8195 and mt8365 do not define this callback, which prevents the gpiochip from being registered properly. Add the missing bind callback to these drivers. Signed-off-by: Julien Stephan Link: https://patch.msgid.link/20260312-pinctrl-mtk-bind-gpio-v1-1-21b8968902ed@baylibre.com Signed-off-by: David Lechner --- drivers/pinctrl/mediatek/pinctrl-mt8188.c | 1 + drivers/pinctrl/mediatek/pinctrl-mt8189.c | 1 + drivers/pinctrl/mediatek/pinctrl-mt8195.c | 1 + drivers/pinctrl/mediatek/pinctrl-mt8365.c | 1 + 4 files changed, 4 insertions(+) diff --git a/drivers/pinctrl/mediatek/pinctrl-mt8188.c b/drivers/pinctrl/mediatek/pinctrl-mt8188.c index 386d4d4a922..256053f269f 100644 --- a/drivers/pinctrl/mediatek/pinctrl-mt8188.c +++ b/drivers/pinctrl/mediatek/pinctrl-mt8188.c @@ -1339,6 +1339,7 @@ U_BOOT_DRIVER(mt8188_pinctrl) = { .id = UCLASS_PINCTRL, .of_match = mt8188_pctrl_match, .ops = &mtk_pinctrl_ops, + .bind = mtk_pinctrl_common_bind, .probe = mtk_pinctrl_mt8188_probe, .priv_auto = sizeof(struct mtk_pinctrl_priv), }; diff --git a/drivers/pinctrl/mediatek/pinctrl-mt8189.c b/drivers/pinctrl/mediatek/pinctrl-mt8189.c index b798f3c019b..a64440d8bb3 100644 --- a/drivers/pinctrl/mediatek/pinctrl-mt8189.c +++ b/drivers/pinctrl/mediatek/pinctrl-mt8189.c @@ -1271,6 +1271,7 @@ U_BOOT_DRIVER(mt8189_pinctrl) = { .id = UCLASS_PINCTRL, .of_match = mt8189_pctrl_match, .ops = &mtk_pinctrl_ops, + .bind = mtk_pinctrl_common_bind, .probe = mtk_pinctrl_mt8189_probe, .priv_auto = sizeof(struct mtk_pinctrl_priv), }; diff --git a/drivers/pinctrl/mediatek/pinctrl-mt8195.c b/drivers/pinctrl/mediatek/pinctrl-mt8195.c index 031ad5f6a8a..db619766a99 100644 --- a/drivers/pinctrl/mediatek/pinctrl-mt8195.c +++ b/drivers/pinctrl/mediatek/pinctrl-mt8195.c @@ -1074,6 +1074,7 @@ U_BOOT_DRIVER(mt8195_pinctrl) = { .id = UCLASS_PINCTRL, .of_match = mt8195_pctrl_match, .ops = &mtk_pinctrl_ops, + .bind = mtk_pinctrl_common_bind, .probe = mtk_pinctrl_mt8195_probe, .priv_auto = sizeof(struct mtk_pinctrl_priv), }; diff --git a/drivers/pinctrl/mediatek/pinctrl-mt8365.c b/drivers/pinctrl/mediatek/pinctrl-mt8365.c index a6985e48858..0ce99b92a9f 100644 --- a/drivers/pinctrl/mediatek/pinctrl-mt8365.c +++ b/drivers/pinctrl/mediatek/pinctrl-mt8365.c @@ -596,6 +596,7 @@ U_BOOT_DRIVER(mt8365_pinctrl) = { .id = UCLASS_PINCTRL, .of_match = mt8365_pctrl_match, .ops = &mtk_pinctrl_ops, + .bind = mtk_pinctrl_common_bind, .probe = mtk_pinctrl_mt8365_probe, .priv_auto = sizeof(struct mtk_pinctrl_priv), }; -- cgit v1.3.1 From 730958e9b01801fb2be194c1281e886236f4d08d Mon Sep 17 00:00:00 2001 From: David Lechner Date: Fri, 13 Mar 2026 09:46:04 -0500 Subject: clk: mediatek: mt7623: fix pericfg priv_auto size Change the pericfg priv_auto size to mtk_clk_priv. The driver is registered using mtk_common_clk_infrasys_init() which expect that struct. The old value of struct mtk_cg_priv was larger, so there was no issue out of bounds access. Also replace tab with space to be consistent with the surrounding code. Reported-by: Julien Stephan Closes: https://lore.kernel.org/u-boot/CAEHHSvYMiCZ4jAXp6jEhg6AhZ5Dv3_Ak-8H1mT7S2FPD3_X7dw@mail.gmail.com/ Reviewed-by: Julien Stephan Link: https://patch.msgid.link/20260313-clk-mtk-fix-priv-auto-size-v1-1-bc649e1b301a@baylibre.com Signed-off-by: David Lechner --- drivers/clk/mediatek/clk-mt7623.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/clk/mediatek/clk-mt7623.c b/drivers/clk/mediatek/clk-mt7623.c index 41bd91a8e05..0a302b405e2 100644 --- a/drivers/clk/mediatek/clk-mt7623.c +++ b/drivers/clk/mediatek/clk-mt7623.c @@ -1194,7 +1194,7 @@ U_BOOT_DRIVER(mtk_clk_pericfg) = { .id = UCLASS_CLK, .of_match = mt7623_pericfg_compat, .probe = mt7623_pericfg_probe, - .priv_auto = sizeof(struct mtk_cg_priv), + .priv_auto = sizeof(struct mtk_clk_priv), .ops = &mtk_clk_infrasys_ops, .flags = DM_FLAG_PRE_RELOC, }; -- cgit v1.3.1