From 33e63831080d28d099abec5ef40d5f8ae83ec7c0 Mon Sep 17 00:00:00 2001 From: Hiago De Franco Date: Thu, 30 Apr 2026 16:13:06 -0300 Subject: doc: sophgo: licheerv_nano: fix incorrect step numbering Steps 2 and 3 are incorrectly numbered. Fix them. Signed-off-by: Hiago De Franco --- doc/board/sophgo/licheerv_nano.rst | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/doc/board/sophgo/licheerv_nano.rst b/doc/board/sophgo/licheerv_nano.rst index a75c6a37dc5..a3b1171287d 100644 --- a/doc/board/sophgo/licheerv_nano.rst +++ b/doc/board/sophgo/licheerv_nano.rst @@ -43,9 +43,9 @@ To run u-boot.bin on top of FSBL, follow these steps: FSBL, OpenSBI, and U-Boot. Note that you will have to use the file cv181x.bin as the FSBL. -2. Place the generated fip.bin file into the FAT partition of the SD card. +4. Place the generated fip.bin file into the FAT partition of the SD card. -3. Insert the SD card into the board and power it on. +5. Insert the SD card into the board and power it on. The board will automatically execute the FSBL from the fip.bin file. Subsequently, it will transition to OpenSBI, and finally, OpenSBI will invoke -- cgit v1.3.1 From 40ea5423f9aaa5cc9c8364f96542a72e830113ce Mon Sep 17 00:00:00 2001 From: Hiago De Franco Date: Thu, 30 Apr 2026 16:35:18 -0300 Subject: riscv: dts: cv18xx: fix spi node name Fix warning: arch/riscv/dts/cv18xx.dtsi:208.26-216.5: Warning (spi_bus_bridge): /soc/spi-nor@10000000: node name for SPI buses should be 'spi' Signed-off-by: Hiago De Franco --- arch/riscv/dts/cv18xx.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/riscv/dts/cv18xx.dtsi b/arch/riscv/dts/cv18xx.dtsi index 6fac247e7ac..8530527aa39 100644 --- a/arch/riscv/dts/cv18xx.dtsi +++ b/arch/riscv/dts/cv18xx.dtsi @@ -205,7 +205,7 @@ status = "disabled"; }; - spif: spi-nor@10000000 { + spif: spi@10000000 { compatible = "sophgo,cv1800b-spif"; reg = <0x10000000 0x10000000>; #address-cells = <1>; -- cgit v1.3.1 From 13b990d05fa40cf4e8b348bef602eb2f521b6c2b Mon Sep 17 00:00:00 2001 From: Hal Feng Date: Mon, 4 May 2026 21:41:34 +0800 Subject: configs: visionfive2: Add VisionFive 2 Lite eMMC DT to OF_LIST So the VisionFive 2 Lite eMMC DT will be built and merged into FIT. Reviewed-by: E Shattow Signed-off-by: Hal Feng --- configs/starfive_visionfive2_defconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/configs/starfive_visionfive2_defconfig b/configs/starfive_visionfive2_defconfig index 23f903a6df4..6fd43544a0c 100644 --- a/configs/starfive_visionfive2_defconfig +++ b/configs/starfive_visionfive2_defconfig @@ -80,7 +80,7 @@ CONFIG_WGET_HTTPS=y CONFIG_CMD_BOOTSTAGE=y CONFIG_OF_BOARD=y CONFIG_DEVICE_TREE_INCLUDES="starfive-visionfive2-u-boot.dtsi" -CONFIG_OF_LIST="starfive/jh7110-deepcomputing-fml13v01 starfive/jh7110-milkv-mars starfive/jh7110-milkv-marscm-emmc starfive/jh7110-milkv-marscm-lite starfive/jh7110-orangepi-rv starfive/jh7110-pine64-star64 starfive/jh7110-starfive-visionfive-2-v1.2a starfive/jh7110-starfive-visionfive-2-v1.3b starfive/jh7110-starfive-visionfive-2-lite" +CONFIG_OF_LIST="starfive/jh7110-deepcomputing-fml13v01 starfive/jh7110-milkv-mars starfive/jh7110-milkv-marscm-emmc starfive/jh7110-milkv-marscm-lite starfive/jh7110-orangepi-rv starfive/jh7110-pine64-star64 starfive/jh7110-starfive-visionfive-2-v1.2a starfive/jh7110-starfive-visionfive-2-v1.3b starfive/jh7110-starfive-visionfive-2-lite starfive/jh7110-starfive-visionfive-2-lite-emmc" CONFIG_MULTI_DTB_FIT=y CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_SPI_FLASH=y -- cgit v1.3.1 From be256bd560dc3bd19ee42b821d2590fd25f92179 Mon Sep 17 00:00:00 2001 From: Hal Feng Date: Mon, 4 May 2026 21:41:35 +0800 Subject: board: starfive: visionfive2: Support VisionFive 2 Lite eMMC Add emmc detection to VisionFive 2 Lite DT selection and fdtfile environment variable setting. Reviewed-by: E Shattow Signed-off-by: Hal Feng --- board/starfive/visionfive2/spl.c | 7 ++++++- board/starfive/visionfive2/starfive_visionfive2.c | 6 +++++- 2 files changed, 11 insertions(+), 2 deletions(-) diff --git a/board/starfive/visionfive2/spl.c b/board/starfive/visionfive2/spl.c index e231467f2a1..1b4d623d002 100644 --- a/board/starfive/visionfive2/spl.c +++ b/board/starfive/visionfive2/spl.c @@ -144,7 +144,12 @@ int board_fit_config_name_match(const char *name) !strncmp(get_product_id_from_eeprom(), "VF7110B", 7)) { return 0; } else if (!strcmp(name, "starfive/jh7110-starfive-visionfive-2-lite") && - !strncmp(get_product_id_from_eeprom(), "VF7110SL", 8)) { + !strncmp(get_product_id_from_eeprom(), "VF7110SL", 8) && + !get_mmc_size_from_eeprom()) { + return 0; + } else if (!strcmp(name, "starfive/jh7110-starfive-visionfive-2-lite-emmc") && + !strncmp(get_product_id_from_eeprom(), "VF7110SL", 8) && + get_mmc_size_from_eeprom()) { return 0; } diff --git a/board/starfive/visionfive2/starfive_visionfive2.c b/board/starfive/visionfive2/starfive_visionfive2.c index 1a76f745ec8..97f40715f8f 100644 --- a/board/starfive/visionfive2/starfive_visionfive2.c +++ b/board/starfive/visionfive2/starfive_visionfive2.c @@ -72,7 +72,11 @@ static void set_fdtfile(void) } else if (!strncmp(get_product_id_from_eeprom(), "VF7110B", 7)) { fdtfile = "starfive/jh7110-starfive-visionfive-2-v1.3b.dtb"; } else if (!strncmp(get_product_id_from_eeprom(), "VF7110SL", 8)) { - fdtfile = "starfive/jh7110-starfive-visionfive-2-lite.dtb"; + if (get_mmc_size_from_eeprom()) { + fdtfile = "starfive/jh7110-starfive-visionfive-2-lite-emmc.dtb"; + } else { + fdtfile = "starfive/jh7110-starfive-visionfive-2-lite.dtb"; + } } else { log_err("Unknown product\n"); return; -- cgit v1.3.1 From d8810e1d4f82b8064e4b9e0a52b352670d79ae06 Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Mon, 11 May 2026 10:31:52 +0200 Subject: riscv: Skip riscv_cpu_setup() when CPU driver is disabled Building on commit c64fc632a86a ("riscv: cpu: Use CONFIG_IS_ENABLED(CPU) instead of plain ifdef"), add an early return in riscv_cpu_setup() when CONFIG_CPU is not enabled. This allows platforms to save code space in SPL by disabling CONFIG_SPL_CPU. Without this patch, building U-Boot with CONFIG_CPU=n and CONFIG_EVENT=y is broken: riscv_cpu_setup() is registered as an EVT_DM_POST_INIT_F event spy, and when the CPU uclass is unavailable uclass_find_first_device() returns no device, so the function returns -ENODEV. That in turn makes event_notify_null() in dm_init_and_scan() fail and triggers a boot hang ("initcall initf_dm() failed"). Returning 0 early avoids that failure. The compiler's dead-code elimination combined with --gc-sections removes the unreachable code and all associated static data, achieving significant size reduction without preprocessor guards: spl/u-boot-spl:all -4332 spl/u-boot-spl:rodata -2872 spl/u-boot-spl:text -1460 Signed-off-by: Michal Simek Reviewed-by: Yao Zi --- arch/riscv/cpu/cpu.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/arch/riscv/cpu/cpu.c b/arch/riscv/cpu/cpu.c index bbadd0c9a46..3bec7c7cb6d 100644 --- a/arch/riscv/cpu/cpu.c +++ b/arch/riscv/cpu/cpu.c @@ -638,6 +638,9 @@ int riscv_cpu_setup(void) const char *isa, **exts; struct udevice *dev; + if (!CONFIG_IS_ENABLED(CPU)) + return 0; + uclass_find_first_device(UCLASS_CPU, &dev); if (!dev) { debug("unable to find the RISC-V cpu device\n"); -- cgit v1.3.1 From 0798f12031d0f5101e2dc05433e6d6984a610782 Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Fri, 15 May 2026 14:47:52 +0200 Subject: riscv: Make RISCV_ACLINT visible A platform (like Xilinx Microblaze V) does not have an ACLINT (Advanced Core Local Interruptor) hardware block. Make RISCV_ACLINT and SPL_RISCV_ACLINT Kconfig symbols visible with prompts. Signed-off-by: Michal Simek Reviewed-by: Yao Zi --- arch/riscv/Kconfig | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig index 485067ed266..0865620912c 100644 --- a/arch/riscv/Kconfig +++ b/arch/riscv/Kconfig @@ -378,7 +378,7 @@ config DMA_ADDR_T_64BIT default y if 64BIT config RISCV_ACLINT - bool + bool "RISC-V ACLINT support" depends on RISCV_MMODE select REGMAP select SYSCON @@ -387,7 +387,7 @@ config RISCV_ACLINT associated with software and timer interrupts. config SPL_RISCV_ACLINT - bool + bool "RISC-V ACLINT support in SPL" depends on SPL_RISCV_MMODE select SPL_REGMAP select SPL_SYSCON -- cgit v1.3.1 From 84b48a918103f0b80719b4f8f42abd9a8ea2582a Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Fri, 15 May 2026 14:47:53 +0200 Subject: riscv: Exclude ACLINT for TARGET_XILINX_MBV The Xilinx MicroBlaze V platform does not have an ACLINT (Advanced Core Local Interruptor) hardware block. The timer functionality is provided through a different mechanism. Exclude both RISCV_ACLINT and SPL_RISCV_ACLINT from being implied for TARGET_XILINX_MBV while keeping the default behavior for other generic RISC-V targets that do have ACLINT hardware. spl/u-boot-spl: all -1382 data -360 rodata -200 text -822 Signed-off-by: Michal Simek Reviewed-by: Leo Yu-Chi Liang --- configs/xilinx_mbv32_defconfig | 2 ++ 1 file changed, 2 insertions(+) diff --git a/configs/xilinx_mbv32_defconfig b/configs/xilinx_mbv32_defconfig index 9d0111fe8e5..097d6095df2 100644 --- a/configs/xilinx_mbv32_defconfig +++ b/configs/xilinx_mbv32_defconfig @@ -17,6 +17,8 @@ CONFIG_SYS_CLK_FREQ=100000000 CONFIG_BOOT_SCRIPT_OFFSET=0x0 CONFIG_TARGET_XILINX_MBV=y # CONFIG_RISCV_ISA_F is not set +# CONFIG_RISCV_ACLINT is not set +# CONFIG_SPL_RISCV_ACLINT is not set # CONFIG_SPL_SMP is not set # CONFIG_AVAILABLE_HARTS is not set CONFIG_SPL_OPTIMIZE_INLINING=y -- cgit v1.3.1 From c7c969d7e268b8cd2be0ffa7a815d25453e0fd8d Mon Sep 17 00:00:00 2001 From: Francois Berder Date: Tue, 26 May 2026 10:58:13 +0200 Subject: rng: jh7110: Fix invalid usage of dev_read_addr dev_read_addr returns FDT_ADDR_T_NONE (-1), not NULL, in case of errors. Replace dev_read_addr by dev_read_addr_ptr. Replace error to EINVAL. Signed-off-by: Francois Berder Reviewed-by: Hal Feng --- drivers/rng/jh7110_rng.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/rng/jh7110_rng.c b/drivers/rng/jh7110_rng.c index eb21afe4e7c..d54898c67f6 100644 --- a/drivers/rng/jh7110_rng.c +++ b/drivers/rng/jh7110_rng.c @@ -233,9 +233,9 @@ static int starfive_trng_of_to_plat(struct udevice *dev) { struct starfive_trng_plat *pdata = dev_get_plat(dev); - pdata->base = (void *)dev_read_addr(dev); + pdata->base = dev_read_addr_ptr(dev); if (!pdata->base) - return -ENODEV; + return -EINVAL; pdata->hclk = devm_clk_get(dev, "hclk"); if (IS_ERR(pdata->hclk)) -- cgit v1.3.1 From e1b16d3c0f53c2291b1583e8eee72a0d6581e2dd Mon Sep 17 00:00:00 2001 From: Yao Zi Date: Wed, 24 Jun 2026 04:56:49 +0000 Subject: MAINTAINERS: riscv: Add myself as a reviewer Add myself to help review patches for RISC-V port. Signed-off-by: Yao Zi Reviewed-by: Leo Yu-Chi Liang --- MAINTAINERS | 1 + 1 file changed, 1 insertion(+) diff --git a/MAINTAINERS b/MAINTAINERS index 53034b703df..87cd487c5f3 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -1576,6 +1576,7 @@ F: drivers/mtd/nand/raw/ RISC-V M: Tim Ouyang M: Leo Liang +R: Yao Zi S: Maintained T: git https://git.u-boot-project.org/u-boot/custodians/u-boot-riscv.git F: arch/riscv/ -- cgit v1.3.1 From b3b5b305e2c9f09440bda5fd3edf9e230c54d94f Mon Sep 17 00:00:00 2001 From: Charles Perry Date: Mon, 22 Jun 2026 12:43:07 -0700 Subject: riscv: remove log_debug() in enable_caches() log_debug() cannot be used before log_init() has been called. Remove the log_debug() statement in enable_caches() since it is called before log_init() in initcall_run_r(). This fixes a bug where a RISC-V system which does not have the "zicbom" extension (such as PIC64-HPSC/HX) would get lost in an infinite loop in log_dispatch(). Fixes: 9e859849e2ca ("riscv: cache: Add CBO instructions") Signed-off-by: Charles Perry Reviewed-by: Leo Yu-Chi Liang --- arch/riscv/lib/cache.c | 2 -- 1 file changed, 2 deletions(-) diff --git a/arch/riscv/lib/cache.c b/arch/riscv/lib/cache.c index 31aa30bc7d7..ac5136fa6be 100644 --- a/arch/riscv/lib/cache.c +++ b/arch/riscv/lib/cache.c @@ -149,8 +149,6 @@ __weak int dcache_status(void) __weak void enable_caches(void) { zicbom_block_size = riscv_get_cbom_block_size(); - if (!zicbom_block_size) - log_debug("Zicbom not initialized.\n"); } int __weak pgprot_set_attrs(phys_addr_t addr, size_t size, enum pgprot_attrs perm) -- cgit v1.3.1 From c201051a9cd3a358cb67cbba9b1c5fa717cf1c40 Mon Sep 17 00:00:00 2001 From: Naveen Kumar Chaudhary Date: Sun, 7 Jun 2026 21:06:31 +0530 Subject: serial: sifive: remove busy-loops from getc and putc ops The DM serial framework in __serial_getc() and __serial_putc() already retries when driver ops return -EAGAIN, calling schedule() between attempts to service the watchdog. sifive_serial_getc() and sifive_serial_putc() spin internally on -EAGAIN, which prevents the framework from calling schedule(). This can lead to watchdog timeouts when waiting for RX data or TX FIFO space. Remove the busy-loops and return -EAGAIN directly from the underlying helpers, letting the framework handle retries with proper watchdog servicing. This is consistent with how other DM serial drivers (pl01x, meson, cortina, etc.) implement their ops. Signed-off-by: Naveen Kumar Chaudhary Reviewed-by: Leo Yu-Chi Liang --- drivers/serial/serial_sifive.c | 11 ++--------- 1 file changed, 2 insertions(+), 9 deletions(-) diff --git a/drivers/serial/serial_sifive.c b/drivers/serial/serial_sifive.c index e47828e4d6a..0203e2fc37c 100644 --- a/drivers/serial/serial_sifive.c +++ b/drivers/serial/serial_sifive.c @@ -144,23 +144,16 @@ static int sifive_serial_probe(struct udevice *dev) static int sifive_serial_getc(struct udevice *dev) { - int c; struct sifive_uart_plat *plat = dev_get_plat(dev); - struct uart_sifive *regs = plat->regs; - - while ((c = _sifive_serial_getc(regs)) == -EAGAIN) ; - return c; + return _sifive_serial_getc(plat->regs); } static int sifive_serial_putc(struct udevice *dev, const char ch) { - int rc; struct sifive_uart_plat *plat = dev_get_plat(dev); - while ((rc = _sifive_serial_putc(plat->regs, ch)) == -EAGAIN) ; - - return rc; + return _sifive_serial_putc(plat->regs, ch); } static int sifive_serial_pending(struct udevice *dev, bool input) -- cgit v1.3.1