From 5fa1de058293f4737ae3eeee6683dd87f5542360 Mon Sep 17 00:00:00 2001 From: Julien Stephan Date: Mon, 27 Jul 2026 10:43:45 +0200 Subject: edid: add default EDID_ADDR macro EDID info is most of the time stored at address 0x50, so define a macro for it in the common edid.h header. Also drop the now-duplicate definition from the Rockchip edp_rk3288.h header and rely on the common one. Signed-off-by: Julien Stephan Reviewed-by: Heiko Schocher Link: https://patch.msgid.link/20260727-mt8188-add-ddc-i2c-driver-v2-1-bf1c45fcd588@baylibre.com Signed-off-by: David Lechner --- arch/arm/include/asm/arch-rockchip/edp_rk3288.h | 1 - include/edid.h | 3 +++ 2 files changed, 3 insertions(+), 1 deletion(-) diff --git a/arch/arm/include/asm/arch-rockchip/edp_rk3288.h b/arch/arm/include/asm/arch-rockchip/edp_rk3288.h index edacf102852..2332ae30953 100644 --- a/arch/arm/include/asm/arch-rockchip/edp_rk3288.h +++ b/arch/arm/include/asm/arch-rockchip/edp_rk3288.h @@ -527,7 +527,6 @@ check_member(rk3288_edp, pll_reg_5, 0xa00); #define PLL_LOCK_TIMEOUT 10 #define DP_INIT_TRIES 10 -#define EDID_ADDR 0x50 #define EDID_LENGTH 0x80 #define EDID_HEADER 0x00 #define EDID_EXTENSION_FLAG 0x7e diff --git a/include/edid.h b/include/edid.h index cee7c4c7637..77a5d258311 100644 --- a/include/edid.h +++ b/include/edid.h @@ -14,6 +14,9 @@ #include +/* Default EDID address */ +#define EDID_ADDR 0x50 + /* Size of the EDID data */ #define EDID_SIZE 128 #define EDID_EXT_SIZE 256 -- cgit v1.3.1 From 71142b57cd1afa78117cd5be8baf071392599939 Mon Sep 17 00:00:00 2001 From: Julien Stephan Date: Mon, 27 Jul 2026 10:43:46 +0200 Subject: i2c: mtk_mt8195_i2c_ddc: add new driver Add a new driver for HDMI DDC channel reading for MT8195 based SoCs. The driver is based on the corresponding kernel driver. Signed-off-by: Pavlo Yadvychuk Signed-off-by: Julien Stephan Reviewed-by: Heiko Schocher Link: https://patch.msgid.link/20260727-mt8188-add-ddc-i2c-driver-v2-2-bf1c45fcd588@baylibre.com Signed-off-by: David Lechner --- drivers/i2c/Kconfig | 11 ++ drivers/i2c/Makefile | 1 + drivers/i2c/mtk_mt8195_i2c_ddc.c | 394 +++++++++++++++++++++++++++++++++++++++ 3 files changed, 406 insertions(+) create mode 100644 drivers/i2c/mtk_mt8195_i2c_ddc.c diff --git a/drivers/i2c/Kconfig b/drivers/i2c/Kconfig index 0e8b2408376..0b5225fd3f5 100644 --- a/drivers/i2c/Kconfig +++ b/drivers/i2c/Kconfig @@ -232,6 +232,17 @@ config SYS_I2C_DAVINCI help Say yes here to add support for Davinci and Keystone I2C controller +config SYS_I2C_DDC_MTK + bool "MediaTek HDMI DDC driver" + depends on DM_I2C + depends on CLK + help + This selects the MediaTek Inter-Integrated Circuit (I2C) bus driver + used for HDMI DDC communication. The driver supports MT8188 and + MT8195 compatible SoCs. + If you want to use the MediaTek DDC interface, say Y here. + If unsure, say N. + config SYS_I2C_DW bool "Designware I2C Controller" help diff --git a/drivers/i2c/Makefile b/drivers/i2c/Makefile index 0e3a0f9fb5f..79e6a298808 100644 --- a/drivers/i2c/Makefile +++ b/drivers/i2c/Makefile @@ -18,6 +18,7 @@ obj-$(CONFIG_SYS_I2C_AT91) += at91_i2c.o obj-$(CONFIG_SYS_I2C_CADENCE) += i2c-cdns.o obj-$(CONFIG_SYS_I2C_CA) += i2c-cortina.o obj-$(CONFIG_SYS_I2C_DAVINCI) += davinci_i2c.o +obj-$(CONFIG_SYS_I2C_DDC_MTK) += mtk_mt8195_i2c_ddc.o obj-$(CONFIG_SYS_I2C_DW) += designware_i2c.o obj-$(CONFIG_SYS_I2C_DW_PCI) += designware_i2c_pci.o obj-$(CONFIG_SYS_I2C_FSL) += fsl_i2c.o diff --git a/drivers/i2c/mtk_mt8195_i2c_ddc.c b/drivers/i2c/mtk_mt8195_i2c_ddc.c new file mode 100644 index 00000000000..cbdac6fa5db --- /dev/null +++ b/drivers/i2c/mtk_mt8195_i2c_ddc.c @@ -0,0 +1,394 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) 2021 MediaTek Inc. + * Copyright (c) 2026 BayLibre, SAS + * + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +#define DDC2_CLOCK 572 /* BIM=208M/(v*4) = 90Khz */ +#define DDC2_CLOCK_EDID 832 /* BIM=208M/(v*4) = 62.5Khz */ + +#define SCDC_I2C_SLAVE_ADDRESS 0x54 + +#define HDCP2X_DDCM_STATUS 0xC68 + +#define SCDC_CTRL 0xC18 + +#define CLEAR_FIFO 0x9 + +#define CLOCK_SCL 0xA + +#define ENH_READ_NO_ACK 0x4 + +#define DDC_CMD GENMASK(31, 28) +#define DDC_CMD_SHIFT (28) +#define DDC_CTRL 0xC10 +#define DDC_DATA_OUT GENMASK(23, 16) +#define DDC_DATA_OUT_SHIFT (16) +#define DDC_DELAY_CNT GENMASK(31, 16) +#define DDC_DELAY_CNT_SHIFT (16) +#define DDC_DIN_CNT_SHIFT (16) +#define DDC_I2C_BUS_LOW BIT(11) +#define DDC_I2C_IN_PROG BIT(13) +#define DDC_I2C_NO_ACK BIT(10) +#define DDC_OFFSET_SHIFT (8) +#define DDC_SEGMENT GENMASK(15, 8) +#define DDC_SEGMENT_SHIFT (8) + +#define HPD_DDC_CTRL 0xC08 +#define HPD_DDC_STATUS 0xC60 + +#define SEQ_READ_NO_ACK 0x2 +#define SEQ_WRITE_REQ_ACK 0x7 + +#define SI2C_CTRL 0xCAC +#define SI2C_ADDR_READ (0xF4) +#define SI2C_ADDR_SHIFT (16) +#define SI2C_WDATA GENMASK(15, 8) +#define SI2C_WDATA_SHIFT (8) +#define SI2C_CONFIRM_READ BIT(2) +#define SI2C_RD BIT(1) +#define SI2C_WR BIT(0) + +#define HDCP2X_POL_CTRL 0xC54 +#define HDCP2X_DIS_POLL_EN BIT(16) + +struct mtk_hdmi_ddc { + struct udevice *udev; + struct clk clk; + void __iomem *regs; +}; + +enum sif_bit_t_hdmi { + SIF_8_BIT_HDMI, /* 8 bits data address */ + SIF_16_BIT_HDMI, /* 16 bits data address */ +}; + +static inline unsigned int mtk_ddc_read(struct mtk_hdmi_ddc *ddc, + unsigned int reg) +{ + return readl(ddc->regs + reg); +} + +static inline void mtk_ddc_write(struct mtk_hdmi_ddc *ddc, unsigned int reg, + unsigned int val) +{ + writel(val, ddc->regs + reg); +} + +static inline void mtk_ddc_mask(struct mtk_hdmi_ddc *ddc, unsigned int reg, + unsigned int val, unsigned int mask) +{ + clrsetbits_32(ddc->regs + reg, mask, val); +} + +static void mtk_ddc_disable_hdcp_polling(struct mtk_hdmi_ddc *ddc) +{ + mtk_ddc_mask(ddc, HDCP2X_POL_CTRL, HDCP2X_DIS_POLL_EN, + HDCP2X_DIS_POLL_EN); +} + +static void ddc_wr_one(struct mtk_hdmi_ddc *ddc, unsigned int addr_id, + unsigned int offset_id, unsigned char wr_data) +{ + if (mtk_ddc_read(ddc, HDCP2X_DDCM_STATUS) & DDC_I2C_BUS_LOW) { + mtk_ddc_mask(ddc, DDC_CTRL, (CLOCK_SCL << DDC_CMD_SHIFT), + DDC_CMD); + udelay(300); + } + mtk_ddc_mask(ddc, HPD_DDC_CTRL, DDC2_CLOCK << DDC_DELAY_CNT_SHIFT, + DDC_DELAY_CNT); + mtk_ddc_write(ddc, SI2C_CTRL, SI2C_ADDR_READ << SI2C_ADDR_SHIFT); + mtk_ddc_mask(ddc, SI2C_CTRL, wr_data << SI2C_WDATA_SHIFT, SI2C_WDATA); + mtk_ddc_mask(ddc, SI2C_CTRL, SI2C_WR, SI2C_WR); + + mtk_ddc_write(ddc, DDC_CTRL, + (SEQ_WRITE_REQ_ACK << DDC_CMD_SHIFT) + + (1 << DDC_DIN_CNT_SHIFT) + + (offset_id << DDC_OFFSET_SHIFT) + (addr_id << 1)); + + udelay(1250); + + if ((mtk_ddc_read(ddc, HDCP2X_DDCM_STATUS) & + (DDC_I2C_NO_ACK | DDC_I2C_BUS_LOW))) { + if (mtk_ddc_read(ddc, HDCP2X_DDCM_STATUS) & DDC_I2C_BUS_LOW) { + mtk_ddc_mask(ddc, DDC_CTRL, + (CLOCK_SCL << DDC_CMD_SHIFT), DDC_CMD); + udelay(300); + } + } +} + +static unsigned int +ddcm_read_hdmi(struct mtk_hdmi_ddc *ddc, unsigned int u4_clk_div, + unsigned char uc_dev, unsigned int u4_addr, + unsigned char *puc_value, unsigned int u4_count) +{ + unsigned int i, temp_length, loop_counter; + unsigned int uc_read_count = 0, uc_idx; + unsigned long ddc_start_time, ddc_end_time, ddc_timeout; + + if (!puc_value || !u4_count || !u4_clk_div) + return 0; + + if (mtk_ddc_read(ddc, HDCP2X_DDCM_STATUS) & DDC_I2C_BUS_LOW) { + mtk_ddc_mask(ddc, DDC_CTRL, (CLOCK_SCL << DDC_CMD_SHIFT), + DDC_CMD); + udelay(300); + } + + mtk_ddc_mask(ddc, DDC_CTRL, (CLEAR_FIFO << DDC_CMD_SHIFT), DDC_CMD); + + if (u4_count >= 16) { + temp_length = 16; + loop_counter = u4_count / 16 + ((u4_count % 16 == 0) ? 0 : 1); + } else { + temp_length = u4_count; + loop_counter = 1; + } + + if (uc_dev >= EDID_ADDR && u4_clk_div < DDC2_CLOCK_EDID) + u4_clk_div = DDC2_CLOCK_EDID; + + mtk_ddc_mask(ddc, HPD_DDC_CTRL, u4_clk_div << DDC_DELAY_CNT_SHIFT, + DDC_DELAY_CNT); + + for (i = 0; i < loop_counter; i++) { + if (i == (loop_counter - 1) && i != 0 && u4_count % 16) + temp_length = u4_count % 16; + + /* EDID_ADDR(0x50) + 1 .. 0x53 select an EDID segment */ + if (uc_dev > EDID_ADDR && uc_dev <= 0x53) { + mtk_ddc_mask(ddc, SCDC_CTRL, + (uc_dev - EDID_ADDR) + << DDC_SEGMENT_SHIFT, + DDC_SEGMENT); + mtk_ddc_write(ddc, DDC_CTRL, + (ENH_READ_NO_ACK << DDC_CMD_SHIFT) + + (temp_length << DDC_DIN_CNT_SHIFT) + + ((u4_addr + i * temp_length) + << DDC_OFFSET_SHIFT) + + (EDID_ADDR << 1)); + } else { + mtk_ddc_write(ddc, DDC_CTRL, + (SEQ_READ_NO_ACK << DDC_CMD_SHIFT) + + (temp_length << DDC_DIN_CNT_SHIFT) + + ((u4_addr + i * 16) + << DDC_OFFSET_SHIFT) + (uc_dev << 1)); + } + udelay(5500); + ddc_start_time = get_timer(0); + /* timeout in ms: about 1 ms per byte plus some margin */ + ddc_timeout = temp_length + 5; + ddc_end_time = ddc_start_time + ddc_timeout; + while (1) { + if ((mtk_ddc_read(ddc, HPD_DDC_STATUS) & + DDC_I2C_IN_PROG) == 0) + break; + + if (time_after(get_timer(0), ddc_end_time)) { + dev_err(ddc->udev, "DDC transfer timeout\n"); + return 0; + } + udelay(1500); + } + if ((mtk_ddc_read(ddc, HDCP2X_DDCM_STATUS) & + (DDC_I2C_NO_ACK | DDC_I2C_BUS_LOW))) { + if (mtk_ddc_read(ddc, HDCP2X_DDCM_STATUS) & + DDC_I2C_BUS_LOW) { + mtk_ddc_mask(ddc, DDC_CTRL, + (CLOCK_SCL << DDC_CMD_SHIFT), + DDC_CMD); + udelay(300); + } + return 0; + } + + /* get the DDC data from the FIFO */ + for (uc_idx = 0; uc_idx < temp_length; uc_idx++) { + /* latch the FIFO output */ + mtk_ddc_write(ddc, SI2C_CTRL, + (SI2C_ADDR_READ << SI2C_ADDR_SHIFT) + + SI2C_RD); + + /* read FIFO output value from DDC_STATUS */ + puc_value[i * 16 + uc_idx] = + (mtk_ddc_read(ddc, HPD_DDC_STATUS) & + DDC_DATA_OUT) >> DDC_DATA_OUT_SHIFT; + + /* increment FIFO read pointer, un-latch the FIFO */ + mtk_ddc_write(ddc, SI2C_CTRL, + (SI2C_ADDR_READ << SI2C_ADDR_SHIFT) + + SI2C_CONFIRM_READ); + /* + * if the hdmi block was reset while reading, the DDC + * speed falls back below DDC2_CLOCK: abort + */ + if (((mtk_ddc_read(ddc, HPD_DDC_CTRL) >> 16) & + 0xFFFF) < DDC2_CLOCK) + return 0; + + uc_read_count = i * 16 + uc_idx + 1; + } + } + + return uc_read_count; +} + +static unsigned int vddc_read(struct mtk_hdmi_ddc *ddc, + unsigned int u4_clk_div, unsigned char uc_dev, + unsigned int u4_addr, + enum sif_bit_t_hdmi uc_addr_type, + unsigned char *puc_value, unsigned int u4_count) +{ + unsigned int u4_read_count = 0; + + if (!puc_value || !u4_count || !u4_clk_div) + return 0; + if (uc_addr_type > SIF_16_BIT_HDMI) + return 0; + if (uc_addr_type == SIF_8_BIT_HDMI && u4_addr > 255) + return 0; + if (uc_addr_type == SIF_16_BIT_HDMI && u4_addr > 65535) + return 0; + + if (uc_addr_type == SIF_8_BIT_HDMI) + u4_read_count = 255 - u4_addr + 1; + else if (uc_addr_type == SIF_16_BIT_HDMI) + u4_read_count = 65535 - u4_addr + 1; + + u4_read_count = min(u4_read_count, u4_count); + + return ddcm_read_hdmi(ddc, u4_clk_div, uc_dev, u4_addr, puc_value, + u4_read_count); +} + +static int fg_ddc_data_read(struct mtk_hdmi_ddc *ddc, unsigned char b_dev, + unsigned char b_data_addr, + unsigned int b_data_count, unsigned char *pr_data) +{ + mtk_ddc_disable_hdcp_polling(ddc); + if (vddc_read(ddc, DDC2_CLOCK, b_dev, b_data_addr, SIF_8_BIT_HDMI, + pr_data, b_data_count) != b_data_count) + return -EREMOTEIO; + + return 0; +} + +static int fg_ddc_data_write(struct mtk_hdmi_ddc *ddc, unsigned char b_dev, + unsigned char b_data_addr, + unsigned int b_data_count, + unsigned char *pr_data) +{ + unsigned int i; + + mtk_ddc_disable_hdcp_polling(ddc); + for (i = 0; i < b_data_count; i++) + ddc_wr_one(ddc, b_dev, b_data_addr + i, *(pr_data + i)); + + return 0; +} + +static int mtk_hdmi_ddc_xfer(struct udevice *dev, struct i2c_msg *msgs, int num) +{ + struct mtk_hdmi_ddc *ddc = dev_get_priv(dev); + unsigned char offset = 0; + int ret; + int i; + + if (!msgs) + return -EINVAL; + + if (!ddc || !ddc->regs) + return -EINVAL; + + for (i = 0; i < num; i++) { + struct i2c_msg *msg = &msgs[i]; + + if (!msg->buf || !msg->len) + return -EINVAL; + + if (msg->flags & I2C_M_RD) { + /* + * The underlying DDC hardware always issues a write + * request that assigns the read offset as part of the + * read operation, so use the offset value stored on + * the previous write request. + */ + ret = fg_ddc_data_read(ddc, msg->addr, offset, + msg->len, &msg->buf[0]); + } else { + ret = fg_ddc_data_write(ddc, msg->addr, msg->buf[0], + msg->len - 1, &msg->buf[1]); + + /* + * store the offset requested by the EDID/SCDC + * framework for use by subsequent read requests + */ + if ((msg->addr == EDID_ADDR || + msg->addr == SCDC_I2C_SLAVE_ADDRESS) && + msg->len == 1) + offset = msg->buf[0]; + } + + if (ret) { + dev_err(dev, "ddc transfer failed: %d\n", ret); + return ret; + } + } + + return 0; +} + +static int mtk_hdmi_ddc_probe(struct udevice *dev) +{ + struct mtk_hdmi_ddc *ddc = dev_get_priv(dev); + int ret; + + ddc->udev = dev; + /* the ddc node sits below the hdmi node, which holds the registers */ + ddc->regs = dev_read_addr_ptr(dev->parent); + if (!ddc->regs) + return -EINVAL; + + ret = clk_get_by_index(dev, 0, &ddc->clk); + if (ret) { + dev_err(dev, "failed to get ddc clk: %d\n", ret); + return ret; + } + + ret = clk_enable(&ddc->clk); + if (ret) { + dev_err(dev, "failed to enable ddc clk: %d\n", ret); + return ret; + } + + return 0; +} + +static const struct dm_i2c_ops mtk_hdmi_ddc_ops = { + .xfer = mtk_hdmi_ddc_xfer, +}; + +static const struct udevice_id mtk_hdmi_ddc_ids[] = { + { .compatible = "mediatek,mt8195-hdmi-ddc", }, + { } +}; + +U_BOOT_DRIVER(mtk_i2c_ddc) = { + .name = "mtk_i2c_ddc", + .id = UCLASS_I2C, + .of_match = mtk_hdmi_ddc_ids, + .probe = mtk_hdmi_ddc_probe, + .priv_auto = sizeof(struct mtk_hdmi_ddc), + .ops = &mtk_hdmi_ddc_ops, +}; -- cgit v1.3.1 From f9cb14dd25e65062283453b9755b9f09714565dc Mon Sep 17 00:00:00 2001 From: Julien Stephan Date: Tue, 28 Jul 2026 17:01:56 +0200 Subject: phy: phy-mtk-hdmi: add new driver Add a new driver for the HDMI PHY. The driver supports MT8188 and MT8195 based SoCs. The driver is based on the corresponding kernel driver (Commit 7a4ce5a9b674 - phy: mediatek: phy-mtk-hdmi-mt8195: convert from round_rate() to determine_rate()). Signed-off-by: Pavlo Yadvychuk Signed-off-by: Julien Stephan Reviewed-by: Mattijs Korpershoek Link: https://patch.msgid.link/20260728-mt8188-add-hdmi-phy-driver-v2-1-8b2893b151ba@baylibre.com Signed-off-by: David Lechner --- drivers/phy/Kconfig | 11 + drivers/phy/Makefile | 1 + drivers/phy/phy-mtk-hdmi-mt8195.c | 493 ++++++++++++++++++++++++++++++++++++++ drivers/phy/phy-mtk-hdmi-mt8195.h | 115 +++++++++ drivers/phy/phy-mtk-hdmi.c | 106 ++++++++ drivers/phy/phy-mtk-hdmi.h | 46 ++++ drivers/phy/phy-mtk-io.h | 46 ++++ 7 files changed, 818 insertions(+) create mode 100644 drivers/phy/phy-mtk-hdmi-mt8195.c create mode 100644 drivers/phy/phy-mtk-hdmi-mt8195.h create mode 100644 drivers/phy/phy-mtk-hdmi.c create mode 100644 drivers/phy/phy-mtk-hdmi.h create mode 100644 drivers/phy/phy-mtk-io.h diff --git a/drivers/phy/Kconfig b/drivers/phy/Kconfig index 16eaa67fd02..6262380a60a 100644 --- a/drivers/phy/Kconfig +++ b/drivers/phy/Kconfig @@ -278,6 +278,17 @@ config PHY_EXYNOS_USBDRD help Enable USB DRD PHY support for Exynos SoC series. +config PHY_MTK_HDMI + bool "MediaTek HDMI-PHY Driver" + depends on PHY + depends on ARCH_MEDIATEK + depends on ARM64 + depends on CLK + help + Support for the HDMI TX PHY found on MediaTek SoCs such as the + MT8188 and MT8195. The PHY provides the TMDS links and the pixel + clock PLL to the HDMI TX controller. + config PHY_MTK_TPHY bool "MediaTek T-PHY Driver" depends on PHY diff --git a/drivers/phy/Makefile b/drivers/phy/Makefile index 7ad0bd59407..19cf95759e5 100644 --- a/drivers/phy/Makefile +++ b/drivers/phy/Makefile @@ -37,6 +37,7 @@ obj-$(CONFIG_MT76X8_USB_PHY) += mt76x8-usb-phy.o obj-$(CONFIG_PHY_AXIADO_EMMC) += phy-axiado-emmc.o obj-$(CONFIG_PHY_DA8XX_USB) += phy-da8xx-usb.o obj-$(CONFIG_PHY_EXYNOS_USBDRD) += phy-exynos-usbdrd.o +obj-$(CONFIG_PHY_MTK_HDMI) += phy-mtk-hdmi.o phy-mtk-hdmi-mt8195.o obj-$(CONFIG_PHY_MTK_TPHY) += phy-mtk-tphy.o obj-$(CONFIG_PHY_MTK_UFS) += phy-mtk-ufs.o obj-$(CONFIG_PHY_MTK_XSPHY) += phy-mtk-xsphy.o diff --git a/drivers/phy/phy-mtk-hdmi-mt8195.c b/drivers/phy/phy-mtk-hdmi-mt8195.c new file mode 100644 index 00000000000..cba4564bc47 --- /dev/null +++ b/drivers/phy/phy-mtk-hdmi-mt8195.c @@ -0,0 +1,493 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) 2022 MediaTek Inc. + * Copyright (c) 2026 BayLibre, SAS + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +#include "phy-mtk-io.h" +#include "phy-mtk-hdmi.h" +#include "phy-mtk-hdmi-mt8195.h" + +/* linux/units.h is not available in U-Boot */ +#define MEGA 1000000UL +#define GIGA 1000000000UL + +static void mtk_hdmi_ana_fifo_en(struct mtk_hdmi_phy *hdmi_phy) +{ + /* make data fifo writable for hdmi2.0 */ + mtk_phy_set_bits(hdmi_phy->regs + HDMI_ANA_CTL, REG_ANA_HDMI20_FIFO_EN); +} + +static void +mtk_phy_tmds_clk_ratio(struct mtk_hdmi_phy *hdmi_phy, bool enable) +{ + void __iomem *regs = hdmi_phy->regs; + + mtk_hdmi_ana_fifo_en(hdmi_phy); + + /* HDMI 2.0 specification, 3.4Gbps <= TMDS Bit Rate <= 6G, + * clock bit ratio 1:40, under 3.4Gbps, clock bit ratio 1:10 + */ + if (enable) + mtk_phy_update_field(regs + HDMI20_CLK_CFG, REG_TXC_DIV, 3); + else + mtk_phy_clear_bits(regs + HDMI20_CLK_CFG, REG_TXC_DIV); +} + +static void mtk_hdmi_pll_sel_src(struct mtk_hdmi_phy *hdmi_phy) +{ + void __iomem *regs = hdmi_phy->regs; + + mtk_phy_clear_bits(regs + HDMI_CTL_3, REG_HDMITX_REF_XTAL_SEL); + mtk_phy_clear_bits(regs + HDMI_CTL_3, REG_HDMITX_REF_RESPLL_SEL); + + /* DA_HDMITX21_REF_CK for TXPLL input source */ + mtk_phy_clear_bits(regs + HDMI_1_CFG_10, RG_HDMITXPLL_REF_CK_SEL); +} + +static void mtk_hdmi_pll_perf(struct mtk_hdmi_phy *hdmi_phy) +{ + void __iomem *regs = hdmi_phy->regs; + + mtk_phy_set_bits(regs + HDMI_1_PLL_CFG_0, RG_HDMITXPLL_BP2); + mtk_phy_set_bits(regs + HDMI_1_PLL_CFG_2, RG_HDMITXPLL_BC); + mtk_phy_update_field(regs + HDMI_1_PLL_CFG_2, RG_HDMITXPLL_IC, 0x1); + mtk_phy_update_field(regs + HDMI_1_PLL_CFG_2, RG_HDMITXPLL_BR, 0x2); + mtk_phy_update_field(regs + HDMI_1_PLL_CFG_2, RG_HDMITXPLL_IR, 0x2); + mtk_phy_set_bits(regs + HDMI_1_PLL_CFG_2, RG_HDMITXPLL_BP); + mtk_phy_clear_bits(regs + HDMI_1_PLL_CFG_0, RG_HDMITXPLL_IBAND_FIX_EN); + mtk_phy_clear_bits(regs + HDMI_1_PLL_CFG_1, RG_HDMITXPLL_RESERVE_BIT14); + mtk_phy_clear_bits(regs + HDMI_1_PLL_CFG_2, RG_HDMITXPLL_HIKVCO); + mtk_phy_update_field(regs + HDMI_1_PLL_CFG_0, RG_HDMITXPLL_HREN, 0x1); + mtk_phy_update_field(regs + HDMI_1_PLL_CFG_0, RG_HDMITXPLL_LVR_SEL, 0x1); + mtk_phy_set_bits(regs + HDMI_1_PLL_CFG_1, RG_HDMITXPLL_RESERVE_BIT12_11); + mtk_phy_set_bits(regs + HDMI_1_PLL_CFG_0, RG_HDMITXPLL_TCL_EN); +} + +static int mtk_hdmi_pll_set_hw(struct mtk_hdmi_phy *hdmi_phy, u8 prediv, + u8 fbkdiv_high, + u32 fbkdiv_low, + u8 fbkdiv_hs3, u8 posdiv1, + u8 posdiv2, u8 txprediv, + u8 txposdiv, + u8 digital_div) +{ + u8 txposdiv_value; + u8 div3_ctrl_value; + u8 posdiv_vallue; + u8 div_ctrl_value; + u8 reserve_3_2_value; + u8 prediv_value; + u8 reserve13_value; + void __iomem *regs = hdmi_phy->regs; + + mtk_hdmi_pll_sel_src(hdmi_phy); + + mtk_hdmi_pll_perf(hdmi_phy); + + mtk_phy_update_field(regs + HDMI_1_CFG_10, RG_HDMITX21_BIAS_PE_BG_VREF_SEL, 0x2); + mtk_phy_clear_bits(regs + HDMI_1_CFG_10, RG_HDMITX21_VREF_SEL); + mtk_phy_update_field(regs + HDMI_1_CFG_9, RG_HDMITX21_SLDO_VREF_SEL, 0x2); + mtk_phy_clear_bits(regs + HDMI_1_CFG_10, RG_HDMITX21_BIAS_PE_VREF_SELB); + mtk_phy_set_bits(regs + HDMI_1_CFG_3, RG_HDMITX21_SLDOLPF_EN); + mtk_phy_update_field(regs + HDMI_1_CFG_6, RG_HDMITX21_INTR_CAL, 0x11); + mtk_phy_set_bits(regs + HDMI_1_PLL_CFG_2, RG_HDMITXPLL_PWD); + + /* TXPOSDIV */ + txposdiv_value = ilog2(txposdiv); + + mtk_phy_update_field(regs + HDMI_1_CFG_6, RG_HDMITX21_TX_POSDIV, txposdiv_value); + mtk_phy_set_bits(regs + HDMI_1_CFG_6, RG_HDMITX21_TX_POSDIV_EN); + mtk_phy_clear_bits(regs + HDMI_1_CFG_6, RG_HDMITX21_FRL_EN); + + /* TXPREDIV */ + switch (txprediv) { + case 2: + div3_ctrl_value = 0x0; + posdiv_vallue = 0x0; + break; + case 4: + div3_ctrl_value = 0x0; + posdiv_vallue = 0x1; + break; + case 6: + div3_ctrl_value = 0x1; + posdiv_vallue = 0x0; + break; + case 12: + div3_ctrl_value = 0x1; + posdiv_vallue = 0x1; + break; + default: + return -EINVAL; + } + + mtk_phy_update_field(regs + HDMI_1_PLL_CFG_4, RG_HDMITXPLL_POSDIV_DIV3_CTRL, div3_ctrl_value); + mtk_phy_update_field(regs + HDMI_1_PLL_CFG_4, RG_HDMITXPLL_POSDIV, posdiv_vallue); + + /* POSDIV1 */ + switch (posdiv1) { + case 5: + div_ctrl_value = 0x0; + break; + case 10: + div_ctrl_value = 0x1; + break; + case 12: + div_ctrl_value = 0x2; + break; + case 15: + div_ctrl_value = 0x3; + break; + default: + return -EINVAL; + } + + mtk_phy_update_field(regs + HDMI_1_PLL_CFG_4, RG_HDMITXPLL_DIV_CTRL, div_ctrl_value); + + /* DE add new setting */ + mtk_phy_clear_bits(regs + HDMI_1_PLL_CFG_1, RG_HDMITXPLL_RESERVE_BIT14); + + /* POSDIV2 */ + switch (posdiv2) { + case 1: + reserve_3_2_value = 0x0; + break; + case 2: + reserve_3_2_value = 0x1; + break; + case 4: + reserve_3_2_value = 0x2; + break; + case 6: + reserve_3_2_value = 0x3; + break; + default: + return -EINVAL; + } + + mtk_phy_update_field(regs + HDMI_1_PLL_CFG_1, RG_HDMITXPLL_RESERVE_BIT3_2, reserve_3_2_value); + + /* DE add new setting */ + mtk_phy_update_field(regs + HDMI_1_PLL_CFG_1, RG_HDMITXPLL_RESERVE_BIT1_0, 0x2); + + /* PREDIV */ + prediv_value = ilog2(prediv); + + mtk_phy_update_field(regs + HDMI_1_PLL_CFG_4, RG_HDMITXPLL_PREDIV, prediv_value); + + /* FBKDIV_HS3 */ + reserve13_value = ilog2(fbkdiv_hs3); + + mtk_phy_update_field(regs + HDMI_1_PLL_CFG_1, RG_HDMITXPLL_RESERVE_BIT13, reserve13_value); + + /* FBDIV */ + mtk_phy_update_field(regs + HDMI_1_PLL_CFG_4, RG_HDMITXPLL_FBKDIV_HIGH, fbkdiv_high); + mtk_phy_update_field(regs + HDMI_1_PLL_CFG_3, RG_HDMITXPLL_FBKDIV_LOW, fbkdiv_low); + + /* Digital DIVIDER */ + mtk_phy_clear_bits(regs + HDMI_CTL_3, REG_PIXEL_CLOCK_SEL); + + if (digital_div == 1) { + mtk_phy_clear_bits(regs + HDMI_CTL_3, REG_HDMITX_PIXEL_CLOCK); + } else { + mtk_phy_set_bits(regs + HDMI_CTL_3, REG_HDMITX_PIXEL_CLOCK); + mtk_phy_update_field(regs + HDMI_CTL_3, REG_HDMITXPLL_DIV, digital_div - 1); + } + + return 0; +} + +static int mtk_hdmi_pll_calc(struct mtk_hdmi_phy *hdmi_phy, unsigned long rate) +{ + u8 digital_div, txprediv, txposdiv, fbkdiv_high, posdiv1, posdiv2; + u64 tmds_clk, pixel_clk, ns_hdmipll_ck, pcw; + u8 txpredivs[4] = { 2, 4, 6, 12 }; + u32 da_hdmitx21_ref_ck, fbkdiv_low; + int i; + + pixel_clk = rate; + tmds_clk = pixel_clk; + + if (tmds_clk < 25 * MEGA || tmds_clk > 594 * MEGA) + return -EINVAL; + + if (tmds_clk >= 340 * MEGA) + hdmi_phy->tmds_over_340M = true; + else + hdmi_phy->tmds_over_340M = false; + + /* in Hz */ + da_hdmitx21_ref_ck = 26 * MEGA; + + /* TXPOSDIV stage treatment: + * 0M < TMDS clk < 54M /8 + * 54M <= TMDS clk < 148.35M /4 + * 148.35M <=TMDS clk < 296.7M /2 + * 296.7 <=TMDS clk <= 594M /1 + */ + if (tmds_clk < 54 * MEGA) + txposdiv = 8; + else if (tmds_clk >= 54 * MEGA && (tmds_clk * 100) < 14835 * MEGA) + txposdiv = 4; + else if ((tmds_clk * 100) >= 14835 * MEGA && (tmds_clk * 10) < 2967 * MEGA) + txposdiv = 2; + else if ((tmds_clk * 10) >= 2967 * MEGA && tmds_clk <= 594 * MEGA) + txposdiv = 1; + else + return -EINVAL; + + /* calculate txprediv: can be 2, 4, 6, 12 + * ICO clk = 5*TMDS_CLK*TXPOSDIV*TXPREDIV + * ICO clk constraint: 5G =< ICO clk <= 12G + */ + for (i = 0; i < ARRAY_SIZE(txpredivs); i++) { + ns_hdmipll_ck = 5 * tmds_clk * txposdiv * txpredivs[i]; + if (ns_hdmipll_ck >= 5 * GIGA && + ns_hdmipll_ck <= 12 * GIGA) + break; + } + if (i == (ARRAY_SIZE(txpredivs) - 1) && + (ns_hdmipll_ck < 5 * GIGA || ns_hdmipll_ck > 12 * GIGA)) { + return -EINVAL; + } + if (i == ARRAY_SIZE(txpredivs)) + return -EINVAL; + + txprediv = txpredivs[i]; + + /* PCW calculation: FBKDIV + * formula: pcw=(frequency_out*2^pcw_bit) / frequency_in / FBKDIV_HS3; + * RG_HDMITXPLL_FBKDIV[32:0]: + * [32,24] 9bit integer, [23,0]:24bit fraction + */ + pcw = div_u64(((u64)ns_hdmipll_ck) << PCW_DECIMAL_WIDTH, + da_hdmitx21_ref_ck * PLL_FBKDIV_HS3); + + if (pcw > GENMASK_ULL(32, 0)) + return -EINVAL; + + fbkdiv_high = FIELD_GET(GENMASK_ULL(63, 32), pcw); + fbkdiv_low = FIELD_GET(GENMASK(31, 0), pcw); + + /* posdiv1: + * posdiv1 stage treatment according to color_depth: + * 24bit -> posdiv1 /10, 30bit -> posdiv1 /12.5, + * 36bit -> posdiv1 /15, 48bit -> posdiv1 /10 + */ + posdiv1 = 10; + posdiv2 = 1; + + /* Digital clk divider, max /32 */ + digital_div = div64_u64(ns_hdmipll_ck, posdiv1 * posdiv2 * pixel_clk); + if (!(digital_div <= 32 && digital_div >= 1)) + return -EINVAL; + + return mtk_hdmi_pll_set_hw(hdmi_phy, PLL_PREDIV, fbkdiv_high, fbkdiv_low, + PLL_FBKDIV_HS3, posdiv1, posdiv2, txprediv, + txposdiv, digital_div); +} + +static int mtk_hdmi_pll_drv_setting(struct mtk_hdmi_phy *hdmi_phy) +{ + void __iomem *regs = hdmi_phy->regs; + u8 data_channel_bias, clk_channel_bias; + u8 impedance, impedance_en; + u32 tmds_clk; + u32 pixel_clk = hdmi_phy->pll_rate; + + tmds_clk = pixel_clk; + + /* bias & impedance setting: + * 3G < data rate <= 6G: enable impedance 100ohm, + * data channel bias 24mA, clock channel bias 20mA + * pixel clk >= HD, 74.175MHZ <= pixel clk <= 300MHZ: + * enalbe impedance 100ohm + * data channel 20mA, clock channel 16mA + * 27M =< pixel clk < 74.175: disable impedance + * data channel & clock channel bias 10mA + */ + + /* 3G < data rate <= 6G, 300M < tmds rate <= 594M */ + if (tmds_clk > 300 * MEGA && tmds_clk <= 594 * MEGA) { + data_channel_bias = 0x3c; /* 24mA */ + clk_channel_bias = 0x34; /* 20mA */ + impedance_en = 0xf; + impedance = 0x36; /* 100ohm */ + } else if (((u64)pixel_clk * 1000) >= 74175 * MEGA && pixel_clk <= 300 * MEGA) { + data_channel_bias = 0x34; /* 20mA */ + clk_channel_bias = 0x2c; /* 16mA */ + impedance_en = 0xf; + impedance = 0x36; /* 100ohm */ + } else if (pixel_clk >= 27 * MEGA && ((u64)pixel_clk * 1000) < 74175 * MEGA) { + data_channel_bias = 0x14; /* 10mA */ + clk_channel_bias = 0x14; /* 10mA */ + impedance_en = 0x0; + impedance = 0x0; + } else { + return -EINVAL; + } + + /* bias */ + mtk_phy_update_field(regs + HDMI_1_CFG_1, RG_HDMITX21_DRV_IBIAS_D0, data_channel_bias); + mtk_phy_update_field(regs + HDMI_1_CFG_1, RG_HDMITX21_DRV_IBIAS_D1, data_channel_bias); + mtk_phy_update_field(regs + HDMI_1_CFG_1, RG_HDMITX21_DRV_IBIAS_D2, data_channel_bias); + mtk_phy_update_field(regs + HDMI_1_CFG_0, RG_HDMITX21_DRV_IBIAS_CLK, clk_channel_bias); + + /* impedance */ + mtk_phy_update_field(regs + HDMI_1_CFG_0, RG_HDMITX21_DRV_IMP_EN, impedance_en); + mtk_phy_update_field(regs + HDMI_1_CFG_2, RG_HDMITX21_DRV_IMP_D0_EN1, impedance); + mtk_phy_update_field(regs + HDMI_1_CFG_2, RG_HDMITX21_DRV_IMP_D1_EN1, impedance); + mtk_phy_update_field(regs + HDMI_1_CFG_2, RG_HDMITX21_DRV_IMP_D2_EN1, impedance); + mtk_phy_update_field(regs + HDMI_1_CFG_2, RG_HDMITX21_DRV_IMP_CLK_EN1, impedance); + + return 0; +} + +static int mtk_hdmi_pll_prepare(struct mtk_hdmi_phy *hdmi_phy) +{ + void __iomem *regs = hdmi_phy->regs; + int ret; + + mtk_phy_set_bits(regs + HDMI_1_CFG_6, RG_HDMITX21_TX_POSDIV_EN); + + mtk_phy_set_bits(regs + HDMI_1_CFG_0, RG_HDMITX21_SER_EN); + mtk_phy_set_bits(regs + HDMI_1_CFG_6, RG_HDMITX21_D0_DRV_OP_EN); + mtk_phy_set_bits(regs + HDMI_1_CFG_6, RG_HDMITX21_D1_DRV_OP_EN); + mtk_phy_set_bits(regs + HDMI_1_CFG_6, RG_HDMITX21_D2_DRV_OP_EN); + mtk_phy_set_bits(regs + HDMI_1_CFG_6, RG_HDMITX21_CK_DRV_OP_EN); + + mtk_phy_clear_bits(regs + HDMI_1_CFG_6, RG_HDMITX21_FRL_D0_EN); + mtk_phy_clear_bits(regs + HDMI_1_CFG_6, RG_HDMITX21_FRL_D1_EN); + mtk_phy_clear_bits(regs + HDMI_1_CFG_6, RG_HDMITX21_FRL_D2_EN); + mtk_phy_clear_bits(regs + HDMI_1_CFG_6, RG_HDMITX21_FRL_CK_EN); + + ret = mtk_hdmi_pll_drv_setting(hdmi_phy); + if (ret) + return ret; + + mtk_phy_clear_bits(regs + HDMI_1_CFG_10, RG_HDMITX21_BG_PWD); + mtk_phy_set_bits(regs + HDMI_1_CFG_6, RG_HDMITX21_BIAS_EN); + mtk_phy_set_bits(regs + HDMI_1_CFG_3, RG_HDMITX21_CKLDO_EN); + mtk_phy_set_bits(regs + HDMI_1_CFG_3, RG_HDMITX21_SLDO_EN); + + mtk_phy_set_bits(regs + HDMI_1_PLL_CFG_4, DA_HDMITXPLL_PWR_ON); + udelay(10); + mtk_phy_clear_bits(regs + HDMI_1_PLL_CFG_4, DA_HDMITXPLL_ISO_EN); + udelay(10); + mtk_phy_clear_bits(regs + HDMI_1_PLL_CFG_2, RG_HDMITXPLL_PWD); + udelay(50); + + return 0; +} + +static void mtk_hdmi_pll_unprepare(struct mtk_hdmi_phy *hdmi_phy) +{ + void __iomem *regs = hdmi_phy->regs; + + mtk_phy_set_bits(regs + HDMI_1_CFG_10, RG_HDMITX21_BG_PWD); + mtk_phy_clear_bits(regs + HDMI_1_CFG_6, RG_HDMITX21_BIAS_EN); + mtk_phy_clear_bits(regs + HDMI_1_CFG_3, RG_HDMITX21_CKLDO_EN); + mtk_phy_clear_bits(regs + HDMI_1_CFG_3, RG_HDMITX21_SLDO_EN); + + mtk_phy_set_bits(regs + HDMI_1_PLL_CFG_2, RG_HDMITXPLL_PWD); + udelay(20); + mtk_phy_set_bits(regs + HDMI_1_PLL_CFG_4, DA_HDMITXPLL_ISO_EN); + udelay(20); + mtk_phy_clear_bits(regs + HDMI_1_PLL_CFG_4, DA_HDMITXPLL_PWR_ON); +} + +static int mtk_hdmi_pll_set_rate(struct mtk_hdmi_phy *hdmi_phy, + unsigned long rate) +{ + dev_dbg(hdmi_phy->dev, "%s: %lu Hz\n", __func__, rate); + + return mtk_hdmi_pll_calc(hdmi_phy, rate); +} + +static void mtk_hdmi_pll_determine_rate(struct mtk_hdmi_phy *hdmi_phy, + unsigned long rate) +{ + hdmi_phy->pll_rate = rate; +} + +static void vtx_signal_en(struct mtk_hdmi_phy *hdmi_phy, bool on) +{ + void __iomem *regs = hdmi_phy->regs; + + if (on) + mtk_phy_set_bits(regs + HDMI_1_CFG_0, RG_HDMITX21_DRV_EN); + else + mtk_phy_clear_bits(regs + HDMI_1_CFG_0, RG_HDMITX21_DRV_EN); +} + +static void mtk_hdmi_phy_enable_tmds(struct mtk_hdmi_phy *hdmi_phy) +{ + vtx_signal_en(hdmi_phy, true); + udelay(150); +} + +static void mtk_hdmi_phy_disable_tmds(struct mtk_hdmi_phy *hdmi_phy) +{ + vtx_signal_en(hdmi_phy, false); +} + +static int mtk_hdmi_phy_configure(struct phy *phy, void *opts) +{ + struct mtk_hdmi_phy *hdmi_phy = dev_get_priv(phy->dev); + unsigned long link_rate; + int ret; + + if (!opts) + return -EINVAL; + + link_rate = *(unsigned long *)opts; + + /* + * The kernel driver performs this through clk_set_rate() on the PLL + * clock, which runs the determine_rate and set_rate clk_ops. U-Boot + * does not register the PLL as a clock, so drive them directly. + */ + hdmi_phy->conf->pll_determine_rate(hdmi_phy, link_rate); + + ret = hdmi_phy->conf->pll_set_rate(hdmi_phy, hdmi_phy->pll_rate); + if (ret) + return ret; + + mtk_phy_tmds_clk_ratio(hdmi_phy, hdmi_phy->tmds_over_340M); + + return ret; +} + +/* + * The 5V output is modelled as a regulator in the Linux driver; U-Boot has no + * consumer for it, so it is exposed as a simple power_control() callback. + */ +static void mtk_hdmi_phy_power_control(struct mtk_hdmi_phy *hdmi_phy, + bool enable) +{ + if (enable) + mtk_phy_set_bits(hdmi_phy->regs + HDMI_CTL_1, RG_HDMITX_PWR5V_O); + else + mtk_phy_clear_bits(hdmi_phy->regs + HDMI_CTL_1, RG_HDMITX_PWR5V_O); +} + +const struct mtk_hdmi_phy_conf mtk_hdmi_phy_8195_conf = { + .pll_prepare = mtk_hdmi_pll_prepare, + .pll_unprepare = mtk_hdmi_pll_unprepare, + .pll_set_rate = mtk_hdmi_pll_set_rate, + .pll_determine_rate = mtk_hdmi_pll_determine_rate, + .hdmi_phy_enable_tmds = mtk_hdmi_phy_enable_tmds, + .hdmi_phy_disable_tmds = mtk_hdmi_phy_disable_tmds, + .hdmi_phy_configure = mtk_hdmi_phy_configure, + .power_control = mtk_hdmi_phy_power_control, +}; diff --git a/drivers/phy/phy-mtk-hdmi-mt8195.h b/drivers/phy/phy-mtk-hdmi-mt8195.h new file mode 100644 index 00000000000..76c42f378d5 --- /dev/null +++ b/drivers/phy/phy-mtk-hdmi-mt8195.h @@ -0,0 +1,115 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (c) 2022 MediaTek Inc. + * Copyright (c) 2026 BayLibre, SAS + */ + +#ifndef _MTK_HDMI_PHY_8195_H +#define _MTK_HDMI_PHY_8195_H + +#include +#include + +#define PCW_DECIMAL_WIDTH 24 +#define PLL_PREDIV 1 +#define PLL_FBKDIV_HS3 1 + +#define HDMI20_CLK_CFG 0x70 +#define REG_TXC_DIV GENMASK(31, 30) + +#define HDMI_1_CFG_0 0x00 +#define RG_HDMITX21_DRV_IBIAS_CLK GENMASK(10, 5) +#define RG_HDMITX21_DRV_IMP_EN GENMASK(23, 20) +#define RG_HDMITX21_DRV_EN GENMASK(27, 24) +#define RG_HDMITX21_SER_EN GENMASK(31, 28) + +#define HDMI_1_CFG_1 0x04 +#define RG_HDMITX21_DRV_IBIAS_D0 GENMASK(19, 14) +#define RG_HDMITX21_DRV_IBIAS_D1 GENMASK(25, 20) +#define RG_HDMITX21_DRV_IBIAS_D2 GENMASK(31, 26) + +#define HDMI_1_CFG_10 0x40 +#define RG_HDMITXPLL_REF_CK_SEL GENMASK(2, 1) +#define RG_HDMITX21_VREF_SEL BIT(4) +#define RG_HDMITX21_BIAS_PE_VREF_SELB BIT(10) +#define RG_HDMITX21_BIAS_PE_BG_VREF_SEL GENMASK(16, 15) +#define RG_HDMITX21_BG_PWD BIT(20) + +#define HDMI_1_CFG_2 0x08 +#define RG_HDMITX21_DRV_IMP_D0_EN1 GENMASK(13, 8) +#define RG_HDMITX21_DRV_IMP_D1_EN1 GENMASK(19, 14) +#define RG_HDMITX21_DRV_IMP_D2_EN1 GENMASK(25, 20) +#define RG_HDMITX21_DRV_IMP_CLK_EN1 GENMASK(31, 26) + +#define HDMI_1_CFG_3 0x0c +#define RG_HDMITX21_CKLDO_EN BIT(3) +#define RG_HDMITX21_SLDOLPF_EN BIT(7) +#define RG_HDMITX21_SLDO_EN GENMASK(11, 8) + +#define HDMI_1_CFG_6 0x18 +#define RG_HDMITX21_D2_DRV_OP_EN BIT(8) +#define RG_HDMITX21_D1_DRV_OP_EN BIT(9) +#define RG_HDMITX21_D0_DRV_OP_EN BIT(10) +#define RG_HDMITX21_CK_DRV_OP_EN BIT(11) +#define RG_HDMITX21_FRL_EN BIT(12) +#define RG_HDMITX21_FRL_CK_EN BIT(13) +#define RG_HDMITX21_FRL_D0_EN BIT(14) +#define RG_HDMITX21_FRL_D1_EN BIT(15) +#define RG_HDMITX21_FRL_D2_EN BIT(16) +#define RG_HDMITX21_INTR_CAL GENMASK(22, 18) +#define RG_HDMITX21_TX_POSDIV GENMASK(27, 26) +#define RG_HDMITX21_TX_POSDIV_EN BIT(28) +#define RG_HDMITX21_BIAS_EN BIT(29) + +#define HDMI_1_CFG_9 0x24 +#define RG_HDMITX21_SLDO_VREF_SEL GENMASK(5, 4) + +#define HDMI_1_PLL_CFG_0 0x44 +#define RG_HDMITXPLL_HREN GENMASK(13, 12) +#define RG_HDMITXPLL_IBAND_FIX_EN BIT(24) +#define RG_HDMITXPLL_LVR_SEL GENMASK(27, 26) +#define RG_HDMITXPLL_BP2 BIT(30) +#define RG_HDMITXPLL_TCL_EN BIT(31) + +#define HDMI_1_PLL_CFG_1 0x48 +#define RG_HDMITXPLL_RESERVE_BIT1_0 GENMASK(1, 0) +#define RG_HDMITXPLL_RESERVE_BIT3_2 GENMASK(3, 2) +#define RG_HDMITXPLL_RESERVE_BIT12_11 GENMASK(12, 11) +#define RG_HDMITXPLL_RESERVE_BIT13 BIT(13) +#define RG_HDMITXPLL_RESERVE_BIT14 BIT(14) + +#define HDMI_1_PLL_CFG_2 0x4c +#define RG_HDMITXPLL_BC GENMASK(28, 27) +#define RG_HDMITXPLL_IC GENMASK(26, 22) +#define RG_HDMITXPLL_BR GENMASK(21, 19) +#define RG_HDMITXPLL_IR GENMASK(18, 14) +#define RG_HDMITXPLL_BP GENMASK(13, 10) +#define RG_HDMITXPLL_HIKVCO BIT(29) +#define RG_HDMITXPLL_PWD BIT(31) + +#define HDMI_1_PLL_CFG_3 0x50 +#define RG_HDMITXPLL_FBKDIV_LOW GENMASK(31, 0) + +#define HDMI_1_PLL_CFG_4 0x54 +#define DA_HDMITXPLL_ISO_EN BIT(1) +#define DA_HDMITXPLL_PWR_ON BIT(2) +#define RG_HDMITXPLL_POSDIV_DIV3_CTRL BIT(21) +#define RG_HDMITXPLL_POSDIV GENMASK(23, 22) +#define RG_HDMITXPLL_DIV_CTRL GENMASK(25, 24) +#define RG_HDMITXPLL_PREDIV GENMASK(29, 28) +#define RG_HDMITXPLL_FBKDIV_HIGH BIT(31) + +#define HDMI_ANA_CTL 0x7c +#define REG_ANA_HDMI20_FIFO_EN BIT(16) + +#define HDMI_CTL_1 0xc4 +#define RG_HDMITX_PWR5V_O BIT(9) + +#define HDMI_CTL_3 0xcc +#define REG_HDMITXPLL_DIV GENMASK(4, 0) +#define REG_HDMITX_REF_XTAL_SEL BIT(7) +#define REG_HDMITX_REF_RESPLL_SEL BIT(9) +#define REG_PIXEL_CLOCK_SEL BIT(10) +#define REG_HDMITX_PIXEL_CLOCK BIT(23) + +#endif /* MTK_HDMI_PHY_8195_H */ diff --git a/drivers/phy/phy-mtk-hdmi.c b/drivers/phy/phy-mtk-hdmi.c new file mode 100644 index 00000000000..5be16fe3f43 --- /dev/null +++ b/drivers/phy/phy-mtk-hdmi.c @@ -0,0 +1,106 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) 2018 MediaTek Inc. + * Copyright (c) 2026 BayLibre, SAS + * Author: Jie Qiu + */ + +#include +#include + +#include "phy-mtk-hdmi.h" + +static int mtk_hdmi_phy_power_on(struct phy *phy) +{ + struct mtk_hdmi_phy *hdmi_phy = dev_get_priv(phy->dev); + int ret; + + /* + * The 5V output is a regulator in the Linux driver, controlled by the + * HDMI connector. U-Boot has no such consumer, so enable it here. + */ + if (hdmi_phy->conf->power_control) + hdmi_phy->conf->power_control(hdmi_phy, true); + + /* Equivalent of clk_prepare_enable() on the kernel PLL clock. */ + ret = hdmi_phy->conf->pll_prepare(hdmi_phy); + if (ret) + return ret; + + hdmi_phy->conf->hdmi_phy_enable_tmds(hdmi_phy); + + return 0; +} + +static int mtk_hdmi_phy_power_off(struct phy *phy) +{ + struct mtk_hdmi_phy *hdmi_phy = dev_get_priv(phy->dev); + + hdmi_phy->conf->hdmi_phy_disable_tmds(hdmi_phy); + hdmi_phy->conf->pll_unprepare(hdmi_phy); + + if (hdmi_phy->conf->power_control) + hdmi_phy->conf->power_control(hdmi_phy, false); + + return 0; +} + +static int mtk_hdmi_phy_configure(struct phy *phy, void *opts) +{ + struct mtk_hdmi_phy *hdmi_phy = dev_get_priv(phy->dev); + + if (hdmi_phy->conf->hdmi_phy_configure) + return hdmi_phy->conf->hdmi_phy_configure(phy, opts); + + return 0; +} + +static int mtk_hdmi_phy_probe(struct udevice *dev) +{ + struct mtk_hdmi_phy *hdmi_phy = dev_get_priv(dev); + int ret; + + hdmi_phy->dev = dev; + hdmi_phy->conf = + (const struct mtk_hdmi_phy_conf *)dev_get_driver_data(dev); + + hdmi_phy->regs = dev_read_addr_ptr(dev); + if (!hdmi_phy->regs) + return -EINVAL; + + ret = clk_get_by_name(dev, "pll_ref", &hdmi_phy->pll_ref); + if (ret) { + dev_err(dev, "Failed to get PLL reference clock: %d\n", ret); + return ret; + } + + ret = clk_enable(&hdmi_phy->pll_ref); + if (ret) { + dev_err(dev, "Failed to enable PLL reference clock: %d\n", ret); + return ret; + } + + return 0; +} + +static const struct phy_ops mtk_hdmi_phy_ops = { + .power_on = mtk_hdmi_phy_power_on, + .power_off = mtk_hdmi_phy_power_off, + .configure = mtk_hdmi_phy_configure, +}; + +static const struct udevice_id mtk_hdmi_phy_match[] = { + { .compatible = "mediatek,mt8195-hdmi-phy", + .data = (ulong)&mtk_hdmi_phy_8195_conf, + }, + { /* sentinel */ } +}; + +U_BOOT_DRIVER(mtk_hdmi_phy) = { + .name = "mtk-hdmi-phy", + .id = UCLASS_PHY, + .of_match = mtk_hdmi_phy_match, + .ops = &mtk_hdmi_phy_ops, + .probe = mtk_hdmi_phy_probe, + .priv_auto = sizeof(struct mtk_hdmi_phy), +}; diff --git a/drivers/phy/phy-mtk-hdmi.h b/drivers/phy/phy-mtk-hdmi.h new file mode 100644 index 00000000000..f5ebf33b5b4 --- /dev/null +++ b/drivers/phy/phy-mtk-hdmi.h @@ -0,0 +1,46 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (c) 2018 MediaTek Inc. + * Copyright (c) 2026 BayLibre, SAS + * Author: Chunhui Dai + */ + +#ifndef _MTK_HDMI_PHY_H +#define _MTK_HDMI_PHY_H + +#include +#include + +struct mtk_hdmi_phy; + +/* + * The Linux driver models the HDMI PLL as a clock provider (struct clk_hw / + * struct clk_ops) and the 5V output as a regulator. U-Boot has no consumer for + * either, so the PLL clk_ops are folded into the callbacks below (keeping the + * kernel prepare/unprepare/set_rate/determine_rate naming) and the 5V control + * is exposed as power_control(), driven directly from the PHY power ops. + */ +struct mtk_hdmi_phy_conf { + int (*pll_prepare)(struct mtk_hdmi_phy *hdmi_phy); + void (*pll_unprepare)(struct mtk_hdmi_phy *hdmi_phy); + int (*pll_set_rate)(struct mtk_hdmi_phy *hdmi_phy, unsigned long rate); + void (*pll_determine_rate)(struct mtk_hdmi_phy *hdmi_phy, + unsigned long rate); + void (*hdmi_phy_enable_tmds)(struct mtk_hdmi_phy *hdmi_phy); + void (*hdmi_phy_disable_tmds)(struct mtk_hdmi_phy *hdmi_phy); + int (*hdmi_phy_configure)(struct phy *phy, void *opts); + void (*power_control)(struct mtk_hdmi_phy *hdmi_phy, bool enable); +}; + +struct mtk_hdmi_phy { + struct udevice *dev; + void __iomem *regs; + const struct mtk_hdmi_phy_conf *conf; + struct clk pll_ref; + unsigned long pll_rate; + bool tmds_over_340M; +}; + +extern const struct mtk_hdmi_phy_conf mtk_hdmi_phy_8195_conf; + +#endif /* _MTK_HDMI_PHY_H */ diff --git a/drivers/phy/phy-mtk-io.h b/drivers/phy/phy-mtk-io.h new file mode 100644 index 00000000000..127cd705f17 --- /dev/null +++ b/drivers/phy/phy-mtk-io.h @@ -0,0 +1,46 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2021 MediaTek Inc. + * + * Author: Chunfeng Yun + */ + +#ifndef __PHY_MTK_H__ +#define __PHY_MTK_H__ + +#include +#include + +static inline void mtk_phy_clear_bits(void __iomem *reg, u32 bits) +{ + u32 tmp = readl(reg); + + tmp &= ~bits; + writel(tmp, reg); +} + +static inline void mtk_phy_set_bits(void __iomem *reg, u32 bits) +{ + u32 tmp = readl(reg); + + tmp |= bits; + writel(tmp, reg); +} + +static inline void mtk_phy_update_bits(void __iomem *reg, u32 mask, u32 val) +{ + u32 tmp = readl(reg); + + tmp &= ~mask; + tmp |= val & mask; + writel(tmp, reg); +} + +/* field @mask shall be constant and continuous */ +#define mtk_phy_update_field(reg, mask, val) \ +({ \ + BUILD_BUG_ON_MSG(!__builtin_constant_p(mask), "mask is not constant"); \ + mtk_phy_update_bits(reg, mask, FIELD_PREP(mask, val)); \ +}) + +#endif -- cgit v1.3.1 From 4a6f93a28daee8a01fc0c9f797a653e64d97c046 Mon Sep 17 00:00:00 2001 From: David Lechner Date: Fri, 31 Jul 2026 14:25:02 -0500 Subject: clk: mediatek: mt8189: add missing qualifiers Add a missing const and a missing static qualifier to a couple of lookup tables. Reviewed-by: Julien Stephan Link: https://patch.msgid.link/20260731-mtk-clk-mt8189-fix-missing-qualifiers-v1-1-92f3f0e44817@baylibre.com Signed-off-by: David Lechner --- drivers/clk/mediatek/clk-mt8189.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/clk/mediatek/clk-mt8189.c b/drivers/clk/mediatek/clk-mt8189.c index 15e040569e7..3724dffcc3a 100644 --- a/drivers/clk/mediatek/clk-mt8189.c +++ b/drivers/clk/mediatek/clk-mt8189.c @@ -291,7 +291,7 @@ enum { CLK_PAD_AUD_ADC_EXT, }; -static ulong ext_clock_rates[] = { +static const ulong ext_clock_rates[] = { [CLK_PAD_CLK32K] = 32000, [CLK_PAD_CLK26M] = 26 * MHZ, [CLK_PAD_ULPOSC] = 260 * MHZ, @@ -1124,7 +1124,7 @@ static const struct mtk_parent ecc_parents[] = { _mux_clr_ofs, _shift, _width, _gate, \ _upd_ofs, _upd, CLK_MUX_SETCLR_UPD) -const struct mtk_composite top_muxes[] = { +static const struct mtk_composite top_muxes[] = { /* CLK_CFG_0 */ MUX_CLR_SET_UPD(CLK_TOP_AXI_SEL, axi_parents, CLK_CFG_0, CLK_CFG_0_SET, CLK_CFG_0_CLR, 0, 3, CLK_CFG_UPDATE, TOP_MUX_AXI_SHIFT), -- cgit v1.3.1 From 81fdcc79c467ca42363091cab0e5dbb2282571d9 Mon Sep 17 00:00:00 2001 From: David Lechner Date: Fri, 31 Jul 2026 15:31:26 -0500 Subject: arm: mediatek: use phase-aware PSCI reset on MT8365 Change IS_ENABLED() to CONFIG_IS_ENABLED() to prepare for SPL support. PSCI is not available in the SPL stage and would cause a lock-up if called. Reviewed-by: Julien Stephan Link: https://patch.msgid.link/20260731-mtk-mach-phase-aware-reset-v1-1-90b918aa52f5@baylibre.com Signed-off-by: David Lechner --- arch/arm/mach-mediatek/mt8365/init.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/mach-mediatek/mt8365/init.c b/arch/arm/mach-mediatek/mt8365/init.c index 1063dbf72a9..0f990197a38 100644 --- a/arch/arm/mach-mediatek/mt8365/init.c +++ b/arch/arm/mach-mediatek/mt8365/init.c @@ -22,7 +22,7 @@ void reset_cpu(void) { struct udevice *wdt; - if (IS_ENABLED(CONFIG_PSCI_RESET)) { + if (CONFIG_IS_ENABLED(PSCI_RESET)) { psci_system_reset(); } else { uclass_first_device(UCLASS_WDT, &wdt); -- cgit v1.3.1 From 0bd564f4bbada6f10dc5aed31b09d58522ab3978 Mon Sep 17 00:00:00 2001 From: David Lechner Date: Fri, 31 Jul 2026 15:31:27 -0500 Subject: arm: mediatek: use phase-aware PSCI reset on MT8195 Change IS_ENABLED() to CONFIG_IS_ENABLED() to prepare for SPL support. PSCI is not available in the SPL stage and would cause a lock-up if called. Reviewed-by: Julien Stephan Link: https://patch.msgid.link/20260731-mtk-mach-phase-aware-reset-v1-2-90b918aa52f5@baylibre.com Signed-off-by: David Lechner --- arch/arm/mach-mediatek/mt8195/init.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/mach-mediatek/mt8195/init.c b/arch/arm/mach-mediatek/mt8195/init.c index 83cac9d01d6..6afb7330b4e 100644 --- a/arch/arm/mach-mediatek/mt8195/init.c +++ b/arch/arm/mach-mediatek/mt8195/init.c @@ -38,7 +38,7 @@ void reset_cpu(void) { struct udevice *wdt; - if (IS_ENABLED(CONFIG_PSCI_RESET)) { + if (CONFIG_IS_ENABLED(PSCI_RESET)) { psci_system_reset(); } else { uclass_first_device(UCLASS_WDT, &wdt); -- cgit v1.3.1 From 7979d7a6f129a91bc4372410e19ec0de008cfed5 Mon Sep 17 00:00:00 2001 From: David Lechner Date: Wed, 5 Aug 2026 14:20:34 -0500 Subject: phy: mtk-tphy: add v3 hardware support Add devicetree compatible and match data for "mediatek,generic-tphy-v3" in the MediaTek TPHY driver. According to the Linux driver implementation, the only difference between this and v2 is that v3 doesn't need to set slew rate. There is one register write in the U-Boot driver that gets skipped because of this now. Also, according to the upstream devicetree bindings, mt8195 is also v3 TPHY, so it gets updated as well. Reviewed-by: Julien Stephan Link: https://patch.msgid.link/20260805-mtk-tphy-v3-v1-1-f1d6268b8d89@baylibre.com Signed-off-by: David Lechner --- drivers/phy/phy-mtk-tphy.c | 19 +++++++++++++++---- 1 file changed, 15 insertions(+), 4 deletions(-) diff --git a/drivers/phy/phy-mtk-tphy.c b/drivers/phy/phy-mtk-tphy.c index 0a45dc58629..05172f220e6 100644 --- a/drivers/phy/phy-mtk-tphy.c +++ b/drivers/phy/phy-mtk-tphy.c @@ -228,6 +228,7 @@ enum mtk_phy_version { MTK_TPHY_V1 = 1, MTK_TPHY_V2, + MTK_TPHY_V3, }; struct tphy_pdata { @@ -331,9 +332,10 @@ static void u2_phy_instance_init(struct mtk_tphy *tphy, FIELD_PREP(PA6_RG_U2_SQTH, 2)); /* set HS slew rate */ - clrsetbits_le32(u2_banks->com + U3P_USBPHYACR5, - PA5_RG_U2_HSTX_SRCTRL, - FIELD_PREP(PA5_RG_U2_HSTX_SRCTRL, 4)); + if (tphy->pdata->version < MTK_TPHY_V3) + clrsetbits_le32(u2_banks->com + U3P_USBPHYACR5, + PA5_RG_U2_HSTX_SRCTRL, + FIELD_PREP(PA5_RG_U2_HSTX_SRCTRL, 4)); u2_phy_pll_26m_set(tphy, instance); @@ -813,6 +815,7 @@ static int mtk_phy_xlate(struct phy *phy, phy_v1_banks_init(tphy, instance); break; case MTK_TPHY_V2: + case MTK_TPHY_V3: phy_v2_banks_init(tphy, instance); break; default: @@ -900,8 +903,12 @@ static struct tphy_pdata tphy_v2_pdata = { .version = MTK_TPHY_V2, }; +static struct tphy_pdata tphy_v3_pdata = { + .version = MTK_TPHY_V3, +}; + static struct tphy_pdata mt8195_pdata = { - .version = MTK_TPHY_V2, + .version = MTK_TPHY_V3, .sw_pll_48m_to_26m = true, }; @@ -914,6 +921,10 @@ static const struct udevice_id mtk_tphy_id_table[] = { .compatible = "mediatek,generic-tphy-v2", .data = (ulong)&tphy_v2_pdata, }, + { + .compatible = "mediatek,generic-tphy-v3", + .data = (ulong)&tphy_v3_pdata, + }, { .compatible = "mediatek,mt8195-tphy", .data = (ulong)&mt8195_pdata, -- cgit v1.3.1 From 04845af8b08ea651359a4ff3137d59f3f2384794 Mon Sep 17 00:00:00 2001 From: David Lechner Date: Thu, 6 Aug 2026 11:14:59 -0500 Subject: net: dwc_eth_qos_mtk: support platform-specific PERI_ETH_BASE Add infrastructure to support future MediaTek platforms that have a different PERI_ETH_BASE address. There are at least 3 different known base address for this. Reviewed-by: Julien Stephan Link: https://patch.msgid.link/20260806-mtk-net-mt8366-support-v1-1-5eb259ff69dd@baylibre.com Signed-off-by: David Lechner --- drivers/net/dwc_eth_qos_mtk.c | 58 +++++++++++++++++++++++++++++++++++++------ 1 file changed, 50 insertions(+), 8 deletions(-) diff --git a/drivers/net/dwc_eth_qos_mtk.c b/drivers/net/dwc_eth_qos_mtk.c index 43e1085dfe5..a113870dc8a 100644 --- a/drivers/net/dwc_eth_qos_mtk.c +++ b/drivers/net/dwc_eth_qos_mtk.c @@ -18,9 +18,11 @@ * Peri Configuration register is SoC specific, * so add a SoC specific prefix. */ -#define MT8189_PERI_ETH_CTRL0 0x270 -#define MT8189_PERI_ETH_CTRL1 0x274 -#define MT8189_PERI_ETH_CTRL2 0x278 +#define MT8189_PERI_ETH_BASE 0x270 + +#define MTK_PERI_ETH_CTRL0(base) ((base) + 0x0) +#define MTK_PERI_ETH_CTRL1(base) ((base) + 0x4) +#define MTK_PERI_ETH_CTRL2(base) ((base) + 0x8) #define EQOS_MTK_RMII_CLK_SRC_INTERNAL BIT(28) #define EQOS_MTK_RMII_CLK_SRC_RXC BIT(27) @@ -55,6 +57,7 @@ struct eqos_mtk_priv { struct regmap *peri_regmap; + const struct eqos_mtk_soc_data *soc_data; bool rmii_clk_from_mac; bool rmii_rxc; u32 tx_delay_stage; @@ -63,6 +66,32 @@ struct eqos_mtk_priv { bool rx_inv; }; +struct eqos_mtk_soc_data { + const char *compatible; + u32 peri_eth_base; +}; + +static const struct eqos_mtk_soc_data eqos_mtk_soc_data[] = { + { + .compatible = "mediatek,mt8189-gmac", + .peri_eth_base = MT8189_PERI_ETH_BASE, + }, + { } +}; + +static const struct eqos_mtk_soc_data *eqos_mtk_get_soc_data(struct udevice *dev) +{ + const struct eqos_mtk_soc_data *data = eqos_mtk_soc_data; + + while (data->compatible) { + if (device_is_compatible(dev, data->compatible)) + return data; + data++; + } + + return NULL; +} + static int mtk_clk_init(struct udevice *dev) { struct eqos_priv *eqos = dev_get_priv(dev); @@ -87,6 +116,7 @@ static int mtk_set_delay(struct udevice *dev) { struct eth_pdata *pdata = dev_get_plat(dev); struct eqos_mtk_priv *mtk_pdata = pdata->priv_pdata; + u32 peri_eth_base = mtk_pdata->soc_data->peri_eth_base; u32 gtxc_delay_val = 0, delay_val = 0, rmii_delay_val = 0; switch (pdata->phy_interface) { @@ -176,15 +206,17 @@ static int mtk_set_delay(struct udevice *dev) } regmap_update_bits(mtk_pdata->peri_regmap, - MT8189_PERI_ETH_CTRL0, + MTK_PERI_ETH_CTRL0(peri_eth_base), EQOS_MTK_RGMII_TXC_PHASE_CTRL | EQOS_MTK_DLY_GTXC_ENABLE | EQOS_MTK_DLY_GTXC_INV | EQOS_MTK_DLY_GTXC_STAGE_FINE | EQOS_MTK_DLY_GTXC_STAGES, gtxc_delay_val); - regmap_write(mtk_pdata->peri_regmap, MT8189_PERI_ETH_CTRL1, delay_val); - regmap_write(mtk_pdata->peri_regmap, MT8189_PERI_ETH_CTRL2, rmii_delay_val); + regmap_write(mtk_pdata->peri_regmap, + MTK_PERI_ETH_CTRL1(peri_eth_base), delay_val); + regmap_write(mtk_pdata->peri_regmap, + MTK_PERI_ETH_CTRL2(peri_eth_base), rmii_delay_val); return 0; } @@ -195,6 +227,7 @@ static int mtk_set_interface(struct udevice *dev) struct eqos_mtk_priv *mtk_pdata = pdata->priv_pdata; int rmii_clk_from_mac = mtk_pdata->rmii_clk_from_mac ? EQOS_MTK_RMII_CLK_SRC_INTERNAL : 0; int rmii_rxc = mtk_pdata->rmii_rxc ? EQOS_MTK_RMII_CLK_SRC_RXC : 0; + u32 peri_eth_base = mtk_pdata->soc_data->peri_eth_base; u32 intf_val = 0; /* select phy interface in top control domain */ @@ -222,7 +255,8 @@ static int mtk_set_interface(struct udevice *dev) intf_val |= EQOS_MTK_TXC_OUT_OP; - regmap_write(mtk_pdata->peri_regmap, MT8189_PERI_ETH_CTRL0, intf_val); + regmap_write(mtk_pdata->peri_regmap, + MTK_PERI_ETH_CTRL0(peri_eth_base), intf_val); return 0; } @@ -290,6 +324,13 @@ static int eqos_probe_resources_mtk(struct udevice *dev) if (!mtk_pdata) return -ENOMEM; + mtk_pdata->soc_data = eqos_mtk_get_soc_data(dev); + if (!mtk_pdata->soc_data) { + dev_err(dev, "missing MTK SoC data\n"); + ret = -EINVAL; + goto err; + } + pdata->priv_pdata = mtk_pdata; ret = mtk_config_dt(dev); @@ -384,6 +425,7 @@ static int eqos_fix_mac_speed_mtk(struct udevice *dev) struct eqos_priv *eqos = dev_get_priv(dev); struct eth_pdata *pdata = dev_get_plat(dev); struct eqos_mtk_priv *mtk_pdata = pdata->priv_pdata; + u32 peri_eth_base = mtk_pdata->soc_data->peri_eth_base; debug("%s(dev=%p):\n", __func__, dev); @@ -394,7 +436,7 @@ static int eqos_fix_mac_speed_mtk(struct udevice *dev) case PHY_INTERFACE_MODE_RGMII_ID: if (eqos->phy->speed == SPEED_1000) regmap_update_bits(mtk_pdata->peri_regmap, - MT8189_PERI_ETH_CTRL0, + MTK_PERI_ETH_CTRL0(peri_eth_base), EQOS_MTK_RGMII_TXC_PHASE_CTRL | EQOS_MTK_DLY_GTXC_ENABLE | EQOS_MTK_DLY_GTXC_INV | -- cgit v1.3.1 From 66e793bc93738d32e9dd20bab37f5020724a4940 Mon Sep 17 00:00:00 2001 From: David Lechner Date: Thu, 6 Aug 2026 11:15:00 -0500 Subject: net: dwc_eth_qos_mtk: add mt8366 support Add a compatible string match and new PERI_ETH_BASE address for MT8366 targets. Reviewed-by: Julien Stephan Link: https://patch.msgid.link/20260806-mtk-net-mt8366-support-v1-2-5eb259ff69dd@baylibre.com Signed-off-by: David Lechner --- drivers/net/dwc_eth_qos_mtk.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/drivers/net/dwc_eth_qos_mtk.c b/drivers/net/dwc_eth_qos_mtk.c index a113870dc8a..b4ee9c12404 100644 --- a/drivers/net/dwc_eth_qos_mtk.c +++ b/drivers/net/dwc_eth_qos_mtk.c @@ -19,6 +19,7 @@ * so add a SoC specific prefix. */ #define MT8189_PERI_ETH_BASE 0x270 +#define MT8366_PERI_ETH_BASE 0x60 #define MTK_PERI_ETH_CTRL0(base) ((base) + 0x0) #define MTK_PERI_ETH_CTRL1(base) ((base) + 0x4) @@ -76,6 +77,10 @@ static const struct eqos_mtk_soc_data eqos_mtk_soc_data[] = { .compatible = "mediatek,mt8189-gmac", .peri_eth_base = MT8189_PERI_ETH_BASE, }, + { + .compatible = "mediatek,mt8366-gmac", + .peri_eth_base = MT8366_PERI_ETH_BASE, + }, { } }; -- cgit v1.3.1 From 34b86a6741e7cd7ec83c9926bd8a81ddb3206079 Mon Sep 17 00:00:00 2001 From: David Lechner Date: Thu, 6 Aug 2026 11:15:01 -0500 Subject: net: dwc_eth_qos: add mt8366 support Add a compatible string match for MT8366 targets. Reviewed-by: Julien Stephan Link: https://patch.msgid.link/20260806-mtk-net-mt8366-support-v1-3-5eb259ff69dd@baylibre.com Signed-off-by: David Lechner --- drivers/net/dwc_eth_qos.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/drivers/net/dwc_eth_qos.c b/drivers/net/dwc_eth_qos.c index e7cf68d011c..bf590421324 100644 --- a/drivers/net/dwc_eth_qos.c +++ b/drivers/net/dwc_eth_qos.c @@ -1664,6 +1664,10 @@ static const struct udevice_id eqos_ids[] = { .compatible = "mediatek,mt8189-gmac", .data = (ulong)&eqos_mtk_config }, + { + .compatible = "mediatek,mt8366-gmac", + .data = (ulong)&eqos_mtk_config + }, #endif #if IS_ENABLED(CONFIG_DWC_ETH_QOS_SUNXI) { -- cgit v1.3.1 From ca1cf823fa1e59039494d4eabb4d117abd4844a3 Mon Sep 17 00:00:00 2001 From: David Lechner Date: Thu, 6 Aug 2026 18:40:19 -0500 Subject: spi: mtk_snor: combine mt8188 and mt8189 into mediatek,mt8186-nor Replace "mediatek,mt8188-nor" and "mediatek,mt8189-nor" with "mediatek,mt8186-nor" in the mtk_snor driver. Both of these have "mediatek,mt8186-nor" as a fallback, so we can use that instead of adding each new compatible when we add more similar SoCs. Reviewed-by: Julien Stephan Link: https://patch.msgid.link/20260806-mtk-snor-fallback-compatible-v1-1-74559b491b4a@baylibre.com Signed-off-by: David Lechner --- drivers/spi/mtk_snor.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/drivers/spi/mtk_snor.c b/drivers/spi/mtk_snor.c index 40fc1826db6..95bd8f06eb9 100644 --- a/drivers/spi/mtk_snor.c +++ b/drivers/spi/mtk_snor.c @@ -607,8 +607,7 @@ static const struct mtk_snor_caps mtk_snor_caps_extra_bit = { static const struct udevice_id mtk_snor_ids[] = { { .compatible = "mediatek,mtk-snor", .data = (ulong)&mtk_snor_caps_default }, - { .compatible = "mediatek,mt8188-nor", .data = (ulong)&mtk_snor_caps_extra_bit }, - { .compatible = "mediatek,mt8189-nor", .data = (ulong)&mtk_snor_caps_extra_bit }, + { .compatible = "mediatek,mt8186-nor", .data = (ulong)&mtk_snor_caps_extra_bit }, { .compatible = "mediatek,mt8195-nor", .data = (ulong)&mtk_snor_caps_default }, {} }; -- cgit v1.3.1 From 669d102dd71235eba34160a0d560000949c188c8 Mon Sep 17 00:00:00 2001 From: David Lechner Date: Fri, 7 Aug 2026 11:01:28 -0500 Subject: power: regulator: add MT6358 driver with MT6366 support Add a new driver for MediaTek MT6366 PMIC regulators. The register layout is compatible with MT6358, so the driver itself is called "mt6358". Only support for MT6366 is added currently for use with the MediaTek Genio 360 EVK. Reviewed-by: Julien Stephan Link: https://patch.msgid.link/20260807-mtk-pmic-mt6366-v2-1-d9fdef581fb1@baylibre.com Signed-off-by: David Lechner --- drivers/power/regulator/Kconfig | 8 + drivers/power/regulator/Makefile | 1 + drivers/power/regulator/mt6358_regulator.c | 371 +++++++++++++++++++++++++++++ include/power/mt6358.h | 130 ++++++++++ 4 files changed, 510 insertions(+) create mode 100644 drivers/power/regulator/mt6358_regulator.c create mode 100644 include/power/mt6358.h diff --git a/drivers/power/regulator/Kconfig b/drivers/power/regulator/Kconfig index 00a25acfdf9..56f07931c3d 100644 --- a/drivers/power/regulator/Kconfig +++ b/drivers/power/regulator/Kconfig @@ -564,6 +564,14 @@ config DM_REGULATOR_MT6357 This driver supports the control of different power rails of device through regulator interface. +config DM_REGULATOR_MT6358 + bool "Enable driver for MediaTek MT6358-family PMIC regulators" + depends on DM_REGULATOR && DM_PMIC_MTK_PWRAP + help + Say y here to select this option to enable the power regulator path + used by MT6358-family PMICs, including the MT6366 rail model used on + MT8366 Genio 360. + config DM_REGULATOR_MT6359 bool "Enable driver for MediaTek MT6359 PMIC regulators" depends on DM_REGULATOR && DM_PMIC_MTK_PWRAP diff --git a/drivers/power/regulator/Makefile b/drivers/power/regulator/Makefile index a40c9d340d9..e17937f4c26 100644 --- a/drivers/power/regulator/Makefile +++ b/drivers/power/regulator/Makefile @@ -50,6 +50,7 @@ obj-$(CONFIG_DM_REGULATOR_TPS65219) += tps65219_regulator.o obj-$(CONFIG_REGULATOR_RZG2L_USBPHY) += rzg2l-usbphy-regulator.o obj-$(CONFIG_$(PHASE_)DM_REGULATOR_CPCAP) += cpcap_regulator.o obj-$(CONFIG_DM_REGULATOR_MT6357) += mt6357_regulator.o +obj-$(CONFIG_DM_REGULATOR_MT6358) += mt6358_regulator.o obj-$(CONFIG_DM_REGULATOR_MT6359) += mt6359_regulator.o obj-$(CONFIG_DM_REGULATOR_PMBUS_HELPER) += pmbus_helper.o obj-$(CONFIG_DM_REGULATOR_PMBUS_GENERIC) += pmbus_generic.o diff --git a/drivers/power/regulator/mt6358_regulator.c b/drivers/power/regulator/mt6358_regulator.c new file mode 100644 index 00000000000..00e714c9338 --- /dev/null +++ b/drivers/power/regulator/mt6358_regulator.c @@ -0,0 +1,371 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (C) 2026 MediaTek Inc. + * + * MediaTek MT6358-family regulator driver used for MT6366 rails. + */ + +#include +#include +#include +#include +#include +#include +#include + +enum mt6358_regulator_type { + MT6358_REG_TYPE_LINEAR, + MT6358_REG_TYPE_TABLE, + MT6358_REG_TYPE_FIXED, +}; + +struct mt6358_regulator_desc { + const char *name; + const char *of_match; + enum mt6358_regulator_type type; + int id; + unsigned int uV_step; + unsigned int n_voltages; + const unsigned int *volt_table; + unsigned int min_uV; + unsigned int vsel_reg; + unsigned int vsel_mask; + unsigned int enable_reg; + unsigned int enable_mask; + unsigned int fixed_uV; +}; + +struct mt6358_regulator_info { + struct mt6358_regulator_desc desc; + const u32 *index_table; + unsigned int n_table; + u32 da_vsel_reg; + u32 da_vsel_mask; +}; + +#define MT6366_BUCK(match, _name, _min, _max, _step, _enable_reg, _vsel_reg, \ + _vsel_mask, _da_vsel_reg, _da_vsel_mask) \ + [MT6366_ID_##_name] = { \ + .desc = { \ + .name = #_name, \ + .of_match = match, \ + .type = MT6358_REG_TYPE_LINEAR, \ + .id = MT6366_ID_##_name, \ + .uV_step = (_step), \ + .n_voltages = ((_max) - (_min)) / (_step) + 1, \ + .min_uV = (_min), \ + .vsel_reg = (_vsel_reg), \ + .vsel_mask = (_vsel_mask), \ + .enable_reg = (_enable_reg), \ + .enable_mask = BIT(0), \ + }, \ + .da_vsel_reg = (_da_vsel_reg), \ + .da_vsel_mask = (_da_vsel_mask), \ + } + +#define MT6366_LDO(match, _name, _volt_table, _index_table, _enable_reg, \ + _vsel_reg, _vsel_mask) \ + [MT6366_ID_##_name] = { \ + .desc = { \ + .name = #_name, \ + .of_match = match, \ + .type = MT6358_REG_TYPE_TABLE, \ + .id = MT6366_ID_##_name, \ + .n_voltages = ARRAY_SIZE(_volt_table), \ + .volt_table = (_volt_table), \ + .vsel_reg = (_vsel_reg), \ + .vsel_mask = (_vsel_mask), \ + .enable_reg = (_enable_reg), \ + .enable_mask = BIT(0), \ + }, \ + .index_table = (_index_table), \ + .n_table = ARRAY_SIZE(_index_table), \ + } + +#define MT6366_LDO1(match, _name, _min, _max, _step, _enable_reg, _vsel_reg, \ + _vsel_mask, _da_vsel_reg, _da_vsel_mask) \ + [MT6366_ID_##_name] = { \ + .desc = { \ + .name = #_name, \ + .of_match = match, \ + .type = MT6358_REG_TYPE_LINEAR, \ + .id = MT6366_ID_##_name, \ + .uV_step = (_step), \ + .n_voltages = ((_max) - (_min)) / (_step) + 1, \ + .min_uV = (_min), \ + .vsel_reg = (_vsel_reg), \ + .vsel_mask = (_vsel_mask), \ + .enable_reg = (_enable_reg), \ + .enable_mask = BIT(0), \ + }, \ + .da_vsel_reg = (_da_vsel_reg), \ + .da_vsel_mask = (_da_vsel_mask), \ + } + +#define MT6366_REG_FIXED(match, _name, _enable_reg, _fixed_uV) \ + [MT6366_ID_##_name] = { \ + .desc = { \ + .name = #_name, \ + .of_match = match, \ + .type = MT6358_REG_TYPE_FIXED, \ + .id = MT6366_ID_##_name, \ + .n_voltages = 1, \ + .enable_reg = (_enable_reg), \ + .enable_mask = BIT(0), \ + .fixed_uV = (_fixed_uV), \ + }, \ + } + +static const unsigned int vdram2_voltages[] = { + 600000, 1800000 +}; + +static const unsigned int vsim_voltages[] = { + 1700000, 1800000, 2700000, 3000000, 3100000 +}; + +static const unsigned int vibr_voltages[] = { + 1200000, 1300000, 1500000, 1800000, 2000000, 2800000, 3000000, 3300000 +}; + +static const unsigned int vusb_voltages[] = { + 3000000, 3100000 +}; + +static const unsigned int vefuse_voltages[] = { + 1700000, 1800000, 1900000 +}; + +static const unsigned int vmch_vemc_voltages[] = { + 2900000, 3000000, 3300000 +}; + +static const unsigned int vcn33_voltages[] = { + 3300000, 3400000, 3500000 +}; + +static const unsigned int vmc_voltages[] = { + 1800000, 2900000, 3000000, 3300000 +}; + +static const u32 vdram2_idx[] = { 0, 12 }; +static const u32 vsim_idx[] = { 3, 4, 8, 11, 12 }; +static const u32 vibr_idx[] = { 0, 1, 2, 4, 5, 9, 11, 13 }; +static const u32 vusb_idx[] = { 3, 4 }; +static const u32 vefuse_idx[] = { 11, 12, 13 }; +static const u32 vmch_vemc_idx[] = { 2, 3, 5 }; +static const u32 vcn33_idx[] = { 1, 2, 3 }; +static const u32 vmc_idx[] = { 4, 10, 11, 13 }; + +static int mt6358_set_voltage_sel_regmap(struct udevice *dev, + struct mt6358_regulator_info *info, + unsigned int sel) +{ + return pmic_clrsetbits(dev->parent, info->desc.vsel_reg, + info->desc.vsel_mask, + field_prep(info->desc.vsel_mask, sel)); +} + +static int mt6358_get_voltage_sel(struct udevice *dev, + struct mt6358_regulator_info *info) +{ + int ret; + + ret = pmic_reg_read(dev->parent, info->desc.vsel_reg); + if (ret < 0) + return ret; + + return field_get(info->desc.vsel_mask, ret); +} + +static int mt6358_get_enable(struct udevice *dev) +{ + struct mt6358_regulator_info *info = dev_get_priv(dev); + int ret; + + ret = pmic_reg_read(dev->parent, info->desc.enable_reg); + if (ret < 0) + return ret; + + return field_get(info->desc.enable_mask, ret) ? true : false; +} + +static int mt6358_set_enable(struct udevice *dev, bool enable) +{ + struct mt6358_regulator_info *info = dev_get_priv(dev); + + return pmic_clrsetbits(dev->parent, info->desc.enable_reg, + info->desc.enable_mask, + field_prep(info->desc.enable_mask, enable)); +} + +static int mt6358_get_value(struct udevice *dev) +{ + struct mt6358_regulator_info *info = dev_get_priv(dev); + int ret, idx; + u32 selector; + + switch (info->desc.type) { + case MT6358_REG_TYPE_LINEAR: + ret = pmic_reg_read(dev->parent, info->da_vsel_reg); + if (ret < 0) + return ret; + + selector = field_get(info->da_vsel_mask, ret); + if (selector >= info->desc.n_voltages) + return -EINVAL; + + return info->desc.min_uV + (info->desc.uV_step * selector); + case MT6358_REG_TYPE_TABLE: + ret = mt6358_get_voltage_sel(dev, info); + if (ret < 0) + return ret; + + selector = ret; + + for (idx = 0; idx < info->n_table; idx++) { + if (info->index_table[idx] == selector) + return info->desc.volt_table[idx]; + } + + return -EINVAL; + case MT6358_REG_TYPE_FIXED: + return info->desc.fixed_uV; + default: + return -EINVAL; + } +} + +static int mt6358_set_value(struct udevice *dev, int uvolt) +{ + struct mt6358_regulator_info *info = dev_get_priv(dev); + u32 selector; + int idx; + + switch (info->desc.type) { + case MT6358_REG_TYPE_LINEAR: + if (uvolt < (int)info->desc.min_uV) + return -EINVAL; + + selector = DIV_ROUND_UP(uvolt - info->desc.min_uV, + info->desc.uV_step); + if (selector >= info->desc.n_voltages) + return -EINVAL; + + return mt6358_set_voltage_sel_regmap(dev, info, selector); + case MT6358_REG_TYPE_TABLE: + for (idx = 0; idx < info->desc.n_voltages; idx++) { + if (info->desc.volt_table[idx] == (u32)uvolt) + return mt6358_set_voltage_sel_regmap(dev, info, + info->index_table[idx]); + } + + return -EINVAL; + default: + return -EINVAL; + } +} + +static const struct mt6358_regulator_info mt6366_regulators[] = { + MT6366_BUCK("vdram1", VDRAM1, 500000, 2087500, 12500, + MT6358_BUCK_VDRAM1_CON0, MT6358_BUCK_VDRAM1_ELR0, GENMASK(6, 0), + MT6358_BUCK_VDRAM1_DBG0, GENMASK(6, 0)), + MT6366_BUCK("vcore", VCORE, 500000, 1293750, 6250, + MT6358_BUCK_VCORE_CON0, MT6358_BUCK_VCORE_ELR0, GENMASK(6, 0), + MT6358_BUCK_VCORE_DBG0, GENMASK(6, 0)), + MT6366_BUCK("vpa", VPA, 500000, 3650000, 50000, + MT6358_BUCK_VPA_CON0, MT6358_BUCK_VPA_CON1, GENMASK(5, 0), + MT6358_BUCK_VPA_DBG0, GENMASK(5, 0)), + MT6366_BUCK("vproc11", VPROC11, 500000, 1293750, 6250, + MT6358_BUCK_VPROC11_CON0, MT6358_BUCK_VPROC11_ELR0, GENMASK(6, 0), + MT6358_BUCK_VPROC11_DBG0, GENMASK(6, 0)), + MT6366_BUCK("vproc12", VPROC12, 500000, 1293750, 6250, + MT6358_BUCK_VPROC12_CON0, MT6358_BUCK_VPROC12_ELR0, GENMASK(6, 0), + MT6358_BUCK_VPROC12_DBG0, GENMASK(6, 0)), + MT6366_BUCK("vgpu", VGPU, 500000, 1293750, 6250, + MT6358_BUCK_VGPU_CON0, MT6358_BUCK_VGPU_ELR0, GENMASK(6, 0), + MT6358_BUCK_VGPU_ELR0, GENMASK(6, 0)), + MT6366_BUCK("vs2", VS2, 500000, 2087500, 12500, + MT6358_BUCK_VS2_CON0, MT6358_BUCK_VS2_ELR0, GENMASK(6, 0), + MT6358_BUCK_VS2_DBG0, GENMASK(6, 0)), + MT6366_BUCK("vmodem", VMODEM, 500000, 1293750, 6250, + MT6358_BUCK_VMODEM_CON0, MT6358_BUCK_VMODEM_ELR0, GENMASK(6, 0), + MT6358_BUCK_VMODEM_DBG0, GENMASK(6, 0)), + MT6366_BUCK("vs1", VS1, 1000000, 2587500, 12500, + MT6358_BUCK_VS1_CON0, MT6358_BUCK_VS1_ELR0, GENMASK(6, 0), + MT6358_BUCK_VS1_DBG0, GENMASK(6, 0)), + MT6366_REG_FIXED("vrf12", VRF12, MT6358_LDO_VRF12_CON0, 1200000), + MT6366_REG_FIXED("vio18", VIO18, MT6358_LDO_VIO18_CON0, 1800000), + MT6366_REG_FIXED("vcn18", VCN18, MT6358_LDO_VCN18_CON0, 1800000), + MT6366_REG_FIXED("vfe28", VFE28, MT6358_LDO_VFE28_CON0, 2800000), + MT6366_REG_FIXED("vcn28", VCN28, MT6358_LDO_VCN28_CON0, 2800000), + MT6366_REG_FIXED("vxo22", VXO22, MT6358_LDO_VXO22_CON0, 2200000), + MT6366_REG_FIXED("vaux18", VAUX18, MT6358_LDO_VAUX18_CON0, 1800000), + MT6366_REG_FIXED("vbif28", VBIF28, MT6358_LDO_VBIF28_CON0, 2800000), + MT6366_REG_FIXED("vio28", VIO28, MT6358_LDO_VIO28_CON0, 2800000), + MT6366_REG_FIXED("va12", VA12, MT6358_LDO_VA12_CON0, 1200000), + MT6366_REG_FIXED("vrf18", VRF18, MT6358_LDO_VRF18_CON0, 1800000), + MT6366_REG_FIXED("vaud28", VAUD28, MT6358_LDO_VAUD28_CON0, 2800000), + MT6366_LDO("vdram2", VDRAM2, vdram2_voltages, vdram2_idx, + MT6358_LDO_VDRAM2_CON0, MT6358_LDO_VDRAM2_ELR0, GENMASK(3, 0)), + MT6366_LDO("vsim1", VSIM1, vsim_voltages, vsim_idx, + MT6358_LDO_VSIM1_CON0, MT6358_VSIM1_ANA_CON0, GENMASK(11, 8)), + MT6366_LDO("vibr", VIBR, vibr_voltages, vibr_idx, + MT6358_LDO_VIBR_CON0, MT6358_VIBR_ANA_CON0, GENMASK(11, 8)), + MT6366_LDO("vusb", VUSB, vusb_voltages, vusb_idx, + MT6358_LDO_VUSB_CON0_0, MT6358_VUSB_ANA_CON0, GENMASK(10, 8)), + MT6366_LDO("vefuse", VEFUSE, vefuse_voltages, vefuse_idx, + MT6358_LDO_VEFUSE_CON0, MT6358_VEFUSE_ANA_CON0, GENMASK(11, 8)), + MT6366_LDO("vmch", VMCH, vmch_vemc_voltages, vmch_vemc_idx, + MT6358_LDO_VMCH_CON0, MT6358_VMCH_ANA_CON0, GENMASK(10, 8)), + MT6366_LDO("vemc", VEMC, vmch_vemc_voltages, vmch_vemc_idx, + MT6358_LDO_VEMC_CON0, MT6358_VEMC_ANA_CON0, GENMASK(10, 8)), + MT6366_LDO("vcn33", VCN33, vcn33_voltages, vcn33_idx, + MT6358_LDO_VCN33_CON0_0, MT6358_VCN33_ANA_CON0, GENMASK(9, 8)), + MT6366_LDO("vmc", VMC, vmc_voltages, vmc_idx, + MT6358_LDO_VMC_CON0, MT6358_VMC_ANA_CON0, GENMASK(11, 8)), + MT6366_LDO("vsim2", VSIM2, vsim_voltages, vsim_idx, + MT6358_LDO_VSIM2_CON0, MT6358_VSIM2_ANA_CON0, GENMASK(11, 8)), + MT6366_LDO1("vsram-proc11", VSRAM_PROC11, 500000, 1293750, 6250, + MT6358_LDO_VSRAM_PROC11_CON0, MT6358_LDO_VSRAM_CON0, + GENMASK(6, 0), MT6358_LDO_VSRAM_PROC11_DBG0, GENMASK(14, 8)), + MT6366_LDO1("vsram-others", VSRAM_OTHERS, 500000, 1293750, 6250, + MT6358_LDO_VSRAM_OTHERS_CON0, MT6358_LDO_VSRAM_CON2, + GENMASK(6, 0), MT6358_LDO_VSRAM_OTHERS_DBG0, GENMASK(14, 8)), + MT6366_LDO1("vsram-gpu", VSRAM_GPU, 500000, 1293750, 6250, + MT6358_LDO_VSRAM_GPU_CON0, MT6358_LDO_VSRAM_CON3, + GENMASK(6, 0), MT6358_LDO_VSRAM_GPU_DBG0, GENMASK(14, 8)), + MT6366_LDO1("vsram-proc12", VSRAM_PROC12, 500000, 1293750, 6250, + MT6358_LDO_VSRAM_PROC12_CON0, MT6358_LDO_VSRAM_CON1, + GENMASK(6, 0), MT6358_LDO_VSRAM_PROC12_DBG0, GENMASK(14, 8)), +}; + +static int mt6358_regulator_probe(struct udevice *dev) +{ + struct mt6358_regulator_info *priv = dev_get_priv(dev); + int i; + + for (i = 0; i < ARRAY_SIZE(mt6366_regulators); i++) { + if (!strcmp(dev->name, mt6366_regulators[i].desc.of_match)) { + *priv = mt6366_regulators[i]; + return 0; + } + } + + return -ENOENT; +} + +static const struct dm_regulator_ops mt6358_regulator_ops = { + .get_value = mt6358_get_value, + .set_value = mt6358_set_value, + .get_enable = mt6358_get_enable, + .set_enable = mt6358_set_enable, +}; + +U_BOOT_DRIVER(mt6358_regulator) = { + .name = MT6358_REGULATOR_DRIVER, + .id = UCLASS_REGULATOR, + .ops = &mt6358_regulator_ops, + .probe = mt6358_regulator_probe, + .priv_auto = sizeof(struct mt6358_regulator_info), +}; diff --git a/include/power/mt6358.h b/include/power/mt6358.h new file mode 100644 index 00000000000..7621ad6f951 --- /dev/null +++ b/include/power/mt6358.h @@ -0,0 +1,130 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (C) 2026 MediaTek Inc. + */ + +#ifndef __MT6358_H_ +#define __MT6358_H_ + +#define MT6358_REGULATOR_DRIVER "mt6358_regulator" + +enum { + MT6366_ID_VDRAM1 = 0, + MT6366_ID_VCORE, + MT6366_ID_VPA, + MT6366_ID_VPROC11, + MT6366_ID_VPROC12, + MT6366_ID_VGPU, + MT6366_ID_VS2, + MT6366_ID_VMODEM, + MT6366_ID_VS1, + MT6366_ID_VDRAM2, + MT6366_ID_VSIM1, + MT6366_ID_VIBR, + MT6366_ID_VRF12, + MT6366_ID_VIO18, + MT6366_ID_VUSB, + MT6366_ID_VCN18, + MT6366_ID_VFE28, + MT6366_ID_VSRAM_PROC11, + MT6366_ID_VCN28, + MT6366_ID_VSRAM_OTHERS, + MT6366_ID_VSRAM_GPU, + MT6366_ID_VXO22, + MT6366_ID_VEFUSE, + MT6366_ID_VAUX18, + MT6366_ID_VMCH, + MT6366_ID_VBIF28, + MT6366_ID_VSRAM_PROC12, + MT6366_ID_VEMC, + MT6366_ID_VIO28, + MT6366_ID_VA12, + MT6366_ID_VRF18, + MT6366_ID_VCN33, + MT6366_ID_VMC, + MT6366_ID_VAUD28, + MT6366_ID_VSIM2, + MT6366_ID_RG_MAX, +}; + +#define MT6358_BUCK_VPROC11_CON0 0x1388 +#define MT6358_BUCK_VPROC11_DBG0 0x139e +#define MT6358_BUCK_VPROC11_ELR0 0x13a6 +#define MT6358_BUCK_VPROC12_CON0 0x1408 +#define MT6358_BUCK_VPROC12_DBG0 0x141e +#define MT6358_BUCK_VPROC12_ELR0 0x1426 +#define MT6358_BUCK_VCORE_CON0 0x1488 +#define MT6358_BUCK_VCORE_DBG0 0x149e +#define MT6358_BUCK_VCORE_ELR0 0x14aa +#define MT6358_BUCK_VGPU_CON0 0x1508 +#define MT6358_BUCK_VGPU_ELR0 0x1526 +#define MT6358_BUCK_VMODEM_CON0 0x1588 +#define MT6358_BUCK_VMODEM_DBG0 0x159e +#define MT6358_BUCK_VMODEM_ELR0 0x15a6 +#define MT6358_BUCK_VDRAM1_CON0 0x1608 +#define MT6358_BUCK_VDRAM1_DBG0 0x161e +#define MT6358_BUCK_VDRAM1_ELR0 0x1626 +#define MT6358_BUCK_VS1_CON0 0x1688 +#define MT6358_BUCK_VS1_DBG0 0x169e +#define MT6358_BUCK_VS1_ELR0 0x16ae +#define MT6358_BUCK_VS2_CON0 0x1708 +#define MT6358_BUCK_VS2_DBG0 0x171e +#define MT6358_BUCK_VS2_ELR0 0x172e +#define MT6358_BUCK_VPA_CON0 0x1788 +#define MT6358_BUCK_VPA_CON1 0x178a +#define MT6358_BUCK_VPA_DBG0 0x1792 + +#define MT6358_LDO_VXO22_CON0 0x1a88 +#define MT6358_LDO_VA12_CON0 0x1a9c +#define MT6358_LDO_VAUX18_CON0 0x1ab0 +#define MT6358_LDO_VAUD28_CON0 0x1ac4 +#define MT6358_LDO_VIO28_CON0 0x1ad8 +#define MT6358_LDO_VIO18_CON0 0x1aec +#define MT6358_LDO_VDRAM2_CON0 0x1b08 +#define MT6358_LDO_VDRAM2_ELR0 0x1b78 +#define MT6358_LDO_VEMC_CON0 0x1b1c +#define MT6358_LDO_VUSB_CON0_0 0x1b30 +#define MT6358_LDO_VSRAM_PROC11_CON0 0x1b46 +#define MT6358_LDO_VSRAM_PROC11_DBG0 0x1b60 +#define MT6358_LDO_VSRAM_PROC12_CON0 0x1b88 +#define MT6358_LDO_VSRAM_PROC12_DBG0 0x1ba2 +#define MT6358_LDO_VSRAM_OTHERS_CON0 0x1ba6 +#define MT6358_LDO_VSRAM_OTHERS_DBG0 0x1bc0 +#define MT6358_LDO_VSRAM_GPU_CON0 0x1bc8 +#define MT6358_LDO_VSRAM_GPU_DBG0 0x1be2 +#define MT6358_LDO_VSRAM_CON0 0x1bee +#define MT6358_LDO_VSRAM_CON1 0x1bf0 +#define MT6358_LDO_VSRAM_CON2 0x1bf2 +#define MT6358_LDO_VSRAM_CON3 0x1bf4 +#define MT6358_LDO_VFE28_CON0 0x1c08 +#define MT6358_LDO_VRF18_CON0 0x1c1c +#define MT6358_LDO_VRF12_CON0 0x1c30 +#define MT6358_LDO_VEFUSE_CON0 0x1c44 +#define MT6358_LDO_VCN18_CON0 0x1c58 +#define MT6358_LDO_VMC_CON0 0x1cc4 +#define MT6358_LDO_VMCH_CON0 0x1cd8 +#define MT6358_LDO_VIBR_CON0 0x1d08 +#define MT6358_LDO_VCN33_CON0_0 0x1d1c +#define MT6358_LDO_VSIM1_CON0 0x1d48 +#define MT6358_LDO_VSIM2_CON0 0x1d5c +#define MT6358_LDO_VCN28_CON0 0x1d88 +#define MT6358_LDO_VBIF28_CON0 0x1d9e + +#define MT6358_VSIM1_ANA_CON0 0x1e2c +#define MT6358_VSIM2_ANA_CON0 0x1e30 +#define MT6358_VUSB_ANA_CON0 0x1e34 +#define MT6358_VEMC_ANA_CON0 0x1e38 +#define MT6358_VIO28_ANA_CON0 0x1e40 +#define MT6358_VIBR_ANA_CON0 0x1e44 +#define MT6358_VMCH_ANA_CON0 0x1e48 +#define MT6358_VMC_ANA_CON0 0x1e4c +#define MT6358_VRF18_ANA_CON0 0x1e88 +#define MT6358_VCN18_ANA_CON0 0x1e8c +#define MT6358_VIO18_ANA_CON0 0x1e94 +#define MT6358_VEFUSE_ANA_CON0 0x1e98 +#define MT6358_VRF12_ANA_CON0 0x1e9c +#define MT6358_VDRAM2_ANA_CON0 0x1eaa +#define MT6358_VA12_ANA_CON0 0x1eb2 +#define MT6358_VCN33_ANA_CON0 0x1e28 + +#endif -- cgit v1.3.1 From 8362d7784d24b3b9e80f3bc22ac1308f1c802f79 Mon Sep 17 00:00:00 2001 From: David Lechner Date: Fri, 7 Aug 2026 11:01:29 -0500 Subject: power: pmic: mtk-pwrap: fix clock names Change clock names to match the upstream devicetree bindings. There are no known devicetrees using these wrong names. Fixes: 219c05f3f68e ("power: pmic: mtk-pwrap: add MediaTek PMIC Wrapper driver") Reviewed-by: Julien Stephan Link: https://patch.msgid.link/20260807-mtk-pmic-mt6366-v2-2-d9fdef581fb1@baylibre.com Signed-off-by: David Lechner --- drivers/power/pmic/mtk-pwrap.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/power/pmic/mtk-pwrap.c b/drivers/power/pmic/mtk-pwrap.c index 47347785519..f648a784019 100644 --- a/drivers/power/pmic/mtk-pwrap.c +++ b/drivers/power/pmic/mtk-pwrap.c @@ -720,8 +720,8 @@ static int mtk_pwrap_probe(struct udevice *dev) if (IS_ERR(wrp->clk_wrap)) return PTR_ERR(wrp->clk_wrap); - wrp->clk_wrap_sys = devm_clk_get_optional(dev, "wrap_sys"); - wrp->clk_wrap_tmr = devm_clk_get_optional(dev, "wrap_tmr"); + wrp->clk_wrap_sys = devm_clk_get_optional(dev, "sys"); + wrp->clk_wrap_tmr = devm_clk_get_optional(dev, "tmr"); ret = clk_enable(wrp->clk_spi); if (ret) -- cgit v1.3.1 From b237f66ab0500bc82c41fd687c77b91dc1f76bfa Mon Sep 17 00:00:00 2001 From: David Lechner Date: Fri, 7 Aug 2026 11:01:30 -0500 Subject: power: pmic: mtk-pwrap: use mt8195 fallback for mt8188/9 Remove the duplicated info for mt8188 and mt8189 platforms in the MediaTek PMIC wrapper driver. These both have a devicetree fallback to mt8195. There are no differences relevant to U-Boot, so we can avoid the duplication. Reviewed-by: Julien Stephan Link: https://patch.msgid.link/20260807-mtk-pmic-mt6366-v2-3-d9fdef581fb1@baylibre.com Signed-off-by: David Lechner --- drivers/power/pmic/mtk-pwrap.c | 46 ------------------------------------------ 1 file changed, 46 deletions(-) diff --git a/drivers/power/pmic/mtk-pwrap.c b/drivers/power/pmic/mtk-pwrap.c index f648a784019..3320e3cfdc0 100644 --- a/drivers/power/pmic/mtk-pwrap.c +++ b/drivers/power/pmic/mtk-pwrap.c @@ -250,34 +250,6 @@ enum pwrap_regs { PWRAP_WDT_SRC_EN_1, }; -static int mt8188_regs[] = { - [PWRAP_INIT_DONE2] = 0x0, - [PWRAP_STAUPD_CTRL] = 0x4C, - [PWRAP_TIMER_EN] = 0x3E4, - [PWRAP_INT_EN] = 0x420, - [PWRAP_INT_FLG] = 0x428, - [PWRAP_INT_CLR] = 0x42C, - [PWRAP_INT1_EN] = 0x450, - [PWRAP_INT1_FLG] = 0x458, - [PWRAP_INT1_CLR] = 0x45C, - [PWRAP_WACS2_CMD] = 0x880, - [PWRAP_SWINF_2_WDATA_31_0] = 0x884, - [PWRAP_SWINF_2_RDATA_31_0] = 0x894, - [PWRAP_WACS2_VLDCLR] = 0x8A4, - [PWRAP_WACS2_RDATA] = 0x8A8, -}; - -static int mt8189_regs[] = { - [PWRAP_INIT_DONE2] = 0x0, - [PWRAP_TIMER_EN] = 0x3E4, - [PWRAP_INT_EN] = 0x450, - [PWRAP_WACS2_CMD] = 0x880, - [PWRAP_SWINF_2_WDATA_31_0] = 0x884, - [PWRAP_SWINF_2_RDATA_31_0] = 0x894, - [PWRAP_WACS2_VLDCLR] = 0x8A4, - [PWRAP_WACS2_RDATA] = 0x8A8, -}; - static int mt8195_regs[] = { [PWRAP_INIT_DONE2] = 0x0, [PWRAP_STAUPD_CTRL] = 0x4C, @@ -849,22 +821,6 @@ static struct dm_pmic_ops mtk_pwrap_ops = { .write = mtk_pwrap_write, }; -static struct pmic_wrapper_type pwrap_mt8188 = { - .regs = mt8188_regs, - .arb_en_all = 0x777f, - .spi_w = PWRAP_MAN_CMD_SPI_WRITE, - .wdt_src = PWRAP_WDT_SRC_MASK_ALL, - .caps = PWRAP_CAP_ARB, -}; - -static struct pmic_wrapper_type pwrap_mt8189 = { - .regs = mt8189_regs, - .arb_en_all = 0x777f, - .spi_w = PWRAP_MAN_CMD_SPI_WRITE, - .wdt_src = PWRAP_WDT_SRC_MASK_ALL, - .caps = PWRAP_CAP_ARB, -}; - static const struct pmic_wrapper_type pwrap_mt8195 = { .regs = mt8195_regs, .arb_en_all = 0x777f, /* NEED CONFIRM */ @@ -882,8 +838,6 @@ static const struct pmic_wrapper_type pwrap_mt8365 = { }; static const struct udevice_id mtk_pwrap_ids[] = { - { .compatible = "mediatek,mt8188-pwrap", .data = (ulong)&pwrap_mt8188 }, - { .compatible = "mediatek,mt8189-pwrap", .data = (ulong)&pwrap_mt8189 }, { .compatible = "mediatek,mt8195-pwrap", .data = (ulong)&pwrap_mt8195 }, { .compatible = "mediatek,mt8365-pwrap", .data = (ulong)&pwrap_mt8365 }, { } -- cgit v1.3.1 From a5f55ef454996de9e0f5aefac866726c328d9be5 Mon Sep 17 00:00:00 2001 From: David Lechner Date: Fri, 7 Aug 2026 11:01:31 -0500 Subject: power: pmic: mtk-pwrap: add mt6358 PMIC Add support for MT6358 compatible PMICs to the MediaTek PMIC wrapper driver. This has a different register map compared to other already supported PMICs. It will be used initially for Genio 360 EVK support. Reviewed-by: Julien Stephan Link: https://patch.msgid.link/20260807-mtk-pmic-mt6366-v2-4-d9fdef581fb1@baylibre.com Signed-off-by: David Lechner --- drivers/power/pmic/mtk-pwrap.c | 47 ++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 47 insertions(+) diff --git a/drivers/power/pmic/mtk-pwrap.c b/drivers/power/pmic/mtk-pwrap.c index 3320e3cfdc0..21cf4ed6a8f 100644 --- a/drivers/power/pmic/mtk-pwrap.c +++ b/drivers/power/pmic/mtk-pwrap.c @@ -14,6 +14,7 @@ #include #include #include +#include #include #include @@ -23,6 +24,11 @@ static const struct pmic_child_info mt6357_pmic_children_info[] = { { } }; +static const struct pmic_child_info mt6358_pmic_children_info[] = { + { .prefix = "v", .driver = MT6358_REGULATOR_DRIVER }, + { } +}; + static const struct pmic_child_info mt6359_pmic_children_info[] = { { .prefix = "buck", .driver = MT6359_REGULATOR_DRIVER }, { .prefix = "ldo", .driver = MT6359_REGULATOR_DRIVER }, @@ -139,6 +145,34 @@ static const u32 mt6357_regs[] = { [PWRAP_DEW_RDDMY_NO] = 0x0424, }; +static const u32 mt6358_regs[] = { + [PWRAP_SMT_CON1] = 0x0030, + [PWRAP_DRV_CON1] = 0x0038, + [PWRAP_FILTER_CON0] = 0x0040, + [PWRAP_GPIO_PULLEN0_CLR] = 0x0098, + [PWRAP_RG_SPI_CON0] = 0x0408, + [PWRAP_RG_SPI_RECORD0] = 0x040a, + [PWRAP_DEW_DIO_EN] = 0x040c, + [PWRAP_DEW_READ_TEST] = 0x040e, + [PWRAP_DEW_WRITE_TEST] = 0x0410, + [PWRAP_DEW_CRC_EN] = 0x0414, + [PWRAP_DEW_CIPHER_KEY_SEL] = 0x041a, + [PWRAP_DEW_CIPHER_IV_SEL] = 0x041c, + [PWRAP_DEW_CIPHER_EN] = 0x041e, + [PWRAP_DEW_CIPHER_RDY] = 0x0420, + [PWRAP_DEW_CIPHER_MODE] = 0x0422, + [PWRAP_DEW_CIPHER_SWRST] = 0x0424, + [PWRAP_RG_SPI_CON2] = 0x0432, + [PWRAP_RG_SPI_CON3] = 0x0434, + [PWRAP_RG_SPI_CON4] = 0x0436, + [PWRAP_RG_SPI_CON5] = 0x0438, + [PWRAP_RG_SPI_CON6] = 0x043a, + [PWRAP_RG_SPI_CON7] = 0x043c, + [PWRAP_RG_SPI_CON8] = 0x043e, + [PWRAP_RG_SPI_CON13] = 0x0448, + [PWRAP_SPISLV_KEY] = 0x044a, +}; + static const u32 mt6359_regs[] = { [PWRAP_DEW_RG_EN_RECORD] = 0x040a, [PWRAP_DEW_DIO_EN] = 0x040c, @@ -624,6 +658,11 @@ static const struct pwrap_slv_type pmic_mt6357 = { .caps = 0, }; +static const struct pwrap_slv_type pmic_mt6358 = { + .dew_regs = mt6358_regs, + .caps = 0, +}; + static const struct pwrap_slv_type pmic_mt6359 = { .dew_regs = mt6359_regs, .caps = 0, @@ -632,6 +671,12 @@ static const struct pwrap_slv_type pmic_mt6359 = { static const struct udevice_id mtk_pmic_ids[] = { { .compatible = "mediatek,mt6357", .data = (ulong)&pmic_mt6357 }, { .compatible = "mediatek,mt6359", .data = (ulong)&pmic_mt6359 }, + /* + * REVISIT: Cooresponding regulator driver only supports MT6366 for + * now. We can change this to mediatek,mt6358 when the regulator driver + * is updated, but will also have to change ofnode_get_property() below. + */ + { .compatible = "mediatek,mt6366", .data = (ulong)&pmic_mt6358 }, { } }; @@ -770,6 +815,8 @@ static int mtk_pwrap_bind(struct udevice *dev) if (ofnode_device_is_compatible(pmic_node, "mediatek,mt6357")) { pmic_children_info = mt6357_pmic_children_info; + } else if (ofnode_device_is_compatible(pmic_node, "mediatek,mt6358")) { + pmic_children_info = mt6358_pmic_children_info; } else if (ofnode_device_is_compatible(pmic_node, "mediatek,mt6359")) { pmic_children_info = mt6359_pmic_children_info; } else { -- cgit v1.3.1 From 9829a49d14903c7dc63dac064e058f774dd8223a Mon Sep 17 00:00:00 2001 From: David Lechner Date: Fri, 7 Aug 2026 11:01:32 -0500 Subject: arm: dts: add mt6366 PMIC include Add a mt6366.dtsi file for the MediaTek MT6366 PMIC. For now, this just includes the regulators since that is all that U-Boot uses. This should eventually be replaced by an upstream devicetree file. Link: https://patch.msgid.link/20260807-mtk-pmic-mt6366-v2-5-d9fdef581fb1@baylibre.com Signed-off-by: David Lechner --- arch/arm/dts/mt6366.dtsi | 168 +++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 168 insertions(+) create mode 100644 arch/arm/dts/mt6366.dtsi diff --git a/arch/arm/dts/mt6366.dtsi b/arch/arm/dts/mt6366.dtsi new file mode 100644 index 00000000000..23cc2b62c6f --- /dev/null +++ b/arch/arm/dts/mt6366.dtsi @@ -0,0 +1,168 @@ +// SPDX-License-Identifier: (GPL-2.0-only OR MIT) +/* + * Copyright (c) 2026 MediaTek Inc. + */ + +&pwrap { + pmic: pmic { + compatible = "mediatek,mt6366", "mediatek,mt6358"; + + regulators { + compatible = "mediatek,mt6366-regulator", "mediatek,mt6358-regulator"; + + mt6366_vdram1_reg: vdram1 { + regulator-enable-ramp-delay = <0>; + }; + + mt6366_vcore_reg: vcore { + regulator-enable-ramp-delay = <200>; + regulator-always-on; + }; + + mt6366_vpa_reg: vpa { + regulator-enable-ramp-delay = <250>; + }; + + mt6366_vproc11_reg: vproc11 { + regulator-enable-ramp-delay = <200>; + regulator-always-on; + }; + + mt6366_vproc12_reg: vproc12 { + regulator-enable-ramp-delay = <200>; + regulator-always-on; + }; + + mt6366_vgpu_reg: vgpu { + regulator-enable-ramp-delay = <200>; + }; + + mt6366_vs2_reg: vs2 { + regulator-enable-ramp-delay = <0>; + regulator-always-on; + }; + + mt6366_vmodem_reg: vmodem { + regulator-enable-ramp-delay = <900>; + regulator-always-on; + }; + + mt6366_vs1_reg: vs1 { + regulator-enable-ramp-delay = <0>; + regulator-always-on; + }; + + mt6366_vdram2_reg: vdram2 { + regulator-enable-ramp-delay = <3300>; + }; + + mt6366_vsim1_reg: vsim1 { + regulator-enable-ramp-delay = <540>; + }; + + mt6366_vibr_reg: vibr { + regulator-enable-ramp-delay = <60>; + }; + + mt6366_vrf12_reg: vrf12 { + regulator-enable-ramp-delay = <120>; + }; + + mt6366_vio18_reg: vio18 { + regulator-enable-ramp-delay = <2700>; + regulator-always-on; + }; + + mt6366_vusb_reg: vusb { + regulator-enable-ramp-delay = <270>; + regulator-always-on; + }; + + mt6366_vcn18_reg: vcn18 { + regulator-enable-ramp-delay = <270>; + }; + + mt6366_vfe28_reg: vfe28 { + regulator-enable-ramp-delay = <270>; + }; + + mt6366_vsram_proc11_reg: vsram-proc11 { + regulator-enable-ramp-delay = <240>; + regulator-always-on; + }; + + mt6366_vcn28_reg: vcn28 { + regulator-enable-ramp-delay = <270>; + }; + + mt6366_vsram_others_reg: vsram-others { + regulator-enable-ramp-delay = <240>; + regulator-always-on; + }; + + mt6366_vsram_gpu_reg: vsram-gpu { + regulator-enable-ramp-delay = <240>; + }; + + mt6366_vxo22_reg: vxo22 { + regulator-enable-ramp-delay = <120>; + regulator-always-on; + }; + + mt6366_vefuse_reg: vefuse { + regulator-enable-ramp-delay = <270>; + }; + + mt6366_vaux18_reg: vaux18 { + regulator-enable-ramp-delay = <270>; + }; + + mt6366_vmch_reg: vmch { + regulator-enable-ramp-delay = <60>; + }; + + mt6366_vbif28_reg: vbif28 { + regulator-enable-ramp-delay = <270>; + }; + + mt6366_vsram_proc12_reg: vsram-proc12 { + regulator-enable-ramp-delay = <240>; + regulator-always-on; + }; + + mt6366_vemc_reg: vemc { + regulator-enable-ramp-delay = <60>; + }; + + mt6366_vio28_reg: vio28 { + regulator-enable-ramp-delay = <270>; + }; + + mt6366_va12_reg: va12 { + regulator-enable-ramp-delay = <270>; + regulator-always-on; + }; + + mt6366_vrf18_reg: vrf18 { + regulator-enable-ramp-delay = <120>; + }; + + mt6366_vcn33_bt_reg: vcn33 { + regulator-enable-ramp-delay = <270>; + }; + + mt6366_vmc_reg: vmc { + regulator-enable-ramp-delay = <60>; + }; + + mt6366_vaud28_reg: vaud28 { + regulator-enable-ramp-delay = <270>; + regulator-always-on; + }; + + mt6366_vsim2_reg: vsim2 { + regulator-enable-ramp-delay = <540>; + }; + }; + }; +}; -- cgit v1.3.1 From 186a142207e7b8c3f559cb91cef19d4b19c71153 Mon Sep 17 00:00:00 2001 From: David Lechner Date: Fri, 7 Aug 2026 14:16:29 -0500 Subject: pinctrl: mediatek: select PINCONF All MediaTek targets include pinconf registers so we should just always select PINCONF instead of requiring each config to explicitly enable it. MT8518 was the only target that didn't have PINCONF already enabled in the defconfig, so it will be enabled there by default now. (This was likely unintentional as the MT8518 driver does define pinconf registers for drive and pull so supports pinconf operations.) Link: https://patch.msgid.link/20260807-mtk-pinctrl-kconfig-cleanup-v2-1-509a8f833181@baylibre.com Signed-off-by: David Lechner --- drivers/pinctrl/mediatek/Kconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/pinctrl/mediatek/Kconfig b/drivers/pinctrl/mediatek/Kconfig index 5a90d74a9e1..42c7c8b8c80 100644 --- a/drivers/pinctrl/mediatek/Kconfig +++ b/drivers/pinctrl/mediatek/Kconfig @@ -2,6 +2,7 @@ if ARCH_MEDIATEK config PINCTRL_MTK depends on PINCTRL_GENERIC + select PINCONF select REGMAP select SYSCON bool -- cgit v1.3.1 From fd017c4974ae2313c74bf8aa94a0b7bc4d974134 Mon Sep 17 00:00:00 2001 From: David Lechner Date: Fri, 7 Aug 2026 14:16:30 -0500 Subject: pinctrl: mediatek: remove PINCONF conditional compilation Remove #if conditionals that checked if PINCONF was enabled. The Kconfig now selects PINCONF, so it will always be enabled and we don't need the checks anymore. Link: https://patch.msgid.link/20260807-mtk-pinctrl-kconfig-cleanup-v2-2-509a8f833181@baylibre.com Signed-off-by: David Lechner --- drivers/pinctrl/mediatek/pinctrl-mtk-common.c | 13 ------------- drivers/pinctrl/mediatek/pinctrl-mtk-common.h | 6 ------ 2 files changed, 19 deletions(-) diff --git a/drivers/pinctrl/mediatek/pinctrl-mtk-common.c b/drivers/pinctrl/mediatek/pinctrl-mtk-common.c index 01f67f09407..0b8234e167f 100644 --- a/drivers/pinctrl/mediatek/pinctrl-mtk-common.c +++ b/drivers/pinctrl/mediatek/pinctrl-mtk-common.c @@ -19,7 +19,6 @@ #include "pinctrl-mtk-common.h" -#if CONFIG_IS_ENABLED(PINCONF) /** * struct mtk_drive_desc - the structure that holds the information * of the driving current @@ -45,7 +44,6 @@ static const struct mtk_drive_desc mtk_drive[] = { [DRV_GRP3] = { 2, 8, 2, 2 }, [DRV_GRP4] = { 2, 16, 2, 1 }, }; -#endif static const char *mtk_pinctrl_dummy_name = "_dummy"; @@ -223,7 +221,6 @@ static int mtk_hw_get_value(struct udevice *dev, int pin, int field, return 0; } -#if CONFIG_IS_ENABLED(PINCONF) static int mtk_get_pin_io_type(struct udevice *dev, int pin, struct mtk_io_type_desc *io_type) { @@ -265,12 +262,6 @@ static int mtk_pinconf_get(struct udevice *dev, u32 pin, char *buf, size_t size) return pos; } -#else -static int mtk_pinconf_get(struct udevice *dev, u32 pin, char *buf, size_t size) -{ - return 0; -} -#endif static int mtk_get_groups_count(struct udevice *dev) { @@ -378,7 +369,6 @@ static int mtk_pinmux_group_set(struct udevice *dev, return 0; } -#if CONFIG_IS_ENABLED(PINCONF) static const struct pinconf_param mtk_conf_params[] = { { "bias-disable", PIN_CONFIG_BIAS_DISABLE, 0 }, { "bias-pull-up", PIN_CONFIG_BIAS_PULL_UP, 1 }, @@ -757,7 +747,6 @@ int mtk_pinconf_get_pu_pd_rsel(struct udevice *dev, u32 pin, char *buf, size_t s return pos + scnprintf(buf + pos, size - pos, " RSEL:%d", rsel); } -#endif static int mtk_pinctrl_pinmux_property_set(struct udevice *dev, u32 pinmux_group) { @@ -779,12 +768,10 @@ const struct pinctrl_ops mtk_pinctrl_ops = { .get_function_name = mtk_get_function_name, .pinmux_set = mtk_pinmux_set, .pinmux_group_set = mtk_pinmux_group_set, -#if CONFIG_IS_ENABLED(PINCONF) .pinconf_num_params = ARRAY_SIZE(mtk_conf_params), .pinconf_params = mtk_conf_params, .pinconf_set = mtk_pinconf_set, .pinconf_group_set = mtk_pinconf_group_set, -#endif .set_state = pinctrl_generic_set_state, .pinmux_property_set = mtk_pinctrl_pinmux_property_set, }; diff --git a/drivers/pinctrl/mediatek/pinctrl-mtk-common.h b/drivers/pinctrl/mediatek/pinctrl-mtk-common.h index bd17964090a..1f97f3cd7b0 100644 --- a/drivers/pinctrl/mediatek/pinctrl-mtk-common.h +++ b/drivers/pinctrl/mediatek/pinctrl-mtk-common.h @@ -198,14 +198,12 @@ struct mtk_function_desc { */ struct mtk_io_type_desc { const char *name; -#if CONFIG_IS_ENABLED(PINCONF) /* Specific pinconfig operations */ int (*bias_set)(struct udevice *dev, u32 pin, bool disable, bool pullup, u32 val); int (*drive_set)(struct udevice *dev, u32 pin, u32 arg); int (*input_enable)(struct udevice *dev, u32 pin, u32 arg); int (*get_pinconf)(struct udevice *dev, u32 pin, char *buf, size_t size); -#endif }; /* struct mtk_pin_soc - the structure that holds SoC-specific data */ @@ -247,8 +245,6 @@ int mtk_pinctrl_common_bind(struct udevice *dev); int mtk_pinctrl_common_probe(struct udevice *dev, const struct mtk_pinctrl_soc *soc); -#if CONFIG_IS_ENABLED(PINCONF) - int mtk_pinconf_bias_set_pu_pd(struct udevice *dev, u32 pin, bool disable, bool pullup, u32 val); int mtk_pinconf_bias_set_pullen_pullsel(struct udevice *dev, u32 pin, @@ -268,6 +264,4 @@ int mtk_pinconf_get_pu_pd(struct udevice *dev, u32 pin, char *buf, size_t size); int mtk_pinconf_get_pupd_r1_r0(struct udevice *dev, u32 pin, char *buf, size_t size); int mtk_pinconf_get_pu_pd_rsel(struct udevice *dev, u32 pin, char *buf, size_t size); -#endif - #endif /* __PINCTRL_MEDIATEK_H__ */ -- cgit v1.3.1 From 86ae242f246dd6dddeb01588ace0526d2638e962 Mon Sep 17 00:00:00 2001 From: David Lechner Date: Fri, 7 Aug 2026 14:16:31 -0500 Subject: pinctrl: mediatek: simplify Kconfig Change the MediaTek pinctrl Kconfig to just have a single option for all targets. This will simplify adding new targets and SPL support in the future. There is only one MediaTek target that does not have a pinctrl driver. All other targets enable it by default so the configs don't have to explicitly set it in addition to just enabling PINCTRL. In the Makefile, we can use the target config symbol to automatically select the correct driver. And the config selector on the common file was redundant since we already have the same in the parent Makefile, so it is dropped. Targets are also sorted while we are touching this. Suggested-by: Quentin Schulz Closes: https://lore.kernel.org/u-boot/fba47ca8-7cf7-446a-9242-54c50087cf3c@cherry.de/ Acked-by: Quentin Schulz Link: https://patch.msgid.link/20260807-mtk-pinctrl-kconfig-cleanup-v2-3-509a8f833181@baylibre.com Signed-off-by: David Lechner --- drivers/pinctrl/mediatek/Kconfig | 61 +++------------------------------------ drivers/pinctrl/mediatek/Makefile | 30 +++++++++---------- 2 files changed, 19 insertions(+), 72 deletions(-) diff --git a/drivers/pinctrl/mediatek/Kconfig b/drivers/pinctrl/mediatek/Kconfig index 42c7c8b8c80..46e35cbfe6c 100644 --- a/drivers/pinctrl/mediatek/Kconfig +++ b/drivers/pinctrl/mediatek/Kconfig @@ -1,66 +1,13 @@ if ARCH_MEDIATEK config PINCTRL_MTK + bool "MediaTek pinctrl driver" depends on PINCTRL_GENERIC + default y if !TARGET_MT8183 select PINCONF select REGMAP select SYSCON - bool - -config PINCTRL_MT7622 - bool "MT7622 SoC pinctrl driver" - select PINCTRL_MTK - -config PINCTRL_MT7623 - bool "MT7623 SoC pinctrl driver" - select PINCTRL_MTK - -config PINCTRL_MT7629 - bool "MT7629 SoC pinctrl driver" - select PINCTRL_MTK - -config PINCTRL_MT7981 - bool "MT7981 SoC pinctrl driver" - select PINCTRL_MTK - -config PINCTRL_MT7986 - bool "MT7986 SoC pinctrl driver" - select PINCTRL_MTK - -config PINCTRL_MT7987 - bool "MT7987 SoC pinctrl driver" - select PINCTRL_MTK - -config PINCTRL_MT7988 - bool "MT7988 SoC pinctrl driver" - select PINCTRL_MTK - -config PINCTRL_MT8188 - bool "MT8188 SoC pinctrl driver" - select PINCTRL_MTK - -config PINCTRL_MT8195 - bool "MT8195 SoC pinctrl driver" - select PINCTRL_MTK - -config PINCTRL_MT8189 - bool "MT8189 SoC pinctrl driver" - select PINCTRL_MTK - -config PINCTRL_MT8365 - bool "MT8365 SoC pinctrl driver" - select PINCTRL_MTK - -config PINCTRL_MT8512 - bool "MT8512 SoC pinctrl driver" - select PINCTRL_MTK - -config PINCTRL_MT8516 - bool "MT8516 SoC pinctrl driver" - select PINCTRL_MTK - -config PINCTRL_MT8518 - bool "MT8518 SoC pinctrl driver" - select PINCTRL_MTK + help + Enable MediaTek pinctrl support. endif diff --git a/drivers/pinctrl/mediatek/Makefile b/drivers/pinctrl/mediatek/Makefile index f90c74314f4..f367db5c575 100644 --- a/drivers/pinctrl/mediatek/Makefile +++ b/drivers/pinctrl/mediatek/Makefile @@ -1,19 +1,19 @@ # SPDX-License-Identifier: GPL-2.0 # Core -obj-$(CONFIG_PINCTRL_MTK) += pinctrl-mtk-common.o +obj-y += pinctrl-mtk-common.o # SoC Drivers -obj-$(CONFIG_PINCTRL_MT7622) += pinctrl-mt7622.o -obj-$(CONFIG_PINCTRL_MT7623) += pinctrl-mt7623.o -obj-$(CONFIG_PINCTRL_MT7629) += pinctrl-mt7629.o -obj-$(CONFIG_PINCTRL_MT7981) += pinctrl-mt7981.o -obj-$(CONFIG_PINCTRL_MT7986) += pinctrl-mt7986.o -obj-$(CONFIG_PINCTRL_MT7987) += pinctrl-mt7987.o -obj-$(CONFIG_PINCTRL_MT7988) += pinctrl-mt7988.o -obj-$(CONFIG_PINCTRL_MT8188) += pinctrl-mt8188.o -obj-$(CONFIG_PINCTRL_MT8195) += pinctrl-mt8195.o -obj-$(CONFIG_PINCTRL_MT8189) += pinctrl-mt8189.o -obj-$(CONFIG_PINCTRL_MT8365) += pinctrl-mt8365.o -obj-$(CONFIG_PINCTRL_MT8512) += pinctrl-mt8512.o -obj-$(CONFIG_PINCTRL_MT8516) += pinctrl-mt8516.o -obj-$(CONFIG_PINCTRL_MT8518) += pinctrl-mt8518.o +obj-$(CONFIG_TARGET_MT7622) += pinctrl-mt7622.o +obj-$(CONFIG_TARGET_MT7623) += pinctrl-mt7623.o +obj-$(CONFIG_TARGET_MT7629) += pinctrl-mt7629.o +obj-$(CONFIG_TARGET_MT7981) += pinctrl-mt7981.o +obj-$(CONFIG_TARGET_MT7986) += pinctrl-mt7986.o +obj-$(CONFIG_TARGET_MT7987) += pinctrl-mt7987.o +obj-$(CONFIG_TARGET_MT7988) += pinctrl-mt7988.o +obj-$(CONFIG_TARGET_MT8188) += pinctrl-mt8188.o +obj-$(CONFIG_TARGET_MT8189) += pinctrl-mt8189.o +obj-$(CONFIG_TARGET_MT8195) += pinctrl-mt8195.o +obj-$(CONFIG_TARGET_MT8365) += pinctrl-mt8365.o +obj-$(CONFIG_TARGET_MT8512) += pinctrl-mt8512.o +obj-$(CONFIG_TARGET_MT8516) += pinctrl-mt8516.o +obj-$(CONFIG_TARGET_MT8518) += pinctrl-mt8518.o -- cgit v1.3.1 From f807d57664ae2e6128e9a17dcebfd45b8de3a77b Mon Sep 17 00:00:00 2001 From: David Lechner Date: Fri, 7 Aug 2026 14:16:32 -0500 Subject: configs: mediatek: drop no longer needed PINCTRL options Drop CONFIG_PINCONF and CONFIG_PINCTRL_ from all MediaTek defconfig files. The former is always selected now and the latter no longer exists. Link: https://patch.msgid.link/20260807-mtk-pinctrl-kconfig-cleanup-v2-4-509a8f833181@baylibre.com Signed-off-by: David Lechner --- configs/mt7622_rfb_defconfig | 2 -- configs/mt7623a_unielec_u7623_02_defconfig | 2 -- configs/mt7623n_bpir2_defconfig | 2 -- configs/mt7629_rfb_defconfig | 2 -- configs/mt7981_emmc_rfb_defconfig | 2 -- configs/mt7981_rfb_defconfig | 2 -- configs/mt7981_sd_rfb_defconfig | 2 -- configs/mt7986_rfb_defconfig | 2 -- configs/mt7986a_bpir3_emmc_defconfig | 2 -- configs/mt7986a_bpir3_sd_defconfig | 2 -- configs/mt7987_emmc_rfb_defconfig | 2 -- configs/mt7987_rfb_defconfig | 2 -- configs/mt7987_sd_rfb_defconfig | 2 -- configs/mt7988_rfb_defconfig | 2 -- configs/mt7988_sd_rfb_defconfig | 2 -- configs/mt8188.config | 2 -- configs/mt8189.config | 2 -- configs/mt8195.config | 2 -- configs/mt8365_evk_defconfig | 2 -- configs/mt8512_bm1_emmc_defconfig | 2 -- configs/mt8516_pumpkin_defconfig | 2 -- configs/mt8518_ap1_emmc_defconfig | 1 - 22 files changed, 43 deletions(-) diff --git a/configs/mt7622_rfb_defconfig b/configs/mt7622_rfb_defconfig index 10df7847a4b..d35bed49afa 100644 --- a/configs/mt7622_rfb_defconfig +++ b/configs/mt7622_rfb_defconfig @@ -48,8 +48,6 @@ CONFIG_MEDIATEK_ETH=y CONFIG_PHY_FIXED=y CONFIG_PCIE_MEDIATEK=y CONFIG_PINCTRL=y -CONFIG_PINCONF=y -CONFIG_PINCTRL_MT7622=y CONFIG_POWER_DOMAIN=y CONFIG_MT7622_POWER_DOMAIN=y CONFIG_RAM=y diff --git a/configs/mt7623a_unielec_u7623_02_defconfig b/configs/mt7623a_unielec_u7623_02_defconfig index 77473e2731f..13fe8766b98 100644 --- a/configs/mt7623a_unielec_u7623_02_defconfig +++ b/configs/mt7623a_unielec_u7623_02_defconfig @@ -46,8 +46,6 @@ CONFIG_MMC_MTK=y CONFIG_MEDIATEK_ETH=y CONFIG_PHY_FIXED=y CONFIG_PINCTRL=y -CONFIG_PINCONF=y -CONFIG_PINCTRL_MT7623=y CONFIG_POWER_DOMAIN=y CONFIG_MT2701_POWER_DOMAIN=y CONFIG_DM_SERIAL=y diff --git a/configs/mt7623n_bpir2_defconfig b/configs/mt7623n_bpir2_defconfig index aacaf5380fa..13fd033b2f7 100644 --- a/configs/mt7623n_bpir2_defconfig +++ b/configs/mt7623n_bpir2_defconfig @@ -48,8 +48,6 @@ CONFIG_MMC_MTK=y CONFIG_MEDIATEK_ETH=y CONFIG_PHY_FIXED=y CONFIG_PINCTRL=y -CONFIG_PINCONF=y -CONFIG_PINCTRL_MT7623=y CONFIG_POWER_DOMAIN=y CONFIG_MT2701_POWER_DOMAIN=y CONFIG_DM_SERIAL=y diff --git a/configs/mt7629_rfb_defconfig b/configs/mt7629_rfb_defconfig index 91da684939a..4b2412cc571 100644 --- a/configs/mt7629_rfb_defconfig +++ b/configs/mt7629_rfb_defconfig @@ -80,8 +80,6 @@ CONFIG_MEDIATEK_ETH=y CONFIG_PHY=y CONFIG_PHY_MTK_TPHY=y CONFIG_PINCTRL=y -CONFIG_PINCONF=y -CONFIG_PINCTRL_MT7629=y CONFIG_POWER_DOMAIN=y CONFIG_MT7622_POWER_DOMAIN=y CONFIG_DM_REGULATOR=y diff --git a/configs/mt7981_emmc_rfb_defconfig b/configs/mt7981_emmc_rfb_defconfig index 75e7140bdfa..3c24da09505 100644 --- a/configs/mt7981_emmc_rfb_defconfig +++ b/configs/mt7981_emmc_rfb_defconfig @@ -50,8 +50,6 @@ CONFIG_MMC_MTK=y CONFIG_MEDIATEK_ETH=y CONFIG_PHY_FIXED=y CONFIG_PINCTRL=y -CONFIG_PINCONF=y -CONFIG_PINCTRL_MT7981=y CONFIG_DM_REGULATOR=y CONFIG_DM_REGULATOR_FIXED=y CONFIG_DM_SERIAL=y diff --git a/configs/mt7981_rfb_defconfig b/configs/mt7981_rfb_defconfig index 6322af51b18..e57637b9e01 100644 --- a/configs/mt7981_rfb_defconfig +++ b/configs/mt7981_rfb_defconfig @@ -52,8 +52,6 @@ CONFIG_SPI_FLASH_MTD=y CONFIG_MEDIATEK_ETH=y CONFIG_PHY_FIXED=y CONFIG_PINCTRL=y -CONFIG_PINCONF=y -CONFIG_PINCTRL_MT7981=y CONFIG_DM_SERIAL=y CONFIG_MTK_SERIAL=y CONFIG_SPI=y diff --git a/configs/mt7981_sd_rfb_defconfig b/configs/mt7981_sd_rfb_defconfig index de05e2486a0..a3702dc83fd 100644 --- a/configs/mt7981_sd_rfb_defconfig +++ b/configs/mt7981_sd_rfb_defconfig @@ -50,8 +50,6 @@ CONFIG_MMC_MTK=y CONFIG_MEDIATEK_ETH=y CONFIG_PHY_FIXED=y CONFIG_PINCTRL=y -CONFIG_PINCONF=y -CONFIG_PINCTRL_MT7981=y CONFIG_DM_REGULATOR=y CONFIG_DM_REGULATOR_FIXED=y CONFIG_DM_SERIAL=y diff --git a/configs/mt7986_rfb_defconfig b/configs/mt7986_rfb_defconfig index 87fbe677624..519022a8da6 100644 --- a/configs/mt7986_rfb_defconfig +++ b/configs/mt7986_rfb_defconfig @@ -52,8 +52,6 @@ CONFIG_SPI_FLASH_MTD=y CONFIG_MEDIATEK_ETH=y CONFIG_PHY_FIXED=y CONFIG_PINCTRL=y -CONFIG_PINCONF=y -CONFIG_PINCTRL_MT7986=y CONFIG_DM_SERIAL=y CONFIG_MTK_SERIAL=y CONFIG_SPI=y diff --git a/configs/mt7986a_bpir3_emmc_defconfig b/configs/mt7986a_bpir3_emmc_defconfig index 92459ad9fe2..fd255ab8719 100644 --- a/configs/mt7986a_bpir3_emmc_defconfig +++ b/configs/mt7986a_bpir3_emmc_defconfig @@ -50,8 +50,6 @@ CONFIG_MMC_MTK=y CONFIG_MEDIATEK_ETH=y CONFIG_PHY_FIXED=y CONFIG_PINCTRL=y -CONFIG_PINCONF=y -CONFIG_PINCTRL_MT7986=y CONFIG_DM_REGULATOR=y CONFIG_DM_REGULATOR_FIXED=y CONFIG_DM_SERIAL=y diff --git a/configs/mt7986a_bpir3_sd_defconfig b/configs/mt7986a_bpir3_sd_defconfig index 2c88255e69d..b3826dad560 100644 --- a/configs/mt7986a_bpir3_sd_defconfig +++ b/configs/mt7986a_bpir3_sd_defconfig @@ -50,8 +50,6 @@ CONFIG_MMC_MTK=y CONFIG_MEDIATEK_ETH=y CONFIG_PHY_FIXED=y CONFIG_PINCTRL=y -CONFIG_PINCONF=y -CONFIG_PINCTRL_MT7986=y CONFIG_DM_REGULATOR=y CONFIG_DM_REGULATOR_FIXED=y CONFIG_DM_SERIAL=y diff --git a/configs/mt7987_emmc_rfb_defconfig b/configs/mt7987_emmc_rfb_defconfig index 00d7e5a610a..59a1aadb713 100644 --- a/configs/mt7987_emmc_rfb_defconfig +++ b/configs/mt7987_emmc_rfb_defconfig @@ -75,8 +75,6 @@ CONFIG_MTD_UBI=y CONFIG_MEDIATEK_ETH=y CONFIG_PHY_ETHERNET_ID=y CONFIG_PINCTRL=y -CONFIG_PINCONF=y -CONFIG_PINCTRL_MT7987=y CONFIG_DM_PWM=y CONFIG_PWM_MTK=y CONFIG_DM_SERIAL=y diff --git a/configs/mt7987_rfb_defconfig b/configs/mt7987_rfb_defconfig index 0b353c6cf01..9e9ad69e50b 100644 --- a/configs/mt7987_rfb_defconfig +++ b/configs/mt7987_rfb_defconfig @@ -70,8 +70,6 @@ CONFIG_MTD_UBI=y CONFIG_MEDIATEK_ETH=y CONFIG_PHY_ETHERNET_ID=y CONFIG_PINCTRL=y -CONFIG_PINCONF=y -CONFIG_PINCTRL_MT7987=y CONFIG_DM_PWM=y CONFIG_PWM_MTK=y CONFIG_DM_SERIAL=y diff --git a/configs/mt7987_sd_rfb_defconfig b/configs/mt7987_sd_rfb_defconfig index 30ff09365da..5c50dfef072 100644 --- a/configs/mt7987_sd_rfb_defconfig +++ b/configs/mt7987_sd_rfb_defconfig @@ -75,8 +75,6 @@ CONFIG_MTD_UBI=y CONFIG_MEDIATEK_ETH=y CONFIG_PHY_ETHERNET_ID=y CONFIG_PINCTRL=y -CONFIG_PINCONF=y -CONFIG_PINCTRL_MT7987=y CONFIG_DM_PWM=y CONFIG_PWM_MTK=y CONFIG_DM_SERIAL=y diff --git a/configs/mt7988_rfb_defconfig b/configs/mt7988_rfb_defconfig index 375df418ce0..3d74f09f436 100644 --- a/configs/mt7988_rfb_defconfig +++ b/configs/mt7988_rfb_defconfig @@ -65,8 +65,6 @@ CONFIG_SPI_FLASH_MTD=y CONFIG_MEDIATEK_ETH=y CONFIG_PHY_FIXED=y CONFIG_PINCTRL=y -CONFIG_PINCONF=y -CONFIG_PINCTRL_MT7988=y CONFIG_DM_PWM=y CONFIG_PWM_MTK=y CONFIG_RAM=y diff --git a/configs/mt7988_sd_rfb_defconfig b/configs/mt7988_sd_rfb_defconfig index aafbed7bea5..955e6e63d42 100644 --- a/configs/mt7988_sd_rfb_defconfig +++ b/configs/mt7988_sd_rfb_defconfig @@ -53,8 +53,6 @@ CONFIG_MTD_SPI_NAND=y CONFIG_MEDIATEK_ETH=y CONFIG_PHY_FIXED=y CONFIG_PINCTRL=y -CONFIG_PINCONF=y -CONFIG_PINCTRL_MT7988=y CONFIG_DM_PWM=y CONFIG_PWM_MTK=y CONFIG_RAM=y diff --git a/configs/mt8188.config b/configs/mt8188.config index 29e2b3db878..c6785476d9a 100644 --- a/configs/mt8188.config +++ b/configs/mt8188.config @@ -17,8 +17,6 @@ CONFIG_OF_UPSTREAM=y CONFIG_CLK=y CONFIG_MMC_MTK=y CONFIG_PINCTRL=y -CONFIG_PINCONF=y -CONFIG_PINCTRL_MT8188=y CONFIG_POWER_DOMAIN=y CONFIG_MT8188_POWER_DOMAIN=y CONFIG_BAUDRATE=921600 diff --git a/configs/mt8189.config b/configs/mt8189.config index ab56c90a17c..7c37c37a199 100644 --- a/configs/mt8189.config +++ b/configs/mt8189.config @@ -35,8 +35,6 @@ CONFIG_PHY=y CONFIG_PHY_MTK_TPHY=y CONFIG_PHY_MTK_XSPHY=y CONFIG_PINCTRL=y -CONFIG_PINCONF=y -CONFIG_PINCTRL_MT8189=y CONFIG_DM_PMIC=y CONFIG_DM_PMIC_MTK_PWRAP=y CONFIG_DM_REGULATOR=y diff --git a/configs/mt8195.config b/configs/mt8195.config index 03f57d46708..c12ff93e3eb 100644 --- a/configs/mt8195.config +++ b/configs/mt8195.config @@ -17,8 +17,6 @@ CONFIG_OF_UPSTREAM=y CONFIG_CLK=y CONFIG_MMC_MTK=y CONFIG_PINCTRL=y -CONFIG_PINCONF=y -CONFIG_PINCTRL_MT8195=y CONFIG_DM_PMIC=y CONFIG_DM_PMIC_MTK_PWRAP=y CONFIG_DM_REGULATOR=y diff --git a/configs/mt8365_evk_defconfig b/configs/mt8365_evk_defconfig index 5db8418e36f..b3dcc5cc5b4 100644 --- a/configs/mt8365_evk_defconfig +++ b/configs/mt8365_evk_defconfig @@ -22,8 +22,6 @@ CONFIG_OF_UPSTREAM=y CONFIG_CLK=y CONFIG_MMC_MTK=y CONFIG_PINCTRL=y -CONFIG_PINCONF=y -CONFIG_PINCTRL_MT8365=y CONFIG_DM_PMIC=y CONFIG_DM_PMIC_MTK_PWRAP=y CONFIG_DM_REGULATOR=y diff --git a/configs/mt8512_bm1_emmc_defconfig b/configs/mt8512_bm1_emmc_defconfig index c7ac0df39f5..7f0f866e282 100644 --- a/configs/mt8512_bm1_emmc_defconfig +++ b/configs/mt8512_bm1_emmc_defconfig @@ -38,8 +38,6 @@ CONFIG_MMC_MTK=y CONFIG_PHY=y CONFIG_PHY_MTK_TPHY=y CONFIG_PINCTRL=y -CONFIG_PINCONF=y -CONFIG_PINCTRL_MT8512=y CONFIG_DM_REGULATOR=y CONFIG_DM_REGULATOR_FIXED=y CONFIG_RAM=y diff --git a/configs/mt8516_pumpkin_defconfig b/configs/mt8516_pumpkin_defconfig index 72ff8c79153..80184898930 100644 --- a/configs/mt8516_pumpkin_defconfig +++ b/configs/mt8516_pumpkin_defconfig @@ -70,8 +70,6 @@ CONFIG_FASTBOOT_MMC_USER_SUPPORT=y # CONFIG_MMC_QUIRKS is not set CONFIG_MMC_MTK=y CONFIG_PINCTRL=y -CONFIG_PINCONF=y -CONFIG_PINCTRL_MT8516=y CONFIG_RAM=y CONFIG_BAUDRATE=921600 CONFIG_DM_SERIAL=y diff --git a/configs/mt8518_ap1_emmc_defconfig b/configs/mt8518_ap1_emmc_defconfig index 2722e107dc7..fa4b88b24ad 100644 --- a/configs/mt8518_ap1_emmc_defconfig +++ b/configs/mt8518_ap1_emmc_defconfig @@ -32,7 +32,6 @@ CONFIG_FASTBOOT_MMC_USER_SUPPORT=y CONFIG_MMC_HS200_SUPPORT=y CONFIG_MMC_MTK=y CONFIG_PINCTRL=y -CONFIG_PINCTRL_MT8518=y CONFIG_RAM=y CONFIG_BAUDRATE=921600 CONFIG_DM_SERIAL=y -- cgit v1.3.1 From 572c19d3161b4ba4c793a9c2ee3224d61c75fbd9 Mon Sep 17 00:00:00 2001 From: Deep Pani Date: Fri, 7 Aug 2026 13:43:53 -0500 Subject: dt-bindings: pinctrl: add MT8366 pin function header Add a header with MT8366 pin function definitions for use in devicetrees. Upstreaming of MT8366 has not even started yet, so we will have to carry a downstream version of this for some time. Signed-off-by: Deep Pani Link: https://patch.msgid.link/20260807-mtk-pinctrl-mt8366-v2-2-b7358bb31521@baylibre.com Signed-off-by: David Lechner --- .../dt-bindings/pinctrl/mediatek,mt8366-pinfunc.h | 1069 ++++++++++++++++++++ 1 file changed, 1069 insertions(+) create mode 100644 include/dt-bindings/pinctrl/mediatek,mt8366-pinfunc.h diff --git a/include/dt-bindings/pinctrl/mediatek,mt8366-pinfunc.h b/include/dt-bindings/pinctrl/mediatek,mt8366-pinfunc.h new file mode 100644 index 00000000000..5a21b984076 --- /dev/null +++ b/include/dt-bindings/pinctrl/mediatek,mt8366-pinfunc.h @@ -0,0 +1,1069 @@ +/* SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause */ +/* + * Copyright (C) 2026 MediaTek Inc. + * Author: Lei Xue + */ + +#ifndef __MT8366_PINFUNC_H +#define __MT8366_PINFUNC_H + +#include + +#define PINMUX_GPIO0__FUNC_GPIO0 (MTK_PIN_NO(0) | 0) +#define PINMUX_GPIO0__FUNC_PWM_0 (MTK_PIN_NO(0) | 1) +#define PINMUX_GPIO0__FUNC_I2SOUT5_DATA0 (MTK_PIN_NO(0) | 2) +#define PINMUX_GPIO0__FUNC_SRCLKENAI0 (MTK_PIN_NO(0) | 3) +#define PINMUX_GPIO0__FUNC_ANT_SEL7 (MTK_PIN_NO(0) | 4) +#define PINMUX_GPIO0__FUNC_DMIC2_CLK (MTK_PIN_NO(0) | 5) +#define PINMUX_GPIO0__FUNC_CONN_BPI_BUS12_OLAT1 (MTK_PIN_NO(0) | 6) +#define PINMUX_GPIO0__FUNC_DBG_MON_B3 (MTK_PIN_NO(0) | 7) + +#define PINMUX_GPIO1__FUNC_GPIO1 (MTK_PIN_NO(1) | 0) +#define PINMUX_GPIO1__FUNC_PWM_1 (MTK_PIN_NO(1) | 1) +#define PINMUX_GPIO1__FUNC_I2SOUT5_DATA1 (MTK_PIN_NO(1) | 2) +#define PINMUX_GPIO1__FUNC_SRCLKENAI1 (MTK_PIN_NO(1) | 3) +#define PINMUX_GPIO1__FUNC_ANT_SEL8 (MTK_PIN_NO(1) | 4) +#define PINMUX_GPIO1__FUNC_DMIC2_DAT0 (MTK_PIN_NO(1) | 5) +#define PINMUX_GPIO1__FUNC_CONN_BPI_BUS13_OLAT2 (MTK_PIN_NO(1) | 6) +#define PINMUX_GPIO1__FUNC_DBG_MON_B4 (MTK_PIN_NO(1) | 7) + +#define PINMUX_GPIO2__FUNC_GPIO2 (MTK_PIN_NO(2) | 0) +#define PINMUX_GPIO2__FUNC_PWM_2 (MTK_PIN_NO(2) | 1) +#define PINMUX_GPIO2__FUNC_I2SOUT5_DATA2 (MTK_PIN_NO(2) | 2) +#define PINMUX_GPIO2__FUNC_DP_TX_HPD (MTK_PIN_NO(2) | 3) +#define PINMUX_GPIO2__FUNC_ANT_SEL9 (MTK_PIN_NO(2) | 4) +#define PINMUX_GPIO2__FUNC_DMIC2_DAT1 (MTK_PIN_NO(2) | 5) +#define PINMUX_GPIO2__FUNC_CONN_BPI_BUS14_OLAT3 (MTK_PIN_NO(2) | 6) +#define PINMUX_GPIO2__FUNC_DBG_MON_B5 (MTK_PIN_NO(2) | 7) + +#define PINMUX_GPIO3__FUNC_GPIO3 (MTK_PIN_NO(3) | 0) +#define PINMUX_GPIO3__FUNC_ANT_SEL0 (MTK_PIN_NO(3) | 1) +#define PINMUX_GPIO3__FUNC_I2SOUT6_DATA9 (MTK_PIN_NO(3) | 2) +#define PINMUX_GPIO3__FUNC_PWM_0 (MTK_PIN_NO(3) | 3) +#define PINMUX_GPIO3__FUNC_SRCLKENAI0 (MTK_PIN_NO(3) | 4) +#define PINMUX_GPIO3__FUNC_SPM_DVS_0 (MTK_PIN_NO(3) | 5) +#define PINMUX_GPIO3__FUNC_CLKM0 (MTK_PIN_NO(3) | 6) +#define PINMUX_GPIO3__FUNC_DBG_MON_B31 (MTK_PIN_NO(3) | 7) + +#define PINMUX_GPIO4__FUNC_GPIO4 (MTK_PIN_NO(4) | 0) +#define PINMUX_GPIO4__FUNC_ANT_SEL1 (MTK_PIN_NO(4) | 1) +#define PINMUX_GPIO4__FUNC_I2SOUT6_DATA10 (MTK_PIN_NO(4) | 2) +#define PINMUX_GPIO4__FUNC_PWM_1 (MTK_PIN_NO(4) | 3) +#define PINMUX_GPIO4__FUNC_SRCLKENAI1 (MTK_PIN_NO(4) | 4) +#define PINMUX_GPIO4__FUNC_SPM_DVS_1 (MTK_PIN_NO(4) | 5) +#define PINMUX_GPIO4__FUNC_CLKM1 (MTK_PIN_NO(4) | 6) +#define PINMUX_GPIO4__FUNC_LVTS_SCK (MTK_PIN_NO(4) | 7) + +#define PINMUX_GPIO5__FUNC_GPIO5 (MTK_PIN_NO(5) | 0) +#define PINMUX_GPIO5__FUNC_ANT_SEL2 (MTK_PIN_NO(5) | 1) +#define PINMUX_GPIO5__FUNC_I2SOUT6_DATA0 (MTK_PIN_NO(5) | 2) +#define PINMUX_GPIO5__FUNC_PWM_2 (MTK_PIN_NO(5) | 3) +#define PINMUX_GPIO5__FUNC_CONN_TCXOENA_REQ (MTK_PIN_NO(5) | 4) +#define PINMUX_GPIO5__FUNC_CMFLASH0 (MTK_PIN_NO(5) | 5) +#define PINMUX_GPIO5__FUNC_CLKM2 (MTK_PIN_NO(5) | 6) +#define PINMUX_GPIO5__FUNC_LVTS_SDI (MTK_PIN_NO(5) | 7) + +#define PINMUX_GPIO6__FUNC_GPIO6 (MTK_PIN_NO(6) | 0) +#define PINMUX_GPIO6__FUNC_DP_TX_HPD (MTK_PIN_NO(6) | 1) +#define PINMUX_GPIO6__FUNC_DISP_PWM1 (MTK_PIN_NO(6) | 2) +#define PINMUX_GPIO6__FUNC_CONN_TSF (MTK_PIN_NO(6) | 3) +#define PINMUX_GPIO6__FUNC_CMFLASH1 (MTK_PIN_NO(6) | 5) +#define PINMUX_GPIO6__FUNC_CLKM3 (MTK_PIN_NO(6) | 6) +#define PINMUX_GPIO6__FUNC_DBG_MON_B32 (MTK_PIN_NO(6) | 7) + +#define PINMUX_GPIO7__FUNC_GPIO7 (MTK_PIN_NO(7) | 0) +#define PINMUX_GPIO7__FUNC_LCM1_RST (MTK_PIN_NO(7) | 1) +#define PINMUX_GPIO7__FUNC_CONN_TSF (MTK_PIN_NO(7) | 3) +#define PINMUX_GPIO7__FUNC_LVTS_SCF (MTK_PIN_NO(7) | 7) + +#define PINMUX_GPIO8__FUNC_GPIO8 (MTK_PIN_NO(8) | 0) +#define PINMUX_GPIO8__FUNC_DSI1_TE (MTK_PIN_NO(8) | 1) +#define PINMUX_GPIO8__FUNC_LVTS_SDO (MTK_PIN_NO(8) | 7) + +#define PINMUX_GPIO9__FUNC_GPIO9 (MTK_PIN_NO(9) | 0) +#define PINMUX_GPIO9__FUNC_PERSTN (MTK_PIN_NO(9) | 1) +#define PINMUX_GPIO9__FUNC_SPM_DVS_0 (MTK_PIN_NO(9) | 2) +#define PINMUX_GPIO9__FUNC_DSI1_TE (MTK_PIN_NO(9) | 3) +#define PINMUX_GPIO9__FUNC_ANT_SEL3 (MTK_PIN_NO(9) | 4) + +#define PINMUX_GPIO10__FUNC_GPIO10 (MTK_PIN_NO(10) | 0) +#define PINMUX_GPIO10__FUNC_CLKREQN (MTK_PIN_NO(10) | 1) +#define PINMUX_GPIO10__FUNC_SPM_DVS_1 (MTK_PIN_NO(10) | 2) +#define PINMUX_GPIO10__FUNC_LCM1_RST (MTK_PIN_NO(10) | 3) +#define PINMUX_GPIO10__FUNC_ANT_SEL4 (MTK_PIN_NO(10) | 4) + +#define PINMUX_GPIO11__FUNC_GPIO11 (MTK_PIN_NO(11) | 0) +#define PINMUX_GPIO11__FUNC_WAKEN (MTK_PIN_NO(11) | 1) +#define PINMUX_GPIO11__FUNC_CMFLASH2 (MTK_PIN_NO(11) | 4) + +#define PINMUX_GPIO12__FUNC_GPIO12 (MTK_PIN_NO(12) | 0) +#define PINMUX_GPIO12__FUNC_EPDC_DPI_DATA0 (MTK_PIN_NO(12) | 1) +#define PINMUX_GPIO12__FUNC_GBE_TXD3 (MTK_PIN_NO(12) | 2) +#define PINMUX_GPIO12__FUNC_SPIM1_A_CSB (MTK_PIN_NO(12) | 3) +#define PINMUX_GPIO12__FUNC_SPLIN_MCK (MTK_PIN_NO(12) | 4) +#define PINMUX_GPIO12__FUNC_DPI_DATA0 (MTK_PIN_NO(12) | 5) +#define PINMUX_GPIO12__FUNC_ANT_SEL7 (MTK_PIN_NO(12) | 6) +#define PINMUX_GPIO12__FUNC_DBG_MON_A6 (MTK_PIN_NO(12) | 7) + +#define PINMUX_GPIO13__FUNC_GPIO13 (MTK_PIN_NO(13) | 0) +#define PINMUX_GPIO13__FUNC_EPDC_DPI_DATA1 (MTK_PIN_NO(13) | 1) +#define PINMUX_GPIO13__FUNC_GBE_TXD2 (MTK_PIN_NO(13) | 2) +#define PINMUX_GPIO13__FUNC_SPIM1_A_CLK (MTK_PIN_NO(13) | 3) +#define PINMUX_GPIO13__FUNC_SPLIN_LRCK (MTK_PIN_NO(13) | 4) +#define PINMUX_GPIO13__FUNC_DPI_DATA1 (MTK_PIN_NO(13) | 5) +#define PINMUX_GPIO13__FUNC_ANT_SEL8 (MTK_PIN_NO(13) | 6) +#define PINMUX_GPIO13__FUNC_CONN_MCU_AICE_TCKC (MTK_PIN_NO(13) | 7) + +#define PINMUX_GPIO14__FUNC_GPIO14 (MTK_PIN_NO(14) | 0) +#define PINMUX_GPIO14__FUNC_EPDC_DPI_DATA2 (MTK_PIN_NO(14) | 1) +#define PINMUX_GPIO14__FUNC_GBE_TXD1 (MTK_PIN_NO(14) | 2) +#define PINMUX_GPIO14__FUNC_SPIM1_A_MO (MTK_PIN_NO(14) | 3) +#define PINMUX_GPIO14__FUNC_SPLIN_BCK (MTK_PIN_NO(14) | 4) +#define PINMUX_GPIO14__FUNC_DPI_DATA2 (MTK_PIN_NO(14) | 5) +#define PINMUX_GPIO14__FUNC_ANT_SEL9 (MTK_PIN_NO(14) | 6) +#define PINMUX_GPIO14__FUNC_CONN_MCU_AICE_TMSC (MTK_PIN_NO(14) | 7) + +#define PINMUX_GPIO15__FUNC_GPIO15 (MTK_PIN_NO(15) | 0) +#define PINMUX_GPIO15__FUNC_EPDC_DPI_DATA3 (MTK_PIN_NO(15) | 1) +#define PINMUX_GPIO15__FUNC_GBE_TXD0 (MTK_PIN_NO(15) | 2) +#define PINMUX_GPIO15__FUNC_SPIM1_A_MI (MTK_PIN_NO(15) | 3) +#define PINMUX_GPIO15__FUNC_SPLIN_D0 (MTK_PIN_NO(15) | 4) +#define PINMUX_GPIO15__FUNC_DPI_DATA3 (MTK_PIN_NO(15) | 5) +#define PINMUX_GPIO15__FUNC_ANT_SEL10 (MTK_PIN_NO(15) | 6) +#define PINMUX_GPIO15__FUNC_DBG_MON_A5 (MTK_PIN_NO(15) | 7) + +#define PINMUX_GPIO16__FUNC_GPIO16 (MTK_PIN_NO(16) | 0) +#define PINMUX_GPIO16__FUNC_EPDC_DPI_DATA4 (MTK_PIN_NO(16) | 1) +#define PINMUX_GPIO16__FUNC_GBE_RXD3 (MTK_PIN_NO(16) | 2) +#define PINMUX_GPIO16__FUNC_SPIM2_A_CSB (MTK_PIN_NO(16) | 3) +#define PINMUX_GPIO16__FUNC_SPLIN_D1 (MTK_PIN_NO(16) | 4) +#define PINMUX_GPIO16__FUNC_DPI_DATA4 (MTK_PIN_NO(16) | 5) +#define PINMUX_GPIO16__FUNC_URXD1 (MTK_PIN_NO(16) | 6) +#define PINMUX_GPIO16__FUNC_DBG_MON_A7 (MTK_PIN_NO(16) | 7) + +#define PINMUX_GPIO17__FUNC_GPIO17 (MTK_PIN_NO(17) | 0) +#define PINMUX_GPIO17__FUNC_EPDC_DPI_DATA5 (MTK_PIN_NO(17) | 1) +#define PINMUX_GPIO17__FUNC_GBE_RXD2 (MTK_PIN_NO(17) | 2) +#define PINMUX_GPIO17__FUNC_SPIM2_A_CLK (MTK_PIN_NO(17) | 3) +#define PINMUX_GPIO17__FUNC_SPLIN_D2 (MTK_PIN_NO(17) | 4) +#define PINMUX_GPIO17__FUNC_DPI_DATA5 (MTK_PIN_NO(17) | 5) +#define PINMUX_GPIO17__FUNC_UTXD1 (MTK_PIN_NO(17) | 6) +#define PINMUX_GPIO17__FUNC_DBG_MON_A8 (MTK_PIN_NO(17) | 7) + +#define PINMUX_GPIO18__FUNC_GPIO18 (MTK_PIN_NO(18) | 0) +#define PINMUX_GPIO18__FUNC_EPDC_DPI_DATA6 (MTK_PIN_NO(18) | 1) +#define PINMUX_GPIO18__FUNC_GBE_RXD1 (MTK_PIN_NO(18) | 2) +#define PINMUX_GPIO18__FUNC_SPIM2_A_MO (MTK_PIN_NO(18) | 3) +#define PINMUX_GPIO18__FUNC_SPLIN_D3 (MTK_PIN_NO(18) | 4) +#define PINMUX_GPIO18__FUNC_DPI_DATA6 (MTK_PIN_NO(18) | 5) +#define PINMUX_GPIO18__FUNC_UCTS1 (MTK_PIN_NO(18) | 6) +#define PINMUX_GPIO18__FUNC_DBG_MON_A9 (MTK_PIN_NO(18) | 7) + +#define PINMUX_GPIO19__FUNC_GPIO19 (MTK_PIN_NO(19) | 0) +#define PINMUX_GPIO19__FUNC_EPDC_DPI_DATA7 (MTK_PIN_NO(19) | 1) +#define PINMUX_GPIO19__FUNC_GBE_RXD0 (MTK_PIN_NO(19) | 2) +#define PINMUX_GPIO19__FUNC_SPIM2_A_MI (MTK_PIN_NO(19) | 3) +#define PINMUX_GPIO19__FUNC_CONN_TSF (MTK_PIN_NO(19) | 4) +#define PINMUX_GPIO19__FUNC_DPI_DATA7 (MTK_PIN_NO(19) | 5) +#define PINMUX_GPIO19__FUNC_URTS1 (MTK_PIN_NO(19) | 6) +#define PINMUX_GPIO19__FUNC_DBG_MON_A10 (MTK_PIN_NO(19) | 7) + +#define PINMUX_GPIO20__FUNC_GPIO20 (MTK_PIN_NO(20) | 0) +#define PINMUX_GPIO20__FUNC_EPDC_DPI_DATA8 (MTK_PIN_NO(20) | 1) +#define PINMUX_GPIO20__FUNC_GBE_TXC (MTK_PIN_NO(20) | 2) +#define PINMUX_GPIO20__FUNC_SPIM3_A_CSB (MTK_PIN_NO(20) | 3) +#define PINMUX_GPIO20__FUNC_DPI_DATA8 (MTK_PIN_NO(20) | 5) +#define PINMUX_GPIO20__FUNC_UTXD2 (MTK_PIN_NO(20) | 6) +#define PINMUX_GPIO20__FUNC_DBG_MON_A11 (MTK_PIN_NO(20) | 7) + +#define PINMUX_GPIO21__FUNC_GPIO21 (MTK_PIN_NO(21) | 0) +#define PINMUX_GPIO21__FUNC_EPDC_DPI_DATA9 (MTK_PIN_NO(21) | 1) +#define PINMUX_GPIO21__FUNC_GBE_RXC (MTK_PIN_NO(21) | 2) +#define PINMUX_GPIO21__FUNC_SPIM3_A_CLK (MTK_PIN_NO(21) | 3) +#define PINMUX_GPIO21__FUNC_DPI_DATA9 (MTK_PIN_NO(21) | 5) +#define PINMUX_GPIO21__FUNC_URXD2 (MTK_PIN_NO(21) | 6) +#define PINMUX_GPIO21__FUNC_DBG_MON_A12 (MTK_PIN_NO(21) | 7) + +#define PINMUX_GPIO22__FUNC_GPIO22 (MTK_PIN_NO(22) | 0) +#define PINMUX_GPIO22__FUNC_EPDC_DPI_DATA10 (MTK_PIN_NO(22) | 1) +#define PINMUX_GPIO22__FUNC_GBE_RXDV (MTK_PIN_NO(22) | 2) +#define PINMUX_GPIO22__FUNC_SPIM3_A_MO (MTK_PIN_NO(22) | 3) +#define PINMUX_GPIO22__FUNC_DPI_DATA10 (MTK_PIN_NO(22) | 5) +#define PINMUX_GPIO22__FUNC_UCTS2 (MTK_PIN_NO(22) | 6) +#define PINMUX_GPIO22__FUNC_DBG_MON_A13 (MTK_PIN_NO(22) | 7) + +#define PINMUX_GPIO23__FUNC_GPIO23 (MTK_PIN_NO(23) | 0) +#define PINMUX_GPIO23__FUNC_EPDC_DPI_DATA11 (MTK_PIN_NO(23) | 1) +#define PINMUX_GPIO23__FUNC_GBE_TXEN (MTK_PIN_NO(23) | 2) +#define PINMUX_GPIO23__FUNC_SPIM3_A_MI (MTK_PIN_NO(23) | 3) +#define PINMUX_GPIO23__FUNC_DPI_DATA11 (MTK_PIN_NO(23) | 5) +#define PINMUX_GPIO23__FUNC_URTS2 (MTK_PIN_NO(23) | 6) +#define PINMUX_GPIO23__FUNC_DBG_MON_A14 (MTK_PIN_NO(23) | 7) + +#define PINMUX_GPIO24__FUNC_GPIO24 (MTK_PIN_NO(24) | 0) +#define PINMUX_GPIO24__FUNC_EPDC_DPI_DATA12 (MTK_PIN_NO(24) | 1) +#define PINMUX_GPIO24__FUNC_GBE_MDC (MTK_PIN_NO(24) | 2) +#define PINMUX_GPIO24__FUNC_SPIM4_A_CSB (MTK_PIN_NO(24) | 3) +#define PINMUX_GPIO24__FUNC_DPI_DATA12 (MTK_PIN_NO(24) | 5) +#define PINMUX_GPIO24__FUNC_UCTS3 (MTK_PIN_NO(24) | 6) +#define PINMUX_GPIO24__FUNC_DBG_MON_A15 (MTK_PIN_NO(24) | 7) + +#define PINMUX_GPIO25__FUNC_GPIO25 (MTK_PIN_NO(25) | 0) +#define PINMUX_GPIO25__FUNC_EPDC_DPI_DATA13 (MTK_PIN_NO(25) | 1) +#define PINMUX_GPIO25__FUNC_GBE_MDIO (MTK_PIN_NO(25) | 2) +#define PINMUX_GPIO25__FUNC_SPIM4_A_CLK (MTK_PIN_NO(25) | 3) +#define PINMUX_GPIO25__FUNC_DPI_DATA13 (MTK_PIN_NO(25) | 5) +#define PINMUX_GPIO25__FUNC_URTS3 (MTK_PIN_NO(25) | 6) +#define PINMUX_GPIO25__FUNC_DBG_MON_A16 (MTK_PIN_NO(25) | 7) + +#define PINMUX_GPIO26__FUNC_GPIO26 (MTK_PIN_NO(26) | 0) +#define PINMUX_GPIO26__FUNC_EPDC_DPI_DATA14 (MTK_PIN_NO(26) | 1) +#define PINMUX_GPIO26__FUNC_GBE_TXER (MTK_PIN_NO(26) | 2) +#define PINMUX_GPIO26__FUNC_SPIM4_A_MO (MTK_PIN_NO(26) | 3) +#define PINMUX_GPIO26__FUNC_GBE_AUX_PPS2 (MTK_PIN_NO(26) | 4) +#define PINMUX_GPIO26__FUNC_DPI_DATA14 (MTK_PIN_NO(26) | 5) +#define PINMUX_GPIO26__FUNC_URXD3 (MTK_PIN_NO(26) | 6) +#define PINMUX_GPIO26__FUNC_DBG_MON_A17 (MTK_PIN_NO(26) | 7) + +#define PINMUX_GPIO27__FUNC_GPIO27 (MTK_PIN_NO(27) | 0) +#define PINMUX_GPIO27__FUNC_EPDC_DPI_DATA15 (MTK_PIN_NO(27) | 1) +#define PINMUX_GPIO27__FUNC_GBE_RXER (MTK_PIN_NO(27) | 2) +#define PINMUX_GPIO27__FUNC_SPIM4_A_MI (MTK_PIN_NO(27) | 3) +#define PINMUX_GPIO27__FUNC_GBE_AUX_PPS3 (MTK_PIN_NO(27) | 4) +#define PINMUX_GPIO27__FUNC_DPI_DATA15 (MTK_PIN_NO(27) | 5) +#define PINMUX_GPIO27__FUNC_UTXD3 (MTK_PIN_NO(27) | 6) +#define PINMUX_GPIO27__FUNC_DBG_MON_A18 (MTK_PIN_NO(27) | 7) + +#define PINMUX_GPIO28__FUNC_GPIO28 (MTK_PIN_NO(28) | 0) +#define PINMUX_GPIO28__FUNC_EPDC_DPI_DATA16 (MTK_PIN_NO(28) | 1) +#define PINMUX_GPIO28__FUNC_GBE_COL (MTK_PIN_NO(28) | 2) +#define PINMUX_GPIO28__FUNC_SPIM5_A_CSB (MTK_PIN_NO(28) | 3) +#define PINMUX_GPIO28__FUNC_ANT_SEL5 (MTK_PIN_NO(28) | 4) +#define PINMUX_GPIO28__FUNC_DPI_DATA16 (MTK_PIN_NO(28) | 5) +#define PINMUX_GPIO28__FUNC_DBG_MON_A19 (MTK_PIN_NO(28) | 7) + +#define PINMUX_GPIO29__FUNC_GPIO29 (MTK_PIN_NO(29) | 0) +#define PINMUX_GPIO29__FUNC_EPDC_DPI_DATA17 (MTK_PIN_NO(29) | 1) +#define PINMUX_GPIO29__FUNC_GBE_INTR (MTK_PIN_NO(29) | 2) +#define PINMUX_GPIO29__FUNC_SPIM5_A_CLK (MTK_PIN_NO(29) | 3) +#define PINMUX_GPIO29__FUNC_ANT_SEL6 (MTK_PIN_NO(29) | 4) +#define PINMUX_GPIO29__FUNC_DPI_DATA17 (MTK_PIN_NO(29) | 5) +#define PINMUX_GPIO29__FUNC_DBG_MON_A20 (MTK_PIN_NO(29) | 7) + +#define PINMUX_GPIO30__FUNC_GPIO30 (MTK_PIN_NO(30) | 0) +#define PINMUX_GPIO30__FUNC_EPDC_DPI_DATA18 (MTK_PIN_NO(30) | 1) +#define PINMUX_GPIO30__FUNC_GBE_AUX_PPS3 (MTK_PIN_NO(30) | 2) +#define PINMUX_GPIO30__FUNC_SPIM5_A_MO (MTK_PIN_NO(30) | 3) +#define PINMUX_GPIO30__FUNC_DMIC2_CLK (MTK_PIN_NO(30) | 4) +#define PINMUX_GPIO30__FUNC_DPI_DATA18 (MTK_PIN_NO(30) | 5) +#define PINMUX_GPIO30__FUNC_SPDIF_IN0 (MTK_PIN_NO(30) | 6) +#define PINMUX_GPIO30__FUNC_DBG_MON_A21 (MTK_PIN_NO(30) | 7) + +#define PINMUX_GPIO31__FUNC_GPIO31 (MTK_PIN_NO(31) | 0) +#define PINMUX_GPIO31__FUNC_EPDC_DPI_DATA19 (MTK_PIN_NO(31) | 1) +#define PINMUX_GPIO31__FUNC_GBE_AUX_PPS2 (MTK_PIN_NO(31) | 2) +#define PINMUX_GPIO31__FUNC_SPIM5_A_MI (MTK_PIN_NO(31) | 3) +#define PINMUX_GPIO31__FUNC_DMIC2_DAT0 (MTK_PIN_NO(31) | 4) +#define PINMUX_GPIO31__FUNC_DPI_DATA19 (MTK_PIN_NO(31) | 5) +#define PINMUX_GPIO31__FUNC_SPDIF_IN1 (MTK_PIN_NO(31) | 6) + +#define PINMUX_GPIO32__FUNC_GPIO32 (MTK_PIN_NO(32) | 0) +#define PINMUX_GPIO32__FUNC_EPDC_DPI_DATA20 (MTK_PIN_NO(32) | 1) +#define PINMUX_GPIO32__FUNC_GBE_AUX_PPS1 (MTK_PIN_NO(32) | 2) +#define PINMUX_GPIO32__FUNC_SPIM4_B_CSB (MTK_PIN_NO(32) | 3) +#define PINMUX_GPIO32__FUNC_DMIC2_DAT1 (MTK_PIN_NO(32) | 4) +#define PINMUX_GPIO32__FUNC_DPI_DATA20 (MTK_PIN_NO(32) | 5) +#define PINMUX_GPIO32__FUNC_SPDIF_OUT (MTK_PIN_NO(32) | 6) + +#define PINMUX_GPIO33__FUNC_GPIO33 (MTK_PIN_NO(33) | 0) +#define PINMUX_GPIO33__FUNC_EPDC_DPI_DATA21 (MTK_PIN_NO(33) | 1) +#define PINMUX_GPIO33__FUNC_GBE_AUX_PPS0 (MTK_PIN_NO(33) | 2) +#define PINMUX_GPIO33__FUNC_SPIM4_B_CLK (MTK_PIN_NO(33) | 3) +#define PINMUX_GPIO33__FUNC_DMIC3_CLK (MTK_PIN_NO(33) | 4) +#define PINMUX_GPIO33__FUNC_DPI_DATA21 (MTK_PIN_NO(33) | 5) +#define PINMUX_GPIO33__FUNC_IRRX_IN (MTK_PIN_NO(33) | 6) + +#define PINMUX_GPIO34__FUNC_GPIO34 (MTK_PIN_NO(34) | 0) +#define PINMUX_GPIO34__FUNC_EPDC_DPI_DATA22 (MTK_PIN_NO(34) | 1) +#define PINMUX_GPIO34__FUNC_ANT_SEL3 (MTK_PIN_NO(34) | 2) +#define PINMUX_GPIO34__FUNC_SPIM4_B_MO (MTK_PIN_NO(34) | 3) +#define PINMUX_GPIO34__FUNC_DMIC3_DAT0 (MTK_PIN_NO(34) | 4) +#define PINMUX_GPIO34__FUNC_DPI_DATA22 (MTK_PIN_NO(34) | 5) +#define PINMUX_GPIO34__FUNC_CAN0_TXD (MTK_PIN_NO(34) | 6) +#define PINMUX_GPIO34__FUNC_CONN_TSF (MTK_PIN_NO(34) | 7) + +#define PINMUX_GPIO35__FUNC_GPIO35 (MTK_PIN_NO(35) | 0) +#define PINMUX_GPIO35__FUNC_EPDC_DPI_DATA23 (MTK_PIN_NO(35) | 1) +#define PINMUX_GPIO35__FUNC_ANT_SEL4 (MTK_PIN_NO(35) | 2) +#define PINMUX_GPIO35__FUNC_SPIM4_B_MI (MTK_PIN_NO(35) | 3) +#define PINMUX_GPIO35__FUNC_DMIC3_DAT1 (MTK_PIN_NO(35) | 4) +#define PINMUX_GPIO35__FUNC_DPI_DATA23 (MTK_PIN_NO(35) | 5) +#define PINMUX_GPIO35__FUNC_CAN0_RXD (MTK_PIN_NO(35) | 6) + +#define PINMUX_GPIO36__FUNC_GPIO36 (MTK_PIN_NO(36) | 0) +#define PINMUX_GPIO36__FUNC_EPDC_SDCLK (MTK_PIN_NO(36) | 1) +#define PINMUX_GPIO36__FUNC_NCEB0 (MTK_PIN_NO(36) | 2) +#define PINMUX_GPIO36__FUNC_SPIM5_B_CSB (MTK_PIN_NO(36) | 3) +#define PINMUX_GPIO36__FUNC_UTXD2 (MTK_PIN_NO(36) | 4) +#define PINMUX_GPIO36__FUNC_DPI_PCLK (MTK_PIN_NO(36) | 5) +#define PINMUX_GPIO36__FUNC_UCTS3 (MTK_PIN_NO(36) | 6) + +#define PINMUX_GPIO37__FUNC_GPIO37 (MTK_PIN_NO(37) | 0) +#define PINMUX_GPIO37__FUNC_EPDC_SDLE (MTK_PIN_NO(37) | 1) +#define PINMUX_GPIO37__FUNC_NCEB1 (MTK_PIN_NO(37) | 2) +#define PINMUX_GPIO37__FUNC_SPIM5_B_CLK (MTK_PIN_NO(37) | 3) +#define PINMUX_GPIO37__FUNC_URXD2 (MTK_PIN_NO(37) | 4) +#define PINMUX_GPIO37__FUNC_URTS3 (MTK_PIN_NO(37) | 6) + +#define PINMUX_GPIO38__FUNC_GPIO38 (MTK_PIN_NO(38) | 0) +#define PINMUX_GPIO38__FUNC_EPDC_SDOE (MTK_PIN_NO(38) | 1) +#define PINMUX_GPIO38__FUNC_NRNB (MTK_PIN_NO(38) | 2) +#define PINMUX_GPIO38__FUNC_SPIM5_B_MO (MTK_PIN_NO(38) | 3) +#define PINMUX_GPIO38__FUNC_UCTS2 (MTK_PIN_NO(38) | 4) +#define PINMUX_GPIO38__FUNC_URXD3 (MTK_PIN_NO(38) | 6) + +#define PINMUX_GPIO39__FUNC_GPIO39 (MTK_PIN_NO(39) | 0) +#define PINMUX_GPIO39__FUNC_EPDC_GDCLK (MTK_PIN_NO(39) | 1) +#define PINMUX_GPIO39__FUNC_NLD7 (MTK_PIN_NO(39) | 2) +#define PINMUX_GPIO39__FUNC_SPIM5_B_MI (MTK_PIN_NO(39) | 3) +#define PINMUX_GPIO39__FUNC_URTS2 (MTK_PIN_NO(39) | 4) +#define PINMUX_GPIO39__FUNC_DPI_HSYNC (MTK_PIN_NO(39) | 5) +#define PINMUX_GPIO39__FUNC_UTXD3 (MTK_PIN_NO(39) | 6) + +#define PINMUX_GPIO40__FUNC_GPIO40 (MTK_PIN_NO(40) | 0) +#define PINMUX_GPIO40__FUNC_EPDC_GDOE (MTK_PIN_NO(40) | 1) +#define PINMUX_GPIO40__FUNC_NLD6 (MTK_PIN_NO(40) | 2) +#define PINMUX_GPIO40__FUNC_SPIM2_B_CSB (MTK_PIN_NO(40) | 3) +#define PINMUX_GPIO40__FUNC_UCTS3 (MTK_PIN_NO(40) | 4) +#define PINMUX_GPIO40__FUNC_DPI_DE (MTK_PIN_NO(40) | 5) +#define PINMUX_GPIO40__FUNC_UTXD2 (MTK_PIN_NO(40) | 6) + +#define PINMUX_GPIO41__FUNC_GPIO41 (MTK_PIN_NO(41) | 0) +#define PINMUX_GPIO41__FUNC_EPDC_GDSP (MTK_PIN_NO(41) | 1) +#define PINMUX_GPIO41__FUNC_NLD5 (MTK_PIN_NO(41) | 2) +#define PINMUX_GPIO41__FUNC_SPIM2_B_CLK (MTK_PIN_NO(41) | 3) +#define PINMUX_GPIO41__FUNC_URTS3 (MTK_PIN_NO(41) | 4) +#define PINMUX_GPIO41__FUNC_DPI_VSYNC (MTK_PIN_NO(41) | 5) +#define PINMUX_GPIO41__FUNC_URXD2 (MTK_PIN_NO(41) | 6) + +#define PINMUX_GPIO42__FUNC_GPIO42 (MTK_PIN_NO(42) | 0) +#define PINMUX_GPIO42__FUNC_EPDC_GDRST (MTK_PIN_NO(42) | 1) +#define PINMUX_GPIO42__FUNC_NLD4 (MTK_PIN_NO(42) | 2) +#define PINMUX_GPIO42__FUNC_SPIM2_B_MO (MTK_PIN_NO(42) | 3) +#define PINMUX_GPIO42__FUNC_URXD3 (MTK_PIN_NO(42) | 4) +#define PINMUX_GPIO42__FUNC_CAN0_TXD (MTK_PIN_NO(42) | 5) +#define PINMUX_GPIO42__FUNC_UCTS2 (MTK_PIN_NO(42) | 6) + +#define PINMUX_GPIO43__FUNC_GPIO43 (MTK_PIN_NO(43) | 0) +#define PINMUX_GPIO43__FUNC_EPDC_STV (MTK_PIN_NO(43) | 1) +#define PINMUX_GPIO43__FUNC_NLD3 (MTK_PIN_NO(43) | 2) +#define PINMUX_GPIO43__FUNC_SPIM2_B_MI (MTK_PIN_NO(43) | 3) +#define PINMUX_GPIO43__FUNC_UTXD3 (MTK_PIN_NO(43) | 4) +#define PINMUX_GPIO43__FUNC_CAN0_RXD (MTK_PIN_NO(43) | 5) +#define PINMUX_GPIO43__FUNC_URTS2 (MTK_PIN_NO(43) | 6) + +#define PINMUX_GPIO44__FUNC_GPIO44 (MTK_PIN_NO(44) | 0) +#define PINMUX_GPIO44__FUNC_EPDC_GDRSTB (MTK_PIN_NO(44) | 1) +#define PINMUX_GPIO44__FUNC_NLD2 (MTK_PIN_NO(44) | 2) +#define PINMUX_GPIO44__FUNC_CLKM0 (MTK_PIN_NO(44) | 3) +#define PINMUX_GPIO44__FUNC_DP_TX_HPD (MTK_PIN_NO(44) | 4) +#define PINMUX_GPIO44__FUNC_UTXD2 (MTK_PIN_NO(44) | 5) + +#define PINMUX_GPIO45__FUNC_GPIO45 (MTK_PIN_NO(45) | 0) +#define PINMUX_GPIO45__FUNC_EPDC_SDCE0 (MTK_PIN_NO(45) | 1) +#define PINMUX_GPIO45__FUNC_NLD1 (MTK_PIN_NO(45) | 2) +#define PINMUX_GPIO45__FUNC_CLKM1 (MTK_PIN_NO(45) | 3) +#define PINMUX_GPIO45__FUNC_CMFLASH0 (MTK_PIN_NO(45) | 4) +#define PINMUX_GPIO45__FUNC_URXD2 (MTK_PIN_NO(45) | 5) + +#define PINMUX_GPIO46__FUNC_GPIO46 (MTK_PIN_NO(46) | 0) +#define PINMUX_GPIO46__FUNC_EPDC_SDCE1 (MTK_PIN_NO(46) | 1) +#define PINMUX_GPIO46__FUNC_NLD0 (MTK_PIN_NO(46) | 2) +#define PINMUX_GPIO46__FUNC_CLKM2 (MTK_PIN_NO(46) | 3) +#define PINMUX_GPIO46__FUNC_CMFLASH1 (MTK_PIN_NO(46) | 4) + +#define PINMUX_GPIO47__FUNC_GPIO47 (MTK_PIN_NO(47) | 0) +#define PINMUX_GPIO47__FUNC_EPDC_SDCE2 (MTK_PIN_NO(47) | 1) +#define PINMUX_GPIO47__FUNC_NALE (MTK_PIN_NO(47) | 2) +#define PINMUX_GPIO47__FUNC_CLKM3 (MTK_PIN_NO(47) | 3) +#define PINMUX_GPIO47__FUNC_CMMCLK0 (MTK_PIN_NO(47) | 4) + +#define PINMUX_GPIO48__FUNC_GPIO48 (MTK_PIN_NO(48) | 0) +#define PINMUX_GPIO48__FUNC_EPDC_SDCE3 (MTK_PIN_NO(48) | 1) +#define PINMUX_GPIO48__FUNC_NCLE (MTK_PIN_NO(48) | 2) +#define PINMUX_GPIO48__FUNC_PWM_0 (MTK_PIN_NO(48) | 3) +#define PINMUX_GPIO48__FUNC_CMFLASH2 (MTK_PIN_NO(48) | 4) +#define PINMUX_GPIO48__FUNC_DMIC1_CLK (MTK_PIN_NO(48) | 5) + +#define PINMUX_GPIO49__FUNC_GPIO49 (MTK_PIN_NO(49) | 0) +#define PINMUX_GPIO49__FUNC_EPDC_VCOM_0 (MTK_PIN_NO(49) | 1) +#define PINMUX_GPIO49__FUNC_NWEB (MTK_PIN_NO(49) | 2) +#define PINMUX_GPIO49__FUNC_PWM_1 (MTK_PIN_NO(49) | 3) +#define PINMUX_GPIO49__FUNC_CMFLASH3 (MTK_PIN_NO(49) | 4) +#define PINMUX_GPIO49__FUNC_DMIC1_DAT0 (MTK_PIN_NO(49) | 5) + +#define PINMUX_GPIO50__FUNC_GPIO50 (MTK_PIN_NO(50) | 0) +#define PINMUX_GPIO50__FUNC_EPDC_VCOM_1 (MTK_PIN_NO(50) | 1) +#define PINMUX_GPIO50__FUNC_NREB (MTK_PIN_NO(50) | 2) +#define PINMUX_GPIO50__FUNC_PWM_2 (MTK_PIN_NO(50) | 3) +#define PINMUX_GPIO50__FUNC_CMMCLK1 (MTK_PIN_NO(50) | 4) +#define PINMUX_GPIO50__FUNC_DMIC1_DAT1 (MTK_PIN_NO(50) | 5) + +#define PINMUX_GPIO51__FUNC_GPIO51 (MTK_PIN_NO(51) | 0) +#define PINMUX_GPIO51__FUNC_EPDC_STH2 (MTK_PIN_NO(51) | 1) +#define PINMUX_GPIO51__FUNC_DISP_PWM1 (MTK_PIN_NO(51) | 2) +#define PINMUX_GPIO51__FUNC_CONN_TSF (MTK_PIN_NO(51) | 3) +#define PINMUX_GPIO51__FUNC_CMFLASH3 (MTK_PIN_NO(51) | 4) + +#define PINMUX_GPIO52__FUNC_GPIO52 (MTK_PIN_NO(52) | 0) +#define PINMUX_GPIO52__FUNC_IDDIG (MTK_PIN_NO(52) | 1) +#define PINMUX_GPIO52__FUNC_DBG_MON_B10 (MTK_PIN_NO(52) | 7) + +#define PINMUX_GPIO53__FUNC_GPIO53 (MTK_PIN_NO(53) | 0) +#define PINMUX_GPIO53__FUNC_USB_DRVVBUS (MTK_PIN_NO(53) | 1) +#define PINMUX_GPIO53__FUNC_DBG_MON_B11 (MTK_PIN_NO(53) | 7) + +#define PINMUX_GPIO54__FUNC_GPIO54 (MTK_PIN_NO(54) | 0) +#define PINMUX_GPIO54__FUNC_VBUSVALID (MTK_PIN_NO(54) | 1) +#define PINMUX_GPIO54__FUNC_DBG_MON_B12 (MTK_PIN_NO(54) | 7) + +#define PINMUX_GPIO55__FUNC_GPIO55 (MTK_PIN_NO(55) | 0) +#define PINMUX_GPIO55__FUNC_USB_DRVVBUS_1P (MTK_PIN_NO(55) | 1) +#define PINMUX_GPIO55__FUNC_DBG_MON_B13 (MTK_PIN_NO(55) | 7) + +#define PINMUX_GPIO56__FUNC_GPIO56 (MTK_PIN_NO(56) | 0) +#define PINMUX_GPIO56__FUNC_USB_DRVVBUS_2P (MTK_PIN_NO(56) | 1) + +#define PINMUX_GPIO57__FUNC_GPIO57 (MTK_PIN_NO(57) | 0) +#define PINMUX_GPIO57__FUNC_CMFLASH0 (MTK_PIN_NO(57) | 1) +#define PINMUX_GPIO57__FUNC_SPINOR_CK (MTK_PIN_NO(57) | 2) +#define PINMUX_GPIO57__FUNC_I2SOUT5_DATA3 (MTK_PIN_NO(57) | 3) +#define PINMUX_GPIO57__FUNC_ANT_SEL10 (MTK_PIN_NO(57) | 4) +#define PINMUX_GPIO57__FUNC_ANT_SEL7 (MTK_PIN_NO(57) | 5) +#define PINMUX_GPIO57__FUNC_CONN_BPI_BUS15_OLAT4 (MTK_PIN_NO(57) | 6) +#define PINMUX_GPIO57__FUNC_DBG_MON_B15 (MTK_PIN_NO(57) | 7) + +#define PINMUX_GPIO58__FUNC_GPIO58 (MTK_PIN_NO(58) | 0) +#define PINMUX_GPIO58__FUNC_CMFLASH1 (MTK_PIN_NO(58) | 1) +#define PINMUX_GPIO58__FUNC_SPINOR_CS (MTK_PIN_NO(58) | 2) +#define PINMUX_GPIO58__FUNC_I2SOUT5_MCK (MTK_PIN_NO(58) | 3) +#define PINMUX_GPIO58__FUNC_ANT_SEL11 (MTK_PIN_NO(58) | 4) +#define PINMUX_GPIO58__FUNC_ANT_SEL8 (MTK_PIN_NO(58) | 5) +#define PINMUX_GPIO58__FUNC_CONN_BPI_BUS16_OLAT5 (MTK_PIN_NO(58) | 6) +#define PINMUX_GPIO58__FUNC_DBG_MON_B16 (MTK_PIN_NO(58) | 7) + +#define PINMUX_GPIO59__FUNC_GPIO59 (MTK_PIN_NO(59) | 0) +#define PINMUX_GPIO59__FUNC_CMMCLK0 (MTK_PIN_NO(59) | 1) +#define PINMUX_GPIO59__FUNC_SPINOR_IO0 (MTK_PIN_NO(59) | 2) +#define PINMUX_GPIO59__FUNC_I2SOUT5_BCK (MTK_PIN_NO(59) | 3) +#define PINMUX_GPIO59__FUNC_ANT_SEL12 (MTK_PIN_NO(59) | 4) +#define PINMUX_GPIO59__FUNC_ANT_SEL9 (MTK_PIN_NO(59) | 5) +#define PINMUX_GPIO59__FUNC_CONN_BPI_BUS17_ANT0 (MTK_PIN_NO(59) | 6) +#define PINMUX_GPIO59__FUNC_DBG_MON_B17 (MTK_PIN_NO(59) | 7) + +#define PINMUX_GPIO60__FUNC_GPIO60 (MTK_PIN_NO(60) | 0) +#define PINMUX_GPIO60__FUNC_CMFLASH2 (MTK_PIN_NO(60) | 1) +#define PINMUX_GPIO60__FUNC_SPINOR_IO1 (MTK_PIN_NO(60) | 2) +#define PINMUX_GPIO60__FUNC_I2SOUT5_LRCK (MTK_PIN_NO(60) | 3) +#define PINMUX_GPIO60__FUNC_DMIC3_CLK (MTK_PIN_NO(60) | 4) +#define PINMUX_GPIO60__FUNC_ANT_SEL11 (MTK_PIN_NO(60) | 5) +#define PINMUX_GPIO60__FUNC_CONN_BPI_BUS18_ANT1 (MTK_PIN_NO(60) | 6) +#define PINMUX_GPIO60__FUNC_EXTIF0_ACT (MTK_PIN_NO(60) | 7) + +#define PINMUX_GPIO61__FUNC_GPIO61 (MTK_PIN_NO(61) | 0) +#define PINMUX_GPIO61__FUNC_CMFLASH3 (MTK_PIN_NO(61) | 1) +#define PINMUX_GPIO61__FUNC_SPINOR_IO2 (MTK_PIN_NO(61) | 2) +#define PINMUX_GPIO61__FUNC_CONN_BPI_BUS6 (MTK_PIN_NO(61) | 3) +#define PINMUX_GPIO61__FUNC_DMIC3_DAT0 (MTK_PIN_NO(61) | 4) +#define PINMUX_GPIO61__FUNC_ANT_SEL12 (MTK_PIN_NO(61) | 5) +#define PINMUX_GPIO61__FUNC_CONN_BPI_BUS19_ANT2 (MTK_PIN_NO(61) | 6) +#define PINMUX_GPIO61__FUNC_EXTIF0_PRI (MTK_PIN_NO(61) | 7) + +#define PINMUX_GPIO62__FUNC_GPIO62 (MTK_PIN_NO(62) | 0) +#define PINMUX_GPIO62__FUNC_CMMCLK1 (MTK_PIN_NO(62) | 1) +#define PINMUX_GPIO62__FUNC_SPINOR_IO3 (MTK_PIN_NO(62) | 2) +#define PINMUX_GPIO62__FUNC_CONN_BPI_BUS7 (MTK_PIN_NO(62) | 3) +#define PINMUX_GPIO62__FUNC_DMIC3_DAT1 (MTK_PIN_NO(62) | 4) +#define PINMUX_GPIO62__FUNC_CONN_TSF (MTK_PIN_NO(62) | 5) +#define PINMUX_GPIO62__FUNC_CONN_BPI_BUS20_ANT3 (MTK_PIN_NO(62) | 6) +#define PINMUX_GPIO62__FUNC_EXTIF0_GNT_B (MTK_PIN_NO(62) | 7) + +#define PINMUX_GPIO63__FUNC_GPIO63 (MTK_PIN_NO(63) | 0) +#define PINMUX_GPIO63__FUNC_DSI_TE (MTK_PIN_NO(63) | 1) +#define PINMUX_GPIO63__FUNC_I2SOUT6_MCK (MTK_PIN_NO(63) | 2) + +#define PINMUX_GPIO64__FUNC_GPIO64 (MTK_PIN_NO(64) | 0) +#define PINMUX_GPIO64__FUNC_DISP_PWM0 (MTK_PIN_NO(64) | 1) +#define PINMUX_GPIO64__FUNC_I2SOUT6_BCK (MTK_PIN_NO(64) | 2) + +#define PINMUX_GPIO65__FUNC_GPIO65 (MTK_PIN_NO(65) | 0) +#define PINMUX_GPIO65__FUNC_LCM_RST (MTK_PIN_NO(65) | 1) +#define PINMUX_GPIO65__FUNC_I2SOUT6_LRCK (MTK_PIN_NO(65) | 2) + +#define PINMUX_GPIO66__FUNC_GPIO66 (MTK_PIN_NO(66) | 0) +#define PINMUX_GPIO66__FUNC_URXD0 (MTK_PIN_NO(66) | 1) + +#define PINMUX_GPIO67__FUNC_GPIO67 (MTK_PIN_NO(67) | 0) +#define PINMUX_GPIO67__FUNC_UTXD0 (MTK_PIN_NO(67) | 1) + +#define PINMUX_GPIO68__FUNC_GPIO68 (MTK_PIN_NO(68) | 0) +#define PINMUX_GPIO68__FUNC_URXD1 (MTK_PIN_NO(68) | 1) +#define PINMUX_GPIO68__FUNC_UCTS2 (MTK_PIN_NO(68) | 2) +#define PINMUX_GPIO68__FUNC_VADSP_URXD0 (MTK_PIN_NO(68) | 3) +#define PINMUX_GPIO68__FUNC_CONN_UART0_RXD (MTK_PIN_NO(68) | 4) +#define PINMUX_GPIO68__FUNC_MD32_0_RXD (MTK_PIN_NO(68) | 5) +#define PINMUX_GPIO68__FUNC_MD32_1_RXD (MTK_PIN_NO(68) | 6) +#define PINMUX_GPIO68__FUNC_mbistreaden_trigger (MTK_PIN_NO(68) | 7) + +#define PINMUX_GPIO69__FUNC_GPIO69 (MTK_PIN_NO(69) | 0) +#define PINMUX_GPIO69__FUNC_UTXD1 (MTK_PIN_NO(69) | 1) +#define PINMUX_GPIO69__FUNC_URTS2 (MTK_PIN_NO(69) | 2) +#define PINMUX_GPIO69__FUNC_VADSP_UTXD0 (MTK_PIN_NO(69) | 3) +#define PINMUX_GPIO69__FUNC_CONN_UART0_TXD (MTK_PIN_NO(69) | 4) +#define PINMUX_GPIO69__FUNC_MD32_0_TXD (MTK_PIN_NO(69) | 5) +#define PINMUX_GPIO69__FUNC_MD32_1_TXD (MTK_PIN_NO(69) | 6) +#define PINMUX_GPIO69__FUNC_CONN_WIFI_TXD (MTK_PIN_NO(69) | 7) + +#define PINMUX_GPIO70__FUNC_GPIO70 (MTK_PIN_NO(70) | 0) +#define PINMUX_GPIO70__FUNC_URXD2 (MTK_PIN_NO(70) | 1) +#define PINMUX_GPIO70__FUNC_UCTS1 (MTK_PIN_NO(70) | 2) +#define PINMUX_GPIO70__FUNC_SSPM_URXD_AO_VCORE (MTK_PIN_NO(70) | 3) +#define PINMUX_GPIO70__FUNC_CONN_UART0_RXD (MTK_PIN_NO(70) | 4) +#define PINMUX_GPIO70__FUNC_MD32_0_RXD (MTK_PIN_NO(70) | 5) +#define PINMUX_GPIO70__FUNC_MD32_1_RXD (MTK_PIN_NO(70) | 6) +#define PINMUX_GPIO70__FUNC_mbistwriteen_trigger (MTK_PIN_NO(70) | 7) + +#define PINMUX_GPIO71__FUNC_GPIO71 (MTK_PIN_NO(71) | 0) +#define PINMUX_GPIO71__FUNC_UTXD2 (MTK_PIN_NO(71) | 1) +#define PINMUX_GPIO71__FUNC_URTS1 (MTK_PIN_NO(71) | 2) +#define PINMUX_GPIO71__FUNC_SSPM_UTXD_AO_VCORE (MTK_PIN_NO(71) | 3) +#define PINMUX_GPIO71__FUNC_CONN_UART0_TXD (MTK_PIN_NO(71) | 4) +#define PINMUX_GPIO71__FUNC_MD32_0_TXD (MTK_PIN_NO(71) | 5) +#define PINMUX_GPIO71__FUNC_MD32_1_TXD (MTK_PIN_NO(71) | 6) +#define PINMUX_GPIO71__FUNC_CONN_WIFI_TXD (MTK_PIN_NO(71) | 7) + +#define PINMUX_GPIO72__FUNC_GPIO72 (MTK_PIN_NO(72) | 0) +#define PINMUX_GPIO72__FUNC_URXD3 (MTK_PIN_NO(72) | 1) +#define PINMUX_GPIO72__FUNC_UCTS0 (MTK_PIN_NO(72) | 2) +#define PINMUX_GPIO72__FUNC_VADSP_URXD0 (MTK_PIN_NO(72) | 3) +#define PINMUX_GPIO72__FUNC_SSPM_URXD_AO_VCORE (MTK_PIN_NO(72) | 4) +#define PINMUX_GPIO72__FUNC_MD32_0_GPIO0 (MTK_PIN_NO(72) | 5) +#define PINMUX_GPIO72__FUNC_MD32_1_GPIO0 (MTK_PIN_NO(72) | 6) + +#define PINMUX_GPIO73__FUNC_GPIO73 (MTK_PIN_NO(73) | 0) +#define PINMUX_GPIO73__FUNC_UTXD3 (MTK_PIN_NO(73) | 1) +#define PINMUX_GPIO73__FUNC_URTS0 (MTK_PIN_NO(73) | 2) +#define PINMUX_GPIO73__FUNC_VADSP_UTXD0 (MTK_PIN_NO(73) | 3) +#define PINMUX_GPIO73__FUNC_SSPM_UTXD_AO_VCORE (MTK_PIN_NO(73) | 4) +#define PINMUX_GPIO73__FUNC_MD32_0_GPIO0 (MTK_PIN_NO(73) | 5) +#define PINMUX_GPIO73__FUNC_MD32_1_GPIO0 (MTK_PIN_NO(73) | 6) +#define PINMUX_GPIO73__FUNC_CONN_WIFI_TXD (MTK_PIN_NO(73) | 7) + +#define PINMUX_GPIO74__FUNC_GPIO74 (MTK_PIN_NO(74) | 0) +#define PINMUX_GPIO74__FUNC_JTMS_SEL1 (MTK_PIN_NO(74) | 1) + +#define PINMUX_GPIO75__FUNC_GPIO75 (MTK_PIN_NO(75) | 0) +#define PINMUX_GPIO75__FUNC_JTCK_SEL1 (MTK_PIN_NO(75) | 1) + +#define PINMUX_GPIO76__FUNC_GPIO76 (MTK_PIN_NO(76) | 0) +#define PINMUX_GPIO76__FUNC_JTDI_SEL1 (MTK_PIN_NO(76) | 1) + +#define PINMUX_GPIO77__FUNC_GPIO77 (MTK_PIN_NO(77) | 0) +#define PINMUX_GPIO77__FUNC_JTDO_SEL1 (MTK_PIN_NO(77) | 1) + +#define PINMUX_GPIO78__FUNC_GPIO78 (MTK_PIN_NO(78) | 0) +#define PINMUX_GPIO78__FUNC_JTRSTn_SEL1 (MTK_PIN_NO(78) | 1) + +#define PINMUX_GPIO79__FUNC_GPIO79 (MTK_PIN_NO(79) | 0) +#define PINMUX_GPIO79__FUNC_KPCOL0 (MTK_PIN_NO(79) | 1) +#define PINMUX_GPIO79__FUNC_DBG_MON_B22 (MTK_PIN_NO(79) | 7) + +#define PINMUX_GPIO80__FUNC_GPIO80 (MTK_PIN_NO(80) | 0) +#define PINMUX_GPIO80__FUNC_KPCOL1 (MTK_PIN_NO(80) | 1) +#define PINMUX_GPIO80__FUNC_I2SIN5_DATA3 (MTK_PIN_NO(80) | 2) +#define PINMUX_GPIO80__FUNC_mbistreaden_trigger (MTK_PIN_NO(80) | 3) +#define PINMUX_GPIO80__FUNC_CONN_MCU_DBGI_N (MTK_PIN_NO(80) | 4) +#define PINMUX_GPIO80__FUNC_CONN_BPI_BUS21_ANT4 (MTK_PIN_NO(80) | 6) +#define PINMUX_GPIO80__FUNC_DBG_MON_B23 (MTK_PIN_NO(80) | 7) + +#define PINMUX_GPIO81__FUNC_GPIO81 (MTK_PIN_NO(81) | 0) +#define PINMUX_GPIO81__FUNC_KPROW0 (MTK_PIN_NO(81) | 1) +#define PINMUX_GPIO81__FUNC_DBG_MON_B24 (MTK_PIN_NO(81) | 7) + +#define PINMUX_GPIO82__FUNC_GPIO82 (MTK_PIN_NO(82) | 0) +#define PINMUX_GPIO82__FUNC_KPROW1 (MTK_PIN_NO(82) | 1) +#define PINMUX_GPIO82__FUNC_CONN_MIPI0_SDATA (MTK_PIN_NO(82) | 2) +#define PINMUX_GPIO82__FUNC_mbistwriteen_trigger (MTK_PIN_NO(82) | 3) +#define PINMUX_GPIO82__FUNC_CONN_MCU_DBGACK_N (MTK_PIN_NO(82) | 4) +#define PINMUX_GPIO82__FUNC_DBG_MON_B25 (MTK_PIN_NO(82) | 7) + +#define PINMUX_GPIO83__FUNC_GPIO83 (MTK_PIN_NO(83) | 0) +#define PINMUX_GPIO83__FUNC_DMIC0_CLK (MTK_PIN_NO(83) | 1) +#define PINMUX_GPIO83__FUNC_CONN_MIPI0_SCLK (MTK_PIN_NO(83) | 2) +#define PINMUX_GPIO83__FUNC_CONN_MCU_TCK (MTK_PIN_NO(83) | 3) +#define PINMUX_GPIO83__FUNC_SPM_JTAG_TCK (MTK_PIN_NO(83) | 4) +#define PINMUX_GPIO83__FUNC_UDI_TMS (MTK_PIN_NO(83) | 5) +#define PINMUX_GPIO83__FUNC_IPU_JTAG_TCK (MTK_PIN_NO(83) | 6) +#define PINMUX_GPIO83__FUNC_APU_JTAG_TCK (MTK_PIN_NO(83) | 7) + +#define PINMUX_GPIO84__FUNC_GPIO84 (MTK_PIN_NO(84) | 0) +#define PINMUX_GPIO84__FUNC_DMIC0_DAT0 (MTK_PIN_NO(84) | 1) +#define PINMUX_GPIO84__FUNC_CONN_MIPI1_SDATA (MTK_PIN_NO(84) | 2) +#define PINMUX_GPIO84__FUNC_CONN_MCU_TDI (MTK_PIN_NO(84) | 3) +#define PINMUX_GPIO84__FUNC_SPM_JTAG_TDI (MTK_PIN_NO(84) | 4) +#define PINMUX_GPIO84__FUNC_UDI_TCK (MTK_PIN_NO(84) | 5) +#define PINMUX_GPIO84__FUNC_IPU_JTAG_TDI (MTK_PIN_NO(84) | 6) +#define PINMUX_GPIO84__FUNC_APU_JTAG_TDI (MTK_PIN_NO(84) | 7) + +#define PINMUX_GPIO85__FUNC_GPIO85 (MTK_PIN_NO(85) | 0) +#define PINMUX_GPIO85__FUNC_DMIC0_DAT1 (MTK_PIN_NO(85) | 1) +#define PINMUX_GPIO85__FUNC_CONN_MIPI1_SCLK (MTK_PIN_NO(85) | 2) +#define PINMUX_GPIO85__FUNC_CONN_MCU_TDO (MTK_PIN_NO(85) | 3) +#define PINMUX_GPIO85__FUNC_SPM_JTAG_TDO (MTK_PIN_NO(85) | 4) +#define PINMUX_GPIO85__FUNC_UDI_TDI (MTK_PIN_NO(85) | 5) +#define PINMUX_GPIO85__FUNC_IPU_JTAG_TDO (MTK_PIN_NO(85) | 6) +#define PINMUX_GPIO85__FUNC_APU_JTAG_TDO (MTK_PIN_NO(85) | 7) + +#define PINMUX_GPIO86__FUNC_GPIO86 (MTK_PIN_NO(86) | 0) +#define PINMUX_GPIO86__FUNC_PCM0_CLK (MTK_PIN_NO(86) | 1) +#define PINMUX_GPIO86__FUNC_CONN_BPI_BUS8 (MTK_PIN_NO(86) | 2) +#define PINMUX_GPIO86__FUNC_CONN_MCU_TMS (MTK_PIN_NO(86) | 3) +#define PINMUX_GPIO86__FUNC_SPM_JTAG_TMS (MTK_PIN_NO(86) | 4) +#define PINMUX_GPIO86__FUNC_UDI_TDO (MTK_PIN_NO(86) | 5) +#define PINMUX_GPIO86__FUNC_IPU_JTAG_TMS (MTK_PIN_NO(86) | 6) +#define PINMUX_GPIO86__FUNC_APU_JTAG_TMS (MTK_PIN_NO(86) | 7) + +#define PINMUX_GPIO87__FUNC_GPIO87 (MTK_PIN_NO(87) | 0) +#define PINMUX_GPIO87__FUNC_PCM0_SYNC (MTK_PIN_NO(87) | 1) +#define PINMUX_GPIO87__FUNC_CONN_BPI_BUS9 (MTK_PIN_NO(87) | 2) +#define PINMUX_GPIO87__FUNC_CONN_MCU_TRST_B (MTK_PIN_NO(87) | 3) +#define PINMUX_GPIO87__FUNC_SPM_JTAG_TRSTN (MTK_PIN_NO(87) | 4) +#define PINMUX_GPIO87__FUNC_UDI_NTRST (MTK_PIN_NO(87) | 5) +#define PINMUX_GPIO87__FUNC_IPU_JTAG_TRST (MTK_PIN_NO(87) | 6) +#define PINMUX_GPIO87__FUNC_APU_JTAG_TRST (MTK_PIN_NO(87) | 7) + +#define PINMUX_GPIO88__FUNC_GPIO88 (MTK_PIN_NO(88) | 0) +#define PINMUX_GPIO88__FUNC_PCM0_DI (MTK_PIN_NO(88) | 1) +#define PINMUX_GPIO88__FUNC_CONN_BPI_BUS10 (MTK_PIN_NO(88) | 2) +#define PINMUX_GPIO88__FUNC_DBG_MON_B26 (MTK_PIN_NO(88) | 7) + +#define PINMUX_GPIO89__FUNC_GPIO89 (MTK_PIN_NO(89) | 0) +#define PINMUX_GPIO89__FUNC_PCM0_DO (MTK_PIN_NO(89) | 1) +#define PINMUX_GPIO89__FUNC_CONN_BPI_BUS11_OLAT0 (MTK_PIN_NO(89) | 2) +#define PINMUX_GPIO89__FUNC_DBG_MON_B27 (MTK_PIN_NO(89) | 7) + +#define PINMUX_GPIO90__FUNC_GPIO90 (MTK_PIN_NO(90) | 0) +#define PINMUX_GPIO90__FUNC_I2SIN6_MCK (MTK_PIN_NO(90) | 1) +#define PINMUX_GPIO90__FUNC_SPIM1_B_CSB (MTK_PIN_NO(90) | 2) +#define PINMUX_GPIO90__FUNC_CONN_MCU_TCK (MTK_PIN_NO(90) | 3) +#define PINMUX_GPIO90__FUNC_SPM_JTAG_TCK (MTK_PIN_NO(90) | 4) +#define PINMUX_GPIO90__FUNC_IPU_JTAG_TCK (MTK_PIN_NO(90) | 5) +#define PINMUX_GPIO90__FUNC_SPM_JTAG_TCK_VCORE (MTK_PIN_NO(90) | 6) +#define PINMUX_GPIO90__FUNC_SSPM_JTAG_TCK_VCORE (MTK_PIN_NO(90) | 7) + +#define PINMUX_GPIO91__FUNC_GPIO91 (MTK_PIN_NO(91) | 0) +#define PINMUX_GPIO91__FUNC_I2SIN6_BCK (MTK_PIN_NO(91) | 1) +#define PINMUX_GPIO91__FUNC_SPIM1_B_CLK (MTK_PIN_NO(91) | 2) +#define PINMUX_GPIO91__FUNC_CONN_MCU_TDI (MTK_PIN_NO(91) | 3) +#define PINMUX_GPIO91__FUNC_SPM_JTAG_TDI (MTK_PIN_NO(91) | 4) +#define PINMUX_GPIO91__FUNC_IPU_JTAG_TDI (MTK_PIN_NO(91) | 5) +#define PINMUX_GPIO91__FUNC_SPM_JTAG_TDI_VCORE (MTK_PIN_NO(91) | 6) +#define PINMUX_GPIO91__FUNC_SSPM_JTAG_TDI_VCORE (MTK_PIN_NO(91) | 7) + +#define PINMUX_GPIO92__FUNC_GPIO92 (MTK_PIN_NO(92) | 0) +#define PINMUX_GPIO92__FUNC_I2SIN6_LRCK (MTK_PIN_NO(92) | 1) +#define PINMUX_GPIO92__FUNC_SPIM1_B_MO (MTK_PIN_NO(92) | 2) +#define PINMUX_GPIO92__FUNC_CONN_MCU_TDO (MTK_PIN_NO(92) | 3) +#define PINMUX_GPIO92__FUNC_SPM_JTAG_TDO (MTK_PIN_NO(92) | 4) +#define PINMUX_GPIO92__FUNC_IPU_JTAG_TDO (MTK_PIN_NO(92) | 5) +#define PINMUX_GPIO92__FUNC_SPM_JTAG_TDO_VCORE (MTK_PIN_NO(92) | 6) +#define PINMUX_GPIO92__FUNC_SSPM_JTAG_TDO_VCORE (MTK_PIN_NO(92) | 7) + +#define PINMUX_GPIO93__FUNC_GPIO93 (MTK_PIN_NO(93) | 0) +#define PINMUX_GPIO93__FUNC_I2SIN6_DATA0 (MTK_PIN_NO(93) | 1) +#define PINMUX_GPIO93__FUNC_SPIM1_B_MI (MTK_PIN_NO(93) | 2) +#define PINMUX_GPIO93__FUNC_CONN_MCU_TMS (MTK_PIN_NO(93) | 3) +#define PINMUX_GPIO93__FUNC_SPM_JTAG_TMS (MTK_PIN_NO(93) | 4) +#define PINMUX_GPIO93__FUNC_IPU_JTAG_TMS (MTK_PIN_NO(93) | 5) +#define PINMUX_GPIO93__FUNC_SPM_JTAG_TMS_VCORE (MTK_PIN_NO(93) | 6) +#define PINMUX_GPIO93__FUNC_SSPM_JTAG_TMS_VCORE (MTK_PIN_NO(93) | 7) + +#define PINMUX_GPIO94__FUNC_GPIO94 (MTK_PIN_NO(94) | 0) +#define PINMUX_GPIO94__FUNC_I2SOUT4_MCK (MTK_PIN_NO(94) | 1) +#define PINMUX_GPIO94__FUNC_SPIM0_B_CSB (MTK_PIN_NO(94) | 2) +#define PINMUX_GPIO94__FUNC_CONN_MCU_TRST_B (MTK_PIN_NO(94) | 3) +#define PINMUX_GPIO94__FUNC_SPM_JTAG_TRSTN (MTK_PIN_NO(94) | 4) +#define PINMUX_GPIO94__FUNC_IPU_JTAG_TRST (MTK_PIN_NO(94) | 5) +#define PINMUX_GPIO94__FUNC_SPM_JTAG_TRSTN_VCORE (MTK_PIN_NO(94) | 6) +#define PINMUX_GPIO94__FUNC_SSPM_JTAG_TRSTN_VCORE (MTK_PIN_NO(94) | 7) + +#define PINMUX_GPIO95__FUNC_GPIO95 (MTK_PIN_NO(95) | 0) +#define PINMUX_GPIO95__FUNC_I2SOUT4_BCK (MTK_PIN_NO(95) | 1) +#define PINMUX_GPIO95__FUNC_SPIM0_B_CLK (MTK_PIN_NO(95) | 2) +#define PINMUX_GPIO95__FUNC_CONN_TCXOENA_REQ (MTK_PIN_NO(95) | 3) +#define PINMUX_GPIO95__FUNC_ANT_SEL5 (MTK_PIN_NO(95) | 4) +#define PINMUX_GPIO95__FUNC_EXTIF0_ACT (MTK_PIN_NO(95) | 5) +#define PINMUX_GPIO95__FUNC_DBG_MON_B28 (MTK_PIN_NO(95) | 7) + +#define PINMUX_GPIO96__FUNC_GPIO96 (MTK_PIN_NO(96) | 0) +#define PINMUX_GPIO96__FUNC_I2SOUT4_LRCK (MTK_PIN_NO(96) | 1) +#define PINMUX_GPIO96__FUNC_SPIM0_B_MO (MTK_PIN_NO(96) | 2) +#define PINMUX_GPIO96__FUNC_CONN_MCU_DBGI_N (MTK_PIN_NO(96) | 3) +#define PINMUX_GPIO96__FUNC_ANT_SEL6 (MTK_PIN_NO(96) | 4) +#define PINMUX_GPIO96__FUNC_EXTIF0_PRI (MTK_PIN_NO(96) | 5) +#define PINMUX_GPIO96__FUNC_UCTS3 (MTK_PIN_NO(96) | 6) +#define PINMUX_GPIO96__FUNC_DBG_MON_B29 (MTK_PIN_NO(96) | 7) + +#define PINMUX_GPIO97__FUNC_GPIO97 (MTK_PIN_NO(97) | 0) +#define PINMUX_GPIO97__FUNC_I2SOUT4_DATA0 (MTK_PIN_NO(97) | 1) +#define PINMUX_GPIO97__FUNC_SPIM0_B_MI (MTK_PIN_NO(97) | 2) +#define PINMUX_GPIO97__FUNC_CONN_MCU_DBGACK_N (MTK_PIN_NO(97) | 3) +#define PINMUX_GPIO97__FUNC_CONN_TCXOENA_REQ (MTK_PIN_NO(97) | 4) +#define PINMUX_GPIO97__FUNC_EXTIF0_GNT_B (MTK_PIN_NO(97) | 5) +#define PINMUX_GPIO97__FUNC_URTS3 (MTK_PIN_NO(97) | 6) +#define PINMUX_GPIO97__FUNC_DBG_MON_B30 (MTK_PIN_NO(97) | 7) + +#define PINMUX_GPIO98__FUNC_GPIO98 (MTK_PIN_NO(98) | 0) +#define PINMUX_GPIO98__FUNC_SCL0 (MTK_PIN_NO(98) | 1) + +#define PINMUX_GPIO99__FUNC_GPIO99 (MTK_PIN_NO(99) | 0) +#define PINMUX_GPIO99__FUNC_SDA0 (MTK_PIN_NO(99) | 1) + +#define PINMUX_GPIO100__FUNC_GPIO100 (MTK_PIN_NO(100) | 0) +#define PINMUX_GPIO100__FUNC_SCL1 (MTK_PIN_NO(100) | 1) +#define PINMUX_GPIO100__FUNC_I2SIN5_MCK (MTK_PIN_NO(100) | 2) +#define PINMUX_GPIO100__FUNC_DBG_MON_B1 (MTK_PIN_NO(100) | 7) + +#define PINMUX_GPIO101__FUNC_GPIO101 (MTK_PIN_NO(101) | 0) +#define PINMUX_GPIO101__FUNC_SDA1 (MTK_PIN_NO(101) | 1) +#define PINMUX_GPIO101__FUNC_I2SIN5_BCK (MTK_PIN_NO(101) | 2) +#define PINMUX_GPIO101__FUNC_DBG_MON_B2 (MTK_PIN_NO(101) | 7) + +#define PINMUX_GPIO102__FUNC_GPIO102 (MTK_PIN_NO(102) | 0) +#define PINMUX_GPIO102__FUNC_SCL2 (MTK_PIN_NO(102) | 1) +#define PINMUX_GPIO102__FUNC_I2SIN5_LRCK (MTK_PIN_NO(102) | 2) +#define PINMUX_GPIO102__FUNC_DBG_MON_B18 (MTK_PIN_NO(102) | 7) + +#define PINMUX_GPIO103__FUNC_GPIO103 (MTK_PIN_NO(103) | 0) +#define PINMUX_GPIO103__FUNC_SDA2 (MTK_PIN_NO(103) | 1) +#define PINMUX_GPIO103__FUNC_I2SIN5_DATA0 (MTK_PIN_NO(103) | 2) +#define PINMUX_GPIO103__FUNC_DBG_MON_B19 (MTK_PIN_NO(103) | 7) + +#define PINMUX_GPIO104__FUNC_GPIO104 (MTK_PIN_NO(104) | 0) +#define PINMUX_GPIO104__FUNC_SCL3 (MTK_PIN_NO(104) | 1) +#define PINMUX_GPIO104__FUNC_I2SIN5_DATA1 (MTK_PIN_NO(104) | 2) +#define PINMUX_GPIO104__FUNC_DBG_MON_B20 (MTK_PIN_NO(104) | 7) + +#define PINMUX_GPIO105__FUNC_GPIO105 (MTK_PIN_NO(105) | 0) +#define PINMUX_GPIO105__FUNC_SDA3 (MTK_PIN_NO(105) | 1) +#define PINMUX_GPIO105__FUNC_I2SIN5_DATA2 (MTK_PIN_NO(105) | 2) +#define PINMUX_GPIO105__FUNC_DBG_MON_B21 (MTK_PIN_NO(105) | 7) + +#define PINMUX_GPIO106__FUNC_GPIO106 (MTK_PIN_NO(106) | 0) +#define PINMUX_GPIO106__FUNC_SCL4 (MTK_PIN_NO(106) | 1) +#define PINMUX_GPIO106__FUNC_DMIC1_CLK (MTK_PIN_NO(106) | 4) +#define PINMUX_GPIO106__FUNC_DBG_MON_A22 (MTK_PIN_NO(106) | 7) + +#define PINMUX_GPIO107__FUNC_GPIO107 (MTK_PIN_NO(107) | 0) +#define PINMUX_GPIO107__FUNC_SDA4 (MTK_PIN_NO(107) | 1) +#define PINMUX_GPIO107__FUNC_DMIC1_DAT0 (MTK_PIN_NO(107) | 4) +#define PINMUX_GPIO107__FUNC_DBG_MON_A23 (MTK_PIN_NO(107) | 7) + +#define PINMUX_GPIO108__FUNC_GPIO108 (MTK_PIN_NO(108) | 0) +#define PINMUX_GPIO108__FUNC_SCL5 (MTK_PIN_NO(108) | 1) +#define PINMUX_GPIO108__FUNC_DMIC1_DAT1 (MTK_PIN_NO(108) | 4) +#define PINMUX_GPIO108__FUNC_DBG_MON_A24 (MTK_PIN_NO(108) | 7) + +#define PINMUX_GPIO109__FUNC_GPIO109 (MTK_PIN_NO(109) | 0) +#define PINMUX_GPIO109__FUNC_SDA5 (MTK_PIN_NO(109) | 1) +#define PINMUX_GPIO109__FUNC_DBG_MON_A25 (MTK_PIN_NO(109) | 7) + +#define PINMUX_GPIO110__FUNC_GPIO110 (MTK_PIN_NO(110) | 0) +#define PINMUX_GPIO110__FUNC_SCL6 (MTK_PIN_NO(110) | 1) +#define PINMUX_GPIO110__FUNC_DBG_MON_A26 (MTK_PIN_NO(110) | 7) + +#define PINMUX_GPIO111__FUNC_GPIO111 (MTK_PIN_NO(111) | 0) +#define PINMUX_GPIO111__FUNC_SDA6 (MTK_PIN_NO(111) | 1) +#define PINMUX_GPIO111__FUNC_DBG_MON_A27 (MTK_PIN_NO(111) | 7) + +#define PINMUX_GPIO112__FUNC_GPIO112 (MTK_PIN_NO(112) | 0) +#define PINMUX_GPIO112__FUNC_SCL7 (MTK_PIN_NO(112) | 1) +#define PINMUX_GPIO112__FUNC_DBG_MON_A28 (MTK_PIN_NO(112) | 7) + +#define PINMUX_GPIO113__FUNC_GPIO113 (MTK_PIN_NO(113) | 0) +#define PINMUX_GPIO113__FUNC_SDA7 (MTK_PIN_NO(113) | 1) +#define PINMUX_GPIO113__FUNC_DBG_MON_A29 (MTK_PIN_NO(113) | 7) + +#define PINMUX_GPIO114__FUNC_GPIO114 (MTK_PIN_NO(114) | 0) +#define PINMUX_GPIO114__FUNC_SCL8 (MTK_PIN_NO(114) | 1) +#define PINMUX_GPIO114__FUNC_DBG_MON_A30 (MTK_PIN_NO(114) | 7) + +#define PINMUX_GPIO115__FUNC_GPIO115 (MTK_PIN_NO(115) | 0) +#define PINMUX_GPIO115__FUNC_SDA8 (MTK_PIN_NO(115) | 1) +#define PINMUX_GPIO115__FUNC_DBG_MON_A31 (MTK_PIN_NO(115) | 7) + +#define PINMUX_GPIO116__FUNC_GPIO116 (MTK_PIN_NO(116) | 0) +#define PINMUX_GPIO116__FUNC_SDA9 (MTK_PIN_NO(116) | 1) +#define PINMUX_GPIO116__FUNC_DBG_MON_A32 (MTK_PIN_NO(116) | 7) + +#define PINMUX_GPIO117__FUNC_GPIO117 (MTK_PIN_NO(117) | 0) +#define PINMUX_GPIO117__FUNC_SCL9 (MTK_PIN_NO(117) | 1) +#define PINMUX_GPIO117__FUNC_DBG_MON_A4 (MTK_PIN_NO(117) | 7) + +#define PINMUX_GPIO118__FUNC_GPIO118 (MTK_PIN_NO(118) | 0) +#define PINMUX_GPIO118__FUNC_SPIM0_A_CLK (MTK_PIN_NO(118) | 1) +#define PINMUX_GPIO118__FUNC_I2SOUT4_DATA1 (MTK_PIN_NO(118) | 2) +#define PINMUX_GPIO118__FUNC_PERSTN (MTK_PIN_NO(118) | 3) +#define PINMUX_GPIO118__FUNC_SSUSB_U3PHY_I2C_SCL (MTK_PIN_NO(118) | 4) +#define PINMUX_GPIO118__FUNC_SSUSB_U2SIF_SCL_1P (MTK_PIN_NO(118) | 5) +#define PINMUX_GPIO118__FUNC_PCIE_PHY_I2C_SCL (MTK_PIN_NO(118) | 6) + +#define PINMUX_GPIO119__FUNC_GPIO119 (MTK_PIN_NO(119) | 0) +#define PINMUX_GPIO119__FUNC_SPIM0_A_CSB (MTK_PIN_NO(119) | 1) +#define PINMUX_GPIO119__FUNC_I2SOUT4_DATA2 (MTK_PIN_NO(119) | 2) +#define PINMUX_GPIO119__FUNC_CLKREQN (MTK_PIN_NO(119) | 3) +#define PINMUX_GPIO119__FUNC_SSUSB_U3PHY_I2C_SDA (MTK_PIN_NO(119) | 4) +#define PINMUX_GPIO119__FUNC_SSUSB_U2SIF_SDA_1P (MTK_PIN_NO(119) | 5) +#define PINMUX_GPIO119__FUNC_PCIE_PHY_I2C_SDA (MTK_PIN_NO(119) | 6) +#define PINMUX_GPIO119__FUNC_LVTS_FOUT (MTK_PIN_NO(119) | 7) + +#define PINMUX_GPIO120__FUNC_GPIO120 (MTK_PIN_NO(120) | 0) +#define PINMUX_GPIO120__FUNC_SPIM0_A_MO (MTK_PIN_NO(120) | 1) +#define PINMUX_GPIO120__FUNC_I2SOUT4_DATA3 (MTK_PIN_NO(120) | 2) +#define PINMUX_GPIO120__FUNC_WAKEN (MTK_PIN_NO(120) | 3) +#define PINMUX_GPIO120__FUNC_PCIE_PHY_I2C_SCL (MTK_PIN_NO(120) | 4) +#define PINMUX_GPIO120__FUNC_SSUSB_U2SIF_SCL (MTK_PIN_NO(120) | 5) +#define PINMUX_GPIO120__FUNC_SSUSB_U3PHY_I2C_SCL (MTK_PIN_NO(120) | 6) +#define PINMUX_GPIO120__FUNC_LVTS_26M (MTK_PIN_NO(120) | 7) + +#define PINMUX_GPIO121__FUNC_GPIO121 (MTK_PIN_NO(121) | 0) +#define PINMUX_GPIO121__FUNC_SPIM0_A_MI (MTK_PIN_NO(121) | 1) +#define PINMUX_GPIO121__FUNC_PCIE_PHY_I2C_SDA (MTK_PIN_NO(121) | 4) +#define PINMUX_GPIO121__FUNC_SSUSB_U2SIF_SDA (MTK_PIN_NO(121) | 5) +#define PINMUX_GPIO121__FUNC_SSUSB_U3PHY_I2C_SDA (MTK_PIN_NO(121) | 6) + +#define PINMUX_GPIO122__FUNC_GPIO122 (MTK_PIN_NO(122) | 0) +#define PINMUX_GPIO122__FUNC_MSDC0_DSL (MTK_PIN_NO(122) | 1) + +#define PINMUX_GPIO123__FUNC_GPIO123 (MTK_PIN_NO(123) | 0) +#define PINMUX_GPIO123__FUNC_MSDC0_CLK (MTK_PIN_NO(123) | 1) + +#define PINMUX_GPIO124__FUNC_GPIO124 (MTK_PIN_NO(124) | 0) +#define PINMUX_GPIO124__FUNC_MSDC0_CMD (MTK_PIN_NO(124) | 1) + +#define PINMUX_GPIO125__FUNC_GPIO125 (MTK_PIN_NO(125) | 0) +#define PINMUX_GPIO125__FUNC_MSDC0_RSTB (MTK_PIN_NO(125) | 1) + +#define PINMUX_GPIO126__FUNC_GPIO126 (MTK_PIN_NO(126) | 0) +#define PINMUX_GPIO126__FUNC_MSDC0_DAT0 (MTK_PIN_NO(126) | 1) + +#define PINMUX_GPIO127__FUNC_GPIO127 (MTK_PIN_NO(127) | 0) +#define PINMUX_GPIO127__FUNC_MSDC0_DAT1 (MTK_PIN_NO(127) | 1) + +#define PINMUX_GPIO128__FUNC_GPIO128 (MTK_PIN_NO(128) | 0) +#define PINMUX_GPIO128__FUNC_MSDC0_DAT2 (MTK_PIN_NO(128) | 1) + +#define PINMUX_GPIO129__FUNC_GPIO129 (MTK_PIN_NO(129) | 0) +#define PINMUX_GPIO129__FUNC_MSDC0_DAT3 (MTK_PIN_NO(129) | 1) + +#define PINMUX_GPIO130__FUNC_GPIO130 (MTK_PIN_NO(130) | 0) +#define PINMUX_GPIO130__FUNC_MSDC0_DAT4 (MTK_PIN_NO(130) | 1) + +#define PINMUX_GPIO131__FUNC_GPIO131 (MTK_PIN_NO(131) | 0) +#define PINMUX_GPIO131__FUNC_MSDC0_DAT5 (MTK_PIN_NO(131) | 1) + +#define PINMUX_GPIO132__FUNC_GPIO132 (MTK_PIN_NO(132) | 0) +#define PINMUX_GPIO132__FUNC_MSDC0_DAT6 (MTK_PIN_NO(132) | 1) + +#define PINMUX_GPIO133__FUNC_GPIO133 (MTK_PIN_NO(133) | 0) +#define PINMUX_GPIO133__FUNC_MSDC0_DAT7 (MTK_PIN_NO(133) | 1) + +#define PINMUX_GPIO134__FUNC_GPIO134 (MTK_PIN_NO(134) | 0) +#define PINMUX_GPIO134__FUNC_MSDC1_CLK (MTK_PIN_NO(134) | 1) +#define PINMUX_GPIO134__FUNC_VADSP_JTAG0_TCK (MTK_PIN_NO(134) | 2) +#define PINMUX_GPIO134__FUNC_MCUPM_JTAG_TCK (MTK_PIN_NO(134) | 3) +#define PINMUX_GPIO134__FUNC_UDI_TCK (MTK_PIN_NO(134) | 4) +#define PINMUX_GPIO134__FUNC_SSPM_JTAG_TCK_VCORE (MTK_PIN_NO(134) | 5) +#define PINMUX_GPIO134__FUNC_SPM_JTAG_TCK_VCORE (MTK_PIN_NO(134) | 6) + +#define PINMUX_GPIO135__FUNC_GPIO135 (MTK_PIN_NO(135) | 0) +#define PINMUX_GPIO135__FUNC_MSDC1_CMD (MTK_PIN_NO(135) | 1) +#define PINMUX_GPIO135__FUNC_VADSP_JTAG0_TDI (MTK_PIN_NO(135) | 2) +#define PINMUX_GPIO135__FUNC_MCUPM_JTAG_TDI (MTK_PIN_NO(135) | 3) +#define PINMUX_GPIO135__FUNC_UDI_TDI (MTK_PIN_NO(135) | 4) +#define PINMUX_GPIO135__FUNC_SSPM_JTAG_TDI_VCORE (MTK_PIN_NO(135) | 5) +#define PINMUX_GPIO135__FUNC_SPM_JTAG_TDI_VCORE (MTK_PIN_NO(135) | 6) + +#define PINMUX_GPIO136__FUNC_GPIO136 (MTK_PIN_NO(136) | 0) +#define PINMUX_GPIO136__FUNC_MSDC1_DAT0 (MTK_PIN_NO(136) | 1) +#define PINMUX_GPIO136__FUNC_VADSP_JTAG0_TDO (MTK_PIN_NO(136) | 2) +#define PINMUX_GPIO136__FUNC_MCUPM_JTAG_TDO (MTK_PIN_NO(136) | 3) +#define PINMUX_GPIO136__FUNC_UDI_TDO (MTK_PIN_NO(136) | 4) +#define PINMUX_GPIO136__FUNC_SSPM_JTAG_TDO_VCORE (MTK_PIN_NO(136) | 5) +#define PINMUX_GPIO136__FUNC_SPM_JTAG_TDO_VCORE (MTK_PIN_NO(136) | 6) + +#define PINMUX_GPIO137__FUNC_GPIO137 (MTK_PIN_NO(137) | 0) +#define PINMUX_GPIO137__FUNC_MSDC1_DAT1 (MTK_PIN_NO(137) | 1) +#define PINMUX_GPIO137__FUNC_VADSP_JTAG0_TMS (MTK_PIN_NO(137) | 2) +#define PINMUX_GPIO137__FUNC_MCUPM_JTAG_TMS (MTK_PIN_NO(137) | 3) +#define PINMUX_GPIO137__FUNC_UDI_TMS (MTK_PIN_NO(137) | 4) +#define PINMUX_GPIO137__FUNC_SSPM_JTAG_TMS_VCORE (MTK_PIN_NO(137) | 5) +#define PINMUX_GPIO137__FUNC_SPM_JTAG_TMS_VCORE (MTK_PIN_NO(137) | 6) + +#define PINMUX_GPIO138__FUNC_GPIO138 (MTK_PIN_NO(138) | 0) +#define PINMUX_GPIO138__FUNC_MSDC1_DAT2 (MTK_PIN_NO(138) | 1) +#define PINMUX_GPIO138__FUNC_VADSP_JTAG0_TRSTN (MTK_PIN_NO(138) | 2) +#define PINMUX_GPIO138__FUNC_MCUPM_JTAG_TRSTN (MTK_PIN_NO(138) | 3) +#define PINMUX_GPIO138__FUNC_UDI_NTRST (MTK_PIN_NO(138) | 4) +#define PINMUX_GPIO138__FUNC_SSPM_JTAG_TRSTN_VCORE (MTK_PIN_NO(138) | 5) +#define PINMUX_GPIO138__FUNC_SPM_JTAG_TRSTN_VCORE (MTK_PIN_NO(138) | 6) + +#define PINMUX_GPIO139__FUNC_GPIO139 (MTK_PIN_NO(139) | 0) +#define PINMUX_GPIO139__FUNC_MSDC1_DAT3 (MTK_PIN_NO(139) | 1) +#define PINMUX_GPIO139__FUNC_EPDC_STV2 (MTK_PIN_NO(139) | 2) +#define PINMUX_GPIO139__FUNC_CONN_TCXOENA_REQ (MTK_PIN_NO(139) | 3) +#define PINMUX_GPIO139__FUNC_CONN_TSF (MTK_PIN_NO(139) | 4) + +#define PINMUX_GPIO140__FUNC_GPIO140 (MTK_PIN_NO(140) | 0) +#define PINMUX_GPIO140__FUNC_MSDC2_CLK (MTK_PIN_NO(140) | 1) +#define PINMUX_GPIO140__FUNC_CMFLASH0 (MTK_PIN_NO(140) | 2) +#define PINMUX_GPIO140__FUNC_MCUPM_JTAG_TCK (MTK_PIN_NO(140) | 3) +#define PINMUX_GPIO140__FUNC_APU_JTAG_TCK (MTK_PIN_NO(140) | 4) +#define PINMUX_GPIO140__FUNC_VADSP_JTAG0_TCK (MTK_PIN_NO(140) | 6) +#define PINMUX_GPIO140__FUNC_DBG_MON_B6 (MTK_PIN_NO(140) | 7) + +#define PINMUX_GPIO141__FUNC_GPIO141 (MTK_PIN_NO(141) | 0) +#define PINMUX_GPIO141__FUNC_MSDC2_CMD (MTK_PIN_NO(141) | 1) +#define PINMUX_GPIO141__FUNC_CMFLASH1 (MTK_PIN_NO(141) | 2) +#define PINMUX_GPIO141__FUNC_MCUPM_JTAG_TDI (MTK_PIN_NO(141) | 3) +#define PINMUX_GPIO141__FUNC_APU_JTAG_TDI (MTK_PIN_NO(141) | 4) +#define PINMUX_GPIO141__FUNC_VADSP_JTAG0_TDI (MTK_PIN_NO(141) | 6) +#define PINMUX_GPIO141__FUNC_DBG_MON_B0 (MTK_PIN_NO(141) | 7) + +#define PINMUX_GPIO142__FUNC_GPIO142 (MTK_PIN_NO(142) | 0) +#define PINMUX_GPIO142__FUNC_MSDC2_DAT0 (MTK_PIN_NO(142) | 1) +#define PINMUX_GPIO142__FUNC_CMMCLK0 (MTK_PIN_NO(142) | 2) +#define PINMUX_GPIO142__FUNC_MCUPM_JTAG_TDO (MTK_PIN_NO(142) | 3) +#define PINMUX_GPIO142__FUNC_APU_JTAG_TDO (MTK_PIN_NO(142) | 4) +#define PINMUX_GPIO142__FUNC_VADSP_JTAG0_TDO (MTK_PIN_NO(142) | 6) +#define PINMUX_GPIO142__FUNC_DBG_MON_B7 (MTK_PIN_NO(142) | 7) + +#define PINMUX_GPIO143__FUNC_GPIO143 (MTK_PIN_NO(143) | 0) +#define PINMUX_GPIO143__FUNC_MSDC2_DAT1 (MTK_PIN_NO(143) | 1) +#define PINMUX_GPIO143__FUNC_CMFLASH2 (MTK_PIN_NO(143) | 2) +#define PINMUX_GPIO143__FUNC_MCUPM_JTAG_TMS (MTK_PIN_NO(143) | 3) +#define PINMUX_GPIO143__FUNC_APU_JTAG_TMS (MTK_PIN_NO(143) | 4) +#define PINMUX_GPIO143__FUNC_CONN_MCU_AICE_TMSC (MTK_PIN_NO(143) | 5) +#define PINMUX_GPIO143__FUNC_VADSP_JTAG0_TMS (MTK_PIN_NO(143) | 6) +#define PINMUX_GPIO143__FUNC_DBG_MON_B8 (MTK_PIN_NO(143) | 7) + +#define PINMUX_GPIO144__FUNC_GPIO144 (MTK_PIN_NO(144) | 0) +#define PINMUX_GPIO144__FUNC_MSDC2_DAT2 (MTK_PIN_NO(144) | 1) +#define PINMUX_GPIO144__FUNC_CMFLASH3 (MTK_PIN_NO(144) | 2) +#define PINMUX_GPIO144__FUNC_MCUPM_JTAG_TRSTN (MTK_PIN_NO(144) | 3) +#define PINMUX_GPIO144__FUNC_APU_JTAG_TRST (MTK_PIN_NO(144) | 4) +#define PINMUX_GPIO144__FUNC_CONN_MCU_AICE_TCKC (MTK_PIN_NO(144) | 5) +#define PINMUX_GPIO144__FUNC_VADSP_JTAG0_TRSTN (MTK_PIN_NO(144) | 6) +#define PINMUX_GPIO144__FUNC_DBG_MON_B9 (MTK_PIN_NO(144) | 7) + +#define PINMUX_GPIO145__FUNC_GPIO145 (MTK_PIN_NO(145) | 0) +#define PINMUX_GPIO145__FUNC_MSDC2_DAT3 (MTK_PIN_NO(145) | 1) +#define PINMUX_GPIO145__FUNC_CMMCLK1 (MTK_PIN_NO(145) | 2) +#define PINMUX_GPIO145__FUNC_CONN_TSF (MTK_PIN_NO(145) | 3) +#define PINMUX_GPIO145__FUNC_DBG_MON_B14 (MTK_PIN_NO(145) | 7) + +#define PINMUX_GPIO146__FUNC_GPIO146 (MTK_PIN_NO(146) | 0) +#define PINMUX_GPIO146__FUNC_CONN_TOP_CLK (MTK_PIN_NO(146) | 1) +#define PINMUX_GPIO146__FUNC_I2SOUT6_DATA11 (MTK_PIN_NO(146) | 2) +#define PINMUX_GPIO146__FUNC_DBG_MON_A0 (MTK_PIN_NO(146) | 7) + +#define PINMUX_GPIO147__FUNC_GPIO147 (MTK_PIN_NO(147) | 0) +#define PINMUX_GPIO147__FUNC_CONN_TOP_DATA (MTK_PIN_NO(147) | 1) +#define PINMUX_GPIO147__FUNC_I2SOUT6_DATA1 (MTK_PIN_NO(147) | 2) +#define PINMUX_GPIO147__FUNC_DBG_MON_A1 (MTK_PIN_NO(147) | 7) + +#define PINMUX_GPIO148__FUNC_GPIO148 (MTK_PIN_NO(148) | 0) +#define PINMUX_GPIO148__FUNC_CONN_BT_CLK (MTK_PIN_NO(148) | 1) +#define PINMUX_GPIO148__FUNC_I2SOUT6_DATA2 (MTK_PIN_NO(148) | 2) +#define PINMUX_GPIO148__FUNC_DBG_MON_A2 (MTK_PIN_NO(148) | 7) + +#define PINMUX_GPIO149__FUNC_GPIO149 (MTK_PIN_NO(149) | 0) +#define PINMUX_GPIO149__FUNC_CONN_BT_DATA (MTK_PIN_NO(149) | 1) +#define PINMUX_GPIO149__FUNC_I2SOUT6_DATA3 (MTK_PIN_NO(149) | 2) +#define PINMUX_GPIO149__FUNC_DBG_MON_A3 (MTK_PIN_NO(149) | 7) + +#define PINMUX_GPIO150__FUNC_GPIO150 (MTK_PIN_NO(150) | 0) +#define PINMUX_GPIO150__FUNC_CONN_HRST_B (MTK_PIN_NO(150) | 1) +#define PINMUX_GPIO150__FUNC_I2SOUT6_DATA4 (MTK_PIN_NO(150) | 2) + +#define PINMUX_GPIO151__FUNC_GPIO151 (MTK_PIN_NO(151) | 0) +#define PINMUX_GPIO151__FUNC_CONN_WB_PTA (MTK_PIN_NO(151) | 1) +#define PINMUX_GPIO151__FUNC_I2SOUT6_DATA5 (MTK_PIN_NO(151) | 2) + +#define PINMUX_GPIO152__FUNC_GPIO152 (MTK_PIN_NO(152) | 0) +#define PINMUX_GPIO152__FUNC_CONN_WF_CTRL0 (MTK_PIN_NO(152) | 1) +#define PINMUX_GPIO152__FUNC_I2SOUT6_DATA6 (MTK_PIN_NO(152) | 2) + +#define PINMUX_GPIO153__FUNC_GPIO153 (MTK_PIN_NO(153) | 0) +#define PINMUX_GPIO153__FUNC_CONN_WF_CTRL1 (MTK_PIN_NO(153) | 1) +#define PINMUX_GPIO153__FUNC_I2SOUT6_DATA7 (MTK_PIN_NO(153) | 2) + +#define PINMUX_GPIO154__FUNC_GPIO154 (MTK_PIN_NO(154) | 0) +#define PINMUX_GPIO154__FUNC_CONN_WF_CTRL2 (MTK_PIN_NO(154) | 1) +#define PINMUX_GPIO154__FUNC_I2SOUT6_DATA8 (MTK_PIN_NO(154) | 2) + +#define PINMUX_GPIO155__FUNC_GPIO155 (MTK_PIN_NO(155) | 0) +#define PINMUX_GPIO155__FUNC_AUD_CLK_MOSI (MTK_PIN_NO(155) | 1) + +#define PINMUX_GPIO156__FUNC_GPIO156 (MTK_PIN_NO(156) | 0) +#define PINMUX_GPIO156__FUNC_AUD_SYNC_MOSI (MTK_PIN_NO(156) | 1) + +#define PINMUX_GPIO157__FUNC_GPIO157 (MTK_PIN_NO(157) | 0) +#define PINMUX_GPIO157__FUNC_AUD_DAT_MOSI0 (MTK_PIN_NO(157) | 1) + +#define PINMUX_GPIO158__FUNC_GPIO158 (MTK_PIN_NO(158) | 0) +#define PINMUX_GPIO158__FUNC_AUD_DAT_MOSI1 (MTK_PIN_NO(158) | 1) + +#define PINMUX_GPIO159__FUNC_GPIO159 (MTK_PIN_NO(159) | 0) +#define PINMUX_GPIO159__FUNC_AUD_CLK_MISO (MTK_PIN_NO(159) | 1) + +#define PINMUX_GPIO160__FUNC_GPIO160 (MTK_PIN_NO(160) | 0) +#define PINMUX_GPIO160__FUNC_AUD_SYNC_MISO (MTK_PIN_NO(160) | 1) + +#define PINMUX_GPIO161__FUNC_GPIO161 (MTK_PIN_NO(161) | 0) +#define PINMUX_GPIO161__FUNC_AUD_DAT_MISO0 (MTK_PIN_NO(161) | 1) + +#define PINMUX_GPIO162__FUNC_GPIO162 (MTK_PIN_NO(162) | 0) +#define PINMUX_GPIO162__FUNC_AUD_DAT_MISO1 (MTK_PIN_NO(162) | 1) + +#define PINMUX_GPIO163__FUNC_GPIO163 (MTK_PIN_NO(163) | 0) +#define PINMUX_GPIO163__FUNC_PWRAP_SPI0_CSN (MTK_PIN_NO(163) | 1) + +#define PINMUX_GPIO164__FUNC_GPIO164 (MTK_PIN_NO(164) | 0) +#define PINMUX_GPIO164__FUNC_PWRAP_SPI0_CK (MTK_PIN_NO(164) | 1) + +#define PINMUX_GPIO165__FUNC_GPIO165 (MTK_PIN_NO(165) | 0) +#define PINMUX_GPIO165__FUNC_PWRAP_SPI0_MO (MTK_PIN_NO(165) | 1) +#define PINMUX_GPIO165__FUNC_PWRAP_SPI0_MI (MTK_PIN_NO(165) | 2) + +#define PINMUX_GPIO166__FUNC_GPIO166 (MTK_PIN_NO(166) | 0) +#define PINMUX_GPIO166__FUNC_PWRAP_SPI0_MI (MTK_PIN_NO(166) | 1) +#define PINMUX_GPIO166__FUNC_PWRAP_SPI0_MO (MTK_PIN_NO(166) | 2) + +#define PINMUX_GPIO167__FUNC_GPIO167 (MTK_PIN_NO(167) | 0) +#define PINMUX_GPIO167__FUNC_SRCLKENA0 (MTK_PIN_NO(167) | 1) + +#define PINMUX_GPIO168__FUNC_GPIO168 (MTK_PIN_NO(168) | 0) +#define PINMUX_GPIO168__FUNC_SRCLKENA1 (MTK_PIN_NO(168) | 1) + +#define PINMUX_GPIO169__FUNC_GPIO169 (MTK_PIN_NO(169) | 0) +#define PINMUX_GPIO169__FUNC_WATCHDOG (MTK_PIN_NO(169) | 1) + +#define PINMUX_GPIO170__FUNC_GPIO170 (MTK_PIN_NO(170) | 0) +#define PINMUX_GPIO170__FUNC_RTC32K_CK (MTK_PIN_NO(170) | 1) + +#define PINMUX_GPIO171__FUNC_GPIO171 (MTK_PIN_NO(171) | 0) +#define PINMUX_GPIO171__FUNC_DDR_PAD_RRESETB (MTK_PIN_NO(171) | 1) + +#endif /* __MT8366_PINFUNC_H */ + -- cgit v1.3.1 From b02465887e7bee6a817a84cf9203411f730811d5 Mon Sep 17 00:00:00 2001 From: Deep Pani Date: Fri, 7 Aug 2026 13:43:52 -0500 Subject: pinctrl: mediatek: add new mt8366 driver Add driver containing pinctrl register maps for MT8366. Signed-off-by: Deep Pani Signed-off-by: Macpaul Lin Co-developed-by: David Lechner Reviewed-by: Julien Stephan Link: https://patch.msgid.link/20260807-mtk-pinctrl-mt8366-v2-1-b7358bb31521@baylibre.com Signed-off-by: David Lechner --- drivers/pinctrl/mediatek/Makefile | 1 + drivers/pinctrl/mediatek/pinctrl-mt8366.c | 1243 +++++++++++++++++++++++++++++ 2 files changed, 1244 insertions(+) create mode 100644 drivers/pinctrl/mediatek/pinctrl-mt8366.c diff --git a/drivers/pinctrl/mediatek/Makefile b/drivers/pinctrl/mediatek/Makefile index f367db5c575..0e6eedba9c4 100644 --- a/drivers/pinctrl/mediatek/Makefile +++ b/drivers/pinctrl/mediatek/Makefile @@ -14,6 +14,7 @@ obj-$(CONFIG_TARGET_MT8188) += pinctrl-mt8188.o obj-$(CONFIG_TARGET_MT8189) += pinctrl-mt8189.o obj-$(CONFIG_TARGET_MT8195) += pinctrl-mt8195.o obj-$(CONFIG_TARGET_MT8365) += pinctrl-mt8365.o +obj-$(CONFIG_TARGET_MT8366) += pinctrl-mt8366.o obj-$(CONFIG_TARGET_MT8512) += pinctrl-mt8512.o obj-$(CONFIG_TARGET_MT8516) += pinctrl-mt8516.o obj-$(CONFIG_TARGET_MT8518) += pinctrl-mt8518.o diff --git a/drivers/pinctrl/mediatek/pinctrl-mt8366.c b/drivers/pinctrl/mediatek/pinctrl-mt8366.c new file mode 100644 index 00000000000..701d78d57d4 --- /dev/null +++ b/drivers/pinctrl/mediatek/pinctrl-mt8366.c @@ -0,0 +1,1243 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * The MT8366 driver based on Linux generic pinctrl binding. + * + * Copyright (C) 2026 MediaTek Inc. + * Copyright (C) 2026 BayLibre, SAS + * Author: Deep Pani + * Author: David Lechner + */ +#include +#include "pinctrl-mtk-common.h" + +#define PIN_FIELD_GPIO(_s_pin, _e_pin, _s_addr, _s_bit, _x_bits) \ + PIN_FIELD_BASE_CALC(_s_pin, _e_pin, GPIO_BASE, _s_addr, 0x10, _s_bit, \ + _x_bits, 32, 0) + +#define PIN_FIELD_BASE(_s_pin, _i_base, _s_addr, _s_bit, _x_bits) \ + PIN_FIELD_BASE_CALC(_s_pin, _s_pin, _i_base, _s_addr, 0x10, _s_bit, \ + _x_bits, 32, 0) + +enum { + GPIO_BASE, + IOCFG_RM_BASE, + IOCFG_BM_BASE, + IOCFG_LB_BASE, + IOCFG_TR_BASE, + IOCFG_LT_BASE, + IOCFG_TL_BASE, +}; + +static const char * const mt8366_pinctrl_register_base_names[] = { + "gpio", "iocfg_rm", "iocfg_bm", + "iocfg_lb", "iocfg_tr", "iocfg_lt", + "iocfg_tl", +}; + +static const struct mtk_pin_field_calc mt8366_pin_mode_range[] = { + PIN_FIELD_GPIO(0, 171, 0x300, 0, 4), +}; + +static const struct mtk_pin_field_calc mt8366_pin_dir_range[] = { + PIN_FIELD_GPIO(0, 171, 0x0, 0, 1), +}; + +static const struct mtk_pin_field_calc mt8366_pin_di_range[] = { + PIN_FIELD_GPIO(0, 171, 0x200, 0, 1), +}; + +static const struct mtk_pin_field_calc mt8366_pin_do_range[] = { + PIN_FIELD_GPIO(0, 171, 0x100, 0, 1), +}; + +static const struct mtk_pin_field_calc mt8366_pin_smt_range[] = { + PIN_FIELD_BASE(0, IOCFG_RM_BASE, 0x0100, 8, 1), + PIN_FIELD_BASE(1, IOCFG_RM_BASE, 0x0100, 8, 1), + PIN_FIELD_BASE(2, IOCFG_RM_BASE, 0x0100, 8, 1), + PIN_FIELD_BASE(3, IOCFG_LB_BASE, 0x0100, 8, 1), + PIN_FIELD_BASE(4, IOCFG_LB_BASE, 0x0100, 8, 1), + PIN_FIELD_BASE(5, IOCFG_LB_BASE, 0x0100, 8, 1), + PIN_FIELD_BASE(6, IOCFG_LB_BASE, 0x0100, 12, 1), + PIN_FIELD_BASE(7, IOCFG_LB_BASE, 0x0100, 11, 1), + PIN_FIELD_BASE(8, IOCFG_LB_BASE, 0x0100, 12, 1), + PIN_FIELD_BASE(9, IOCFG_LB_BASE, 0x0100, 8, 1), + PIN_FIELD_BASE(10, IOCFG_LB_BASE, 0x0100, 8, 1), + PIN_FIELD_BASE(11, IOCFG_LB_BASE, 0x0100, 12, 1), + PIN_FIELD_BASE(12, IOCFG_BM_BASE, 0x0170, 0, 1), + PIN_FIELD_BASE(13, IOCFG_BM_BASE, 0x0170, 1, 1), + PIN_FIELD_BASE(14, IOCFG_BM_BASE, 0x0170, 12, 1), + PIN_FIELD_BASE(15, IOCFG_BM_BASE, 0x0170, 17, 1), + PIN_FIELD_BASE(16, IOCFG_BM_BASE, 0x0170, 18, 1), + PIN_FIELD_BASE(17, IOCFG_BM_BASE, 0x0170, 19, 1), + PIN_FIELD_BASE(18, IOCFG_BM_BASE, 0x0170, 20, 1), + PIN_FIELD_BASE(19, IOCFG_BM_BASE, 0x0170, 21, 1), + PIN_FIELD_BASE(20, IOCFG_BM_BASE, 0x0170, 22, 1), + PIN_FIELD_BASE(21, IOCFG_BM_BASE, 0x0170, 23, 1), + PIN_FIELD_BASE(22, IOCFG_BM_BASE, 0x0170, 2, 1), + PIN_FIELD_BASE(23, IOCFG_BM_BASE, 0x0170, 3, 1), + PIN_FIELD_BASE(24, IOCFG_BM_BASE, 0x0170, 4, 1), + PIN_FIELD_BASE(25, IOCFG_BM_BASE, 0x0170, 5, 1), + PIN_FIELD_BASE(26, IOCFG_BM_BASE, 0x0170, 6, 1), + PIN_FIELD_BASE(27, IOCFG_BM_BASE, 0x0170, 7, 1), + PIN_FIELD_BASE(28, IOCFG_BM_BASE, 0x0170, 8, 1), + PIN_FIELD_BASE(29, IOCFG_BM_BASE, 0x0170, 9, 1), + PIN_FIELD_BASE(30, IOCFG_BM_BASE, 0x0170, 10, 1), + PIN_FIELD_BASE(31, IOCFG_BM_BASE, 0x0170, 11, 1), + PIN_FIELD_BASE(32, IOCFG_BM_BASE, 0x0170, 13, 1), + PIN_FIELD_BASE(33, IOCFG_BM_BASE, 0x0170, 14, 1), + PIN_FIELD_BASE(34, IOCFG_BM_BASE, 0x0170, 15, 1), + PIN_FIELD_BASE(35, IOCFG_BM_BASE, 0x0170, 16, 1), + PIN_FIELD_BASE(36, IOCFG_BM_BASE, 0x0170, 28, 1), + PIN_FIELD_BASE(37, IOCFG_BM_BASE, 0x0170, 29, 1), + PIN_FIELD_BASE(38, IOCFG_BM_BASE, 0x0170, 30, 1), + PIN_FIELD_BASE(39, IOCFG_BM_BASE, 0x0170, 24, 1), + PIN_FIELD_BASE(40, IOCFG_BM_BASE, 0x0170, 25, 1), + PIN_FIELD_BASE(41, IOCFG_BM_BASE, 0x0170, 26, 1), + PIN_FIELD_BASE(42, IOCFG_BM_BASE, 0x0180, 0, 1), + PIN_FIELD_BASE(43, IOCFG_BM_BASE, 0x0180, 9, 1), + PIN_FIELD_BASE(44, IOCFG_BM_BASE, 0x0180, 7, 1), + PIN_FIELD_BASE(45, IOCFG_BM_BASE, 0x0180, 7, 1), + PIN_FIELD_BASE(46, IOCFG_BM_BASE, 0x0180, 7, 1), + PIN_FIELD_BASE(47, IOCFG_BM_BASE, 0x0170, 27, 1), + PIN_FIELD_BASE(48, IOCFG_BM_BASE, 0x0180, 7, 1), + PIN_FIELD_BASE(49, IOCFG_BM_BASE, 0x0180, 8, 1), + PIN_FIELD_BASE(50, IOCFG_BM_BASE, 0x0170, 31, 1), + PIN_FIELD_BASE(51, IOCFG_BM_BASE, 0x0180, 8, 1), + PIN_FIELD_BASE(52, IOCFG_RM_BASE, 0x0100, 10, 1), + PIN_FIELD_BASE(53, IOCFG_RM_BASE, 0x0100, 10, 1), + PIN_FIELD_BASE(54, IOCFG_RM_BASE, 0x0100, 10, 1), + PIN_FIELD_BASE(55, IOCFG_RM_BASE, 0x0100, 11, 1), + PIN_FIELD_BASE(56, IOCFG_LT_BASE, 0x0090, 3, 1), + PIN_FIELD_BASE(57, IOCFG_RM_BASE, 0x0100, 8, 1), + PIN_FIELD_BASE(58, IOCFG_RM_BASE, 0x0100, 8, 1), + PIN_FIELD_BASE(59, IOCFG_RM_BASE, 0x0100, 0, 1), + PIN_FIELD_BASE(60, IOCFG_RM_BASE, 0x0100, 8, 1), + PIN_FIELD_BASE(61, IOCFG_RM_BASE, 0x0100, 8, 1), + PIN_FIELD_BASE(62, IOCFG_RM_BASE, 0x0100, 1, 1), + PIN_FIELD_BASE(63, IOCFG_LB_BASE, 0x0100, 11, 1), + PIN_FIELD_BASE(64, IOCFG_LB_BASE, 0x0100, 11, 1), + PIN_FIELD_BASE(65, IOCFG_LB_BASE, 0x0100, 11, 1), + PIN_FIELD_BASE(66, IOCFG_LB_BASE, 0x0100, 14, 1), + PIN_FIELD_BASE(67, IOCFG_LB_BASE, 0x0100, 14, 1), + PIN_FIELD_BASE(68, IOCFG_LB_BASE, 0x0100, 9, 1), + PIN_FIELD_BASE(69, IOCFG_LB_BASE, 0x0100, 9, 1), + PIN_FIELD_BASE(70, IOCFG_LB_BASE, 0x0100, 9, 1), + PIN_FIELD_BASE(71, IOCFG_LB_BASE, 0x0100, 9, 1), + PIN_FIELD_BASE(72, IOCFG_LB_BASE, 0x0100, 14, 1), + PIN_FIELD_BASE(73, IOCFG_LB_BASE, 0x0100, 9, 1), + PIN_FIELD_BASE(74, IOCFG_LB_BASE, 0x0100, 13, 1), + PIN_FIELD_BASE(75, IOCFG_LB_BASE, 0x0100, 13, 1), + PIN_FIELD_BASE(76, IOCFG_LB_BASE, 0x0100, 12, 1), + PIN_FIELD_BASE(77, IOCFG_LB_BASE, 0x0100, 13, 1), + PIN_FIELD_BASE(78, IOCFG_LB_BASE, 0x0100, 13, 1), + PIN_FIELD_BASE(79, IOCFG_RM_BASE, 0x0100, 11, 1), + PIN_FIELD_BASE(80, IOCFG_RM_BASE, 0x0100, 9, 1), + PIN_FIELD_BASE(81, IOCFG_RM_BASE, 0x0100, 11, 1), + PIN_FIELD_BASE(82, IOCFG_RM_BASE, 0x0100, 9, 1), + PIN_FIELD_BASE(83, IOCFG_RM_BASE, 0x0100, 9, 1), + PIN_FIELD_BASE(84, IOCFG_RM_BASE, 0x0100, 9, 1), + PIN_FIELD_BASE(85, IOCFG_RM_BASE, 0x0100, 9, 1), + PIN_FIELD_BASE(86, IOCFG_RM_BASE, 0x0100, 9, 1), + PIN_FIELD_BASE(87, IOCFG_RM_BASE, 0x0100, 9, 1), + PIN_FIELD_BASE(88, IOCFG_RM_BASE, 0x0100, 10, 1), + PIN_FIELD_BASE(89, IOCFG_RM_BASE, 0x0100, 11, 1), + PIN_FIELD_BASE(90, IOCFG_LB_BASE, 0x0100, 2, 1), + PIN_FIELD_BASE(91, IOCFG_LB_BASE, 0x0100, 0, 1), + PIN_FIELD_BASE(92, IOCFG_LB_BASE, 0x0100, 3, 1), + PIN_FIELD_BASE(93, IOCFG_LB_BASE, 0x0100, 1, 1), + PIN_FIELD_BASE(94, IOCFG_LB_BASE, 0x0100, 6, 1), + PIN_FIELD_BASE(95, IOCFG_LB_BASE, 0x0100, 4, 1), + PIN_FIELD_BASE(96, IOCFG_LB_BASE, 0x0100, 7, 1), + PIN_FIELD_BASE(97, IOCFG_LB_BASE, 0x0100, 5, 1), + PIN_FIELD_BASE(98, IOCFG_LT_BASE, 0x0090, 4, 1), + PIN_FIELD_BASE(99, IOCFG_LT_BASE, 0x0090, 6, 1), + PIN_FIELD_BASE(100, IOCFG_RM_BASE, 0x0100, 12, 1), + PIN_FIELD_BASE(101, IOCFG_RM_BASE, 0x0100, 15, 1), + PIN_FIELD_BASE(102, IOCFG_RM_BASE, 0x0100, 13, 1), + PIN_FIELD_BASE(103, IOCFG_RM_BASE, 0x0100, 16, 1), + PIN_FIELD_BASE(104, IOCFG_RM_BASE, 0x0100, 14, 1), + PIN_FIELD_BASE(105, IOCFG_RM_BASE, 0x0100, 17, 1), + PIN_FIELD_BASE(106, IOCFG_LT_BASE, 0x0090, 5, 1), + PIN_FIELD_BASE(107, IOCFG_LT_BASE, 0x0090, 7, 1), + PIN_FIELD_BASE(108, IOCFG_LB_BASE, 0x0100, 15, 1), + PIN_FIELD_BASE(109, IOCFG_LB_BASE, 0x0100, 20, 1), + PIN_FIELD_BASE(110, IOCFG_LB_BASE, 0x0100, 16, 1), + PIN_FIELD_BASE(111, IOCFG_LB_BASE, 0x0100, 21, 1), + PIN_FIELD_BASE(112, IOCFG_LB_BASE, 0x0100, 17, 1), + PIN_FIELD_BASE(113, IOCFG_LB_BASE, 0x0100, 22, 1), + PIN_FIELD_BASE(114, IOCFG_LB_BASE, 0x0100, 18, 1), + PIN_FIELD_BASE(115, IOCFG_LB_BASE, 0x0100, 23, 1), + PIN_FIELD_BASE(116, IOCFG_LB_BASE, 0x0100, 24, 1), + PIN_FIELD_BASE(117, IOCFG_LB_BASE, 0x0100, 19, 1), + PIN_FIELD_BASE(118, IOCFG_LB_BASE, 0x0100, 25, 1), + PIN_FIELD_BASE(119, IOCFG_LB_BASE, 0x0100, 26, 1), + PIN_FIELD_BASE(120, IOCFG_LB_BASE, 0x0100, 28, 1), + PIN_FIELD_BASE(121, IOCFG_LB_BASE, 0x0100, 27, 1), + PIN_FIELD_BASE(122, IOCFG_TR_BASE, 0x0090, 10, 1), + PIN_FIELD_BASE(123, IOCFG_TR_BASE, 0x0090, 0, 1), + PIN_FIELD_BASE(124, IOCFG_TR_BASE, 0x0090, 1, 1), + PIN_FIELD_BASE(125, IOCFG_TR_BASE, 0x0090, 11, 1), + PIN_FIELD_BASE(126, IOCFG_TR_BASE, 0x0090, 2, 1), + PIN_FIELD_BASE(127, IOCFG_TR_BASE, 0x0090, 3, 1), + PIN_FIELD_BASE(128, IOCFG_TR_BASE, 0x0090, 4, 1), + PIN_FIELD_BASE(129, IOCFG_TR_BASE, 0x0090, 5, 1), + PIN_FIELD_BASE(130, IOCFG_TR_BASE, 0x0090, 6, 1), + PIN_FIELD_BASE(131, IOCFG_TR_BASE, 0x0090, 7, 1), + PIN_FIELD_BASE(132, IOCFG_TR_BASE, 0x0090, 8, 1), + PIN_FIELD_BASE(133, IOCFG_TR_BASE, 0x0090, 9, 1), + PIN_FIELD_BASE(134, IOCFG_BM_BASE, 0x0180, 1, 1), + PIN_FIELD_BASE(135, IOCFG_BM_BASE, 0x0180, 2, 1), + PIN_FIELD_BASE(136, IOCFG_BM_BASE, 0x0180, 3, 1), + PIN_FIELD_BASE(137, IOCFG_BM_BASE, 0x0180, 4, 1), + PIN_FIELD_BASE(138, IOCFG_BM_BASE, 0x0180, 5, 1), + PIN_FIELD_BASE(139, IOCFG_BM_BASE, 0x0180, 6, 1), + PIN_FIELD_BASE(140, IOCFG_RM_BASE, 0x0100, 2, 1), + PIN_FIELD_BASE(141, IOCFG_RM_BASE, 0x0100, 3, 1), + PIN_FIELD_BASE(142, IOCFG_RM_BASE, 0x0100, 4, 1), + PIN_FIELD_BASE(143, IOCFG_RM_BASE, 0x0100, 5, 1), + PIN_FIELD_BASE(144, IOCFG_RM_BASE, 0x0100, 6, 1), + PIN_FIELD_BASE(145, IOCFG_RM_BASE, 0x0100, 7, 1), + PIN_FIELD_BASE(146, IOCFG_LB_BASE, 0x0100, 10, 1), + PIN_FIELD_BASE(147, IOCFG_LB_BASE, 0x0100, 10, 1), + PIN_FIELD_BASE(148, IOCFG_LB_BASE, 0x0100, 10, 1), + PIN_FIELD_BASE(149, IOCFG_LB_BASE, 0x0100, 10, 1), + PIN_FIELD_BASE(150, IOCFG_LB_BASE, 0x0100, 10, 1), + PIN_FIELD_BASE(151, IOCFG_LB_BASE, 0x0100, 10, 1), + PIN_FIELD_BASE(152, IOCFG_LB_BASE, 0x0100, 10, 1), + PIN_FIELD_BASE(153, IOCFG_LB_BASE, 0x0100, 10, 1), + PIN_FIELD_BASE(154, IOCFG_LB_BASE, 0x0100, 10, 1), + PIN_FIELD_BASE(155, IOCFG_LT_BASE, 0x0090, 1, 1), + PIN_FIELD_BASE(156, IOCFG_LT_BASE, 0x0090, 2, 1), + PIN_FIELD_BASE(157, IOCFG_LT_BASE, 0x0090, 1, 1), + PIN_FIELD_BASE(158, IOCFG_LT_BASE, 0x0090, 3, 1), + PIN_FIELD_BASE(159, IOCFG_LT_BASE, 0x0090, 2, 1), + PIN_FIELD_BASE(160, IOCFG_LT_BASE, 0x0090, 2, 1), + PIN_FIELD_BASE(161, IOCFG_LT_BASE, 0x0090, 2, 1), + PIN_FIELD_BASE(162, IOCFG_LT_BASE, 0x0090, 1, 1), + PIN_FIELD_BASE(163, IOCFG_TL_BASE, 0x0050, 1, 1), + PIN_FIELD_BASE(164, IOCFG_TL_BASE, 0x0050, 1, 1), + PIN_FIELD_BASE(165, IOCFG_TL_BASE, 0x0050, 1, 1), + PIN_FIELD_BASE(166, IOCFG_TL_BASE, 0x0050, 1, 1), + PIN_FIELD_BASE(167, IOCFG_TL_BASE, 0x0050, 2, 1), + PIN_FIELD_BASE(168, IOCFG_TL_BASE, 0x0050, 2, 1), + PIN_FIELD_BASE(169, IOCFG_LT_BASE, 0x0090, 0, 1), + PIN_FIELD_BASE(170, IOCFG_LT_BASE, 0x0090, 1, 1), + PIN_FIELD_BASE(171, IOCFG_TL_BASE, 0x0050, 0, 1), +}; + +static const struct mtk_pin_field_calc mt8366_pin_ies_range[] = { + PIN_FIELD_BASE(0, IOCFG_RM_BASE, 0x0060, 9, 1), + PIN_FIELD_BASE(1, IOCFG_RM_BASE, 0x0060, 10, 1), + PIN_FIELD_BASE(2, IOCFG_RM_BASE, 0x0060, 11, 1), + PIN_FIELD_BASE(3, IOCFG_LB_BASE, 0x0070, 13, 1), + PIN_FIELD_BASE(4, IOCFG_LB_BASE, 0x0070, 14, 1), + PIN_FIELD_BASE(5, IOCFG_LB_BASE, 0x0070, 15, 1), + PIN_FIELD_BASE(6, IOCFG_LB_BASE, 0x0070, 16, 1), + PIN_FIELD_BASE(7, IOCFG_LB_BASE, 0x0070, 17, 1), + PIN_FIELD_BASE(8, IOCFG_LB_BASE, 0x0070, 18, 1), + PIN_FIELD_BASE(9, IOCFG_LB_BASE, 0x0070, 19, 1), + PIN_FIELD_BASE(10, IOCFG_LB_BASE, 0x0070, 11, 1), + PIN_FIELD_BASE(11, IOCFG_LB_BASE, 0x0070, 12, 1), + PIN_FIELD_BASE(12, IOCFG_BM_BASE, 0x0050, 0, 1), + PIN_FIELD_BASE(13, IOCFG_BM_BASE, 0x0050, 1, 1), + PIN_FIELD_BASE(14, IOCFG_BM_BASE, 0x0050, 12, 1), + PIN_FIELD_BASE(15, IOCFG_BM_BASE, 0x0050, 17, 1), + PIN_FIELD_BASE(16, IOCFG_BM_BASE, 0x0050, 18, 1), + PIN_FIELD_BASE(17, IOCFG_BM_BASE, 0x0050, 19, 1), + PIN_FIELD_BASE(18, IOCFG_BM_BASE, 0x0050, 20, 1), + PIN_FIELD_BASE(19, IOCFG_BM_BASE, 0x0050, 21, 1), + PIN_FIELD_BASE(20, IOCFG_BM_BASE, 0x0050, 22, 1), + PIN_FIELD_BASE(21, IOCFG_BM_BASE, 0x0050, 23, 1), + PIN_FIELD_BASE(22, IOCFG_BM_BASE, 0x0050, 2, 1), + PIN_FIELD_BASE(23, IOCFG_BM_BASE, 0x0050, 3, 1), + PIN_FIELD_BASE(24, IOCFG_BM_BASE, 0x0050, 4, 1), + PIN_FIELD_BASE(25, IOCFG_BM_BASE, 0x0050, 5, 1), + PIN_FIELD_BASE(26, IOCFG_BM_BASE, 0x0050, 6, 1), + PIN_FIELD_BASE(27, IOCFG_BM_BASE, 0x0050, 7, 1), + PIN_FIELD_BASE(28, IOCFG_BM_BASE, 0x0050, 8, 1), + PIN_FIELD_BASE(29, IOCFG_BM_BASE, 0x0050, 9, 1), + PIN_FIELD_BASE(30, IOCFG_BM_BASE, 0x0050, 10, 1), + PIN_FIELD_BASE(31, IOCFG_BM_BASE, 0x0050, 11, 1), + PIN_FIELD_BASE(32, IOCFG_BM_BASE, 0x0050, 13, 1), + PIN_FIELD_BASE(33, IOCFG_BM_BASE, 0x0050, 14, 1), + PIN_FIELD_BASE(34, IOCFG_BM_BASE, 0x0050, 15, 1), + PIN_FIELD_BASE(35, IOCFG_BM_BASE, 0x0050, 16, 1), + PIN_FIELD_BASE(36, IOCFG_BM_BASE, 0x0050, 31, 1), + PIN_FIELD_BASE(37, IOCFG_BM_BASE, 0x0060, 0, 1), + PIN_FIELD_BASE(38, IOCFG_BM_BASE, 0x0060, 1, 1), + PIN_FIELD_BASE(39, IOCFG_BM_BASE, 0x0050, 24, 1), + PIN_FIELD_BASE(40, IOCFG_BM_BASE, 0x0050, 25, 1), + PIN_FIELD_BASE(41, IOCFG_BM_BASE, 0x0050, 26, 1), + PIN_FIELD_BASE(42, IOCFG_BM_BASE, 0x0060, 5, 1), + PIN_FIELD_BASE(43, IOCFG_BM_BASE, 0x0060, 13, 1), + PIN_FIELD_BASE(44, IOCFG_BM_BASE, 0x0060, 6, 1), + PIN_FIELD_BASE(45, IOCFG_BM_BASE, 0x0050, 27, 1), + PIN_FIELD_BASE(46, IOCFG_BM_BASE, 0x0050, 28, 1), + PIN_FIELD_BASE(47, IOCFG_BM_BASE, 0x0050, 29, 1), + PIN_FIELD_BASE(48, IOCFG_BM_BASE, 0x0050, 30, 1), + PIN_FIELD_BASE(49, IOCFG_BM_BASE, 0x0060, 3, 1), + PIN_FIELD_BASE(50, IOCFG_BM_BASE, 0x0060, 4, 1), + PIN_FIELD_BASE(51, IOCFG_BM_BASE, 0x0060, 2, 1), + PIN_FIELD_BASE(52, IOCFG_RM_BASE, 0x0060, 12, 1), + PIN_FIELD_BASE(53, IOCFG_RM_BASE, 0x0070, 1, 1), + PIN_FIELD_BASE(54, IOCFG_RM_BASE, 0x0070, 3, 1), + PIN_FIELD_BASE(55, IOCFG_RM_BASE, 0x0070, 2, 1), + PIN_FIELD_BASE(56, IOCFG_LT_BASE, 0x0040, 13, 1), + PIN_FIELD_BASE(57, IOCFG_RM_BASE, 0x0060, 2, 1), + PIN_FIELD_BASE(58, IOCFG_RM_BASE, 0x0060, 4, 1), + PIN_FIELD_BASE(59, IOCFG_RM_BASE, 0x0060, 0, 1), + PIN_FIELD_BASE(60, IOCFG_RM_BASE, 0x0060, 3, 1), + PIN_FIELD_BASE(61, IOCFG_RM_BASE, 0x0060, 5, 1), + PIN_FIELD_BASE(62, IOCFG_RM_BASE, 0x0060, 1, 1), + PIN_FIELD_BASE(63, IOCFG_LB_BASE, 0x0070, 10, 1), + PIN_FIELD_BASE(64, IOCFG_LB_BASE, 0x0070, 9, 1), + PIN_FIELD_BASE(65, IOCFG_LB_BASE, 0x0080, 1, 1), + PIN_FIELD_BASE(66, IOCFG_LB_BASE, 0x0080, 16, 1), + PIN_FIELD_BASE(67, IOCFG_LB_BASE, 0x0080, 20, 1), + PIN_FIELD_BASE(68, IOCFG_LB_BASE, 0x0080, 17, 1), + PIN_FIELD_BASE(69, IOCFG_LB_BASE, 0x0080, 21, 1), + PIN_FIELD_BASE(70, IOCFG_LB_BASE, 0x0080, 18, 1), + PIN_FIELD_BASE(71, IOCFG_LB_BASE, 0x0080, 22, 1), + PIN_FIELD_BASE(72, IOCFG_LB_BASE, 0x0080, 19, 1), + PIN_FIELD_BASE(73, IOCFG_LB_BASE, 0x0080, 23, 1), + PIN_FIELD_BASE(74, IOCFG_LB_BASE, 0x0070, 31, 1), + PIN_FIELD_BASE(75, IOCFG_LB_BASE, 0x0070, 28, 1), + PIN_FIELD_BASE(76, IOCFG_LB_BASE, 0x0070, 29, 1), + PIN_FIELD_BASE(77, IOCFG_LB_BASE, 0x0070, 30, 1), + PIN_FIELD_BASE(78, IOCFG_LB_BASE, 0x0080, 0, 1), + PIN_FIELD_BASE(79, IOCFG_RM_BASE, 0x0060, 13, 1), + PIN_FIELD_BASE(80, IOCFG_RM_BASE, 0x0060, 14, 1), + PIN_FIELD_BASE(81, IOCFG_RM_BASE, 0x0060, 15, 1), + PIN_FIELD_BASE(82, IOCFG_RM_BASE, 0x0060, 16, 1), + PIN_FIELD_BASE(83, IOCFG_RM_BASE, 0x0060, 6, 1), + PIN_FIELD_BASE(84, IOCFG_RM_BASE, 0x0060, 7, 1), + PIN_FIELD_BASE(85, IOCFG_RM_BASE, 0x0060, 8, 1), + PIN_FIELD_BASE(86, IOCFG_RM_BASE, 0x0060, 23, 1), + PIN_FIELD_BASE(87, IOCFG_RM_BASE, 0x0060, 26, 1), + PIN_FIELD_BASE(88, IOCFG_RM_BASE, 0x0060, 24, 1), + PIN_FIELD_BASE(89, IOCFG_RM_BASE, 0x0060, 25, 1), + PIN_FIELD_BASE(90, IOCFG_LB_BASE, 0x0070, 22, 1), + PIN_FIELD_BASE(91, IOCFG_LB_BASE, 0x0070, 20, 1), + PIN_FIELD_BASE(92, IOCFG_LB_BASE, 0x0070, 23, 1), + PIN_FIELD_BASE(93, IOCFG_LB_BASE, 0x0070, 21, 1), + PIN_FIELD_BASE(94, IOCFG_LB_BASE, 0x0070, 26, 1), + PIN_FIELD_BASE(95, IOCFG_LB_BASE, 0x0070, 24, 1), + PIN_FIELD_BASE(96, IOCFG_LB_BASE, 0x0070, 27, 1), + PIN_FIELD_BASE(97, IOCFG_LB_BASE, 0x0070, 25, 1), + PIN_FIELD_BASE(98, IOCFG_LT_BASE, 0x0040, 9, 1), + PIN_FIELD_BASE(99, IOCFG_LT_BASE, 0x0040, 11, 1), + PIN_FIELD_BASE(100, IOCFG_RM_BASE, 0x0060, 27, 1), + PIN_FIELD_BASE(101, IOCFG_RM_BASE, 0x0060, 30, 1), + PIN_FIELD_BASE(102, IOCFG_RM_BASE, 0x0060, 28, 1), + PIN_FIELD_BASE(103, IOCFG_RM_BASE, 0x0060, 31, 1), + PIN_FIELD_BASE(104, IOCFG_RM_BASE, 0x0060, 29, 1), + PIN_FIELD_BASE(105, IOCFG_RM_BASE, 0x0070, 0, 1), + PIN_FIELD_BASE(106, IOCFG_LT_BASE, 0x0040, 10, 1), + PIN_FIELD_BASE(107, IOCFG_LT_BASE, 0x0040, 12, 1), + PIN_FIELD_BASE(108, IOCFG_LB_BASE, 0x0080, 2, 1), + PIN_FIELD_BASE(109, IOCFG_LB_BASE, 0x0080, 7, 1), + PIN_FIELD_BASE(110, IOCFG_LB_BASE, 0x0080, 3, 1), + PIN_FIELD_BASE(111, IOCFG_LB_BASE, 0x0080, 8, 1), + PIN_FIELD_BASE(112, IOCFG_LB_BASE, 0x0080, 4, 1), + PIN_FIELD_BASE(113, IOCFG_LB_BASE, 0x0080, 9, 1), + PIN_FIELD_BASE(114, IOCFG_LB_BASE, 0x0080, 5, 1), + PIN_FIELD_BASE(115, IOCFG_LB_BASE, 0x0080, 10, 1), + PIN_FIELD_BASE(116, IOCFG_LB_BASE, 0x0080, 11, 1), + PIN_FIELD_BASE(117, IOCFG_LB_BASE, 0x0080, 6, 1), + PIN_FIELD_BASE(118, IOCFG_LB_BASE, 0x0080, 12, 1), + PIN_FIELD_BASE(119, IOCFG_LB_BASE, 0x0080, 13, 1), + PIN_FIELD_BASE(120, IOCFG_LB_BASE, 0x0080, 15, 1), + PIN_FIELD_BASE(121, IOCFG_LB_BASE, 0x0080, 14, 1), + PIN_FIELD_BASE(122, IOCFG_TR_BASE, 0x0020, 10, 1), + PIN_FIELD_BASE(123, IOCFG_TR_BASE, 0x0020, 0, 1), + PIN_FIELD_BASE(124, IOCFG_TR_BASE, 0x0020, 1, 1), + PIN_FIELD_BASE(125, IOCFG_TR_BASE, 0x0020, 11, 1), + PIN_FIELD_BASE(126, IOCFG_TR_BASE, 0x0020, 2, 1), + PIN_FIELD_BASE(127, IOCFG_TR_BASE, 0x0020, 3, 1), + PIN_FIELD_BASE(128, IOCFG_TR_BASE, 0x0020, 4, 1), + PIN_FIELD_BASE(129, IOCFG_TR_BASE, 0x0020, 5, 1), + PIN_FIELD_BASE(130, IOCFG_TR_BASE, 0x0020, 6, 1), + PIN_FIELD_BASE(131, IOCFG_TR_BASE, 0x0020, 7, 1), + PIN_FIELD_BASE(132, IOCFG_TR_BASE, 0x0020, 8, 1), + PIN_FIELD_BASE(133, IOCFG_TR_BASE, 0x0020, 9, 1), + PIN_FIELD_BASE(134, IOCFG_BM_BASE, 0x0060, 7, 1), + PIN_FIELD_BASE(135, IOCFG_BM_BASE, 0x0060, 8, 1), + PIN_FIELD_BASE(136, IOCFG_BM_BASE, 0x0060, 9, 1), + PIN_FIELD_BASE(137, IOCFG_BM_BASE, 0x0060, 10, 1), + PIN_FIELD_BASE(138, IOCFG_BM_BASE, 0x0060, 11, 1), + PIN_FIELD_BASE(139, IOCFG_BM_BASE, 0x0060, 12, 1), + PIN_FIELD_BASE(140, IOCFG_RM_BASE, 0x0060, 17, 1), + PIN_FIELD_BASE(141, IOCFG_RM_BASE, 0x0060, 18, 1), + PIN_FIELD_BASE(142, IOCFG_RM_BASE, 0x0060, 19, 1), + PIN_FIELD_BASE(143, IOCFG_RM_BASE, 0x0060, 20, 1), + PIN_FIELD_BASE(144, IOCFG_RM_BASE, 0x0060, 21, 1), + PIN_FIELD_BASE(145, IOCFG_RM_BASE, 0x0060, 22, 1), + PIN_FIELD_BASE(146, IOCFG_LB_BASE, 0x0070, 3, 1), + PIN_FIELD_BASE(147, IOCFG_LB_BASE, 0x0070, 4, 1), + PIN_FIELD_BASE(148, IOCFG_LB_BASE, 0x0070, 0, 1), + PIN_FIELD_BASE(149, IOCFG_LB_BASE, 0x0070, 1, 1), + PIN_FIELD_BASE(150, IOCFG_LB_BASE, 0x0070, 2, 1), + PIN_FIELD_BASE(151, IOCFG_LB_BASE, 0x0070, 5, 1), + PIN_FIELD_BASE(152, IOCFG_LB_BASE, 0x0070, 6, 1), + PIN_FIELD_BASE(153, IOCFG_LB_BASE, 0x0070, 7, 1), + PIN_FIELD_BASE(154, IOCFG_LB_BASE, 0x0070, 8, 1), + PIN_FIELD_BASE(155, IOCFG_LT_BASE, 0x0040, 1, 1), + PIN_FIELD_BASE(156, IOCFG_LT_BASE, 0x0040, 7, 1), + PIN_FIELD_BASE(157, IOCFG_LT_BASE, 0x0040, 4, 1), + PIN_FIELD_BASE(158, IOCFG_LT_BASE, 0x0040, 5, 1), + PIN_FIELD_BASE(159, IOCFG_LT_BASE, 0x0040, 0, 1), + PIN_FIELD_BASE(160, IOCFG_LT_BASE, 0x0040, 6, 1), + PIN_FIELD_BASE(161, IOCFG_LT_BASE, 0x0040, 2, 1), + PIN_FIELD_BASE(162, IOCFG_LT_BASE, 0x0040, 3, 1), + PIN_FIELD_BASE(163, IOCFG_TL_BASE, 0x0010, 2, 1), + PIN_FIELD_BASE(164, IOCFG_TL_BASE, 0x0010, 1, 1), + PIN_FIELD_BASE(165, IOCFG_TL_BASE, 0x0010, 4, 1), + PIN_FIELD_BASE(166, IOCFG_TL_BASE, 0x0010, 3, 1), + PIN_FIELD_BASE(167, IOCFG_TL_BASE, 0x0010, 5, 1), + PIN_FIELD_BASE(168, IOCFG_TL_BASE, 0x0010, 6, 1), + PIN_FIELD_BASE(169, IOCFG_LT_BASE, 0x0040, 14, 1), + PIN_FIELD_BASE(170, IOCFG_LT_BASE, 0x0040, 8, 1), + PIN_FIELD_BASE(171, IOCFG_TL_BASE, 0x0010, 0, 1), +}; + +static const struct mtk_pin_field_calc mt8366_pin_pu_range[] = { + PIN_FIELD_BASE(0, IOCFG_RM_BASE, 0x00a0, 9, 1), + PIN_FIELD_BASE(1, IOCFG_RM_BASE, 0x00a0, 10, 1), + PIN_FIELD_BASE(2, IOCFG_RM_BASE, 0x00a0, 11, 1), + PIN_FIELD_BASE(3, IOCFG_LB_BASE, 0x00b0, 13, 1), + PIN_FIELD_BASE(4, IOCFG_LB_BASE, 0x00b0, 14, 1), + PIN_FIELD_BASE(5, IOCFG_LB_BASE, 0x00b0, 15, 1), + PIN_FIELD_BASE(6, IOCFG_LB_BASE, 0x00b0, 16, 1), + PIN_FIELD_BASE(7, IOCFG_LB_BASE, 0x00b0, 17, 1), + PIN_FIELD_BASE(8, IOCFG_LB_BASE, 0x00b0, 18, 1), + PIN_FIELD_BASE(9, IOCFG_LB_BASE, 0x00b0, 19, 1), + PIN_FIELD_BASE(10, IOCFG_LB_BASE, 0x00b0, 11, 1), + PIN_FIELD_BASE(11, IOCFG_LB_BASE, 0x00b0, 12, 1), + PIN_FIELD_BASE(12, IOCFG_BM_BASE, 0x00a0, 0, 1), + PIN_FIELD_BASE(13, IOCFG_BM_BASE, 0x00a0, 1, 1), + PIN_FIELD_BASE(14, IOCFG_BM_BASE, 0x00a0, 12, 1), + PIN_FIELD_BASE(15, IOCFG_BM_BASE, 0x00a0, 17, 1), + PIN_FIELD_BASE(16, IOCFG_BM_BASE, 0x00a0, 18, 1), + PIN_FIELD_BASE(17, IOCFG_BM_BASE, 0x00a0, 19, 1), + PIN_FIELD_BASE(18, IOCFG_BM_BASE, 0x00a0, 20, 1), + PIN_FIELD_BASE(19, IOCFG_BM_BASE, 0x00a0, 21, 1), + PIN_FIELD_BASE(20, IOCFG_BM_BASE, 0x00a0, 22, 1), + PIN_FIELD_BASE(21, IOCFG_BM_BASE, 0x00a0, 23, 1), + PIN_FIELD_BASE(22, IOCFG_BM_BASE, 0x00a0, 2, 1), + PIN_FIELD_BASE(23, IOCFG_BM_BASE, 0x00a0, 3, 1), + PIN_FIELD_BASE(24, IOCFG_BM_BASE, 0x00a0, 4, 1), + PIN_FIELD_BASE(25, IOCFG_BM_BASE, 0x00a0, 5, 1), + PIN_FIELD_BASE(26, IOCFG_BM_BASE, 0x00a0, 6, 1), + PIN_FIELD_BASE(27, IOCFG_BM_BASE, 0x00a0, 7, 1), + PIN_FIELD_BASE(28, IOCFG_BM_BASE, 0x00a0, 8, 1), + PIN_FIELD_BASE(29, IOCFG_BM_BASE, 0x00a0, 9, 1), + PIN_FIELD_BASE(30, IOCFG_BM_BASE, 0x00a0, 10, 1), + PIN_FIELD_BASE(31, IOCFG_BM_BASE, 0x00a0, 11, 1), + PIN_FIELD_BASE(32, IOCFG_BM_BASE, 0x00a0, 13, 1), + PIN_FIELD_BASE(33, IOCFG_BM_BASE, 0x00a0, 14, 1), + PIN_FIELD_BASE(34, IOCFG_BM_BASE, 0x00a0, 15, 1), + PIN_FIELD_BASE(35, IOCFG_BM_BASE, 0x00a0, 16, 1), + PIN_FIELD_BASE(36, IOCFG_BM_BASE, 0x00a0, 31, 1), + PIN_FIELD_BASE(37, IOCFG_BM_BASE, 0x00b0, 0, 1), + PIN_FIELD_BASE(38, IOCFG_BM_BASE, 0x00b0, 1, 1), + PIN_FIELD_BASE(39, IOCFG_BM_BASE, 0x00a0, 24, 1), + PIN_FIELD_BASE(40, IOCFG_BM_BASE, 0x00a0, 25, 1), + PIN_FIELD_BASE(41, IOCFG_BM_BASE, 0x00a0, 26, 1), + PIN_FIELD_BASE(42, IOCFG_BM_BASE, 0x00b0, 5, 1), + PIN_FIELD_BASE(43, IOCFG_BM_BASE, 0x00b0, 7, 1), + PIN_FIELD_BASE(44, IOCFG_BM_BASE, 0x00b0, 6, 1), + PIN_FIELD_BASE(45, IOCFG_BM_BASE, 0x00a0, 27, 1), + PIN_FIELD_BASE(46, IOCFG_BM_BASE, 0x00a0, 28, 1), + PIN_FIELD_BASE(47, IOCFG_BM_BASE, 0x00a0, 29, 1), + PIN_FIELD_BASE(48, IOCFG_BM_BASE, 0x00a0, 30, 1), + PIN_FIELD_BASE(49, IOCFG_BM_BASE, 0x00b0, 3, 1), + PIN_FIELD_BASE(50, IOCFG_BM_BASE, 0x00b0, 4, 1), + PIN_FIELD_BASE(51, IOCFG_BM_BASE, 0x00b0, 2, 1), + PIN_FIELD_BASE(52, IOCFG_RM_BASE, 0x00a0, 12, 1), + PIN_FIELD_BASE(53, IOCFG_RM_BASE, 0x00a0, 23, 1), + PIN_FIELD_BASE(54, IOCFG_RM_BASE, 0x00a0, 25, 1), + PIN_FIELD_BASE(55, IOCFG_RM_BASE, 0x00a0, 24, 1), + PIN_FIELD_BASE(56, IOCFG_LT_BASE, 0x0060, 15, 1), + PIN_FIELD_BASE(57, IOCFG_RM_BASE, 0x00a0, 2, 1), + PIN_FIELD_BASE(58, IOCFG_RM_BASE, 0x00a0, 4, 1), + PIN_FIELD_BASE(59, IOCFG_RM_BASE, 0x00a0, 0, 1), + PIN_FIELD_BASE(60, IOCFG_RM_BASE, 0x00a0, 3, 1), + PIN_FIELD_BASE(61, IOCFG_RM_BASE, 0x00a0, 5, 1), + PIN_FIELD_BASE(62, IOCFG_RM_BASE, 0x00a0, 1, 1), + PIN_FIELD_BASE(63, IOCFG_LB_BASE, 0x00b0, 10, 1), + PIN_FIELD_BASE(64, IOCFG_LB_BASE, 0x00b0, 9, 1), + PIN_FIELD_BASE(65, IOCFG_LB_BASE, 0x00c0, 1, 1), + PIN_FIELD_BASE(66, IOCFG_LB_BASE, 0x00c0, 16, 1), + PIN_FIELD_BASE(67, IOCFG_LB_BASE, 0x00c0, 20, 1), + PIN_FIELD_BASE(68, IOCFG_LB_BASE, 0x00c0, 17, 1), + PIN_FIELD_BASE(69, IOCFG_LB_BASE, 0x00c0, 21, 1), + PIN_FIELD_BASE(70, IOCFG_LB_BASE, 0x00c0, 18, 1), + PIN_FIELD_BASE(71, IOCFG_LB_BASE, 0x00c0, 22, 1), + PIN_FIELD_BASE(72, IOCFG_LB_BASE, 0x00c0, 19, 1), + PIN_FIELD_BASE(73, IOCFG_LB_BASE, 0x00c0, 23, 1), + PIN_FIELD_BASE(74, IOCFG_LB_BASE, 0x00b0, 31, 1), + PIN_FIELD_BASE(75, IOCFG_LB_BASE, 0x00b0, 28, 1), + PIN_FIELD_BASE(76, IOCFG_LB_BASE, 0x00b0, 29, 1), + PIN_FIELD_BASE(77, IOCFG_LB_BASE, 0x00b0, 30, 1), + PIN_FIELD_BASE(78, IOCFG_LB_BASE, 0x00c0, 0, 1), + PIN_FIELD_BASE(83, IOCFG_RM_BASE, 0x00a0, 6, 1), + PIN_FIELD_BASE(84, IOCFG_RM_BASE, 0x00a0, 7, 1), + PIN_FIELD_BASE(85, IOCFG_RM_BASE, 0x00a0, 8, 1), + PIN_FIELD_BASE(86, IOCFG_RM_BASE, 0x00a0, 13, 1), + PIN_FIELD_BASE(87, IOCFG_RM_BASE, 0x00a0, 16, 1), + PIN_FIELD_BASE(88, IOCFG_RM_BASE, 0x00a0, 14, 1), + PIN_FIELD_BASE(89, IOCFG_RM_BASE, 0x00a0, 15, 1), + PIN_FIELD_BASE(90, IOCFG_LB_BASE, 0x00b0, 22, 1), + PIN_FIELD_BASE(91, IOCFG_LB_BASE, 0x00b0, 20, 1), + PIN_FIELD_BASE(92, IOCFG_LB_BASE, 0x00b0, 23, 1), + PIN_FIELD_BASE(93, IOCFG_LB_BASE, 0x00b0, 21, 1), + PIN_FIELD_BASE(94, IOCFG_LB_BASE, 0x00b0, 26, 1), + PIN_FIELD_BASE(95, IOCFG_LB_BASE, 0x00b0, 24, 1), + PIN_FIELD_BASE(96, IOCFG_LB_BASE, 0x00b0, 27, 1), + PIN_FIELD_BASE(97, IOCFG_LB_BASE, 0x00b0, 25, 1), + PIN_FIELD_BASE(98, IOCFG_LT_BASE, 0x0060, 9, 1), + PIN_FIELD_BASE(99, IOCFG_LT_BASE, 0x0060, 11, 1), + PIN_FIELD_BASE(100, IOCFG_RM_BASE, 0x00a0, 17, 1), + PIN_FIELD_BASE(101, IOCFG_RM_BASE, 0x00a0, 20, 1), + PIN_FIELD_BASE(102, IOCFG_RM_BASE, 0x00a0, 18, 1), + PIN_FIELD_BASE(103, IOCFG_RM_BASE, 0x00a0, 21, 1), + PIN_FIELD_BASE(104, IOCFG_RM_BASE, 0x00a0, 19, 1), + PIN_FIELD_BASE(105, IOCFG_RM_BASE, 0x00a0, 22, 1), + PIN_FIELD_BASE(106, IOCFG_LT_BASE, 0x0060, 10, 1), + PIN_FIELD_BASE(107, IOCFG_LT_BASE, 0x0060, 12, 1), + PIN_FIELD_BASE(108, IOCFG_LB_BASE, 0x00c0, 2, 1), + PIN_FIELD_BASE(109, IOCFG_LB_BASE, 0x00c0, 7, 1), + PIN_FIELD_BASE(110, IOCFG_LB_BASE, 0x00c0, 3, 1), + PIN_FIELD_BASE(111, IOCFG_LB_BASE, 0x00c0, 8, 1), + PIN_FIELD_BASE(112, IOCFG_LB_BASE, 0x00c0, 4, 1), + PIN_FIELD_BASE(113, IOCFG_LB_BASE, 0x00c0, 9, 1), + PIN_FIELD_BASE(114, IOCFG_LB_BASE, 0x00c0, 5, 1), + PIN_FIELD_BASE(115, IOCFG_LB_BASE, 0x00c0, 10, 1), + PIN_FIELD_BASE(116, IOCFG_LB_BASE, 0x00c0, 11, 1), + PIN_FIELD_BASE(117, IOCFG_LB_BASE, 0x00c0, 6, 1), + PIN_FIELD_BASE(118, IOCFG_LB_BASE, 0x00c0, 12, 1), + PIN_FIELD_BASE(119, IOCFG_LB_BASE, 0x00c0, 13, 1), + PIN_FIELD_BASE(120, IOCFG_LB_BASE, 0x00c0, 15, 1), + PIN_FIELD_BASE(121, IOCFG_LB_BASE, 0x00c0, 14, 1), + PIN_FIELD_BASE(146, IOCFG_LB_BASE, 0x00b0, 3, 1), + PIN_FIELD_BASE(147, IOCFG_LB_BASE, 0x00b0, 4, 1), + PIN_FIELD_BASE(148, IOCFG_LB_BASE, 0x00b0, 0, 1), + PIN_FIELD_BASE(149, IOCFG_LB_BASE, 0x00b0, 1, 1), + PIN_FIELD_BASE(150, IOCFG_LB_BASE, 0x00b0, 2, 1), + PIN_FIELD_BASE(151, IOCFG_LB_BASE, 0x00b0, 5, 1), + PIN_FIELD_BASE(152, IOCFG_LB_BASE, 0x00b0, 6, 1), + PIN_FIELD_BASE(153, IOCFG_LB_BASE, 0x00b0, 7, 1), + PIN_FIELD_BASE(154, IOCFG_LB_BASE, 0x00b0, 8, 1), + PIN_FIELD_BASE(155, IOCFG_LT_BASE, 0x0060, 1, 1), + PIN_FIELD_BASE(156, IOCFG_LT_BASE, 0x0060, 7, 1), + PIN_FIELD_BASE(157, IOCFG_LT_BASE, 0x0060, 4, 1), + PIN_FIELD_BASE(158, IOCFG_LT_BASE, 0x0060, 5, 1), + PIN_FIELD_BASE(159, IOCFG_LT_BASE, 0x0060, 0, 1), + PIN_FIELD_BASE(160, IOCFG_LT_BASE, 0x0060, 6, 1), + PIN_FIELD_BASE(161, IOCFG_LT_BASE, 0x0060, 2, 1), + PIN_FIELD_BASE(162, IOCFG_LT_BASE, 0x0060, 3, 1), + PIN_FIELD_BASE(163, IOCFG_TL_BASE, 0x0030, 2, 1), + PIN_FIELD_BASE(164, IOCFG_TL_BASE, 0x0030, 1, 1), + PIN_FIELD_BASE(165, IOCFG_TL_BASE, 0x0030, 4, 1), + PIN_FIELD_BASE(166, IOCFG_TL_BASE, 0x0030, 3, 1), + PIN_FIELD_BASE(167, IOCFG_TL_BASE, 0x0030, 5, 1), + PIN_FIELD_BASE(168, IOCFG_TL_BASE, 0x0030, 6, 1), + PIN_FIELD_BASE(169, IOCFG_LT_BASE, 0x0060, 16, 1), + PIN_FIELD_BASE(170, IOCFG_LT_BASE, 0x0060, 8, 1), + PIN_FIELD_BASE(171, IOCFG_TL_BASE, 0x0030, 0, 1), +}; + +static const struct mtk_pin_field_calc mt8366_pin_pd_range[] = { + PIN_FIELD_BASE(0, IOCFG_RM_BASE, 0x0080, 9, 1), + PIN_FIELD_BASE(1, IOCFG_RM_BASE, 0x0080, 10, 1), + PIN_FIELD_BASE(2, IOCFG_RM_BASE, 0x0080, 11, 1), + PIN_FIELD_BASE(3, IOCFG_LB_BASE, 0x0090, 13, 1), + PIN_FIELD_BASE(4, IOCFG_LB_BASE, 0x0090, 14, 1), + PIN_FIELD_BASE(5, IOCFG_LB_BASE, 0x0090, 15, 1), + PIN_FIELD_BASE(6, IOCFG_LB_BASE, 0x0090, 16, 1), + PIN_FIELD_BASE(7, IOCFG_LB_BASE, 0x0090, 17, 1), + PIN_FIELD_BASE(8, IOCFG_LB_BASE, 0x0090, 18, 1), + PIN_FIELD_BASE(9, IOCFG_LB_BASE, 0x0090, 19, 1), + PIN_FIELD_BASE(10, IOCFG_LB_BASE, 0x0090, 11, 1), + PIN_FIELD_BASE(11, IOCFG_LB_BASE, 0x0090, 12, 1), + PIN_FIELD_BASE(12, IOCFG_BM_BASE, 0x0070, 0, 1), + PIN_FIELD_BASE(13, IOCFG_BM_BASE, 0x0070, 1, 1), + PIN_FIELD_BASE(14, IOCFG_BM_BASE, 0x0070, 12, 1), + PIN_FIELD_BASE(15, IOCFG_BM_BASE, 0x0070, 17, 1), + PIN_FIELD_BASE(16, IOCFG_BM_BASE, 0x0070, 18, 1), + PIN_FIELD_BASE(17, IOCFG_BM_BASE, 0x0070, 19, 1), + PIN_FIELD_BASE(18, IOCFG_BM_BASE, 0x0070, 20, 1), + PIN_FIELD_BASE(19, IOCFG_BM_BASE, 0x0070, 21, 1), + PIN_FIELD_BASE(20, IOCFG_BM_BASE, 0x0070, 22, 1), + PIN_FIELD_BASE(21, IOCFG_BM_BASE, 0x0070, 23, 1), + PIN_FIELD_BASE(22, IOCFG_BM_BASE, 0x0070, 2, 1), + PIN_FIELD_BASE(23, IOCFG_BM_BASE, 0x0070, 3, 1), + PIN_FIELD_BASE(24, IOCFG_BM_BASE, 0x0070, 4, 1), + PIN_FIELD_BASE(25, IOCFG_BM_BASE, 0x0070, 5, 1), + PIN_FIELD_BASE(26, IOCFG_BM_BASE, 0x0070, 6, 1), + PIN_FIELD_BASE(27, IOCFG_BM_BASE, 0x0070, 7, 1), + PIN_FIELD_BASE(28, IOCFG_BM_BASE, 0x0070, 8, 1), + PIN_FIELD_BASE(29, IOCFG_BM_BASE, 0x0070, 9, 1), + PIN_FIELD_BASE(30, IOCFG_BM_BASE, 0x0070, 10, 1), + PIN_FIELD_BASE(31, IOCFG_BM_BASE, 0x0070, 11, 1), + PIN_FIELD_BASE(32, IOCFG_BM_BASE, 0x0070, 13, 1), + PIN_FIELD_BASE(33, IOCFG_BM_BASE, 0x0070, 14, 1), + PIN_FIELD_BASE(34, IOCFG_BM_BASE, 0x0070, 15, 1), + PIN_FIELD_BASE(35, IOCFG_BM_BASE, 0x0070, 16, 1), + PIN_FIELD_BASE(36, IOCFG_BM_BASE, 0x0070, 31, 1), + PIN_FIELD_BASE(37, IOCFG_BM_BASE, 0x0080, 0, 1), + PIN_FIELD_BASE(38, IOCFG_BM_BASE, 0x0080, 1, 1), + PIN_FIELD_BASE(39, IOCFG_BM_BASE, 0x0070, 24, 1), + PIN_FIELD_BASE(40, IOCFG_BM_BASE, 0x0070, 25, 1), + PIN_FIELD_BASE(41, IOCFG_BM_BASE, 0x0070, 26, 1), + PIN_FIELD_BASE(42, IOCFG_BM_BASE, 0x0080, 5, 1), + PIN_FIELD_BASE(43, IOCFG_BM_BASE, 0x0080, 7, 1), + PIN_FIELD_BASE(44, IOCFG_BM_BASE, 0x0080, 6, 1), + PIN_FIELD_BASE(45, IOCFG_BM_BASE, 0x0070, 27, 1), + PIN_FIELD_BASE(46, IOCFG_BM_BASE, 0x0070, 28, 1), + PIN_FIELD_BASE(47, IOCFG_BM_BASE, 0x0070, 29, 1), + PIN_FIELD_BASE(48, IOCFG_BM_BASE, 0x0070, 30, 1), + PIN_FIELD_BASE(49, IOCFG_BM_BASE, 0x0080, 3, 1), + PIN_FIELD_BASE(50, IOCFG_BM_BASE, 0x0080, 4, 1), + PIN_FIELD_BASE(51, IOCFG_BM_BASE, 0x0080, 2, 1), + PIN_FIELD_BASE(52, IOCFG_RM_BASE, 0x0080, 12, 1), + PIN_FIELD_BASE(53, IOCFG_RM_BASE, 0x0080, 23, 1), + PIN_FIELD_BASE(54, IOCFG_RM_BASE, 0x0080, 25, 1), + PIN_FIELD_BASE(55, IOCFG_RM_BASE, 0x0080, 24, 1), + PIN_FIELD_BASE(56, IOCFG_LT_BASE, 0x0050, 15, 1), + PIN_FIELD_BASE(57, IOCFG_RM_BASE, 0x0080, 2, 1), + PIN_FIELD_BASE(58, IOCFG_RM_BASE, 0x0080, 4, 1), + PIN_FIELD_BASE(59, IOCFG_RM_BASE, 0x0080, 0, 1), + PIN_FIELD_BASE(60, IOCFG_RM_BASE, 0x0080, 3, 1), + PIN_FIELD_BASE(61, IOCFG_RM_BASE, 0x0080, 5, 1), + PIN_FIELD_BASE(62, IOCFG_RM_BASE, 0x0080, 1, 1), + PIN_FIELD_BASE(63, IOCFG_LB_BASE, 0x0090, 10, 1), + PIN_FIELD_BASE(64, IOCFG_LB_BASE, 0x0090, 9, 1), + PIN_FIELD_BASE(65, IOCFG_LB_BASE, 0x00a0, 1, 1), + PIN_FIELD_BASE(66, IOCFG_LB_BASE, 0x00a0, 16, 1), + PIN_FIELD_BASE(67, IOCFG_LB_BASE, 0x00a0, 20, 1), + PIN_FIELD_BASE(68, IOCFG_LB_BASE, 0x00a0, 17, 1), + PIN_FIELD_BASE(69, IOCFG_LB_BASE, 0x00a0, 21, 1), + PIN_FIELD_BASE(70, IOCFG_LB_BASE, 0x00a0, 18, 1), + PIN_FIELD_BASE(71, IOCFG_LB_BASE, 0x00a0, 22, 1), + PIN_FIELD_BASE(72, IOCFG_LB_BASE, 0x00a0, 19, 1), + PIN_FIELD_BASE(73, IOCFG_LB_BASE, 0x00a0, 23, 1), + PIN_FIELD_BASE(74, IOCFG_LB_BASE, 0x0090, 31, 1), + PIN_FIELD_BASE(75, IOCFG_LB_BASE, 0x0090, 28, 1), + PIN_FIELD_BASE(76, IOCFG_LB_BASE, 0x0090, 29, 1), + PIN_FIELD_BASE(77, IOCFG_LB_BASE, 0x0090, 30, 1), + PIN_FIELD_BASE(78, IOCFG_LB_BASE, 0x00a0, 0, 1), + PIN_FIELD_BASE(83, IOCFG_RM_BASE, 0x0080, 6, 1), + PIN_FIELD_BASE(84, IOCFG_RM_BASE, 0x0080, 7, 1), + PIN_FIELD_BASE(85, IOCFG_RM_BASE, 0x0080, 8, 1), + PIN_FIELD_BASE(86, IOCFG_RM_BASE, 0x0080, 13, 1), + PIN_FIELD_BASE(87, IOCFG_RM_BASE, 0x0080, 16, 1), + PIN_FIELD_BASE(88, IOCFG_RM_BASE, 0x0080, 14, 1), + PIN_FIELD_BASE(89, IOCFG_RM_BASE, 0x0080, 15, 1), + PIN_FIELD_BASE(90, IOCFG_LB_BASE, 0x0090, 22, 1), + PIN_FIELD_BASE(91, IOCFG_LB_BASE, 0x0090, 20, 1), + PIN_FIELD_BASE(92, IOCFG_LB_BASE, 0x0090, 23, 1), + PIN_FIELD_BASE(93, IOCFG_LB_BASE, 0x0090, 21, 1), + PIN_FIELD_BASE(94, IOCFG_LB_BASE, 0x0090, 26, 1), + PIN_FIELD_BASE(95, IOCFG_LB_BASE, 0x0090, 24, 1), + PIN_FIELD_BASE(96, IOCFG_LB_BASE, 0x0090, 27, 1), + PIN_FIELD_BASE(97, IOCFG_LB_BASE, 0x0090, 25, 1), + PIN_FIELD_BASE(98, IOCFG_LT_BASE, 0x0050, 9, 1), + PIN_FIELD_BASE(99, IOCFG_LT_BASE, 0x0050, 11, 1), + PIN_FIELD_BASE(100, IOCFG_RM_BASE, 0x0080, 17, 1), + PIN_FIELD_BASE(101, IOCFG_RM_BASE, 0x0080, 20, 1), + PIN_FIELD_BASE(102, IOCFG_RM_BASE, 0x0080, 18, 1), + PIN_FIELD_BASE(103, IOCFG_RM_BASE, 0x0080, 21, 1), + PIN_FIELD_BASE(104, IOCFG_RM_BASE, 0x0080, 19, 1), + PIN_FIELD_BASE(105, IOCFG_RM_BASE, 0x0080, 22, 1), + PIN_FIELD_BASE(106, IOCFG_LT_BASE, 0x0050, 10, 1), + PIN_FIELD_BASE(107, IOCFG_LT_BASE, 0x0050, 12, 1), + PIN_FIELD_BASE(108, IOCFG_LB_BASE, 0x00a0, 2, 1), + PIN_FIELD_BASE(109, IOCFG_LB_BASE, 0x00a0, 7, 1), + PIN_FIELD_BASE(110, IOCFG_LB_BASE, 0x00a0, 3, 1), + PIN_FIELD_BASE(111, IOCFG_LB_BASE, 0x00a0, 8, 1), + PIN_FIELD_BASE(112, IOCFG_LB_BASE, 0x00a0, 4, 1), + PIN_FIELD_BASE(113, IOCFG_LB_BASE, 0x00a0, 9, 1), + PIN_FIELD_BASE(114, IOCFG_LB_BASE, 0x00a0, 5, 1), + PIN_FIELD_BASE(115, IOCFG_LB_BASE, 0x00a0, 10, 1), + PIN_FIELD_BASE(116, IOCFG_LB_BASE, 0x00a0, 11, 1), + PIN_FIELD_BASE(117, IOCFG_LB_BASE, 0x00a0, 6, 1), + PIN_FIELD_BASE(118, IOCFG_LB_BASE, 0x00a0, 12, 1), + PIN_FIELD_BASE(119, IOCFG_LB_BASE, 0x00a0, 13, 1), + PIN_FIELD_BASE(120, IOCFG_LB_BASE, 0x00a0, 15, 1), + PIN_FIELD_BASE(121, IOCFG_LB_BASE, 0x00a0, 14, 1), + PIN_FIELD_BASE(146, IOCFG_LB_BASE, 0x0090, 3, 1), + PIN_FIELD_BASE(147, IOCFG_LB_BASE, 0x0090, 4, 1), + PIN_FIELD_BASE(148, IOCFG_LB_BASE, 0x0090, 0, 1), + PIN_FIELD_BASE(149, IOCFG_LB_BASE, 0x0090, 1, 1), + PIN_FIELD_BASE(150, IOCFG_LB_BASE, 0x0090, 2, 1), + PIN_FIELD_BASE(151, IOCFG_LB_BASE, 0x0090, 5, 1), + PIN_FIELD_BASE(152, IOCFG_LB_BASE, 0x0090, 6, 1), + PIN_FIELD_BASE(153, IOCFG_LB_BASE, 0x0090, 7, 1), + PIN_FIELD_BASE(154, IOCFG_LB_BASE, 0x0090, 8, 1), + PIN_FIELD_BASE(155, IOCFG_LT_BASE, 0x0050, 1, 1), + PIN_FIELD_BASE(156, IOCFG_LT_BASE, 0x0050, 7, 1), + PIN_FIELD_BASE(157, IOCFG_LT_BASE, 0x0050, 4, 1), + PIN_FIELD_BASE(158, IOCFG_LT_BASE, 0x0050, 5, 1), + PIN_FIELD_BASE(159, IOCFG_LT_BASE, 0x0050, 0, 1), + PIN_FIELD_BASE(160, IOCFG_LT_BASE, 0x0050, 6, 1), + PIN_FIELD_BASE(161, IOCFG_LT_BASE, 0x0050, 2, 1), + PIN_FIELD_BASE(162, IOCFG_LT_BASE, 0x0050, 3, 1), + PIN_FIELD_BASE(163, IOCFG_TL_BASE, 0x0020, 2, 1), + PIN_FIELD_BASE(164, IOCFG_TL_BASE, 0x0020, 1, 1), + PIN_FIELD_BASE(165, IOCFG_TL_BASE, 0x0020, 4, 1), + PIN_FIELD_BASE(166, IOCFG_TL_BASE, 0x0020, 3, 1), + PIN_FIELD_BASE(167, IOCFG_TL_BASE, 0x0020, 5, 1), + PIN_FIELD_BASE(168, IOCFG_TL_BASE, 0x0020, 6, 1), + PIN_FIELD_BASE(169, IOCFG_LT_BASE, 0x0050, 16, 1), + PIN_FIELD_BASE(170, IOCFG_LT_BASE, 0x0050, 8, 1), + PIN_FIELD_BASE(171, IOCFG_TL_BASE, 0x0020, 0, 1), +}; + +static const struct mtk_pin_field_calc mt8366_pin_drv_range[] = { + PIN_FIELD_BASE(0, IOCFG_RM_BASE, 0x0000, 27, 3), + PIN_FIELD_BASE(1, IOCFG_RM_BASE, 0x0010, 0, 3), + PIN_FIELD_BASE(2, IOCFG_RM_BASE, 0x0010, 3, 3), + PIN_FIELD_BASE(3, IOCFG_LB_BASE, 0x0010, 3, 3), + PIN_FIELD_BASE(4, IOCFG_LB_BASE, 0x0010, 6, 3), + PIN_FIELD_BASE(5, IOCFG_LB_BASE, 0x0010, 9, 3), + PIN_FIELD_BASE(6, IOCFG_LB_BASE, 0x0020, 15, 3), + PIN_FIELD_BASE(7, IOCFG_LB_BASE, 0x0020, 15, 3), + PIN_FIELD_BASE(8, IOCFG_LB_BASE, 0x0020, 15, 3), + PIN_FIELD_BASE(9, IOCFG_LB_BASE, 0x0020, 9, 3), + PIN_FIELD_BASE(10, IOCFG_LB_BASE, 0x0020, 9, 3), + PIN_FIELD_BASE(11, IOCFG_LB_BASE, 0x0020, 15, 3), + PIN_FIELD_BASE(12, IOCFG_BM_BASE, 0x0000, 0, 3), + PIN_FIELD_BASE(13, IOCFG_BM_BASE, 0x0010, 3, 3), + PIN_FIELD_BASE(14, IOCFG_BM_BASE, 0x0010, 18, 3), + PIN_FIELD_BASE(15, IOCFG_BM_BASE, 0x0010, 21, 3), + PIN_FIELD_BASE(16, IOCFG_BM_BASE, 0x0010, 24, 3), + PIN_FIELD_BASE(17, IOCFG_BM_BASE, 0x0010, 27, 3), + PIN_FIELD_BASE(18, IOCFG_BM_BASE, 0x0020, 0, 3), + PIN_FIELD_BASE(19, IOCFG_BM_BASE, 0x0020, 3, 3), + PIN_FIELD_BASE(20, IOCFG_BM_BASE, 0x0020, 6, 3), + PIN_FIELD_BASE(21, IOCFG_BM_BASE, 0x0020, 9, 3), + PIN_FIELD_BASE(22, IOCFG_BM_BASE, 0x0000, 3, 3), + PIN_FIELD_BASE(23, IOCFG_BM_BASE, 0x0000, 6, 3), + PIN_FIELD_BASE(24, IOCFG_BM_BASE, 0x0000, 9, 3), + PIN_FIELD_BASE(25, IOCFG_BM_BASE, 0x0000, 12, 3), + PIN_FIELD_BASE(26, IOCFG_BM_BASE, 0x0000, 15, 3), + PIN_FIELD_BASE(27, IOCFG_BM_BASE, 0x0000, 18, 3), + PIN_FIELD_BASE(28, IOCFG_BM_BASE, 0x0000, 21, 3), + PIN_FIELD_BASE(29, IOCFG_BM_BASE, 0x0000, 24, 3), + PIN_FIELD_BASE(30, IOCFG_BM_BASE, 0x0000, 27, 3), + PIN_FIELD_BASE(31, IOCFG_BM_BASE, 0x0010, 0, 3), + PIN_FIELD_BASE(32, IOCFG_BM_BASE, 0x0010, 6, 3), + PIN_FIELD_BASE(33, IOCFG_BM_BASE, 0x0010, 9, 3), + PIN_FIELD_BASE(34, IOCFG_BM_BASE, 0x0010, 12, 3), + PIN_FIELD_BASE(35, IOCFG_BM_BASE, 0x0010, 15, 3), + PIN_FIELD_BASE(36, IOCFG_BM_BASE, 0x0020, 27, 3), + PIN_FIELD_BASE(37, IOCFG_BM_BASE, 0x0030, 0, 3), + PIN_FIELD_BASE(38, IOCFG_BM_BASE, 0x0030, 3, 3), + PIN_FIELD_BASE(39, IOCFG_BM_BASE, 0x0020, 12, 3), + PIN_FIELD_BASE(40, IOCFG_BM_BASE, 0x0020, 15, 3), + PIN_FIELD_BASE(41, IOCFG_BM_BASE, 0x0020, 18, 3), + PIN_FIELD_BASE(42, IOCFG_BM_BASE, 0x0030, 12, 3), + PIN_FIELD_BASE(43, IOCFG_BM_BASE, 0x0040, 6, 3), + PIN_FIELD_BASE(44, IOCFG_BM_BASE, 0x0040, 3, 3), + PIN_FIELD_BASE(45, IOCFG_BM_BASE, 0x0040, 3, 3), + PIN_FIELD_BASE(46, IOCFG_BM_BASE, 0x0040, 3, 3), + PIN_FIELD_BASE(47, IOCFG_BM_BASE, 0x0020, 21, 3), + PIN_FIELD_BASE(48, IOCFG_BM_BASE, 0x0020, 24, 3), + PIN_FIELD_BASE(49, IOCFG_BM_BASE, 0x0030, 6, 3), + PIN_FIELD_BASE(50, IOCFG_BM_BASE, 0x0030, 9, 3), + PIN_FIELD_BASE(51, IOCFG_BM_BASE, 0x0040, 3, 3), + PIN_FIELD_BASE(52, IOCFG_RM_BASE, 0x0020, 6, 3), + PIN_FIELD_BASE(53, IOCFG_RM_BASE, 0x0020, 6, 3), + PIN_FIELD_BASE(54, IOCFG_RM_BASE, 0x0020, 6, 3), + PIN_FIELD_BASE(55, IOCFG_RM_BASE, 0x0020, 12, 3), + PIN_FIELD_BASE(56, IOCFG_LT_BASE, 0x0000, 24, 3), + PIN_FIELD_BASE(57, IOCFG_RM_BASE, 0x0000, 6, 3), + PIN_FIELD_BASE(58, IOCFG_RM_BASE, 0x0000, 12, 3), + PIN_FIELD_BASE(59, IOCFG_RM_BASE, 0x0000, 0, 3), + PIN_FIELD_BASE(60, IOCFG_RM_BASE, 0x0000, 9, 3), + PIN_FIELD_BASE(61, IOCFG_RM_BASE, 0x0000, 15, 3), + PIN_FIELD_BASE(62, IOCFG_RM_BASE, 0x0000, 3, 3), + PIN_FIELD_BASE(63, IOCFG_LB_BASE, 0x0010, 0, 3), + PIN_FIELD_BASE(64, IOCFG_LB_BASE, 0x0000, 27, 3), + PIN_FIELD_BASE(65, IOCFG_LB_BASE, 0x0020, 6, 3), + PIN_FIELD_BASE(66, IOCFG_LB_BASE, 0x0020, 21, 3), + PIN_FIELD_BASE(67, IOCFG_LB_BASE, 0x0020, 21, 3), + PIN_FIELD_BASE(68, IOCFG_LB_BASE, 0x0020, 12, 3), + PIN_FIELD_BASE(69, IOCFG_LB_BASE, 0x0020, 12, 3), + PIN_FIELD_BASE(70, IOCFG_LB_BASE, 0x0020, 12, 3), + PIN_FIELD_BASE(71, IOCFG_LB_BASE, 0x0020, 12, 3), + PIN_FIELD_BASE(72, IOCFG_LB_BASE, 0x0020, 21, 3), + PIN_FIELD_BASE(73, IOCFG_LB_BASE, 0x0020, 12, 3), + PIN_FIELD_BASE(74, IOCFG_LB_BASE, 0x0020, 18, 3), + PIN_FIELD_BASE(75, IOCFG_LB_BASE, 0x0020, 21, 3), + PIN_FIELD_BASE(76, IOCFG_LB_BASE, 0x0020, 18, 3), + PIN_FIELD_BASE(77, IOCFG_LB_BASE, 0x0020, 18, 3), + PIN_FIELD_BASE(78, IOCFG_LB_BASE, 0x0020, 18, 3), + PIN_FIELD_BASE(79, IOCFG_RM_BASE, 0x0020, 12, 3), + PIN_FIELD_BASE(80, IOCFG_RM_BASE, 0x0010, 6, 3), + PIN_FIELD_BASE(81, IOCFG_RM_BASE, 0x0020, 12, 3), + PIN_FIELD_BASE(82, IOCFG_RM_BASE, 0x0020, 3, 3), + PIN_FIELD_BASE(83, IOCFG_RM_BASE, 0x0000, 18, 3), + PIN_FIELD_BASE(84, IOCFG_RM_BASE, 0x0000, 21, 3), + PIN_FIELD_BASE(85, IOCFG_RM_BASE, 0x0000, 24, 3), + PIN_FIELD_BASE(86, IOCFG_RM_BASE, 0x0010, 27, 3), + PIN_FIELD_BASE(87, IOCFG_RM_BASE, 0x0020, 0, 3), + PIN_FIELD_BASE(88, IOCFG_RM_BASE, 0x0020, 9, 3), + PIN_FIELD_BASE(89, IOCFG_RM_BASE, 0x0020, 15, 3), + PIN_FIELD_BASE(90, IOCFG_LB_BASE, 0x0010, 18, 3), + PIN_FIELD_BASE(91, IOCFG_LB_BASE, 0x0010, 12, 3), + PIN_FIELD_BASE(92, IOCFG_LB_BASE, 0x0010, 21, 3), + PIN_FIELD_BASE(93, IOCFG_LB_BASE, 0x0010, 15, 3), + PIN_FIELD_BASE(94, IOCFG_LB_BASE, 0x0020, 0, 3), + PIN_FIELD_BASE(95, IOCFG_LB_BASE, 0x0010, 24, 3), + PIN_FIELD_BASE(96, IOCFG_LB_BASE, 0x0020, 3, 3), + PIN_FIELD_BASE(97, IOCFG_LB_BASE, 0x0010, 27, 3), + PIN_FIELD_BASE(98, IOCFG_LT_BASE, 0x0000, 27, 3), + PIN_FIELD_BASE(99, IOCFG_LT_BASE, 0x0010, 3, 3), + PIN_FIELD_BASE(100, IOCFG_RM_BASE, 0x0020, 18, 3), + PIN_FIELD_BASE(101, IOCFG_RM_BASE, 0x0020, 27, 3), + PIN_FIELD_BASE(102, IOCFG_RM_BASE, 0x0020, 21, 3), + PIN_FIELD_BASE(103, IOCFG_RM_BASE, 0x0030, 0, 3), + PIN_FIELD_BASE(104, IOCFG_RM_BASE, 0x0020, 24, 3), + PIN_FIELD_BASE(105, IOCFG_RM_BASE, 0x0030, 3, 3), + PIN_FIELD_BASE(106, IOCFG_LT_BASE, 0x0010, 0, 3), + PIN_FIELD_BASE(107, IOCFG_LT_BASE, 0x0010, 6, 3), + PIN_FIELD_BASE(108, IOCFG_LB_BASE, 0x0020, 24, 3), + PIN_FIELD_BASE(109, IOCFG_LB_BASE, 0x0030, 9, 3), + PIN_FIELD_BASE(110, IOCFG_LB_BASE, 0x0020, 27, 3), + PIN_FIELD_BASE(111, IOCFG_LB_BASE, 0x0030, 12, 3), + PIN_FIELD_BASE(112, IOCFG_LB_BASE, 0x0030, 0, 3), + PIN_FIELD_BASE(113, IOCFG_LB_BASE, 0x0030, 15, 3), + PIN_FIELD_BASE(114, IOCFG_LB_BASE, 0x0030, 3, 3), + PIN_FIELD_BASE(115, IOCFG_LB_BASE, 0x0030, 18, 3), + PIN_FIELD_BASE(116, IOCFG_LB_BASE, 0x0030, 21, 3), + PIN_FIELD_BASE(117, IOCFG_LB_BASE, 0x0030, 6, 3), + PIN_FIELD_BASE(118, IOCFG_LB_BASE, 0x0030, 24, 3), + PIN_FIELD_BASE(119, IOCFG_LB_BASE, 0x0030, 27, 3), + PIN_FIELD_BASE(120, IOCFG_LB_BASE, 0x0040, 3, 3), + PIN_FIELD_BASE(121, IOCFG_LB_BASE, 0x0040, 0, 3), + PIN_FIELD_BASE(122, IOCFG_TR_BASE, 0x0010, 0, 3), + PIN_FIELD_BASE(123, IOCFG_TR_BASE, 0x0000, 0, 3), + PIN_FIELD_BASE(124, IOCFG_TR_BASE, 0x0000, 3, 3), + PIN_FIELD_BASE(125, IOCFG_TR_BASE, 0x0010, 3, 3), + PIN_FIELD_BASE(126, IOCFG_TR_BASE, 0x0000, 6, 3), + PIN_FIELD_BASE(127, IOCFG_TR_BASE, 0x0000, 9, 3), + PIN_FIELD_BASE(128, IOCFG_TR_BASE, 0x0000, 12, 3), + PIN_FIELD_BASE(129, IOCFG_TR_BASE, 0x0000, 15, 3), + PIN_FIELD_BASE(130, IOCFG_TR_BASE, 0x0000, 18, 3), + PIN_FIELD_BASE(131, IOCFG_TR_BASE, 0x0000, 21, 3), + PIN_FIELD_BASE(132, IOCFG_TR_BASE, 0x0000, 24, 3), + PIN_FIELD_BASE(133, IOCFG_TR_BASE, 0x0000, 27, 3), + PIN_FIELD_BASE(134, IOCFG_BM_BASE, 0x0030, 15, 3), + PIN_FIELD_BASE(135, IOCFG_BM_BASE, 0x0030, 18, 3), + PIN_FIELD_BASE(136, IOCFG_BM_BASE, 0x0030, 21, 3), + PIN_FIELD_BASE(137, IOCFG_BM_BASE, 0x0030, 24, 3), + PIN_FIELD_BASE(138, IOCFG_BM_BASE, 0x0030, 27, 3), + PIN_FIELD_BASE(139, IOCFG_BM_BASE, 0x0040, 0, 3), + PIN_FIELD_BASE(140, IOCFG_RM_BASE, 0x0010, 9, 3), + PIN_FIELD_BASE(141, IOCFG_RM_BASE, 0x0010, 12, 3), + PIN_FIELD_BASE(142, IOCFG_RM_BASE, 0x0010, 15, 3), + PIN_FIELD_BASE(143, IOCFG_RM_BASE, 0x0010, 18, 3), + PIN_FIELD_BASE(144, IOCFG_RM_BASE, 0x0010, 21, 3), + PIN_FIELD_BASE(145, IOCFG_RM_BASE, 0x0010, 24, 3), + PIN_FIELD_BASE(146, IOCFG_LB_BASE, 0x0000, 9, 3), + PIN_FIELD_BASE(147, IOCFG_LB_BASE, 0x0000, 12, 3), + PIN_FIELD_BASE(148, IOCFG_LB_BASE, 0x0000, 0, 3), + PIN_FIELD_BASE(149, IOCFG_LB_BASE, 0x0000, 3, 3), + PIN_FIELD_BASE(150, IOCFG_LB_BASE, 0x0000, 6, 3), + PIN_FIELD_BASE(151, IOCFG_LB_BASE, 0x0000, 15, 3), + PIN_FIELD_BASE(152, IOCFG_LB_BASE, 0x0000, 18, 3), + PIN_FIELD_BASE(153, IOCFG_LB_BASE, 0x0000, 21, 3), + PIN_FIELD_BASE(154, IOCFG_LB_BASE, 0x0000, 24, 3), + PIN_FIELD_BASE(155, IOCFG_LT_BASE, 0x0000, 3, 3), + PIN_FIELD_BASE(156, IOCFG_LT_BASE, 0x0000, 21, 3), + PIN_FIELD_BASE(157, IOCFG_LT_BASE, 0x0000, 12, 3), + PIN_FIELD_BASE(158, IOCFG_LT_BASE, 0x0000, 15, 3), + PIN_FIELD_BASE(159, IOCFG_LT_BASE, 0x0000, 0, 3), + PIN_FIELD_BASE(160, IOCFG_LT_BASE, 0x0000, 18, 3), + PIN_FIELD_BASE(161, IOCFG_LT_BASE, 0x0000, 6, 3), + PIN_FIELD_BASE(162, IOCFG_LT_BASE, 0x0000, 9, 3), + PIN_FIELD_BASE(163, IOCFG_TL_BASE, 0x0000, 3, 3), + PIN_FIELD_BASE(164, IOCFG_TL_BASE, 0x0000, 3, 3), + PIN_FIELD_BASE(165, IOCFG_TL_BASE, 0x0000, 3, 3), + PIN_FIELD_BASE(166, IOCFG_TL_BASE, 0x0000, 3, 3), + PIN_FIELD_BASE(167, IOCFG_TL_BASE, 0x0000, 6, 3), + PIN_FIELD_BASE(168, IOCFG_TL_BASE, 0x0000, 6, 3), + PIN_FIELD_BASE(169, IOCFG_LT_BASE, 0x0010, 9, 3), + PIN_FIELD_BASE(170, IOCFG_LT_BASE, 0x0000, 24, 3), + PIN_FIELD_BASE(171, IOCFG_TL_BASE, 0x0000, 0, 3), +}; + +static const struct mtk_pin_field_calc mt8366_pin_pupd_range[] = { + PIN_FIELD_BASE(79, IOCFG_RM_BASE, 0x0090, 0, 1), + PIN_FIELD_BASE(80, IOCFG_RM_BASE, 0x0090, 1, 1), + PIN_FIELD_BASE(81, IOCFG_RM_BASE, 0x0090, 2, 1), + PIN_FIELD_BASE(82, IOCFG_RM_BASE, 0x0090, 3, 1), + PIN_FIELD_BASE(122, IOCFG_TR_BASE, 0x0030, 10, 1), + PIN_FIELD_BASE(123, IOCFG_TR_BASE, 0x0030, 0, 1), + PIN_FIELD_BASE(124, IOCFG_TR_BASE, 0x0030, 1, 1), + PIN_FIELD_BASE(125, IOCFG_TR_BASE, 0x0030, 11, 1), + PIN_FIELD_BASE(126, IOCFG_TR_BASE, 0x0030, 2, 1), + PIN_FIELD_BASE(127, IOCFG_TR_BASE, 0x0030, 3, 1), + PIN_FIELD_BASE(128, IOCFG_TR_BASE, 0x0030, 4, 1), + PIN_FIELD_BASE(129, IOCFG_TR_BASE, 0x0030, 5, 1), + PIN_FIELD_BASE(130, IOCFG_TR_BASE, 0x0030, 6, 1), + PIN_FIELD_BASE(131, IOCFG_TR_BASE, 0x0030, 7, 1), + PIN_FIELD_BASE(132, IOCFG_TR_BASE, 0x0030, 8, 1), + PIN_FIELD_BASE(133, IOCFG_TR_BASE, 0x0030, 9, 1), + PIN_FIELD_BASE(134, IOCFG_BM_BASE, 0x0090, 0, 1), + PIN_FIELD_BASE(135, IOCFG_BM_BASE, 0x0090, 1, 1), + PIN_FIELD_BASE(136, IOCFG_BM_BASE, 0x0090, 2, 1), + PIN_FIELD_BASE(137, IOCFG_BM_BASE, 0x0090, 3, 1), + PIN_FIELD_BASE(138, IOCFG_BM_BASE, 0x0090, 4, 1), + PIN_FIELD_BASE(139, IOCFG_BM_BASE, 0x0090, 5, 1), + PIN_FIELD_BASE(140, IOCFG_RM_BASE, 0x0090, 4, 1), + PIN_FIELD_BASE(141, IOCFG_RM_BASE, 0x0090, 5, 1), + PIN_FIELD_BASE(142, IOCFG_RM_BASE, 0x0090, 6, 1), + PIN_FIELD_BASE(143, IOCFG_RM_BASE, 0x0090, 7, 1), + PIN_FIELD_BASE(144, IOCFG_RM_BASE, 0x0090, 8, 1), + PIN_FIELD_BASE(145, IOCFG_RM_BASE, 0x0090, 9, 1), +}; + +static const struct mtk_pin_field_calc mt8366_pin_r0_range[] = { + PIN_FIELD_BASE(79, IOCFG_RM_BASE, 0x00b0, 0, 1), + PIN_FIELD_BASE(80, IOCFG_RM_BASE, 0x00b0, 1, 1), + PIN_FIELD_BASE(81, IOCFG_RM_BASE, 0x00b0, 2, 1), + PIN_FIELD_BASE(82, IOCFG_RM_BASE, 0x00b0, 3, 1), + PIN_FIELD_BASE(122, IOCFG_TR_BASE, 0x0040, 10, 1), + PIN_FIELD_BASE(123, IOCFG_TR_BASE, 0x0040, 0, 1), + PIN_FIELD_BASE(124, IOCFG_TR_BASE, 0x0040, 1, 1), + PIN_FIELD_BASE(125, IOCFG_TR_BASE, 0x0040, 11, 1), + PIN_FIELD_BASE(126, IOCFG_TR_BASE, 0x0040, 2, 1), + PIN_FIELD_BASE(127, IOCFG_TR_BASE, 0x0040, 3, 1), + PIN_FIELD_BASE(128, IOCFG_TR_BASE, 0x0040, 4, 1), + PIN_FIELD_BASE(129, IOCFG_TR_BASE, 0x0040, 5, 1), + PIN_FIELD_BASE(130, IOCFG_TR_BASE, 0x0040, 6, 1), + PIN_FIELD_BASE(131, IOCFG_TR_BASE, 0x0040, 7, 1), + PIN_FIELD_BASE(132, IOCFG_TR_BASE, 0x0040, 8, 1), + PIN_FIELD_BASE(133, IOCFG_TR_BASE, 0x0040, 9, 1), + PIN_FIELD_BASE(134, IOCFG_BM_BASE, 0x00c0, 0, 1), + PIN_FIELD_BASE(135, IOCFG_BM_BASE, 0x00c0, 1, 1), + PIN_FIELD_BASE(136, IOCFG_BM_BASE, 0x00c0, 2, 1), + PIN_FIELD_BASE(137, IOCFG_BM_BASE, 0x00c0, 3, 1), + PIN_FIELD_BASE(138, IOCFG_BM_BASE, 0x00c0, 4, 1), + PIN_FIELD_BASE(139, IOCFG_BM_BASE, 0x00c0, 5, 1), + PIN_FIELD_BASE(140, IOCFG_RM_BASE, 0x00b0, 4, 1), + PIN_FIELD_BASE(141, IOCFG_RM_BASE, 0x00b0, 5, 1), + PIN_FIELD_BASE(142, IOCFG_RM_BASE, 0x00b0, 6, 1), + PIN_FIELD_BASE(143, IOCFG_RM_BASE, 0x00b0, 7, 1), + PIN_FIELD_BASE(144, IOCFG_RM_BASE, 0x00b0, 8, 1), + PIN_FIELD_BASE(145, IOCFG_RM_BASE, 0x00b0, 9, 1), +}; + +static const struct mtk_pin_field_calc mt8366_pin_r1_range[] = { + PIN_FIELD_BASE(79, IOCFG_RM_BASE, 0x00c0, 0, 1), + PIN_FIELD_BASE(80, IOCFG_RM_BASE, 0x00c0, 1, 1), + PIN_FIELD_BASE(81, IOCFG_RM_BASE, 0x00c0, 2, 1), + PIN_FIELD_BASE(82, IOCFG_RM_BASE, 0x00c0, 3, 1), + PIN_FIELD_BASE(122, IOCFG_TR_BASE, 0x0050, 10, 1), + PIN_FIELD_BASE(123, IOCFG_TR_BASE, 0x0050, 0, 1), + PIN_FIELD_BASE(124, IOCFG_TR_BASE, 0x0050, 1, 1), + PIN_FIELD_BASE(125, IOCFG_TR_BASE, 0x0050, 11, 1), + PIN_FIELD_BASE(126, IOCFG_TR_BASE, 0x0050, 2, 1), + PIN_FIELD_BASE(127, IOCFG_TR_BASE, 0x0050, 3, 1), + PIN_FIELD_BASE(128, IOCFG_TR_BASE, 0x0050, 4, 1), + PIN_FIELD_BASE(129, IOCFG_TR_BASE, 0x0050, 5, 1), + PIN_FIELD_BASE(130, IOCFG_TR_BASE, 0x0050, 6, 1), + PIN_FIELD_BASE(131, IOCFG_TR_BASE, 0x0050, 7, 1), + PIN_FIELD_BASE(132, IOCFG_TR_BASE, 0x0050, 8, 1), + PIN_FIELD_BASE(133, IOCFG_TR_BASE, 0x0050, 9, 1), + PIN_FIELD_BASE(134, IOCFG_BM_BASE, 0x00d0, 0, 1), + PIN_FIELD_BASE(135, IOCFG_BM_BASE, 0x00d0, 1, 1), + PIN_FIELD_BASE(136, IOCFG_BM_BASE, 0x00d0, 2, 1), + PIN_FIELD_BASE(137, IOCFG_BM_BASE, 0x00d0, 3, 1), + PIN_FIELD_BASE(138, IOCFG_BM_BASE, 0x00d0, 4, 1), + PIN_FIELD_BASE(139, IOCFG_BM_BASE, 0x00d0, 5, 1), + PIN_FIELD_BASE(140, IOCFG_RM_BASE, 0x00c0, 4, 1), + PIN_FIELD_BASE(141, IOCFG_RM_BASE, 0x00c0, 5, 1), + PIN_FIELD_BASE(142, IOCFG_RM_BASE, 0x00c0, 6, 1), + PIN_FIELD_BASE(143, IOCFG_RM_BASE, 0x00c0, 7, 1), + PIN_FIELD_BASE(144, IOCFG_RM_BASE, 0x00c0, 8, 1), + PIN_FIELD_BASE(145, IOCFG_RM_BASE, 0x00c0, 9, 1), +}; + +static const struct mtk_pin_field_calc mt8366_pin_rsel_range[] = { + PIN_FIELD_BASE(98, IOCFG_LT_BASE, 0x0080, 0, 3), + PIN_FIELD_BASE(99, IOCFG_LT_BASE, 0x0080, 6, 3), + PIN_FIELD_BASE(100, IOCFG_RM_BASE, 0x00f0, 0, 3), + PIN_FIELD_BASE(101, IOCFG_RM_BASE, 0x00f0, 9, 3), + PIN_FIELD_BASE(102, IOCFG_RM_BASE, 0x00f0, 3, 3), + PIN_FIELD_BASE(103, IOCFG_RM_BASE, 0x00f0, 12, 3), + PIN_FIELD_BASE(104, IOCFG_RM_BASE, 0x00f0, 6, 3), + PIN_FIELD_BASE(105, IOCFG_RM_BASE, 0x00f0, 15, 3), + PIN_FIELD_BASE(106, IOCFG_LT_BASE, 0x0080, 3, 3), + PIN_FIELD_BASE(107, IOCFG_LT_BASE, 0x0080, 9, 3), + PIN_FIELD_BASE(108, IOCFG_LB_BASE, 0x00f0, 0, 3), + PIN_FIELD_BASE(109, IOCFG_LB_BASE, 0x00f0, 15, 3), + PIN_FIELD_BASE(110, IOCFG_LB_BASE, 0x00f0, 3, 3), + PIN_FIELD_BASE(111, IOCFG_LB_BASE, 0x00f0, 18, 3), + PIN_FIELD_BASE(112, IOCFG_LB_BASE, 0x00f0, 6, 3), + PIN_FIELD_BASE(113, IOCFG_LB_BASE, 0x00f0, 21, 3), + PIN_FIELD_BASE(114, IOCFG_LB_BASE, 0x00f0, 9, 3), + PIN_FIELD_BASE(115, IOCFG_LB_BASE, 0x00f0, 24, 3), + PIN_FIELD_BASE(116, IOCFG_LB_BASE, 0x00f0, 27, 3), + PIN_FIELD_BASE(117, IOCFG_LB_BASE, 0x00f0, 12, 3), +}; + +static const struct mtk_pin_reg_calc mt8366_reg_cals[] = { + [PINCTRL_PIN_REG_MODE] = MTK_RANGE(mt8366_pin_mode_range), + [PINCTRL_PIN_REG_DIR] = MTK_RANGE(mt8366_pin_dir_range), + [PINCTRL_PIN_REG_DI] = MTK_RANGE(mt8366_pin_di_range), + [PINCTRL_PIN_REG_DO] = MTK_RANGE(mt8366_pin_do_range), + [PINCTRL_PIN_REG_SMT] = MTK_RANGE(mt8366_pin_smt_range), + [PINCTRL_PIN_REG_IES] = MTK_RANGE(mt8366_pin_ies_range), + [PINCTRL_PIN_REG_PU] = MTK_RANGE(mt8366_pin_pu_range), + [PINCTRL_PIN_REG_PD] = MTK_RANGE(mt8366_pin_pd_range), + [PINCTRL_PIN_REG_DRV] = MTK_RANGE(mt8366_pin_drv_range), + [PINCTRL_PIN_REG_PUPD] = MTK_RANGE(mt8366_pin_pupd_range), + [PINCTRL_PIN_REG_R0] = MTK_RANGE(mt8366_pin_r0_range), + [PINCTRL_PIN_REG_R1] = MTK_RANGE(mt8366_pin_r1_range), + [PINCTRL_PIN_REG_RSEL] = MTK_RANGE(mt8366_pin_rsel_range), +}; + +#define MT8366_PIN(_number, _name) \ + MTK_TYPED_PIN(_number, _name, DRV_GRP4, IO_TYPE_GRP0) + +#define MT8366_R1R0_PIN(_number, _name) \ + MTK_TYPED_PIN(_number, _name, DRV_GRP4, IO_TYPE_GRP1) + +#define MT8366_RSEL_PIN(_number, _name) \ + MTK_TYPED_PIN(_number, _name, DRV_GRP4, IO_TYPE_GRP2) + +static const struct mtk_pin_desc mt8366_pins[] = { + MT8366_PIN(0, "GPIO0"), + MT8366_PIN(1, "GPIO1"), + MT8366_PIN(2, "GPIO2"), + MT8366_PIN(3, "GPIO3"), + MT8366_PIN(4, "GPIO4"), + MT8366_PIN(5, "GPIO5"), + MT8366_PIN(6, "GPIO6"), + MT8366_PIN(7, "GPIO7"), + MT8366_PIN(8, "GPIO8"), + MT8366_PIN(9, "GPIO9"), + MT8366_PIN(10, "GPIO10"), + MT8366_PIN(11, "GPIO11"), + MT8366_PIN(12, "GPIO12"), + MT8366_PIN(13, "GPIO13"), + MT8366_PIN(14, "GPIO14"), + MT8366_PIN(15, "GPIO15"), + MT8366_PIN(16, "GPIO16"), + MT8366_PIN(17, "GPIO17"), + MT8366_PIN(18, "GPIO18"), + MT8366_PIN(19, "GPIO19"), + MT8366_PIN(20, "GPIO20"), + MT8366_PIN(21, "GPIO21"), + MT8366_PIN(22, "GPIO22"), + MT8366_PIN(23, "GPIO23"), + MT8366_PIN(24, "GPIO24"), + MT8366_PIN(25, "GPIO25"), + MT8366_PIN(26, "GPIO26"), + MT8366_PIN(27, "GPIO27"), + MT8366_PIN(28, "GPIO28"), + MT8366_PIN(29, "GPIO29"), + MT8366_PIN(30, "GPIO30"), + MT8366_PIN(31, "GPIO31"), + MT8366_PIN(32, "GPIO32"), + MT8366_PIN(33, "GPIO33"), + MT8366_PIN(34, "GPIO34"), + MT8366_PIN(35, "GPIO35"), + MT8366_PIN(36, "GPIO36"), + MT8366_PIN(37, "GPIO37"), + MT8366_PIN(38, "GPIO38"), + MT8366_PIN(39, "GPIO39"), + MT8366_PIN(40, "GPIO40"), + MT8366_PIN(41, "GPIO41"), + MT8366_PIN(42, "GPIO42"), + MT8366_PIN(43, "GPIO43"), + MT8366_PIN(44, "GPIO44"), + MT8366_PIN(45, "GPIO45"), + MT8366_PIN(46, "GPIO46"), + MT8366_PIN(47, "GPIO47"), + MT8366_PIN(48, "GPIO48"), + MT8366_PIN(49, "GPIO49"), + MT8366_PIN(50, "GPIO50"), + MT8366_PIN(51, "GPIO51"), + MT8366_PIN(52, "GPIO52"), + MT8366_PIN(53, "GPIO53"), + MT8366_PIN(54, "GPIO54"), + MT8366_PIN(55, "GPIO55"), + MT8366_PIN(56, "GPIO56"), + MT8366_PIN(57, "GPIO57"), + MT8366_PIN(58, "GPIO58"), + MT8366_PIN(59, "GPIO59"), + MT8366_PIN(60, "GPIO60"), + MT8366_PIN(61, "GPIO61"), + MT8366_PIN(62, "GPIO62"), + MT8366_PIN(63, "GPIO63"), + MT8366_PIN(64, "GPIO64"), + MT8366_PIN(65, "GPIO65"), + MT8366_PIN(66, "GPIO66"), + MT8366_PIN(67, "GPIO67"), + MT8366_PIN(68, "GPIO68"), + MT8366_PIN(69, "GPIO69"), + MT8366_PIN(70, "GPIO70"), + MT8366_PIN(71, "GPIO71"), + MT8366_PIN(72, "GPIO72"), + MT8366_PIN(73, "GPIO73"), + MT8366_PIN(74, "GPIO74"), + MT8366_PIN(75, "GPIO75"), + MT8366_PIN(76, "GPIO76"), + MT8366_PIN(77, "GPIO77"), + MT8366_PIN(78, "GPIO78"), + MT8366_R1R0_PIN(79, "GPIO79"), + MT8366_R1R0_PIN(80, "GPIO80"), + MT8366_R1R0_PIN(81, "GPIO81"), + MT8366_R1R0_PIN(82, "GPIO82"), + MT8366_PIN(83, "GPIO83"), + MT8366_PIN(84, "GPIO84"), + MT8366_PIN(85, "GPIO85"), + MT8366_PIN(86, "GPIO86"), + MT8366_PIN(87, "GPIO87"), + MT8366_PIN(88, "GPIO88"), + MT8366_PIN(89, "GPIO89"), + MT8366_PIN(90, "GPIO90"), + MT8366_PIN(91, "GPIO91"), + MT8366_PIN(92, "GPIO92"), + MT8366_PIN(93, "GPIO93"), + MT8366_PIN(94, "GPIO94"), + MT8366_PIN(95, "GPIO95"), + MT8366_PIN(96, "GPIO96"), + MT8366_PIN(97, "GPIO97"), + MT8366_RSEL_PIN(98, "GPIO98"), + MT8366_RSEL_PIN(99, "GPIO99"), + MT8366_RSEL_PIN(100, "GPIO100"), + MT8366_RSEL_PIN(101, "GPIO101"), + MT8366_RSEL_PIN(102, "GPIO102"), + MT8366_RSEL_PIN(103, "GPIO103"), + MT8366_RSEL_PIN(104, "GPIO104"), + MT8366_RSEL_PIN(105, "GPIO105"), + MT8366_RSEL_PIN(106, "GPIO106"), + MT8366_RSEL_PIN(107, "GPIO107"), + MT8366_RSEL_PIN(108, "GPIO108"), + MT8366_RSEL_PIN(109, "GPIO109"), + MT8366_RSEL_PIN(110, "GPIO110"), + MT8366_RSEL_PIN(111, "GPIO111"), + MT8366_RSEL_PIN(112, "GPIO112"), + MT8366_RSEL_PIN(113, "GPIO113"), + MT8366_RSEL_PIN(114, "GPIO114"), + MT8366_RSEL_PIN(115, "GPIO115"), + MT8366_RSEL_PIN(116, "GPIO116"), + MT8366_RSEL_PIN(117, "GPIO117"), + MT8366_PIN(118, "GPIO118"), + MT8366_PIN(119, "GPIO119"), + MT8366_PIN(120, "GPIO120"), + MT8366_PIN(121, "GPIO121"), + MT8366_R1R0_PIN(122, "GPIO122"), + MT8366_R1R0_PIN(123, "GPIO123"), + MT8366_R1R0_PIN(124, "GPIO124"), + MT8366_R1R0_PIN(125, "GPIO125"), + MT8366_R1R0_PIN(126, "GPIO126"), + MT8366_R1R0_PIN(127, "GPIO127"), + MT8366_R1R0_PIN(128, "GPIO128"), + MT8366_R1R0_PIN(129, "GPIO129"), + MT8366_R1R0_PIN(130, "GPIO130"), + MT8366_R1R0_PIN(131, "GPIO131"), + MT8366_R1R0_PIN(132, "GPIO132"), + MT8366_R1R0_PIN(133, "GPIO133"), + MT8366_R1R0_PIN(134, "GPIO134"), + MT8366_R1R0_PIN(135, "GPIO135"), + MT8366_R1R0_PIN(136, "GPIO136"), + MT8366_R1R0_PIN(137, "GPIO137"), + MT8366_R1R0_PIN(138, "GPIO138"), + MT8366_R1R0_PIN(139, "GPIO139"), + MT8366_R1R0_PIN(140, "GPIO140"), + MT8366_R1R0_PIN(141, "GPIO141"), + MT8366_R1R0_PIN(142, "GPIO142"), + MT8366_R1R0_PIN(143, "GPIO143"), + MT8366_R1R0_PIN(144, "GPIO144"), + MT8366_R1R0_PIN(145, "GPIO145"), + MT8366_PIN(146, "GPIO146"), + MT8366_PIN(147, "GPIO147"), + MT8366_PIN(148, "GPIO148"), + MT8366_PIN(149, "GPIO149"), + MT8366_PIN(150, "GPIO150"), + MT8366_PIN(151, "GPIO151"), + MT8366_PIN(152, "GPIO152"), + MT8366_PIN(153, "GPIO153"), + MT8366_PIN(154, "GPIO154"), + MT8366_PIN(155, "GPIO155"), + MT8366_PIN(156, "GPIO156"), + MT8366_PIN(157, "GPIO157"), + MT8366_PIN(158, "GPIO158"), + MT8366_PIN(159, "GPIO159"), + MT8366_PIN(160, "GPIO160"), + MT8366_PIN(161, "GPIO161"), + MT8366_PIN(162, "GPIO162"), + MT8366_PIN(163, "GPIO163"), + MT8366_PIN(164, "GPIO164"), + MT8366_PIN(165, "GPIO165"), + MT8366_PIN(166, "GPIO166"), + MT8366_PIN(167, "GPIO167"), + MT8366_PIN(168, "GPIO168"), + MT8366_PIN(169, "GPIO169"), + MT8366_PIN(170, "GPIO170"), + MT8366_PIN(171, "GPIO171"), +}; + +static const struct mtk_io_type_desc mt8366_io_type_desc[] = { + [IO_TYPE_GRP0] = { + .name = "mt8366_pupd", + .bias_set = mtk_pinconf_bias_set_pu_pd, + .drive_set = mtk_pinconf_drive_set_v1, + .input_enable = mtk_pinconf_input_enable_v1, + .get_pinconf = mtk_pinconf_get_pu_pd, + }, + [IO_TYPE_GRP1] = { + .name = "mt8366_pupd_r1r0", + .bias_set = mtk_pinconf_bias_set_pupd_r1_r0, + .drive_set = mtk_pinconf_drive_set_v1, + .input_enable = mtk_pinconf_input_enable_v1, + .get_pinconf = mtk_pinconf_get_pupd_r1_r0, + }, + [IO_TYPE_GRP2] = { + .name = "mt8366_pupd_rsel", + .bias_set = mtk_pinconf_bias_set_pu_pd_rsel, + .drive_set = mtk_pinconf_drive_set_v1, + .input_enable = mtk_pinconf_input_enable_v1, + .get_pinconf = mtk_pinconf_get_pu_pd_rsel, + }, +}; + +static const struct mtk_pinctrl_soc mt8366_data = { + .name = "mt8366_pinctrl", + .reg_cal = mt8366_reg_cals, + .pins = mt8366_pins, + .npins = ARRAY_SIZE(mt8366_pins), + .io_type = mt8366_io_type_desc, + .ntype = ARRAY_SIZE(mt8366_io_type_desc), + .gpio_mode = 0, + .base_names = mt8366_pinctrl_register_base_names, + .nbase_names = ARRAY_SIZE(mt8366_pinctrl_register_base_names), + .base_calc = 1, +}; + +static int mtk_pinctrl_mt8366_probe(struct udevice *dev) +{ + return mtk_pinctrl_common_probe(dev, &mt8366_data); +} + +static const struct udevice_id mt8366_pctrl_match[] = { + { .compatible = "mediatek,mt8366-pinctrl" }, + { } +}; + +U_BOOT_DRIVER(mt8366_pinctrl) = { + .name = "mt8366_pinctrl", + .id = UCLASS_PINCTRL, + .of_match = mt8366_pctrl_match, + .ops = &mtk_pinctrl_ops, + .bind = mtk_pinctrl_common_bind, + .probe = mtk_pinctrl_mt8366_probe, + .priv_auto = sizeof(struct mtk_pinctrl_priv), +}; -- cgit v1.3.1 From 50c148cfcaa30a584a827a5b54a2864c5dc8a998 Mon Sep 17 00:00:00 2001 From: Suhrid Subramaniam Date: Fri, 7 Aug 2026 13:59:39 -0500 Subject: serial: mtk: use ulong for clk_rate Use ulong for return value of clk_get_rate() in the MediaTek serial driver. IS_ERR_VALUE() does a signed 64-bit comparison against the range of possible error codes. If clk_get_rate() returns an error, assigning this to a u32 truncates the top 32 bits making the value smaller, defeating IS_ERR_VALUE() and producing a garbage divisor that hangs the UART. Fixes: 3b17f2e2c2a9 ("serial: mtk: add support for using dynamic baud clock souce") Signed-off-by: Suhrid Subramaniam Reviewed-by: Julien Stephan Link: https://patch.msgid.link/20260807-serial-mtk-clock-fixes-v3-1-8cc94d313b57@baylibre.com Signed-off-by: David Lechner --- drivers/serial/serial_mtk.c | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/drivers/serial/serial_mtk.c b/drivers/serial/serial_mtk.c index 01cc415efdd..28e87f485a2 100644 --- a/drivers/serial/serial_mtk.c +++ b/drivers/serial/serial_mtk.c @@ -213,7 +213,7 @@ static int _mtk_serial_pending(struct mtk_serial_priv *priv, bool input) static int mtk_serial_setbrg(struct udevice *dev, int baudrate) { struct mtk_serial_priv *priv = dev_get_priv(dev); - u32 clk_rate; + ulong clk_rate; clk_rate = clk_get_rate(&priv->clk); if (IS_ERR_VALUE(clk_rate) || clk_rate == 0) @@ -266,6 +266,7 @@ static int mtk_serial_of_to_plat(struct udevice *dev) { struct mtk_serial_priv *priv = dev_get_priv(dev); fdt_addr_t addr; + ulong clk_rate; int err; addr = dev_read_addr(dev); @@ -282,8 +283,8 @@ static int mtk_serial_of_to_plat(struct udevice *dev) return -EINVAL; } } else { - err = clk_get_rate(&priv->clk); - if (IS_ERR_VALUE(err)) { + clk_rate = clk_get_rate(&priv->clk); + if (IS_ERR_VALUE(clk_rate)) { dev_err(dev, "invalid baud clock\n"); return -EINVAL; } -- cgit v1.3.1 From a2ffe8d63a2b7f2326a5235cddc2ded2ec43953c Mon Sep 17 00:00:00 2001 From: Suhrid Subramaniam Date: Fri, 7 Aug 2026 13:59:40 -0500 Subject: serial: mtk: guard clk_get_rate() with clk_valid() Check that priv->clk has been populated before trying to use it in the MediaTek serial driver. The clock is optional and may not be populated in all cases (in which case it is expected that there was a fixed clock rate provided.) Note this changes behavior slightly: previously, a populated clock whose clk_get_rate() failed silently fell back to priv->fixed_clk_rate (which is only set from DT when clk_get_by_index() failed, so it would have been 0 here). Now an error is returned instead. Fixes: 3b17f2e2c2a9 ("serial: mtk: add support for using dynamic baud clock souce") Signed-off-by: Suhrid Subramaniam Link: https://patch.msgid.link/20260807-serial-mtk-clock-fixes-v3-2-8cc94d313b57@baylibre.com Signed-off-by: David Lechner --- drivers/serial/serial_mtk.c | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) diff --git a/drivers/serial/serial_mtk.c b/drivers/serial/serial_mtk.c index 28e87f485a2..697f5faec1b 100644 --- a/drivers/serial/serial_mtk.c +++ b/drivers/serial/serial_mtk.c @@ -215,9 +215,13 @@ static int mtk_serial_setbrg(struct udevice *dev, int baudrate) struct mtk_serial_priv *priv = dev_get_priv(dev); ulong clk_rate; - clk_rate = clk_get_rate(&priv->clk); - if (IS_ERR_VALUE(clk_rate) || clk_rate == 0) + if (clk_valid(&priv->clk)) { + clk_rate = clk_get_rate(&priv->clk); + if (IS_ERR_VALUE(clk_rate) || clk_rate == 0) + return -EINVAL; + } else { clk_rate = priv->fixed_clk_rate; + } _mtk_serial_setbrg(priv, baudrate, clk_rate); -- cgit v1.3.1 From 8a5ddf6cd349ef86eb8f3c44381cdccb8a848c66 Mon Sep 17 00:00:00 2001 From: David Lechner Date: Fri, 7 Aug 2026 13:59:41 -0500 Subject: serial: mtk: return error value from clk_get_rate() Pass the return value from clk_get_rate() instead of changing it to -EINVAL. These return values are either ignored or logged, so it should make debugging easier in the cases where it is logged. Reviewed-by: Julien Stephan Link: https://patch.msgid.link/20260807-serial-mtk-clock-fixes-v3-3-8cc94d313b57@baylibre.com Signed-off-by: David Lechner --- drivers/serial/serial_mtk.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/serial/serial_mtk.c b/drivers/serial/serial_mtk.c index 697f5faec1b..d6a7cf488b9 100644 --- a/drivers/serial/serial_mtk.c +++ b/drivers/serial/serial_mtk.c @@ -218,7 +218,7 @@ static int mtk_serial_setbrg(struct udevice *dev, int baudrate) if (clk_valid(&priv->clk)) { clk_rate = clk_get_rate(&priv->clk); if (IS_ERR_VALUE(clk_rate) || clk_rate == 0) - return -EINVAL; + return (int)clk_rate ?: -EINVAL; } else { clk_rate = priv->fixed_clk_rate; } @@ -290,7 +290,7 @@ static int mtk_serial_of_to_plat(struct udevice *dev) clk_rate = clk_get_rate(&priv->clk); if (IS_ERR_VALUE(clk_rate)) { dev_err(dev, "invalid baud clock\n"); - return -EINVAL; + return clk_rate; } } -- cgit v1.3.1 From 01834e2273b9a1226105c7566415a6b0ba8c6955 Mon Sep 17 00:00:00 2001 From: David Lechner Date: Fri, 7 Aug 2026 13:59:42 -0500 Subject: serial: mtk: drop check before clk_bus enable Drop the redundant check that clk_bus.dev is valid before enabling it. clk_enable() already calls clk_valid() which does the same check. Link: https://patch.msgid.link/20260807-serial-mtk-clock-fixes-v3-4-8cc94d313b57@baylibre.com Signed-off-by: David Lechner --- drivers/serial/serial_mtk.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/drivers/serial/serial_mtk.c b/drivers/serial/serial_mtk.c index d6a7cf488b9..16e4fc0813f 100644 --- a/drivers/serial/serial_mtk.c +++ b/drivers/serial/serial_mtk.c @@ -260,8 +260,7 @@ static int mtk_serial_probe(struct udevice *dev) writel(UART_FCRVAL, &priv->regs->fcr); clk_enable(&priv->clk); - if (priv->clk_bus.dev) - clk_enable(&priv->clk_bus); + clk_enable(&priv->clk_bus); return 0; } -- cgit v1.3.1