From 2b634a80b5ce92232f309fdd7d7864098ca7fb95 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Thu, 18 Sep 2025 18:36:00 +0200 Subject: pci: pcie-rcar-gen4: Shut down controller on link down and remove In case the link is down, or the controller driver is removed before booting the next stage, shut down the PCIe link, put both the remote PCIe device and the controller into reset, and disable clock. This way, the hardware is not left active when not in use. Signed-off-by: Marek Vasut --- drivers/pci/pci-rcar-gen4.c | 26 ++++++++++++++++++++++++++ 1 file changed, 26 insertions(+) diff --git a/drivers/pci/pci-rcar-gen4.c b/drivers/pci/pci-rcar-gen4.c index 1f41ce28b0b..e165271f58c 100644 --- a/drivers/pci/pci-rcar-gen4.c +++ b/drivers/pci/pci-rcar-gen4.c @@ -477,6 +477,10 @@ static int rcar_gen4_pcie_probe(struct udevice *dev) if (!rcar_gen4_pcie_link_up(rcar)) { printf("PCIE-%d: Link down\n", dev_seq(dev)); + rcar_gen4_pcie_ltssm_control(rcar, false); + dm_gpio_set_value(&rcar->pe_rst, 1); + reset_assert(&rcar->pwr_rst); + clk_disable_unprepare(rcar->ref_clk); return -ENODEV; } @@ -493,6 +497,26 @@ static int rcar_gen4_pcie_probe(struct udevice *dev) return 0; } +/** + * rcar_gen4_pcie_remove() - Stop the PCIe bus active link + * @dev: A pointer to the device being operated on + * + * Stop an active link on the PCIe bus and deconfigure the controller. + * + * Return: 0 on success, else -ENODEV + */ +static int rcar_gen4_pcie_remove(struct udevice *dev) +{ + struct rcar_gen4_pcie *rcar = dev_get_priv(dev); + + rcar_gen4_pcie_ltssm_control(rcar, false); + dm_gpio_set_value(&rcar->pe_rst, 1); + reset_assert(&rcar->pwr_rst); + clk_disable_unprepare(rcar->ref_clk); + + return 0; +} + /** * rcar_gen4_pcie_of_to_plat() - Translate from DT to device state * @@ -566,5 +590,7 @@ U_BOOT_DRIVER(rcar_gen4_pcie) = { .ops = &rcar_gen4_pcie_ops, .of_to_plat = rcar_gen4_pcie_of_to_plat, .probe = rcar_gen4_pcie_probe, + .remove = rcar_gen4_pcie_remove, .priv_auto = sizeof(struct rcar_gen4_pcie), + .flags = DM_FLAG_ACTIVE_DMA, }; -- cgit v1.3.1 From a1a898588c803da43d625e5ca25cb4c78f80c7f3 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Thu, 18 Sep 2025 18:36:01 +0200 Subject: arm64: renesas: r8a779g3: Reset PCIe before next stage on Retronix R-Car V4H Sparrow Hawk Fully reset both PCIe controllers before booting the next stage on Retronix R-Car V4H Sparrow Hawk board. This is necessary especially in case U-Boot brought up the PCIe controllers, at which point the next stage might be confused by the state of the PCIe controller. The reset has to happen this late and not in the PCIe controller driver, because the SRCR11 bits seem to affect both controllers. Signed-off-by: Marek Vasut --- board/renesas/sparrowhawk/sparrowhawk.c | 27 +++++++++++++++++++++++++++ 1 file changed, 27 insertions(+) diff --git a/board/renesas/sparrowhawk/sparrowhawk.c b/board/renesas/sparrowhawk/sparrowhawk.c index 58de7f25cbd..a4eda852743 100644 --- a/board/renesas/sparrowhawk/sparrowhawk.c +++ b/board/renesas/sparrowhawk/sparrowhawk.c @@ -267,3 +267,30 @@ void renesas_dram_init_banksize(void) gd->bd->bi_dram[bank].size = 0x200000000ULL; } } + +#define SRCR6 0xe6152c18 +#define SRCR11 0xe6152c2c +#define SRSTCLR6 0xe6152c98 +#define SRSTCLR11 0xe6152cac +#define SRCR_PCIEC0_PWR_RESET BIT(24) +#define SRCR_PCIEC1_PWR_RESET BIT(25) +#define SRCR_PCIEC0_APP_RESET BIT(21) +#define SRCR_PCIEC1_APP_RESET BIT(22) + +void board_cleanup_before_linux(void) +{ + if (!IS_ENABLED(CONFIG_PCI_RCAR_GEN4)) + return; + + /* Set cold and application reset for both PCIe cores */ + writel(SRCR_PCIEC0_PWR_RESET | SRCR_PCIEC1_PWR_RESET, SRCR6); + readl(SRCR6); + writel(SRCR_PCIEC0_APP_RESET | SRCR_PCIEC1_APP_RESET, SRCR11); + readl(SRCR11); + + /* Clear cold and application reset for both PCIe cores */ + writel(SRCR_PCIEC0_PWR_RESET | SRCR_PCIEC1_PWR_RESET, SRSTCLR6); + readl(SRSTCLR6); + writel(SRCR_PCIEC0_APP_RESET | SRCR_PCIEC1_APP_RESET, SRSTCLR11); + readl(SRSTCLR11); +} -- cgit v1.3.1 From 92b779cd9f1493dad467b08e94c916b66270c47c Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Sun, 7 Sep 2025 21:16:27 +0200 Subject: serial: sh: Handle HSCIF RX FIFO overflow The HSCIF RX FIFO may overflow when data are streaming from remote end into the HSCIF while U-Boot is still starting up. In that case, HSFSR bit RDF is set, but HSFDR field R is zero. This confuses .tstc callback into considering RX FIFO to be empty, which leads to .getc to be never invoked, even when user attempts to pass more input onto the command line. Fix this by considering the RDF flag in serial_rx_fifo_level(), which is called from .tstc in case of no errors. If RDF flag is set, trigger the .getc callback and let it clear the RX FIFO. Signed-off-by: Marek Vasut --- drivers/serial/serial_sh.c | 11 ++++++++++- 1 file changed, 10 insertions(+), 1 deletion(-) diff --git a/drivers/serial/serial_sh.c b/drivers/serial/serial_sh.c index e4cc4ee4260..7ab62e0e90b 100644 --- a/drivers/serial/serial_sh.c +++ b/drivers/serial/serial_sh.c @@ -112,7 +112,16 @@ static int serial_raw_putc(struct uart_port *port, const char c) static int serial_rx_fifo_level(struct uart_port *port) { - return scif_rxfill(port); + int ret; + + ret = scif_rxfill(port); + if (ret) + return ret; + + if (sci_in(port, SCxSR) & SCxSR_RDxF(port)) + return 1; + + return 0; } static int sh_serial_tstc_generic(struct uart_port *port) -- cgit v1.3.1 From 1d94364c7f172644d7f1cb0f6cc7ffbdb920ff64 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Sat, 18 Oct 2025 00:04:07 +0200 Subject: ARM: dts: renesas: Disable R8A779G0 V4H White Hawk RPC SPI DT node again Commit 3faeb78378ea ("ARM: dts: renesas: Minimize R8A779G0 V4H RPC SPI DT node") incorrectly re-enabled the RPC SPI DT node, which was disabled in commit 13bdb6a26910 ("ARM: dts: renesas: Disable RPC driver on R8A779G0 V4H White Hawk board") Reinstate the disablement. Fixes: 3faeb78378ea ("ARM: dts: renesas: Minimize R8A779G0 V4H RPC SPI DT node") Signed-off-by: Marek Vasut --- arch/arm/dts/r8a779g0-white-hawk-u-boot.dtsi | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm/dts/r8a779g0-white-hawk-u-boot.dtsi b/arch/arm/dts/r8a779g0-white-hawk-u-boot.dtsi index 85e32208b29..8e4307ff87d 100644 --- a/arch/arm/dts/r8a779g0-white-hawk-u-boot.dtsi +++ b/arch/arm/dts/r8a779g0-white-hawk-u-boot.dtsi @@ -23,6 +23,8 @@ &rpc { bootph-all; + status = "disabled"; + flash@0 { bootph-all; spi-tx-bus-width = <1>; -- cgit v1.3.1 From 81e050250c0b8b3c6ba5d27449cc5817456bb024 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Sat, 18 Oct 2025 00:06:33 +0200 Subject: ARM: dts: renesas: Reinstate R8A779H0 V4M U-Boot DTs Commit 63da3a795e86 ("ARM: dts: renesas: Drop R8A779H0 V4M DTs with OF_UPSTREAM counterparts") removed unnecessary V4H DTs from arch/arm/dts , but in the process also incorrectly dropped the -u-boot.dtsi U-Boot extras. Reinstate those extras. Due to DT file name change for the R8A779H0 V4M Gray Hawk, update the r8a779h0-gray-hawk-u-boot.dtsi filename to newly matching r8a779h0-gray-hawk-single-u-boot.dtsi . Align r8a779h0-u-boot.dtsi with clean up commits 1487c34efa7b ("arm64: dts: renesas: Deduplicate extalr_clk bootph-all") dd8f57ed2f0b ("ARM: dts: renesas: Drop most of bootph-* tags") Fixes: 63da3a795e86 ("ARM: dts: renesas: Drop R8A779H0 V4M DTs with OF_UPSTREAM counterparts") Signed-off-by: Marek Vasut --- arch/arm/dts/r8a779h0-gray-hawk-single-u-boot.dtsi | 41 ++++++++++++++++++++++ arch/arm/dts/r8a779h0-u-boot.dtsi | 11 ++++++ 2 files changed, 52 insertions(+) create mode 100644 arch/arm/dts/r8a779h0-gray-hawk-single-u-boot.dtsi create mode 100644 arch/arm/dts/r8a779h0-u-boot.dtsi diff --git a/arch/arm/dts/r8a779h0-gray-hawk-single-u-boot.dtsi b/arch/arm/dts/r8a779h0-gray-hawk-single-u-boot.dtsi new file mode 100644 index 00000000000..91e1ee1f890 --- /dev/null +++ b/arch/arm/dts/r8a779h0-gray-hawk-single-u-boot.dtsi @@ -0,0 +1,41 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Device Tree Source extras for U-Boot for the Gray Hawk board + * + * Copyright (C) 2025 Renesas Electronics Corp. + */ + +#include "r8a779h0-u-boot.dtsi" + +/ { + aliases { + spi0 = &rpc; + }; +}; + +&pfc { + qspi0_pins: qspi0 { + groups = "qspi0_ctrl", "qspi0_data4"; + function = "qspi0"; + }; +}; + +&rpc { + pinctrl-0 = <&qspi0_pins>; + pinctrl-names = "default"; + + #address-cells = <1>; + #size-cells = <0>; + spi-max-frequency = <40000000>; + status = "okay"; + + flash@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "s25fs512s", "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <40000000>; + spi-tx-bus-width = <1>; + spi-rx-bus-width = <1>; + }; +}; diff --git a/arch/arm/dts/r8a779h0-u-boot.dtsi b/arch/arm/dts/r8a779h0-u-boot.dtsi new file mode 100644 index 00000000000..40e070be9a8 --- /dev/null +++ b/arch/arm/dts/r8a779h0-u-boot.dtsi @@ -0,0 +1,11 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Device Tree Source extras for U-Boot on R-Car R8A779H0 SoC + * + * Copyright (C) 2025 Renesas Electronics Corp. + */ + +&rpc { + bank-width = <2>; + num-cs = <1>; +}; -- cgit v1.3.1 From b9efaf6729d06df94ded46710725746a41eaf0fc Mon Sep 17 00:00:00 2001 From: Nguyen Tran Date: Sat, 18 Oct 2025 00:09:09 +0200 Subject: ARM: dts: renesas: Disable RPC driver on R8A779H0 V4M Gray Hawk board As requirement of CR side, QSPI Flash usage via RPC driver shall be disabled and leaving the control of this module to CR side. Perform DT modification to disable the RPC SPI. Signed-off-by: Nguyen Tran Reviewed-by: Khanh Le Signed-off-by: Marek Vasut [Marek: Do not modify defconfig, modify the DT instead, this way the RPC SPI can be enabled without recompiling the U-Boot itself. Update commit message accordingly.] --- arch/arm/dts/r8a779h0-gray-hawk-single-u-boot.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/dts/r8a779h0-gray-hawk-single-u-boot.dtsi b/arch/arm/dts/r8a779h0-gray-hawk-single-u-boot.dtsi index 91e1ee1f890..c04d2ae2be4 100644 --- a/arch/arm/dts/r8a779h0-gray-hawk-single-u-boot.dtsi +++ b/arch/arm/dts/r8a779h0-gray-hawk-single-u-boot.dtsi @@ -27,7 +27,7 @@ #address-cells = <1>; #size-cells = <0>; spi-max-frequency = <40000000>; - status = "okay"; + status = "disabled"; flash@0 { #address-cells = <1>; -- cgit v1.3.1